Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.88 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T502 /workspace/coverage/default/24.rstmgr_por_stretcher.1830575049 Dec 27 12:47:30 PM PST 23 Dec 27 12:47:40 PM PST 23 85946580 ps
T503 /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.3253644036 Dec 27 12:48:00 PM PST 23 Dec 27 12:48:11 PM PST 23 99781053 ps
T504 /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.3560068033 Dec 27 12:48:08 PM PST 23 Dec 27 12:48:17 PM PST 23 108034762 ps
T505 /workspace/coverage/default/33.rstmgr_stress_all.3370947605 Dec 27 12:47:55 PM PST 23 Dec 27 12:48:25 PM PST 23 4603606854 ps
T506 /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.1443948267 Dec 27 12:47:35 PM PST 23 Dec 27 12:47:46 PM PST 23 101355008 ps
T507 /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.1901726412 Dec 27 12:47:35 PM PST 23 Dec 27 12:47:54 PM PST 23 2355014263 ps
T508 /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.4146721410 Dec 27 12:47:43 PM PST 23 Dec 27 12:47:54 PM PST 23 243994433 ps
T509 /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.3306951563 Dec 27 12:47:08 PM PST 23 Dec 27 12:47:21 PM PST 23 178582123 ps
T510 /workspace/coverage/default/25.rstmgr_por_stretcher.801342645 Dec 27 12:47:35 PM PST 23 Dec 27 12:47:45 PM PST 23 106365318 ps
T511 /workspace/coverage/default/42.rstmgr_alert_test.2540756740 Dec 27 12:48:03 PM PST 23 Dec 27 12:48:13 PM PST 23 76120171 ps
T512 /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.720581215 Dec 27 12:48:08 PM PST 23 Dec 27 12:48:23 PM PST 23 1888790926 ps
T513 /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.587434484 Dec 27 12:47:41 PM PST 23 Dec 27 12:47:59 PM PST 23 2169264510 ps
T514 /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.1360845177 Dec 27 12:47:49 PM PST 23 Dec 27 12:48:05 PM PST 23 1900050571 ps
T515 /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.1253180060 Dec 27 12:47:03 PM PST 23 Dec 27 12:47:19 PM PST 23 243113255 ps
T516 /workspace/coverage/default/3.rstmgr_por_stretcher.2914078171 Dec 27 12:46:58 PM PST 23 Dec 27 12:47:16 PM PST 23 150147350 ps
T517 /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.1017515281 Dec 27 12:47:24 PM PST 23 Dec 27 12:47:35 PM PST 23 246692365 ps
T518 /workspace/coverage/default/11.rstmgr_por_stretcher.2574612664 Dec 27 12:47:22 PM PST 23 Dec 27 12:47:34 PM PST 23 115564534 ps
T519 /workspace/coverage/default/5.rstmgr_sw_rst.3686886573 Dec 27 12:47:17 PM PST 23 Dec 27 12:47:30 PM PST 23 270028998 ps
T520 /workspace/coverage/default/43.rstmgr_reset.704938652 Dec 27 12:48:07 PM PST 23 Dec 27 12:48:23 PM PST 23 2344598225 ps
T521 /workspace/coverage/default/36.rstmgr_stress_all.4019563709 Dec 27 12:48:13 PM PST 23 Dec 27 12:48:28 PM PST 23 1384002027 ps
T522 /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.73935764 Dec 27 12:47:57 PM PST 23 Dec 27 12:48:15 PM PST 23 2365298055 ps
T523 /workspace/coverage/default/43.rstmgr_sw_rst.691303505 Dec 27 12:48:14 PM PST 23 Dec 27 12:48:23 PM PST 23 122572907 ps
T524 /workspace/coverage/default/38.rstmgr_smoke.559052034 Dec 27 12:48:09 PM PST 23 Dec 27 12:48:17 PM PST 23 120442864 ps
T525 /workspace/coverage/default/23.rstmgr_por_stretcher.784409174 Dec 27 12:47:30 PM PST 23 Dec 27 12:47:40 PM PST 23 127740040 ps
T526 /workspace/coverage/default/17.rstmgr_sw_rst.2717763035 Dec 27 12:47:31 PM PST 23 Dec 27 12:47:41 PM PST 23 140580022 ps
T527 /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.1861749393 Dec 27 12:47:17 PM PST 23 Dec 27 12:47:30 PM PST 23 244202566 ps
T528 /workspace/coverage/default/32.rstmgr_sw_rst.3588272915 Dec 27 12:47:49 PM PST 23 Dec 27 12:48:00 PM PST 23 362667434 ps
T529 /workspace/coverage/default/2.rstmgr_alert_test.862680284 Dec 27 12:46:59 PM PST 23 Dec 27 12:47:17 PM PST 23 57815906 ps
T530 /workspace/coverage/default/7.rstmgr_reset.381604619 Dec 27 12:47:21 PM PST 23 Dec 27 12:47:36 PM PST 23 851919531 ps
T531 /workspace/coverage/default/28.rstmgr_stress_all.965293141 Dec 27 12:47:39 PM PST 23 Dec 27 12:48:27 PM PST 23 10382062961 ps
T532 /workspace/coverage/default/28.rstmgr_smoke.864598777 Dec 27 12:47:42 PM PST 23 Dec 27 12:47:53 PM PST 23 118658747 ps
T533 /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.319105418 Dec 27 12:48:04 PM PST 23 Dec 27 12:48:14 PM PST 23 243915367 ps
T534 /workspace/coverage/default/35.rstmgr_por_stretcher.1558928053 Dec 27 12:47:56 PM PST 23 Dec 27 12:48:06 PM PST 23 130582193 ps
T535 /workspace/coverage/default/18.rstmgr_stress_all.1669339629 Dec 27 12:47:35 PM PST 23 Dec 27 12:48:08 PM PST 23 6813368019 ps
T536 /workspace/coverage/default/34.rstmgr_sw_rst.4106965464 Dec 27 12:47:55 PM PST 23 Dec 27 12:48:07 PM PST 23 143704861 ps
T537 /workspace/coverage/default/4.rstmgr_alert_test.1972301048 Dec 27 12:47:17 PM PST 23 Dec 27 12:47:29 PM PST 23 84038314 ps
T538 /workspace/coverage/default/23.rstmgr_reset.2476734741 Dec 27 12:47:34 PM PST 23 Dec 27 12:47:48 PM PST 23 760461029 ps
T539 /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.1687534209 Dec 27 12:46:58 PM PST 23 Dec 27 12:47:17 PM PST 23 244278448 ps
T540 /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.2762010541 Dec 27 12:47:33 PM PST 23 Dec 27 12:47:55 PM PST 23 1229406186 ps
T541 /workspace/coverage/default/28.rstmgr_alert_test.2942366294 Dec 27 12:47:37 PM PST 23 Dec 27 12:47:47 PM PST 23 65862843 ps
T542 /workspace/coverage/default/6.rstmgr_alert_test.801560771 Dec 27 12:47:17 PM PST 23 Dec 27 12:47:30 PM PST 23 89610537 ps
T543 /workspace/coverage/default/41.rstmgr_alert_test.3224232172 Dec 27 12:47:57 PM PST 23 Dec 27 12:48:09 PM PST 23 111455772 ps
T544 /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.491519022 Dec 27 12:48:10 PM PST 23 Dec 27 12:48:18 PM PST 23 130161019 ps
T545 /workspace/coverage/default/16.rstmgr_reset.1429433705 Dec 27 12:47:30 PM PST 23 Dec 27 12:47:45 PM PST 23 1764677630 ps
T546 /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.3257953836 Dec 27 12:46:54 PM PST 23 Dec 27 12:47:14 PM PST 23 184358553 ps
T547 /workspace/coverage/default/37.rstmgr_por_stretcher.1740624888 Dec 27 12:48:10 PM PST 23 Dec 27 12:48:18 PM PST 23 143832504 ps
T548 /workspace/coverage/default/47.rstmgr_stress_all.403111808 Dec 27 12:48:48 PM PST 23 Dec 27 12:49:15 PM PST 23 5013870270 ps
T549 /workspace/coverage/default/6.rstmgr_sw_rst.2540898475 Dec 27 12:47:03 PM PST 23 Dec 27 12:47:19 PM PST 23 263815655 ps
T550 /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.453202616 Dec 27 12:46:55 PM PST 23 Dec 27 12:47:14 PM PST 23 245165933 ps
T551 /workspace/coverage/default/0.rstmgr_alert_test.1062882437 Dec 27 12:46:56 PM PST 23 Dec 27 12:47:15 PM PST 23 72744738 ps
T552 /workspace/coverage/default/21.rstmgr_stress_all.3936065799 Dec 27 12:47:30 PM PST 23 Dec 27 12:47:55 PM PST 23 4294190339 ps
T553 /workspace/coverage/default/2.rstmgr_smoke.819244296 Dec 27 12:46:55 PM PST 23 Dec 27 12:47:15 PM PST 23 240331148 ps
T554 /workspace/coverage/default/4.rstmgr_sw_rst.2566477210 Dec 27 12:46:59 PM PST 23 Dec 27 12:47:19 PM PST 23 369608589 ps
T555 /workspace/coverage/default/45.rstmgr_sw_rst.1364871077 Dec 27 12:48:07 PM PST 23 Dec 27 12:48:17 PM PST 23 344905469 ps
T556 /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.568362867 Dec 27 12:47:29 PM PST 23 Dec 27 12:47:46 PM PST 23 2352758428 ps
T557 /workspace/coverage/default/38.rstmgr_reset.535873168 Dec 27 12:47:55 PM PST 23 Dec 27 12:48:10 PM PST 23 997535699 ps
T558 /workspace/coverage/default/5.rstmgr_alert_test.1677937614 Dec 27 12:47:11 PM PST 23 Dec 27 12:47:22 PM PST 23 71749378 ps
T559 /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.563900330 Dec 27 12:47:26 PM PST 23 Dec 27 12:47:44 PM PST 23 2375099634 ps
T560 /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.3165640608 Dec 27 12:47:40 PM PST 23 Dec 27 12:47:52 PM PST 23 243859439 ps
T561 /workspace/coverage/default/5.rstmgr_por_stretcher.731755296 Dec 27 12:47:11 PM PST 23 Dec 27 12:47:22 PM PST 23 186706899 ps
T562 /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.749823853 Dec 27 12:47:17 PM PST 23 Dec 27 12:47:35 PM PST 23 1887459951 ps
T563 /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.2872713652 Dec 27 12:47:30 PM PST 23 Dec 27 12:47:40 PM PST 23 244662562 ps
T564 /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.169480815 Dec 27 12:46:59 PM PST 23 Dec 27 12:47:17 PM PST 23 153451541 ps
T565 /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.1162759287 Dec 27 12:47:40 PM PST 23 Dec 27 12:47:57 PM PST 23 1898055283 ps
T566 /workspace/coverage/default/38.rstmgr_stress_all.4117811922 Dec 27 12:47:51 PM PST 23 Dec 27 12:48:19 PM PST 23 4942896351 ps
T567 /workspace/coverage/default/25.rstmgr_sw_rst.1506055871 Dec 27 12:47:42 PM PST 23 Dec 27 12:47:54 PM PST 23 474042542 ps
T568 /workspace/coverage/default/15.rstmgr_reset.2655063670 Dec 27 12:47:25 PM PST 23 Dec 27 12:47:39 PM PST 23 938170384 ps
T86 /workspace/coverage/default/2.rstmgr_sec_cm.59948533 Dec 27 12:47:00 PM PST 23 Dec 27 12:47:29 PM PST 23 8440980777 ps
T569 /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.954403977 Dec 27 12:48:04 PM PST 23 Dec 27 12:48:14 PM PST 23 244362724 ps
T570 /workspace/coverage/default/41.rstmgr_reset.2102386205 Dec 27 12:47:56 PM PST 23 Dec 27 12:48:10 PM PST 23 842167320 ps
T571 /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.1808255973 Dec 27 12:47:57 PM PST 23 Dec 27 12:48:09 PM PST 23 162566911 ps
T572 /workspace/coverage/default/8.rstmgr_stress_all.3857070856 Dec 27 12:47:19 PM PST 23 Dec 27 12:47:31 PM PST 23 159573203 ps
T573 /workspace/coverage/default/44.rstmgr_sw_rst.461744728 Dec 27 12:48:10 PM PST 23 Dec 27 12:48:18 PM PST 23 129159792 ps
T574 /workspace/coverage/default/31.rstmgr_alert_test.1875556726 Dec 27 12:47:43 PM PST 23 Dec 27 12:47:54 PM PST 23 86414726 ps
T575 /workspace/coverage/default/34.rstmgr_reset.3861897565 Dec 27 12:47:56 PM PST 23 Dec 27 12:48:14 PM PST 23 2189130437 ps
T576 /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.1296223549 Dec 27 12:47:52 PM PST 23 Dec 27 12:48:04 PM PST 23 244780148 ps
T577 /workspace/coverage/default/8.rstmgr_sw_rst.2675995389 Dec 27 12:47:10 PM PST 23 Dec 27 12:47:23 PM PST 23 345530610 ps
T578 /workspace/coverage/default/47.rstmgr_alert_test.1896601187 Dec 27 12:48:43 PM PST 23 Dec 27 12:48:46 PM PST 23 63790629 ps
T579 /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.2587439721 Dec 27 12:47:47 PM PST 23 Dec 27 12:47:58 PM PST 23 205486057 ps
T580 /workspace/coverage/default/8.rstmgr_por_stretcher.2450414276 Dec 27 12:47:10 PM PST 23 Dec 27 12:47:21 PM PST 23 93023066 ps
T581 /workspace/coverage/default/15.rstmgr_stress_all.2319136276 Dec 27 12:47:34 PM PST 23 Dec 27 12:47:45 PM PST 23 126233884 ps
T582 /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.3913278960 Dec 27 12:48:24 PM PST 23 Dec 27 12:48:37 PM PST 23 1892508559 ps
T583 /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.2383448582 Dec 27 12:47:42 PM PST 23 Dec 27 12:47:57 PM PST 23 1225841597 ps
T584 /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.1622092738 Dec 27 12:46:58 PM PST 23 Dec 27 12:47:21 PM PST 23 1228906737 ps
T585 /workspace/coverage/default/39.rstmgr_alert_test.3770861711 Dec 27 12:47:57 PM PST 23 Dec 27 12:48:08 PM PST 23 89772095 ps
T586 /workspace/coverage/default/48.rstmgr_reset.3508063685 Dec 27 12:48:31 PM PST 23 Dec 27 12:48:40 PM PST 23 967783341 ps
T587 /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.3297190325 Dec 27 12:47:22 PM PST 23 Dec 27 12:47:34 PM PST 23 112538999 ps
T588 /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.527795184 Dec 27 12:48:26 PM PST 23 Dec 27 12:48:31 PM PST 23 113280445 ps
T589 /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.2733424646 Dec 27 12:46:55 PM PST 23 Dec 27 12:47:15 PM PST 23 244828167 ps
T590 /workspace/coverage/default/29.rstmgr_stress_all.3781443552 Dec 27 12:47:41 PM PST 23 Dec 27 12:48:26 PM PST 23 7287638460 ps
T591 /workspace/coverage/default/32.rstmgr_por_stretcher.3110382826 Dec 27 12:47:42 PM PST 23 Dec 27 12:47:53 PM PST 23 129984759 ps
T592 /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.1241206616 Dec 27 12:47:33 PM PST 23 Dec 27 12:47:50 PM PST 23 245617167 ps
T593 /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.2796823562 Dec 27 12:48:20 PM PST 23 Dec 27 12:48:32 PM PST 23 1223417798 ps
T594 /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.1581166391 Dec 27 12:47:41 PM PST 23 Dec 27 12:47:52 PM PST 23 109039624 ps
T595 /workspace/coverage/default/27.rstmgr_reset.2987081613 Dec 27 12:47:42 PM PST 23 Dec 27 12:47:58 PM PST 23 1576008143 ps
T596 /workspace/coverage/default/49.rstmgr_reset.944325819 Dec 27 12:48:12 PM PST 23 Dec 27 12:48:27 PM PST 23 1983872334 ps
T597 /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.3427682682 Dec 27 12:47:49 PM PST 23 Dec 27 12:48:05 PM PST 23 1867084507 ps
T598 /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.2407916255 Dec 27 12:46:56 PM PST 23 Dec 27 12:47:22 PM PST 23 2393457265 ps
T599 /workspace/coverage/default/21.rstmgr_smoke.2313738773 Dec 27 12:47:58 PM PST 23 Dec 27 12:48:10 PM PST 23 190619129 ps
T600 /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.1099052400 Dec 27 12:48:11 PM PST 23 Dec 27 12:48:19 PM PST 23 244277701 ps
T601 /workspace/coverage/default/21.rstmgr_sw_rst.511542244 Dec 27 12:47:48 PM PST 23 Dec 27 12:47:59 PM PST 23 295316010 ps
T602 /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.2898725277 Dec 27 12:48:04 PM PST 23 Dec 27 12:48:14 PM PST 23 195244610 ps
T603 /workspace/coverage/default/10.rstmgr_alert_test.4066324823 Dec 27 12:47:24 PM PST 23 Dec 27 12:47:35 PM PST 23 87064456 ps
T604 /workspace/coverage/default/18.rstmgr_reset.1013674680 Dec 27 12:47:40 PM PST 23 Dec 27 12:47:55 PM PST 23 1012954998 ps
T605 /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.1439161054 Dec 27 12:48:06 PM PST 23 Dec 27 12:48:15 PM PST 23 99781723 ps
T606 /workspace/coverage/default/33.rstmgr_alert_test.3728177788 Dec 27 12:47:57 PM PST 23 Dec 27 12:48:08 PM PST 23 68940624 ps
T607 /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.602657784 Dec 27 12:48:24 PM PST 23 Dec 27 12:48:31 PM PST 23 144706230 ps
T608 /workspace/coverage/default/20.rstmgr_stress_all.3404141143 Dec 27 12:47:57 PM PST 23 Dec 27 12:48:24 PM PST 23 3942762624 ps
T609 /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.3809164402 Dec 27 12:46:56 PM PST 23 Dec 27 12:47:15 PM PST 23 143904534 ps
T610 /workspace/coverage/default/2.rstmgr_reset.3785843241 Dec 27 12:46:52 PM PST 23 Dec 27 12:47:19 PM PST 23 1722128734 ps
T611 /workspace/coverage/default/8.rstmgr_reset.2383897373 Dec 27 12:47:11 PM PST 23 Dec 27 12:47:26 PM PST 23 1016548267 ps
T612 /workspace/coverage/default/17.rstmgr_alert_test.1117370560 Dec 27 12:47:33 PM PST 23 Dec 27 12:47:43 PM PST 23 72938127 ps
T613 /workspace/coverage/default/33.rstmgr_reset.2396854275 Dec 27 12:47:43 PM PST 23 Dec 27 12:47:58 PM PST 23 1187074389 ps
T614 /workspace/coverage/default/44.rstmgr_stress_all.2929431192 Dec 27 12:48:07 PM PST 23 Dec 27 12:48:18 PM PST 23 687872818 ps
T615 /workspace/coverage/default/36.rstmgr_sw_rst.1511135273 Dec 27 12:47:55 PM PST 23 Dec 27 12:48:07 PM PST 23 375488257 ps
T616 /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.169853410 Dec 27 12:48:06 PM PST 23 Dec 27 12:48:15 PM PST 23 97784409 ps
T617 /workspace/coverage/default/39.rstmgr_stress_all.2522570603 Dec 27 12:48:09 PM PST 23 Dec 27 12:48:38 PM PST 23 5460374946 ps
T618 /workspace/coverage/default/37.rstmgr_stress_all.3699525859 Dec 27 12:47:56 PM PST 23 Dec 27 12:48:37 PM PST 23 10010536029 ps
T619 /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.3843387750 Dec 27 12:47:17 PM PST 23 Dec 27 12:47:30 PM PST 23 243912124 ps
T620 /workspace/coverage/default/1.rstmgr_sw_rst.4103267200 Dec 27 12:46:54 PM PST 23 Dec 27 12:47:15 PM PST 23 260914415 ps

Test location /workspace/coverage/default/0.rstmgr_reset.2870898851
Short name T2
Test name
Test status
Simulation time 885671426 ps
CPU time 4.67 seconds
Started Dec 27 12:46:50 PM PST 23
Finished Dec 27 12:47:16 PM PST 23
Peak memory 199468 kb
Host smart-170178fb-7f66-43f4-869b-090548309366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870898851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.2870898851
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.2453991052
Short name T50
Test name
Test status
Simulation time 383661222 ps
CPU time 2.07 seconds
Started Dec 27 12:47:30 PM PST 23
Finished Dec 27 12:47:41 PM PST 23
Peak memory 199260 kb
Host smart-5edda3ec-5e65-4bdd-a470-a9a402e495ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453991052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.2453991052
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.4099886935
Short name T52
Test name
Test status
Simulation time 4481487157 ps
CPU time 14.75 seconds
Started Dec 27 12:48:14 PM PST 23
Finished Dec 27 12:48:36 PM PST 23
Peak memory 199588 kb
Host smart-512dc1df-a7a0-47fc-b255-066069fd148c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099886935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.4099886935
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1212837700
Short name T84
Test name
Test status
Simulation time 938251190 ps
CPU time 3.25 seconds
Started Dec 27 12:36:07 PM PST 23
Finished Dec 27 12:36:31 PM PST 23
Peak memory 199492 kb
Host smart-61fea936-8e35-44e2-983a-75ca46c54ba3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212837700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.1212837700
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.575755295
Short name T61
Test name
Test status
Simulation time 18245923851 ps
CPU time 26.5 seconds
Started Dec 27 12:46:59 PM PST 23
Finished Dec 27 12:47:42 PM PST 23
Peak memory 217376 kb
Host smart-d09b2d17-d5fb-402a-a83e-c59fb0dc9ba6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575755295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.575755295
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.2341757077
Short name T21
Test name
Test status
Simulation time 2339921342 ps
CPU time 8.7 seconds
Started Dec 27 12:48:18 PM PST 23
Finished Dec 27 12:48:34 PM PST 23
Peak memory 216536 kb
Host smart-e5f91e5a-e591-4c0f-95a0-890ec8b07741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341757077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.2341757077
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.2738782653
Short name T78
Test name
Test status
Simulation time 521741033 ps
CPU time 3 seconds
Started Dec 27 12:36:02 PM PST 23
Finished Dec 27 12:36:23 PM PST 23
Peak memory 199440 kb
Host smart-02b5f39c-6380-4a85-8885-998e457d6e63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738782653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.2738782653
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.1413065342
Short name T94
Test name
Test status
Simulation time 109980976 ps
CPU time 1.05 seconds
Started Dec 27 12:48:19 PM PST 23
Finished Dec 27 12:48:27 PM PST 23
Peak memory 199312 kb
Host smart-20b83cc8-533b-42b3-96b6-e8fd95de5503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413065342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.1413065342
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.2134523643
Short name T36
Test name
Test status
Simulation time 72162191 ps
CPU time 0.74 seconds
Started Dec 27 12:46:54 PM PST 23
Finished Dec 27 12:47:13 PM PST 23
Peak memory 199076 kb
Host smart-e57781da-f79e-4971-9742-c26be9fc8990
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134523643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.2134523643
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.2529273356
Short name T65
Test name
Test status
Simulation time 2168667355 ps
CPU time 7.42 seconds
Started Dec 27 12:47:34 PM PST 23
Finished Dec 27 12:47:51 PM PST 23
Peak memory 216748 kb
Host smart-a9119f12-bd78-4392-916d-55a741e5b218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529273356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.2529273356
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.1063085665
Short name T144
Test name
Test status
Simulation time 84905544 ps
CPU time 0.88 seconds
Started Dec 27 12:47:22 PM PST 23
Finished Dec 27 12:47:34 PM PST 23
Peak memory 199236 kb
Host smart-2bf5d2cf-6fbe-40bf-a17a-b7316e52a491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063085665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.1063085665
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3748104852
Short name T135
Test name
Test status
Simulation time 782782496 ps
CPU time 2.67 seconds
Started Dec 27 12:35:35 PM PST 23
Finished Dec 27 12:35:50 PM PST 23
Peak memory 199528 kb
Host smart-bde1679d-c961-4f13-bb70-12eeb9172994
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748104852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.3748104852
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.2172342115
Short name T139
Test name
Test status
Simulation time 902543585 ps
CPU time 2.9 seconds
Started Dec 27 12:35:51 PM PST 23
Finished Dec 27 12:36:14 PM PST 23
Peak memory 199476 kb
Host smart-69cf4dc4-22e9-4590-a889-3e5e8603ad9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172342115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.2172342115
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.4184659948
Short name T117
Test name
Test status
Simulation time 4697529416 ps
CPU time 19.82 seconds
Started Dec 27 12:47:08 PM PST 23
Finished Dec 27 12:47:39 PM PST 23
Peak memory 199512 kb
Host smart-6b8d5a7c-68d1-4ed8-afb7-95dfbfcbafbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184659948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.4184659948
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.647715004
Short name T26
Test name
Test status
Simulation time 2352931638 ps
CPU time 8.3 seconds
Started Dec 27 12:46:55 PM PST 23
Finished Dec 27 12:47:22 PM PST 23
Peak memory 217292 kb
Host smart-7863786a-5233-4479-9de7-52595854d2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647715004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.647715004
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.59903268
Short name T121
Test name
Test status
Simulation time 78489894 ps
CPU time 0.78 seconds
Started Dec 27 12:37:14 PM PST 23
Finished Dec 27 12:37:36 PM PST 23
Peak memory 199312 kb
Host smart-e683b89a-5415-4d59-8bd4-a3fb1d538fd2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59903268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.59903268
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.3661678969
Short name T11
Test name
Test status
Simulation time 148536825 ps
CPU time 0.86 seconds
Started Dec 27 12:46:56 PM PST 23
Finished Dec 27 12:47:15 PM PST 23
Peak memory 199028 kb
Host smart-7da456ea-6109-437e-a74c-f7eadd49b504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661678969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.3661678969
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.647737275
Short name T235
Test name
Test status
Simulation time 219652621 ps
CPU time 1.51 seconds
Started Dec 27 12:35:56 PM PST 23
Finished Dec 27 12:36:16 PM PST 23
Peak memory 199428 kb
Host smart-971e3fd0-0c16-463e-8840-5760dbaa02ce
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647737275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.647737275
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3299091269
Short name T124
Test name
Test status
Simulation time 1191501741 ps
CPU time 5.26 seconds
Started Dec 27 12:36:46 PM PST 23
Finished Dec 27 12:37:20 PM PST 23
Peak memory 199600 kb
Host smart-ec47f9c9-00d6-4888-8df7-5848ff5d6bec
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299091269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.3
299091269
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.2351211307
Short name T76
Test name
Test status
Simulation time 93358472 ps
CPU time 0.76 seconds
Started Dec 27 12:35:48 PM PST 23
Finished Dec 27 12:36:08 PM PST 23
Peak memory 199340 kb
Host smart-0cfccedf-a086-4337-b153-475de5a9f34d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351211307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.2
351211307
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2948558208
Short name T206
Test name
Test status
Simulation time 145739799 ps
CPU time 1 seconds
Started Dec 27 12:35:55 PM PST 23
Finished Dec 27 12:36:14 PM PST 23
Peak memory 199556 kb
Host smart-3f711d20-9051-4318-8bb8-27965ccc351e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948558208 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.2948558208
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.1645144792
Short name T201
Test name
Test status
Simulation time 69816193 ps
CPU time 0.77 seconds
Started Dec 27 12:35:41 PM PST 23
Finished Dec 27 12:35:57 PM PST 23
Peak memory 199340 kb
Host smart-118e77df-af53-429c-ad1f-8b03a9889318
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645144792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.1645144792
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3046255340
Short name T213
Test name
Test status
Simulation time 237149184 ps
CPU time 1.4 seconds
Started Dec 27 12:35:39 PM PST 23
Finished Dec 27 12:35:54 PM PST 23
Peak memory 199624 kb
Host smart-73afc92d-ee05-4329-9626-8a48721a6ba8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046255340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.3046255340
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2892987625
Short name T104
Test name
Test status
Simulation time 104194798 ps
CPU time 1.4 seconds
Started Dec 27 12:36:22 PM PST 23
Finished Dec 27 12:36:45 PM PST 23
Peak memory 199528 kb
Host smart-c74e916c-79d5-4e4e-b529-ee88bcec4775
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892987625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.2892987625
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2887524681
Short name T242
Test name
Test status
Simulation time 415161092 ps
CPU time 1.61 seconds
Started Dec 27 12:36:24 PM PST 23
Finished Dec 27 12:36:47 PM PST 23
Peak memory 199628 kb
Host smart-2058ed61-2e59-4d14-af7d-8654cb77205c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887524681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.2887524681
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.1382989263
Short name T241
Test name
Test status
Simulation time 347454368 ps
CPU time 2.27 seconds
Started Dec 27 12:35:30 PM PST 23
Finished Dec 27 12:35:46 PM PST 23
Peak memory 199580 kb
Host smart-88744c86-8083-4095-acc1-102c1f4a7eaf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382989263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.1
382989263
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.203301145
Short name T177
Test name
Test status
Simulation time 798402627 ps
CPU time 4.07 seconds
Started Dec 27 12:35:59 PM PST 23
Finished Dec 27 12:36:21 PM PST 23
Peak memory 199472 kb
Host smart-65e2dc34-efb9-4e8b-adce-9ac33efe2bfb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203301145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.203301145
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.765258266
Short name T216
Test name
Test status
Simulation time 91450173 ps
CPU time 0.76 seconds
Started Dec 27 12:35:51 PM PST 23
Finished Dec 27 12:36:12 PM PST 23
Peak memory 199408 kb
Host smart-4e964c55-2b6e-434c-9308-f25e6a280edc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765258266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.765258266
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3780454678
Short name T238
Test name
Test status
Simulation time 153245089 ps
CPU time 1.32 seconds
Started Dec 27 12:35:33 PM PST 23
Finished Dec 27 12:35:47 PM PST 23
Peak memory 199560 kb
Host smart-9f9d63c8-050e-4522-80bc-122acab8db56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780454678 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.3780454678
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.156955929
Short name T226
Test name
Test status
Simulation time 56238484 ps
CPU time 0.74 seconds
Started Dec 27 12:35:55 PM PST 23
Finished Dec 27 12:36:14 PM PST 23
Peak memory 199388 kb
Host smart-19856cb1-3cd4-44f2-bb15-d4e3de58e34b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156955929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.156955929
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.166455034
Short name T194
Test name
Test status
Simulation time 127441674 ps
CPU time 1.21 seconds
Started Dec 27 12:35:53 PM PST 23
Finished Dec 27 12:36:13 PM PST 23
Peak memory 199608 kb
Host smart-78081588-ed52-44c2-8edb-f1745c9e18c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166455034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sam
e_csr_outstanding.166455034
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.3832964045
Short name T138
Test name
Test status
Simulation time 304245885 ps
CPU time 2.32 seconds
Started Dec 27 12:36:10 PM PST 23
Finished Dec 27 12:36:33 PM PST 23
Peak memory 199528 kb
Host smart-1f505f5b-6661-4b7e-bb30-97db5c6b8e2f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832964045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.3832964045
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.4083647208
Short name T83
Test name
Test status
Simulation time 470406338 ps
CPU time 1.89 seconds
Started Dec 27 12:35:40 PM PST 23
Finished Dec 27 12:35:57 PM PST 23
Peak memory 199496 kb
Host smart-a0543917-ac6a-41db-ba21-96327278b0f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083647208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.4083647208
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.2636856015
Short name T239
Test name
Test status
Simulation time 145153783 ps
CPU time 1.23 seconds
Started Dec 27 12:36:00 PM PST 23
Finished Dec 27 12:36:20 PM PST 23
Peak memory 199412 kb
Host smart-83000616-da78-47db-9981-ce77da8efb6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636856015 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.2636856015
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1421415257
Short name T203
Test name
Test status
Simulation time 125241574 ps
CPU time 1.19 seconds
Started Dec 27 12:35:51 PM PST 23
Finished Dec 27 12:36:12 PM PST 23
Peak memory 199520 kb
Host smart-ed415990-8224-4acd-bb2f-5711dcaafbbc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421415257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.1421415257
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3264407554
Short name T106
Test name
Test status
Simulation time 107664178 ps
CPU time 1.42 seconds
Started Dec 27 12:36:30 PM PST 23
Finished Dec 27 12:36:58 PM PST 23
Peak memory 199488 kb
Host smart-8c9e93a4-46cc-4406-bceb-99f0a9f50ea3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264407554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.3264407554
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.612663006
Short name T140
Test name
Test status
Simulation time 788656185 ps
CPU time 2.78 seconds
Started Dec 27 12:36:31 PM PST 23
Finished Dec 27 12:36:59 PM PST 23
Peak memory 199272 kb
Host smart-71e4c260-7c67-4032-b40e-5103cb397032
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612663006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_err
.612663006
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.647219483
Short name T189
Test name
Test status
Simulation time 158154650 ps
CPU time 1.41 seconds
Started Dec 27 12:35:42 PM PST 23
Finished Dec 27 12:36:01 PM PST 23
Peak memory 207996 kb
Host smart-539b4a56-a4f4-45db-8b5e-a9b5ecdc3af7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647219483 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.647219483
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.3538650516
Short name T186
Test name
Test status
Simulation time 79480777 ps
CPU time 0.83 seconds
Started Dec 27 12:35:53 PM PST 23
Finished Dec 27 12:36:13 PM PST 23
Peak memory 199484 kb
Host smart-6850178d-459d-42dd-bcf1-93fefa65f7c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538650516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.3538650516
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.4226617494
Short name T134
Test name
Test status
Simulation time 131692014 ps
CPU time 1.17 seconds
Started Dec 27 12:35:34 PM PST 23
Finished Dec 27 12:35:47 PM PST 23
Peak memory 199572 kb
Host smart-b7cd4104-371c-47c5-97ec-2e0b76fdf0ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226617494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.4226617494
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.1145795330
Short name T196
Test name
Test status
Simulation time 273570576 ps
CPU time 2.05 seconds
Started Dec 27 12:35:54 PM PST 23
Finished Dec 27 12:36:15 PM PST 23
Peak memory 199456 kb
Host smart-25d22956-0cd8-49c6-b087-63e7bae35422
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145795330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.1145795330
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.2262133875
Short name T112
Test name
Test status
Simulation time 494831671 ps
CPU time 1.93 seconds
Started Dec 27 12:35:52 PM PST 23
Finished Dec 27 12:36:14 PM PST 23
Peak memory 199520 kb
Host smart-9f23f372-8ba6-4583-9f9e-650c6528c94b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262133875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.2262133875
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2113542848
Short name T181
Test name
Test status
Simulation time 129327326 ps
CPU time 1.03 seconds
Started Dec 27 12:36:04 PM PST 23
Finished Dec 27 12:36:23 PM PST 23
Peak memory 199632 kb
Host smart-0acda6e1-a916-4d52-8f33-43d8a0321942
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113542848 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.2113542848
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.2252945930
Short name T223
Test name
Test status
Simulation time 71024712 ps
CPU time 0.74 seconds
Started Dec 27 12:36:14 PM PST 23
Finished Dec 27 12:36:35 PM PST 23
Peak memory 199352 kb
Host smart-841e174b-1fef-40a9-bb47-ff41a240e2bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252945930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.2252945930
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.488026635
Short name T107
Test name
Test status
Simulation time 130791522 ps
CPU time 1.01 seconds
Started Dec 27 12:35:51 PM PST 23
Finished Dec 27 12:36:12 PM PST 23
Peak memory 199476 kb
Host smart-e6883b0a-c346-448a-b46e-69ef6ab56e2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488026635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_sa
me_csr_outstanding.488026635
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.440142045
Short name T105
Test name
Test status
Simulation time 319152804 ps
CPU time 2.2 seconds
Started Dec 27 12:36:33 PM PST 23
Finished Dec 27 12:37:02 PM PST 23
Peak memory 199552 kb
Host smart-1ea09885-d0b7-4d09-babf-44adab4916f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440142045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.440142045
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.2936345635
Short name T136
Test name
Test status
Simulation time 802248136 ps
CPU time 2.67 seconds
Started Dec 27 12:36:12 PM PST 23
Finished Dec 27 12:36:35 PM PST 23
Peak memory 199640 kb
Host smart-c5d7062b-bb23-478c-b211-7b8e3eefa987
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936345635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.2936345635
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.1013769805
Short name T249
Test name
Test status
Simulation time 171526900 ps
CPU time 1.17 seconds
Started Dec 27 12:35:40 PM PST 23
Finished Dec 27 12:35:56 PM PST 23
Peak memory 199500 kb
Host smart-f4bde586-ab27-4012-8dac-87e90cb3b27f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013769805 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.1013769805
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.2348499554
Short name T131
Test name
Test status
Simulation time 66193876 ps
CPU time 0.75 seconds
Started Dec 27 12:36:19 PM PST 23
Finished Dec 27 12:36:40 PM PST 23
Peak memory 199508 kb
Host smart-689249a6-c44f-453a-98b9-d62ca017142a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348499554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.2348499554
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.59968816
Short name T133
Test name
Test status
Simulation time 236067678 ps
CPU time 1.46 seconds
Started Dec 27 12:37:23 PM PST 23
Finished Dec 27 12:37:43 PM PST 23
Peak memory 199524 kb
Host smart-6a066f31-c530-4aac-a1c3-5155db949b6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59968816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_sam
e_csr_outstanding.59968816
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.2060604930
Short name T187
Test name
Test status
Simulation time 225737618 ps
CPU time 3.02 seconds
Started Dec 27 12:36:08 PM PST 23
Finished Dec 27 12:36:32 PM PST 23
Peak memory 199532 kb
Host smart-48192c70-445f-4240-9110-84a68a71b30c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060604930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.2060604930
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3160185817
Short name T141
Test name
Test status
Simulation time 764879288 ps
CPU time 2.82 seconds
Started Dec 27 12:36:04 PM PST 23
Finished Dec 27 12:36:25 PM PST 23
Peak memory 199500 kb
Host smart-f2f5a7cc-8f1d-4531-abb7-c6b61d733626
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160185817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.3160185817
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.1728754617
Short name T197
Test name
Test status
Simulation time 91034934 ps
CPU time 0.81 seconds
Started Dec 27 12:36:23 PM PST 23
Finished Dec 27 12:36:45 PM PST 23
Peak memory 199464 kb
Host smart-b5f8851f-9e7e-4d50-95c3-4e5e81640474
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728754617 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.1728754617
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.1326365876
Short name T221
Test name
Test status
Simulation time 81701198 ps
CPU time 0.83 seconds
Started Dec 27 12:35:54 PM PST 23
Finished Dec 27 12:36:14 PM PST 23
Peak memory 199388 kb
Host smart-2a86a74b-0325-4abc-9881-215318bffa1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326365876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.1326365876
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3853825817
Short name T191
Test name
Test status
Simulation time 290498468 ps
CPU time 1.59 seconds
Started Dec 27 12:35:31 PM PST 23
Finished Dec 27 12:35:46 PM PST 23
Peak memory 199640 kb
Host smart-52d69e0f-cb43-49a5-9c4a-0df1f051d978
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853825817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.3853825817
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.958870511
Short name T240
Test name
Test status
Simulation time 189332197 ps
CPU time 2.54 seconds
Started Dec 27 12:35:44 PM PST 23
Finished Dec 27 12:36:05 PM PST 23
Peak memory 199512 kb
Host smart-1dba3516-6748-48e0-a5b8-58f1ea2ac037
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958870511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.958870511
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.92156963
Short name T148
Test name
Test status
Simulation time 805571882 ps
CPU time 2.76 seconds
Started Dec 27 12:36:04 PM PST 23
Finished Dec 27 12:36:25 PM PST 23
Peak memory 199560 kb
Host smart-be2cfa8f-9fad-4688-8e28-d24854c91740
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92156963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_err.92156963
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.1052187387
Short name T183
Test name
Test status
Simulation time 130696687 ps
CPU time 1.02 seconds
Started Dec 27 12:36:02 PM PST 23
Finished Dec 27 12:36:21 PM PST 23
Peak memory 199500 kb
Host smart-01d533bd-239b-4fc4-80d9-907da8921201
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052187387 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.1052187387
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3609243539
Short name T75
Test name
Test status
Simulation time 76207358 ps
CPU time 0.74 seconds
Started Dec 27 12:35:53 PM PST 23
Finished Dec 27 12:36:13 PM PST 23
Peak memory 199264 kb
Host smart-1c5940a2-8ccf-408c-9b1b-3fc47ed962ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609243539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.3609243539
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2611962037
Short name T227
Test name
Test status
Simulation time 148405901 ps
CPU time 1.19 seconds
Started Dec 27 12:35:37 PM PST 23
Finished Dec 27 12:35:51 PM PST 23
Peak memory 199412 kb
Host smart-319c5ad0-9fcd-4697-98cb-2d1cedd13678
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611962037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.2611962037
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1706346846
Short name T234
Test name
Test status
Simulation time 433324268 ps
CPU time 1.66 seconds
Started Dec 27 12:36:08 PM PST 23
Finished Dec 27 12:36:31 PM PST 23
Peak memory 199492 kb
Host smart-20d2a3ec-4545-4247-b34a-1fc87c552765
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706346846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.1706346846
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3327832510
Short name T142
Test name
Test status
Simulation time 175791614 ps
CPU time 1.18 seconds
Started Dec 27 12:36:07 PM PST 23
Finished Dec 27 12:36:29 PM PST 23
Peak memory 199508 kb
Host smart-d204a623-ec87-4159-9f91-976b969a170e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327832510 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.3327832510
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2209309902
Short name T132
Test name
Test status
Simulation time 64036576 ps
CPU time 0.73 seconds
Started Dec 27 12:36:12 PM PST 23
Finished Dec 27 12:36:33 PM PST 23
Peak memory 199464 kb
Host smart-8b4070eb-ff26-443f-82ca-867877787138
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209309902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.2209309902
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1028215617
Short name T210
Test name
Test status
Simulation time 96275228 ps
CPU time 1.11 seconds
Started Dec 27 12:36:08 PM PST 23
Finished Dec 27 12:36:30 PM PST 23
Peak memory 199516 kb
Host smart-5a0915a0-c069-478f-86ec-db8410a3451e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028215617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.1028215617
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.1007205067
Short name T243
Test name
Test status
Simulation time 87911405 ps
CPU time 1.21 seconds
Started Dec 27 12:36:12 PM PST 23
Finished Dec 27 12:36:34 PM PST 23
Peak memory 199460 kb
Host smart-70bf9620-26f2-4ac5-8bee-fdf6f9071ebb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007205067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.1007205067
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3224543411
Short name T178
Test name
Test status
Simulation time 159990175 ps
CPU time 1.09 seconds
Started Dec 27 12:36:21 PM PST 23
Finished Dec 27 12:36:44 PM PST 23
Peak memory 199548 kb
Host smart-83fb3bd7-b203-4951-ba77-9a108ff1b710
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224543411 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.3224543411
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.1432620356
Short name T122
Test name
Test status
Simulation time 57408005 ps
CPU time 0.74 seconds
Started Dec 27 12:35:57 PM PST 23
Finished Dec 27 12:36:21 PM PST 23
Peak memory 199504 kb
Host smart-6772946c-6e4c-4a3d-a30f-03a7f89b01a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432620356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.1432620356
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1699896608
Short name T214
Test name
Test status
Simulation time 153077938 ps
CPU time 1.14 seconds
Started Dec 27 12:36:23 PM PST 23
Finished Dec 27 12:36:45 PM PST 23
Peak memory 199444 kb
Host smart-59d9aec5-2754-4f30-a40e-6aa91df0cacc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699896608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.1699896608
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.3818632897
Short name T229
Test name
Test status
Simulation time 135742781 ps
CPU time 1.86 seconds
Started Dec 27 12:36:06 PM PST 23
Finished Dec 27 12:36:27 PM PST 23
Peak memory 199548 kb
Host smart-5e7a51ca-ba82-41ad-b468-dfed6a238506
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818632897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.3818632897
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3962186733
Short name T220
Test name
Test status
Simulation time 420831485 ps
CPU time 1.74 seconds
Started Dec 27 12:35:48 PM PST 23
Finished Dec 27 12:36:09 PM PST 23
Peak memory 199648 kb
Host smart-faa87734-8a25-4fd0-ae63-1453d61a3075
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962186733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.3962186733
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.237487373
Short name T108
Test name
Test status
Simulation time 103328272 ps
CPU time 0.89 seconds
Started Dec 27 12:36:00 PM PST 23
Finished Dec 27 12:36:19 PM PST 23
Peak memory 199496 kb
Host smart-2df5708d-ef1f-4534-98c5-8962a244e7c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237487373 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.237487373
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.2429832286
Short name T130
Test name
Test status
Simulation time 62981338 ps
CPU time 0.7 seconds
Started Dec 27 12:36:16 PM PST 23
Finished Dec 27 12:36:38 PM PST 23
Peak memory 199360 kb
Host smart-618c259e-1e82-4d75-bd46-b1f529b105d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429832286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.2429832286
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2378103187
Short name T208
Test name
Test status
Simulation time 71323471 ps
CPU time 0.85 seconds
Started Dec 27 12:36:20 PM PST 23
Finished Dec 27 12:36:42 PM PST 23
Peak memory 199332 kb
Host smart-61b79761-68a3-496a-9a30-11c20e7bc6b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378103187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.2378103187
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.857005824
Short name T237
Test name
Test status
Simulation time 198191117 ps
CPU time 2.73 seconds
Started Dec 27 12:36:07 PM PST 23
Finished Dec 27 12:36:30 PM PST 23
Peak memory 199468 kb
Host smart-732ff432-4310-4871-86ca-dbc4f6b2a5ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857005824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.857005824
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1113397963
Short name T103
Test name
Test status
Simulation time 966539405 ps
CPU time 2.95 seconds
Started Dec 27 12:36:31 PM PST 23
Finished Dec 27 12:37:00 PM PST 23
Peak memory 199608 kb
Host smart-372ce992-96c6-4448-9efb-756ccbc85c89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113397963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.1113397963
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1565857837
Short name T74
Test name
Test status
Simulation time 95580303 ps
CPU time 0.87 seconds
Started Dec 27 12:36:09 PM PST 23
Finished Dec 27 12:36:31 PM PST 23
Peak memory 199660 kb
Host smart-c2d1725f-faf8-42ca-b2cb-df6e8f2210a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565857837 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.1565857837
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2992505138
Short name T212
Test name
Test status
Simulation time 83023648 ps
CPU time 0.79 seconds
Started Dec 27 12:35:36 PM PST 23
Finished Dec 27 12:35:50 PM PST 23
Peak memory 199404 kb
Host smart-3c98d125-cb47-4c21-9d50-c829b75f8d55
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992505138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.2992505138
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.3415690726
Short name T250
Test name
Test status
Simulation time 258533064 ps
CPU time 1.63 seconds
Started Dec 27 12:36:30 PM PST 23
Finished Dec 27 12:36:56 PM PST 23
Peak memory 199484 kb
Host smart-77972fd9-8466-404e-905c-0529e3bfc788
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415690726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.3415690726
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.2507125717
Short name T102
Test name
Test status
Simulation time 546035430 ps
CPU time 3.51 seconds
Started Dec 27 12:36:20 PM PST 23
Finished Dec 27 12:36:45 PM PST 23
Peak memory 199536 kb
Host smart-18558f56-2a7d-4a02-8451-4f00ee2516f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507125717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.2507125717
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3455082628
Short name T127
Test name
Test status
Simulation time 201957061 ps
CPU time 1.53 seconds
Started Dec 27 12:35:47 PM PST 23
Finished Dec 27 12:36:07 PM PST 23
Peak memory 199496 kb
Host smart-2b568d88-24bc-4be1-bf49-b7d792c4ba38
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455082628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.3
455082628
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3205365960
Short name T224
Test name
Test status
Simulation time 478067509 ps
CPU time 5.45 seconds
Started Dec 27 12:35:54 PM PST 23
Finished Dec 27 12:36:18 PM PST 23
Peak memory 199516 kb
Host smart-9814bb31-0b64-4b71-a33b-1a334cc27a4f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205365960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.3
205365960
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.3113090693
Short name T128
Test name
Test status
Simulation time 99117945 ps
CPU time 0.8 seconds
Started Dec 27 12:35:25 PM PST 23
Finished Dec 27 12:35:40 PM PST 23
Peak memory 199316 kb
Host smart-ad7077c6-548d-4d60-aa30-b6f4cb521938
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113090693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.3
113090693
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2529842708
Short name T110
Test name
Test status
Simulation time 125740645 ps
CPU time 1.41 seconds
Started Dec 27 12:35:26 PM PST 23
Finished Dec 27 12:35:41 PM PST 23
Peak memory 207840 kb
Host smart-928bccac-932b-4585-bd40-8fa62a26c0b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529842708 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.2529842708
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.758818132
Short name T198
Test name
Test status
Simulation time 85872719 ps
CPU time 0.8 seconds
Started Dec 27 12:35:29 PM PST 23
Finished Dec 27 12:35:43 PM PST 23
Peak memory 199480 kb
Host smart-7c8fec07-2065-426c-b077-91774af044cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758818132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.758818132
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1741770762
Short name T219
Test name
Test status
Simulation time 155366101 ps
CPU time 1.14 seconds
Started Dec 27 12:36:10 PM PST 23
Finished Dec 27 12:36:31 PM PST 23
Peak memory 199404 kb
Host smart-1272471a-1cc7-46d7-b9b3-2dec853492a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741770762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.1741770762
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.2731714330
Short name T200
Test name
Test status
Simulation time 366495201 ps
CPU time 2.68 seconds
Started Dec 27 12:35:27 PM PST 23
Finished Dec 27 12:35:43 PM PST 23
Peak memory 199660 kb
Host smart-6282b6e7-dca4-44ff-9c43-355ba2e1e451
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731714330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.2731714330
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1019957328
Short name T246
Test name
Test status
Simulation time 479195386 ps
CPU time 1.84 seconds
Started Dec 27 12:35:42 PM PST 23
Finished Dec 27 12:36:01 PM PST 23
Peak memory 199536 kb
Host smart-6e647e9b-c401-4906-bcbb-8c6d88b4fcdf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019957328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.1019957328
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.2605742654
Short name T247
Test name
Test status
Simulation time 251829954 ps
CPU time 1.58 seconds
Started Dec 27 12:35:37 PM PST 23
Finished Dec 27 12:35:51 PM PST 23
Peak memory 199608 kb
Host smart-638bcee0-92b7-4b6a-94cb-e9503f9006ff
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605742654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.2
605742654
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.3332884691
Short name T184
Test name
Test status
Simulation time 1168582513 ps
CPU time 5.48 seconds
Started Dec 27 12:35:54 PM PST 23
Finished Dec 27 12:36:18 PM PST 23
Peak memory 199420 kb
Host smart-c3993c1b-134f-422d-b0f3-21cef86eb0b2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332884691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.3
332884691
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.995883949
Short name T244
Test name
Test status
Simulation time 116041487 ps
CPU time 0.87 seconds
Started Dec 27 12:35:29 PM PST 23
Finished Dec 27 12:35:43 PM PST 23
Peak memory 199460 kb
Host smart-2dde5702-0ed6-425c-9503-d89f0ed0f863
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995883949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.995883949
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2304694734
Short name T204
Test name
Test status
Simulation time 179621675 ps
CPU time 1.72 seconds
Started Dec 27 12:36:03 PM PST 23
Finished Dec 27 12:36:23 PM PST 23
Peak memory 208360 kb
Host smart-f52c700e-8575-43c9-a615-4ebfd279e7fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304694734 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.2304694734
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3515499305
Short name T205
Test name
Test status
Simulation time 83647625 ps
CPU time 0.83 seconds
Started Dec 27 12:35:41 PM PST 23
Finished Dec 27 12:35:57 PM PST 23
Peak memory 199064 kb
Host smart-c9e2ce62-79ba-47e1-8a44-220c08af170c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515499305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.3515499305
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.3997015534
Short name T232
Test name
Test status
Simulation time 148029596 ps
CPU time 1.09 seconds
Started Dec 27 12:35:50 PM PST 23
Finished Dec 27 12:36:11 PM PST 23
Peak memory 199412 kb
Host smart-1aa85260-3513-4497-bdb9-f96f83a894ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997015534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.3997015534
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.1103912950
Short name T231
Test name
Test status
Simulation time 169373149 ps
CPU time 2.16 seconds
Started Dec 27 12:35:37 PM PST 23
Finished Dec 27 12:35:52 PM PST 23
Peak memory 199672 kb
Host smart-59d4b492-3b8a-43eb-8086-ffe2211c806e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103912950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.1103912950
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.2747743113
Short name T199
Test name
Test status
Simulation time 480579759 ps
CPU time 1.84 seconds
Started Dec 27 12:35:41 PM PST 23
Finished Dec 27 12:35:58 PM PST 23
Peak memory 199296 kb
Host smart-f36cd696-42eb-43d7-9562-58809f65ec7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747743113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.2747743113
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2540070750
Short name T190
Test name
Test status
Simulation time 106947484 ps
CPU time 1.35 seconds
Started Dec 27 12:36:21 PM PST 23
Finished Dec 27 12:36:44 PM PST 23
Peak memory 199452 kb
Host smart-56a3313d-2ad7-428b-8bb9-7269039f0106
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540070750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.2
540070750
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2574970512
Short name T211
Test name
Test status
Simulation time 490158759 ps
CPU time 5.52 seconds
Started Dec 27 12:35:57 PM PST 23
Finished Dec 27 12:36:21 PM PST 23
Peak memory 199496 kb
Host smart-9a3a82e6-069c-4a01-a2e3-8d4202d6b022
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574970512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.2
574970512
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.618612655
Short name T230
Test name
Test status
Simulation time 108314499 ps
CPU time 0.79 seconds
Started Dec 27 12:36:00 PM PST 23
Finished Dec 27 12:36:19 PM PST 23
Peak memory 199428 kb
Host smart-22e89d8c-435a-4d00-9a64-74d6408bcdd2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618612655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.618612655
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2074156611
Short name T111
Test name
Test status
Simulation time 136356708 ps
CPU time 0.95 seconds
Started Dec 27 12:36:17 PM PST 23
Finished Dec 27 12:36:39 PM PST 23
Peak memory 199416 kb
Host smart-0d997ddf-4d29-486e-98ed-a6e6fa6c8e63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074156611 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.2074156611
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.2272819431
Short name T123
Test name
Test status
Simulation time 87039334 ps
CPU time 0.85 seconds
Started Dec 27 12:36:15 PM PST 23
Finished Dec 27 12:36:37 PM PST 23
Peak memory 199368 kb
Host smart-8ae445f9-d31d-4945-a55d-bdcba5241aa5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272819431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.2272819431
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1675851116
Short name T202
Test name
Test status
Simulation time 169829725 ps
CPU time 1.31 seconds
Started Dec 27 12:35:23 PM PST 23
Finished Dec 27 12:35:40 PM PST 23
Peak memory 199616 kb
Host smart-60056a20-61cb-47d0-a976-06c3e398bcfa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675851116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.1675851116
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3404927415
Short name T233
Test name
Test status
Simulation time 512660872 ps
CPU time 3.59 seconds
Started Dec 27 12:35:45 PM PST 23
Finished Dec 27 12:36:07 PM PST 23
Peak memory 199584 kb
Host smart-c90794f5-9c5d-4836-b976-18188be0a7d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404927415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.3404927415
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3559730948
Short name T137
Test name
Test status
Simulation time 482191776 ps
CPU time 1.99 seconds
Started Dec 27 12:35:47 PM PST 23
Finished Dec 27 12:36:08 PM PST 23
Peak memory 199540 kb
Host smart-5ae3a37d-c149-4f72-8cbe-2a99537ceff9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559730948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.3559730948
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.756823490
Short name T192
Test name
Test status
Simulation time 183820109 ps
CPU time 1.21 seconds
Started Dec 27 12:35:55 PM PST 23
Finished Dec 27 12:36:14 PM PST 23
Peak memory 199444 kb
Host smart-106df9c9-ace0-4ff8-95ca-249a996e8842
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756823490 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.756823490
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.3371366482
Short name T129
Test name
Test status
Simulation time 90867433 ps
CPU time 0.83 seconds
Started Dec 27 12:35:34 PM PST 23
Finished Dec 27 12:35:47 PM PST 23
Peak memory 199360 kb
Host smart-21646091-b921-4416-961c-a7bc1c8b9543
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371366482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.3371366482
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.1436521222
Short name T209
Test name
Test status
Simulation time 79444352 ps
CPU time 0.91 seconds
Started Dec 27 12:36:07 PM PST 23
Finished Dec 27 12:36:29 PM PST 23
Peak memory 199552 kb
Host smart-4e5a0eac-0925-4c25-ac04-f2631489d814
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436521222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.1436521222
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.3342774399
Short name T245
Test name
Test status
Simulation time 195780050 ps
CPU time 2.69 seconds
Started Dec 27 12:36:00 PM PST 23
Finished Dec 27 12:36:21 PM PST 23
Peak memory 199504 kb
Host smart-68341ad3-4fe7-41b0-8874-3c311d3092d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342774399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.3342774399
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.482300302
Short name T188
Test name
Test status
Simulation time 874171812 ps
CPU time 2.94 seconds
Started Dec 27 12:35:49 PM PST 23
Finished Dec 27 12:36:12 PM PST 23
Peak memory 199532 kb
Host smart-f3c4b664-ba11-468a-a40e-599b7accc043
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482300302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err.
482300302
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.808721495
Short name T215
Test name
Test status
Simulation time 93621971 ps
CPU time 0.82 seconds
Started Dec 27 12:35:42 PM PST 23
Finished Dec 27 12:36:00 PM PST 23
Peak memory 199404 kb
Host smart-a4e15b9c-76fc-4b1f-a994-b17e27a5a88e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808721495 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.808721495
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1323204542
Short name T109
Test name
Test status
Simulation time 63659323 ps
CPU time 0.73 seconds
Started Dec 27 12:36:13 PM PST 23
Finished Dec 27 12:36:35 PM PST 23
Peak memory 199504 kb
Host smart-e25ef781-6e68-435d-8cee-c1ad50b9979c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323204542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.1323204542
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.508731789
Short name T182
Test name
Test status
Simulation time 132373670 ps
CPU time 0.97 seconds
Started Dec 27 12:36:02 PM PST 23
Finished Dec 27 12:36:22 PM PST 23
Peak memory 199544 kb
Host smart-d52c30d0-b39f-43a9-af2d-3634d06d923f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508731789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sam
e_csr_outstanding.508731789
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.625567509
Short name T79
Test name
Test status
Simulation time 371242434 ps
CPU time 2.24 seconds
Started Dec 27 12:35:36 PM PST 23
Finished Dec 27 12:35:51 PM PST 23
Peak memory 199616 kb
Host smart-00d4ab69-da7e-458c-bb13-6e2e42e85d7e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625567509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.625567509
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.981351710
Short name T248
Test name
Test status
Simulation time 102530228 ps
CPU time 0.97 seconds
Started Dec 27 12:36:09 PM PST 23
Finished Dec 27 12:36:31 PM PST 23
Peak memory 199472 kb
Host smart-fcc6a85b-3f1b-4082-8f8b-586ecdf19f3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981351710 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.981351710
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.555325464
Short name T217
Test name
Test status
Simulation time 70576751 ps
CPU time 0.78 seconds
Started Dec 27 12:36:26 PM PST 23
Finished Dec 27 12:36:49 PM PST 23
Peak memory 199416 kb
Host smart-22f3443a-60ac-4e6e-b375-8c12b9f4bc73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555325464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.555325464
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.2489540322
Short name T222
Test name
Test status
Simulation time 122330593 ps
CPU time 1 seconds
Started Dec 27 12:36:09 PM PST 23
Finished Dec 27 12:36:31 PM PST 23
Peak memory 199588 kb
Host smart-c266149d-7112-4ee6-942d-320b9060161c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489540322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.2489540322
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.585551468
Short name T77
Test name
Test status
Simulation time 328166707 ps
CPU time 2.05 seconds
Started Dec 27 12:35:59 PM PST 23
Finished Dec 27 12:36:20 PM PST 23
Peak memory 199480 kb
Host smart-d6efbd0c-df1b-4cc4-a0ec-df06296b0894
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585551468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.585551468
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.1856552089
Short name T179
Test name
Test status
Simulation time 776829641 ps
CPU time 2.74 seconds
Started Dec 27 12:36:05 PM PST 23
Finished Dec 27 12:36:26 PM PST 23
Peak memory 199556 kb
Host smart-58f74196-d563-45d2-b94a-486d1aa778b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856552089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.1856552089
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.4248600239
Short name T228
Test name
Test status
Simulation time 105619903 ps
CPU time 0.97 seconds
Started Dec 27 12:36:28 PM PST 23
Finished Dec 27 12:36:51 PM PST 23
Peak memory 199516 kb
Host smart-56677d99-d078-4215-88d9-e04e8bee041f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248600239 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.4248600239
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.891225665
Short name T236
Test name
Test status
Simulation time 67730464 ps
CPU time 0.73 seconds
Started Dec 27 12:36:30 PM PST 23
Finished Dec 27 12:36:55 PM PST 23
Peak memory 199484 kb
Host smart-9ebf6cd0-9e97-439f-b7f4-a45eb65720c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891225665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.891225665
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.95780286
Short name T195
Test name
Test status
Simulation time 141080852 ps
CPU time 1.04 seconds
Started Dec 27 12:35:38 PM PST 23
Finished Dec 27 12:35:52 PM PST 23
Peak memory 199464 kb
Host smart-e3833073-901a-49e1-ac92-02d741633187
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95780286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_same
_csr_outstanding.95780286
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.3802479684
Short name T180
Test name
Test status
Simulation time 310946265 ps
CPU time 2.16 seconds
Started Dec 27 12:35:32 PM PST 23
Finished Dec 27 12:35:53 PM PST 23
Peak memory 199556 kb
Host smart-c0fe82a9-f2b5-4ecf-b0a2-096ce98c134d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802479684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.3802479684
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3313533456
Short name T193
Test name
Test status
Simulation time 896323293 ps
CPU time 3.09 seconds
Started Dec 27 12:36:12 PM PST 23
Finished Dec 27 12:36:36 PM PST 23
Peak memory 199640 kb
Host smart-dd1e1a91-bb2d-4c7c-ae84-268f1fcd5af5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313533456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.3313533456
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2305132153
Short name T143
Test name
Test status
Simulation time 162321903 ps
CPU time 1.03 seconds
Started Dec 27 12:36:31 PM PST 23
Finished Dec 27 12:36:59 PM PST 23
Peak memory 199544 kb
Host smart-0ff032b7-99db-496b-9437-265880fc57ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305132153 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.2305132153
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1688251790
Short name T185
Test name
Test status
Simulation time 73783761 ps
CPU time 0.73 seconds
Started Dec 27 12:35:48 PM PST 23
Finished Dec 27 12:36:08 PM PST 23
Peak memory 199400 kb
Host smart-c0a6b604-83e4-4222-96a5-63be5677c994
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688251790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.1688251790
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.3055550835
Short name T218
Test name
Test status
Simulation time 128779886 ps
CPU time 0.96 seconds
Started Dec 27 12:35:46 PM PST 23
Finished Dec 27 12:36:06 PM PST 23
Peak memory 199468 kb
Host smart-6bbb0c29-6b85-471d-9b5d-0f27a06bfda0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055550835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.3055550835
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.728160865
Short name T225
Test name
Test status
Simulation time 552192398 ps
CPU time 3.75 seconds
Started Dec 27 12:36:12 PM PST 23
Finished Dec 27 12:36:36 PM PST 23
Peak memory 199564 kb
Host smart-e8bbe153-3ee3-4b3f-80a3-8cf98180285f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728160865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.728160865
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1213669986
Short name T207
Test name
Test status
Simulation time 497568936 ps
CPU time 1.82 seconds
Started Dec 27 12:35:43 PM PST 23
Finished Dec 27 12:36:03 PM PST 23
Peak memory 199516 kb
Host smart-66b20c53-5656-4776-a766-bab332fb6fad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213669986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.1213669986
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.1062882437
Short name T551
Test name
Test status
Simulation time 72744738 ps
CPU time 0.8 seconds
Started Dec 27 12:46:56 PM PST 23
Finished Dec 27 12:47:15 PM PST 23
Peak memory 199144 kb
Host smart-5daaad57-68e6-4af2-afc2-dc10d2e20b3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062882437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.1062882437
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.2733424646
Short name T589
Test name
Test status
Simulation time 244828167 ps
CPU time 1.08 seconds
Started Dec 27 12:46:55 PM PST 23
Finished Dec 27 12:47:15 PM PST 23
Peak memory 216404 kb
Host smart-fd466bfb-336a-4c35-ab4b-2dd4b8e40841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733424646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.2733424646
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.2419102263
Short name T81
Test name
Test status
Simulation time 16509406685 ps
CPU time 30.78 seconds
Started Dec 27 12:46:55 PM PST 23
Finished Dec 27 12:47:44 PM PST 23
Peak memory 217360 kb
Host smart-95cb74c5-694f-4586-8562-f429bba9270e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419102263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.2419102263
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.3406718936
Short name T164
Test name
Test status
Simulation time 99666542 ps
CPU time 0.97 seconds
Started Dec 27 12:46:57 PM PST 23
Finished Dec 27 12:47:16 PM PST 23
Peak memory 199248 kb
Host smart-6cdedbf4-440f-4dff-8ace-20c7b3e3677f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406718936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.3406718936
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.4180364539
Short name T430
Test name
Test status
Simulation time 254362188 ps
CPU time 1.47 seconds
Started Dec 27 12:46:56 PM PST 23
Finished Dec 27 12:47:16 PM PST 23
Peak memory 199376 kb
Host smart-17414bea-536b-43e4-8dd9-f05b22984379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180364539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.4180364539
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.4018320487
Short name T435
Test name
Test status
Simulation time 8904065098 ps
CPU time 30.89 seconds
Started Dec 27 12:46:53 PM PST 23
Finished Dec 27 12:47:43 PM PST 23
Peak memory 199536 kb
Host smart-9977ebaa-680a-42fa-9897-2568e1c139af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018320487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.4018320487
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.2563082874
Short name T476
Test name
Test status
Simulation time 315664585 ps
CPU time 1.88 seconds
Started Dec 27 12:46:53 PM PST 23
Finished Dec 27 12:47:14 PM PST 23
Peak memory 199236 kb
Host smart-1049d5a3-8efb-4238-9c4e-5ccc8dc4c623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563082874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.2563082874
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.3809164402
Short name T609
Test name
Test status
Simulation time 143904534 ps
CPU time 1.1 seconds
Started Dec 27 12:46:56 PM PST 23
Finished Dec 27 12:47:15 PM PST 23
Peak memory 199232 kb
Host smart-48bf6a45-eb78-4877-af1e-cafc42dd8b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809164402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.3809164402
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.77313265
Short name T470
Test name
Test status
Simulation time 1228463918 ps
CPU time 5.21 seconds
Started Dec 27 12:46:57 PM PST 23
Finished Dec 27 12:47:20 PM PST 23
Peak memory 217620 kb
Host smart-9ea53cd5-1a53-4057-a3df-5c4c86341fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77313265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.77313265
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.453202616
Short name T550
Test name
Test status
Simulation time 245165933 ps
CPU time 1.02 seconds
Started Dec 27 12:46:55 PM PST 23
Finished Dec 27 12:47:14 PM PST 23
Peak memory 216496 kb
Host smart-645c47bc-bc98-4d4e-85f1-cd7275b577db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453202616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.453202616
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.800393478
Short name T480
Test name
Test status
Simulation time 210749760 ps
CPU time 0.95 seconds
Started Dec 27 12:46:52 PM PST 23
Finished Dec 27 12:47:13 PM PST 23
Peak memory 199056 kb
Host smart-77de54ac-9608-4f49-8fe7-e7781be109a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800393478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.800393478
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.2276981613
Short name T286
Test name
Test status
Simulation time 859579519 ps
CPU time 4.12 seconds
Started Dec 27 12:46:55 PM PST 23
Finished Dec 27 12:47:18 PM PST 23
Peak memory 199524 kb
Host smart-558929d6-7f84-4fd2-abeb-dfb3dbfabc71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276981613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.2276981613
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.3426133988
Short name T85
Test name
Test status
Simulation time 9575392266 ps
CPU time 15.62 seconds
Started Dec 27 12:46:54 PM PST 23
Finished Dec 27 12:47:28 PM PST 23
Peak memory 216296 kb
Host smart-4156fb24-54a1-46ad-b91b-f31a03664726
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426133988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.3426133988
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.1768770548
Short name T156
Test name
Test status
Simulation time 94116232 ps
CPU time 0.96 seconds
Started Dec 27 12:46:57 PM PST 23
Finished Dec 27 12:47:16 PM PST 23
Peak memory 199252 kb
Host smart-133f67e7-b548-4a0e-8e38-e32662d8df20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768770548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.1768770548
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.948746303
Short name T161
Test name
Test status
Simulation time 110193181 ps
CPU time 1.15 seconds
Started Dec 27 12:46:54 PM PST 23
Finished Dec 27 12:47:14 PM PST 23
Peak memory 199392 kb
Host smart-a7fb3891-49e2-4ee0-b483-f346a3c0060c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948746303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.948746303
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.2556193527
Short name T125
Test name
Test status
Simulation time 13407637921 ps
CPU time 48.21 seconds
Started Dec 27 12:46:55 PM PST 23
Finished Dec 27 12:48:02 PM PST 23
Peak memory 199540 kb
Host smart-2761e586-513a-442d-b6a2-3e433160550b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556193527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.2556193527
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.4103267200
Short name T620
Test name
Test status
Simulation time 260914415 ps
CPU time 1.74 seconds
Started Dec 27 12:46:54 PM PST 23
Finished Dec 27 12:47:15 PM PST 23
Peak memory 199184 kb
Host smart-f2cb1409-f827-4bab-b617-f42fa0d82e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103267200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.4103267200
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.3267619746
Short name T445
Test name
Test status
Simulation time 152369144 ps
CPU time 1.26 seconds
Started Dec 27 12:46:55 PM PST 23
Finished Dec 27 12:47:15 PM PST 23
Peak memory 199412 kb
Host smart-349ba6fe-4d7f-4785-b161-34d9c27bf8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267619746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.3267619746
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.4066324823
Short name T603
Test name
Test status
Simulation time 87064456 ps
CPU time 0.78 seconds
Started Dec 27 12:47:24 PM PST 23
Finished Dec 27 12:47:35 PM PST 23
Peak memory 199136 kb
Host smart-8ec19c13-a71f-4a31-ac74-e5de361eca54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066324823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.4066324823
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.3563440633
Short name T32
Test name
Test status
Simulation time 1224421680 ps
CPU time 5.28 seconds
Started Dec 27 12:47:26 PM PST 23
Finished Dec 27 12:47:41 PM PST 23
Peak memory 220100 kb
Host smart-38287a92-890a-446f-9c85-5387386166d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563440633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.3563440633
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.3843387750
Short name T619
Test name
Test status
Simulation time 243912124 ps
CPU time 1.03 seconds
Started Dec 27 12:47:17 PM PST 23
Finished Dec 27 12:47:30 PM PST 23
Peak memory 216436 kb
Host smart-6149f481-b1c7-4686-854f-8f7f45e56d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843387750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.3843387750
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.4216369555
Short name T17
Test name
Test status
Simulation time 91498706 ps
CPU time 0.74 seconds
Started Dec 27 12:47:22 PM PST 23
Finished Dec 27 12:47:33 PM PST 23
Peak memory 199060 kb
Host smart-a0955cde-eb21-49be-90bc-74e877d105b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216369555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.4216369555
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.2516498861
Short name T257
Test name
Test status
Simulation time 1748202139 ps
CPU time 6.5 seconds
Started Dec 27 12:47:24 PM PST 23
Finished Dec 27 12:47:41 PM PST 23
Peak memory 199452 kb
Host smart-3a7d6caf-8982-4a39-9da4-67995f68e46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516498861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.2516498861
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.4219397387
Short name T410
Test name
Test status
Simulation time 143704178 ps
CPU time 1.08 seconds
Started Dec 27 12:47:25 PM PST 23
Finished Dec 27 12:47:36 PM PST 23
Peak memory 199360 kb
Host smart-38ef2dab-5a79-493e-aa36-2b716141bc0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219397387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.4219397387
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.3897215953
Short name T485
Test name
Test status
Simulation time 121363062 ps
CPU time 1.18 seconds
Started Dec 27 12:47:24 PM PST 23
Finished Dec 27 12:47:36 PM PST 23
Peak memory 199420 kb
Host smart-5b915651-ec18-419a-8c43-635386d7fc20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897215953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.3897215953
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.2254924157
Short name T482
Test name
Test status
Simulation time 3163427487 ps
CPU time 15.19 seconds
Started Dec 27 12:47:18 PM PST 23
Finished Dec 27 12:47:44 PM PST 23
Peak memory 199480 kb
Host smart-535f4044-3034-4e64-baeb-2eec9899b030
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254924157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.2254924157
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.3751926558
Short name T374
Test name
Test status
Simulation time 138861850 ps
CPU time 1.78 seconds
Started Dec 27 12:47:24 PM PST 23
Finished Dec 27 12:47:36 PM PST 23
Peak memory 199268 kb
Host smart-c5410b5b-3b6a-4344-bc11-304a824722e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751926558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.3751926558
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.2947389343
Short name T344
Test name
Test status
Simulation time 134537305 ps
CPU time 1.12 seconds
Started Dec 27 12:47:29 PM PST 23
Finished Dec 27 12:47:39 PM PST 23
Peak memory 199308 kb
Host smart-90ba76a8-ef02-464e-8c66-7e04e4494a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947389343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.2947389343
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.1178983744
Short name T316
Test name
Test status
Simulation time 77831302 ps
CPU time 0.77 seconds
Started Dec 27 12:47:26 PM PST 23
Finished Dec 27 12:47:37 PM PST 23
Peak memory 199132 kb
Host smart-57b87ded-8e8c-495b-b26f-65bf1b611470
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178983744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.1178983744
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.790056925
Short name T56
Test name
Test status
Simulation time 1225039115 ps
CPU time 5.98 seconds
Started Dec 27 12:47:18 PM PST 23
Finished Dec 27 12:47:35 PM PST 23
Peak memory 217764 kb
Host smart-f8e2a4c1-7037-4ba7-8e5b-baacc69e51ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790056925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.790056925
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.1391910204
Short name T426
Test name
Test status
Simulation time 244606159 ps
CPU time 1.13 seconds
Started Dec 27 12:47:19 PM PST 23
Finished Dec 27 12:47:31 PM PST 23
Peak memory 216304 kb
Host smart-de507ee0-f098-4570-baaf-777cbdc88feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391910204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.1391910204
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.2574612664
Short name T518
Test name
Test status
Simulation time 115564534 ps
CPU time 0.74 seconds
Started Dec 27 12:47:22 PM PST 23
Finished Dec 27 12:47:34 PM PST 23
Peak memory 199096 kb
Host smart-8ebe7a9b-a148-4123-9b2e-11e26855f891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574612664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.2574612664
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.3961268500
Short name T299
Test name
Test status
Simulation time 1563211706 ps
CPU time 6.37 seconds
Started Dec 27 12:47:24 PM PST 23
Finished Dec 27 12:47:40 PM PST 23
Peak memory 199464 kb
Host smart-6871128f-5f6b-40af-b984-3a8f549d63e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961268500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.3961268500
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.1353597367
Short name T468
Test name
Test status
Simulation time 99526301 ps
CPU time 0.99 seconds
Started Dec 27 12:47:21 PM PST 23
Finished Dec 27 12:47:32 PM PST 23
Peak memory 199268 kb
Host smart-2e4a75d8-611c-44eb-90a7-1cad9806cc0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353597367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.1353597367
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.1141370041
Short name T446
Test name
Test status
Simulation time 122318856 ps
CPU time 1.2 seconds
Started Dec 27 12:47:24 PM PST 23
Finished Dec 27 12:47:35 PM PST 23
Peak memory 199412 kb
Host smart-19a954ba-cdac-4d29-a1d4-d209c5d27c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141370041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.1141370041
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.2411685188
Short name T420
Test name
Test status
Simulation time 4915435594 ps
CPU time 18.58 seconds
Started Dec 27 12:47:22 PM PST 23
Finished Dec 27 12:47:51 PM PST 23
Peak memory 199508 kb
Host smart-461b9593-ee52-4ae8-8f5d-818cd63eb2db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411685188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.2411685188
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.1797500888
Short name T267
Test name
Test status
Simulation time 468705524 ps
CPU time 2.58 seconds
Started Dec 27 12:47:35 PM PST 23
Finished Dec 27 12:47:48 PM PST 23
Peak memory 199224 kb
Host smart-dc0ee5b5-d26f-4765-b364-2f1223297161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797500888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.1797500888
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.962719371
Short name T174
Test name
Test status
Simulation time 73366785 ps
CPU time 0.79 seconds
Started Dec 27 12:47:23 PM PST 23
Finished Dec 27 12:47:34 PM PST 23
Peak memory 199108 kb
Host smart-b0addd00-dff2-4ff5-a15a-7022ecbb4d9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962719371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.962719371
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.568362867
Short name T556
Test name
Test status
Simulation time 2352758428 ps
CPU time 7.6 seconds
Started Dec 27 12:47:29 PM PST 23
Finished Dec 27 12:47:46 PM PST 23
Peak memory 216508 kb
Host smart-af3d4b4a-6c73-4b44-a91b-d12a84316a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568362867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.568362867
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.3320425097
Short name T407
Test name
Test status
Simulation time 244245660 ps
CPU time 1.11 seconds
Started Dec 27 12:47:26 PM PST 23
Finished Dec 27 12:47:37 PM PST 23
Peak memory 216476 kb
Host smart-239439b3-aa1c-4a41-9109-d8a0dd8aacdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320425097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.3320425097
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.2246109567
Short name T259
Test name
Test status
Simulation time 100189282 ps
CPU time 0.73 seconds
Started Dec 27 12:47:18 PM PST 23
Finished Dec 27 12:47:30 PM PST 23
Peak memory 199056 kb
Host smart-e6fc33fd-6142-4a5e-9641-510c5fbcf296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246109567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.2246109567
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.808219494
Short name T51
Test name
Test status
Simulation time 1313258751 ps
CPU time 5.43 seconds
Started Dec 27 12:47:16 PM PST 23
Finished Dec 27 12:47:34 PM PST 23
Peak memory 199424 kb
Host smart-593f7b23-9915-466e-b391-cd96762c544e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808219494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.808219494
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.437362628
Short name T361
Test name
Test status
Simulation time 99147550 ps
CPU time 0.94 seconds
Started Dec 27 12:47:17 PM PST 23
Finished Dec 27 12:47:30 PM PST 23
Peak memory 199264 kb
Host smart-4ef9a469-77e6-44e5-a1d2-adc12d8bf50e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437362628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.437362628
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.2403464177
Short name T297
Test name
Test status
Simulation time 206108296 ps
CPU time 1.31 seconds
Started Dec 27 12:47:24 PM PST 23
Finished Dec 27 12:47:36 PM PST 23
Peak memory 199412 kb
Host smart-323137d6-d0dd-4959-844b-555c63139a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403464177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.2403464177
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.3543892548
Short name T289
Test name
Test status
Simulation time 5645948607 ps
CPU time 25.41 seconds
Started Dec 27 12:47:23 PM PST 23
Finished Dec 27 12:47:59 PM PST 23
Peak memory 199564 kb
Host smart-5e56d575-ba96-48a0-8dc5-a0aeff1c03b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543892548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.3543892548
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.1083870305
Short name T385
Test name
Test status
Simulation time 408831576 ps
CPU time 2.26 seconds
Started Dec 27 12:47:21 PM PST 23
Finished Dec 27 12:47:34 PM PST 23
Peak memory 199252 kb
Host smart-acd1c8f2-2c84-42c3-82d2-c4d88b4cd442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083870305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.1083870305
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.3267406837
Short name T150
Test name
Test status
Simulation time 245703119 ps
CPU time 1.36 seconds
Started Dec 27 12:47:18 PM PST 23
Finished Dec 27 12:47:31 PM PST 23
Peak memory 199276 kb
Host smart-beb2ce64-6a47-4c8d-bf4e-6e1b5fea716f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267406837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.3267406837
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.1823812799
Short name T173
Test name
Test status
Simulation time 65563504 ps
CPU time 0.76 seconds
Started Dec 27 12:47:15 PM PST 23
Finished Dec 27 12:47:28 PM PST 23
Peak memory 199156 kb
Host smart-9c8cb8de-9184-46be-a4a2-74724ca610af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823812799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.1823812799
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.1254246364
Short name T59
Test name
Test status
Simulation time 1228915221 ps
CPU time 5.66 seconds
Started Dec 27 12:47:32 PM PST 23
Finished Dec 27 12:47:47 PM PST 23
Peak memory 217232 kb
Host smart-06f4a49a-021c-4e9d-bbdd-d9a4f3f7c462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254246364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.1254246364
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.218025389
Short name T340
Test name
Test status
Simulation time 243530794 ps
CPU time 1.08 seconds
Started Dec 27 12:47:24 PM PST 23
Finished Dec 27 12:47:35 PM PST 23
Peak memory 216416 kb
Host smart-80902781-9f38-4d7f-aa92-130c31357ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218025389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.218025389
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.3265166167
Short name T362
Test name
Test status
Simulation time 142273991 ps
CPU time 0.85 seconds
Started Dec 27 12:47:26 PM PST 23
Finished Dec 27 12:47:37 PM PST 23
Peak memory 199164 kb
Host smart-6ee4ace3-8f2e-44b5-b8f1-3f4d38c1e174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265166167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.3265166167
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.3419574952
Short name T113
Test name
Test status
Simulation time 1708428675 ps
CPU time 6.39 seconds
Started Dec 27 12:47:23 PM PST 23
Finished Dec 27 12:47:40 PM PST 23
Peak memory 199468 kb
Host smart-cc399ed0-a95e-45ac-8f14-ed92ff934d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419574952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.3419574952
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.3297190325
Short name T587
Test name
Test status
Simulation time 112538999 ps
CPU time 0.99 seconds
Started Dec 27 12:47:22 PM PST 23
Finished Dec 27 12:47:34 PM PST 23
Peak memory 199268 kb
Host smart-042e9ec8-331c-4b7c-b0bf-308705068672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297190325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.3297190325
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.3959248456
Short name T301
Test name
Test status
Simulation time 199904701 ps
CPU time 1.28 seconds
Started Dec 27 12:47:25 PM PST 23
Finished Dec 27 12:47:36 PM PST 23
Peak memory 199412 kb
Host smart-8a9dc98b-3c9e-4e78-8629-5f919f23b770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959248456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.3959248456
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.1270969292
Short name T477
Test name
Test status
Simulation time 7389307532 ps
CPU time 32.21 seconds
Started Dec 27 12:47:20 PM PST 23
Finished Dec 27 12:48:03 PM PST 23
Peak memory 199548 kb
Host smart-7c56004c-9f13-4c25-931b-f98006a0403a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270969292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.1270969292
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.4080618020
Short name T101
Test name
Test status
Simulation time 130661685 ps
CPU time 1.65 seconds
Started Dec 27 12:47:16 PM PST 23
Finished Dec 27 12:47:29 PM PST 23
Peak memory 199252 kb
Host smart-682487ad-3450-435f-be03-a539097780f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080618020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.4080618020
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.2718996630
Short name T269
Test name
Test status
Simulation time 171582907 ps
CPU time 1.1 seconds
Started Dec 27 12:47:23 PM PST 23
Finished Dec 27 12:47:35 PM PST 23
Peak memory 199284 kb
Host smart-4b90c523-bffd-4058-a2f5-313169db0240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718996630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.2718996630
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.131349378
Short name T53
Test name
Test status
Simulation time 72565885 ps
CPU time 0.76 seconds
Started Dec 27 12:47:27 PM PST 23
Finished Dec 27 12:47:37 PM PST 23
Peak memory 199104 kb
Host smart-a8f56fad-8a01-4400-ab00-c45598be52b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131349378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.131349378
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.3005550866
Short name T48
Test name
Test status
Simulation time 1876591317 ps
CPU time 7.46 seconds
Started Dec 27 12:47:23 PM PST 23
Finished Dec 27 12:47:41 PM PST 23
Peak memory 216644 kb
Host smart-1d5d8c54-6ad9-44cb-828f-06d3ee74e78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005550866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.3005550866
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.1017515281
Short name T517
Test name
Test status
Simulation time 246692365 ps
CPU time 1.01 seconds
Started Dec 27 12:47:24 PM PST 23
Finished Dec 27 12:47:35 PM PST 23
Peak memory 216476 kb
Host smart-594f068b-560a-4673-85e6-c5f61847c49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017515281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.1017515281
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.2806401504
Short name T473
Test name
Test status
Simulation time 100904209 ps
CPU time 0.72 seconds
Started Dec 27 12:47:23 PM PST 23
Finished Dec 27 12:47:34 PM PST 23
Peak memory 199136 kb
Host smart-626cb545-266c-4fcb-8498-d7d4307fcb6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806401504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.2806401504
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.2104342162
Short name T360
Test name
Test status
Simulation time 1477628118 ps
CPU time 5.47 seconds
Started Dec 27 12:47:25 PM PST 23
Finished Dec 27 12:47:40 PM PST 23
Peak memory 199348 kb
Host smart-ac1d3f63-532e-44e0-8eb6-9f852b7eda64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104342162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.2104342162
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.1121520015
Short name T166
Test name
Test status
Simulation time 144451860 ps
CPU time 1.11 seconds
Started Dec 27 12:47:23 PM PST 23
Finished Dec 27 12:47:35 PM PST 23
Peak memory 199252 kb
Host smart-17eefb82-02af-4aa3-bf9c-d86f83c81058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121520015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.1121520015
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.309036105
Short name T63
Test name
Test status
Simulation time 188024094 ps
CPU time 1.32 seconds
Started Dec 27 12:47:31 PM PST 23
Finished Dec 27 12:47:42 PM PST 23
Peak memory 199384 kb
Host smart-71ba7dad-4351-4101-b145-7332c7707ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309036105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.309036105
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.2871164923
Short name T440
Test name
Test status
Simulation time 506069167 ps
CPU time 2.33 seconds
Started Dec 27 12:47:25 PM PST 23
Finished Dec 27 12:47:37 PM PST 23
Peak memory 199480 kb
Host smart-f1cf15ae-db9a-4ee2-9d6e-fbdf5a876cae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871164923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.2871164923
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.824873461
Short name T268
Test name
Test status
Simulation time 105736127 ps
CPU time 0.88 seconds
Started Dec 27 12:47:20 PM PST 23
Finished Dec 27 12:47:32 PM PST 23
Peak memory 199292 kb
Host smart-a8101ac3-0e4b-4ea5-b685-c6585f997353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824873461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.824873461
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.3927650028
Short name T312
Test name
Test status
Simulation time 72452426 ps
CPU time 0.77 seconds
Started Dec 27 12:47:31 PM PST 23
Finished Dec 27 12:47:40 PM PST 23
Peak memory 199136 kb
Host smart-491f05da-227d-4d67-855b-4f8ac7c1cfce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927650028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.3927650028
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.563900330
Short name T559
Test name
Test status
Simulation time 2375099634 ps
CPU time 8.56 seconds
Started Dec 27 12:47:26 PM PST 23
Finished Dec 27 12:47:44 PM PST 23
Peak memory 216952 kb
Host smart-c48072b2-8134-4ca9-a84c-61cc103dacba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563900330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.563900330
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.1784357912
Short name T392
Test name
Test status
Simulation time 245737847 ps
CPU time 1 seconds
Started Dec 27 12:47:31 PM PST 23
Finished Dec 27 12:47:41 PM PST 23
Peak memory 216416 kb
Host smart-fab9b2db-a21d-43d7-b56e-b33139f19352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784357912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.1784357912
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.3274433366
Short name T13
Test name
Test status
Simulation time 236189793 ps
CPU time 0.96 seconds
Started Dec 27 12:47:23 PM PST 23
Finished Dec 27 12:47:35 PM PST 23
Peak memory 199072 kb
Host smart-6cd69910-3be0-46f6-80cb-76c639b2f5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274433366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.3274433366
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.2655063670
Short name T568
Test name
Test status
Simulation time 938170384 ps
CPU time 4.57 seconds
Started Dec 27 12:47:25 PM PST 23
Finished Dec 27 12:47:39 PM PST 23
Peak memory 199332 kb
Host smart-1a3b1911-d53f-4dfe-818e-c908cd737771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655063670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.2655063670
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.3622346634
Short name T391
Test name
Test status
Simulation time 102820791 ps
CPU time 0.95 seconds
Started Dec 27 12:47:24 PM PST 23
Finished Dec 27 12:47:35 PM PST 23
Peak memory 199272 kb
Host smart-935353ff-85a0-4313-9f0b-b6103ccacdfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622346634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.3622346634
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.895908151
Short name T401
Test name
Test status
Simulation time 246874381 ps
CPU time 1.53 seconds
Started Dec 27 12:47:26 PM PST 23
Finished Dec 27 12:47:37 PM PST 23
Peak memory 199404 kb
Host smart-b956f957-424a-40e0-9d49-cd3be7adb981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895908151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.895908151
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.2319136276
Short name T581
Test name
Test status
Simulation time 126233884 ps
CPU time 1 seconds
Started Dec 27 12:47:34 PM PST 23
Finished Dec 27 12:47:45 PM PST 23
Peak memory 199180 kb
Host smart-c90ba542-8db1-4d18-8d6d-69c9541bba56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319136276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.2319136276
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.1329839122
Short name T171
Test name
Test status
Simulation time 367745743 ps
CPU time 2.39 seconds
Started Dec 27 12:47:23 PM PST 23
Finished Dec 27 12:47:36 PM PST 23
Peak memory 199200 kb
Host smart-95259d90-5367-457a-b0a3-1eb7416e6a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329839122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.1329839122
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.3405771326
Short name T406
Test name
Test status
Simulation time 138956050 ps
CPU time 1.09 seconds
Started Dec 27 12:47:27 PM PST 23
Finished Dec 27 12:47:37 PM PST 23
Peak memory 199340 kb
Host smart-e21bd959-cee3-4ad9-bb66-a042a9d499e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405771326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.3405771326
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.2910291952
Short name T315
Test name
Test status
Simulation time 88157853 ps
CPU time 0.8 seconds
Started Dec 27 12:47:30 PM PST 23
Finished Dec 27 12:47:40 PM PST 23
Peak memory 199156 kb
Host smart-af0b9f9a-5edc-4c40-9e78-06692d31e3e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910291952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.2910291952
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.3771807203
Short name T29
Test name
Test status
Simulation time 1227665772 ps
CPU time 5.27 seconds
Started Dec 27 12:47:36 PM PST 23
Finished Dec 27 12:47:51 PM PST 23
Peak memory 220520 kb
Host smart-948ab957-5bc3-4e32-b682-58bb72bb92c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771807203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.3771807203
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.1241206616
Short name T592
Test name
Test status
Simulation time 245617167 ps
CPU time 1.08 seconds
Started Dec 27 12:47:33 PM PST 23
Finished Dec 27 12:47:50 PM PST 23
Peak memory 216328 kb
Host smart-189f3bc2-e50c-4f16-8753-3660e2da7cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241206616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.1241206616
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.2110089554
Short name T416
Test name
Test status
Simulation time 191082537 ps
CPU time 0.88 seconds
Started Dec 27 12:47:30 PM PST 23
Finished Dec 27 12:47:40 PM PST 23
Peak memory 199048 kb
Host smart-d30674db-dc58-4d2c-96be-3406c6310691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110089554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.2110089554
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.1429433705
Short name T545
Test name
Test status
Simulation time 1764677630 ps
CPU time 5.66 seconds
Started Dec 27 12:47:30 PM PST 23
Finished Dec 27 12:47:45 PM PST 23
Peak memory 199432 kb
Host smart-4b1d4b22-278e-4441-9aff-5e238b547db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429433705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.1429433705
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.2990407012
Short name T293
Test name
Test status
Simulation time 107359238 ps
CPU time 0.97 seconds
Started Dec 27 12:47:26 PM PST 23
Finished Dec 27 12:47:36 PM PST 23
Peak memory 199284 kb
Host smart-4528ae93-3b15-47f8-9c86-1a795088ca76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990407012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.2990407012
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.144744662
Short name T23
Test name
Test status
Simulation time 115444586 ps
CPU time 1.13 seconds
Started Dec 27 12:47:26 PM PST 23
Finished Dec 27 12:47:37 PM PST 23
Peak memory 199408 kb
Host smart-c1c39d45-1a8a-4427-8475-817ce21a39e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144744662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.144744662
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.451813748
Short name T337
Test name
Test status
Simulation time 8835304410 ps
CPU time 37.05 seconds
Started Dec 27 12:47:31 PM PST 23
Finished Dec 27 12:48:17 PM PST 23
Peak memory 199512 kb
Host smart-62111b1c-27d9-412a-afc5-eb97e65235ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451813748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.451813748
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.3845632482
Short name T265
Test name
Test status
Simulation time 120456677 ps
CPU time 1.5 seconds
Started Dec 27 12:47:32 PM PST 23
Finished Dec 27 12:47:42 PM PST 23
Peak memory 199332 kb
Host smart-b6e655b9-d475-4a89-84a6-5311cfb3456e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845632482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.3845632482
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.2104421377
Short name T120
Test name
Test status
Simulation time 107112419 ps
CPU time 0.92 seconds
Started Dec 27 12:47:31 PM PST 23
Finished Dec 27 12:47:41 PM PST 23
Peak memory 199268 kb
Host smart-9c539dfd-e155-45bd-928e-df8b3fc7de4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104421377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.2104421377
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.1117370560
Short name T612
Test name
Test status
Simulation time 72938127 ps
CPU time 0.85 seconds
Started Dec 27 12:47:33 PM PST 23
Finished Dec 27 12:47:43 PM PST 23
Peak memory 198936 kb
Host smart-d9665f42-3b19-470f-9d22-6c091298955c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117370560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.1117370560
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.2089952863
Short name T33
Test name
Test status
Simulation time 2350553086 ps
CPU time 7.71 seconds
Started Dec 27 12:47:35 PM PST 23
Finished Dec 27 12:47:52 PM PST 23
Peak memory 216452 kb
Host smart-3262ce1f-89b6-48cd-97e3-db9f769eb0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089952863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.2089952863
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.2265850669
Short name T447
Test name
Test status
Simulation time 244750897 ps
CPU time 1.11 seconds
Started Dec 27 12:47:35 PM PST 23
Finished Dec 27 12:47:46 PM PST 23
Peak memory 216276 kb
Host smart-c38e663c-8790-42ca-9f8c-359c2d7561e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265850669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.2265850669
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.976701197
Short name T4
Test name
Test status
Simulation time 117734553 ps
CPU time 0.82 seconds
Started Dec 27 12:47:32 PM PST 23
Finished Dec 27 12:47:42 PM PST 23
Peak memory 199064 kb
Host smart-d3eb39bb-a07c-45aa-89cc-1c1fe9ff1cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976701197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.976701197
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.4030934999
Short name T367
Test name
Test status
Simulation time 1579093981 ps
CPU time 5.63 seconds
Started Dec 27 12:47:32 PM PST 23
Finished Dec 27 12:47:46 PM PST 23
Peak memory 199508 kb
Host smart-33917f95-94b3-4e7e-9fe2-262ac023df1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030934999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.4030934999
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.1820362493
Short name T255
Test name
Test status
Simulation time 102406594 ps
CPU time 0.95 seconds
Started Dec 27 12:47:34 PM PST 23
Finished Dec 27 12:47:45 PM PST 23
Peak memory 199256 kb
Host smart-6d3689a1-15f5-42ce-a21f-1eca34cbf835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820362493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.1820362493
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.296378236
Short name T271
Test name
Test status
Simulation time 124040314 ps
CPU time 1.13 seconds
Started Dec 27 12:47:29 PM PST 23
Finished Dec 27 12:47:40 PM PST 23
Peak memory 199400 kb
Host smart-7802fc51-e1f6-4b13-91b1-47426868b15b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296378236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.296378236
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.4259264475
Short name T92
Test name
Test status
Simulation time 10469528181 ps
CPU time 33.04 seconds
Started Dec 27 12:47:33 PM PST 23
Finished Dec 27 12:48:16 PM PST 23
Peak memory 199492 kb
Host smart-ab6cbf0a-6fbb-42e2-9569-4330115db56d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259264475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.4259264475
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.2717763035
Short name T526
Test name
Test status
Simulation time 140580022 ps
CPU time 1.83 seconds
Started Dec 27 12:47:31 PM PST 23
Finished Dec 27 12:47:41 PM PST 23
Peak memory 199308 kb
Host smart-ab381a9c-1a82-4ac0-a6fc-2136acef9cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717763035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.2717763035
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.2001182365
Short name T90
Test name
Test status
Simulation time 232816317 ps
CPU time 1.37 seconds
Started Dec 27 12:47:31 PM PST 23
Finished Dec 27 12:47:41 PM PST 23
Peak memory 199212 kb
Host smart-a4cfa89c-412e-4234-b6ad-c7326733f7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001182365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.2001182365
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.3072114331
Short name T403
Test name
Test status
Simulation time 88326576 ps
CPU time 0.77 seconds
Started Dec 27 12:47:52 PM PST 23
Finished Dec 27 12:48:02 PM PST 23
Peak memory 199144 kb
Host smart-3e7f9f52-0681-4c07-839f-8cc4b947e167
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072114331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.3072114331
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.2738109572
Short name T47
Test name
Test status
Simulation time 1228912091 ps
CPU time 5.55 seconds
Started Dec 27 12:47:35 PM PST 23
Finished Dec 27 12:47:54 PM PST 23
Peak memory 216536 kb
Host smart-cda1de8a-44ef-464e-8ac9-e112145cbe8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738109572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.2738109572
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.1604160628
Short name T350
Test name
Test status
Simulation time 244239455 ps
CPU time 1.04 seconds
Started Dec 27 12:47:35 PM PST 23
Finished Dec 27 12:47:46 PM PST 23
Peak memory 216548 kb
Host smart-20093719-70f6-4cfb-89bd-952cd153acae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604160628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.1604160628
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.872289370
Short name T455
Test name
Test status
Simulation time 78104994 ps
CPU time 0.7 seconds
Started Dec 27 12:47:43 PM PST 23
Finished Dec 27 12:47:53 PM PST 23
Peak memory 199140 kb
Host smart-81b9ef84-21b8-42ca-b254-372bb240f038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872289370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.872289370
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.1013674680
Short name T604
Test name
Test status
Simulation time 1012954998 ps
CPU time 4.71 seconds
Started Dec 27 12:47:40 PM PST 23
Finished Dec 27 12:47:55 PM PST 23
Peak memory 199484 kb
Host smart-23ecf984-7607-4cb4-bb16-8775ec991c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013674680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.1013674680
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.495912380
Short name T176
Test name
Test status
Simulation time 141864540 ps
CPU time 1.05 seconds
Started Dec 27 12:47:39 PM PST 23
Finished Dec 27 12:47:51 PM PST 23
Peak memory 199216 kb
Host smart-a4330d5a-0dc2-4ac6-ae37-dcfea70c70f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495912380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.495912380
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.2088168176
Short name T487
Test name
Test status
Simulation time 254160282 ps
CPU time 1.47 seconds
Started Dec 27 12:47:33 PM PST 23
Finished Dec 27 12:47:45 PM PST 23
Peak memory 199456 kb
Host smart-c7cb3261-ca26-47a7-b403-b933f30db8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088168176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.2088168176
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.1669339629
Short name T535
Test name
Test status
Simulation time 6813368019 ps
CPU time 22.91 seconds
Started Dec 27 12:47:35 PM PST 23
Finished Dec 27 12:48:08 PM PST 23
Peak memory 198332 kb
Host smart-636043a8-1f2e-468b-a20b-e6adee94d66c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669339629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.1669339629
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.2437423788
Short name T387
Test name
Test status
Simulation time 132278589 ps
CPU time 1.67 seconds
Started Dec 27 12:47:34 PM PST 23
Finished Dec 27 12:47:46 PM PST 23
Peak memory 199260 kb
Host smart-ee9405f9-420e-4a8a-b101-e507bdd95563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437423788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.2437423788
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.2578842770
Short name T396
Test name
Test status
Simulation time 259071799 ps
CPU time 1.35 seconds
Started Dec 27 12:47:42 PM PST 23
Finished Dec 27 12:47:53 PM PST 23
Peak memory 199264 kb
Host smart-cbc12c94-2bf0-4b90-a1d6-fd36a7b65a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578842770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.2578842770
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.2279336067
Short name T347
Test name
Test status
Simulation time 65247323 ps
CPU time 0.72 seconds
Started Dec 27 12:47:42 PM PST 23
Finished Dec 27 12:47:53 PM PST 23
Peak memory 199072 kb
Host smart-58112868-9f37-440b-8581-5a797e6f1f36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279336067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.2279336067
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.1035412486
Short name T67
Test name
Test status
Simulation time 1223077533 ps
CPU time 5.44 seconds
Started Dec 27 12:47:44 PM PST 23
Finished Dec 27 12:47:59 PM PST 23
Peak memory 221304 kb
Host smart-db34e59e-cf82-45a9-8dff-25ae9876ebf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035412486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.1035412486
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.4146721410
Short name T508
Test name
Test status
Simulation time 243994433 ps
CPU time 1.14 seconds
Started Dec 27 12:47:43 PM PST 23
Finished Dec 27 12:47:54 PM PST 23
Peak memory 216480 kb
Host smart-cabef4ad-fd3d-47b8-b511-a6eeba193420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146721410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.4146721410
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.298724407
Short name T479
Test name
Test status
Simulation time 196817631 ps
CPU time 0.88 seconds
Started Dec 27 12:47:41 PM PST 23
Finished Dec 27 12:47:53 PM PST 23
Peak memory 199076 kb
Host smart-8145bc1a-7d6f-4477-a152-ad43a96654b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298724407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.298724407
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.3606525979
Short name T471
Test name
Test status
Simulation time 726168773 ps
CPU time 3.56 seconds
Started Dec 27 12:47:49 PM PST 23
Finished Dec 27 12:48:01 PM PST 23
Peak memory 199376 kb
Host smart-89c41cd1-0e9c-429a-98fe-b08be2c3197a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606525979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.3606525979
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.1203018439
Short name T317
Test name
Test status
Simulation time 157156455 ps
CPU time 1.08 seconds
Started Dec 27 12:47:45 PM PST 23
Finished Dec 27 12:47:56 PM PST 23
Peak memory 199304 kb
Host smart-c047238e-a12b-421a-a84d-d9b8385032ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203018439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.1203018439
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.2139512417
Short name T489
Test name
Test status
Simulation time 124285737 ps
CPU time 1.13 seconds
Started Dec 27 12:47:42 PM PST 23
Finished Dec 27 12:47:53 PM PST 23
Peak memory 199448 kb
Host smart-fd915f0e-b13b-419a-9a5d-ba3c32fedaa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139512417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.2139512417
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.2110943957
Short name T464
Test name
Test status
Simulation time 143375095 ps
CPU time 1.05 seconds
Started Dec 27 12:47:53 PM PST 23
Finished Dec 27 12:48:04 PM PST 23
Peak memory 199320 kb
Host smart-855f288b-cde8-42a9-9b3d-2392515c3557
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110943957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.2110943957
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.2180541876
Short name T389
Test name
Test status
Simulation time 131775073 ps
CPU time 1.59 seconds
Started Dec 27 12:47:43 PM PST 23
Finished Dec 27 12:47:54 PM PST 23
Peak memory 199172 kb
Host smart-8c1665b9-cd0b-4f9d-9038-e0f0e05dde48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180541876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.2180541876
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.3159280375
Short name T436
Test name
Test status
Simulation time 109784376 ps
CPU time 0.93 seconds
Started Dec 27 12:47:47 PM PST 23
Finished Dec 27 12:47:57 PM PST 23
Peak memory 199308 kb
Host smart-f857f2c3-8dc9-4ca7-9465-92edd4c6a722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159280375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.3159280375
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.862680284
Short name T529
Test name
Test status
Simulation time 57815906 ps
CPU time 0.77 seconds
Started Dec 27 12:46:59 PM PST 23
Finished Dec 27 12:47:17 PM PST 23
Peak memory 199056 kb
Host smart-b111e423-7924-4512-a4f7-90a650d44994
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862680284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.862680284
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.2407916255
Short name T598
Test name
Test status
Simulation time 2393457265 ps
CPU time 7.56 seconds
Started Dec 27 12:46:56 PM PST 23
Finished Dec 27 12:47:22 PM PST 23
Peak memory 220952 kb
Host smart-812e32f5-7697-462a-9105-056686ee0c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407916255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.2407916255
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.1687534209
Short name T539
Test name
Test status
Simulation time 244278448 ps
CPU time 1.21 seconds
Started Dec 27 12:46:58 PM PST 23
Finished Dec 27 12:47:17 PM PST 23
Peak memory 216516 kb
Host smart-d22713fe-e24e-4127-8dbc-7ef19c199b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687534209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.1687534209
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.3649117260
Short name T18
Test name
Test status
Simulation time 127618217 ps
CPU time 0.81 seconds
Started Dec 27 12:46:54 PM PST 23
Finished Dec 27 12:47:14 PM PST 23
Peak memory 199124 kb
Host smart-be066a45-7c71-4486-85ff-934f4a228af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649117260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.3649117260
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.3785843241
Short name T610
Test name
Test status
Simulation time 1722128734 ps
CPU time 6.83 seconds
Started Dec 27 12:46:52 PM PST 23
Finished Dec 27 12:47:19 PM PST 23
Peak memory 199520 kb
Host smart-daacef78-288a-4f6d-99eb-ebb232065720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785843241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.3785843241
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.59948533
Short name T86
Test name
Test status
Simulation time 8440980777 ps
CPU time 12.38 seconds
Started Dec 27 12:47:00 PM PST 23
Finished Dec 27 12:47:29 PM PST 23
Peak memory 216172 kb
Host smart-521b3c0e-dbcb-4be1-b785-5fff81ea914d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59948533 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.59948533
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.3257953836
Short name T546
Test name
Test status
Simulation time 184358553 ps
CPU time 1.23 seconds
Started Dec 27 12:46:54 PM PST 23
Finished Dec 27 12:47:14 PM PST 23
Peak memory 199264 kb
Host smart-be6453e5-e9f9-4ebe-9315-4260f177105d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257953836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.3257953836
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.819244296
Short name T553
Test name
Test status
Simulation time 240331148 ps
CPU time 1.48 seconds
Started Dec 27 12:46:55 PM PST 23
Finished Dec 27 12:47:15 PM PST 23
Peak memory 199468 kb
Host smart-fd753699-20d6-4c2a-a119-d8e5b086ba78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819244296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.819244296
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.227870294
Short name T62
Test name
Test status
Simulation time 9987893022 ps
CPU time 35.04 seconds
Started Dec 27 12:46:58 PM PST 23
Finished Dec 27 12:47:51 PM PST 23
Peak memory 199484 kb
Host smart-eca4d65c-0176-4127-9521-2adaa6e63ac8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227870294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.227870294
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.2467322363
Short name T69
Test name
Test status
Simulation time 273118164 ps
CPU time 1.87 seconds
Started Dec 27 12:46:55 PM PST 23
Finished Dec 27 12:47:15 PM PST 23
Peak memory 199224 kb
Host smart-be9777df-56df-47fa-87cf-606d0328f486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467322363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.2467322363
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.3026771124
Short name T352
Test name
Test status
Simulation time 130908891 ps
CPU time 1.08 seconds
Started Dec 27 12:46:54 PM PST 23
Finished Dec 27 12:47:14 PM PST 23
Peak memory 199340 kb
Host smart-34b5e574-db5d-4c7f-bfcd-2c58ab2a2244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026771124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.3026771124
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.3102561625
Short name T358
Test name
Test status
Simulation time 53204443 ps
CPU time 0.68 seconds
Started Dec 27 12:47:50 PM PST 23
Finished Dec 27 12:47:59 PM PST 23
Peak memory 199032 kb
Host smart-c7eb26f2-8d6a-4e9e-bff1-1bc71c05666b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102561625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.3102561625
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.1360845177
Short name T514
Test name
Test status
Simulation time 1900050571 ps
CPU time 7.23 seconds
Started Dec 27 12:47:49 PM PST 23
Finished Dec 27 12:48:05 PM PST 23
Peak memory 217280 kb
Host smart-b9d40777-3d9f-4e90-bf95-834037e8a73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360845177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.1360845177
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.1296223549
Short name T576
Test name
Test status
Simulation time 244780148 ps
CPU time 1.06 seconds
Started Dec 27 12:47:52 PM PST 23
Finished Dec 27 12:48:04 PM PST 23
Peak memory 216388 kb
Host smart-a5c0da87-4f2b-427c-b898-e78340652b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296223549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.1296223549
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.1996813259
Short name T279
Test name
Test status
Simulation time 212233366 ps
CPU time 0.89 seconds
Started Dec 27 12:47:56 PM PST 23
Finished Dec 27 12:48:06 PM PST 23
Peak memory 199092 kb
Host smart-38a0c16e-bf92-49bf-9443-ceaae324d1d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996813259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.1996813259
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.2273904303
Short name T501
Test name
Test status
Simulation time 758622297 ps
CPU time 4.12 seconds
Started Dec 27 12:47:32 PM PST 23
Finished Dec 27 12:47:46 PM PST 23
Peak memory 199412 kb
Host smart-fa6aeaec-6783-4a41-ba0a-a7c1418e2f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273904303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.2273904303
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.3830282784
Short name T40
Test name
Test status
Simulation time 168862796 ps
CPU time 1.13 seconds
Started Dec 27 12:47:47 PM PST 23
Finished Dec 27 12:47:58 PM PST 23
Peak memory 199352 kb
Host smart-2af8a925-28da-4f1c-8adb-7c3fccd090e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830282784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.3830282784
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.596106653
Short name T492
Test name
Test status
Simulation time 118791457 ps
CPU time 1.18 seconds
Started Dec 27 12:47:56 PM PST 23
Finished Dec 27 12:48:07 PM PST 23
Peak memory 199376 kb
Host smart-765f3b02-acff-4a81-963a-6c08c1ef2e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596106653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.596106653
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.3404141143
Short name T608
Test name
Test status
Simulation time 3942762624 ps
CPU time 16.39 seconds
Started Dec 27 12:47:57 PM PST 23
Finished Dec 27 12:48:24 PM PST 23
Peak memory 199532 kb
Host smart-014be606-158c-43c8-aafb-5eeb5bdf9b0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404141143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.3404141143
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.2028760461
Short name T353
Test name
Test status
Simulation time 289708332 ps
CPU time 1.92 seconds
Started Dec 27 12:47:41 PM PST 23
Finished Dec 27 12:47:53 PM PST 23
Peak memory 199256 kb
Host smart-c5887f50-33d8-4a44-b5ce-b8123e27add4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028760461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.2028760461
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.1841010499
Short name T454
Test name
Test status
Simulation time 95997141 ps
CPU time 0.86 seconds
Started Dec 27 12:47:55 PM PST 23
Finished Dec 27 12:48:05 PM PST 23
Peak memory 199224 kb
Host smart-d4c70127-67a0-4a81-8dd6-14fe4dbd7b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841010499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.1841010499
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.4194691604
Short name T37
Test name
Test status
Simulation time 61569916 ps
CPU time 0.7 seconds
Started Dec 27 12:47:36 PM PST 23
Finished Dec 27 12:47:47 PM PST 23
Peak memory 199024 kb
Host smart-099796e9-48c7-48cc-a4f5-61de6b72e27b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194691604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.4194691604
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.3459777033
Short name T431
Test name
Test status
Simulation time 244361519 ps
CPU time 1.03 seconds
Started Dec 27 12:47:31 PM PST 23
Finished Dec 27 12:47:41 PM PST 23
Peak memory 216348 kb
Host smart-60be0684-6926-4c5f-bc8d-bfdd3862d67c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459777033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.3459777033
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.2678310919
Short name T368
Test name
Test status
Simulation time 236859912 ps
CPU time 0.89 seconds
Started Dec 27 12:47:41 PM PST 23
Finished Dec 27 12:47:53 PM PST 23
Peak memory 199060 kb
Host smart-d9304002-f821-4dc3-ad3c-897f34606a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678310919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.2678310919
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.900347537
Short name T429
Test name
Test status
Simulation time 930040548 ps
CPU time 4.65 seconds
Started Dec 27 12:48:02 PM PST 23
Finished Dec 27 12:48:16 PM PST 23
Peak memory 199436 kb
Host smart-51042026-f49f-43f7-a6fe-2f632cdf3a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900347537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.900347537
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.2065024313
Short name T146
Test name
Test status
Simulation time 150778226 ps
CPU time 1.1 seconds
Started Dec 27 12:47:30 PM PST 23
Finished Dec 27 12:47:40 PM PST 23
Peak memory 199240 kb
Host smart-b27cef56-376c-4725-b317-cf4effff4f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065024313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.2065024313
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.2313738773
Short name T599
Test name
Test status
Simulation time 190619129 ps
CPU time 1.3 seconds
Started Dec 27 12:47:58 PM PST 23
Finished Dec 27 12:48:10 PM PST 23
Peak memory 199396 kb
Host smart-dc5c238f-514b-4445-a38b-4ba4649da467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313738773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.2313738773
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.3936065799
Short name T552
Test name
Test status
Simulation time 4294190339 ps
CPU time 16.49 seconds
Started Dec 27 12:47:30 PM PST 23
Finished Dec 27 12:47:55 PM PST 23
Peak memory 199516 kb
Host smart-7bae49bf-1dd5-4ddc-b63a-3ca767202beb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936065799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.3936065799
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.511542244
Short name T601
Test name
Test status
Simulation time 295316010 ps
CPU time 1.87 seconds
Started Dec 27 12:47:48 PM PST 23
Finished Dec 27 12:47:59 PM PST 23
Peak memory 199176 kb
Host smart-f0de26ce-441a-4584-9193-8a33057d46cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511542244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.511542244
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.353860391
Short name T462
Test name
Test status
Simulation time 146822354 ps
CPU time 1.06 seconds
Started Dec 27 12:48:03 PM PST 23
Finished Dec 27 12:48:13 PM PST 23
Peak memory 199276 kb
Host smart-f752008e-ce50-454e-bade-98ed918e3b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353860391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.353860391
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.615394614
Short name T348
Test name
Test status
Simulation time 80954509 ps
CPU time 0.83 seconds
Started Dec 27 12:47:32 PM PST 23
Finished Dec 27 12:47:42 PM PST 23
Peak memory 199164 kb
Host smart-6a67499b-deb6-48bc-a311-dbc24e83de9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615394614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.615394614
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.641211863
Short name T443
Test name
Test status
Simulation time 2363331750 ps
CPU time 8 seconds
Started Dec 27 12:47:33 PM PST 23
Finished Dec 27 12:47:51 PM PST 23
Peak memory 220588 kb
Host smart-608ca5af-bc95-4b9b-a5b5-ac3771be6bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641211863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.641211863
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.3366378190
Short name T159
Test name
Test status
Simulation time 244535947 ps
CPU time 1.13 seconds
Started Dec 27 12:47:32 PM PST 23
Finished Dec 27 12:47:42 PM PST 23
Peak memory 216576 kb
Host smart-6c35deb6-8d7c-4df0-bc62-575bf9af6578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366378190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.3366378190
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.3047820774
Short name T16
Test name
Test status
Simulation time 147037258 ps
CPU time 0.86 seconds
Started Dec 27 12:47:31 PM PST 23
Finished Dec 27 12:47:41 PM PST 23
Peak memory 199072 kb
Host smart-e5484f7a-7a33-4b63-85a4-e0094abc0298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047820774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.3047820774
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.1176907992
Short name T377
Test name
Test status
Simulation time 1700965867 ps
CPU time 6.24 seconds
Started Dec 27 12:47:30 PM PST 23
Finished Dec 27 12:47:45 PM PST 23
Peak memory 199452 kb
Host smart-58976568-006a-4687-987f-4a03ae831321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176907992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.1176907992
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.2637958213
Short name T71
Test name
Test status
Simulation time 99156283 ps
CPU time 0.97 seconds
Started Dec 27 12:47:31 PM PST 23
Finished Dec 27 12:47:41 PM PST 23
Peak memory 199320 kb
Host smart-b581b5c3-31df-4af3-8de7-3b97c86dbbd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637958213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.2637958213
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.1142642622
Short name T5
Test name
Test status
Simulation time 241709179 ps
CPU time 1.39 seconds
Started Dec 27 12:47:29 PM PST 23
Finished Dec 27 12:47:40 PM PST 23
Peak memory 199392 kb
Host smart-e346e2c5-f071-4cf9-bcae-ed0f546f4c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142642622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.1142642622
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.1012546418
Short name T383
Test name
Test status
Simulation time 3505930829 ps
CPU time 14.77 seconds
Started Dec 27 12:47:31 PM PST 23
Finished Dec 27 12:47:54 PM PST 23
Peak memory 199464 kb
Host smart-05577a9e-a33a-4c47-ad31-3f27b2c3c14a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012546418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.1012546418
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.867985816
Short name T12
Test name
Test status
Simulation time 335690945 ps
CPU time 2.23 seconds
Started Dec 27 12:47:32 PM PST 23
Finished Dec 27 12:47:44 PM PST 23
Peak memory 199248 kb
Host smart-77b88f1b-7e4f-4a4a-a763-0fd37931043f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867985816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.867985816
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.43187555
Short name T283
Test name
Test status
Simulation time 250541896 ps
CPU time 1.41 seconds
Started Dec 27 12:47:31 PM PST 23
Finished Dec 27 12:47:41 PM PST 23
Peak memory 199416 kb
Host smart-3bb7f8a8-8c36-4b5f-b3de-a6ecf79a2db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43187555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.43187555
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.117532492
Short name T448
Test name
Test status
Simulation time 73522965 ps
CPU time 0.73 seconds
Started Dec 27 12:47:32 PM PST 23
Finished Dec 27 12:47:42 PM PST 23
Peak memory 199112 kb
Host smart-a8834f2f-83c5-40e8-b91b-09a67d705b54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117532492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.117532492
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.2762010541
Short name T540
Test name
Test status
Simulation time 1229406186 ps
CPU time 5.66 seconds
Started Dec 27 12:47:33 PM PST 23
Finished Dec 27 12:47:55 PM PST 23
Peak memory 216672 kb
Host smart-00d89d8e-3899-4415-9993-d7af18c1317a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762010541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.2762010541
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.3042653643
Short name T64
Test name
Test status
Simulation time 245443410 ps
CPU time 1.09 seconds
Started Dec 27 12:47:31 PM PST 23
Finished Dec 27 12:47:41 PM PST 23
Peak memory 216484 kb
Host smart-83f22721-4b19-4ed5-a800-521dfd7cdd3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042653643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.3042653643
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.784409174
Short name T525
Test name
Test status
Simulation time 127740040 ps
CPU time 0.78 seconds
Started Dec 27 12:47:30 PM PST 23
Finished Dec 27 12:47:40 PM PST 23
Peak memory 199044 kb
Host smart-34c610da-8e78-4ae6-8eb2-668c3f75137e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784409174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.784409174
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.2476734741
Short name T538
Test name
Test status
Simulation time 760461029 ps
CPU time 3.75 seconds
Started Dec 27 12:47:34 PM PST 23
Finished Dec 27 12:47:48 PM PST 23
Peak memory 199324 kb
Host smart-6e73aac7-9d35-45ff-a7cd-1cea1da17021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476734741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.2476734741
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.3558693413
Short name T270
Test name
Test status
Simulation time 110946678 ps
CPU time 1.01 seconds
Started Dec 27 12:47:35 PM PST 23
Finished Dec 27 12:47:46 PM PST 23
Peak memory 199272 kb
Host smart-2dc11d11-1c6f-4ce9-a6b3-e8551388b3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558693413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.3558693413
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.1598762774
Short name T158
Test name
Test status
Simulation time 196574118 ps
CPU time 1.33 seconds
Started Dec 27 12:47:32 PM PST 23
Finished Dec 27 12:47:43 PM PST 23
Peak memory 199432 kb
Host smart-105c59c4-dc34-4583-8d0d-ad0e2552e95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598762774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.1598762774
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.3632847396
Short name T382
Test name
Test status
Simulation time 10777570735 ps
CPU time 35.62 seconds
Started Dec 27 12:47:33 PM PST 23
Finished Dec 27 12:48:19 PM PST 23
Peak memory 199528 kb
Host smart-a883e0b1-710f-4ac7-906f-9d315f67684b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632847396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.3632847396
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.4189541139
Short name T346
Test name
Test status
Simulation time 137064155 ps
CPU time 1.52 seconds
Started Dec 27 12:47:32 PM PST 23
Finished Dec 27 12:47:50 PM PST 23
Peak memory 199112 kb
Host smart-0069040c-6401-4c93-b92f-331e3009ef7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189541139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.4189541139
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.587502303
Short name T149
Test name
Test status
Simulation time 171398214 ps
CPU time 1.2 seconds
Started Dec 27 12:47:32 PM PST 23
Finished Dec 27 12:47:42 PM PST 23
Peak memory 199484 kb
Host smart-3c3a7261-3929-4ae7-8493-5a322a076677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587502303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.587502303
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.2825683141
Short name T333
Test name
Test status
Simulation time 69944829 ps
CPU time 0.7 seconds
Started Dec 27 12:47:34 PM PST 23
Finished Dec 27 12:47:44 PM PST 23
Peak memory 198988 kb
Host smart-6db45dfb-6f38-4432-863e-5ffa5b124255
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825683141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.2825683141
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.1240175344
Short name T28
Test name
Test status
Simulation time 2344758662 ps
CPU time 8.07 seconds
Started Dec 27 12:47:32 PM PST 23
Finished Dec 27 12:47:50 PM PST 23
Peak memory 216364 kb
Host smart-2b7802d4-3853-4feb-b7c4-ce046004f3c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240175344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.1240175344
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.2952686504
Short name T307
Test name
Test status
Simulation time 245740443 ps
CPU time 1.12 seconds
Started Dec 27 12:47:30 PM PST 23
Finished Dec 27 12:47:40 PM PST 23
Peak memory 216468 kb
Host smart-aa8407cd-243c-4c2b-9eb8-13e0f3b9a40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952686504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.2952686504
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.1830575049
Short name T502
Test name
Test status
Simulation time 85946580 ps
CPU time 0.72 seconds
Started Dec 27 12:47:30 PM PST 23
Finished Dec 27 12:47:40 PM PST 23
Peak memory 199112 kb
Host smart-4046de1f-e35c-4469-9aa4-deeaf30f7fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830575049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.1830575049
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.3967086172
Short name T364
Test name
Test status
Simulation time 701738285 ps
CPU time 3.56 seconds
Started Dec 27 12:47:33 PM PST 23
Finished Dec 27 12:47:47 PM PST 23
Peak memory 199360 kb
Host smart-a407fbe7-675d-420a-b933-f253c450b849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967086172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.3967086172
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.3965378358
Short name T329
Test name
Test status
Simulation time 101244213 ps
CPU time 0.96 seconds
Started Dec 27 12:47:32 PM PST 23
Finished Dec 27 12:47:43 PM PST 23
Peak memory 199376 kb
Host smart-40cdd2e9-cf39-4347-9924-2ff3cb49daf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965378358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.3965378358
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.1626258494
Short name T275
Test name
Test status
Simulation time 203865932 ps
CPU time 1.4 seconds
Started Dec 27 12:47:31 PM PST 23
Finished Dec 27 12:47:41 PM PST 23
Peak memory 199384 kb
Host smart-f44659b9-740d-4775-9d37-cd6ecb37051e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626258494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.1626258494
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.1567017667
Short name T330
Test name
Test status
Simulation time 8031017697 ps
CPU time 27.81 seconds
Started Dec 27 12:47:33 PM PST 23
Finished Dec 27 12:48:10 PM PST 23
Peak memory 199320 kb
Host smart-67de4b5c-27ec-4da0-9d48-a0d39c449f93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567017667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.1567017667
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.1650728999
Short name T152
Test name
Test status
Simulation time 288524386 ps
CPU time 1.81 seconds
Started Dec 27 12:47:31 PM PST 23
Finished Dec 27 12:47:42 PM PST 23
Peak memory 199264 kb
Host smart-a86718ef-d581-4b86-a1da-6aa6c127061a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650728999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.1650728999
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.23726113
Short name T484
Test name
Test status
Simulation time 204274701 ps
CPU time 1.25 seconds
Started Dec 27 12:47:32 PM PST 23
Finished Dec 27 12:47:42 PM PST 23
Peak memory 199228 kb
Host smart-31c53684-cbdf-4a6a-b21f-3063643182dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23726113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.23726113
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.161112158
Short name T342
Test name
Test status
Simulation time 54693720 ps
CPU time 0.67 seconds
Started Dec 27 12:47:32 PM PST 23
Finished Dec 27 12:47:42 PM PST 23
Peak memory 199052 kb
Host smart-72ac40b9-1162-4562-a1d8-7c108c7e7694
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161112158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.161112158
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.582131009
Short name T463
Test name
Test status
Simulation time 1222300281 ps
CPU time 5.38 seconds
Started Dec 27 12:47:35 PM PST 23
Finished Dec 27 12:47:50 PM PST 23
Peak memory 220896 kb
Host smart-0978e49d-b727-4395-99fa-4c0dfe2421b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582131009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.582131009
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.3240479808
Short name T415
Test name
Test status
Simulation time 244076859 ps
CPU time 1.06 seconds
Started Dec 27 12:47:44 PM PST 23
Finished Dec 27 12:47:56 PM PST 23
Peak memory 216420 kb
Host smart-2aefd991-4dad-4b5e-af40-3c08febeeb5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240479808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.3240479808
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.801342645
Short name T510
Test name
Test status
Simulation time 106365318 ps
CPU time 0.74 seconds
Started Dec 27 12:47:35 PM PST 23
Finished Dec 27 12:47:45 PM PST 23
Peak memory 199012 kb
Host smart-17e9e85b-2ea7-4429-a33d-839dd5c207ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801342645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.801342645
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.1181361420
Short name T24
Test name
Test status
Simulation time 1569207799 ps
CPU time 6.17 seconds
Started Dec 27 12:47:36 PM PST 23
Finished Dec 27 12:47:52 PM PST 23
Peak memory 199384 kb
Host smart-68f51d0b-6915-4a5a-a299-58e77057f6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181361420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.1181361420
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.1178632141
Short name T478
Test name
Test status
Simulation time 176821465 ps
CPU time 1.2 seconds
Started Dec 27 12:47:41 PM PST 23
Finished Dec 27 12:47:52 PM PST 23
Peak memory 199268 kb
Host smart-c365aa9a-cb73-4b21-b7fa-060611d646f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178632141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.1178632141
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.3986653479
Short name T93
Test name
Test status
Simulation time 232273686 ps
CPU time 1.33 seconds
Started Dec 27 12:47:31 PM PST 23
Finished Dec 27 12:47:41 PM PST 23
Peak memory 199372 kb
Host smart-ed1c2fc0-e46f-4f98-91ae-597d5b9e1931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986653479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.3986653479
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.990864537
Short name T466
Test name
Test status
Simulation time 17667419265 ps
CPU time 59.46 seconds
Started Dec 27 12:47:41 PM PST 23
Finished Dec 27 12:48:51 PM PST 23
Peak memory 199520 kb
Host smart-9ba30485-af8d-416a-9726-2c6f58478080
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990864537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.990864537
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.1506055871
Short name T567
Test name
Test status
Simulation time 474042542 ps
CPU time 2.71 seconds
Started Dec 27 12:47:42 PM PST 23
Finished Dec 27 12:47:54 PM PST 23
Peak memory 199204 kb
Host smart-3cb7c815-98ba-40ff-bb80-bab615cd3dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506055871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.1506055871
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.3205714479
Short name T292
Test name
Test status
Simulation time 62564772 ps
CPU time 0.72 seconds
Started Dec 27 12:47:42 PM PST 23
Finished Dec 27 12:47:53 PM PST 23
Peak memory 199256 kb
Host smart-e96649db-bd2e-4a0a-90b6-b115f5366886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205714479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.3205714479
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.4285433742
Short name T336
Test name
Test status
Simulation time 66371955 ps
CPU time 0.7 seconds
Started Dec 27 12:47:33 PM PST 23
Finished Dec 27 12:47:43 PM PST 23
Peak memory 199048 kb
Host smart-a3c8f3d1-4420-447b-80e9-77354297ff5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285433742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.4285433742
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.1901726412
Short name T507
Test name
Test status
Simulation time 2355014263 ps
CPU time 9.39 seconds
Started Dec 27 12:47:35 PM PST 23
Finished Dec 27 12:47:54 PM PST 23
Peak memory 218104 kb
Host smart-b870d806-26dc-48e7-804c-9c909b7d622f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901726412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.1901726412
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.3165640608
Short name T560
Test name
Test status
Simulation time 243859439 ps
CPU time 1.14 seconds
Started Dec 27 12:47:40 PM PST 23
Finished Dec 27 12:47:52 PM PST 23
Peak memory 216408 kb
Host smart-5e5bfe16-8e22-4b86-affa-a9a65c776003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165640608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.3165640608
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.3429833941
Short name T119
Test name
Test status
Simulation time 165162739 ps
CPU time 0.83 seconds
Started Dec 27 12:47:42 PM PST 23
Finished Dec 27 12:47:53 PM PST 23
Peak memory 199120 kb
Host smart-df2904a3-fb1d-4b9f-ae74-2411bced4126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429833941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.3429833941
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.3743167534
Short name T474
Test name
Test status
Simulation time 686293457 ps
CPU time 3.98 seconds
Started Dec 27 12:47:38 PM PST 23
Finished Dec 27 12:47:54 PM PST 23
Peak memory 199420 kb
Host smart-4ddca97e-d978-46f9-9c85-979abbe2b6b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743167534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.3743167534
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.1443948267
Short name T506
Test name
Test status
Simulation time 101355008 ps
CPU time 0.93 seconds
Started Dec 27 12:47:35 PM PST 23
Finished Dec 27 12:47:46 PM PST 23
Peak memory 199352 kb
Host smart-a88c0dd9-b127-4c40-a023-a68bc01197d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443948267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.1443948267
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.2960055571
Short name T276
Test name
Test status
Simulation time 248121993 ps
CPU time 1.46 seconds
Started Dec 27 12:47:36 PM PST 23
Finished Dec 27 12:47:53 PM PST 23
Peak memory 199412 kb
Host smart-d9a236b5-826d-4df5-87ed-9240f47d6150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960055571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.2960055571
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.2957340187
Short name T284
Test name
Test status
Simulation time 390249917 ps
CPU time 2.09 seconds
Started Dec 27 12:47:36 PM PST 23
Finished Dec 27 12:47:48 PM PST 23
Peak memory 199464 kb
Host smart-b62ecfc5-8de7-477d-a166-1bd406899706
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957340187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.2957340187
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.2042687242
Short name T413
Test name
Test status
Simulation time 434494657 ps
CPU time 2.28 seconds
Started Dec 27 12:47:33 PM PST 23
Finished Dec 27 12:47:45 PM PST 23
Peak memory 199216 kb
Host smart-2336afbd-e8aa-471a-99c4-46cf19c91a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042687242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.2042687242
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.2379501337
Short name T298
Test name
Test status
Simulation time 84825052 ps
CPU time 0.82 seconds
Started Dec 27 12:47:39 PM PST 23
Finished Dec 27 12:47:51 PM PST 23
Peak memory 199332 kb
Host smart-3bb9e1cd-1cae-41f1-b51e-6194fd129006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379501337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.2379501337
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.1222664842
Short name T328
Test name
Test status
Simulation time 88662361 ps
CPU time 0.78 seconds
Started Dec 27 12:47:39 PM PST 23
Finished Dec 27 12:47:51 PM PST 23
Peak memory 199084 kb
Host smart-d3e25f05-0666-43ef-9da9-f5cb6ddc2bbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222664842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.1222664842
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.2383448582
Short name T583
Test name
Test status
Simulation time 1225841597 ps
CPU time 5.5 seconds
Started Dec 27 12:47:42 PM PST 23
Finished Dec 27 12:47:57 PM PST 23
Peak memory 216692 kb
Host smart-6dd6d8c4-8c85-40c9-91d0-c332ed7c7271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383448582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.2383448582
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.3743103904
Short name T288
Test name
Test status
Simulation time 245334335 ps
CPU time 1.04 seconds
Started Dec 27 12:47:39 PM PST 23
Finished Dec 27 12:47:51 PM PST 23
Peak memory 216496 kb
Host smart-093d02f1-c0ef-4445-80e1-209c58aaf7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743103904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.3743103904
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.2956199909
Short name T357
Test name
Test status
Simulation time 192989108 ps
CPU time 0.86 seconds
Started Dec 27 12:47:46 PM PST 23
Finished Dec 27 12:47:57 PM PST 23
Peak memory 199156 kb
Host smart-b832598c-fd4f-4344-86d0-861f434c075d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956199909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.2956199909
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.2987081613
Short name T595
Test name
Test status
Simulation time 1576008143 ps
CPU time 6.05 seconds
Started Dec 27 12:47:42 PM PST 23
Finished Dec 27 12:47:58 PM PST 23
Peak memory 199336 kb
Host smart-1760f076-f2a6-41dd-a815-635546c4c11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987081613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.2987081613
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.4084456918
Short name T363
Test name
Test status
Simulation time 173612181 ps
CPU time 1.27 seconds
Started Dec 27 12:47:40 PM PST 23
Finished Dec 27 12:47:52 PM PST 23
Peak memory 199264 kb
Host smart-d822fec5-52d3-4a51-bed1-cfcc8219f82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084456918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.4084456918
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.1508021829
Short name T326
Test name
Test status
Simulation time 118915978 ps
CPU time 1.16 seconds
Started Dec 27 12:47:36 PM PST 23
Finished Dec 27 12:47:48 PM PST 23
Peak memory 199412 kb
Host smart-972e0755-b4a1-4f46-a3d7-5c5bb6d74d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508021829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.1508021829
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.1060556025
Short name T91
Test name
Test status
Simulation time 170483394 ps
CPU time 1.5 seconds
Started Dec 27 12:47:34 PM PST 23
Finished Dec 27 12:47:46 PM PST 23
Peak memory 199424 kb
Host smart-08873faa-43d2-4025-9224-81fc6d47843e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060556025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.1060556025
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.2336774535
Short name T402
Test name
Test status
Simulation time 337370972 ps
CPU time 2.1 seconds
Started Dec 27 12:47:39 PM PST 23
Finished Dec 27 12:47:53 PM PST 23
Peak memory 199336 kb
Host smart-a0938ab0-69fd-47dd-9bd2-3adeb4827d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336774535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.2336774535
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.1140545134
Short name T405
Test name
Test status
Simulation time 144692357 ps
CPU time 0.99 seconds
Started Dec 27 12:47:42 PM PST 23
Finished Dec 27 12:47:53 PM PST 23
Peak memory 199288 kb
Host smart-c27f9ecb-a50e-4b2d-b6b0-957928e10b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140545134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.1140545134
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.2942366294
Short name T541
Test name
Test status
Simulation time 65862843 ps
CPU time 0.72 seconds
Started Dec 27 12:47:37 PM PST 23
Finished Dec 27 12:47:47 PM PST 23
Peak memory 199120 kb
Host smart-4577edd0-4b07-4ebf-8df3-3b10d814a7a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942366294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.2942366294
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.1162759287
Short name T565
Test name
Test status
Simulation time 1898055283 ps
CPU time 6.84 seconds
Started Dec 27 12:47:40 PM PST 23
Finished Dec 27 12:47:57 PM PST 23
Peak memory 216652 kb
Host smart-816645d3-667f-4d9d-8417-571277e02d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162759287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.1162759287
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.3956622340
Short name T419
Test name
Test status
Simulation time 243916349 ps
CPU time 1.04 seconds
Started Dec 27 12:47:35 PM PST 23
Finished Dec 27 12:47:46 PM PST 23
Peak memory 216548 kb
Host smart-aa7b6f82-2a23-4cd8-a833-33a9e26045e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956622340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.3956622340
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.2327281428
Short name T370
Test name
Test status
Simulation time 80360929 ps
CPU time 0.7 seconds
Started Dec 27 12:47:40 PM PST 23
Finished Dec 27 12:47:51 PM PST 23
Peak memory 199140 kb
Host smart-fd38ed01-0392-467f-90e1-2abe934e9ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327281428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.2327281428
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.4177163237
Short name T116
Test name
Test status
Simulation time 1512454598 ps
CPU time 5.49 seconds
Started Dec 27 12:47:44 PM PST 23
Finished Dec 27 12:48:00 PM PST 23
Peak memory 199408 kb
Host smart-e1d836d9-ad89-4434-b6c6-26e60c31c2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177163237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.4177163237
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.383318431
Short name T456
Test name
Test status
Simulation time 180150198 ps
CPU time 1.21 seconds
Started Dec 27 12:47:33 PM PST 23
Finished Dec 27 12:47:44 PM PST 23
Peak memory 199304 kb
Host smart-6c1c9b3c-b8b6-4290-90ef-cf11334ac83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383318431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.383318431
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.864598777
Short name T532
Test name
Test status
Simulation time 118658747 ps
CPU time 1.15 seconds
Started Dec 27 12:47:42 PM PST 23
Finished Dec 27 12:47:53 PM PST 23
Peak memory 199468 kb
Host smart-64c253d9-f3af-4be8-bd16-c36298022bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864598777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.864598777
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.965293141
Short name T531
Test name
Test status
Simulation time 10382062961 ps
CPU time 36.68 seconds
Started Dec 27 12:47:39 PM PST 23
Finished Dec 27 12:48:27 PM PST 23
Peak memory 199472 kb
Host smart-777d07fb-e62f-49f9-9fc6-a7e3a3acdaa2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965293141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.965293141
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.2504366864
Short name T493
Test name
Test status
Simulation time 329613506 ps
CPU time 2.21 seconds
Started Dec 27 12:47:37 PM PST 23
Finished Dec 27 12:47:50 PM PST 23
Peak memory 199288 kb
Host smart-cf28fb0d-e156-4a19-8bd0-b997487454ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504366864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.2504366864
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.1237734283
Short name T258
Test name
Test status
Simulation time 131957747 ps
CPU time 0.98 seconds
Started Dec 27 12:47:42 PM PST 23
Finished Dec 27 12:47:53 PM PST 23
Peak memory 199276 kb
Host smart-765da594-f37a-4dbe-90f5-a72d22bf5cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237734283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.1237734283
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.3954807963
Short name T285
Test name
Test status
Simulation time 103105323 ps
CPU time 0.95 seconds
Started Dec 27 12:47:52 PM PST 23
Finished Dec 27 12:48:03 PM PST 23
Peak memory 199092 kb
Host smart-700e67fb-3373-499c-b62d-bff5a32b34c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954807963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.3954807963
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.3568754551
Short name T57
Test name
Test status
Simulation time 1227373730 ps
CPU time 5.64 seconds
Started Dec 27 12:47:42 PM PST 23
Finished Dec 27 12:47:58 PM PST 23
Peak memory 221252 kb
Host smart-7026e891-7695-45c5-b889-ea12416d5ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568754551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.3568754551
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.3660591002
Short name T314
Test name
Test status
Simulation time 243858804 ps
CPU time 1.14 seconds
Started Dec 27 12:47:41 PM PST 23
Finished Dec 27 12:47:52 PM PST 23
Peak memory 216452 kb
Host smart-7ce43cd8-b9a0-4fb2-be3e-d9111ab40506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660591002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.3660591002
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.4006838747
Short name T20
Test name
Test status
Simulation time 153190636 ps
CPU time 0.85 seconds
Started Dec 27 12:47:41 PM PST 23
Finished Dec 27 12:47:52 PM PST 23
Peak memory 199060 kb
Host smart-04110c85-b7be-4b52-98bf-cf1ad0fe153d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006838747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.4006838747
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.2003660916
Short name T380
Test name
Test status
Simulation time 1085626508 ps
CPU time 5.3 seconds
Started Dec 27 12:47:35 PM PST 23
Finished Dec 27 12:47:53 PM PST 23
Peak memory 199420 kb
Host smart-611e7c3f-f9be-404a-84c7-14b4748c9860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003660916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.2003660916
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.1235281516
Short name T417
Test name
Test status
Simulation time 154367464 ps
CPU time 1.1 seconds
Started Dec 27 12:47:38 PM PST 23
Finished Dec 27 12:47:50 PM PST 23
Peak memory 199332 kb
Host smart-56a8dcf3-b6ce-43d9-b13e-d768b24cd067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235281516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.1235281516
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.603657049
Short name T427
Test name
Test status
Simulation time 109440905 ps
CPU time 1.17 seconds
Started Dec 27 12:47:34 PM PST 23
Finished Dec 27 12:47:46 PM PST 23
Peak memory 199424 kb
Host smart-50068337-e065-4f59-9d22-ba745f6a9550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603657049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.603657049
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.3781443552
Short name T590
Test name
Test status
Simulation time 7287638460 ps
CPU time 34.08 seconds
Started Dec 27 12:47:41 PM PST 23
Finished Dec 27 12:48:26 PM PST 23
Peak memory 199500 kb
Host smart-895f18ed-4d4c-4ae2-bb86-21878e9e8492
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781443552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.3781443552
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.2936540794
Short name T68
Test name
Test status
Simulation time 116995559 ps
CPU time 1.49 seconds
Started Dec 27 12:47:41 PM PST 23
Finished Dec 27 12:47:53 PM PST 23
Peak memory 199284 kb
Host smart-f1508d0a-89e3-4dc7-b411-00fd42b12d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936540794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.2936540794
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.3019669780
Short name T25
Test name
Test status
Simulation time 161739382 ps
CPU time 1.18 seconds
Started Dec 27 12:47:34 PM PST 23
Finished Dec 27 12:47:45 PM PST 23
Peak memory 199332 kb
Host smart-5ac5367d-9308-44f4-aa1f-f18a48ae2121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019669780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.3019669780
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.3219744178
Short name T335
Test name
Test status
Simulation time 63699865 ps
CPU time 0.71 seconds
Started Dec 27 12:46:59 PM PST 23
Finished Dec 27 12:47:17 PM PST 23
Peak memory 199148 kb
Host smart-78eb294d-6d14-4db7-9b44-c31a8709922e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219744178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.3219744178
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.1622092738
Short name T584
Test name
Test status
Simulation time 1228906737 ps
CPU time 5.22 seconds
Started Dec 27 12:46:58 PM PST 23
Finished Dec 27 12:47:21 PM PST 23
Peak memory 221264 kb
Host smart-3adbfb1d-56e7-4552-8c47-b74c169f8e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622092738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.1622092738
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.679269666
Short name T378
Test name
Test status
Simulation time 244866693 ps
CPU time 1.07 seconds
Started Dec 27 12:46:57 PM PST 23
Finished Dec 27 12:47:16 PM PST 23
Peak memory 216492 kb
Host smart-72eefa36-6c6b-4c32-a99d-321abbc6d8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679269666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.679269666
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.2914078171
Short name T516
Test name
Test status
Simulation time 150147350 ps
CPU time 0.76 seconds
Started Dec 27 12:46:58 PM PST 23
Finished Dec 27 12:47:16 PM PST 23
Peak memory 199020 kb
Host smart-b1b8ae16-69c6-49d1-a1cc-25942a3612ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914078171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.2914078171
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.1344125314
Short name T282
Test name
Test status
Simulation time 1392036278 ps
CPU time 5.79 seconds
Started Dec 27 12:46:57 PM PST 23
Finished Dec 27 12:47:21 PM PST 23
Peak memory 199412 kb
Host smart-0324f1f5-9a43-4f7a-a052-89cb67c90814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344125314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.1344125314
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.3953428361
Short name T82
Test name
Test status
Simulation time 16645865250 ps
CPU time 24.81 seconds
Started Dec 27 12:46:59 PM PST 23
Finished Dec 27 12:47:41 PM PST 23
Peak memory 217264 kb
Host smart-0d207d7c-aa03-4334-9724-b00a8426f1cd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953428361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.3953428361
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.3018038770
Short name T155
Test name
Test status
Simulation time 93537329 ps
CPU time 0.97 seconds
Started Dec 27 12:46:57 PM PST 23
Finished Dec 27 12:47:16 PM PST 23
Peak memory 199260 kb
Host smart-69f72d18-9819-4aac-960b-9bf8e0663014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018038770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.3018038770
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.3931666103
Short name T465
Test name
Test status
Simulation time 262820653 ps
CPU time 1.59 seconds
Started Dec 27 12:46:57 PM PST 23
Finished Dec 27 12:47:17 PM PST 23
Peak memory 199396 kb
Host smart-ba3432cf-4ca7-4c60-97df-12ce78fb06b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931666103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.3931666103
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.2993471189
Short name T355
Test name
Test status
Simulation time 1080621530 ps
CPU time 5.02 seconds
Started Dec 27 12:47:00 PM PST 23
Finished Dec 27 12:47:22 PM PST 23
Peak memory 199488 kb
Host smart-1fea16a3-775d-4bf9-9fd1-f0f07f52bd9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993471189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.2993471189
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.1534116020
Short name T99
Test name
Test status
Simulation time 267288698 ps
CPU time 1.85 seconds
Started Dec 27 12:46:58 PM PST 23
Finished Dec 27 12:47:17 PM PST 23
Peak memory 199296 kb
Host smart-e5b82b23-fd97-48b0-994c-7525159d5915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534116020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.1534116020
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.3466026310
Short name T151
Test name
Test status
Simulation time 226696656 ps
CPU time 1.3 seconds
Started Dec 27 12:46:58 PM PST 23
Finished Dec 27 12:47:17 PM PST 23
Peak memory 199280 kb
Host smart-44ee59be-1763-4756-8a28-cbfc7a2d2428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466026310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.3466026310
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.1880182827
Short name T310
Test name
Test status
Simulation time 70122307 ps
CPU time 0.72 seconds
Started Dec 27 12:47:47 PM PST 23
Finished Dec 27 12:47:57 PM PST 23
Peak memory 199136 kb
Host smart-69d29cc7-a5af-4b5a-97fb-07ca48eeb189
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880182827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.1880182827
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.587434484
Short name T513
Test name
Test status
Simulation time 2169264510 ps
CPU time 7.73 seconds
Started Dec 27 12:47:41 PM PST 23
Finished Dec 27 12:47:59 PM PST 23
Peak memory 217240 kb
Host smart-f6c4472e-bb2e-493f-9644-5d78d74ea794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587434484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.587434484
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.2679458382
Short name T381
Test name
Test status
Simulation time 244333137 ps
CPU time 1.06 seconds
Started Dec 27 12:47:43 PM PST 23
Finished Dec 27 12:47:54 PM PST 23
Peak memory 216544 kb
Host smart-6b7e5732-2dfe-4789-87e1-23ec423191d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679458382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.2679458382
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.3209545550
Short name T19
Test name
Test status
Simulation time 128705044 ps
CPU time 0.84 seconds
Started Dec 27 12:47:55 PM PST 23
Finished Dec 27 12:48:06 PM PST 23
Peak memory 199168 kb
Host smart-fdfdcf3e-0a2b-41bf-a420-88e7e719722f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209545550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.3209545550
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.357086597
Short name T399
Test name
Test status
Simulation time 1671370361 ps
CPU time 6.9 seconds
Started Dec 27 12:47:42 PM PST 23
Finished Dec 27 12:47:59 PM PST 23
Peak memory 199396 kb
Host smart-b8b9c69f-cc5a-4772-8632-22fa51b550a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357086597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.357086597
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.1581166391
Short name T594
Test name
Test status
Simulation time 109039624 ps
CPU time 0.97 seconds
Started Dec 27 12:47:41 PM PST 23
Finished Dec 27 12:47:52 PM PST 23
Peak memory 199316 kb
Host smart-edfbb497-4183-4498-a12f-10ee50d86a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581166391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.1581166391
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.2169409112
Short name T89
Test name
Test status
Simulation time 118360272 ps
CPU time 1.15 seconds
Started Dec 27 12:47:50 PM PST 23
Finished Dec 27 12:48:00 PM PST 23
Peak memory 199464 kb
Host smart-125b81a5-679e-470a-b670-dcaef71cd904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169409112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.2169409112
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.4147427018
Short name T444
Test name
Test status
Simulation time 2237850072 ps
CPU time 9.04 seconds
Started Dec 27 12:47:43 PM PST 23
Finished Dec 27 12:48:01 PM PST 23
Peak memory 199460 kb
Host smart-7d721ff9-323b-462a-9e29-67ff130d7782
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147427018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.4147427018
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.818123210
Short name T495
Test name
Test status
Simulation time 290276074 ps
CPU time 2.04 seconds
Started Dec 27 12:47:40 PM PST 23
Finished Dec 27 12:47:53 PM PST 23
Peak memory 199252 kb
Host smart-4d9dc8e1-b66d-4630-9c87-2a73c8e05f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818123210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.818123210
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.752933735
Short name T467
Test name
Test status
Simulation time 161792053 ps
CPU time 1.18 seconds
Started Dec 27 12:47:41 PM PST 23
Finished Dec 27 12:47:53 PM PST 23
Peak memory 199472 kb
Host smart-72846049-735f-4bcf-b9ac-8870daab3a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752933735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.752933735
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.1875556726
Short name T574
Test name
Test status
Simulation time 86414726 ps
CPU time 0.78 seconds
Started Dec 27 12:47:43 PM PST 23
Finished Dec 27 12:47:54 PM PST 23
Peak memory 199120 kb
Host smart-4e74cf09-dfb2-4a5c-b4d9-6708c6c7a3a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875556726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.1875556726
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.2861984260
Short name T432
Test name
Test status
Simulation time 1226212744 ps
CPU time 6.09 seconds
Started Dec 27 12:47:49 PM PST 23
Finished Dec 27 12:48:04 PM PST 23
Peak memory 216724 kb
Host smart-fcd4b58a-5dd8-40bc-ada7-eb49fb22ec04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861984260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.2861984260
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.4065720657
Short name T170
Test name
Test status
Simulation time 244453096 ps
CPU time 1.14 seconds
Started Dec 27 12:47:41 PM PST 23
Finished Dec 27 12:47:52 PM PST 23
Peak memory 216544 kb
Host smart-9ffd56af-72f0-4cce-aae0-bf0d1c3c592a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065720657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.4065720657
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.254838320
Short name T343
Test name
Test status
Simulation time 104695265 ps
CPU time 0.77 seconds
Started Dec 27 12:47:41 PM PST 23
Finished Dec 27 12:47:52 PM PST 23
Peak memory 199008 kb
Host smart-08f9af33-bccf-46e4-8396-17d48eb6f277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254838320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.254838320
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.3099544312
Short name T411
Test name
Test status
Simulation time 1572341506 ps
CPU time 5.8 seconds
Started Dec 27 12:47:48 PM PST 23
Finished Dec 27 12:48:03 PM PST 23
Peak memory 199452 kb
Host smart-b071a0f2-6c3b-4e9f-a2b0-6167fa0ecdbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099544312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.3099544312
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.3107666386
Short name T393
Test name
Test status
Simulation time 171781346 ps
CPU time 1.15 seconds
Started Dec 27 12:47:44 PM PST 23
Finished Dec 27 12:47:55 PM PST 23
Peak memory 198356 kb
Host smart-ff3667a0-a6e3-4101-8e5a-800130925a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107666386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.3107666386
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.113148555
Short name T43
Test name
Test status
Simulation time 251281891 ps
CPU time 1.53 seconds
Started Dec 27 12:47:44 PM PST 23
Finished Dec 27 12:47:55 PM PST 23
Peak memory 199464 kb
Host smart-a8b0b67a-468f-48fd-ba6e-1ac8598f6cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113148555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.113148555
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.2312852429
Short name T442
Test name
Test status
Simulation time 953291780 ps
CPU time 4.58 seconds
Started Dec 27 12:47:54 PM PST 23
Finished Dec 27 12:48:08 PM PST 23
Peak memory 199504 kb
Host smart-bab6a236-2a64-4ba6-86bb-5ba5711f3610
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312852429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.2312852429
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.3444839993
Short name T10
Test name
Test status
Simulation time 261618482 ps
CPU time 1.71 seconds
Started Dec 27 12:47:44 PM PST 23
Finished Dec 27 12:47:55 PM PST 23
Peak memory 198296 kb
Host smart-8370b1d3-195c-411e-b716-64c0ed424d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444839993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.3444839993
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.3798303248
Short name T331
Test name
Test status
Simulation time 137947200 ps
CPU time 1.14 seconds
Started Dec 27 12:47:43 PM PST 23
Finished Dec 27 12:47:54 PM PST 23
Peak memory 199276 kb
Host smart-3d9d431d-5593-4ce0-b65b-b9961d438b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798303248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.3798303248
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.2157392468
Short name T302
Test name
Test status
Simulation time 68707230 ps
CPU time 0.72 seconds
Started Dec 27 12:48:00 PM PST 23
Finished Dec 27 12:48:11 PM PST 23
Peak memory 199056 kb
Host smart-bc2bf21d-d217-4bf5-a7cf-aa01263049bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157392468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.2157392468
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.1335332529
Short name T46
Test name
Test status
Simulation time 1221957150 ps
CPU time 5.69 seconds
Started Dec 27 12:47:47 PM PST 23
Finished Dec 27 12:48:02 PM PST 23
Peak memory 217212 kb
Host smart-97131923-2420-4edd-898f-ad483f6d91c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335332529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.1335332529
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.791103215
Short name T95
Test name
Test status
Simulation time 245148457 ps
CPU time 1.07 seconds
Started Dec 27 12:48:01 PM PST 23
Finished Dec 27 12:48:11 PM PST 23
Peak memory 216432 kb
Host smart-ba76af41-9bfa-41ec-b706-8df0ef8599f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791103215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.791103215
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.3110382826
Short name T591
Test name
Test status
Simulation time 129984759 ps
CPU time 0.84 seconds
Started Dec 27 12:47:42 PM PST 23
Finished Dec 27 12:47:53 PM PST 23
Peak memory 199112 kb
Host smart-2bdcb62f-c513-4a2b-a557-a09a9220c191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110382826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.3110382826
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.4225302368
Short name T458
Test name
Test status
Simulation time 946871968 ps
CPU time 5 seconds
Started Dec 27 12:47:48 PM PST 23
Finished Dec 27 12:48:02 PM PST 23
Peak memory 199484 kb
Host smart-626a9bbd-3d31-4d6e-aaaf-5dce5adb60a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225302368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.4225302368
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.2455127167
Short name T306
Test name
Test status
Simulation time 100288062 ps
CPU time 0.95 seconds
Started Dec 27 12:47:57 PM PST 23
Finished Dec 27 12:48:09 PM PST 23
Peak memory 199256 kb
Host smart-e1db9665-b1a8-4426-8975-9b6f8499e800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455127167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.2455127167
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.291320296
Short name T319
Test name
Test status
Simulation time 199574707 ps
CPU time 1.35 seconds
Started Dec 27 12:47:47 PM PST 23
Finished Dec 27 12:47:58 PM PST 23
Peak memory 199460 kb
Host smart-cfbbec55-f514-413c-a744-39471ce049d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291320296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.291320296
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.3491202923
Short name T354
Test name
Test status
Simulation time 7927671300 ps
CPU time 26.51 seconds
Started Dec 27 12:48:03 PM PST 23
Finished Dec 27 12:48:38 PM PST 23
Peak memory 199576 kb
Host smart-189b96a4-584b-4451-b71c-4fecaa5623fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491202923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.3491202923
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.3588272915
Short name T528
Test name
Test status
Simulation time 362667434 ps
CPU time 2.24 seconds
Started Dec 27 12:47:49 PM PST 23
Finished Dec 27 12:48:00 PM PST 23
Peak memory 199168 kb
Host smart-ef0fc33c-5b17-426b-8d9b-f3bd5d14f1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588272915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.3588272915
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.2587439721
Short name T579
Test name
Test status
Simulation time 205486057 ps
CPU time 1.28 seconds
Started Dec 27 12:47:47 PM PST 23
Finished Dec 27 12:47:58 PM PST 23
Peak memory 199180 kb
Host smart-b69032e4-ac52-4ae5-bd83-5c2a0a6a96ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587439721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.2587439721
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.3728177788
Short name T606
Test name
Test status
Simulation time 68940624 ps
CPU time 0.8 seconds
Started Dec 27 12:47:57 PM PST 23
Finished Dec 27 12:48:08 PM PST 23
Peak memory 199132 kb
Host smart-9f901b27-5fd8-4f2a-9749-f6d51388f19f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728177788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.3728177788
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.3427682682
Short name T597
Test name
Test status
Simulation time 1867084507 ps
CPU time 7.45 seconds
Started Dec 27 12:47:49 PM PST 23
Finished Dec 27 12:48:05 PM PST 23
Peak memory 216540 kb
Host smart-1d627cc0-7d95-4e5a-aad4-ab09179b3b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427682682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.3427682682
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.4026049462
Short name T384
Test name
Test status
Simulation time 244374443 ps
CPU time 1.05 seconds
Started Dec 27 12:47:56 PM PST 23
Finished Dec 27 12:48:07 PM PST 23
Peak memory 216308 kb
Host smart-1a7bf7d2-c09a-463f-bac8-4bd371a049b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026049462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.4026049462
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.2784406584
Short name T460
Test name
Test status
Simulation time 222158540 ps
CPU time 0.99 seconds
Started Dec 27 12:48:00 PM PST 23
Finished Dec 27 12:48:11 PM PST 23
Peak memory 199072 kb
Host smart-a4a7dac0-f7df-445c-a4d5-fc21b7ef7d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784406584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.2784406584
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.2396854275
Short name T613
Test name
Test status
Simulation time 1187074389 ps
CPU time 5.13 seconds
Started Dec 27 12:47:43 PM PST 23
Finished Dec 27 12:47:58 PM PST 23
Peak memory 199380 kb
Host smart-2c083470-5764-4f07-a7ff-0b7d304b51d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396854275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.2396854275
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.911907938
Short name T311
Test name
Test status
Simulation time 105741715 ps
CPU time 0.99 seconds
Started Dec 27 12:47:54 PM PST 23
Finished Dec 27 12:48:05 PM PST 23
Peak memory 199320 kb
Host smart-89e31b05-2170-4d93-8eeb-5a6be8d78a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911907938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.911907938
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.184776223
Short name T459
Test name
Test status
Simulation time 249653746 ps
CPU time 1.51 seconds
Started Dec 27 12:47:49 PM PST 23
Finished Dec 27 12:47:59 PM PST 23
Peak memory 199416 kb
Host smart-e7f51d94-c6cb-46d9-a4a6-f4d82e11dc7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184776223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.184776223
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.3370947605
Short name T505
Test name
Test status
Simulation time 4603606854 ps
CPU time 19.57 seconds
Started Dec 27 12:47:55 PM PST 23
Finished Dec 27 12:48:25 PM PST 23
Peak memory 199528 kb
Host smart-55760213-f7f8-4946-88a2-2cdfa480c5a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370947605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.3370947605
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.3437078614
Short name T437
Test name
Test status
Simulation time 136406686 ps
CPU time 1.65 seconds
Started Dec 27 12:47:52 PM PST 23
Finished Dec 27 12:48:04 PM PST 23
Peak memory 199308 kb
Host smart-fdf93019-6b07-46ec-a7a8-f9718bc2ac64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437078614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.3437078614
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.3369547238
Short name T44
Test name
Test status
Simulation time 146787550 ps
CPU time 1.25 seconds
Started Dec 27 12:47:51 PM PST 23
Finished Dec 27 12:48:03 PM PST 23
Peak memory 199504 kb
Host smart-b9d15cbf-db78-421b-8032-0b89212b82d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369547238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.3369547238
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.2710746617
Short name T88
Test name
Test status
Simulation time 69950777 ps
CPU time 0.72 seconds
Started Dec 27 12:47:49 PM PST 23
Finished Dec 27 12:47:58 PM PST 23
Peak memory 199120 kb
Host smart-47744251-2f95-429e-841e-0d9fa5dbde2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710746617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.2710746617
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.73935764
Short name T522
Test name
Test status
Simulation time 2365298055 ps
CPU time 7.65 seconds
Started Dec 27 12:47:57 PM PST 23
Finished Dec 27 12:48:15 PM PST 23
Peak memory 216540 kb
Host smart-6467c72d-c0b8-4b4f-b552-c6179216e75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73935764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.73935764
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.4008108612
Short name T472
Test name
Test status
Simulation time 243741541 ps
CPU time 1.09 seconds
Started Dec 27 12:48:04 PM PST 23
Finished Dec 27 12:48:13 PM PST 23
Peak memory 216368 kb
Host smart-aaa83b73-c668-4b6a-8389-a1c5948b1aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008108612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.4008108612
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.143816594
Short name T334
Test name
Test status
Simulation time 181041000 ps
CPU time 0.87 seconds
Started Dec 27 12:47:47 PM PST 23
Finished Dec 27 12:47:57 PM PST 23
Peak memory 199004 kb
Host smart-c333dcf6-0567-4c5f-9f3b-a5c4a22af5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143816594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.143816594
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.3861897565
Short name T575
Test name
Test status
Simulation time 2189130437 ps
CPU time 8.54 seconds
Started Dec 27 12:47:56 PM PST 23
Finished Dec 27 12:48:14 PM PST 23
Peak memory 199544 kb
Host smart-040c06d8-8992-4456-a361-262a77c28969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861897565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.3861897565
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.1881622722
Short name T498
Test name
Test status
Simulation time 100901917 ps
CPU time 1.03 seconds
Started Dec 27 12:47:57 PM PST 23
Finished Dec 27 12:48:08 PM PST 23
Peak memory 199344 kb
Host smart-8d994c23-ca8f-4c55-a33b-d2a3664bdd96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881622722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.1881622722
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.75018396
Short name T252
Test name
Test status
Simulation time 120482409 ps
CPU time 1.2 seconds
Started Dec 27 12:47:58 PM PST 23
Finished Dec 27 12:48:10 PM PST 23
Peak memory 199452 kb
Host smart-163123d6-7e42-4428-a6ea-3c9935d7805f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75018396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.75018396
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.961927255
Short name T287
Test name
Test status
Simulation time 1328992266 ps
CPU time 6.01 seconds
Started Dec 27 12:48:02 PM PST 23
Finished Dec 27 12:48:17 PM PST 23
Peak memory 199484 kb
Host smart-dcd2e6f9-5fcb-47ad-82db-fb6b0a13c59c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961927255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.961927255
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.4106965464
Short name T536
Test name
Test status
Simulation time 143704861 ps
CPU time 1.77 seconds
Started Dec 27 12:47:55 PM PST 23
Finished Dec 27 12:48:07 PM PST 23
Peak memory 199220 kb
Host smart-b0adfcef-b7cc-47ad-bb7e-ab23e711ad30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106965464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.4106965464
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.3141298002
Short name T313
Test name
Test status
Simulation time 159197147 ps
CPU time 1.07 seconds
Started Dec 27 12:47:55 PM PST 23
Finished Dec 27 12:48:06 PM PST 23
Peak memory 199292 kb
Host smart-b3949418-4b81-4ad1-a7a2-97c09fe17f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141298002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.3141298002
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.1733205486
Short name T309
Test name
Test status
Simulation time 78239470 ps
CPU time 0.75 seconds
Started Dec 27 12:47:49 PM PST 23
Finished Dec 27 12:47:58 PM PST 23
Peak memory 199100 kb
Host smart-2470950f-aa99-433d-9a63-049cc4c5e83c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733205486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.1733205486
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.4200295699
Short name T497
Test name
Test status
Simulation time 1914173351 ps
CPU time 7.19 seconds
Started Dec 27 12:47:49 PM PST 23
Finished Dec 27 12:48:05 PM PST 23
Peak memory 216728 kb
Host smart-e2582e88-0f89-41f5-a3f5-0ca09af40e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200295699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.4200295699
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.3336558685
Short name T398
Test name
Test status
Simulation time 244159062 ps
CPU time 1.15 seconds
Started Dec 27 12:47:52 PM PST 23
Finished Dec 27 12:48:03 PM PST 23
Peak memory 216424 kb
Host smart-1ef669c2-aeb1-4a5d-bf9b-51143d15178a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336558685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.3336558685
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.1558928053
Short name T534
Test name
Test status
Simulation time 130582193 ps
CPU time 0.78 seconds
Started Dec 27 12:47:56 PM PST 23
Finished Dec 27 12:48:06 PM PST 23
Peak memory 199048 kb
Host smart-20dab0fd-051d-47da-beed-60037b95d005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558928053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.1558928053
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.1313110798
Short name T500
Test name
Test status
Simulation time 1412792020 ps
CPU time 5.78 seconds
Started Dec 27 12:47:55 PM PST 23
Finished Dec 27 12:48:10 PM PST 23
Peak memory 199412 kb
Host smart-f997e0b4-bc7f-44b1-9d58-50f5847cf0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313110798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.1313110798
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.2256488366
Short name T168
Test name
Test status
Simulation time 177273773 ps
CPU time 1.17 seconds
Started Dec 27 12:47:56 PM PST 23
Finished Dec 27 12:48:06 PM PST 23
Peak memory 199304 kb
Host smart-7f32b002-b745-4b83-809a-8b200e8ab768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256488366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.2256488366
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.3957703353
Short name T324
Test name
Test status
Simulation time 201035076 ps
CPU time 1.31 seconds
Started Dec 27 12:47:48 PM PST 23
Finished Dec 27 12:47:59 PM PST 23
Peak memory 199480 kb
Host smart-da769bd5-4ad7-453f-936d-9e091a3b7934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957703353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.3957703353
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.2366783427
Short name T126
Test name
Test status
Simulation time 1502659995 ps
CPU time 7.67 seconds
Started Dec 27 12:48:03 PM PST 23
Finished Dec 27 12:48:20 PM PST 23
Peak memory 199436 kb
Host smart-82bdc208-bb58-4d65-9d19-24184fe4676e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366783427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.2366783427
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.1777720313
Short name T49
Test name
Test status
Simulation time 316706431 ps
CPU time 2.01 seconds
Started Dec 27 12:47:56 PM PST 23
Finished Dec 27 12:48:08 PM PST 23
Peak memory 199256 kb
Host smart-ca0fdf9c-9ae9-4a6a-bfd3-80e4cfa31f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777720313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.1777720313
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.2165331737
Short name T70
Test name
Test status
Simulation time 76915622 ps
CPU time 0.76 seconds
Started Dec 27 12:47:56 PM PST 23
Finished Dec 27 12:48:06 PM PST 23
Peak memory 199280 kb
Host smart-2e9861ae-bde1-4ef9-914e-4d5520c447b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165331737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.2165331737
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.2701696793
Short name T72
Test name
Test status
Simulation time 71314001 ps
CPU time 0.76 seconds
Started Dec 27 12:48:06 PM PST 23
Finished Dec 27 12:48:14 PM PST 23
Peak memory 199140 kb
Host smart-cff108a6-a34c-4be5-94b4-7fa8e36fcad0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701696793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.2701696793
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.1320992238
Short name T66
Test name
Test status
Simulation time 2368005698 ps
CPU time 8.37 seconds
Started Dec 27 12:47:59 PM PST 23
Finished Dec 27 12:48:18 PM PST 23
Peak memory 217244 kb
Host smart-092802ae-7168-4918-a058-f70dddee75bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320992238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.1320992238
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.3848859814
Short name T327
Test name
Test status
Simulation time 243943968 ps
CPU time 1.04 seconds
Started Dec 27 12:48:06 PM PST 23
Finished Dec 27 12:48:15 PM PST 23
Peak memory 216460 kb
Host smart-47109094-789e-4b6f-a422-b18d7ff8cace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848859814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.3848859814
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.1152739949
Short name T450
Test name
Test status
Simulation time 205999096 ps
CPU time 0.89 seconds
Started Dec 27 12:48:02 PM PST 23
Finished Dec 27 12:48:12 PM PST 23
Peak memory 199068 kb
Host smart-b75ddadb-6bb6-4b6f-80c9-3320fcd64c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152739949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.1152739949
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.2457733555
Short name T483
Test name
Test status
Simulation time 1919093901 ps
CPU time 6.84 seconds
Started Dec 27 12:47:59 PM PST 23
Finished Dec 27 12:48:16 PM PST 23
Peak memory 199436 kb
Host smart-727cf47c-3f14-465e-b0c2-0003d637af10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457733555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.2457733555
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.3253644036
Short name T503
Test name
Test status
Simulation time 99781053 ps
CPU time 0.99 seconds
Started Dec 27 12:48:00 PM PST 23
Finished Dec 27 12:48:11 PM PST 23
Peak memory 199244 kb
Host smart-a0bc432a-3c25-4377-9e06-7ffbca5e1d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253644036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.3253644036
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.3698897752
Short name T388
Test name
Test status
Simulation time 254368358 ps
CPU time 1.43 seconds
Started Dec 27 12:47:46 PM PST 23
Finished Dec 27 12:47:57 PM PST 23
Peak memory 199416 kb
Host smart-864eb50d-a513-43fe-bb40-a4f644006f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698897752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.3698897752
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.4019563709
Short name T521
Test name
Test status
Simulation time 1384002027 ps
CPU time 7.14 seconds
Started Dec 27 12:48:13 PM PST 23
Finished Dec 27 12:48:28 PM PST 23
Peak memory 199448 kb
Host smart-dfad5c64-eef2-40fa-b60a-b516747927f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019563709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.4019563709
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.1511135273
Short name T615
Test name
Test status
Simulation time 375488257 ps
CPU time 2.03 seconds
Started Dec 27 12:47:55 PM PST 23
Finished Dec 27 12:48:07 PM PST 23
Peak memory 199364 kb
Host smart-0e75f284-0d87-49ed-806a-b56b6eb1bb77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511135273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.1511135273
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.1788105677
Short name T280
Test name
Test status
Simulation time 58736723 ps
CPU time 0.72 seconds
Started Dec 27 12:47:50 PM PST 23
Finished Dec 27 12:48:00 PM PST 23
Peak memory 199280 kb
Host smart-15e93be4-f10e-4b14-b882-22bc7c79d14b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788105677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.1788105677
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.1975095022
Short name T256
Test name
Test status
Simulation time 84652691 ps
CPU time 0.81 seconds
Started Dec 27 12:47:56 PM PST 23
Finished Dec 27 12:48:06 PM PST 23
Peak memory 199080 kb
Host smart-8b02ea7e-6c6e-4642-a612-c8394100ac0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975095022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.1975095022
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.720581215
Short name T512
Test name
Test status
Simulation time 1888790926 ps
CPU time 7.38 seconds
Started Dec 27 12:48:08 PM PST 23
Finished Dec 27 12:48:23 PM PST 23
Peak memory 221040 kb
Host smart-cbedb8a2-b9d9-43ed-aae0-756757c48c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720581215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.720581215
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.3191328506
Short name T449
Test name
Test status
Simulation time 244323814 ps
CPU time 1.06 seconds
Started Dec 27 12:48:02 PM PST 23
Finished Dec 27 12:48:12 PM PST 23
Peak memory 216392 kb
Host smart-8dc74d1d-31f0-4bd8-a3d7-ea4028a24dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191328506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.3191328506
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.1740624888
Short name T547
Test name
Test status
Simulation time 143832504 ps
CPU time 0.8 seconds
Started Dec 27 12:48:10 PM PST 23
Finished Dec 27 12:48:18 PM PST 23
Peak memory 199116 kb
Host smart-329235d5-25fa-4ea2-8a3c-4be019396708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740624888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.1740624888
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.1001486859
Short name T303
Test name
Test status
Simulation time 1731378504 ps
CPU time 6.04 seconds
Started Dec 27 12:48:07 PM PST 23
Finished Dec 27 12:48:21 PM PST 23
Peak memory 199412 kb
Host smart-eab86939-1099-4dc6-822a-5406b005c489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001486859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.1001486859
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.4212783528
Short name T290
Test name
Test status
Simulation time 182027054 ps
CPU time 1.16 seconds
Started Dec 27 12:48:10 PM PST 23
Finished Dec 27 12:48:19 PM PST 23
Peak memory 199288 kb
Host smart-c4f4de8f-81ee-4b6f-9921-c2afe576d943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212783528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.4212783528
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.1497005113
Short name T414
Test name
Test status
Simulation time 198485275 ps
CPU time 1.31 seconds
Started Dec 27 12:48:10 PM PST 23
Finished Dec 27 12:48:18 PM PST 23
Peak memory 199460 kb
Host smart-4592b600-d258-4bef-973b-64e6b147898c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497005113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.1497005113
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.3699525859
Short name T618
Test name
Test status
Simulation time 10010536029 ps
CPU time 31.88 seconds
Started Dec 27 12:47:56 PM PST 23
Finished Dec 27 12:48:37 PM PST 23
Peak memory 199508 kb
Host smart-328f2b54-a936-4d26-bad0-647b1cda18b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699525859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.3699525859
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.717670754
Short name T97
Test name
Test status
Simulation time 337695323 ps
CPU time 2.09 seconds
Started Dec 27 12:48:11 PM PST 23
Finished Dec 27 12:48:20 PM PST 23
Peak memory 199244 kb
Host smart-efb408a8-09fd-4ffd-a36e-19a659222827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717670754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.717670754
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.1808255973
Short name T571
Test name
Test status
Simulation time 162566911 ps
CPU time 1.23 seconds
Started Dec 27 12:47:57 PM PST 23
Finished Dec 27 12:48:09 PM PST 23
Peak memory 199508 kb
Host smart-170e51bb-efc0-4291-87dd-729d7b55ee5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808255973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.1808255973
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.1681843427
Short name T300
Test name
Test status
Simulation time 72158341 ps
CPU time 0.76 seconds
Started Dec 27 12:48:25 PM PST 23
Finished Dec 27 12:48:30 PM PST 23
Peak memory 199124 kb
Host smart-49dfc3aa-6908-4b09-bcd4-f75d2fbb15a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681843427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.1681843427
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.1549162510
Short name T31
Test name
Test status
Simulation time 1220665093 ps
CPU time 5.45 seconds
Started Dec 27 12:48:02 PM PST 23
Finished Dec 27 12:48:17 PM PST 23
Peak memory 217164 kb
Host smart-36dbaa36-030c-458c-830d-4f68afee6384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549162510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.1549162510
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.1493242093
Short name T376
Test name
Test status
Simulation time 244532812 ps
CPU time 1.05 seconds
Started Dec 27 12:48:08 PM PST 23
Finished Dec 27 12:48:16 PM PST 23
Peak memory 216336 kb
Host smart-c016c024-157e-414d-9fab-59df9cdf159b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493242093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.1493242093
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.1492038276
Short name T475
Test name
Test status
Simulation time 189112299 ps
CPU time 0.84 seconds
Started Dec 27 12:47:59 PM PST 23
Finished Dec 27 12:48:10 PM PST 23
Peak memory 199092 kb
Host smart-9bf40885-a498-4970-a4c7-ad3bb814ac6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492038276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.1492038276
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.535873168
Short name T557
Test name
Test status
Simulation time 997535699 ps
CPU time 4.51 seconds
Started Dec 27 12:47:55 PM PST 23
Finished Dec 27 12:48:10 PM PST 23
Peak memory 199452 kb
Host smart-fff8352e-916b-4acd-aa28-9febe8e88e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535873168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.535873168
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.1739092713
Short name T6
Test name
Test status
Simulation time 171279596 ps
CPU time 1.27 seconds
Started Dec 27 12:47:59 PM PST 23
Finished Dec 27 12:48:11 PM PST 23
Peak memory 199264 kb
Host smart-e68dc70a-5256-4701-aa0b-543041dba0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739092713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.1739092713
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.559052034
Short name T524
Test name
Test status
Simulation time 120442864 ps
CPU time 1.12 seconds
Started Dec 27 12:48:09 PM PST 23
Finished Dec 27 12:48:17 PM PST 23
Peak memory 199488 kb
Host smart-a26c8ca5-fbf8-4e31-9e15-c4aa9661e601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559052034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.559052034
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.4117811922
Short name T566
Test name
Test status
Simulation time 4942896351 ps
CPU time 17.61 seconds
Started Dec 27 12:47:51 PM PST 23
Finished Dec 27 12:48:19 PM PST 23
Peak memory 199496 kb
Host smart-d54605d3-bb81-4b3a-95a6-4d5d572acd9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117811922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.4117811922
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.3939750344
Short name T397
Test name
Test status
Simulation time 464953188 ps
CPU time 2.36 seconds
Started Dec 27 12:48:09 PM PST 23
Finished Dec 27 12:48:18 PM PST 23
Peak memory 199292 kb
Host smart-cc047bde-a7cd-41b8-862b-ffebfb491e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939750344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.3939750344
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.2613072544
Short name T39
Test name
Test status
Simulation time 178949282 ps
CPU time 1.2 seconds
Started Dec 27 12:48:18 PM PST 23
Finished Dec 27 12:48:26 PM PST 23
Peak memory 199356 kb
Host smart-61e9d69c-2640-4df2-93a3-9d06ae23f75d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613072544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.2613072544
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.3770861711
Short name T585
Test name
Test status
Simulation time 89772095 ps
CPU time 0.82 seconds
Started Dec 27 12:47:57 PM PST 23
Finished Dec 27 12:48:08 PM PST 23
Peak memory 199068 kb
Host smart-a79b0c35-0925-4fce-91b1-719de2e62186
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770861711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.3770861711
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.2286343731
Short name T318
Test name
Test status
Simulation time 2144180183 ps
CPU time 8.01 seconds
Started Dec 27 12:47:55 PM PST 23
Finished Dec 27 12:48:13 PM PST 23
Peak memory 217236 kb
Host smart-37da2852-6adb-496d-a70a-3f2b71e4a030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286343731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.2286343731
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.3750858688
Short name T169
Test name
Test status
Simulation time 243368195 ps
CPU time 1.06 seconds
Started Dec 27 12:47:56 PM PST 23
Finished Dec 27 12:48:07 PM PST 23
Peak memory 216384 kb
Host smart-4657868f-814a-4443-bbf5-b4462aa9a9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750858688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.3750858688
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.114635631
Short name T390
Test name
Test status
Simulation time 149452004 ps
CPU time 0.8 seconds
Started Dec 27 12:48:04 PM PST 23
Finished Dec 27 12:48:13 PM PST 23
Peak memory 199132 kb
Host smart-6dc2e669-f754-407b-a1fd-77f9cb42569a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114635631 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.114635631
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.3346360610
Short name T294
Test name
Test status
Simulation time 820611027 ps
CPU time 4.06 seconds
Started Dec 27 12:48:06 PM PST 23
Finished Dec 27 12:48:18 PM PST 23
Peak memory 199468 kb
Host smart-919a45bc-d309-47ab-a657-d61a4a9f9edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346360610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.3346360610
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.1921780676
Short name T22
Test name
Test status
Simulation time 97453874 ps
CPU time 0.93 seconds
Started Dec 27 12:48:18 PM PST 23
Finished Dec 27 12:48:26 PM PST 23
Peak memory 199328 kb
Host smart-307eb223-61bf-48dc-b277-086421d6fa37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921780676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.1921780676
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.52486428
Short name T439
Test name
Test status
Simulation time 122454432 ps
CPU time 1.15 seconds
Started Dec 27 12:47:50 PM PST 23
Finished Dec 27 12:48:02 PM PST 23
Peak memory 199492 kb
Host smart-0da182d3-59c4-44df-b584-47088644d86b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52486428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.52486428
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.2522570603
Short name T617
Test name
Test status
Simulation time 5460374946 ps
CPU time 22.11 seconds
Started Dec 27 12:48:09 PM PST 23
Finished Dec 27 12:48:38 PM PST 23
Peak memory 199588 kb
Host smart-4b672438-5952-4162-8d85-eba233efa172
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522570603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.2522570603
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.3748857916
Short name T263
Test name
Test status
Simulation time 294285067 ps
CPU time 1.86 seconds
Started Dec 27 12:48:19 PM PST 23
Finished Dec 27 12:48:28 PM PST 23
Peak memory 199260 kb
Host smart-930e30bf-af8a-4126-a877-eed010811d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748857916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.3748857916
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.2898725277
Short name T602
Test name
Test status
Simulation time 195244610 ps
CPU time 1.27 seconds
Started Dec 27 12:48:04 PM PST 23
Finished Dec 27 12:48:14 PM PST 23
Peak memory 199324 kb
Host smart-cfdbf765-9b62-49c0-bdf4-0f3cbbcbc03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898725277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.2898725277
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.1972301048
Short name T537
Test name
Test status
Simulation time 84038314 ps
CPU time 0.78 seconds
Started Dec 27 12:47:17 PM PST 23
Finished Dec 27 12:47:29 PM PST 23
Peak memory 199088 kb
Host smart-0788f6e3-5135-4861-af5b-dbd02300c401
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972301048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.1972301048
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.2986695047
Short name T27
Test name
Test status
Simulation time 1882968677 ps
CPU time 6.88 seconds
Started Dec 27 12:46:58 PM PST 23
Finished Dec 27 12:47:22 PM PST 23
Peak memory 217160 kb
Host smart-6d0b942f-7ef8-4269-bec3-8ed19f6ac488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986695047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.2986695047
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.3319657819
Short name T281
Test name
Test status
Simulation time 244289210 ps
CPU time 1.01 seconds
Started Dec 27 12:46:58 PM PST 23
Finished Dec 27 12:47:16 PM PST 23
Peak memory 216496 kb
Host smart-6ad7f85d-2168-4dd2-a369-3c95098d8cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319657819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.3319657819
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.3982863683
Short name T373
Test name
Test status
Simulation time 188949264 ps
CPU time 0.84 seconds
Started Dec 27 12:46:58 PM PST 23
Finished Dec 27 12:47:17 PM PST 23
Peak memory 199008 kb
Host smart-9be27fb7-8d8c-4c9a-8b58-be200f78ada2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982863683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.3982863683
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.420741855
Short name T254
Test name
Test status
Simulation time 672950451 ps
CPU time 3.48 seconds
Started Dec 27 12:46:57 PM PST 23
Finished Dec 27 12:47:19 PM PST 23
Peak memory 199476 kb
Host smart-5b75298c-d255-4d86-b3c6-dd97d03febd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420741855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.420741855
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.169480815
Short name T564
Test name
Test status
Simulation time 153451541 ps
CPU time 1.07 seconds
Started Dec 27 12:46:59 PM PST 23
Finished Dec 27 12:47:17 PM PST 23
Peak memory 199276 kb
Host smart-0e1cd240-994b-42ca-97b3-a5a79661312b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169480815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.169480815
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.2591871663
Short name T175
Test name
Test status
Simulation time 131661173 ps
CPU time 1.13 seconds
Started Dec 27 12:46:57 PM PST 23
Finished Dec 27 12:47:16 PM PST 23
Peak memory 199488 kb
Host smart-7313bf13-69af-4c91-815d-966d1ef63722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591871663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.2591871663
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.3463642724
Short name T356
Test name
Test status
Simulation time 597956778 ps
CPU time 3.31 seconds
Started Dec 27 12:47:00 PM PST 23
Finished Dec 27 12:47:20 PM PST 23
Peak memory 199472 kb
Host smart-952409e9-8ff4-4aff-b11a-d6c5c4c9b220
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463642724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.3463642724
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.2566477210
Short name T554
Test name
Test status
Simulation time 369608589 ps
CPU time 2.53 seconds
Started Dec 27 12:46:59 PM PST 23
Finished Dec 27 12:47:19 PM PST 23
Peak memory 199256 kb
Host smart-5d7ea732-3bc9-43b5-8197-b2abb280957c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566477210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.2566477210
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.519645864
Short name T157
Test name
Test status
Simulation time 69232700 ps
CPU time 0.73 seconds
Started Dec 27 12:46:56 PM PST 23
Finished Dec 27 12:47:15 PM PST 23
Peak memory 199268 kb
Host smart-cba411ea-0c99-4869-ad13-7d0a66f62222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519645864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.519645864
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.2161037920
Short name T7
Test name
Test status
Simulation time 85869244 ps
CPU time 0.77 seconds
Started Dec 27 12:48:01 PM PST 23
Finished Dec 27 12:48:11 PM PST 23
Peak memory 199144 kb
Host smart-951ffcbd-6be8-404a-8959-3b66465d794e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161037920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.2161037920
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.4157795184
Short name T379
Test name
Test status
Simulation time 1907453156 ps
CPU time 6.9 seconds
Started Dec 27 12:47:59 PM PST 23
Finished Dec 27 12:48:16 PM PST 23
Peak memory 221180 kb
Host smart-bfdf69f0-9c43-4571-9229-e6a1862f3576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157795184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.4157795184
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.1099052400
Short name T600
Test name
Test status
Simulation time 244277701 ps
CPU time 1.1 seconds
Started Dec 27 12:48:11 PM PST 23
Finished Dec 27 12:48:19 PM PST 23
Peak memory 216540 kb
Host smart-23f3fc8c-a5e8-4391-9879-fd1e8e10780b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099052400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.1099052400
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.2186398595
Short name T372
Test name
Test status
Simulation time 146196653 ps
CPU time 0.91 seconds
Started Dec 27 12:48:03 PM PST 23
Finished Dec 27 12:48:13 PM PST 23
Peak memory 199056 kb
Host smart-10b8da3d-d655-40d0-89e8-e98d9dc0923a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186398595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.2186398595
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.652667120
Short name T115
Test name
Test status
Simulation time 789027169 ps
CPU time 4.01 seconds
Started Dec 27 12:47:53 PM PST 23
Finished Dec 27 12:48:07 PM PST 23
Peak memory 199412 kb
Host smart-32c66782-2f9f-43a2-b377-956787565ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652667120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.652667120
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.395542780
Short name T441
Test name
Test status
Simulation time 104035728 ps
CPU time 0.96 seconds
Started Dec 27 12:47:53 PM PST 23
Finished Dec 27 12:48:04 PM PST 23
Peak memory 199236 kb
Host smart-5d8077e7-8202-4f15-99b7-02cc980465b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395542780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.395542780
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.832523489
Short name T425
Test name
Test status
Simulation time 207571597 ps
CPU time 1.38 seconds
Started Dec 27 12:48:18 PM PST 23
Finished Dec 27 12:48:26 PM PST 23
Peak memory 199472 kb
Host smart-82fa00a0-acac-439a-b036-5481beee2551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832523489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.832523489
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.850391420
Short name T41
Test name
Test status
Simulation time 372165705 ps
CPU time 2.04 seconds
Started Dec 27 12:47:54 PM PST 23
Finished Dec 27 12:48:06 PM PST 23
Peak memory 199284 kb
Host smart-2144d2e8-ccf8-4ecd-9e1e-a885d83647e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850391420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.850391420
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.1301776490
Short name T422
Test name
Test status
Simulation time 134440373 ps
CPU time 0.93 seconds
Started Dec 27 12:48:06 PM PST 23
Finished Dec 27 12:48:15 PM PST 23
Peak memory 199332 kb
Host smart-21613e2a-ae6b-4604-8fa8-f00eb498e49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301776490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.1301776490
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.3224232172
Short name T543
Test name
Test status
Simulation time 111455772 ps
CPU time 0.83 seconds
Started Dec 27 12:47:57 PM PST 23
Finished Dec 27 12:48:09 PM PST 23
Peak memory 199144 kb
Host smart-aeb1323a-c9cc-4228-98b3-8971989b52cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224232172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.3224232172
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.949010405
Short name T54
Test name
Test status
Simulation time 1225999085 ps
CPU time 5.16 seconds
Started Dec 27 12:48:08 PM PST 23
Finished Dec 27 12:48:20 PM PST 23
Peak memory 216692 kb
Host smart-f18f9d17-c4d9-4bc4-a8e8-589ee3f8344f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949010405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.949010405
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.319105418
Short name T533
Test name
Test status
Simulation time 243915367 ps
CPU time 1.03 seconds
Started Dec 27 12:48:04 PM PST 23
Finished Dec 27 12:48:14 PM PST 23
Peak memory 216472 kb
Host smart-33f4bdf4-cc75-4109-8363-b0dd19839643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319105418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.319105418
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.1105954067
Short name T278
Test name
Test status
Simulation time 141565932 ps
CPU time 0.87 seconds
Started Dec 27 12:48:02 PM PST 23
Finished Dec 27 12:48:12 PM PST 23
Peak memory 199144 kb
Host smart-9ecf82c6-6f56-4f06-9184-c8df6b951ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105954067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.1105954067
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.2102386205
Short name T570
Test name
Test status
Simulation time 842167320 ps
CPU time 4.08 seconds
Started Dec 27 12:47:56 PM PST 23
Finished Dec 27 12:48:10 PM PST 23
Peak memory 199472 kb
Host smart-c7f17f69-9047-4c02-aa8b-6febb38fb163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102386205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.2102386205
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.1585606811
Short name T295
Test name
Test status
Simulation time 100788183 ps
CPU time 1 seconds
Started Dec 27 12:48:02 PM PST 23
Finished Dec 27 12:48:12 PM PST 23
Peak memory 199304 kb
Host smart-b81342a4-9ff9-408b-9652-655dd4565d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585606811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.1585606811
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.1242000294
Short name T375
Test name
Test status
Simulation time 126618205 ps
CPU time 1.15 seconds
Started Dec 27 12:48:07 PM PST 23
Finished Dec 27 12:48:16 PM PST 23
Peak memory 199480 kb
Host smart-73235e03-8074-4aec-ae9b-78f7ee5e22f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242000294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.1242000294
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.12142538
Short name T400
Test name
Test status
Simulation time 5964992746 ps
CPU time 20 seconds
Started Dec 27 12:48:02 PM PST 23
Finished Dec 27 12:48:32 PM PST 23
Peak memory 199552 kb
Host smart-318e14cb-b7df-4000-beef-6321d72fd54b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12142538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.12142538
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.802478540
Short name T96
Test name
Test status
Simulation time 129580683 ps
CPU time 1.54 seconds
Started Dec 27 12:48:07 PM PST 23
Finished Dec 27 12:48:16 PM PST 23
Peak memory 199344 kb
Host smart-f21fc719-96d8-4353-bab8-b017453fcf94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802478540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.802478540
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.2182150097
Short name T386
Test name
Test status
Simulation time 150708105 ps
CPU time 1.2 seconds
Started Dec 27 12:48:10 PM PST 23
Finished Dec 27 12:48:19 PM PST 23
Peak memory 199296 kb
Host smart-d17183e8-77d4-4948-9b43-113bd9516dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182150097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.2182150097
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.2540756740
Short name T511
Test name
Test status
Simulation time 76120171 ps
CPU time 0.77 seconds
Started Dec 27 12:48:03 PM PST 23
Finished Dec 27 12:48:13 PM PST 23
Peak memory 199088 kb
Host smart-c3619bfe-b540-4016-b68c-81003ba65c12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540756740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.2540756740
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.1825209259
Short name T322
Test name
Test status
Simulation time 245239819 ps
CPU time 1.01 seconds
Started Dec 27 12:48:04 PM PST 23
Finished Dec 27 12:48:13 PM PST 23
Peak memory 216388 kb
Host smart-ce9e753b-cbcc-4b33-94db-eb17009349bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825209259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.1825209259
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.2340608360
Short name T359
Test name
Test status
Simulation time 176998024 ps
CPU time 0.86 seconds
Started Dec 27 12:48:03 PM PST 23
Finished Dec 27 12:48:13 PM PST 23
Peak memory 199068 kb
Host smart-8c271bd1-b953-4960-8ed3-5ed9979e3385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340608360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.2340608360
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.3891549036
Short name T469
Test name
Test status
Simulation time 2032957079 ps
CPU time 7.55 seconds
Started Dec 27 12:48:10 PM PST 23
Finished Dec 27 12:48:24 PM PST 23
Peak memory 199372 kb
Host smart-1924ae6f-e81f-4fd0-a1f3-018ccb8c0b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891549036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.3891549036
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.169853410
Short name T616
Test name
Test status
Simulation time 97784409 ps
CPU time 1.01 seconds
Started Dec 27 12:48:06 PM PST 23
Finished Dec 27 12:48:15 PM PST 23
Peak memory 199312 kb
Host smart-ebd438fe-de28-4a30-a8c4-05cba443185e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169853410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.169853410
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.3856411212
Short name T412
Test name
Test status
Simulation time 235939924 ps
CPU time 1.41 seconds
Started Dec 27 12:48:02 PM PST 23
Finished Dec 27 12:48:13 PM PST 23
Peak memory 199444 kb
Host smart-71bc61db-7538-4dec-ac63-f5ed543f9c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856411212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.3856411212
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.10157863
Short name T349
Test name
Test status
Simulation time 2500012104 ps
CPU time 8.26 seconds
Started Dec 27 12:47:59 PM PST 23
Finished Dec 27 12:48:17 PM PST 23
Peak memory 199528 kb
Host smart-d7dffce8-7ab0-4467-8b33-5fcef265dd7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10157863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.10157863
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.2220131442
Short name T264
Test name
Test status
Simulation time 468249613 ps
CPU time 2.51 seconds
Started Dec 27 12:48:12 PM PST 23
Finished Dec 27 12:48:22 PM PST 23
Peak memory 199256 kb
Host smart-315c8b25-9bc5-4794-a7fa-d10e00bf6166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220131442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.2220131442
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.1778521704
Short name T14
Test name
Test status
Simulation time 80404534 ps
CPU time 0.8 seconds
Started Dec 27 12:48:09 PM PST 23
Finished Dec 27 12:48:17 PM PST 23
Peak memory 199292 kb
Host smart-c0cba327-2778-4fce-9497-d71ef43dc54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778521704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.1778521704
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.3898369622
Short name T481
Test name
Test status
Simulation time 66155703 ps
CPU time 0.74 seconds
Started Dec 27 12:48:20 PM PST 23
Finished Dec 27 12:48:30 PM PST 23
Peak memory 199088 kb
Host smart-de51380d-8a60-44dd-9428-56a4f47d4e1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898369622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.3898369622
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.3512220503
Short name T58
Test name
Test status
Simulation time 1221706167 ps
CPU time 5.26 seconds
Started Dec 27 12:48:04 PM PST 23
Finished Dec 27 12:48:18 PM PST 23
Peak memory 216668 kb
Host smart-ce984c5c-bb20-43a7-b87a-3f55416d955a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512220503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.3512220503
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.3372691112
Short name T339
Test name
Test status
Simulation time 243749281 ps
CPU time 1.12 seconds
Started Dec 27 12:48:14 PM PST 23
Finished Dec 27 12:48:23 PM PST 23
Peak memory 216352 kb
Host smart-6c364689-f161-498a-8c6c-8935356b1209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372691112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.3372691112
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.2506607701
Short name T499
Test name
Test status
Simulation time 219780314 ps
CPU time 0.87 seconds
Started Dec 27 12:48:05 PM PST 23
Finished Dec 27 12:48:14 PM PST 23
Peak memory 199136 kb
Host smart-edc5b590-eae8-4ae4-9426-aacc1e884383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506607701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.2506607701
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.704938652
Short name T520
Test name
Test status
Simulation time 2344598225 ps
CPU time 8.17 seconds
Started Dec 27 12:48:07 PM PST 23
Finished Dec 27 12:48:23 PM PST 23
Peak memory 199520 kb
Host smart-e5806608-e2f1-4910-bde1-10fb97c4fc27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704938652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.704938652
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.1439161054
Short name T605
Test name
Test status
Simulation time 99781723 ps
CPU time 1 seconds
Started Dec 27 12:48:06 PM PST 23
Finished Dec 27 12:48:15 PM PST 23
Peak memory 199268 kb
Host smart-a9831e24-c44c-4f9d-9cd4-4530e7f08a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439161054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.1439161054
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.726898595
Short name T424
Test name
Test status
Simulation time 186481704 ps
CPU time 1.31 seconds
Started Dec 27 12:47:58 PM PST 23
Finished Dec 27 12:48:10 PM PST 23
Peak memory 199472 kb
Host smart-3fce8ab1-dd33-4f37-84cd-d9f4b086df4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726898595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.726898595
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.1922490280
Short name T366
Test name
Test status
Simulation time 4904024800 ps
CPU time 22.58 seconds
Started Dec 27 12:48:07 PM PST 23
Finished Dec 27 12:48:37 PM PST 23
Peak memory 199480 kb
Host smart-94232bc5-8153-4c65-9f72-0ed39c701a23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922490280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.1922490280
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.691303505
Short name T523
Test name
Test status
Simulation time 122572907 ps
CPU time 1.58 seconds
Started Dec 27 12:48:14 PM PST 23
Finished Dec 27 12:48:23 PM PST 23
Peak memory 199356 kb
Host smart-cf342f8b-a584-4a98-9fa8-715145a2b7d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691303505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.691303505
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.1623275154
Short name T172
Test name
Test status
Simulation time 170483328 ps
CPU time 1.11 seconds
Started Dec 27 12:48:01 PM PST 23
Finished Dec 27 12:48:12 PM PST 23
Peak memory 199272 kb
Host smart-01709658-4a81-4352-9ede-2b4d8de032ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623275154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.1623275154
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.4056460363
Short name T9
Test name
Test status
Simulation time 86066702 ps
CPU time 0.8 seconds
Started Dec 27 12:48:12 PM PST 23
Finished Dec 27 12:48:21 PM PST 23
Peak memory 199084 kb
Host smart-bc410f70-17ee-4896-9281-7c534ca0583e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056460363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.4056460363
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.3913278960
Short name T582
Test name
Test status
Simulation time 1892508559 ps
CPU time 7.89 seconds
Started Dec 27 12:48:24 PM PST 23
Finished Dec 27 12:48:37 PM PST 23
Peak memory 220340 kb
Host smart-73d2b440-7060-4940-87cb-f027e9a6052e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913278960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.3913278960
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.2589895543
Short name T261
Test name
Test status
Simulation time 244203395 ps
CPU time 1.08 seconds
Started Dec 27 12:48:10 PM PST 23
Finished Dec 27 12:48:18 PM PST 23
Peak memory 216432 kb
Host smart-b62bec99-cb2b-43dd-b5b7-e641f6cb52f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589895543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.2589895543
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.3991566870
Short name T308
Test name
Test status
Simulation time 237076432 ps
CPU time 0.92 seconds
Started Dec 27 12:48:11 PM PST 23
Finished Dec 27 12:48:19 PM PST 23
Peak memory 199052 kb
Host smart-4af5fd08-71fb-42e8-aea7-ec3cedcd579e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991566870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.3991566870
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.176217091
Short name T291
Test name
Test status
Simulation time 827028849 ps
CPU time 3.92 seconds
Started Dec 27 12:48:03 PM PST 23
Finished Dec 27 12:48:16 PM PST 23
Peak memory 199512 kb
Host smart-40c9663a-db74-463f-adf4-931e441b7f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176217091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.176217091
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.3560068033
Short name T504
Test name
Test status
Simulation time 108034762 ps
CPU time 0.96 seconds
Started Dec 27 12:48:08 PM PST 23
Finished Dec 27 12:48:17 PM PST 23
Peak memory 199264 kb
Host smart-04d9bd5f-2b33-4d07-89cd-603c82463d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560068033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.3560068033
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.4072709265
Short name T491
Test name
Test status
Simulation time 249607679 ps
CPU time 1.42 seconds
Started Dec 27 12:48:02 PM PST 23
Finished Dec 27 12:48:16 PM PST 23
Peak memory 199412 kb
Host smart-ac40a738-0532-4563-b3fc-0b905c4abcc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072709265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.4072709265
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.2929431192
Short name T614
Test name
Test status
Simulation time 687872818 ps
CPU time 3.5 seconds
Started Dec 27 12:48:07 PM PST 23
Finished Dec 27 12:48:18 PM PST 23
Peak memory 199436 kb
Host smart-c4a429c1-3fbd-401c-b140-e9d69b50098c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929431192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.2929431192
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.461744728
Short name T573
Test name
Test status
Simulation time 129159792 ps
CPU time 1.66 seconds
Started Dec 27 12:48:10 PM PST 23
Finished Dec 27 12:48:18 PM PST 23
Peak memory 199352 kb
Host smart-2dff3de3-c5f3-4220-bd31-c44acc6d0b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461744728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.461744728
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.3556862390
Short name T42
Test name
Test status
Simulation time 133900110 ps
CPU time 0.96 seconds
Started Dec 27 12:48:05 PM PST 23
Finished Dec 27 12:48:14 PM PST 23
Peak memory 199292 kb
Host smart-ece94e4a-8d5c-4ce0-bf32-f375f62247fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556862390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.3556862390
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.2384598804
Short name T421
Test name
Test status
Simulation time 72997901 ps
CPU time 0.79 seconds
Started Dec 27 12:48:08 PM PST 23
Finished Dec 27 12:48:16 PM PST 23
Peak memory 199032 kb
Host smart-469d0c06-aae0-418d-a54c-bc2da4e4e8d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384598804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.2384598804
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.2796823562
Short name T593
Test name
Test status
Simulation time 1223417798 ps
CPU time 5.54 seconds
Started Dec 27 12:48:20 PM PST 23
Finished Dec 27 12:48:32 PM PST 23
Peak memory 217248 kb
Host smart-4936550c-649a-41bf-a277-905f2a54406a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796823562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.2796823562
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.1901199783
Short name T80
Test name
Test status
Simulation time 244619985 ps
CPU time 1.11 seconds
Started Dec 27 12:48:03 PM PST 23
Finished Dec 27 12:48:13 PM PST 23
Peak memory 216452 kb
Host smart-c4b403ef-8baa-4461-9973-556c2a6d0619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901199783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.1901199783
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.818854516
Short name T167
Test name
Test status
Simulation time 187317770 ps
CPU time 0.83 seconds
Started Dec 27 12:48:24 PM PST 23
Finished Dec 27 12:48:30 PM PST 23
Peak memory 199064 kb
Host smart-c562ab84-76bd-48a7-9e54-5856c51dd4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818854516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.818854516
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.3881123896
Short name T321
Test name
Test status
Simulation time 1362252783 ps
CPU time 5.19 seconds
Started Dec 27 12:48:07 PM PST 23
Finished Dec 27 12:48:20 PM PST 23
Peak memory 199464 kb
Host smart-a4765d22-5269-462f-aeb3-4fdbe6b224de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881123896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.3881123896
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.241509415
Short name T394
Test name
Test status
Simulation time 107954192 ps
CPU time 0.95 seconds
Started Dec 27 12:48:20 PM PST 23
Finished Dec 27 12:48:28 PM PST 23
Peak memory 199312 kb
Host smart-d2835567-c980-4c6a-9ef4-9959834e784b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241509415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.241509415
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.1240732136
Short name T73
Test name
Test status
Simulation time 119081278 ps
CPU time 1.15 seconds
Started Dec 27 12:47:57 PM PST 23
Finished Dec 27 12:48:09 PM PST 23
Peak memory 199436 kb
Host smart-c9768d32-1c07-4452-943e-6d2ded0abf69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240732136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.1240732136
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.3075171101
Short name T345
Test name
Test status
Simulation time 5344397550 ps
CPU time 23.47 seconds
Started Dec 27 12:47:59 PM PST 23
Finished Dec 27 12:48:33 PM PST 23
Peak memory 199504 kb
Host smart-4d2ac43b-6584-4ae3-9d7c-c20281b181bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075171101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.3075171101
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.1364871077
Short name T555
Test name
Test status
Simulation time 344905469 ps
CPU time 1.92 seconds
Started Dec 27 12:48:07 PM PST 23
Finished Dec 27 12:48:17 PM PST 23
Peak memory 199224 kb
Host smart-019f3942-c48b-416a-9d58-189b6dff32ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364871077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.1364871077
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.823653597
Short name T496
Test name
Test status
Simulation time 82329758 ps
CPU time 0.9 seconds
Started Dec 27 12:48:29 PM PST 23
Finished Dec 27 12:48:34 PM PST 23
Peak memory 199280 kb
Host smart-36e2e299-c947-4362-9cf4-a2e6da0bf073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823653597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.823653597
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.3586154771
Short name T325
Test name
Test status
Simulation time 58191038 ps
CPU time 0.68 seconds
Started Dec 27 12:48:46 PM PST 23
Finished Dec 27 12:48:48 PM PST 23
Peak memory 199032 kb
Host smart-4e072852-fa82-4030-81e9-bebadc9b57eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586154771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.3586154771
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.3395517004
Short name T35
Test name
Test status
Simulation time 1212080827 ps
CPU time 5.78 seconds
Started Dec 27 12:48:24 PM PST 23
Finished Dec 27 12:48:35 PM PST 23
Peak memory 217716 kb
Host smart-35f3a470-3833-4c31-a27f-55ef87f3866b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395517004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.3395517004
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.954403977
Short name T569
Test name
Test status
Simulation time 244362724 ps
CPU time 1.05 seconds
Started Dec 27 12:48:04 PM PST 23
Finished Dec 27 12:48:14 PM PST 23
Peak memory 216476 kb
Host smart-9aa4de53-3eb2-4f50-83ed-9a179f1363b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954403977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.954403977
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.2966304377
Short name T8
Test name
Test status
Simulation time 121783171 ps
CPU time 0.77 seconds
Started Dec 27 12:48:03 PM PST 23
Finished Dec 27 12:48:13 PM PST 23
Peak memory 199124 kb
Host smart-ab72b384-ca02-4243-bd8c-bdb103284a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966304377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.2966304377
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.1359562694
Short name T118
Test name
Test status
Simulation time 932946618 ps
CPU time 4.45 seconds
Started Dec 27 12:47:53 PM PST 23
Finished Dec 27 12:48:08 PM PST 23
Peak memory 199536 kb
Host smart-5294c0a9-8f08-4f37-b9e1-dc641ddf5ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359562694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.1359562694
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.2575026722
Short name T147
Test name
Test status
Simulation time 256080511 ps
CPU time 1.45 seconds
Started Dec 27 12:48:10 PM PST 23
Finished Dec 27 12:48:19 PM PST 23
Peak memory 199368 kb
Host smart-9538ba9a-7228-4db7-aba5-7c266da736f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575026722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.2575026722
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.329429158
Short name T488
Test name
Test status
Simulation time 409748996 ps
CPU time 2.07 seconds
Started Dec 27 12:48:25 PM PST 23
Finished Dec 27 12:48:32 PM PST 23
Peak memory 199440 kb
Host smart-3b76e91e-0f16-4fb6-a1a5-7cbede97e6f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329429158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.329429158
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.100954203
Short name T305
Test name
Test status
Simulation time 152356649 ps
CPU time 1.72 seconds
Started Dec 27 12:48:00 PM PST 23
Finished Dec 27 12:48:12 PM PST 23
Peak memory 199272 kb
Host smart-d6552527-5a99-4d6d-8827-734dc3f4fc4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100954203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.100954203
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.491519022
Short name T544
Test name
Test status
Simulation time 130161019 ps
CPU time 1.08 seconds
Started Dec 27 12:48:10 PM PST 23
Finished Dec 27 12:48:18 PM PST 23
Peak memory 199324 kb
Host smart-57bc2717-ab59-43fc-976b-22d063451444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491519022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.491519022
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.1896601187
Short name T578
Test name
Test status
Simulation time 63790629 ps
CPU time 0.7 seconds
Started Dec 27 12:48:43 PM PST 23
Finished Dec 27 12:48:46 PM PST 23
Peak memory 199092 kb
Host smart-0bc350d4-4d03-44e6-aa18-6fa44cb84df9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896601187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.1896601187
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.2701472104
Short name T45
Test name
Test status
Simulation time 2347916751 ps
CPU time 8.73 seconds
Started Dec 27 12:48:16 PM PST 23
Finished Dec 27 12:48:36 PM PST 23
Peak memory 216628 kb
Host smart-8f1441a8-6b34-4a96-a7a6-f6a75bc8df2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701472104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.2701472104
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.4015782194
Short name T87
Test name
Test status
Simulation time 245733049 ps
CPU time 1.04 seconds
Started Dec 27 12:48:34 PM PST 23
Finished Dec 27 12:48:39 PM PST 23
Peak memory 216476 kb
Host smart-4c969dd7-10c4-45ed-92ea-61242442c125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015782194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.4015782194
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.113282257
Short name T418
Test name
Test status
Simulation time 121781045 ps
CPU time 0.83 seconds
Started Dec 27 12:48:24 PM PST 23
Finished Dec 27 12:48:35 PM PST 23
Peak memory 199060 kb
Host smart-15668a88-82c8-48c7-b822-3a55debe0ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113282257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.113282257
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.2917570819
Short name T438
Test name
Test status
Simulation time 1461291897 ps
CPU time 5.66 seconds
Started Dec 27 12:48:23 PM PST 23
Finished Dec 27 12:48:35 PM PST 23
Peak memory 199420 kb
Host smart-6fb87b80-13e8-49ae-a0b2-998b2eb69f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917570819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.2917570819
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.222739290
Short name T3
Test name
Test status
Simulation time 97822648 ps
CPU time 0.93 seconds
Started Dec 27 12:48:15 PM PST 23
Finished Dec 27 12:48:23 PM PST 23
Peak memory 199268 kb
Host smart-cbbef9b4-1e50-4e87-b08e-c6897ebed40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222739290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.222739290
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.981994829
Short name T434
Test name
Test status
Simulation time 249650526 ps
CPU time 1.4 seconds
Started Dec 27 12:48:04 PM PST 23
Finished Dec 27 12:48:14 PM PST 23
Peak memory 199380 kb
Host smart-38d7fef5-401b-4a6a-b28b-76dce2e5cabc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981994829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.981994829
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.403111808
Short name T548
Test name
Test status
Simulation time 5013870270 ps
CPU time 24.94 seconds
Started Dec 27 12:48:48 PM PST 23
Finished Dec 27 12:49:15 PM PST 23
Peak memory 199548 kb
Host smart-9881ab29-0308-437f-9e3b-5cc12ce71e47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403111808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.403111808
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.3064798773
Short name T433
Test name
Test status
Simulation time 378285144 ps
CPU time 2.3 seconds
Started Dec 27 12:48:45 PM PST 23
Finished Dec 27 12:48:49 PM PST 23
Peak memory 199224 kb
Host smart-d9ed63bb-4700-49e8-ba7d-bb8be0dacba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064798773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.3064798773
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.3678747467
Short name T273
Test name
Test status
Simulation time 61940526 ps
CPU time 0.75 seconds
Started Dec 27 12:48:35 PM PST 23
Finished Dec 27 12:48:40 PM PST 23
Peak memory 199212 kb
Host smart-b3e6416b-a30d-4abe-9c11-7aa671c794dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678747467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.3678747467
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.3802693557
Short name T262
Test name
Test status
Simulation time 91454066 ps
CPU time 0.84 seconds
Started Dec 27 12:48:15 PM PST 23
Finished Dec 27 12:48:23 PM PST 23
Peak memory 199160 kb
Host smart-ab89c147-8815-49cb-ae76-689bc36acb61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802693557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.3802693557
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.4185602674
Short name T55
Test name
Test status
Simulation time 2348216673 ps
CPU time 7.79 seconds
Started Dec 27 12:48:15 PM PST 23
Finished Dec 27 12:48:30 PM PST 23
Peak memory 216840 kb
Host smart-207b56d5-b26c-40fb-889f-caca286be162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185602674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.4185602674
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.2832664822
Short name T332
Test name
Test status
Simulation time 243371043 ps
CPU time 1.07 seconds
Started Dec 27 12:48:13 PM PST 23
Finished Dec 27 12:48:22 PM PST 23
Peak memory 216608 kb
Host smart-8f77aef8-c23c-477c-a426-64d6af9d6192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832664822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.2832664822
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.1083546646
Short name T160
Test name
Test status
Simulation time 215694818 ps
CPU time 0.93 seconds
Started Dec 27 12:48:09 PM PST 23
Finished Dec 27 12:48:17 PM PST 23
Peak memory 199008 kb
Host smart-e7305969-bc22-486f-952f-4dc44dd2050c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083546646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.1083546646
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.3508063685
Short name T586
Test name
Test status
Simulation time 967783341 ps
CPU time 4.94 seconds
Started Dec 27 12:48:31 PM PST 23
Finished Dec 27 12:48:40 PM PST 23
Peak memory 199432 kb
Host smart-ff08d158-99ea-4e14-8e66-d84582a99902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508063685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.3508063685
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.602657784
Short name T607
Test name
Test status
Simulation time 144706230 ps
CPU time 1.03 seconds
Started Dec 27 12:48:24 PM PST 23
Finished Dec 27 12:48:31 PM PST 23
Peak memory 199248 kb
Host smart-5b5265c5-65f0-4d11-8b2a-8deec9a2b19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602657784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.602657784
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.3453647779
Short name T272
Test name
Test status
Simulation time 251860074 ps
CPU time 1.41 seconds
Started Dec 27 12:48:14 PM PST 23
Finished Dec 27 12:48:23 PM PST 23
Peak memory 199376 kb
Host smart-88387003-60a9-4aae-95a8-d7835c5bd7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453647779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.3453647779
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.3678757325
Short name T457
Test name
Test status
Simulation time 8633731246 ps
CPU time 30.69 seconds
Started Dec 27 12:48:21 PM PST 23
Finished Dec 27 12:48:58 PM PST 23
Peak memory 199612 kb
Host smart-8c877e9d-f5ca-4e98-894d-4bc0c803c48e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678757325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.3678757325
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.3578423548
Short name T145
Test name
Test status
Simulation time 503078601 ps
CPU time 2.55 seconds
Started Dec 27 12:48:17 PM PST 23
Finished Dec 27 12:48:27 PM PST 23
Peak memory 199284 kb
Host smart-4db6d1c8-0b00-438f-839e-a3bba631f3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578423548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.3578423548
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.2358101636
Short name T341
Test name
Test status
Simulation time 175152925 ps
CPU time 1.15 seconds
Started Dec 27 12:48:17 PM PST 23
Finished Dec 27 12:48:25 PM PST 23
Peak memory 199256 kb
Host smart-1acb6907-00b4-4fb8-87ea-eefff96c4a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358101636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.2358101636
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.304559486
Short name T38
Test name
Test status
Simulation time 70790276 ps
CPU time 0.73 seconds
Started Dec 27 12:48:37 PM PST 23
Finished Dec 27 12:48:42 PM PST 23
Peak memory 199072 kb
Host smart-c5d853c7-6104-40f8-b2a9-5605f11311c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304559486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.304559486
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.441996982
Short name T409
Test name
Test status
Simulation time 1228877781 ps
CPU time 5.14 seconds
Started Dec 27 12:48:19 PM PST 23
Finished Dec 27 12:48:32 PM PST 23
Peak memory 216176 kb
Host smart-01b91dcd-65dc-4b18-b8c1-3c1e2093cbc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441996982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.441996982
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.3478687864
Short name T371
Test name
Test status
Simulation time 243945215 ps
CPU time 1.13 seconds
Started Dec 27 12:48:12 PM PST 23
Finished Dec 27 12:48:21 PM PST 23
Peak memory 216564 kb
Host smart-ddb7d2e1-955d-4ab1-8c6a-2f68f67cd788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478687864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.3478687864
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.81953224
Short name T15
Test name
Test status
Simulation time 166314217 ps
CPU time 0.8 seconds
Started Dec 27 12:48:16 PM PST 23
Finished Dec 27 12:48:24 PM PST 23
Peak memory 199124 kb
Host smart-495576e9-d057-4a92-9d7f-fd95fa034816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81953224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.81953224
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.944325819
Short name T596
Test name
Test status
Simulation time 1983872334 ps
CPU time 6.75 seconds
Started Dec 27 12:48:12 PM PST 23
Finished Dec 27 12:48:27 PM PST 23
Peak memory 199468 kb
Host smart-767ef739-9864-4092-ae9b-270a441c5016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944325819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.944325819
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.1414261543
Short name T153
Test name
Test status
Simulation time 98067162 ps
CPU time 0.96 seconds
Started Dec 27 12:49:16 PM PST 23
Finished Dec 27 12:49:25 PM PST 23
Peak memory 199324 kb
Host smart-7dfdf7d1-8c4f-4f01-aacd-cf58b747a6f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414261543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.1414261543
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.2077669087
Short name T60
Test name
Test status
Simulation time 251787592 ps
CPU time 1.63 seconds
Started Dec 27 12:48:40 PM PST 23
Finished Dec 27 12:48:44 PM PST 23
Peak memory 199472 kb
Host smart-89c6de25-5b6a-4249-b374-fe0cb6f2336e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077669087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.2077669087
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.3034121969
Short name T251
Test name
Test status
Simulation time 103480510 ps
CPU time 1.13 seconds
Started Dec 27 12:48:20 PM PST 23
Finished Dec 27 12:48:28 PM PST 23
Peak memory 199240 kb
Host smart-73b5b2ea-6ae9-4d75-b5f5-d3f608528424
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034121969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.3034121969
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.734575611
Short name T408
Test name
Test status
Simulation time 375663087 ps
CPU time 2.31 seconds
Started Dec 27 12:48:18 PM PST 23
Finished Dec 27 12:48:27 PM PST 23
Peak memory 199296 kb
Host smart-957dd69d-34f1-4170-bcb0-214d18df161b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734575611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.734575611
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.527795184
Short name T588
Test name
Test status
Simulation time 113280445 ps
CPU time 0.99 seconds
Started Dec 27 12:48:26 PM PST 23
Finished Dec 27 12:48:31 PM PST 23
Peak memory 199316 kb
Host smart-cdfd5736-e924-4139-a952-77bd34884242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527795184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.527795184
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.1677937614
Short name T558
Test name
Test status
Simulation time 71749378 ps
CPU time 0.75 seconds
Started Dec 27 12:47:11 PM PST 23
Finished Dec 27 12:47:22 PM PST 23
Peak memory 199132 kb
Host smart-7551fff0-b6e8-4d2e-bf66-1863b0878e33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677937614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.1677937614
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.3173549301
Short name T461
Test name
Test status
Simulation time 1905004764 ps
CPU time 6.58 seconds
Started Dec 27 12:47:09 PM PST 23
Finished Dec 27 12:47:27 PM PST 23
Peak memory 220184 kb
Host smart-e55346ea-cae1-422f-9a29-f83de178c35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173549301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.3173549301
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.1253180060
Short name T515
Test name
Test status
Simulation time 243113255 ps
CPU time 1.11 seconds
Started Dec 27 12:47:03 PM PST 23
Finished Dec 27 12:47:19 PM PST 23
Peak memory 216580 kb
Host smart-6ebca5ca-8664-4b6c-a3c5-c45de2e7d26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253180060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.1253180060
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.731755296
Short name T561
Test name
Test status
Simulation time 186706899 ps
CPU time 0.87 seconds
Started Dec 27 12:47:11 PM PST 23
Finished Dec 27 12:47:22 PM PST 23
Peak memory 199136 kb
Host smart-116d7d52-52b4-4cd5-9e07-80148615bf3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731755296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.731755296
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.1688261718
Short name T494
Test name
Test status
Simulation time 1123039358 ps
CPU time 4.61 seconds
Started Dec 27 12:47:08 PM PST 23
Finished Dec 27 12:47:24 PM PST 23
Peak memory 199400 kb
Host smart-af6f6cad-a979-496e-bcb3-0767fa139b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688261718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.1688261718
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.1452960341
Short name T266
Test name
Test status
Simulation time 135165577 ps
CPU time 1.07 seconds
Started Dec 27 12:47:18 PM PST 23
Finished Dec 27 12:47:31 PM PST 23
Peak memory 199304 kb
Host smart-17c2c7f3-0b54-477e-b64c-9bdf9f4cd8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452960341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.1452960341
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.2736969296
Short name T338
Test name
Test status
Simulation time 256566690 ps
CPU time 1.5 seconds
Started Dec 27 12:47:11 PM PST 23
Finished Dec 27 12:47:23 PM PST 23
Peak memory 199432 kb
Host smart-ce530d56-abe9-4b20-8241-76a277e76aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736969296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.2736969296
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.2553345236
Short name T1
Test name
Test status
Simulation time 222403178 ps
CPU time 1.54 seconds
Started Dec 27 12:47:11 PM PST 23
Finished Dec 27 12:47:24 PM PST 23
Peak memory 199224 kb
Host smart-1b912080-3810-48e8-8bc4-17c672f2a29f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553345236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.2553345236
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.3686886573
Short name T519
Test name
Test status
Simulation time 270028998 ps
CPU time 1.82 seconds
Started Dec 27 12:47:17 PM PST 23
Finished Dec 27 12:47:30 PM PST 23
Peak memory 199188 kb
Host smart-3e694fd2-e7cf-4f4f-a7e8-2a46d557ac4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686886573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.3686886573
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.2222198601
Short name T165
Test name
Test status
Simulation time 148621115 ps
CPU time 1.14 seconds
Started Dec 27 12:47:11 PM PST 23
Finished Dec 27 12:47:22 PM PST 23
Peak memory 199260 kb
Host smart-bb72931b-d031-468f-8c8f-d61a07c91ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222198601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.2222198601
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.801560771
Short name T542
Test name
Test status
Simulation time 89610537 ps
CPU time 0.83 seconds
Started Dec 27 12:47:17 PM PST 23
Finished Dec 27 12:47:30 PM PST 23
Peak memory 199120 kb
Host smart-736a025c-53c9-4ed4-b486-ddc01f476ec4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801560771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.801560771
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.1151967347
Short name T30
Test name
Test status
Simulation time 1236905829 ps
CPU time 5.63 seconds
Started Dec 27 12:47:02 PM PST 23
Finished Dec 27 12:47:23 PM PST 23
Peak memory 217652 kb
Host smart-90160322-c9fc-4de3-8114-22d63a349c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151967347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.1151967347
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.2654262970
Short name T351
Test name
Test status
Simulation time 243859943 ps
CPU time 1.06 seconds
Started Dec 27 12:47:10 PM PST 23
Finished Dec 27 12:47:22 PM PST 23
Peak memory 216568 kb
Host smart-71029237-fffb-4628-8817-0f4f3b13d8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654262970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.2654262970
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.195874535
Short name T423
Test name
Test status
Simulation time 143331885 ps
CPU time 0.81 seconds
Started Dec 27 12:47:03 PM PST 23
Finished Dec 27 12:47:18 PM PST 23
Peak memory 199120 kb
Host smart-43cd61bd-7e73-499e-a513-5a63c19e5c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195874535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.195874535
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.2971610380
Short name T260
Test name
Test status
Simulation time 855663124 ps
CPU time 4.04 seconds
Started Dec 27 12:47:10 PM PST 23
Finished Dec 27 12:47:24 PM PST 23
Peak memory 199468 kb
Host smart-8a3a6093-2f18-49f8-9764-02815c258821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971610380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.2971610380
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.3306951563
Short name T509
Test name
Test status
Simulation time 178582123 ps
CPU time 1.11 seconds
Started Dec 27 12:47:08 PM PST 23
Finished Dec 27 12:47:21 PM PST 23
Peak memory 199332 kb
Host smart-246771f1-f750-4e0e-9b01-19af4c1945e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306951563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.3306951563
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.4138147369
Short name T490
Test name
Test status
Simulation time 112624164 ps
CPU time 1.14 seconds
Started Dec 27 12:47:16 PM PST 23
Finished Dec 27 12:47:29 PM PST 23
Peak memory 199376 kb
Host smart-ee80a66f-4086-46d7-a29a-04453602c280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138147369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.4138147369
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.2540898475
Short name T549
Test name
Test status
Simulation time 263815655 ps
CPU time 1.76 seconds
Started Dec 27 12:47:03 PM PST 23
Finished Dec 27 12:47:19 PM PST 23
Peak memory 199200 kb
Host smart-fca0ca14-2236-4f68-a502-85cc7688996a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540898475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.2540898475
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.127687200
Short name T253
Test name
Test status
Simulation time 86776674 ps
CPU time 0.87 seconds
Started Dec 27 12:47:02 PM PST 23
Finished Dec 27 12:47:18 PM PST 23
Peak memory 199320 kb
Host smart-df7b8fc0-9354-40bc-9cb6-dd240e6b6f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127687200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.127687200
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.1606758549
Short name T369
Test name
Test status
Simulation time 81617676 ps
CPU time 0.79 seconds
Started Dec 27 12:47:11 PM PST 23
Finished Dec 27 12:47:22 PM PST 23
Peak memory 199084 kb
Host smart-8430ddbd-ba60-4070-801d-21abe5f8b9ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606758549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.1606758549
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.3461277598
Short name T486
Test name
Test status
Simulation time 1880914962 ps
CPU time 7.21 seconds
Started Dec 27 12:47:17 PM PST 23
Finished Dec 27 12:47:36 PM PST 23
Peak memory 216252 kb
Host smart-2404274a-5be8-4e56-9d31-83473bf9f2d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461277598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.3461277598
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.1861749393
Short name T527
Test name
Test status
Simulation time 244202566 ps
CPU time 1.03 seconds
Started Dec 27 12:47:17 PM PST 23
Finished Dec 27 12:47:30 PM PST 23
Peak memory 216408 kb
Host smart-a5a37b1f-b5dd-4357-86be-9ea6cf123e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861749393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.1861749393
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.1787347623
Short name T320
Test name
Test status
Simulation time 187241885 ps
CPU time 0.9 seconds
Started Dec 27 12:47:12 PM PST 23
Finished Dec 27 12:47:25 PM PST 23
Peak memory 199084 kb
Host smart-80c66da5-248a-4daf-bf20-804a95f70f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787347623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.1787347623
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.381604619
Short name T530
Test name
Test status
Simulation time 851919531 ps
CPU time 4.48 seconds
Started Dec 27 12:47:21 PM PST 23
Finished Dec 27 12:47:36 PM PST 23
Peak memory 199476 kb
Host smart-5d508f4d-6b01-4bd7-bc91-2d026d3c943c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381604619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.381604619
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.1480069683
Short name T296
Test name
Test status
Simulation time 166238105 ps
CPU time 1.11 seconds
Started Dec 27 12:47:16 PM PST 23
Finished Dec 27 12:47:29 PM PST 23
Peak memory 199208 kb
Host smart-a45c5249-8616-4204-9136-e6ebdeefc6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480069683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.1480069683
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.3704146603
Short name T395
Test name
Test status
Simulation time 201486778 ps
CPU time 1.31 seconds
Started Dec 27 12:47:05 PM PST 23
Finished Dec 27 12:47:20 PM PST 23
Peak memory 199400 kb
Host smart-5a40638c-5c47-4bdc-b1b4-29fef15e9b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704146603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.3704146603
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.372576509
Short name T154
Test name
Test status
Simulation time 121740051 ps
CPU time 1.03 seconds
Started Dec 27 12:47:17 PM PST 23
Finished Dec 27 12:47:30 PM PST 23
Peak memory 199252 kb
Host smart-e624844d-756c-45c9-a853-b5ac4a934395
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372576509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.372576509
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.278980880
Short name T100
Test name
Test status
Simulation time 370199431 ps
CPU time 2.42 seconds
Started Dec 27 12:47:14 PM PST 23
Finished Dec 27 12:47:29 PM PST 23
Peak memory 199200 kb
Host smart-99f8f923-5035-4071-b05f-23fe917f26a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278980880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.278980880
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.1625134364
Short name T404
Test name
Test status
Simulation time 118235571 ps
CPU time 0.94 seconds
Started Dec 27 12:47:12 PM PST 23
Finished Dec 27 12:47:24 PM PST 23
Peak memory 199268 kb
Host smart-f5957e0b-dd25-4c3d-b748-f13313964533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625134364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.1625134364
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.224215334
Short name T365
Test name
Test status
Simulation time 79082720 ps
CPU time 0.76 seconds
Started Dec 27 12:47:13 PM PST 23
Finished Dec 27 12:47:26 PM PST 23
Peak memory 199104 kb
Host smart-923492aa-1457-4a8e-9561-df5a451e029f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224215334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.224215334
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.4023888564
Short name T34
Test name
Test status
Simulation time 2358515901 ps
CPU time 8.33 seconds
Started Dec 27 12:47:18 PM PST 23
Finished Dec 27 12:47:38 PM PST 23
Peak memory 221336 kb
Host smart-554ccacf-5eb4-46b0-973e-f8078fa2fa57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023888564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.4023888564
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.3905163282
Short name T451
Test name
Test status
Simulation time 243154418 ps
CPU time 1.11 seconds
Started Dec 27 12:47:17 PM PST 23
Finished Dec 27 12:47:30 PM PST 23
Peak memory 216428 kb
Host smart-e001e240-d085-49a5-af1e-936690fbf7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905163282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.3905163282
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.2450414276
Short name T580
Test name
Test status
Simulation time 93023066 ps
CPU time 0.74 seconds
Started Dec 27 12:47:10 PM PST 23
Finished Dec 27 12:47:21 PM PST 23
Peak memory 199084 kb
Host smart-d72c7e8d-cfae-43bc-9aa0-22a909912369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450414276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.2450414276
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.2383897373
Short name T611
Test name
Test status
Simulation time 1016548267 ps
CPU time 4.93 seconds
Started Dec 27 12:47:11 PM PST 23
Finished Dec 27 12:47:26 PM PST 23
Peak memory 199372 kb
Host smart-655d5c33-ed36-492e-a880-133fe1ef0d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383897373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.2383897373
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.2124193730
Short name T428
Test name
Test status
Simulation time 186649121 ps
CPU time 1.21 seconds
Started Dec 27 12:47:18 PM PST 23
Finished Dec 27 12:47:30 PM PST 23
Peak memory 199332 kb
Host smart-1928739f-18fb-4e62-a67c-fd2bcd5be490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124193730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.2124193730
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.3392861107
Short name T98
Test name
Test status
Simulation time 252078297 ps
CPU time 1.46 seconds
Started Dec 27 12:47:20 PM PST 23
Finished Dec 27 12:47:33 PM PST 23
Peak memory 199432 kb
Host smart-47aa21c0-6993-489f-80f6-b3233f8c4a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392861107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.3392861107
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.3857070856
Short name T572
Test name
Test status
Simulation time 159573203 ps
CPU time 1.08 seconds
Started Dec 27 12:47:19 PM PST 23
Finished Dec 27 12:47:31 PM PST 23
Peak memory 199248 kb
Host smart-6b26e009-7b18-4380-bebb-5cad4c5f24d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857070856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.3857070856
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.2675995389
Short name T577
Test name
Test status
Simulation time 345530610 ps
CPU time 2.11 seconds
Started Dec 27 12:47:10 PM PST 23
Finished Dec 27 12:47:23 PM PST 23
Peak memory 199312 kb
Host smart-53210d8c-ba52-41a6-a61e-22c1663716c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675995389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.2675995389
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.2930385526
Short name T453
Test name
Test status
Simulation time 123112553 ps
CPU time 0.97 seconds
Started Dec 27 12:47:11 PM PST 23
Finished Dec 27 12:47:23 PM PST 23
Peak memory 199348 kb
Host smart-92d773b3-73a0-4dbf-b9bf-f8534a662e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930385526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.2930385526
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.2794079417
Short name T163
Test name
Test status
Simulation time 66957406 ps
CPU time 0.76 seconds
Started Dec 27 12:47:26 PM PST 23
Finished Dec 27 12:47:36 PM PST 23
Peak memory 199100 kb
Host smart-0119a3e0-c5d6-49fe-b046-1138f2e12bc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794079417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.2794079417
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.749823853
Short name T562
Test name
Test status
Simulation time 1887459951 ps
CPU time 7.11 seconds
Started Dec 27 12:47:17 PM PST 23
Finished Dec 27 12:47:35 PM PST 23
Peak memory 221284 kb
Host smart-0fc00134-ab0d-494b-821d-ef60066d6f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749823853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.749823853
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.2872713652
Short name T563
Test name
Test status
Simulation time 244662562 ps
CPU time 1.06 seconds
Started Dec 27 12:47:30 PM PST 23
Finished Dec 27 12:47:40 PM PST 23
Peak memory 216476 kb
Host smart-41d20476-45e3-442f-9683-0cf43e985e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872713652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.2872713652
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.3973945241
Short name T277
Test name
Test status
Simulation time 81656507 ps
CPU time 0.72 seconds
Started Dec 27 12:47:18 PM PST 23
Finished Dec 27 12:47:30 PM PST 23
Peak memory 199152 kb
Host smart-34621f89-ba64-44be-9878-7e803c588c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973945241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.3973945241
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.3420114235
Short name T452
Test name
Test status
Simulation time 1488088654 ps
CPU time 5.48 seconds
Started Dec 27 12:47:17 PM PST 23
Finished Dec 27 12:47:34 PM PST 23
Peak memory 199372 kb
Host smart-c7bc2b64-1683-41bd-9a67-c76766feb287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420114235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.3420114235
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.1635814772
Short name T274
Test name
Test status
Simulation time 153000297 ps
CPU time 1.06 seconds
Started Dec 27 12:47:10 PM PST 23
Finished Dec 27 12:47:22 PM PST 23
Peak memory 199308 kb
Host smart-a8b22076-179c-4f93-b884-64160e7eba6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635814772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.1635814772
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.3874120720
Short name T162
Test name
Test status
Simulation time 116035622 ps
CPU time 1.12 seconds
Started Dec 27 12:47:17 PM PST 23
Finished Dec 27 12:47:30 PM PST 23
Peak memory 199412 kb
Host smart-6b7b96b4-511f-49c3-834c-6b93dbf45323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874120720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.3874120720
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.1606783159
Short name T114
Test name
Test status
Simulation time 5392704214 ps
CPU time 22.09 seconds
Started Dec 27 12:47:31 PM PST 23
Finished Dec 27 12:48:02 PM PST 23
Peak memory 199592 kb
Host smart-411884b2-8a5c-42b2-85e9-32dc88324437
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606783159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.1606783159
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.2300195859
Short name T323
Test name
Test status
Simulation time 405366198 ps
CPU time 2.42 seconds
Started Dec 27 12:47:09 PM PST 23
Finished Dec 27 12:47:22 PM PST 23
Peak memory 199256 kb
Host smart-d48d8bf7-feca-4cd8-b8df-648edba4143c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300195859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.2300195859
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.125409093
Short name T304
Test name
Test status
Simulation time 66455692 ps
CPU time 0.77 seconds
Started Dec 27 12:47:19 PM PST 23
Finished Dec 27 12:47:31 PM PST 23
Peak memory 199268 kb
Host smart-052ac45b-70c9-420b-b185-826e2305abd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125409093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.125409093
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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