Group : rstmgr_env_pkg::rstmgr_env_cov::reset_stretcher_cg
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Group : rstmgr_env_pkg::rstmgr_env_cov::reset_stretcher_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv



Summary for Group rstmgr_env_pkg::rstmgr_env_cov::reset_stretcher_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00


Variables for Group rstmgr_env_pkg::rstmgr_env_cov::reset_stretcher_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
count_cp 4 0 4 100.00 100 1 1 0
length_cp 8 0 8 100.00 100 1 1 0


Summary for Variable count_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for count_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
others 8618 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
cb[0] 1149 1 T1 1 T2 1 T3 1
cb[1] 1031 1 T5 4 T9 4 T12 4
cb[2] 972 1 T5 4 T9 4 T12 4
cb[3] 906 1 T5 4 T9 4 T12 4



Summary for Variable length_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for length_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
others 10356 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
lb[0] 356 1 T9 1 T12 1 T13 1
lb[1] 311 1 T5 1 T9 4 T12 1
lb[2] 285 1 T9 2 T13 2 T14 2
lb[3] 258 1 T11 1 T14 1 T15 2
lb[4] 307 1 T9 3 T15 2 T33 1
lb[5] 280 1 T5 1 T9 1 T13 3
lb[6] 299 1 T5 2 T13 2 T15 2
lb[7] 224 1 T5 2 T9 1 T14 2

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