Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6703

1

T5

31

T7

14

T9

148

auto[1]

9701

1

T2

4

T3

4

T5

27

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5165	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	5489	1			T1	1		T2	2		T3	2
reset_info_cp[2]	2572	1			T2	1		T3	1		T5	9
reset_info_cp[4]	3273	1			T2	1		T3	1		T5	9
reset_info_cp[8]	100	1			T9	2		T13	1		T43	2
reset_info_cp[16]	91	1			T7	1		T9	1		T13	1
reset_info_cp[32]	112	1			T11	1		T13	3		T14	1
reset_info_cp[64]	81	1			T9	2		T44	1		T94	1
reset_info_cp[128]	74	1			T9	1		T13	1		T27	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	2595	1			T5	13		T9	49		T11	11
reset_info_cp[1]	auto[1]	2341	1			T2	1		T3	1		T5	12
reset_info_cp[2]	auto[0]	682	1			T5	4		T9	23		T11	3
reset_info_cp[2]	auto[1]	1890	1			T2	1		T3	1		T5	5
reset_info_cp[4]	auto[0]	1124	1			T5	3		T9	29		T11	4
reset_info_cp[4]	auto[1]	2149	1			T2	1		T3	1		T5	6
reset_info_cp[8]	auto[0]	41	1			T43	1		T127	1		T130	1
reset_info_cp[8]	auto[1]	59	1			T9	2		T13	1		T43	1
reset_info_cp[16]	auto[0]	33	1			T7	1		T15	1		T91	1
reset_info_cp[16]	auto[1]	58	1			T9	1		T13	1		T129	1
reset_info_cp[32]	auto[0]	40	1			T91	1		T27	1		T131	2
reset_info_cp[32]	auto[1]	72	1			T11	1		T13	3		T14	1
reset_info_cp[64]	auto[0]	34	1			T44	1		T94	1		T127	1
reset_info_cp[64]	auto[1]	47	1			T9	2		T132	1		T131	1
reset_info_cp[128]	auto[0]	24	1			T27	1		T127	2		T131	1
reset_info_cp[128]	auto[1]	50	1			T9	1		T13	1		T63	1