Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.88 99.83 99.46 98.77


Total test records in report: 553
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html
T502 /workspace/coverage/default/1.rstmgr_stress_all.416619179 Jan 07 12:56:26 PM PST 24 Jan 07 12:58:14 PM PST 24 6240210528 ps
T503 /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.1439741704 Jan 07 12:56:39 PM PST 24 Jan 07 12:58:28 PM PST 24 244233881 ps
T504 /workspace/coverage/default/14.rstmgr_smoke.3022575821 Jan 07 12:56:27 PM PST 24 Jan 07 12:58:11 PM PST 24 247750299 ps
T505 /workspace/coverage/default/28.rstmgr_smoke.710874225 Jan 07 12:56:43 PM PST 24 Jan 07 12:58:17 PM PST 24 202737542 ps
T506 /workspace/coverage/default/13.rstmgr_por_stretcher.2786886979 Jan 07 12:56:55 PM PST 24 Jan 07 12:58:14 PM PST 24 204951646 ps
T507 /workspace/coverage/default/5.rstmgr_por_stretcher.1090851911 Jan 07 12:56:30 PM PST 24 Jan 07 12:58:18 PM PST 24 147620019 ps
T508 /workspace/coverage/default/32.rstmgr_por_stretcher.2580252962 Jan 07 12:57:17 PM PST 24 Jan 07 12:58:42 PM PST 24 220108293 ps
T509 /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.2664227920 Jan 07 12:56:03 PM PST 24 Jan 07 12:58:07 PM PST 24 245830916 ps
T510 /workspace/coverage/default/16.rstmgr_sw_rst.4096241 Jan 07 12:56:42 PM PST 24 Jan 07 12:58:12 PM PST 24 367942527 ps
T511 /workspace/coverage/default/45.rstmgr_reset.1653222177 Jan 07 12:57:50 PM PST 24 Jan 07 12:59:21 PM PST 24 1911787398 ps
T512 /workspace/coverage/default/7.rstmgr_smoke.2296811221 Jan 07 12:56:15 PM PST 24 Jan 07 12:57:46 PM PST 24 203148238 ps
T513 /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.1941342456 Jan 07 12:57:02 PM PST 24 Jan 07 12:58:34 PM PST 24 1882873587 ps
T514 /workspace/coverage/default/23.rstmgr_smoke.2909371172 Jan 07 12:56:43 PM PST 24 Jan 07 12:58:09 PM PST 24 229697158 ps
T515 /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.3137143379 Jan 07 12:56:44 PM PST 24 Jan 07 12:58:07 PM PST 24 188661121 ps
T516 /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.2383060228 Jan 07 12:56:39 PM PST 24 Jan 07 12:58:01 PM PST 24 243742164 ps
T517 /workspace/coverage/default/34.rstmgr_alert_test.3589960556 Jan 07 12:57:26 PM PST 24 Jan 07 12:59:13 PM PST 24 60446374 ps
T518 /workspace/coverage/default/43.rstmgr_alert_test.1457807308 Jan 07 12:57:41 PM PST 24 Jan 07 12:59:22 PM PST 24 61563343 ps
T519 /workspace/coverage/default/23.rstmgr_por_stretcher.2800518462 Jan 07 12:56:42 PM PST 24 Jan 07 12:58:38 PM PST 24 157995343 ps
T520 /workspace/coverage/default/26.rstmgr_reset.1084639391 Jan 07 12:56:59 PM PST 24 Jan 07 12:58:41 PM PST 24 1839708524 ps
T521 /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.1678362590 Jan 07 12:56:33 PM PST 24 Jan 07 12:58:04 PM PST 24 126788327 ps
T522 /workspace/coverage/default/32.rstmgr_reset.1475503924 Jan 07 12:57:19 PM PST 24 Jan 07 12:59:06 PM PST 24 1247794239 ps
T523 /workspace/coverage/default/30.rstmgr_por_stretcher.2452771369 Jan 07 12:57:25 PM PST 24 Jan 07 12:58:52 PM PST 24 91414433 ps
T524 /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.1069399391 Jan 07 12:57:20 PM PST 24 Jan 07 12:58:52 PM PST 24 2351553781 ps
T525 /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.2372395160 Jan 07 12:58:06 PM PST 24 Jan 07 12:59:37 PM PST 24 245368559 ps
T526 /workspace/coverage/default/37.rstmgr_smoke.863056399 Jan 07 12:57:46 PM PST 24 Jan 07 12:59:10 PM PST 24 110817639 ps
T527 /workspace/coverage/default/28.rstmgr_stress_all.2984748209 Jan 07 12:56:49 PM PST 24 Jan 07 12:58:34 PM PST 24 4656521639 ps
T528 /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.2732584282 Jan 07 12:56:42 PM PST 24 Jan 07 12:58:29 PM PST 24 1893798134 ps
T529 /workspace/coverage/default/12.rstmgr_smoke.4007069492 Jan 07 12:56:43 PM PST 24 Jan 07 12:58:16 PM PST 24 203705346 ps
T530 /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.225027997 Jan 07 12:57:42 PM PST 24 Jan 07 12:59:16 PM PST 24 156326885 ps
T531 /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.4294956435 Jan 07 12:58:13 PM PST 24 Jan 07 12:59:38 PM PST 24 243864155 ps
T532 /workspace/coverage/default/11.rstmgr_por_stretcher.3857070965 Jan 07 12:56:08 PM PST 24 Jan 07 12:57:56 PM PST 24 114912586 ps
T533 /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.677196876 Jan 07 12:57:45 PM PST 24 Jan 07 12:59:06 PM PST 24 175000290 ps
T534 /workspace/coverage/default/4.rstmgr_por_stretcher.3236757749 Jan 07 12:56:09 PM PST 24 Jan 07 12:58:00 PM PST 24 89147519 ps
T535 /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.3340870022 Jan 07 12:56:08 PM PST 24 Jan 07 12:57:33 PM PST 24 179691388 ps
T536 /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.438778623 Jan 07 12:57:18 PM PST 24 Jan 07 12:58:37 PM PST 24 223538368 ps
T537 /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.650890751 Jan 07 12:56:40 PM PST 24 Jan 07 12:58:22 PM PST 24 243865794 ps
T538 /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.2289272780 Jan 07 12:57:24 PM PST 24 Jan 07 12:59:00 PM PST 24 1220953648 ps
T539 /workspace/coverage/default/6.rstmgr_alert_test.3940898862 Jan 07 12:56:14 PM PST 24 Jan 07 12:57:46 PM PST 24 66607862 ps
T540 /workspace/coverage/default/23.rstmgr_stress_all.473689102 Jan 07 12:56:59 PM PST 24 Jan 07 12:58:42 PM PST 24 3994432361 ps
T541 /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.1580244645 Jan 07 12:55:51 PM PST 24 Jan 07 12:57:54 PM PST 24 1893130791 ps
T542 /workspace/coverage/default/48.rstmgr_alert_test.2965787006 Jan 07 12:57:47 PM PST 24 Jan 07 12:59:33 PM PST 24 66654272 ps
T543 /workspace/coverage/default/10.rstmgr_stress_all.2931877798 Jan 07 12:56:11 PM PST 24 Jan 07 12:58:02 PM PST 24 1002294478 ps
T544 /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.973227126 Jan 07 12:56:39 PM PST 24 Jan 07 12:58:01 PM PST 24 138655314 ps
T545 /workspace/coverage/default/8.rstmgr_stress_all.1599938247 Jan 07 12:56:38 PM PST 24 Jan 07 12:58:50 PM PST 24 7235098275 ps
T83 /workspace/coverage/default/3.rstmgr_sec_cm.2983113517 Jan 07 12:56:36 PM PST 24 Jan 07 12:58:56 PM PST 24 16593629762 ps
T546 /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.2421176116 Jan 07 12:56:43 PM PST 24 Jan 07 12:58:17 PM PST 24 1904373426 ps
T547 /workspace/coverage/default/38.rstmgr_alert_test.276614943 Jan 07 12:57:43 PM PST 24 Jan 07 12:59:14 PM PST 24 72189863 ps
T548 /workspace/coverage/default/27.rstmgr_reset.3882453751 Jan 07 12:57:05 PM PST 24 Jan 07 12:58:33 PM PST 24 1885496149 ps
T549 /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.3799544988 Jan 07 12:56:41 PM PST 24 Jan 07 12:58:08 PM PST 24 244281840 ps
T550 /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.3879297199 Jan 07 12:56:39 PM PST 24 Jan 07 12:58:01 PM PST 24 182780819 ps
T551 /workspace/coverage/default/2.rstmgr_reset.1505495059 Jan 07 12:56:25 PM PST 24 Jan 07 12:58:21 PM PST 24 1890459290 ps
T552 /workspace/coverage/default/30.rstmgr_smoke.2889979255 Jan 07 12:57:18 PM PST 24 Jan 07 12:58:43 PM PST 24 254861218 ps
T553 /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.1011566409 Jan 07 12:57:42 PM PST 24 Jan 07 12:59:07 PM PST 24 1228786956 ps

Test location /workspace/coverage/default/26.rstmgr_stress_all.1646451375
Short name T9
Test name
Test status
Simulation time 10453157592 ps
CPU time 38.21 seconds
Started Jan 07 12:56:40 PM PST 24
Finished Jan 07 12:59:05 PM PST 24
Peak memory 199568 kb
Host smart-b3bc8685-84e6-4bf4-9497-09e2b62d195c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646451375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.1646451375
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.2525260839
Short name T10
Test name
Test status
Simulation time 255834415 ps
CPU time 1.66 seconds
Started Jan 07 12:58:13 PM PST 24
Finished Jan 07 12:59:44 PM PST 24
Peak memory 199308 kb
Host smart-7c6fe15e-a2af-4dd4-83bf-90e971d7d0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525260839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.2525260839
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.54495842
Short name T73
Test name
Test status
Simulation time 878779040 ps
CPU time 2.82 seconds
Started Jan 07 12:29:51 PM PST 24
Finished Jan 07 12:31:21 PM PST 24
Peak memory 198924 kb
Host smart-ff180082-a6a1-4ab6-a5f7-a94862111d00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54495842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err.54495842
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.453959609
Short name T79
Test name
Test status
Simulation time 16507165487 ps
CPU time 30.07 seconds
Started Jan 07 12:56:01 PM PST 24
Finished Jan 07 12:58:14 PM PST 24
Peak memory 217252 kb
Host smart-7645355d-2fd2-4203-9b73-acdf25212847
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453959609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.453959609
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.1412154449
Short name T33
Test name
Test status
Simulation time 1219871194 ps
CPU time 5.65 seconds
Started Jan 07 12:56:39 PM PST 24
Finished Jan 07 12:58:34 PM PST 24
Peak memory 221380 kb
Host smart-0b578cb3-5fc7-4e82-90fa-ed6d5b3b87fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412154449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.1412154449
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3741694127
Short name T74
Test name
Test status
Simulation time 509959483 ps
CPU time 3.48 seconds
Started Jan 07 12:30:56 PM PST 24
Finished Jan 07 12:32:40 PM PST 24
Peak memory 198664 kb
Host smart-1f5ecf4f-1b47-40fc-86f0-55f906035a65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741694127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.3741694127
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.1043094016
Short name T220
Test name
Test status
Simulation time 11103791480 ps
CPU time 40.19 seconds
Started Jan 07 12:56:05 PM PST 24
Finished Jan 07 12:58:19 PM PST 24
Peak memory 199636 kb
Host smart-ecd5db51-9faf-44ef-ae2a-6cce5f05e7bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043094016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.1043094016
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.2979926446
Short name T32
Test name
Test status
Simulation time 68619113 ps
CPU time 0.71 seconds
Started Jan 07 12:56:39 PM PST 24
Finished Jan 07 12:58:12 PM PST 24
Peak memory 199216 kb
Host smart-30891d13-1933-40cc-b3d1-b7d9f5224133
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979926446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.2979926446
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.2583254996
Short name T67
Test name
Test status
Simulation time 164194389 ps
CPU time 1.12 seconds
Started Jan 07 12:56:33 PM PST 24
Finished Jan 07 12:58:07 PM PST 24
Peak memory 199348 kb
Host smart-c86665ec-8bc8-4e40-8828-a0e83dbe415a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583254996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.2583254996
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2033838623
Short name T118
Test name
Test status
Simulation time 900536203 ps
CPU time 2.79 seconds
Started Jan 07 12:26:52 PM PST 24
Finished Jan 07 12:28:11 PM PST 24
Peak memory 199268 kb
Host smart-1b5c3696-6978-41c7-9a65-5a352e80e9fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033838623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.2033838623
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.1885608689
Short name T46
Test name
Test status
Simulation time 1215992030 ps
CPU time 5.28 seconds
Started Jan 07 12:57:38 PM PST 24
Finished Jan 07 12:59:21 PM PST 24
Peak memory 221348 kb
Host smart-71ca41a1-e031-46aa-a3a7-ee973086a145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885608689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.1885608689
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.1109912443
Short name T91
Test name
Test status
Simulation time 204285460 ps
CPU time 1.21 seconds
Started Jan 07 12:55:51 PM PST 24
Finished Jan 07 12:57:54 PM PST 24
Peak memory 199212 kb
Host smart-7592bfbc-1bef-4e4a-9b90-0b994e4bb716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109912443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.1109912443
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.2661253561
Short name T19
Test name
Test status
Simulation time 220866373 ps
CPU time 0.91 seconds
Started Jan 07 12:55:58 PM PST 24
Finished Jan 07 12:57:39 PM PST 24
Peak memory 199104 kb
Host smart-bf73ef09-71aa-492e-858c-1fa6759d717e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661253561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.2661253561
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.3745702040
Short name T75
Test name
Test status
Simulation time 493208801 ps
CPU time 1.75 seconds
Started Jan 07 12:34:59 PM PST 24
Finished Jan 07 12:36:28 PM PST 24
Peak memory 199356 kb
Host smart-06a0b4c1-5ee9-49ee-a731-6698b046f879
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745702040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.3745702040
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/20.rstmgr_reset.77876381
Short name T250
Test name
Test status
Simulation time 777959055 ps
CPU time 3.66 seconds
Started Jan 07 12:56:48 PM PST 24
Finished Jan 07 12:58:09 PM PST 24
Peak memory 199356 kb
Host smart-b89cfcf9-31f4-4163-88ca-6a73abddbf88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77876381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.77876381
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.52138509
Short name T63
Test name
Test status
Simulation time 2349723147 ps
CPU time 9.41 seconds
Started Jan 07 12:57:47 PM PST 24
Finished Jan 07 12:59:30 PM PST 24
Peak memory 216584 kb
Host smart-73d3406f-6b16-43aa-b2e4-278938aa4380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52138509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.52138509
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.764509146
Short name T113
Test name
Test status
Simulation time 59944710 ps
CPU time 0.76 seconds
Started Jan 07 12:34:03 PM PST 24
Finished Jan 07 12:35:13 PM PST 24
Peak memory 199372 kb
Host smart-9f8f4182-e00a-447b-8341-fdf1a74f79b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764509146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.764509146
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.1338810547
Short name T189
Test name
Test status
Simulation time 420209602 ps
CPU time 2.82 seconds
Started Jan 07 12:29:54 PM PST 24
Finished Jan 07 12:31:40 PM PST 24
Peak memory 214996 kb
Host smart-336ed543-7393-4462-8bf2-35985ee280d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338810547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.1338810547
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.4123188774
Short name T76
Test name
Test status
Simulation time 879287182 ps
CPU time 2.86 seconds
Started Jan 07 12:26:04 PM PST 24
Finished Jan 07 12:27:04 PM PST 24
Peak memory 198792 kb
Host smart-4866ef6a-b069-439a-bb99-611bf9da82f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123188774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.4123188774
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.1189135528
Short name T93
Test name
Test status
Simulation time 120913525 ps
CPU time 1.42 seconds
Started Jan 07 12:56:09 PM PST 24
Finished Jan 07 12:57:38 PM PST 24
Peak memory 199316 kb
Host smart-7eba991a-b410-4de4-8ccc-4511b6413202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189135528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.1189135528
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2256792443
Short name T155
Test name
Test status
Simulation time 110994993 ps
CPU time 1.42 seconds
Started Jan 07 12:26:24 PM PST 24
Finished Jan 07 12:27:30 PM PST 24
Peak memory 199532 kb
Host smart-5f3bf6d7-948a-42f5-90bc-3586919744c8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256792443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.2
256792443
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2977215155
Short name T162
Test name
Test status
Simulation time 94038472 ps
CPU time 0.87 seconds
Started Jan 07 12:29:47 PM PST 24
Finished Jan 07 12:31:28 PM PST 24
Peak memory 199216 kb
Host smart-86905336-5de5-4494-816a-3275c4254708
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977215155 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.2977215155
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.91019937
Short name T156
Test name
Test status
Simulation time 243200936 ps
CPU time 1.65 seconds
Started Jan 07 12:34:58 PM PST 24
Finished Jan 07 12:36:25 PM PST 24
Peak memory 199004 kb
Host smart-4cf72951-8aec-446d-a3f8-cdad11a259b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91019937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.91019937
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1069724681
Short name T158
Test name
Test status
Simulation time 2290956868 ps
CPU time 9.19 seconds
Started Jan 07 12:25:30 PM PST 24
Finished Jan 07 12:26:41 PM PST 24
Peak memory 197480 kb
Host smart-b98c2746-4f5a-441c-b16a-81165b0d688b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069724681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.1
069724681
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.196780601
Short name T185
Test name
Test status
Simulation time 94776823 ps
CPU time 0.76 seconds
Started Jan 07 12:25:45 PM PST 24
Finished Jan 07 12:26:44 PM PST 24
Peak memory 199116 kb
Host smart-0712a1f9-5007-4266-8e85-9398f721cbea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196780601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.196780601
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.26580308
Short name T167
Test name
Test status
Simulation time 58697005 ps
CPU time 0.92 seconds
Started Jan 07 12:26:25 PM PST 24
Finished Jan 07 12:27:36 PM PST 24
Peak memory 198320 kb
Host smart-53ce7e45-08a6-4450-9b0c-32928a8165d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26580308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.26580308
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2225163437
Short name T154
Test name
Test status
Simulation time 128369300 ps
CPU time 0.98 seconds
Started Jan 07 12:25:45 PM PST 24
Finished Jan 07 12:26:44 PM PST 24
Peak memory 199184 kb
Host smart-41ed543b-a98e-435c-98e9-70fe36cb6873
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225163437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.2225163437
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1890960018
Short name T173
Test name
Test status
Simulation time 174080376 ps
CPU time 2.4 seconds
Started Jan 07 12:26:06 PM PST 24
Finished Jan 07 12:27:09 PM PST 24
Peak memory 199688 kb
Host smart-493a8094-a3fb-47b3-810b-f901c9b71301
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890960018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.1890960018
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.121235
Short name T121
Test name
Test status
Simulation time 795113389 ps
CPU time 2.84 seconds
Started Jan 07 12:35:36 PM PST 24
Finished Jan 07 12:36:54 PM PST 24
Peak memory 199368 kb
Host smart-b2c3daac-b307-4752-94e1-94ac98d8603e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err.121235
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.2819093265
Short name T78
Test name
Test status
Simulation time 114363113 ps
CPU time 1.05 seconds
Started Jan 07 12:29:06 PM PST 24
Finished Jan 07 12:30:20 PM PST 24
Peak memory 198976 kb
Host smart-2f3ad8f8-6b12-406e-97a3-28e942306d3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819093265 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.2819093265
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.3599666632
Short name T176
Test name
Test status
Simulation time 86944967 ps
CPU time 0.78 seconds
Started Jan 07 12:26:26 PM PST 24
Finished Jan 07 12:27:34 PM PST 24
Peak memory 199208 kb
Host smart-e55afac9-03a4-44de-90eb-3216fbd651d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599666632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.3599666632
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2233750158
Short name T198
Test name
Test status
Simulation time 362577954 ps
CPU time 2.65 seconds
Started Jan 07 12:26:38 PM PST 24
Finished Jan 07 12:27:54 PM PST 24
Peak memory 199296 kb
Host smart-a1a0b9a8-afce-4a82-b1c6-261dec4201a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233750158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.2233750158
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.2730796684
Short name T166
Test name
Test status
Simulation time 85499259 ps
CPU time 0.8 seconds
Started Jan 07 12:31:35 PM PST 24
Finished Jan 07 12:33:09 PM PST 24
Peak memory 199140 kb
Host smart-c42cae6d-036b-4dba-91ad-1f5b2125fdb1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730796684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.2730796684
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.2501448328
Short name T168
Test name
Test status
Simulation time 270782903 ps
CPU time 1.94 seconds
Started Jan 07 12:31:58 PM PST 24
Finished Jan 07 12:33:47 PM PST 24
Peak memory 215152 kb
Host smart-289e1c3b-7397-4369-a794-7c28aa74322e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501448328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.2501448328
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.3655698597
Short name T119
Test name
Test status
Simulation time 428161717 ps
CPU time 1.72 seconds
Started Jan 07 12:28:04 PM PST 24
Finished Jan 07 12:29:07 PM PST 24
Peak memory 198632 kb
Host smart-b8ff039d-8e4e-4709-9e28-43dba0c10944
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655698597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.3655698597
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.135605467
Short name T183
Test name
Test status
Simulation time 155607889 ps
CPU time 1.05 seconds
Started Jan 07 12:26:43 PM PST 24
Finished Jan 07 12:27:59 PM PST 24
Peak memory 199220 kb
Host smart-76550190-a04b-47d2-90e8-2cf03070d4e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135605467 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.135605467
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1828243601
Short name T184
Test name
Test status
Simulation time 126028284 ps
CPU time 1.06 seconds
Started Jan 07 12:31:02 PM PST 24
Finished Jan 07 12:32:51 PM PST 24
Peak memory 198904 kb
Host smart-48e46b59-bee8-48c2-9547-6e9609a7fa84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828243601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.1828243601
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1027047345
Short name T195
Test name
Test status
Simulation time 472369733 ps
CPU time 1.99 seconds
Started Jan 07 12:24:29 PM PST 24
Finished Jan 07 12:25:10 PM PST 24
Peak memory 199548 kb
Host smart-0992b29c-2702-4b30-b878-1a52e8467ffd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027047345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.1027047345
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3390023382
Short name T125
Test name
Test status
Simulation time 154664200 ps
CPU time 1.04 seconds
Started Jan 07 12:29:49 PM PST 24
Finished Jan 07 12:31:13 PM PST 24
Peak memory 198900 kb
Host smart-6f52daaf-2712-46ae-892a-bfb17489d6e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390023382 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.3390023382
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3778082664
Short name T104
Test name
Test status
Simulation time 64697916 ps
CPU time 0.78 seconds
Started Jan 07 12:24:34 PM PST 24
Finished Jan 07 12:25:27 PM PST 24
Peak memory 199512 kb
Host smart-bc6eeb0b-f9ce-4d99-8268-b444325428d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778082664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.3778082664
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.462127591
Short name T148
Test name
Test status
Simulation time 105865998 ps
CPU time 1.19 seconds
Started Jan 07 12:28:30 PM PST 24
Finished Jan 07 12:30:01 PM PST 24
Peak memory 199300 kb
Host smart-6063c8fb-8a0d-4741-ae97-de599456d638
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462127591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_sa
me_csr_outstanding.462127591
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.2039699819
Short name T105
Test name
Test status
Simulation time 481240141 ps
CPU time 1.9 seconds
Started Jan 07 12:29:11 PM PST 24
Finished Jan 07 12:31:05 PM PST 24
Peak memory 198956 kb
Host smart-3d4ff0b2-84c8-42c1-ad7e-923d1202afb3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039699819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.2039699819
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3868473228
Short name T147
Test name
Test status
Simulation time 159692891 ps
CPU time 1.02 seconds
Started Jan 07 12:31:58 PM PST 24
Finished Jan 07 12:33:43 PM PST 24
Peak memory 199276 kb
Host smart-285b4b38-04c7-42fb-8700-50d9df49a89f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868473228 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.3868473228
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.328101726
Short name T180
Test name
Test status
Simulation time 79369244 ps
CPU time 0.8 seconds
Started Jan 07 12:33:26 PM PST 24
Finished Jan 07 12:34:51 PM PST 24
Peak memory 199148 kb
Host smart-1d2cabb3-a5d9-4a53-bd06-c2a73030352f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328101726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.328101726
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.2574847790
Short name T152
Test name
Test status
Simulation time 198191182 ps
CPU time 2.52 seconds
Started Jan 07 12:28:58 PM PST 24
Finished Jan 07 12:30:17 PM PST 24
Peak memory 199300 kb
Host smart-f107866a-f377-4649-9792-4885ee0f0c71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574847790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.2574847790
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2410542755
Short name T182
Test name
Test status
Simulation time 167873476 ps
CPU time 1.48 seconds
Started Jan 07 12:30:07 PM PST 24
Finished Jan 07 12:31:48 PM PST 24
Peak memory 207636 kb
Host smart-c06d9a93-31c5-4a5d-a77d-0df00b33a547
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410542755 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.2410542755
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3561789096
Short name T115
Test name
Test status
Simulation time 71946755 ps
CPU time 0.75 seconds
Started Jan 07 12:25:58 PM PST 24
Finished Jan 07 12:26:59 PM PST 24
Peak memory 198776 kb
Host smart-ffa410c2-07de-4834-818c-94b3c86f24d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561789096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.3561789096
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2486616975
Short name T116
Test name
Test status
Simulation time 72740446 ps
CPU time 0.83 seconds
Started Jan 07 12:31:58 PM PST 24
Finished Jan 07 12:33:46 PM PST 24
Peak memory 199192 kb
Host smart-09f49e56-9c12-4f57-8f5b-3e6207864493
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486616975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.2486616975
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.2263064819
Short name T124
Test name
Test status
Simulation time 174947066 ps
CPU time 2.19 seconds
Started Jan 07 12:31:26 PM PST 24
Finished Jan 07 12:33:31 PM PST 24
Peak memory 199300 kb
Host smart-fda127d3-7480-43e0-8979-849b2a3430fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263064819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.2263064819
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3220775429
Short name T98
Test name
Test status
Simulation time 918122897 ps
CPU time 2.96 seconds
Started Jan 07 12:25:50 PM PST 24
Finished Jan 07 12:26:52 PM PST 24
Peak memory 198756 kb
Host smart-c1fb0c98-1e2d-4ca8-9e3b-9fc5d6aeb205
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220775429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.3220775429
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.4171943054
Short name T161
Test name
Test status
Simulation time 109399899 ps
CPU time 0.87 seconds
Started Jan 07 12:32:06 PM PST 24
Finished Jan 07 12:33:48 PM PST 24
Peak memory 199568 kb
Host smart-14f8dc11-e568-4631-a75e-d5c06bf48413
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171943054 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.4171943054
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2665737346
Short name T181
Test name
Test status
Simulation time 77149593 ps
CPU time 0.81 seconds
Started Jan 07 12:32:46 PM PST 24
Finished Jan 07 12:34:14 PM PST 24
Peak memory 199108 kb
Host smart-b35c75b2-f28d-4ef8-9b38-89b29c4444bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665737346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.2665737346
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3360991802
Short name T188
Test name
Test status
Simulation time 118776976 ps
CPU time 1.01 seconds
Started Jan 07 12:26:13 PM PST 24
Finished Jan 07 12:27:15 PM PST 24
Peak memory 199424 kb
Host smart-c2d2fc2e-bd9f-4fa6-8ae2-c207e64e4ac6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360991802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.3360991802
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.313551
Short name T120
Test name
Test status
Simulation time 450692909 ps
CPU time 1.67 seconds
Started Jan 07 12:26:05 PM PST 24
Finished Jan 07 12:27:04 PM PST 24
Peak memory 199340 kb
Host smart-6745a4af-46d5-441c-a937-15926b69a5c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_err.313551
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2921559916
Short name T172
Test name
Test status
Simulation time 132984360 ps
CPU time 0.98 seconds
Started Jan 07 12:36:58 PM PST 24
Finished Jan 07 12:38:16 PM PST 24
Peak memory 199312 kb
Host smart-b8b32a91-80b4-4c6e-91b6-499686121663
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921559916 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.2921559916
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.698346144
Short name T165
Test name
Test status
Simulation time 68487012 ps
CPU time 0.78 seconds
Started Jan 07 12:29:23 PM PST 24
Finished Jan 07 12:31:01 PM PST 24
Peak memory 199240 kb
Host smart-7d82c6bf-f769-4372-ac20-ba4ec3442541
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698346144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.698346144
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.4271470708
Short name T174
Test name
Test status
Simulation time 238535930 ps
CPU time 1.47 seconds
Started Jan 07 12:25:58 PM PST 24
Finished Jan 07 12:26:59 PM PST 24
Peak memory 198560 kb
Host smart-f7aaa3d3-2602-45cc-bab3-5c99c0b60482
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271470708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.4271470708
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.3011119612
Short name T170
Test name
Test status
Simulation time 513418505 ps
CPU time 3.22 seconds
Started Jan 07 12:34:07 PM PST 24
Finished Jan 07 12:35:44 PM PST 24
Peak memory 199304 kb
Host smart-055b14ac-12a8-40c7-84cc-5208af613b9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011119612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.3011119612
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2872349466
Short name T123
Test name
Test status
Simulation time 833668788 ps
CPU time 2.83 seconds
Started Jan 07 12:30:24 PM PST 24
Finished Jan 07 12:32:17 PM PST 24
Peak memory 199724 kb
Host smart-bd719cbd-9372-43e1-8a32-6bd8bf63b035
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872349466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.2872349466
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2392004602
Short name T145
Test name
Test status
Simulation time 181031977 ps
CPU time 1.39 seconds
Started Jan 07 12:24:09 PM PST 24
Finished Jan 07 12:24:28 PM PST 24
Peak memory 199500 kb
Host smart-8024bead-d11a-4369-a0c6-bb3e3d633c05
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392004602 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.2392004602
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.2804750513
Short name T163
Test name
Test status
Simulation time 69451002 ps
CPU time 0.74 seconds
Started Jan 07 12:26:22 PM PST 24
Finished Jan 07 12:27:26 PM PST 24
Peak memory 199172 kb
Host smart-58fa3669-565a-46a8-8e8a-031c166c32a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804750513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.2804750513
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.3787546750
Short name T106
Test name
Test status
Simulation time 80325172 ps
CPU time 0.92 seconds
Started Jan 07 12:26:23 PM PST 24
Finished Jan 07 12:27:29 PM PST 24
Peak memory 199188 kb
Host smart-7c84cc19-dbf8-41ff-a694-9960e908c96c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787546750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.3787546750
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.3344649708
Short name T100
Test name
Test status
Simulation time 513537936 ps
CPU time 3.44 seconds
Started Jan 07 12:27:09 PM PST 24
Finished Jan 07 12:28:22 PM PST 24
Peak memory 214992 kb
Host smart-283d7d79-db40-4c1a-9a4a-7dc66091c810
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344649708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.3344649708
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1539060569
Short name T196
Test name
Test status
Simulation time 409750189 ps
CPU time 1.61 seconds
Started Jan 07 12:36:42 PM PST 24
Finished Jan 07 12:38:12 PM PST 24
Peak memory 198988 kb
Host smart-583d8a05-81bf-431c-96a6-c2b234171035
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539060569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.1539060569
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.3865294548
Short name T151
Test name
Test status
Simulation time 84497827 ps
CPU time 0.83 seconds
Started Jan 07 12:29:43 PM PST 24
Finished Jan 07 12:31:11 PM PST 24
Peak memory 199088 kb
Host smart-9efb4a21-d51a-47f8-8d79-ce73fdc3008e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865294548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.3865294548
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.284678481
Short name T149
Test name
Test status
Simulation time 194192258 ps
CPU time 1.34 seconds
Started Jan 07 12:26:24 PM PST 24
Finished Jan 07 12:27:32 PM PST 24
Peak memory 199296 kb
Host smart-56986847-9e96-4db7-9349-59006615fe42
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284678481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_sa
me_csr_outstanding.284678481
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.540236718
Short name T193
Test name
Test status
Simulation time 136404398 ps
CPU time 1.8 seconds
Started Jan 07 12:27:49 PM PST 24
Finished Jan 07 12:28:55 PM PST 24
Peak memory 199576 kb
Host smart-978c1535-9fd9-4285-89ca-831d36ea1b21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540236718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.540236718
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.88603021
Short name T109
Test name
Test status
Simulation time 2313850432 ps
CPU time 9.12 seconds
Started Jan 07 12:32:46 PM PST 24
Finished Jan 07 12:34:12 PM PST 24
Peak memory 199324 kb
Host smart-6ec22f63-b390-4c7d-9f8b-cf7e7400cffd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88603021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.88603021
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1501290339
Short name T179
Test name
Test status
Simulation time 119666592 ps
CPU time 0.86 seconds
Started Jan 07 12:28:36 PM PST 24
Finished Jan 07 12:30:05 PM PST 24
Peak memory 199164 kb
Host smart-1fe3ff8e-d485-4d07-8d32-c2383066f62b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501290339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.1
501290339
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.139819062
Short name T144
Test name
Test status
Simulation time 106162800 ps
CPU time 0.99 seconds
Started Jan 07 12:25:30 PM PST 24
Finished Jan 07 12:26:33 PM PST 24
Peak memory 197388 kb
Host smart-f8a2523f-e42c-4013-834d-9b0baff83fc1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139819062 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.139819062
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.4033605040
Short name T71
Test name
Test status
Simulation time 70081120 ps
CPU time 0.78 seconds
Started Jan 07 12:33:35 PM PST 24
Finished Jan 07 12:35:01 PM PST 24
Peak memory 199400 kb
Host smart-b3ad4f70-8441-4878-8c45-2f7a4962acfe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033605040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.4033605040
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.3950726133
Short name T199
Test name
Test status
Simulation time 203028934 ps
CPU time 1.49 seconds
Started Jan 07 12:33:06 PM PST 24
Finished Jan 07 12:34:17 PM PST 24
Peak memory 199700 kb
Host smart-51fafe7f-4a01-4003-b378-e2c00b0f2356
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950726133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.3950726133
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.2554343509
Short name T190
Test name
Test status
Simulation time 103290552 ps
CPU time 1.32 seconds
Started Jan 07 12:25:31 PM PST 24
Finished Jan 07 12:26:36 PM PST 24
Peak memory 199176 kb
Host smart-c58613fa-16b2-4d39-bf53-e2326d3639d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554343509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.2554343509
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.973992904
Short name T143
Test name
Test status
Simulation time 350195982 ps
CPU time 2.3 seconds
Started Jan 07 12:26:13 PM PST 24
Finished Jan 07 12:27:17 PM PST 24
Peak memory 199228 kb
Host smart-4b2092f2-abba-4f8a-bc5a-8f1796f7f117
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973992904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.973992904
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.345123679
Short name T112
Test name
Test status
Simulation time 1180541390 ps
CPU time 5.56 seconds
Started Jan 07 12:24:59 PM PST 24
Finished Jan 07 12:26:16 PM PST 24
Peak memory 199528 kb
Host smart-add1d0a2-08d0-4775-b2c6-2dae1852b701
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345123679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.345123679
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.2728003330
Short name T110
Test name
Test status
Simulation time 100110201 ps
CPU time 0.83 seconds
Started Jan 07 12:25:57 PM PST 24
Finished Jan 07 12:26:58 PM PST 24
Peak memory 198596 kb
Host smart-c0e6679a-8e5f-4492-baa9-f01616a61eb2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728003330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.2
728003330
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3697482138
Short name T114
Test name
Test status
Simulation time 70827210 ps
CPU time 0.73 seconds
Started Jan 07 12:31:25 PM PST 24
Finished Jan 07 12:32:55 PM PST 24
Peak memory 199200 kb
Host smart-77d65ef8-8240-4d66-bdda-4c7cef4a4fd1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697482138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.3697482138
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1629451182
Short name T160
Test name
Test status
Simulation time 196705846 ps
CPU time 1.33 seconds
Started Jan 07 12:26:13 PM PST 24
Finished Jan 07 12:27:16 PM PST 24
Peak memory 199324 kb
Host smart-4ee0b8f3-8dca-4e7a-88fa-bb31707de243
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629451182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.1629451182
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3095272490
Short name T99
Test name
Test status
Simulation time 434862573 ps
CPU time 1.78 seconds
Started Jan 07 12:23:50 PM PST 24
Finished Jan 07 12:24:02 PM PST 24
Peak memory 199500 kb
Host smart-9eaef458-96ec-48e2-b1d8-62261c48ace0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095272490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.3095272490
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.397096348
Short name T178
Test name
Test status
Simulation time 114653602 ps
CPU time 1.27 seconds
Started Jan 07 12:29:27 PM PST 24
Finished Jan 07 12:31:09 PM PST 24
Peak memory 199212 kb
Host smart-e07bb59a-b1ca-4da1-b533-af7e0e963cb4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397096348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.397096348
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.4279180409
Short name T171
Test name
Test status
Simulation time 1560461807 ps
CPU time 7.98 seconds
Started Jan 07 12:37:02 PM PST 24
Finished Jan 07 12:38:35 PM PST 24
Peak memory 199304 kb
Host smart-29e48cfa-1ed5-40fe-a760-d489aad8fcf4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279180409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.4
279180409
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1286379033
Short name T72
Test name
Test status
Simulation time 154320939 ps
CPU time 0.93 seconds
Started Jan 07 12:24:42 PM PST 24
Finished Jan 07 12:25:45 PM PST 24
Peak memory 199372 kb
Host smart-0cc9cb50-7fd9-4687-a377-87e1b60ba2b5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286379033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.1
286379033
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2820276718
Short name T107
Test name
Test status
Simulation time 184315722 ps
CPU time 1.18 seconds
Started Jan 07 12:26:14 PM PST 24
Finished Jan 07 12:27:19 PM PST 24
Peak memory 199304 kb
Host smart-7277556a-0f59-42c6-9c8b-2edfafe6d788
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820276718 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.2820276718
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.2956307386
Short name T157
Test name
Test status
Simulation time 130951170 ps
CPU time 1.07 seconds
Started Jan 07 12:24:59 PM PST 24
Finished Jan 07 12:26:10 PM PST 24
Peak memory 199508 kb
Host smart-ccb5ccdb-ac5b-4973-bcaa-436c81365424
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956307386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.2956307386
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.280988346
Short name T169
Test name
Test status
Simulation time 421233459 ps
CPU time 1.85 seconds
Started Jan 07 12:25:24 PM PST 24
Finished Jan 07 12:26:28 PM PST 24
Peak memory 199604 kb
Host smart-549e4889-8729-483a-b3d7-09dc5090a043
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280988346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err.
280988346
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2653916622
Short name T146
Test name
Test status
Simulation time 142942876 ps
CPU time 0.97 seconds
Started Jan 07 12:26:12 PM PST 24
Finished Jan 07 12:27:16 PM PST 24
Peak memory 199264 kb
Host smart-139b9f48-957a-4542-9233-4cb77192e579
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653916622 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.2653916622
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.592408693
Short name T70
Test name
Test status
Simulation time 82739015 ps
CPU time 0.78 seconds
Started Jan 07 12:31:46 PM PST 24
Finished Jan 07 12:33:32 PM PST 24
Peak memory 199208 kb
Host smart-e21d5be4-c139-4bf7-b20b-412472be9817
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592408693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.592408693
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.1196902307
Short name T153
Test name
Test status
Simulation time 82200143 ps
CPU time 0.93 seconds
Started Jan 07 12:26:28 PM PST 24
Finished Jan 07 12:27:37 PM PST 24
Peak memory 198272 kb
Host smart-a7111d2f-65f1-4274-a155-a3e39b553226
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196902307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.1196902307
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.2721369745
Short name T186
Test name
Test status
Simulation time 207149827 ps
CPU time 2.9 seconds
Started Jan 07 12:26:52 PM PST 24
Finished Jan 07 12:28:11 PM PST 24
Peak memory 199272 kb
Host smart-382fcd7b-3486-4dde-b7df-0232eb139a46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721369745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.2721369745
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.902541351
Short name T150
Test name
Test status
Simulation time 125236987 ps
CPU time 1.03 seconds
Started Jan 07 12:26:28 PM PST 24
Finished Jan 07 12:27:37 PM PST 24
Peak memory 198220 kb
Host smart-7f66362f-0f88-4c44-a744-17c00aa7f955
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902541351 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.902541351
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.3855259373
Short name T159
Test name
Test status
Simulation time 66200669 ps
CPU time 0.75 seconds
Started Jan 07 12:30:56 PM PST 24
Finished Jan 07 12:32:37 PM PST 24
Peak memory 198604 kb
Host smart-041556e6-f9f0-4b3b-a690-87572814b2d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855259373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.3855259373
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.2360391928
Short name T197
Test name
Test status
Simulation time 210231440 ps
CPU time 1.48 seconds
Started Jan 07 12:42:10 PM PST 24
Finished Jan 07 12:43:37 PM PST 24
Peak memory 199780 kb
Host smart-5b25153e-7573-4cd9-8beb-d234250637c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360391928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.2360391928
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.508883560
Short name T102
Test name
Test status
Simulation time 206583065 ps
CPU time 2.6 seconds
Started Jan 07 12:26:20 PM PST 24
Finished Jan 07 12:27:26 PM PST 24
Peak memory 199308 kb
Host smart-efb745e2-697c-48dc-be80-71f712630d1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508883560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.508883560
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.341478789
Short name T200
Test name
Test status
Simulation time 522526629 ps
CPU time 1.82 seconds
Started Jan 07 12:31:22 PM PST 24
Finished Jan 07 12:32:45 PM PST 24
Peak memory 199356 kb
Host smart-979a954e-e190-4123-bcf0-b84dcee58311
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341478789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err.
341478789
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.666022155
Short name T101
Test name
Test status
Simulation time 180901825 ps
CPU time 1.79 seconds
Started Jan 07 12:29:39 PM PST 24
Finished Jan 07 12:31:44 PM PST 24
Peak memory 206892 kb
Host smart-6a04db54-a5db-4e3f-acf7-2a7b763d785d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666022155 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.666022155
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2178420640
Short name T177
Test name
Test status
Simulation time 58447761 ps
CPU time 0.68 seconds
Started Jan 07 12:26:13 PM PST 24
Finished Jan 07 12:27:15 PM PST 24
Peak memory 199128 kb
Host smart-36942f77-ee03-40a9-b132-85ee44f0e286
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178420640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.2178420640
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.2741797049
Short name T191
Test name
Test status
Simulation time 76985603 ps
CPU time 0.88 seconds
Started Jan 07 12:29:59 PM PST 24
Finished Jan 07 12:31:45 PM PST 24
Peak memory 199280 kb
Host smart-85ff08cb-1aab-4a5b-bd64-32fcef4dfaed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741797049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.2741797049
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.11191612
Short name T77
Test name
Test status
Simulation time 110206140 ps
CPU time 1.5 seconds
Started Jan 07 12:26:21 PM PST 24
Finished Jan 07 12:27:28 PM PST 24
Peak memory 199280 kb
Host smart-66984124-196d-44dd-8d38-4a559b725fe4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11191612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.11191612
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2179045319
Short name T164
Test name
Test status
Simulation time 186902645 ps
CPU time 1.47 seconds
Started Jan 07 12:23:53 PM PST 24
Finished Jan 07 12:24:08 PM PST 24
Peak memory 198264 kb
Host smart-3bc281fb-af67-4e3e-b8c3-046c9567e9ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179045319 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.2179045319
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.1513215279
Short name T111
Test name
Test status
Simulation time 61868498 ps
CPU time 0.79 seconds
Started Jan 07 12:26:13 PM PST 24
Finished Jan 07 12:27:16 PM PST 24
Peak memory 199172 kb
Host smart-5e04fe9e-31bf-405e-aa59-d4d3d9328cdc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513215279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.1513215279
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.1781410502
Short name T117
Test name
Test status
Simulation time 84618655 ps
CPU time 1 seconds
Started Jan 07 12:26:05 PM PST 24
Finished Jan 07 12:27:19 PM PST 24
Peak memory 198540 kb
Host smart-b34abc46-8866-4022-84cc-ddfedb25652f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781410502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.1781410502
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.2875599481
Short name T192
Test name
Test status
Simulation time 195703953 ps
CPU time 2.45 seconds
Started Jan 07 12:42:31 PM PST 24
Finished Jan 07 12:44:04 PM PST 24
Peak memory 207712 kb
Host smart-d2023e98-2e34-457d-ab3f-6bed1ab0bd48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875599481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.2875599481
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2962065009
Short name T103
Test name
Test status
Simulation time 110082957 ps
CPU time 1.23 seconds
Started Jan 07 12:29:17 PM PST 24
Finished Jan 07 12:31:02 PM PST 24
Peak memory 199308 kb
Host smart-976cfa23-57d7-4574-b5c1-498137778d63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962065009 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.2962065009
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.2092077091
Short name T175
Test name
Test status
Simulation time 59415983 ps
CPU time 0.68 seconds
Started Jan 07 12:26:24 PM PST 24
Finished Jan 07 12:27:29 PM PST 24
Peak memory 199140 kb
Host smart-27be918f-a903-45f3-ba2c-0e9a5f6f66e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092077091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.2092077091
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.120128651
Short name T187
Test name
Test status
Simulation time 99613523 ps
CPU time 1.2 seconds
Started Jan 07 12:24:37 PM PST 24
Finished Jan 07 12:25:36 PM PST 24
Peak memory 199560 kb
Host smart-33341945-9321-4423-92ea-7ae9efd96849
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120128651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sam
e_csr_outstanding.120128651
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.337452295
Short name T194
Test name
Test status
Simulation time 240248886 ps
CPU time 1.69 seconds
Started Jan 07 12:24:05 PM PST 24
Finished Jan 07 12:24:24 PM PST 24
Peak memory 207788 kb
Host smart-97bc104b-09c0-4d3b-b4ee-3dd1aa30a22c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337452295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.337452295
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.3562778221
Short name T122
Test name
Test status
Simulation time 425084601 ps
CPU time 1.81 seconds
Started Jan 07 12:23:50 PM PST 24
Finished Jan 07 12:24:03 PM PST 24
Peak memory 199532 kb
Host smart-0ea403a0-180f-497a-aea5-b8d9fa125388
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562778221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.3562778221
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.2401435634
Short name T475
Test name
Test status
Simulation time 90535237 ps
CPU time 0.8 seconds
Started Jan 07 12:55:56 PM PST 24
Finished Jan 07 12:57:25 PM PST 24
Peak memory 199136 kb
Host smart-eebe9a1c-d7f0-4313-b159-ff4ab7bd1fed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401435634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.2401435634
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.1580244645
Short name T541
Test name
Test status
Simulation time 1893130791 ps
CPU time 7.85 seconds
Started Jan 07 12:55:51 PM PST 24
Finished Jan 07 12:57:54 PM PST 24
Peak memory 217272 kb
Host smart-cc8ef934-1d87-4213-becd-4bce632d21c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580244645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.1580244645
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.2664227920
Short name T509
Test name
Test status
Simulation time 245830916 ps
CPU time 1.1 seconds
Started Jan 07 12:56:03 PM PST 24
Finished Jan 07 12:58:07 PM PST 24
Peak memory 216480 kb
Host smart-df848da6-522d-42fc-8ad2-336c6204b7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664227920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.2664227920
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.1344670934
Short name T24
Test name
Test status
Simulation time 175856796 ps
CPU time 0.83 seconds
Started Jan 07 12:56:16 PM PST 24
Finished Jan 07 12:58:18 PM PST 24
Peak memory 199136 kb
Host smart-59a630bc-e8bc-45fb-a136-d32a1dd71749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344670934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.1344670934
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.2573527198
Short name T87
Test name
Test status
Simulation time 1716718717 ps
CPU time 6.3 seconds
Started Jan 07 12:56:26 PM PST 24
Finished Jan 07 12:58:24 PM PST 24
Peak memory 199540 kb
Host smart-07c12052-aee2-4fda-81bb-05e44bd86316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573527198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.2573527198
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.2322093534
Short name T375
Test name
Test status
Simulation time 254238176 ps
CPU time 1.39 seconds
Started Jan 07 12:55:55 PM PST 24
Finished Jan 07 12:57:19 PM PST 24
Peak memory 199480 kb
Host smart-aea5e918-2152-45b6-8a84-9e21c4ec8493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322093534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.2322093534
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.2539706984
Short name T278
Test name
Test status
Simulation time 3593776053 ps
CPU time 15.22 seconds
Started Jan 07 12:55:58 PM PST 24
Finished Jan 07 12:57:54 PM PST 24
Peak memory 199508 kb
Host smart-f3c7c76a-7f63-4918-970a-3b022530401d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539706984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.2539706984
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.1405586778
Short name T360
Test name
Test status
Simulation time 65535229 ps
CPU time 0.72 seconds
Started Jan 07 12:55:57 PM PST 24
Finished Jan 07 12:57:24 PM PST 24
Peak memory 199172 kb
Host smart-7c3ff7cb-a1d3-454b-ad0e-a2ce05e0e91d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405586778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.1405586778
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.2116075954
Short name T52
Test name
Test status
Simulation time 2353306856 ps
CPU time 9.09 seconds
Started Jan 07 12:55:54 PM PST 24
Finished Jan 07 12:57:57 PM PST 24
Peak memory 220460 kb
Host smart-cde5df87-baed-46fd-91b0-ca3ad7f52de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116075954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.2116075954
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.3307800669
Short name T248
Test name
Test status
Simulation time 243815364 ps
CPU time 1.09 seconds
Started Jan 07 12:55:52 PM PST 24
Finished Jan 07 12:57:33 PM PST 24
Peak memory 216536 kb
Host smart-15a58ecb-d61c-4b2c-bff1-bf9df1aad0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307800669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.3307800669
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.1344113603
Short name T277
Test name
Test status
Simulation time 177454773 ps
CPU time 0.87 seconds
Started Jan 07 12:56:26 PM PST 24
Finished Jan 07 12:58:17 PM PST 24
Peak memory 199092 kb
Host smart-28f38989-c41d-46a0-a2db-e755e8810739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344113603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.1344113603
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.4139016944
Short name T249
Test name
Test status
Simulation time 889573530 ps
CPU time 4.55 seconds
Started Jan 07 12:56:25 PM PST 24
Finished Jan 07 12:58:09 PM PST 24
Peak memory 199488 kb
Host smart-c11dbb3f-1aad-437b-b91b-b139b03b0769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139016944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.4139016944
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.325834410
Short name T499
Test name
Test status
Simulation time 176780108 ps
CPU time 1.14 seconds
Started Jan 07 12:55:53 PM PST 24
Finished Jan 07 12:57:25 PM PST 24
Peak memory 199320 kb
Host smart-ae9c6a06-b2fa-49bc-8585-a39e2f8366a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325834410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.325834410
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.145624988
Short name T232
Test name
Test status
Simulation time 109831258 ps
CPU time 1.09 seconds
Started Jan 07 12:55:58 PM PST 24
Finished Jan 07 12:57:40 PM PST 24
Peak memory 199432 kb
Host smart-aab31873-c94c-4c27-8a9f-0f63e4c083ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145624988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.145624988
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.416619179
Short name T502
Test name
Test status
Simulation time 6240210528 ps
CPU time 21.62 seconds
Started Jan 07 12:56:26 PM PST 24
Finished Jan 07 12:58:14 PM PST 24
Peak memory 199544 kb
Host smart-86891f17-3545-4714-bfdc-9c134fb48215
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416619179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.416619179
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.252795199
Short name T353
Test name
Test status
Simulation time 436959406 ps
CPU time 2.31 seconds
Started Jan 07 12:55:52 PM PST 24
Finished Jan 07 12:57:34 PM PST 24
Peak memory 199344 kb
Host smart-fca52e4e-552c-4bb1-8d00-1339c3faa7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252795199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.252795199
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.1562017854
Short name T141
Test name
Test status
Simulation time 74951013 ps
CPU time 0.76 seconds
Started Jan 07 12:56:38 PM PST 24
Finished Jan 07 12:58:45 PM PST 24
Peak memory 199256 kb
Host smart-21e17b47-bb48-4b2d-8533-76616ee03d92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562017854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.1562017854
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.3866960812
Short name T40
Test name
Test status
Simulation time 1226415922 ps
CPU time 5.67 seconds
Started Jan 07 12:56:14 PM PST 24
Finished Jan 07 12:57:56 PM PST 24
Peak memory 217132 kb
Host smart-249568fa-5e10-4f55-bf34-7e407839bfa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866960812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.3866960812
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.2977886113
Short name T201
Test name
Test status
Simulation time 245082813 ps
CPU time 1.02 seconds
Started Jan 07 12:56:11 PM PST 24
Finished Jan 07 12:57:55 PM PST 24
Peak memory 216520 kb
Host smart-6c8a16cf-d02c-4c3b-bcc9-9363f33fa953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977886113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.2977886113
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.2160971577
Short name T401
Test name
Test status
Simulation time 143037018 ps
CPU time 0.79 seconds
Started Jan 07 12:56:55 PM PST 24
Finished Jan 07 12:58:54 PM PST 24
Peak memory 199168 kb
Host smart-2b89a2dc-8a3f-442c-9fa6-a495638f3228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160971577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.2160971577
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.3037296879
Short name T411
Test name
Test status
Simulation time 1011952314 ps
CPU time 4.82 seconds
Started Jan 07 12:56:36 PM PST 24
Finished Jan 07 12:58:34 PM PST 24
Peak memory 199560 kb
Host smart-f3dae54f-cd7f-4276-9739-6a147404d13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037296879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.3037296879
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.892691136
Short name T397
Test name
Test status
Simulation time 109318213 ps
CPU time 0.95 seconds
Started Jan 07 12:56:10 PM PST 24
Finished Jan 07 12:58:05 PM PST 24
Peak memory 199380 kb
Host smart-249b92b5-6228-4e41-a9ff-cb717cc068f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892691136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.892691136
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.2379403768
Short name T6
Test name
Test status
Simulation time 114481127 ps
CPU time 1.13 seconds
Started Jan 07 12:56:16 PM PST 24
Finished Jan 07 12:57:57 PM PST 24
Peak memory 199508 kb
Host smart-2c49274a-9340-4903-bb60-eafc48b830bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379403768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.2379403768
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.2931877798
Short name T543
Test name
Test status
Simulation time 1002294478 ps
CPU time 4.64 seconds
Started Jan 07 12:56:11 PM PST 24
Finished Jan 07 12:58:02 PM PST 24
Peak memory 199476 kb
Host smart-538a63dd-e127-40c7-9ed8-541fb9f21aad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931877798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.2931877798
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.4101020073
Short name T273
Test name
Test status
Simulation time 124913811 ps
CPU time 1.33 seconds
Started Jan 07 12:56:15 PM PST 24
Finished Jan 07 12:57:51 PM PST 24
Peak memory 199172 kb
Host smart-49f7df1e-7c17-40fd-9db2-1d3f0a7c0c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101020073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.4101020073
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.3340870022
Short name T535
Test name
Test status
Simulation time 179691388 ps
CPU time 1.08 seconds
Started Jan 07 12:56:08 PM PST 24
Finished Jan 07 12:57:33 PM PST 24
Peak memory 199336 kb
Host smart-c11b9031-7879-4bb2-b894-4edd0bd48eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340870022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.3340870022
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.868205785
Short name T339
Test name
Test status
Simulation time 67618778 ps
CPU time 0.68 seconds
Started Jan 07 12:56:42 PM PST 24
Finished Jan 07 12:58:23 PM PST 24
Peak memory 199176 kb
Host smart-e1addeee-8cac-4466-801b-2b3f55edc9da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868205785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.868205785
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.2509326228
Short name T293
Test name
Test status
Simulation time 2173582623 ps
CPU time 7.21 seconds
Started Jan 07 12:56:40 PM PST 24
Finished Jan 07 12:58:07 PM PST 24
Peak memory 216696 kb
Host smart-dbc90dd0-8bfc-460d-a7c4-29e0b14f7664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509326228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.2509326228
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.3799544988
Short name T549
Test name
Test status
Simulation time 244281840 ps
CPU time 1.06 seconds
Started Jan 07 12:56:41 PM PST 24
Finished Jan 07 12:58:08 PM PST 24
Peak memory 216452 kb
Host smart-e7ffe154-0db5-45b5-84af-7633202fea30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799544988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.3799544988
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.3857070965
Short name T532
Test name
Test status
Simulation time 114912586 ps
CPU time 0.74 seconds
Started Jan 07 12:56:08 PM PST 24
Finished Jan 07 12:57:56 PM PST 24
Peak memory 199140 kb
Host smart-7862726b-015d-4f96-a323-d73869e1fec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857070965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.3857070965
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.594239628
Short name T442
Test name
Test status
Simulation time 720912575 ps
CPU time 3.76 seconds
Started Jan 07 12:56:22 PM PST 24
Finished Jan 07 12:58:03 PM PST 24
Peak memory 199504 kb
Host smart-f10e27de-8c71-439e-8f3b-44a495045adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594239628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.594239628
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.1837151100
Short name T338
Test name
Test status
Simulation time 169861405 ps
CPU time 1.11 seconds
Started Jan 07 12:56:43 PM PST 24
Finished Jan 07 12:58:20 PM PST 24
Peak memory 199332 kb
Host smart-96f981f1-cbad-4724-8a42-d692924b01cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837151100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.1837151100
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.3678128087
Short name T379
Test name
Test status
Simulation time 117034596 ps
CPU time 1.16 seconds
Started Jan 07 12:56:11 PM PST 24
Finished Jan 07 12:57:59 PM PST 24
Peak memory 199428 kb
Host smart-13b4a376-717a-40f3-b6a9-a4768b3bb250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678128087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.3678128087
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.2809412888
Short name T303
Test name
Test status
Simulation time 6516134080 ps
CPU time 22.72 seconds
Started Jan 07 12:56:42 PM PST 24
Finished Jan 07 12:58:33 PM PST 24
Peak memory 199548 kb
Host smart-2958d761-57e8-4670-bccd-6d885b1a69bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809412888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.2809412888
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.49989910
Short name T4
Test name
Test status
Simulation time 454651030 ps
CPU time 2.2 seconds
Started Jan 07 12:56:35 PM PST 24
Finished Jan 07 12:58:17 PM PST 24
Peak memory 199412 kb
Host smart-b39e6939-82aa-42bd-9553-738419864118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49989910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.49989910
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.336196828
Short name T381
Test name
Test status
Simulation time 74364335 ps
CPU time 0.76 seconds
Started Jan 07 12:56:43 PM PST 24
Finished Jan 07 12:58:20 PM PST 24
Peak memory 199336 kb
Host smart-5f372cf8-8307-4d1e-b5a1-03ff13f2ed72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336196828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.336196828
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.2223154963
Short name T256
Test name
Test status
Simulation time 61040674 ps
CPU time 0.7 seconds
Started Jan 07 12:56:40 PM PST 24
Finished Jan 07 12:58:08 PM PST 24
Peak memory 199160 kb
Host smart-fd733293-4ff1-42b7-ac4c-6dc0d9badafa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223154963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.2223154963
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.108200782
Short name T69
Test name
Test status
Simulation time 1216127626 ps
CPU time 5.51 seconds
Started Jan 07 12:56:57 PM PST 24
Finished Jan 07 12:58:19 PM PST 24
Peak memory 216192 kb
Host smart-b7b3a3ce-5fc1-4da0-b15c-d8bcd9030544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108200782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.108200782
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.938511991
Short name T437
Test name
Test status
Simulation time 243910921 ps
CPU time 1.08 seconds
Started Jan 07 12:56:25 PM PST 24
Finished Jan 07 12:57:53 PM PST 24
Peak memory 216496 kb
Host smart-362b76e2-d7c5-4b62-b877-1d7f869e2196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938511991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.938511991
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.401664280
Short name T18
Test name
Test status
Simulation time 215119573 ps
CPU time 0.9 seconds
Started Jan 07 12:56:39 PM PST 24
Finished Jan 07 12:58:01 PM PST 24
Peak memory 199144 kb
Host smart-9594e76a-3cb0-43ef-9d08-58b4481f9370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401664280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.401664280
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.3824048522
Short name T432
Test name
Test status
Simulation time 1123466425 ps
CPU time 5.22 seconds
Started Jan 07 12:56:55 PM PST 24
Finished Jan 07 12:58:59 PM PST 24
Peak memory 199448 kb
Host smart-68b1fbbd-30ff-4f9b-a0ab-e39bae62bfa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824048522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.3824048522
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.1606644674
Short name T489
Test name
Test status
Simulation time 181025537 ps
CPU time 1.2 seconds
Started Jan 07 12:56:57 PM PST 24
Finished Jan 07 12:58:35 PM PST 24
Peak memory 199328 kb
Host smart-a7761812-b4f8-437a-8e0e-fc963ace46e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606644674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.1606644674
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.4007069492
Short name T529
Test name
Test status
Simulation time 203705346 ps
CPU time 1.41 seconds
Started Jan 07 12:56:43 PM PST 24
Finished Jan 07 12:58:16 PM PST 24
Peak memory 199484 kb
Host smart-15f2bee7-2b5c-4d1d-b4ef-d245e90f731d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007069492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.4007069492
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.203940110
Short name T291
Test name
Test status
Simulation time 6677537995 ps
CPU time 30.48 seconds
Started Jan 07 12:56:28 PM PST 24
Finished Jan 07 12:58:22 PM PST 24
Peak memory 199564 kb
Host smart-13a98967-6060-44f4-981f-9b2b337d9281
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203940110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.203940110
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.3416666808
Short name T295
Test name
Test status
Simulation time 121984686 ps
CPU time 1.53 seconds
Started Jan 07 12:56:39 PM PST 24
Finished Jan 07 12:58:10 PM PST 24
Peak memory 199332 kb
Host smart-bca6e463-6265-4408-b05d-ff70ba1ca995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416666808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.3416666808
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.3879297199
Short name T550
Test name
Test status
Simulation time 182780819 ps
CPU time 1.08 seconds
Started Jan 07 12:56:39 PM PST 24
Finished Jan 07 12:58:01 PM PST 24
Peak memory 199332 kb
Host smart-a5a2ea2d-128d-4a58-b03a-d82772c7c8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879297199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.3879297199
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.2687087930
Short name T54
Test name
Test status
Simulation time 61446967 ps
CPU time 0.73 seconds
Started Jan 07 12:56:34 PM PST 24
Finished Jan 07 12:58:00 PM PST 24
Peak memory 199200 kb
Host smart-f21e23bb-6124-49e5-97c3-6e4af4609909
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687087930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.2687087930
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.4003846804
Short name T388
Test name
Test status
Simulation time 1228164032 ps
CPU time 5.89 seconds
Started Jan 07 12:56:26 PM PST 24
Finished Jan 07 12:58:04 PM PST 24
Peak memory 220356 kb
Host smart-a20a435f-11d7-4966-8b73-8d165a14a9dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003846804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.4003846804
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.1550660665
Short name T219
Test name
Test status
Simulation time 244570258 ps
CPU time 1.13 seconds
Started Jan 07 12:56:40 PM PST 24
Finished Jan 07 12:58:09 PM PST 24
Peak memory 216368 kb
Host smart-e40414cd-fee1-4d8d-aa66-b649a33a11a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550660665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.1550660665
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.2786886979
Short name T506
Test name
Test status
Simulation time 204951646 ps
CPU time 0.84 seconds
Started Jan 07 12:56:55 PM PST 24
Finished Jan 07 12:58:14 PM PST 24
Peak memory 199128 kb
Host smart-c2f82f96-3d46-4d3f-894d-7b73d17539c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786886979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.2786886979
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.3794368445
Short name T496
Test name
Test status
Simulation time 878574170 ps
CPU time 4.15 seconds
Started Jan 07 12:56:55 PM PST 24
Finished Jan 07 12:58:58 PM PST 24
Peak memory 199476 kb
Host smart-66194756-6605-4578-a707-d6ce688c8a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794368445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.3794368445
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.1712736709
Short name T217
Test name
Test status
Simulation time 109369591 ps
CPU time 0.98 seconds
Started Jan 07 12:56:25 PM PST 24
Finished Jan 07 12:57:53 PM PST 24
Peak memory 199252 kb
Host smart-eeaed72c-9652-47a9-85f0-05e6b2ef7b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712736709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.1712736709
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.3217646991
Short name T342
Test name
Test status
Simulation time 227610473 ps
CPU time 1.36 seconds
Started Jan 07 12:56:34 PM PST 24
Finished Jan 07 12:57:59 PM PST 24
Peak memory 199464 kb
Host smart-3d741ed3-46d8-47a0-9b57-1bbf0494f9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217646991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.3217646991
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.1241707543
Short name T492
Test name
Test status
Simulation time 124204248 ps
CPU time 1.5 seconds
Started Jan 07 12:56:39 PM PST 24
Finished Jan 07 12:58:27 PM PST 24
Peak memory 199288 kb
Host smart-12deccf4-4073-4b57-b671-22fffdc2a813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241707543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.1241707543
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.224658713
Short name T409
Test name
Test status
Simulation time 163400660 ps
CPU time 1.24 seconds
Started Jan 07 12:56:59 PM PST 24
Finished Jan 07 12:58:27 PM PST 24
Peak memory 199492 kb
Host smart-928d6809-4362-4027-8df8-cfdffb260cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224658713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.224658713
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.2127905158
Short name T253
Test name
Test status
Simulation time 90285025 ps
CPU time 0.77 seconds
Started Jan 07 12:56:26 PM PST 24
Finished Jan 07 12:58:26 PM PST 24
Peak memory 199236 kb
Host smart-4f900f97-0e62-4aa3-aef5-f61f130ce3f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127905158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.2127905158
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.1057424190
Short name T41
Test name
Test status
Simulation time 1224203250 ps
CPU time 5.5 seconds
Started Jan 07 12:56:36 PM PST 24
Finished Jan 07 12:58:31 PM PST 24
Peak memory 216628 kb
Host smart-4e2c37f1-36f9-4e64-90fe-2c956496e8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057424190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.1057424190
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.899137447
Short name T369
Test name
Test status
Simulation time 227576998 ps
CPU time 0.87 seconds
Started Jan 07 12:56:33 PM PST 24
Finished Jan 07 12:57:56 PM PST 24
Peak memory 199108 kb
Host smart-b1895c0a-aaaa-4021-9b9d-36fc78a00b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899137447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.899137447
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.2081787497
Short name T392
Test name
Test status
Simulation time 1714334763 ps
CPU time 6.89 seconds
Started Jan 07 12:56:32 PM PST 24
Finished Jan 07 12:58:35 PM PST 24
Peak memory 199540 kb
Host smart-799f63af-a24a-41d3-9f00-db9e9d0d8b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081787497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.2081787497
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.3022575821
Short name T504
Test name
Test status
Simulation time 247750299 ps
CPU time 1.41 seconds
Started Jan 07 12:56:27 PM PST 24
Finished Jan 07 12:58:11 PM PST 24
Peak memory 199488 kb
Host smart-1bc3be6c-ff99-46a0-8ae1-2f6eeb009fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022575821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.3022575821
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.1329202390
Short name T423
Test name
Test status
Simulation time 117909276 ps
CPU time 1.34 seconds
Started Jan 07 12:56:59 PM PST 24
Finished Jan 07 12:58:20 PM PST 24
Peak memory 199364 kb
Host smart-53b77c4e-5104-4b02-adb8-524198b8e9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329202390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.1329202390
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.4106186076
Short name T467
Test name
Test status
Simulation time 136701977 ps
CPU time 1.09 seconds
Started Jan 07 12:56:26 PM PST 24
Finished Jan 07 12:58:02 PM PST 24
Peak memory 199344 kb
Host smart-6486f67f-4529-4954-af87-164fdebaff81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106186076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.4106186076
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.1941342456
Short name T513
Test name
Test status
Simulation time 1882873587 ps
CPU time 6.79 seconds
Started Jan 07 12:57:02 PM PST 24
Finished Jan 07 12:58:34 PM PST 24
Peak memory 216104 kb
Host smart-7d648073-bd4b-4cc8-bf67-62601ebd0947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941342456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.1941342456
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.650890751
Short name T537
Test name
Test status
Simulation time 243865794 ps
CPU time 1.11 seconds
Started Jan 07 12:56:40 PM PST 24
Finished Jan 07 12:58:22 PM PST 24
Peak memory 216520 kb
Host smart-508f125b-c7b2-4827-b4a7-2e11c5d58730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650890751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.650890751
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_reset.2123077880
Short name T374
Test name
Test status
Simulation time 993949373 ps
CPU time 4.33 seconds
Started Jan 07 12:56:27 PM PST 24
Finished Jan 07 12:58:00 PM PST 24
Peak memory 199472 kb
Host smart-5f126575-b5b4-4182-841c-aa3694cbbc23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123077880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.2123077880
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.1588716367
Short name T407
Test name
Test status
Simulation time 144999017 ps
CPU time 1.04 seconds
Started Jan 07 12:57:09 PM PST 24
Finished Jan 07 12:58:36 PM PST 24
Peak memory 199304 kb
Host smart-3bfa0b52-56c1-41ec-b78f-ef60a8680b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588716367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.1588716367
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.838876990
Short name T272
Test name
Test status
Simulation time 248697234 ps
CPU time 1.45 seconds
Started Jan 07 12:56:38 PM PST 24
Finished Jan 07 12:58:18 PM PST 24
Peak memory 199448 kb
Host smart-a2ea21f0-50f4-466f-a066-731c46733784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838876990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.838876990
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.1678362590
Short name T521
Test name
Test status
Simulation time 126788327 ps
CPU time 1.05 seconds
Started Jan 07 12:56:33 PM PST 24
Finished Jan 07 12:58:04 PM PST 24
Peak memory 199384 kb
Host smart-63cac01e-8b16-461e-8db1-08d5ad729d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678362590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.1678362590
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.4109882127
Short name T483
Test name
Test status
Simulation time 74077175 ps
CPU time 0.77 seconds
Started Jan 07 12:56:33 PM PST 24
Finished Jan 07 12:58:07 PM PST 24
Peak memory 199216 kb
Host smart-3e461c13-0890-4685-b54e-d9072e3f1e57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109882127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.4109882127
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.1195399108
Short name T68
Test name
Test status
Simulation time 1235300404 ps
CPU time 5.36 seconds
Started Jan 07 12:56:43 PM PST 24
Finished Jan 07 12:58:11 PM PST 24
Peak memory 216008 kb
Host smart-7239e40d-d375-43e3-af7e-7c4e36eb13b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195399108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.1195399108
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_reset.3198940434
Short name T90
Test name
Test status
Simulation time 728003982 ps
CPU time 3.89 seconds
Started Jan 07 12:57:01 PM PST 24
Finished Jan 07 12:58:38 PM PST 24
Peak memory 199492 kb
Host smart-1dd6b76b-71a0-4d3a-ab13-29b984c53d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198940434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.3198940434
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.501953553
Short name T3
Test name
Test status
Simulation time 173907675 ps
CPU time 1.19 seconds
Started Jan 07 12:56:39 PM PST 24
Finished Jan 07 12:58:01 PM PST 24
Peak memory 199324 kb
Host smart-a0a60cca-49df-4708-aa63-d976a703f912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501953553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.501953553
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.2668922499
Short name T320
Test name
Test status
Simulation time 232906738 ps
CPU time 1.36 seconds
Started Jan 07 12:56:32 PM PST 24
Finished Jan 07 12:58:11 PM PST 24
Peak memory 199536 kb
Host smart-353abc5d-2e8c-48df-a44e-777e95082b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668922499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.2668922499
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.4096241
Short name T510
Test name
Test status
Simulation time 367942527 ps
CPU time 2.14 seconds
Started Jan 07 12:56:42 PM PST 24
Finished Jan 07 12:58:12 PM PST 24
Peak memory 199352 kb
Host smart-78545bf2-dcd3-456c-9f27-e0080947074a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.4096241
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.1902102582
Short name T218
Test name
Test status
Simulation time 65201516 ps
CPU time 0.71 seconds
Started Jan 07 12:56:29 PM PST 24
Finished Jan 07 12:57:58 PM PST 24
Peak memory 199172 kb
Host smart-d18b408d-cd5f-4da0-9d3f-98b02e23d175
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902102582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.1902102582
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.2873616753
Short name T415
Test name
Test status
Simulation time 2368793090 ps
CPU time 7.71 seconds
Started Jan 07 12:56:39 PM PST 24
Finished Jan 07 12:58:15 PM PST 24
Peak memory 217092 kb
Host smart-f864c088-b1d3-4f5d-8f4d-631300105f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873616753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.2873616753
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.3656743310
Short name T88
Test name
Test status
Simulation time 243822746 ps
CPU time 1.06 seconds
Started Jan 07 12:56:29 PM PST 24
Finished Jan 07 12:57:57 PM PST 24
Peak memory 216568 kb
Host smart-5e24f321-e0c5-4692-bb10-bfc16737721b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656743310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.3656743310
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.4018235725
Short name T366
Test name
Test status
Simulation time 98741971 ps
CPU time 0.71 seconds
Started Jan 07 12:56:25 PM PST 24
Finished Jan 07 12:58:00 PM PST 24
Peak memory 199176 kb
Host smart-65ad0570-0bde-4d56-a04f-0e702595ac73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018235725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.4018235725
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.130368986
Short name T288
Test name
Test status
Simulation time 1269630033 ps
CPU time 4.6 seconds
Started Jan 07 12:56:55 PM PST 24
Finished Jan 07 12:58:55 PM PST 24
Peak memory 199488 kb
Host smart-9c71a43a-b077-4809-8cd0-ac4e3839dcaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130368986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.130368986
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.1997381777
Short name T434
Test name
Test status
Simulation time 106790034 ps
CPU time 0.95 seconds
Started Jan 07 12:56:26 PM PST 24
Finished Jan 07 12:58:32 PM PST 24
Peak memory 199440 kb
Host smart-3bb74d73-6ba8-40d8-ba93-7f38b3ebf1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997381777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.1997381777
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.3198402337
Short name T241
Test name
Test status
Simulation time 180995509 ps
CPU time 1.24 seconds
Started Jan 07 12:56:32 PM PST 24
Finished Jan 07 12:58:19 PM PST 24
Peak memory 199488 kb
Host smart-650d2137-2813-4805-8355-8b63cc7543b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198402337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.3198402337
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.3656853366
Short name T97
Test name
Test status
Simulation time 141327535 ps
CPU time 1.71 seconds
Started Jan 07 12:56:46 PM PST 24
Finished Jan 07 12:58:31 PM PST 24
Peak memory 199320 kb
Host smart-faa5ca64-e74d-445c-9d6e-6c09f51c1fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656853366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.3656853366
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.999529922
Short name T301
Test name
Test status
Simulation time 150326850 ps
CPU time 1.02 seconds
Started Jan 07 12:56:39 PM PST 24
Finished Jan 07 12:58:12 PM PST 24
Peak memory 199372 kb
Host smart-4891cdbb-3f61-4005-bde9-83870b021350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999529922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.999529922
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.3984417402
Short name T65
Test name
Test status
Simulation time 1231831572 ps
CPU time 6.27 seconds
Started Jan 07 12:57:05 PM PST 24
Finished Jan 07 12:58:33 PM PST 24
Peak memory 217856 kb
Host smart-97ea3ebf-14b7-4ccc-82b1-32e72e52099c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984417402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.3984417402
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.1611862922
Short name T30
Test name
Test status
Simulation time 243691469 ps
CPU time 1.1 seconds
Started Jan 07 12:56:54 PM PST 24
Finished Jan 07 12:58:31 PM PST 24
Peak memory 216544 kb
Host smart-41a9c28c-0c3b-4213-9325-f2dd6bcdbe31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611862922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.1611862922
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.112123836
Short name T462
Test name
Test status
Simulation time 157314120 ps
CPU time 0.81 seconds
Started Jan 07 12:56:26 PM PST 24
Finished Jan 07 12:57:56 PM PST 24
Peak memory 199192 kb
Host smart-eba8c4f0-8f2c-4675-ad19-1d8ec7b1102d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112123836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.112123836
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.2344688316
Short name T274
Test name
Test status
Simulation time 1738593787 ps
CPU time 7.3 seconds
Started Jan 07 12:56:42 PM PST 24
Finished Jan 07 12:58:36 PM PST 24
Peak memory 199480 kb
Host smart-c6513122-309f-4d4c-9cc8-82239c421846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344688316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.2344688316
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.3324921411
Short name T354
Test name
Test status
Simulation time 95907635 ps
CPU time 0.96 seconds
Started Jan 07 12:56:39 PM PST 24
Finished Jan 07 12:58:17 PM PST 24
Peak memory 199384 kb
Host smart-daec53ff-d965-42fc-866b-155ddd36e12c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324921411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.3324921411
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.1407521532
Short name T302
Test name
Test status
Simulation time 119735941 ps
CPU time 1.21 seconds
Started Jan 07 12:56:54 PM PST 24
Finished Jan 07 12:58:30 PM PST 24
Peak memory 199356 kb
Host smart-30d80c25-c3b3-41b0-a48e-cc4e7c58e221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407521532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.1407521532
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.2655970728
Short name T365
Test name
Test status
Simulation time 123332190 ps
CPU time 1.4 seconds
Started Jan 07 12:56:29 PM PST 24
Finished Jan 07 12:57:57 PM PST 24
Peak memory 199380 kb
Host smart-11cee75c-c4e0-4770-91bd-aebbde0fa136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655970728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.2655970728
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.1394673056
Short name T333
Test name
Test status
Simulation time 90996713 ps
CPU time 0.79 seconds
Started Jan 07 12:56:27 PM PST 24
Finished Jan 07 12:57:51 PM PST 24
Peak memory 199192 kb
Host smart-86c93ab6-6ff2-48ef-8bdb-61c6ca7e7a56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394673056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.1394673056
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.1252799379
Short name T53
Test name
Test status
Simulation time 1907089554 ps
CPU time 7.65 seconds
Started Jan 07 12:56:48 PM PST 24
Finished Jan 07 12:58:24 PM PST 24
Peak memory 216736 kb
Host smart-3b65449a-d2a2-4d89-a31a-8a7c88622aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252799379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.1252799379
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.1592529588
Short name T269
Test name
Test status
Simulation time 243742631 ps
CPU time 1.13 seconds
Started Jan 07 12:56:58 PM PST 24
Finished Jan 07 12:58:45 PM PST 24
Peak memory 216396 kb
Host smart-f56973cc-f091-496b-9d6b-89f114551e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592529588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.1592529588
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.1377344191
Short name T410
Test name
Test status
Simulation time 130863756 ps
CPU time 0.78 seconds
Started Jan 07 12:57:07 PM PST 24
Finished Jan 07 12:58:27 PM PST 24
Peak memory 199160 kb
Host smart-7fe6982d-1b2b-4dbc-84c9-2fc527904337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377344191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.1377344191
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.2495384237
Short name T247
Test name
Test status
Simulation time 1878178466 ps
CPU time 6.16 seconds
Started Jan 07 12:57:10 PM PST 24
Finished Jan 07 12:58:36 PM PST 24
Peak memory 199468 kb
Host smart-5db1bff9-e34e-406b-86de-2e9c8d43ca9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495384237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.2495384237
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.2038921758
Short name T245
Test name
Test status
Simulation time 191746670 ps
CPU time 1.11 seconds
Started Jan 07 12:57:05 PM PST 24
Finished Jan 07 12:58:56 PM PST 24
Peak memory 199340 kb
Host smart-343944e5-9f46-440e-8848-7ef1430a7c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038921758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.2038921758
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.58121994
Short name T402
Test name
Test status
Simulation time 260114480 ps
CPU time 1.52 seconds
Started Jan 07 12:57:01 PM PST 24
Finished Jan 07 12:58:52 PM PST 24
Peak memory 199528 kb
Host smart-e00d998c-41c8-4e23-aa6a-09f72e8c7f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58121994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.58121994
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.666976432
Short name T422
Test name
Test status
Simulation time 4161762843 ps
CPU time 15.58 seconds
Started Jan 07 12:56:26 PM PST 24
Finished Jan 07 12:58:32 PM PST 24
Peak memory 199576 kb
Host smart-ae362b38-f4c8-432c-a00e-56e0472ad7e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666976432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.666976432
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.3113543832
Short name T394
Test name
Test status
Simulation time 389697948 ps
CPU time 2.12 seconds
Started Jan 07 12:56:36 PM PST 24
Finished Jan 07 12:58:15 PM PST 24
Peak memory 199348 kb
Host smart-ec7b530c-1977-49f9-ac4e-fbb70af016c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113543832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.3113543832
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.547935467
Short name T126
Test name
Test status
Simulation time 126706702 ps
CPU time 0.93 seconds
Started Jan 07 12:56:47 PM PST 24
Finished Jan 07 12:58:06 PM PST 24
Peak memory 199404 kb
Host smart-14ead80c-aef4-4a25-89f0-35da3cd98bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547935467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.547935467
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.1387658919
Short name T326
Test name
Test status
Simulation time 84605632 ps
CPU time 0.82 seconds
Started Jan 07 12:55:53 PM PST 24
Finished Jan 07 12:57:27 PM PST 24
Peak memory 199156 kb
Host smart-dd114e05-bc4d-4053-9bb1-f5f6551de844
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387658919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.1387658919
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.3537871925
Short name T283
Test name
Test status
Simulation time 2178080405 ps
CPU time 7.71 seconds
Started Jan 07 12:55:52 PM PST 24
Finished Jan 07 12:57:36 PM PST 24
Peak memory 220936 kb
Host smart-17eab4aa-e677-42b4-8828-14e12ae1c389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537871925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.3537871925
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.1139878218
Short name T390
Test name
Test status
Simulation time 243655380 ps
CPU time 1.07 seconds
Started Jan 07 12:55:51 PM PST 24
Finished Jan 07 12:57:54 PM PST 24
Peak memory 216556 kb
Host smart-c6ae9c79-770a-411d-bcad-071534374640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139878218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.1139878218
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_reset.1505495059
Short name T551
Test name
Test status
Simulation time 1890459290 ps
CPU time 6.32 seconds
Started Jan 07 12:56:25 PM PST 24
Finished Jan 07 12:58:21 PM PST 24
Peak memory 199472 kb
Host smart-40e5e2ae-9b5e-4de6-809f-112c4f8cb0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505495059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.1505495059
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.3409671646
Short name T80
Test name
Test status
Simulation time 16520695765 ps
CPU time 32.79 seconds
Started Jan 07 12:55:54 PM PST 24
Finished Jan 07 12:58:23 PM PST 24
Peak memory 221124 kb
Host smart-abfe3c74-7568-416c-94bf-c2ec03cc9aad
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409671646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.3409671646
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.878899760
Short name T263
Test name
Test status
Simulation time 115114639 ps
CPU time 0.97 seconds
Started Jan 07 12:56:28 PM PST 24
Finished Jan 07 12:58:15 PM PST 24
Peak memory 199348 kb
Host smart-1843e80f-1d1f-4272-988a-e1b19cafc3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878899760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.878899760
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.3655812507
Short name T203
Test name
Test status
Simulation time 198441723 ps
CPU time 1.31 seconds
Started Jan 07 12:56:21 PM PST 24
Finished Jan 07 12:57:52 PM PST 24
Peak memory 199504 kb
Host smart-ba531046-1a1b-406a-91ee-304a8bff5cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655812507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.3655812507
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.161012105
Short name T336
Test name
Test status
Simulation time 4304822445 ps
CPU time 19.26 seconds
Started Jan 07 12:56:05 PM PST 24
Finished Jan 07 12:57:47 PM PST 24
Peak memory 199540 kb
Host smart-a183a82e-8e41-4fee-92fb-2e92ebc8d73d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161012105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.161012105
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.115786097
Short name T281
Test name
Test status
Simulation time 128149169 ps
CPU time 1.58 seconds
Started Jan 07 12:56:30 PM PST 24
Finished Jan 07 12:58:06 PM PST 24
Peak memory 199332 kb
Host smart-df31da7d-1511-4381-8eb1-785e0602413f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115786097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.115786097
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.2496806280
Short name T449
Test name
Test status
Simulation time 78823169 ps
CPU time 0.74 seconds
Started Jan 07 12:55:56 PM PST 24
Finished Jan 07 12:57:18 PM PST 24
Peak memory 199336 kb
Host smart-d3231b49-a43e-4418-ba85-54615a25aa99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496806280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.2496806280
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.1366435043
Short name T226
Test name
Test status
Simulation time 79245123 ps
CPU time 0.72 seconds
Started Jan 07 12:56:39 PM PST 24
Finished Jan 07 12:58:01 PM PST 24
Peak memory 199152 kb
Host smart-b20d4648-6c48-4dbe-8a8c-fe8a288eb960
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366435043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.1366435043
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.2719197082
Short name T488
Test name
Test status
Simulation time 2152630654 ps
CPU time 8.78 seconds
Started Jan 07 12:57:11 PM PST 24
Finished Jan 07 12:58:37 PM PST 24
Peak memory 216540 kb
Host smart-b3bcd770-aa63-43d0-8d1b-bb180f8e439e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719197082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.2719197082
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.1627488033
Short name T456
Test name
Test status
Simulation time 243947208 ps
CPU time 1.06 seconds
Started Jan 07 12:57:13 PM PST 24
Finished Jan 07 12:58:44 PM PST 24
Peak memory 216532 kb
Host smart-96997fa3-ced4-44ab-b030-d2ac59afcaf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627488033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.1627488033
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.3815147391
Short name T257
Test name
Test status
Simulation time 211041719 ps
CPU time 0.86 seconds
Started Jan 07 12:56:36 PM PST 24
Finished Jan 07 12:58:27 PM PST 24
Peak memory 199124 kb
Host smart-2900fb99-efe1-41ba-b423-4aafaf889e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815147391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.3815147391
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.4036769536
Short name T452
Test name
Test status
Simulation time 144704194 ps
CPU time 1.08 seconds
Started Jan 07 12:57:10 PM PST 24
Finished Jan 07 12:58:45 PM PST 24
Peak memory 199288 kb
Host smart-f028c557-e26b-46d6-aed7-298b77837f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036769536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.4036769536
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.1060596814
Short name T328
Test name
Test status
Simulation time 9833867288 ps
CPU time 36.29 seconds
Started Jan 07 12:57:10 PM PST 24
Finished Jan 07 12:59:34 PM PST 24
Peak memory 199548 kb
Host smart-81ab6d2d-d0cb-4987-8e09-867860ec9e0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060596814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.1060596814
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.174776612
Short name T214
Test name
Test status
Simulation time 533918755 ps
CPU time 2.77 seconds
Started Jan 07 12:56:39 PM PST 24
Finished Jan 07 12:58:24 PM PST 24
Peak memory 199296 kb
Host smart-158397a5-9f09-4dcf-97e1-33e464694db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174776612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.174776612
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.947940026
Short name T430
Test name
Test status
Simulation time 181067354 ps
CPU time 1.08 seconds
Started Jan 07 12:57:09 PM PST 24
Finished Jan 07 12:58:36 PM PST 24
Peak memory 199340 kb
Host smart-b492f4f4-7de2-403c-8939-3a4423fed6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947940026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.947940026
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.364708594
Short name T37
Test name
Test status
Simulation time 1217413511 ps
CPU time 5.83 seconds
Started Jan 07 12:56:44 PM PST 24
Finished Jan 07 12:58:25 PM PST 24
Peak memory 220848 kb
Host smart-e7e6a815-9698-4f30-9954-8816f2e77ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364708594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.364708594
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.2893388369
Short name T400
Test name
Test status
Simulation time 243792287 ps
CPU time 1.09 seconds
Started Jan 07 12:57:01 PM PST 24
Finished Jan 07 12:58:44 PM PST 24
Peak memory 216544 kb
Host smart-110edad5-2f44-4849-8a5e-4c2580c2a6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893388369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.2893388369
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.3137143379
Short name T515
Test name
Test status
Simulation time 188661121 ps
CPU time 1.15 seconds
Started Jan 07 12:56:44 PM PST 24
Finished Jan 07 12:58:07 PM PST 24
Peak memory 199340 kb
Host smart-79a78a56-a9cb-4fb6-8b74-98586d47afb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137143379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.3137143379
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.4277691849
Short name T465
Test name
Test status
Simulation time 120078003 ps
CPU time 1.16 seconds
Started Jan 07 12:56:54 PM PST 24
Finished Jan 07 12:58:32 PM PST 24
Peak memory 199484 kb
Host smart-9744ce47-66a4-4740-a979-648bacf9c701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277691849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.4277691849
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.1238166037
Short name T500
Test name
Test status
Simulation time 8103101396 ps
CPU time 28.16 seconds
Started Jan 07 12:56:39 PM PST 24
Finished Jan 07 12:58:54 PM PST 24
Peak memory 199520 kb
Host smart-fa3c9ebf-f4b5-422e-8937-926fbbff3c5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238166037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.1238166037
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.1682079687
Short name T458
Test name
Test status
Simulation time 409319961 ps
CPU time 2.2 seconds
Started Jan 07 12:56:55 PM PST 24
Finished Jan 07 12:58:33 PM PST 24
Peak memory 199332 kb
Host smart-6d66a53e-7175-4dcc-85cd-b61c3b84fac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682079687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.1682079687
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.973227126
Short name T544
Test name
Test status
Simulation time 138655314 ps
CPU time 1.05 seconds
Started Jan 07 12:56:39 PM PST 24
Finished Jan 07 12:58:01 PM PST 24
Peak memory 199372 kb
Host smart-672e3cbd-da28-4d8e-a5a7-76eeddc00cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973227126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.973227126
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.1689397351
Short name T413
Test name
Test status
Simulation time 86703185 ps
CPU time 0.8 seconds
Started Jan 07 12:56:57 PM PST 24
Finished Jan 07 12:58:14 PM PST 24
Peak memory 199228 kb
Host smart-3d663771-4235-4938-94ec-80f354fbce7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689397351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.1689397351
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.2732584282
Short name T528
Test name
Test status
Simulation time 1893798134 ps
CPU time 7.06 seconds
Started Jan 07 12:56:42 PM PST 24
Finished Jan 07 12:58:29 PM PST 24
Peak memory 216764 kb
Host smart-9693a11c-477a-41fb-9eb3-bdf2a218434e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732584282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.2732584282
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.2451233764
Short name T261
Test name
Test status
Simulation time 244996394 ps
CPU time 1.08 seconds
Started Jan 07 12:57:11 PM PST 24
Finished Jan 07 12:58:28 PM PST 24
Peak memory 216476 kb
Host smart-a114315f-5ae6-4be5-b6ca-d6543e99fa7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451233764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.2451233764
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.1163949257
Short name T406
Test name
Test status
Simulation time 158873850 ps
CPU time 0.79 seconds
Started Jan 07 12:56:55 PM PST 24
Finished Jan 07 12:58:28 PM PST 24
Peak memory 199176 kb
Host smart-ea1333d0-a711-4e8e-a77d-bf4841ad5c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163949257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.1163949257
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.3630862876
Short name T244
Test name
Test status
Simulation time 1519047658 ps
CPU time 5.54 seconds
Started Jan 07 12:57:11 PM PST 24
Finished Jan 07 12:58:54 PM PST 24
Peak memory 199480 kb
Host smart-236b1057-6560-4ba6-ad92-5f8580198a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630862876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.3630862876
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.4018079673
Short name T321
Test name
Test status
Simulation time 111024323 ps
CPU time 0.95 seconds
Started Jan 07 12:57:11 PM PST 24
Finished Jan 07 12:58:40 PM PST 24
Peak memory 199352 kb
Host smart-033ffcee-6df9-4e71-99e3-7a73b1adb34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018079673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.4018079673
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.736819971
Short name T2
Test name
Test status
Simulation time 117872362 ps
CPU time 1.12 seconds
Started Jan 07 12:56:55 PM PST 24
Finished Jan 07 12:58:54 PM PST 24
Peak memory 199472 kb
Host smart-c69df9ad-8b93-4f2c-ac27-f5a2ff76df85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736819971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.736819971
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.696661366
Short name T319
Test name
Test status
Simulation time 2561221640 ps
CPU time 10.92 seconds
Started Jan 07 12:56:55 PM PST 24
Finished Jan 07 12:59:04 PM PST 24
Peak memory 199660 kb
Host smart-6c0c7a0d-d4fc-44ce-bdcd-59e4a225aeda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696661366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.696661366
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.1407461389
Short name T95
Test name
Test status
Simulation time 340573334 ps
CPU time 2.2 seconds
Started Jan 07 12:56:56 PM PST 24
Finished Jan 07 12:58:30 PM PST 24
Peak memory 199360 kb
Host smart-21a781bf-ec58-4771-a820-b9ce34343c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407461389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.1407461389
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.2695295735
Short name T298
Test name
Test status
Simulation time 191939030 ps
CPU time 1.19 seconds
Started Jan 07 12:56:59 PM PST 24
Finished Jan 07 12:58:35 PM PST 24
Peak memory 199336 kb
Host smart-dc7d2a83-2f4b-4246-959c-387f664101c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695295735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.2695295735
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.212389118
Short name T396
Test name
Test status
Simulation time 67237609 ps
CPU time 0.71 seconds
Started Jan 07 12:56:48 PM PST 24
Finished Jan 07 12:58:06 PM PST 24
Peak memory 199132 kb
Host smart-17c55495-f2d0-44e6-a790-6a2e53f648c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212389118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.212389118
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.1083184660
Short name T48
Test name
Test status
Simulation time 2152419078 ps
CPU time 7.66 seconds
Started Jan 07 12:57:00 PM PST 24
Finished Jan 07 12:58:36 PM PST 24
Peak memory 216764 kb
Host smart-33293a3a-5c78-4d07-9244-b31622a122d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083184660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.1083184660
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.2506902133
Short name T474
Test name
Test status
Simulation time 244528327 ps
CPU time 1.03 seconds
Started Jan 07 12:57:19 PM PST 24
Finished Jan 07 12:58:58 PM PST 24
Peak memory 216560 kb
Host smart-a64d1be0-d1ca-4944-8f94-b9efefeaefb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506902133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.2506902133
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.2800518462
Short name T519
Test name
Test status
Simulation time 157995343 ps
CPU time 0.88 seconds
Started Jan 07 12:56:42 PM PST 24
Finished Jan 07 12:58:38 PM PST 24
Peak memory 199128 kb
Host smart-9150e2fc-562c-4d4b-9915-0638866bf628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800518462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.2800518462
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.2533203685
Short name T287
Test name
Test status
Simulation time 1348573622 ps
CPU time 5.24 seconds
Started Jan 07 12:56:50 PM PST 24
Finished Jan 07 12:58:17 PM PST 24
Peak memory 199528 kb
Host smart-ada3772c-dccb-4003-b67f-21b169c9894c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533203685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.2533203685
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.3703029521
Short name T387
Test name
Test status
Simulation time 173494123 ps
CPU time 1.23 seconds
Started Jan 07 12:56:51 PM PST 24
Finished Jan 07 12:58:52 PM PST 24
Peak memory 199388 kb
Host smart-fda12ab1-7b4e-4c35-9018-f21308a8d360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703029521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.3703029521
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.2909371172
Short name T514
Test name
Test status
Simulation time 229697158 ps
CPU time 1.56 seconds
Started Jan 07 12:56:43 PM PST 24
Finished Jan 07 12:58:09 PM PST 24
Peak memory 199480 kb
Host smart-1e5df204-f843-4846-8b86-8d2b299b7e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909371172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.2909371172
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.473689102
Short name T540
Test name
Test status
Simulation time 3994432361 ps
CPU time 13.7 seconds
Started Jan 07 12:56:59 PM PST 24
Finished Jan 07 12:58:42 PM PST 24
Peak memory 199504 kb
Host smart-1b062e5d-83c3-492f-8bf8-16ed7feb4b30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473689102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.473689102
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.320244613
Short name T351
Test name
Test status
Simulation time 356112238 ps
CPU time 2.26 seconds
Started Jan 07 12:57:20 PM PST 24
Finished Jan 07 12:58:47 PM PST 24
Peak memory 199304 kb
Host smart-cf6299f1-e2e1-491e-a4fb-d301f851d35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320244613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.320244613
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.4255589031
Short name T228
Test name
Test status
Simulation time 193649609 ps
CPU time 1.27 seconds
Started Jan 07 12:56:43 PM PST 24
Finished Jan 07 12:58:19 PM PST 24
Peak memory 199400 kb
Host smart-3e8542c5-235a-42af-ba9d-dae0549683f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255589031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.4255589031
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.2186334576
Short name T242
Test name
Test status
Simulation time 67479732 ps
CPU time 0.7 seconds
Started Jan 07 12:57:25 PM PST 24
Finished Jan 07 12:58:54 PM PST 24
Peak memory 199104 kb
Host smart-4f3025f7-0141-46c3-9881-795e51cef5ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186334576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.2186334576
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.2289272780
Short name T538
Test name
Test status
Simulation time 1220953648 ps
CPU time 5.05 seconds
Started Jan 07 12:57:24 PM PST 24
Finished Jan 07 12:59:00 PM PST 24
Peak memory 216252 kb
Host smart-270a025b-433c-4794-a27b-42c417d41a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289272780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.2289272780
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.2634249114
Short name T61
Test name
Test status
Simulation time 249037923 ps
CPU time 1.02 seconds
Started Jan 07 12:56:52 PM PST 24
Finished Jan 07 12:58:19 PM PST 24
Peak memory 216612 kb
Host smart-5e7ffdb5-db85-4d50-b4ed-a05a5f7dd344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634249114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.2634249114
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.1405571301
Short name T317
Test name
Test status
Simulation time 132986279 ps
CPU time 0.75 seconds
Started Jan 07 12:56:42 PM PST 24
Finished Jan 07 12:58:40 PM PST 24
Peak memory 199136 kb
Host smart-1799f27d-0f1d-40e1-af4a-1cfb5c67af14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405571301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.1405571301
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.3073448127
Short name T290
Test name
Test status
Simulation time 953288121 ps
CPU time 4.94 seconds
Started Jan 07 12:56:45 PM PST 24
Finished Jan 07 12:58:25 PM PST 24
Peak memory 199464 kb
Host smart-65c9f954-fd47-40c1-89b6-30ff2ff1d289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073448127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.3073448127
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.4244042210
Short name T447
Test name
Test status
Simulation time 187355782 ps
CPU time 1.2 seconds
Started Jan 07 12:57:05 PM PST 24
Finished Jan 07 12:58:43 PM PST 24
Peak memory 199348 kb
Host smart-b4ea7afe-d3da-418e-a654-00b2cf671ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244042210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.4244042210
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.4170059370
Short name T348
Test name
Test status
Simulation time 124364526 ps
CPU time 1.18 seconds
Started Jan 07 12:56:46 PM PST 24
Finished Jan 07 12:58:17 PM PST 24
Peak memory 199480 kb
Host smart-f2911a9b-af24-4d4c-abfd-1f0f15da9c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170059370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.4170059370
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.766929571
Short name T292
Test name
Test status
Simulation time 194943189 ps
CPU time 1.32 seconds
Started Jan 07 12:57:08 PM PST 24
Finished Jan 07 12:58:37 PM PST 24
Peak memory 199488 kb
Host smart-3b2634e2-573e-435e-9f43-37ef925534b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766929571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.766929571
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.2989997803
Short name T384
Test name
Test status
Simulation time 357034411 ps
CPU time 2.25 seconds
Started Jan 07 12:56:59 PM PST 24
Finished Jan 07 12:58:18 PM PST 24
Peak memory 199348 kb
Host smart-5cf9189b-1491-4303-8dd8-961246f49584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989997803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.2989997803
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.1748647578
Short name T28
Test name
Test status
Simulation time 115164650 ps
CPU time 0.9 seconds
Started Jan 07 12:56:52 PM PST 24
Finished Jan 07 12:58:37 PM PST 24
Peak memory 199436 kb
Host smart-fea15607-0657-46ec-bd49-67c28cd4766d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748647578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.1748647578
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.1181621904
Short name T221
Test name
Test status
Simulation time 63649340 ps
CPU time 0.68 seconds
Started Jan 07 12:56:55 PM PST 24
Finished Jan 07 12:58:40 PM PST 24
Peak memory 199128 kb
Host smart-c8ee86ad-e6b4-4e5c-92ca-81b207e9b1fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181621904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.1181621904
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.1577139744
Short name T466
Test name
Test status
Simulation time 1224173077 ps
CPU time 5.14 seconds
Started Jan 07 12:57:10 PM PST 24
Finished Jan 07 12:58:44 PM PST 24
Peak memory 216200 kb
Host smart-7e134fab-3a20-4d84-8578-6f9ebae59897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577139744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.1577139744
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.49503056
Short name T441
Test name
Test status
Simulation time 244327669 ps
CPU time 1.1 seconds
Started Jan 07 12:56:39 PM PST 24
Finished Jan 07 12:58:33 PM PST 24
Peak memory 216652 kb
Host smart-c32eb283-261a-4c2d-b4b5-5b35d7774070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49503056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.49503056
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.3001901491
Short name T23
Test name
Test status
Simulation time 222625011 ps
CPU time 0.98 seconds
Started Jan 07 12:57:20 PM PST 24
Finished Jan 07 12:58:45 PM PST 24
Peak memory 199108 kb
Host smart-4d3a6ecc-8b0a-4b40-8f15-c25bcfe1ed70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001901491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.3001901491
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.2456893403
Short name T327
Test name
Test status
Simulation time 1677217987 ps
CPU time 6.33 seconds
Started Jan 07 12:57:24 PM PST 24
Finished Jan 07 12:58:54 PM PST 24
Peak memory 199472 kb
Host smart-6840ddc5-9cff-4200-af84-65401d1159f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456893403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.2456893403
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.991301830
Short name T439
Test name
Test status
Simulation time 99911403 ps
CPU time 0.93 seconds
Started Jan 07 12:56:52 PM PST 24
Finished Jan 07 12:58:38 PM PST 24
Peak memory 199340 kb
Host smart-e4030dd4-6a2b-4f9f-972c-0a1d1668c403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991301830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.991301830
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.767788499
Short name T209
Test name
Test status
Simulation time 203449442 ps
CPU time 1.31 seconds
Started Jan 07 12:57:02 PM PST 24
Finished Jan 07 12:58:36 PM PST 24
Peak memory 199480 kb
Host smart-19c8d4e3-23d5-4f03-8ea8-63e750d64806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767788499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.767788499
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.1363461142
Short name T425
Test name
Test status
Simulation time 4420445088 ps
CPU time 18.34 seconds
Started Jan 07 12:56:40 PM PST 24
Finished Jan 07 12:58:32 PM PST 24
Peak memory 199544 kb
Host smart-680839cc-0dbb-4dac-a183-73314d2dd2a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363461142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.1363461142
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.3157293343
Short name T304
Test name
Test status
Simulation time 486498870 ps
CPU time 2.56 seconds
Started Jan 07 12:57:11 PM PST 24
Finished Jan 07 12:58:43 PM PST 24
Peak memory 199328 kb
Host smart-812dcce3-9de9-496d-9df2-de15d57e530e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157293343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.3157293343
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.3972202867
Short name T491
Test name
Test status
Simulation time 183279142 ps
CPU time 1.12 seconds
Started Jan 07 12:56:55 PM PST 24
Finished Jan 07 12:58:49 PM PST 24
Peak memory 199312 kb
Host smart-9a3b4352-7ac2-40b3-b56e-ace20cd3d6a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972202867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.3972202867
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.2122713234
Short name T480
Test name
Test status
Simulation time 61569882 ps
CPU time 0.74 seconds
Started Jan 07 12:56:55 PM PST 24
Finished Jan 07 12:58:49 PM PST 24
Peak memory 199232 kb
Host smart-e0a34976-c301-4637-91f2-3e349bf35ea9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122713234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.2122713234
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.932695718
Short name T47
Test name
Test status
Simulation time 1226500587 ps
CPU time 5.55 seconds
Started Jan 07 12:56:56 PM PST 24
Finished Jan 07 12:58:37 PM PST 24
Peak memory 217292 kb
Host smart-53eca95b-49f2-4ebe-9ea4-30e09bb05265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932695718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.932695718
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.2511340521
Short name T419
Test name
Test status
Simulation time 243457485 ps
CPU time 1.06 seconds
Started Jan 07 12:57:00 PM PST 24
Finished Jan 07 12:58:41 PM PST 24
Peak memory 216512 kb
Host smart-5f2b0428-47b4-4dc0-89e4-c85f7c1dda65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511340521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.2511340521
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.3023138710
Short name T25
Test name
Test status
Simulation time 110483216 ps
CPU time 0.78 seconds
Started Jan 07 12:56:42 PM PST 24
Finished Jan 07 12:58:29 PM PST 24
Peak memory 199176 kb
Host smart-fb74f5c6-c93a-465f-ab0d-60d405b8580d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023138710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.3023138710
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.1084639391
Short name T520
Test name
Test status
Simulation time 1839708524 ps
CPU time 6.94 seconds
Started Jan 07 12:56:59 PM PST 24
Finished Jan 07 12:58:41 PM PST 24
Peak memory 199536 kb
Host smart-1329b9c0-c67c-46a2-be47-b51f48dcb212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084639391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.1084639391
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.1925055021
Short name T431
Test name
Test status
Simulation time 99357472 ps
CPU time 0.95 seconds
Started Jan 07 12:57:02 PM PST 24
Finished Jan 07 12:58:32 PM PST 24
Peak memory 199344 kb
Host smart-f74bda48-fd2b-40f3-a719-a0480c6bfcf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925055021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.1925055021
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.767347194
Short name T454
Test name
Test status
Simulation time 123455908 ps
CPU time 1.17 seconds
Started Jan 07 12:57:05 PM PST 24
Finished Jan 07 12:58:49 PM PST 24
Peak memory 199540 kb
Host smart-370db964-014b-4439-b1a7-49e327796e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767347194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.767347194
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.4280024446
Short name T490
Test name
Test status
Simulation time 350744797 ps
CPU time 2.04 seconds
Started Jan 07 12:57:10 PM PST 24
Finished Jan 07 12:58:37 PM PST 24
Peak memory 199340 kb
Host smart-4f1865e4-d224-4294-bafa-4a45b352ef0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280024446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.4280024446
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.2198105137
Short name T7
Test name
Test status
Simulation time 131081144 ps
CPU time 1.13 seconds
Started Jan 07 12:56:58 PM PST 24
Finished Jan 07 12:58:24 PM PST 24
Peak memory 199368 kb
Host smart-5d4e0473-bfe3-4469-8115-8d8c8674adb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198105137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.2198105137
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.1029143104
Short name T236
Test name
Test status
Simulation time 67117341 ps
CPU time 0.71 seconds
Started Jan 07 12:56:42 PM PST 24
Finished Jan 07 12:58:18 PM PST 24
Peak memory 199140 kb
Host smart-3e83d6d2-01aa-4255-8f43-87db40dbe7f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029143104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.1029143104
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.2421176116
Short name T546
Test name
Test status
Simulation time 1904373426 ps
CPU time 6.89 seconds
Started Jan 07 12:56:43 PM PST 24
Finished Jan 07 12:58:17 PM PST 24
Peak memory 217272 kb
Host smart-f097bd93-3c34-43e0-95cf-b915db91f2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421176116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.2421176116
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.1537793072
Short name T363
Test name
Test status
Simulation time 245992159 ps
CPU time 1.03 seconds
Started Jan 07 12:57:10 PM PST 24
Finished Jan 07 12:58:31 PM PST 24
Peak memory 216364 kb
Host smart-79f18d54-44da-4c93-9ddc-9e1b0b38e124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537793072 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.1537793072
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.3399055989
Short name T340
Test name
Test status
Simulation time 203624584 ps
CPU time 0.91 seconds
Started Jan 07 12:56:44 PM PST 24
Finished Jan 07 12:58:20 PM PST 24
Peak memory 199176 kb
Host smart-7c71426b-0d75-452f-af34-fb5f3bb3172c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399055989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.3399055989
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.3882453751
Short name T548
Test name
Test status
Simulation time 1885496149 ps
CPU time 6.52 seconds
Started Jan 07 12:57:05 PM PST 24
Finished Jan 07 12:58:33 PM PST 24
Peak memory 199444 kb
Host smart-2e9b4128-45ca-44f8-a412-f1fcbfcd9c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882453751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.3882453751
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.3485442699
Short name T243
Test name
Test status
Simulation time 104777324 ps
CPU time 0.93 seconds
Started Jan 07 12:56:49 PM PST 24
Finished Jan 07 12:58:17 PM PST 24
Peak memory 199296 kb
Host smart-d56413a9-aee7-4ba4-b5a9-f3d158e353b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485442699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.3485442699
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.1459032418
Short name T42
Test name
Test status
Simulation time 262738086 ps
CPU time 1.41 seconds
Started Jan 07 12:56:59 PM PST 24
Finished Jan 07 12:58:17 PM PST 24
Peak memory 199484 kb
Host smart-f21a22f1-d2d9-473a-bd94-c61890237d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459032418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.1459032418
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.3673379465
Short name T420
Test name
Test status
Simulation time 10752625476 ps
CPU time 36.91 seconds
Started Jan 07 12:56:52 PM PST 24
Finished Jan 07 12:59:07 PM PST 24
Peak memory 199568 kb
Host smart-56282799-9e94-4d0c-9bb1-cc7fcb428bcd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673379465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.3673379465
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.3554685882
Short name T86
Test name
Test status
Simulation time 476000398 ps
CPU time 2.53 seconds
Started Jan 07 12:56:58 PM PST 24
Finished Jan 07 12:58:44 PM PST 24
Peak memory 199292 kb
Host smart-0e03e25a-7be7-4bf9-b9ba-17db9572732e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554685882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.3554685882
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.2866387158
Short name T275
Test name
Test status
Simulation time 127110392 ps
CPU time 0.95 seconds
Started Jan 07 12:57:14 PM PST 24
Finished Jan 07 12:58:37 PM PST 24
Peak memory 199300 kb
Host smart-f24074ad-8a3d-4b07-869b-cf1a6a8f05d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866387158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.2866387158
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.4006459648
Short name T479
Test name
Test status
Simulation time 69245040 ps
CPU time 0.72 seconds
Started Jan 07 12:57:12 PM PST 24
Finished Jan 07 12:58:51 PM PST 24
Peak memory 199184 kb
Host smart-71f5ea19-0ea4-4676-857b-e844610759a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006459648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.4006459648
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.3844257504
Short name T49
Test name
Test status
Simulation time 1214295684 ps
CPU time 5.44 seconds
Started Jan 07 12:56:58 PM PST 24
Finished Jan 07 12:58:49 PM PST 24
Peak memory 216720 kb
Host smart-6857552f-49e5-4d34-9398-564cd02ab0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844257504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.3844257504
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.2861320698
Short name T55
Test name
Test status
Simulation time 243791414 ps
CPU time 1.05 seconds
Started Jan 07 12:57:06 PM PST 24
Finished Jan 07 12:58:37 PM PST 24
Peak memory 216352 kb
Host smart-e6eaeb1c-00f4-4436-9a7f-ade15aed8ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861320698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.2861320698
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.3537061859
Short name T356
Test name
Test status
Simulation time 90194076 ps
CPU time 0.72 seconds
Started Jan 07 12:56:43 PM PST 24
Finished Jan 07 12:58:19 PM PST 24
Peak memory 199200 kb
Host smart-97d77f61-9026-4ead-9b4c-6cfdf28c8b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537061859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.3537061859
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.4151996427
Short name T57
Test name
Test status
Simulation time 915085166 ps
CPU time 4.87 seconds
Started Jan 07 12:56:52 PM PST 24
Finished Jan 07 12:58:32 PM PST 24
Peak memory 199480 kb
Host smart-7ef58afa-4be2-47d4-8640-772ed205a284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151996427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.4151996427
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.2990012498
Short name T330
Test name
Test status
Simulation time 96480447 ps
CPU time 0.94 seconds
Started Jan 07 12:56:51 PM PST 24
Finished Jan 07 12:58:32 PM PST 24
Peak memory 199432 kb
Host smart-b0702bc0-e66c-43fb-9c8d-292abc449100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990012498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.2990012498
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.710874225
Short name T505
Test name
Test status
Simulation time 202737542 ps
CPU time 1.27 seconds
Started Jan 07 12:56:43 PM PST 24
Finished Jan 07 12:58:17 PM PST 24
Peak memory 199504 kb
Host smart-b21ec08a-c3c8-480c-9cd2-6c62961df842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710874225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.710874225
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.2984748209
Short name T527
Test name
Test status
Simulation time 4656521639 ps
CPU time 18.61 seconds
Started Jan 07 12:56:49 PM PST 24
Finished Jan 07 12:58:34 PM PST 24
Peak memory 199544 kb
Host smart-5614d1e4-8fd0-46bf-be3c-c965220cfc77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984748209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.2984748209
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.4122746597
Short name T350
Test name
Test status
Simulation time 322614102 ps
CPU time 2.02 seconds
Started Jan 07 12:56:56 PM PST 24
Finished Jan 07 12:58:28 PM PST 24
Peak memory 199340 kb
Host smart-5e67b634-68f4-493e-80f3-1f38c35fa027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122746597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.4122746597
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.3861828827
Short name T127
Test name
Test status
Simulation time 298314975 ps
CPU time 1.6 seconds
Started Jan 07 12:56:42 PM PST 24
Finished Jan 07 12:58:29 PM PST 24
Peak memory 199468 kb
Host smart-7b7b363d-0cbf-493e-a738-16e69cd6f67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861828827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.3861828827
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.4017636123
Short name T142
Test name
Test status
Simulation time 71489690 ps
CPU time 0.75 seconds
Started Jan 07 12:57:23 PM PST 24
Finished Jan 07 12:59:04 PM PST 24
Peak memory 199188 kb
Host smart-31af6727-dd3e-4774-9bb2-088993a97590
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017636123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.4017636123
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.2550499569
Short name T464
Test name
Test status
Simulation time 2355141897 ps
CPU time 7.96 seconds
Started Jan 07 12:57:18 PM PST 24
Finished Jan 07 12:58:50 PM PST 24
Peak memory 217348 kb
Host smart-27f0ec22-6ea9-4f6c-85a9-b74217200f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550499569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.2550499569
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.2186463776
Short name T59
Test name
Test status
Simulation time 245167456 ps
CPU time 1.04 seconds
Started Jan 07 12:57:46 PM PST 24
Finished Jan 07 12:59:10 PM PST 24
Peak memory 216300 kb
Host smart-140eb581-92c9-49d0-85f8-9289c8268fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186463776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.2186463776
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.2163661617
Short name T299
Test name
Test status
Simulation time 209774824 ps
CPU time 0.9 seconds
Started Jan 07 12:56:45 PM PST 24
Finished Jan 07 12:58:55 PM PST 24
Peak memory 199012 kb
Host smart-f2f67e9d-8da7-4523-bf94-51af4ca9afb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163661617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.2163661617
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.1233531983
Short name T204
Test name
Test status
Simulation time 1732410513 ps
CPU time 5.97 seconds
Started Jan 07 12:57:20 PM PST 24
Finished Jan 07 12:58:50 PM PST 24
Peak memory 199472 kb
Host smart-44bd49ca-6764-45f3-9cfb-c08690d4e88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233531983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.1233531983
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.3635704301
Short name T262
Test name
Test status
Simulation time 108239387 ps
CPU time 0.98 seconds
Started Jan 07 12:57:18 PM PST 24
Finished Jan 07 12:58:51 PM PST 24
Peak memory 199248 kb
Host smart-3d318a0d-cc52-4700-ae88-268054b6634e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635704301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.3635704301
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.1666189772
Short name T436
Test name
Test status
Simulation time 251740570 ps
CPU time 1.42 seconds
Started Jan 07 12:56:42 PM PST 24
Finished Jan 07 12:58:28 PM PST 24
Peak memory 199544 kb
Host smart-ea07caea-855f-45f6-8a70-242c7caab0af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666189772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.1666189772
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.716223028
Short name T461
Test name
Test status
Simulation time 4799242879 ps
CPU time 20.66 seconds
Started Jan 07 12:57:23 PM PST 24
Finished Jan 07 12:59:02 PM PST 24
Peak memory 199516 kb
Host smart-46048d6f-ad47-4b22-bfb1-f7719a77b278
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716223028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.716223028
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.2844603396
Short name T92
Test name
Test status
Simulation time 385285285 ps
CPU time 2.21 seconds
Started Jan 07 12:57:18 PM PST 24
Finished Jan 07 12:58:44 PM PST 24
Peak memory 199372 kb
Host smart-7acf40db-ad24-4451-8bd9-df189608ace5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844603396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.2844603396
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.438778623
Short name T536
Test name
Test status
Simulation time 223538368 ps
CPU time 1.39 seconds
Started Jan 07 12:57:18 PM PST 24
Finished Jan 07 12:58:37 PM PST 24
Peak memory 199348 kb
Host smart-86bd57c9-33c4-4434-be97-dcd03967c096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438778623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.438778623
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.859487098
Short name T501
Test name
Test status
Simulation time 61781021 ps
CPU time 0.73 seconds
Started Jan 07 12:56:07 PM PST 24
Finished Jan 07 12:57:44 PM PST 24
Peak memory 199108 kb
Host smart-aa3b9a96-9c72-4b7f-bc89-a213a495a092
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859487098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.859487098
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.2138981005
Short name T66
Test name
Test status
Simulation time 1894619990 ps
CPU time 6.86 seconds
Started Jan 07 12:55:52 PM PST 24
Finished Jan 07 12:58:06 PM PST 24
Peak memory 229544 kb
Host smart-d96521ab-5d45-40d9-98cc-447328d708fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138981005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.2138981005
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.1982445317
Short name T233
Test name
Test status
Simulation time 244362508 ps
CPU time 1 seconds
Started Jan 07 12:56:04 PM PST 24
Finished Jan 07 12:57:41 PM PST 24
Peak memory 216488 kb
Host smart-c8f42ec3-3da6-4249-b2e0-98ed4a792c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982445317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.1982445317
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.2974671511
Short name T493
Test name
Test status
Simulation time 135243807 ps
CPU time 0.92 seconds
Started Jan 07 12:56:02 PM PST 24
Finished Jan 07 12:57:32 PM PST 24
Peak memory 199204 kb
Host smart-9272637f-01c0-4566-aab3-62ecd466b9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974671511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.2974671511
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.2771046088
Short name T498
Test name
Test status
Simulation time 1481508211 ps
CPU time 6 seconds
Started Jan 07 12:55:53 PM PST 24
Finished Jan 07 12:57:36 PM PST 24
Peak memory 199468 kb
Host smart-4c2c2428-9e99-4908-8112-32bbeef1d084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771046088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.2771046088
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.2983113517
Short name T83
Test name
Test status
Simulation time 16593629762 ps
CPU time 24.59 seconds
Started Jan 07 12:56:36 PM PST 24
Finished Jan 07 12:58:56 PM PST 24
Peak memory 217388 kb
Host smart-e684b45d-79ea-4bd1-9bd1-0eca7d76b26c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983113517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.2983113517
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.2611744131
Short name T129
Test name
Test status
Simulation time 145408158 ps
CPU time 1.04 seconds
Started Jan 07 12:55:56 PM PST 24
Finished Jan 07 12:57:25 PM PST 24
Peak memory 199316 kb
Host smart-8b7d9e62-c1b5-41ec-8660-ceb4e1319f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611744131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.2611744131
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.2253452420
Short name T412
Test name
Test status
Simulation time 199690700 ps
CPU time 1.37 seconds
Started Jan 07 12:55:52 PM PST 24
Finished Jan 07 12:57:57 PM PST 24
Peak memory 199356 kb
Host smart-c6072d11-0eec-453f-8c34-c5d85f1d2365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253452420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.2253452420
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.486126934
Short name T337
Test name
Test status
Simulation time 1511454962 ps
CPU time 6.52 seconds
Started Jan 07 12:55:53 PM PST 24
Finished Jan 07 12:57:26 PM PST 24
Peak memory 199532 kb
Host smart-5d1c6b84-d088-40a1-8160-71a74a5280dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486126934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.486126934
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.761889641
Short name T56
Test name
Test status
Simulation time 344204895 ps
CPU time 2.1 seconds
Started Jan 07 12:55:58 PM PST 24
Finished Jan 07 12:57:34 PM PST 24
Peak memory 199268 kb
Host smart-c006421d-e474-443b-984c-5af1d5a47ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761889641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.761889641
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.374313620
Short name T469
Test name
Test status
Simulation time 94242829 ps
CPU time 0.85 seconds
Started Jan 07 12:55:56 PM PST 24
Finished Jan 07 12:57:18 PM PST 24
Peak memory 199336 kb
Host smart-4f2f9a0e-f884-4663-ad4d-94d81b4fd822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374313620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.374313620
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.3010630029
Short name T225
Test name
Test status
Simulation time 86495915 ps
CPU time 0.79 seconds
Started Jan 07 12:57:31 PM PST 24
Finished Jan 07 12:59:08 PM PST 24
Peak memory 199144 kb
Host smart-8b87e2c8-0493-4c7c-a959-10cceb1d7e9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010630029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.3010630029
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.2609725981
Short name T335
Test name
Test status
Simulation time 1225667653 ps
CPU time 5.71 seconds
Started Jan 07 12:57:48 PM PST 24
Finished Jan 07 12:59:21 PM PST 24
Peak memory 216176 kb
Host smart-1211d659-6095-4768-95be-ede94875a8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609725981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.2609725981
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.2452771369
Short name T523
Test name
Test status
Simulation time 91414433 ps
CPU time 0.73 seconds
Started Jan 07 12:57:25 PM PST 24
Finished Jan 07 12:58:52 PM PST 24
Peak memory 199152 kb
Host smart-6f2580b7-2c6d-4810-870d-5926c1c962bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452771369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.2452771369
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.3847117938
Short name T306
Test name
Test status
Simulation time 1954714009 ps
CPU time 7.75 seconds
Started Jan 07 12:57:21 PM PST 24
Finished Jan 07 12:59:13 PM PST 24
Peak memory 199476 kb
Host smart-9cfe8a98-e48a-46f4-8795-8ac312e9914c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847117938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.3847117938
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.3035837492
Short name T231
Test name
Test status
Simulation time 169250161 ps
CPU time 1.08 seconds
Started Jan 07 12:57:46 PM PST 24
Finished Jan 07 12:59:16 PM PST 24
Peak memory 199328 kb
Host smart-5eaffd72-7549-43cc-8d57-59a4113df8ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035837492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.3035837492
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.2889979255
Short name T552
Test name
Test status
Simulation time 254861218 ps
CPU time 1.54 seconds
Started Jan 07 12:57:18 PM PST 24
Finished Jan 07 12:58:43 PM PST 24
Peak memory 199460 kb
Host smart-45793ce0-fbb5-45d3-96cd-63d472d01e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889979255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.2889979255
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.774567383
Short name T260
Test name
Test status
Simulation time 15481109478 ps
CPU time 53.47 seconds
Started Jan 07 12:57:33 PM PST 24
Finished Jan 07 12:59:58 PM PST 24
Peak memory 199536 kb
Host smart-305c45b4-6704-4a62-99a4-339bc73e7c55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774567383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.774567383
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.1437022559
Short name T382
Test name
Test status
Simulation time 134665336 ps
CPU time 1.62 seconds
Started Jan 07 12:57:24 PM PST 24
Finished Jan 07 12:58:56 PM PST 24
Peak memory 199316 kb
Host smart-fde9c00e-bcb6-4014-8dc7-2b728aee49c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437022559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.1437022559
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.3597482605
Short name T455
Test name
Test status
Simulation time 241984433 ps
CPU time 1.32 seconds
Started Jan 07 12:57:19 PM PST 24
Finished Jan 07 12:58:58 PM PST 24
Peak memory 199392 kb
Host smart-54fae173-8a37-4442-88d7-dd2f461fd7b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597482605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.3597482605
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.720829121
Short name T1
Test name
Test status
Simulation time 67982062 ps
CPU time 0.72 seconds
Started Jan 07 12:57:24 PM PST 24
Finished Jan 07 12:58:43 PM PST 24
Peak memory 199160 kb
Host smart-4172dccf-de98-4832-b96c-ae03426dfd1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720829121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.720829121
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.1069399391
Short name T524
Test name
Test status
Simulation time 2351553781 ps
CPU time 8.4 seconds
Started Jan 07 12:57:20 PM PST 24
Finished Jan 07 12:58:52 PM PST 24
Peak memory 218100 kb
Host smart-780ab6e4-ca80-4514-b4d7-6fa2e1288a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069399391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.1069399391
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.2056641570
Short name T84
Test name
Test status
Simulation time 245410245 ps
CPU time 1.01 seconds
Started Jan 07 12:57:17 PM PST 24
Finished Jan 07 12:58:43 PM PST 24
Peak memory 216484 kb
Host smart-db7f5775-7692-4281-b2db-bc464f19f64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056641570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.2056641570
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.770338844
Short name T285
Test name
Test status
Simulation time 81614958 ps
CPU time 0.69 seconds
Started Jan 07 12:57:24 PM PST 24
Finished Jan 07 12:58:55 PM PST 24
Peak memory 199116 kb
Host smart-cd874603-e612-4223-b535-5bf13e4ce82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770338844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.770338844
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.1100873915
Short name T418
Test name
Test status
Simulation time 1722498496 ps
CPU time 6.07 seconds
Started Jan 07 12:57:18 PM PST 24
Finished Jan 07 12:58:47 PM PST 24
Peak memory 199480 kb
Host smart-adda52db-3b88-4cb4-a6ed-371cd3f04ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100873915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.1100873915
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.2324773572
Short name T223
Test name
Test status
Simulation time 96199951 ps
CPU time 1.03 seconds
Started Jan 07 12:57:19 PM PST 24
Finished Jan 07 12:59:06 PM PST 24
Peak memory 199348 kb
Host smart-16e1e1f4-fdb7-489a-b746-e8b538d30fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324773572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.2324773572
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.2200428483
Short name T386
Test name
Test status
Simulation time 112494955 ps
CPU time 1.14 seconds
Started Jan 07 12:57:18 PM PST 24
Finished Jan 07 12:58:48 PM PST 24
Peak memory 199532 kb
Host smart-65dace8c-e8d4-4433-b2e8-64fa44505fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200428483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.2200428483
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.3118925092
Short name T329
Test name
Test status
Simulation time 2158213065 ps
CPU time 7.5 seconds
Started Jan 07 12:57:23 PM PST 24
Finished Jan 07 12:59:08 PM PST 24
Peak memory 199596 kb
Host smart-8465ac21-9928-4d09-a756-47ae072361f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118925092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.3118925092
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.499057605
Short name T60
Test name
Test status
Simulation time 352112410 ps
CPU time 1.83 seconds
Started Jan 07 12:57:23 PM PST 24
Finished Jan 07 12:58:56 PM PST 24
Peak memory 199316 kb
Host smart-c57f3f8d-8c27-4a18-88f2-2d29b6398a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499057605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.499057605
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.1129016218
Short name T85
Test name
Test status
Simulation time 298110994 ps
CPU time 1.5 seconds
Started Jan 07 12:57:47 PM PST 24
Finished Jan 07 12:59:34 PM PST 24
Peak memory 199592 kb
Host smart-e3df2f20-35c6-420a-a26e-c7a729f79a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129016218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.1129016218
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.2290759671
Short name T307
Test name
Test status
Simulation time 71785490 ps
CPU time 0.72 seconds
Started Jan 07 12:57:33 PM PST 24
Finished Jan 07 12:59:05 PM PST 24
Peak memory 199168 kb
Host smart-c4e634d6-c0e3-4580-ace8-9aed16393883
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290759671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.2290759671
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.2540755624
Short name T429
Test name
Test status
Simulation time 2345630737 ps
CPU time 7.78 seconds
Started Jan 07 12:57:21 PM PST 24
Finished Jan 07 12:58:53 PM PST 24
Peak memory 221224 kb
Host smart-2b7fd83c-2a79-4378-a1dd-9cd7854f1030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540755624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.2540755624
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.3811725197
Short name T395
Test name
Test status
Simulation time 244406005 ps
CPU time 1.05 seconds
Started Jan 07 12:57:20 PM PST 24
Finished Jan 07 12:58:46 PM PST 24
Peak memory 216568 kb
Host smart-4bb4ee2f-cf23-49e0-8f24-b053f79d804b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811725197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.3811725197
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.2580252962
Short name T508
Test name
Test status
Simulation time 220108293 ps
CPU time 0.93 seconds
Started Jan 07 12:57:17 PM PST 24
Finished Jan 07 12:58:42 PM PST 24
Peak memory 199136 kb
Host smart-139f7953-9181-494a-918b-143da0fb9b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580252962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.2580252962
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.1475503924
Short name T522
Test name
Test status
Simulation time 1247794239 ps
CPU time 5.18 seconds
Started Jan 07 12:57:19 PM PST 24
Finished Jan 07 12:59:06 PM PST 24
Peak memory 199372 kb
Host smart-a906903f-c0f2-46bd-9e9e-d15815484060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475503924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.1475503924
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.608531713
Short name T297
Test name
Test status
Simulation time 187033222 ps
CPU time 1.15 seconds
Started Jan 07 12:57:25 PM PST 24
Finished Jan 07 12:58:50 PM PST 24
Peak memory 199264 kb
Host smart-571dd1e3-d364-486c-99a7-1f53bc283c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608531713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.608531713
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.765205965
Short name T357
Test name
Test status
Simulation time 289124757 ps
CPU time 1.56 seconds
Started Jan 07 12:57:48 PM PST 24
Finished Jan 07 12:59:09 PM PST 24
Peak memory 199548 kb
Host smart-3dbb945f-b716-499d-8563-670d12858233
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765205965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.765205965
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.4236966958
Short name T96
Test name
Test status
Simulation time 529747342 ps
CPU time 2.84 seconds
Started Jan 07 12:57:21 PM PST 24
Finished Jan 07 12:58:48 PM PST 24
Peak memory 199348 kb
Host smart-ccfb09e9-8916-4e1e-87f7-19f2fc0f8611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236966958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.4236966958
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.417371918
Short name T391
Test name
Test status
Simulation time 216816961 ps
CPU time 1.25 seconds
Started Jan 07 12:57:23 PM PST 24
Finished Jan 07 12:58:56 PM PST 24
Peak memory 199316 kb
Host smart-fd2821b5-f4d2-4768-889f-fb15c24c7f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417371918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.417371918
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.679692113
Short name T252
Test name
Test status
Simulation time 52192783 ps
CPU time 0.68 seconds
Started Jan 07 12:57:18 PM PST 24
Finished Jan 07 12:58:42 PM PST 24
Peak memory 199120 kb
Host smart-258077a4-4ac8-4cce-a400-5636dc86180d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679692113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.679692113
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.556068393
Short name T399
Test name
Test status
Simulation time 2381000436 ps
CPU time 8.34 seconds
Started Jan 07 12:57:23 PM PST 24
Finished Jan 07 12:59:09 PM PST 24
Peak memory 218168 kb
Host smart-1c34fa9b-bc78-42d7-910b-4e7ba22a2479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556068393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.556068393
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.1974318495
Short name T481
Test name
Test status
Simulation time 244489085 ps
CPU time 1.07 seconds
Started Jan 07 12:57:18 PM PST 24
Finished Jan 07 12:58:43 PM PST 24
Peak memory 216488 kb
Host smart-314f7c5c-5f94-4885-abc6-4156cb2e9ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974318495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.1974318495
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.2148959946
Short name T373
Test name
Test status
Simulation time 251992218 ps
CPU time 0.89 seconds
Started Jan 07 12:57:24 PM PST 24
Finished Jan 07 12:59:17 PM PST 24
Peak memory 199100 kb
Host smart-ed883a54-c3c3-4933-b817-d606ee5d7845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148959946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.2148959946
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.3009967116
Short name T206
Test name
Test status
Simulation time 1754579809 ps
CPU time 6.45 seconds
Started Jan 07 12:57:23 PM PST 24
Finished Jan 07 12:58:54 PM PST 24
Peak memory 199472 kb
Host smart-f55ab73c-4b90-4dc6-9cb1-c19a284cc603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009967116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.3009967116
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.3040890217
Short name T445
Test name
Test status
Simulation time 153243641 ps
CPU time 1.1 seconds
Started Jan 07 12:57:18 PM PST 24
Finished Jan 07 12:59:02 PM PST 24
Peak memory 199328 kb
Host smart-ac38a0a7-ad64-425e-a579-288cd78b279b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040890217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.3040890217
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.287795198
Short name T280
Test name
Test status
Simulation time 121664702 ps
CPU time 1.23 seconds
Started Jan 07 12:57:46 PM PST 24
Finished Jan 07 12:59:11 PM PST 24
Peak memory 199520 kb
Host smart-87274079-8615-4f34-b702-559e1e5f3f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287795198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.287795198
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.2751749943
Short name T344
Test name
Test status
Simulation time 3001642549 ps
CPU time 13.65 seconds
Started Jan 07 12:57:20 PM PST 24
Finished Jan 07 12:58:52 PM PST 24
Peak memory 199520 kb
Host smart-451b6cf7-299f-4b68-b54c-121c8b0f791c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751749943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.2751749943
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.3170158597
Short name T316
Test name
Test status
Simulation time 469538804 ps
CPU time 2.46 seconds
Started Jan 07 12:57:25 PM PST 24
Finished Jan 07 12:58:51 PM PST 24
Peak memory 199316 kb
Host smart-e40db5ee-6f6b-43f3-b3b4-6c17ded17327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170158597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.3170158597
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.3009480198
Short name T364
Test name
Test status
Simulation time 287066310 ps
CPU time 1.5 seconds
Started Jan 07 12:57:19 PM PST 24
Finished Jan 07 12:59:03 PM PST 24
Peak memory 199376 kb
Host smart-a73c6de9-9889-4d4b-80d2-62ac6ac32cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009480198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.3009480198
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.3589960556
Short name T517
Test name
Test status
Simulation time 60446374 ps
CPU time 0.71 seconds
Started Jan 07 12:57:26 PM PST 24
Finished Jan 07 12:59:13 PM PST 24
Peak memory 199196 kb
Host smart-e852b109-7aad-44b1-8054-151b20cf3889
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589960556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.3589960556
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.3022343062
Short name T50
Test name
Test status
Simulation time 1884133360 ps
CPU time 7.23 seconds
Started Jan 07 12:57:25 PM PST 24
Finished Jan 07 12:59:05 PM PST 24
Peak memory 216792 kb
Host smart-04e09576-f5c9-4554-981b-296016150b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022343062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.3022343062
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.1975819115
Short name T16
Test name
Test status
Simulation time 243832602 ps
CPU time 1.04 seconds
Started Jan 07 12:57:19 PM PST 24
Finished Jan 07 12:58:56 PM PST 24
Peak memory 216432 kb
Host smart-c52fdc19-efb5-4f4c-8e6e-9be137fadee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975819115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.1975819115
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.2924704766
Short name T284
Test name
Test status
Simulation time 186606370 ps
CPU time 0.81 seconds
Started Jan 07 12:57:17 PM PST 24
Finished Jan 07 12:58:36 PM PST 24
Peak memory 199076 kb
Host smart-f17ec21a-8fee-4273-bd96-a4bfbe8dee9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924704766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.2924704766
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.1789820179
Short name T289
Test name
Test status
Simulation time 733656890 ps
CPU time 3.56 seconds
Started Jan 07 12:57:18 PM PST 24
Finished Jan 07 12:58:49 PM PST 24
Peak memory 199504 kb
Host smart-045e3577-8501-4aea-b7fd-f7a12d69a165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789820179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.1789820179
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.1390740066
Short name T240
Test name
Test status
Simulation time 106788910 ps
CPU time 0.98 seconds
Started Jan 07 12:57:32 PM PST 24
Finished Jan 07 12:58:54 PM PST 24
Peak memory 199320 kb
Host smart-50bd8e0f-bfd6-4c57-a729-26a30cb729e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390740066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.1390740066
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.2580597356
Short name T268
Test name
Test status
Simulation time 121075507 ps
CPU time 1.16 seconds
Started Jan 07 12:57:23 PM PST 24
Finished Jan 07 12:59:00 PM PST 24
Peak memory 199532 kb
Host smart-507ae53f-d4bc-4f7d-a587-0d489074e0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580597356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.2580597356
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.1636015123
Short name T131
Test name
Test status
Simulation time 14291777304 ps
CPU time 53.79 seconds
Started Jan 07 12:57:18 PM PST 24
Finished Jan 07 12:59:35 PM PST 24
Peak memory 199624 kb
Host smart-93aacb58-c97b-425d-8dd4-c877a72350af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636015123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.1636015123
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.809534552
Short name T308
Test name
Test status
Simulation time 318791738 ps
CPU time 1.82 seconds
Started Jan 07 12:57:46 PM PST 24
Finished Jan 07 12:59:11 PM PST 24
Peak memory 199372 kb
Host smart-dcd0f0bc-88c6-4b4e-ae5b-de7744738dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809534552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.809534552
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.460866659
Short name T213
Test name
Test status
Simulation time 165281809 ps
CPU time 1.19 seconds
Started Jan 07 12:57:18 PM PST 24
Finished Jan 07 12:58:41 PM PST 24
Peak memory 199528 kb
Host smart-ba0523a6-4d3d-4801-a66c-42d26d9ef31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460866659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.460866659
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.2332919149
Short name T255
Test name
Test status
Simulation time 70914982 ps
CPU time 0.74 seconds
Started Jan 07 12:57:20 PM PST 24
Finished Jan 07 12:58:45 PM PST 24
Peak memory 199152 kb
Host smart-ffc2c924-0354-4b25-917c-9b0a6d9e90ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332919149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.2332919149
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.2898939800
Short name T494
Test name
Test status
Simulation time 1892755687 ps
CPU time 7.38 seconds
Started Jan 07 12:57:27 PM PST 24
Finished Jan 07 12:58:53 PM PST 24
Peak memory 217772 kb
Host smart-fba5ed90-cbd4-4f07-802c-d2cfbfab27d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898939800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.2898939800
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.2831819670
Short name T457
Test name
Test status
Simulation time 244279602 ps
CPU time 1.14 seconds
Started Jan 07 12:57:23 PM PST 24
Finished Jan 07 12:59:04 PM PST 24
Peak memory 216640 kb
Host smart-b262185b-325c-4408-ba72-68bd618544a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831819670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.2831819670
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.1703665827
Short name T424
Test name
Test status
Simulation time 205939803 ps
CPU time 0.89 seconds
Started Jan 07 12:57:23 PM PST 24
Finished Jan 07 12:59:01 PM PST 24
Peak memory 199208 kb
Host smart-6a074453-a059-4606-bc96-821663f49d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703665827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.1703665827
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.4158047242
Short name T309
Test name
Test status
Simulation time 1981420227 ps
CPU time 7.63 seconds
Started Jan 07 12:57:20 PM PST 24
Finished Jan 07 12:58:54 PM PST 24
Peak memory 199520 kb
Host smart-48747375-da9d-4dac-a0a9-911a4851bc65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158047242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.4158047242
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.1614433663
Short name T208
Test name
Test status
Simulation time 102998920 ps
CPU time 0.96 seconds
Started Jan 07 12:57:20 PM PST 24
Finished Jan 07 12:58:46 PM PST 24
Peak memory 199296 kb
Host smart-342dccc3-9972-4d98-a901-6f6f6a32c95e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614433663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.1614433663
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.72120929
Short name T378
Test name
Test status
Simulation time 189447164 ps
CPU time 1.33 seconds
Started Jan 07 12:57:26 PM PST 24
Finished Jan 07 12:58:47 PM PST 24
Peak memory 199480 kb
Host smart-cc649990-2abd-40a9-b658-418213be33f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72120929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.72120929
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.1586372828
Short name T367
Test name
Test status
Simulation time 1853710855 ps
CPU time 7.61 seconds
Started Jan 07 12:57:21 PM PST 24
Finished Jan 07 12:58:52 PM PST 24
Peak memory 199488 kb
Host smart-a26ad426-79f8-400b-9598-c7af024e56d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586372828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.1586372828
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.1288713292
Short name T258
Test name
Test status
Simulation time 134438757 ps
CPU time 1.54 seconds
Started Jan 07 12:57:21 PM PST 24
Finished Jan 07 12:58:40 PM PST 24
Peak memory 199324 kb
Host smart-85dee348-deac-421d-bc7a-3b4abddddf8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288713292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.1288713292
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.3660480377
Short name T239
Test name
Test status
Simulation time 105617387 ps
CPU time 0.86 seconds
Started Jan 07 12:57:18 PM PST 24
Finished Jan 07 12:58:41 PM PST 24
Peak memory 199420 kb
Host smart-399570e1-98ac-4a85-a010-5a17e55c32a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660480377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.3660480377
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.1468639674
Short name T234
Test name
Test status
Simulation time 64904553 ps
CPU time 0.73 seconds
Started Jan 07 12:57:26 PM PST 24
Finished Jan 07 12:59:01 PM PST 24
Peak memory 199228 kb
Host smart-7523bafe-0404-4bfe-b615-ba950de8dffe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468639674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.1468639674
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.3259275419
Short name T128
Test name
Test status
Simulation time 2360504789 ps
CPU time 7.82 seconds
Started Jan 07 12:57:17 PM PST 24
Finished Jan 07 12:58:43 PM PST 24
Peak memory 217192 kb
Host smart-19085eca-b570-41fd-9ca8-51d1d41f3570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259275419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.3259275419
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.3752366961
Short name T140
Test name
Test status
Simulation time 244123432 ps
CPU time 1.01 seconds
Started Jan 07 12:57:24 PM PST 24
Finished Jan 07 12:58:56 PM PST 24
Peak memory 216632 kb
Host smart-0e39e9ad-05eb-403b-a60b-e6971e468cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752366961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.3752366961
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.3154160840
Short name T265
Test name
Test status
Simulation time 169989618 ps
CPU time 0.85 seconds
Started Jan 07 12:57:23 PM PST 24
Finished Jan 07 12:58:55 PM PST 24
Peak memory 199172 kb
Host smart-dbf8f3fc-8ea4-430d-8326-0c90b6f0e424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154160840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.3154160840
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.3905751639
Short name T453
Test name
Test status
Simulation time 1569507495 ps
CPU time 6.35 seconds
Started Jan 07 12:57:43 PM PST 24
Finished Jan 07 12:59:21 PM PST 24
Peak memory 199516 kb
Host smart-633e0497-30f5-4137-8ebd-85e6408dda4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905751639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.3905751639
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.3977665341
Short name T276
Test name
Test status
Simulation time 109535396 ps
CPU time 0.94 seconds
Started Jan 07 12:57:20 PM PST 24
Finished Jan 07 12:58:46 PM PST 24
Peak memory 199308 kb
Host smart-adddca65-bfe7-4f3a-9e0e-59f425617871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977665341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.3977665341
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.273684209
Short name T349
Test name
Test status
Simulation time 117402143 ps
CPU time 1.13 seconds
Started Jan 07 12:57:20 PM PST 24
Finished Jan 07 12:58:45 PM PST 24
Peak memory 199484 kb
Host smart-4fb38706-e1d6-4ebb-b4d8-57dfe7782d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273684209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.273684209
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.2880967191
Short name T450
Test name
Test status
Simulation time 9277434437 ps
CPU time 33.22 seconds
Started Jan 07 12:57:42 PM PST 24
Finished Jan 07 12:59:47 PM PST 24
Peak memory 199588 kb
Host smart-be5d7fbd-f084-4467-9f8d-9ef1a8ba4a46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880967191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.2880967191
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.420580497
Short name T8
Test name
Test status
Simulation time 242374150 ps
CPU time 1.66 seconds
Started Jan 07 12:57:58 PM PST 24
Finished Jan 07 12:59:34 PM PST 24
Peak memory 199380 kb
Host smart-c3e82f9a-8272-442d-a96a-94d8b4dc5664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420580497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.420580497
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.225027997
Short name T530
Test name
Test status
Simulation time 156326885 ps
CPU time 1.16 seconds
Started Jan 07 12:57:42 PM PST 24
Finished Jan 07 12:59:16 PM PST 24
Peak memory 199348 kb
Host smart-7c9b7383-7cfe-4b72-873c-7ab782a020b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225027997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.225027997
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.383852937
Short name T238
Test name
Test status
Simulation time 93070863 ps
CPU time 0.76 seconds
Started Jan 07 12:58:06 PM PST 24
Finished Jan 07 12:59:34 PM PST 24
Peak memory 199252 kb
Host smart-207ae4e3-ed86-4a21-8cfd-bffb9d82c0b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383852937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.383852937
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.2372395160
Short name T525
Test name
Test status
Simulation time 245368559 ps
CPU time 1.01 seconds
Started Jan 07 12:58:06 PM PST 24
Finished Jan 07 12:59:37 PM PST 24
Peak memory 216576 kb
Host smart-6b402f96-cece-4b62-8bcc-a7c420e3dcb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372395160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.2372395160
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.1222580349
Short name T405
Test name
Test status
Simulation time 162363798 ps
CPU time 0.78 seconds
Started Jan 07 12:57:39 PM PST 24
Finished Jan 07 12:59:16 PM PST 24
Peak memory 199128 kb
Host smart-56f7aee5-caa7-4f64-9aef-482c3115c603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222580349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.1222580349
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.923014647
Short name T224
Test name
Test status
Simulation time 1150369740 ps
CPU time 5.45 seconds
Started Jan 07 12:58:07 PM PST 24
Finished Jan 07 12:59:40 PM PST 24
Peak memory 199424 kb
Host smart-af7c8e12-a7d9-4d2a-8f41-861ee2242db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923014647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.923014647
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.838818191
Short name T341
Test name
Test status
Simulation time 168120338 ps
CPU time 1.11 seconds
Started Jan 07 12:57:40 PM PST 24
Finished Jan 07 12:59:34 PM PST 24
Peak memory 199320 kb
Host smart-235cf214-9ba0-4d8a-a423-bed5836a7b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838818191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.838818191
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.863056399
Short name T526
Test name
Test status
Simulation time 110817639 ps
CPU time 1.1 seconds
Started Jan 07 12:57:46 PM PST 24
Finished Jan 07 12:59:10 PM PST 24
Peak memory 199548 kb
Host smart-7a23d57d-f50a-426c-958e-a79dd5edf0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863056399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.863056399
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.804035316
Short name T440
Test name
Test status
Simulation time 3831071235 ps
CPU time 14.03 seconds
Started Jan 07 12:57:38 PM PST 24
Finished Jan 07 12:59:21 PM PST 24
Peak memory 199544 kb
Host smart-28d74b34-fc90-4263-b3ed-1800ec61070b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804035316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.804035316
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.2230945358
Short name T345
Test name
Test status
Simulation time 334494823 ps
CPU time 2.27 seconds
Started Jan 07 12:58:07 PM PST 24
Finished Jan 07 12:59:47 PM PST 24
Peak memory 199360 kb
Host smart-e639b8a0-231f-45ce-b4f2-22c9cd4ac5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230945358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.2230945358
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.549773414
Short name T315
Test name
Test status
Simulation time 133903682 ps
CPU time 1.13 seconds
Started Jan 07 12:57:39 PM PST 24
Finished Jan 07 12:58:58 PM PST 24
Peak memory 199312 kb
Host smart-de032648-9ae2-4ff7-b2ba-581d600aaee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549773414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.549773414
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.276614943
Short name T547
Test name
Test status
Simulation time 72189863 ps
CPU time 0.74 seconds
Started Jan 07 12:57:43 PM PST 24
Finished Jan 07 12:59:14 PM PST 24
Peak memory 199212 kb
Host smart-f4d3962e-2edc-449f-a3f0-1ac95408abb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276614943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.276614943
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.789312700
Short name T408
Test name
Test status
Simulation time 245625993 ps
CPU time 1.07 seconds
Started Jan 07 12:57:42 PM PST 24
Finished Jan 07 12:59:14 PM PST 24
Peak memory 216424 kb
Host smart-490cec55-310b-4517-b1ca-00f24645bc4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789312700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.789312700
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.450259599
Short name T313
Test name
Test status
Simulation time 193361084 ps
CPU time 0.84 seconds
Started Jan 07 12:58:08 PM PST 24
Finished Jan 07 12:59:37 PM PST 24
Peak memory 199200 kb
Host smart-1753ec58-345b-4c52-922c-7dc0eb7d11b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450259599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.450259599
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.4081598433
Short name T372
Test name
Test status
Simulation time 1271091129 ps
CPU time 5.18 seconds
Started Jan 07 12:58:08 PM PST 24
Finished Jan 07 12:59:46 PM PST 24
Peak memory 199504 kb
Host smart-b03cf191-424f-4adc-9539-af83eb2543d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081598433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.4081598433
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.1214201029
Short name T404
Test name
Test status
Simulation time 113158724 ps
CPU time 0.98 seconds
Started Jan 07 12:58:09 PM PST 24
Finished Jan 07 12:59:39 PM PST 24
Peak memory 199328 kb
Host smart-c5b54c3a-5f54-4220-be47-a658390a60ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214201029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.1214201029
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.2105607539
Short name T477
Test name
Test status
Simulation time 126867384 ps
CPU time 1.16 seconds
Started Jan 07 12:58:09 PM PST 24
Finished Jan 07 12:59:39 PM PST 24
Peak memory 199516 kb
Host smart-37f054e4-ecd6-4298-aecb-1f98bea2e14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105607539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.2105607539
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.1193272337
Short name T264
Test name
Test status
Simulation time 1644715803 ps
CPU time 7.36 seconds
Started Jan 07 12:57:39 PM PST 24
Finished Jan 07 12:59:13 PM PST 24
Peak memory 199520 kb
Host smart-8e554444-40b9-48d0-866a-1670f3a8ae4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193272337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.1193272337
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.3118574934
Short name T376
Test name
Test status
Simulation time 328452945 ps
CPU time 2.15 seconds
Started Jan 07 12:58:07 PM PST 24
Finished Jan 07 12:59:33 PM PST 24
Peak memory 199272 kb
Host smart-4e7da6c7-0083-4cb4-9d44-7f5c10672319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118574934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.3118574934
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.4250358009
Short name T393
Test name
Test status
Simulation time 184239469 ps
CPU time 1.12 seconds
Started Jan 07 12:57:39 PM PST 24
Finished Jan 07 12:59:17 PM PST 24
Peak memory 199312 kb
Host smart-291819aa-312c-42a4-8cfa-69a0ebcc7798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250358009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.4250358009
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.1534418116
Short name T334
Test name
Test status
Simulation time 72079697 ps
CPU time 0.71 seconds
Started Jan 07 12:57:46 PM PST 24
Finished Jan 07 12:59:06 PM PST 24
Peak memory 199228 kb
Host smart-468b1644-c969-4bd3-8769-616ff5b4607a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534418116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.1534418116
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.1284896604
Short name T463
Test name
Test status
Simulation time 1887456415 ps
CPU time 7.01 seconds
Started Jan 07 12:57:39 PM PST 24
Finished Jan 07 12:59:23 PM PST 24
Peak memory 221308 kb
Host smart-6a6a6dc7-e7c6-4f1b-8c5b-8935100ea4e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284896604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.1284896604
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.954197980
Short name T470
Test name
Test status
Simulation time 243398093 ps
CPU time 1.09 seconds
Started Jan 07 12:57:39 PM PST 24
Finished Jan 07 12:58:58 PM PST 24
Peak memory 216544 kb
Host smart-ea6da573-55b8-4752-b1f2-340d5e2af4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954197980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.954197980
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.1822161758
Short name T20
Test name
Test status
Simulation time 128789759 ps
CPU time 0.8 seconds
Started Jan 07 12:57:39 PM PST 24
Finished Jan 07 12:59:22 PM PST 24
Peak memory 199172 kb
Host smart-8f1ff357-e0d1-4370-8e7a-7e5dc3c8fe4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822161758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.1822161758
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.1294558492
Short name T362
Test name
Test status
Simulation time 1106283150 ps
CPU time 5.02 seconds
Started Jan 07 12:57:39 PM PST 24
Finished Jan 07 12:59:10 PM PST 24
Peak memory 199572 kb
Host smart-122f5465-d61a-4c42-91dc-9eb9d1c62bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294558492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.1294558492
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.1616531692
Short name T136
Test name
Test status
Simulation time 102743579 ps
CPU time 0.96 seconds
Started Jan 07 12:57:39 PM PST 24
Finished Jan 07 12:59:09 PM PST 24
Peak memory 199404 kb
Host smart-299a3604-2665-4820-b9ec-4a5ff2c6f522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616531692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.1616531692
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.3046605204
Short name T266
Test name
Test status
Simulation time 242284083 ps
CPU time 1.5 seconds
Started Jan 07 12:57:39 PM PST 24
Finished Jan 07 12:59:05 PM PST 24
Peak memory 199428 kb
Host smart-9ca08f79-772c-4f88-a4f8-12c5bc801c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046605204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.3046605204
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.1944664785
Short name T215
Test name
Test status
Simulation time 4190144873 ps
CPU time 15.54 seconds
Started Jan 07 12:57:39 PM PST 24
Finished Jan 07 12:59:13 PM PST 24
Peak memory 199532 kb
Host smart-9796d7d9-7f4d-4739-a0da-b73a7efe7be4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944664785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.1944664785
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.1537386835
Short name T343
Test name
Test status
Simulation time 143749968 ps
CPU time 1.76 seconds
Started Jan 07 12:58:09 PM PST 24
Finished Jan 07 12:59:40 PM PST 24
Peak memory 199304 kb
Host smart-7e4cb2fa-a039-4127-876f-a28f7a575ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537386835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.1537386835
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.2894533818
Short name T361
Test name
Test status
Simulation time 285203153 ps
CPU time 1.42 seconds
Started Jan 07 12:57:39 PM PST 24
Finished Jan 07 12:59:10 PM PST 24
Peak memory 199344 kb
Host smart-807646ed-2d6b-404f-8a96-a8f816f805d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894533818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.2894533818
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.2709211993
Short name T294
Test name
Test status
Simulation time 81622526 ps
CPU time 0.79 seconds
Started Jan 07 12:56:48 PM PST 24
Finished Jan 07 12:58:30 PM PST 24
Peak memory 199124 kb
Host smart-fb5ef626-56a1-4df4-97ea-006f4998c8e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709211993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.2709211993
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.2350529332
Short name T36
Test name
Test status
Simulation time 2171092011 ps
CPU time 7.22 seconds
Started Jan 07 12:56:35 PM PST 24
Finished Jan 07 12:58:07 PM PST 24
Peak memory 217300 kb
Host smart-90fa52f6-872f-4fda-90fb-4ee50d4b6805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350529332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.2350529332
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.2598799120
Short name T359
Test name
Test status
Simulation time 244202366 ps
CPU time 0.98 seconds
Started Jan 07 12:56:21 PM PST 24
Finished Jan 07 12:58:00 PM PST 24
Peak memory 216660 kb
Host smart-1aaff4d4-80df-4149-a5a9-280d95a82fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598799120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.2598799120
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.3236757749
Short name T534
Test name
Test status
Simulation time 89147519 ps
CPU time 0.71 seconds
Started Jan 07 12:56:09 PM PST 24
Finished Jan 07 12:58:00 PM PST 24
Peak memory 199140 kb
Host smart-bb0bc3bf-16f2-4f1c-a8e4-3fd1479f23c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236757749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.3236757749
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.2695702413
Short name T14
Test name
Test status
Simulation time 1170504813 ps
CPU time 5.21 seconds
Started Jan 07 12:56:07 PM PST 24
Finished Jan 07 12:57:58 PM PST 24
Peak memory 199468 kb
Host smart-ec046e7f-cf46-49d4-9bb3-d4b0e629470a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695702413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.2695702413
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.3235539795
Short name T81
Test name
Test status
Simulation time 16524491516 ps
CPU time 28.45 seconds
Started Jan 07 12:56:01 PM PST 24
Finished Jan 07 12:58:12 PM PST 24
Peak memory 217524 kb
Host smart-1753e0c9-856e-4756-9cd9-b63ce5424ff7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235539795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.3235539795
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.1625566674
Short name T267
Test name
Test status
Simulation time 239615468 ps
CPU time 1.41 seconds
Started Jan 07 12:56:26 PM PST 24
Finished Jan 07 12:58:27 PM PST 24
Peak memory 199540 kb
Host smart-3f2af6a9-4ae1-4608-9b0b-2880505f9bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625566674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.1625566674
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.3664194689
Short name T472
Test name
Test status
Simulation time 3491384132 ps
CPU time 14.29 seconds
Started Jan 07 12:56:42 PM PST 24
Finished Jan 07 12:58:42 PM PST 24
Peak memory 199556 kb
Host smart-c6111596-59d0-45da-859e-a109fc98dc38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664194689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.3664194689
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.2726664008
Short name T89
Test name
Test status
Simulation time 119735812 ps
CPU time 1.4 seconds
Started Jan 07 12:56:03 PM PST 24
Finished Jan 07 12:58:20 PM PST 24
Peak memory 199304 kb
Host smart-64fcc1ec-1039-4cc6-a3f5-3cabc945820e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726664008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.2726664008
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.1129626047
Short name T331
Test name
Test status
Simulation time 71446020 ps
CPU time 0.77 seconds
Started Jan 07 12:57:39 PM PST 24
Finished Jan 07 12:59:27 PM PST 24
Peak memory 199140 kb
Host smart-baf4c244-8b04-41bd-a58a-0c841fe2435c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129626047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.1129626047
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.1815531251
Short name T62
Test name
Test status
Simulation time 1231990918 ps
CPU time 6.13 seconds
Started Jan 07 12:58:07 PM PST 24
Finished Jan 07 12:59:40 PM PST 24
Peak memory 216828 kb
Host smart-3c453049-3cd0-4fec-91cc-c0b9a837362e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815531251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.1815531251
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.2293961711
Short name T414
Test name
Test status
Simulation time 244122561 ps
CPU time 1.02 seconds
Started Jan 07 12:57:38 PM PST 24
Finished Jan 07 12:59:17 PM PST 24
Peak memory 216512 kb
Host smart-cd10908f-e104-4f09-960a-e9aafc1b9469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293961711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.2293961711
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.2351273560
Short name T325
Test name
Test status
Simulation time 192288500 ps
CPU time 0.86 seconds
Started Jan 07 12:57:39 PM PST 24
Finished Jan 07 12:59:16 PM PST 24
Peak memory 199152 kb
Host smart-f88ffabf-1de6-4083-8fef-7e4063626f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351273560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.2351273560
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.1768301582
Short name T29
Test name
Test status
Simulation time 139902007 ps
CPU time 1.08 seconds
Started Jan 07 12:57:39 PM PST 24
Finished Jan 07 12:59:06 PM PST 24
Peak memory 199408 kb
Host smart-5cb3f716-7712-4721-8ed1-9957d65282a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768301582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.1768301582
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.3689239977
Short name T495
Test name
Test status
Simulation time 189244227 ps
CPU time 1.41 seconds
Started Jan 07 12:57:39 PM PST 24
Finished Jan 07 12:58:58 PM PST 24
Peak memory 199372 kb
Host smart-64c3db67-94f6-4a46-beee-d2fb1837249b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689239977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.3689239977
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.235279457
Short name T227
Test name
Test status
Simulation time 359872083 ps
CPU time 2.06 seconds
Started Jan 07 12:57:39 PM PST 24
Finished Jan 07 12:58:59 PM PST 24
Peak memory 199308 kb
Host smart-bc401513-436e-40f1-b6a9-aeab99b7a0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235279457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.235279457
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.3795507717
Short name T460
Test name
Test status
Simulation time 112162405 ps
CPU time 0.98 seconds
Started Jan 07 12:57:39 PM PST 24
Finished Jan 07 12:58:58 PM PST 24
Peak memory 199384 kb
Host smart-023b4005-2e3f-4084-a4bc-933d0179f23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795507717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.3795507717
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.2022713806
Short name T485
Test name
Test status
Simulation time 75035619 ps
CPU time 0.73 seconds
Started Jan 07 12:57:40 PM PST 24
Finished Jan 07 12:59:11 PM PST 24
Peak memory 199164 kb
Host smart-982ed05f-d562-4cf2-9c0c-a29eb3fcc590
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022713806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.2022713806
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.3750841531
Short name T39
Test name
Test status
Simulation time 1229827723 ps
CPU time 5.8 seconds
Started Jan 07 12:58:08 PM PST 24
Finished Jan 07 12:59:47 PM PST 24
Peak memory 221384 kb
Host smart-891e4b63-3d4e-40b9-aef5-90b94eb39add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750841531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.3750841531
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.893584806
Short name T416
Test name
Test status
Simulation time 244993262 ps
CPU time 1.04 seconds
Started Jan 07 12:57:43 PM PST 24
Finished Jan 07 12:59:04 PM PST 24
Peak memory 216484 kb
Host smart-d6c0d42b-8e52-4ebb-ad96-1e25cda0bd65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893584806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.893584806
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.2752020812
Short name T17
Test name
Test status
Simulation time 94826768 ps
CPU time 0.76 seconds
Started Jan 07 12:57:39 PM PST 24
Finished Jan 07 12:58:58 PM PST 24
Peak memory 199180 kb
Host smart-e8cd4033-8987-4430-a30e-c3b58fe652cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752020812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.2752020812
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.1919476208
Short name T433
Test name
Test status
Simulation time 749450289 ps
CPU time 3.49 seconds
Started Jan 07 12:57:38 PM PST 24
Finished Jan 07 12:59:12 PM PST 24
Peak memory 199484 kb
Host smart-f1bc04f7-a07d-4b3f-b09e-6e11259ba2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919476208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.1919476208
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.4221577811
Short name T318
Test name
Test status
Simulation time 109698072 ps
CPU time 0.98 seconds
Started Jan 07 12:57:38 PM PST 24
Finished Jan 07 12:59:08 PM PST 24
Peak memory 199400 kb
Host smart-3a182122-8172-4813-a0bb-f8c68aed6ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221577811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.4221577811
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.1465948643
Short name T230
Test name
Test status
Simulation time 3232967621 ps
CPU time 14.08 seconds
Started Jan 07 12:57:40 PM PST 24
Finished Jan 07 12:59:20 PM PST 24
Peak memory 199600 kb
Host smart-bc69e923-944c-44be-b955-f2e39db732d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465948643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.1465948643
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.1121363277
Short name T332
Test name
Test status
Simulation time 260824181 ps
CPU time 1.7 seconds
Started Jan 07 12:57:39 PM PST 24
Finished Jan 07 12:59:05 PM PST 24
Peak memory 199344 kb
Host smart-df5ddd78-77e6-4341-adf2-22eafecdebf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121363277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.1121363277
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.1563362004
Short name T137
Test name
Test status
Simulation time 82189121 ps
CPU time 0.8 seconds
Started Jan 07 12:57:42 PM PST 24
Finished Jan 07 12:59:14 PM PST 24
Peak memory 199232 kb
Host smart-1e81cec5-2de1-4590-9e74-37566c8942c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563362004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.1563362004
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.2583127309
Short name T13
Test name
Test status
Simulation time 1222793285 ps
CPU time 5.5 seconds
Started Jan 07 12:57:47 PM PST 24
Finished Jan 07 12:59:12 PM PST 24
Peak memory 216152 kb
Host smart-d66ea50d-01fe-429b-bb5e-ae47e2c8a9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583127309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.2583127309
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.4294956435
Short name T531
Test name
Test status
Simulation time 243864155 ps
CPU time 1.11 seconds
Started Jan 07 12:58:13 PM PST 24
Finished Jan 07 12:59:38 PM PST 24
Peak memory 216464 kb
Host smart-7e3458a6-a672-4d53-8db0-45e0fd6c8ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294956435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.4294956435
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_reset.1195240610
Short name T43
Test name
Test status
Simulation time 1486510242 ps
CPU time 5.59 seconds
Started Jan 07 12:58:08 PM PST 24
Finished Jan 07 12:59:40 PM PST 24
Peak memory 199472 kb
Host smart-c54a5b2b-7ac2-44bc-8075-d5cb7aae99e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195240610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.1195240610
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.2940862225
Short name T417
Test name
Test status
Simulation time 101576253 ps
CPU time 0.98 seconds
Started Jan 07 12:57:41 PM PST 24
Finished Jan 07 12:59:20 PM PST 24
Peak memory 199380 kb
Host smart-fb2cb060-437d-4796-a2dc-5d9ad12c5e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940862225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.2940862225
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.573095893
Short name T305
Test name
Test status
Simulation time 200117055 ps
CPU time 1.33 seconds
Started Jan 07 12:57:42 PM PST 24
Finished Jan 07 12:59:16 PM PST 24
Peak memory 199556 kb
Host smart-e9bfde15-975a-47f0-bfae-2a187adfa50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573095893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.573095893
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.4279692006
Short name T94
Test name
Test status
Simulation time 6576658644 ps
CPU time 21.6 seconds
Started Jan 07 12:57:47 PM PST 24
Finished Jan 07 12:59:29 PM PST 24
Peak memory 199520 kb
Host smart-f9124bc9-8691-422e-afd0-010d5a5945a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279692006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.4279692006
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.3496697985
Short name T352
Test name
Test status
Simulation time 329041660 ps
CPU time 1.93 seconds
Started Jan 07 12:58:11 PM PST 24
Finished Jan 07 12:59:45 PM PST 24
Peak memory 199364 kb
Host smart-9eed9a7d-3af6-4dde-8402-4cefb0939a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496697985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.3496697985
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.1749117809
Short name T435
Test name
Test status
Simulation time 91038255 ps
CPU time 0.79 seconds
Started Jan 07 12:58:11 PM PST 24
Finished Jan 07 12:59:40 PM PST 24
Peak memory 199376 kb
Host smart-a1e8ce95-e8b3-4227-bc09-551e4f5a5cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749117809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.1749117809
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.1457807308
Short name T518
Test name
Test status
Simulation time 61563343 ps
CPU time 0.67 seconds
Started Jan 07 12:57:41 PM PST 24
Finished Jan 07 12:59:22 PM PST 24
Peak memory 199180 kb
Host smart-3fab1291-66c1-413b-9d18-f082132f815f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457807308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.1457807308
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.2632769479
Short name T35
Test name
Test status
Simulation time 2175705409 ps
CPU time 7.69 seconds
Started Jan 07 12:57:43 PM PST 24
Finished Jan 07 12:59:13 PM PST 24
Peak memory 216972 kb
Host smart-a80aa48c-e2b4-4387-9153-c2e9e380632e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632769479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.2632769479
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.3875426606
Short name T12
Test name
Test status
Simulation time 246281466 ps
CPU time 1.04 seconds
Started Jan 07 12:57:57 PM PST 24
Finished Jan 07 12:59:25 PM PST 24
Peak memory 216464 kb
Host smart-b5a1411f-8712-4e13-a522-661ffdbc1fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875426606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.3875426606
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.170282224
Short name T428
Test name
Test status
Simulation time 101863089 ps
CPU time 0.72 seconds
Started Jan 07 12:57:45 PM PST 24
Finished Jan 07 12:59:18 PM PST 24
Peak memory 199112 kb
Host smart-bf678457-3c02-4b37-b9f3-eb3e8120ec1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170282224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.170282224
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.1913679349
Short name T11
Test name
Test status
Simulation time 925751742 ps
CPU time 4.1 seconds
Started Jan 07 12:58:16 PM PST 24
Finished Jan 07 12:59:50 PM PST 24
Peak memory 199548 kb
Host smart-9121ff2f-3a79-4df6-9860-bcb7f6a79c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913679349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.1913679349
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.962002331
Short name T484
Test name
Test status
Simulation time 106330991 ps
CPU time 0.98 seconds
Started Jan 07 12:57:43 PM PST 24
Finished Jan 07 12:59:15 PM PST 24
Peak memory 199376 kb
Host smart-69fa1071-c640-436d-beb0-82be9d13ab22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962002331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.962002331
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.2805430381
Short name T246
Test name
Test status
Simulation time 127245190 ps
CPU time 1.2 seconds
Started Jan 07 12:57:46 PM PST 24
Finished Jan 07 12:59:06 PM PST 24
Peak memory 199552 kb
Host smart-da016446-3823-415d-bb94-24ab935eac80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805430381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.2805430381
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.2486648016
Short name T478
Test name
Test status
Simulation time 116829837 ps
CPU time 1.07 seconds
Started Jan 07 12:58:11 PM PST 24
Finished Jan 07 12:59:44 PM PST 24
Peak memory 199364 kb
Host smart-8c568bc5-909b-434a-98c8-cbed358e52e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486648016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.2486648016
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.1147173992
Short name T385
Test name
Test status
Simulation time 72326775 ps
CPU time 0.72 seconds
Started Jan 07 12:57:43 PM PST 24
Finished Jan 07 12:59:02 PM PST 24
Peak memory 199176 kb
Host smart-a909c0d9-61ce-4738-aaf3-ee30016b69c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147173992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.1147173992
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.1011566409
Short name T553
Test name
Test status
Simulation time 1228786956 ps
CPU time 5.32 seconds
Started Jan 07 12:57:42 PM PST 24
Finished Jan 07 12:59:07 PM PST 24
Peak memory 221452 kb
Host smart-63916bd8-2d9c-47de-a516-273f136ec22b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011566409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.1011566409
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.3972441318
Short name T497
Test name
Test status
Simulation time 245691507 ps
CPU time 1.03 seconds
Started Jan 07 12:58:11 PM PST 24
Finished Jan 07 12:59:49 PM PST 24
Peak memory 216548 kb
Host smart-20729102-bd49-41e6-bf62-b7ed78a9561f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972441318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.3972441318
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.2251832810
Short name T296
Test name
Test status
Simulation time 85532808 ps
CPU time 0.72 seconds
Started Jan 07 12:57:51 PM PST 24
Finished Jan 07 12:59:12 PM PST 24
Peak memory 199164 kb
Host smart-318adf3d-842a-4b14-ae4a-b8b21039c3f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251832810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.2251832810
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.2810659274
Short name T212
Test name
Test status
Simulation time 835915235 ps
CPU time 4.07 seconds
Started Jan 07 12:58:00 PM PST 24
Finished Jan 07 12:59:28 PM PST 24
Peak memory 199576 kb
Host smart-c10ffc88-a829-4559-82e1-5609a8b2023b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810659274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.2810659274
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.2499429948
Short name T451
Test name
Test status
Simulation time 155149782 ps
CPU time 1.16 seconds
Started Jan 07 12:57:51 PM PST 24
Finished Jan 07 12:59:17 PM PST 24
Peak memory 199392 kb
Host smart-fc8a9272-a659-44f4-a9bf-22d436e8dee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499429948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.2499429948
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.3677344636
Short name T389
Test name
Test status
Simulation time 129273735 ps
CPU time 1.13 seconds
Started Jan 07 12:57:46 PM PST 24
Finished Jan 07 12:59:10 PM PST 24
Peak memory 199492 kb
Host smart-57b5bf96-415d-4ba5-b39b-8bf5b391219a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677344636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.3677344636
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.337893950
Short name T27
Test name
Test status
Simulation time 1681834917 ps
CPU time 6.26 seconds
Started Jan 07 12:58:12 PM PST 24
Finished Jan 07 12:59:43 PM PST 24
Peak memory 199492 kb
Host smart-03db24e9-6ebb-4a48-93f8-5d7c4a72aab2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337893950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.337893950
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.4088876163
Short name T279
Test name
Test status
Simulation time 117985482 ps
CPU time 1.39 seconds
Started Jan 07 12:57:43 PM PST 24
Finished Jan 07 12:59:06 PM PST 24
Peak memory 199448 kb
Host smart-d5b97277-1b4f-49e5-8138-743aa872bd76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088876163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.4088876163
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.1586159964
Short name T486
Test name
Test status
Simulation time 70771437 ps
CPU time 0.76 seconds
Started Jan 07 12:58:11 PM PST 24
Finished Jan 07 12:59:48 PM PST 24
Peak memory 199340 kb
Host smart-dd20da04-f017-4658-afe9-a90a55942021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586159964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.1586159964
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.4010171411
Short name T403
Test name
Test status
Simulation time 244282696 ps
CPU time 1.03 seconds
Started Jan 07 12:57:39 PM PST 24
Finished Jan 07 12:58:58 PM PST 24
Peak memory 216560 kb
Host smart-08dd9e6c-3a6b-4de7-8205-42d93294d5ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010171411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.4010171411
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.3951351957
Short name T22
Test name
Test status
Simulation time 175746940 ps
CPU time 0.79 seconds
Started Jan 07 12:57:39 PM PST 24
Finished Jan 07 12:58:58 PM PST 24
Peak memory 199040 kb
Host smart-056ec5b9-c5bc-4151-a5d1-3365edb5ac25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951351957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.3951351957
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.1653222177
Short name T511
Test name
Test status
Simulation time 1911787398 ps
CPU time 6.71 seconds
Started Jan 07 12:57:50 PM PST 24
Finished Jan 07 12:59:21 PM PST 24
Peak memory 199404 kb
Host smart-63827d81-ee6d-483c-bedc-cbe2196d2b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653222177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.1653222177
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.3960797647
Short name T377
Test name
Test status
Simulation time 110327770 ps
CPU time 0.95 seconds
Started Jan 07 12:58:11 PM PST 24
Finished Jan 07 12:59:49 PM PST 24
Peak memory 199308 kb
Host smart-c40f22f4-25e5-4f08-b023-2895a7999573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960797647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.3960797647
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.2020672222
Short name T438
Test name
Test status
Simulation time 123488846 ps
CPU time 1.16 seconds
Started Jan 07 12:57:45 PM PST 24
Finished Jan 07 12:59:06 PM PST 24
Peak memory 199460 kb
Host smart-944ea8c6-be26-40f4-9294-3cb0e1db2e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020672222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.2020672222
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.3913218466
Short name T358
Test name
Test status
Simulation time 2348668927 ps
CPU time 9.9 seconds
Started Jan 07 12:58:11 PM PST 24
Finished Jan 07 12:59:53 PM PST 24
Peak memory 199656 kb
Host smart-16b07ed1-b50c-4757-8c83-d5fbc750c505
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913218466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.3913218466
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.1685733626
Short name T370
Test name
Test status
Simulation time 297573295 ps
CPU time 1.91 seconds
Started Jan 07 12:57:39 PM PST 24
Finished Jan 07 12:59:14 PM PST 24
Peak memory 199164 kb
Host smart-dff39c1f-1718-4152-acf4-eddf8e446646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685733626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.1685733626
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.3665734799
Short name T322
Test name
Test status
Simulation time 152283428 ps
CPU time 1.15 seconds
Started Jan 07 12:57:39 PM PST 24
Finished Jan 07 12:59:05 PM PST 24
Peak memory 199276 kb
Host smart-7cb1de40-6164-4113-8d78-4cb8c2364b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665734799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.3665734799
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.2306789475
Short name T82
Test name
Test status
Simulation time 64541097 ps
CPU time 0.69 seconds
Started Jan 07 12:57:51 PM PST 24
Finished Jan 07 12:59:11 PM PST 24
Peak memory 199152 kb
Host smart-bff3de17-0260-4ead-b394-30a044d81993
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306789475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.2306789475
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.123161275
Short name T134
Test name
Test status
Simulation time 244538822 ps
CPU time 1 seconds
Started Jan 07 12:58:13 PM PST 24
Finished Jan 07 12:59:38 PM PST 24
Peak memory 216432 kb
Host smart-bbfe9a2c-6c46-4839-9716-52e31129474e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123161275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.123161275
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.2067738735
Short name T473
Test name
Test status
Simulation time 199731574 ps
CPU time 0.84 seconds
Started Jan 07 12:58:11 PM PST 24
Finished Jan 07 12:59:48 PM PST 24
Peak memory 199112 kb
Host smart-a03fa4f6-cfff-4aa5-b0ec-7941bbb2937b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067738735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.2067738735
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.4109809144
Short name T58
Test name
Test status
Simulation time 1496248672 ps
CPU time 5.62 seconds
Started Jan 07 12:58:12 PM PST 24
Finished Jan 07 12:59:42 PM PST 24
Peak memory 199500 kb
Host smart-115d2368-6435-4312-9ac4-77711a25533b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109809144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.4109809144
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.2539349236
Short name T31
Test name
Test status
Simulation time 172448312 ps
CPU time 1.14 seconds
Started Jan 07 12:58:11 PM PST 24
Finished Jan 07 12:59:48 PM PST 24
Peak memory 199328 kb
Host smart-7a5a52f4-b2d2-408e-83b7-19093c49161c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539349236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.2539349236
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.1455875335
Short name T202
Test name
Test status
Simulation time 108412860 ps
CPU time 1.09 seconds
Started Jan 07 12:58:09 PM PST 24
Finished Jan 07 12:59:35 PM PST 24
Peak memory 199548 kb
Host smart-0ce68290-f827-4551-9213-3267b398990f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455875335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.1455875335
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.1107014849
Short name T426
Test name
Test status
Simulation time 7341176824 ps
CPU time 31.37 seconds
Started Jan 07 12:57:46 PM PST 24
Finished Jan 07 12:59:41 PM PST 24
Peak memory 199564 kb
Host smart-687ea6d9-8fee-4aed-b911-d2f97a6e4cc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107014849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.1107014849
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.4108376562
Short name T216
Test name
Test status
Simulation time 133401579 ps
CPU time 1.54 seconds
Started Jan 07 12:58:00 PM PST 24
Finished Jan 07 12:59:29 PM PST 24
Peak memory 199328 kb
Host smart-55f17f2a-2490-454f-8f1a-391a087f6ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108376562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.4108376562
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.3818203594
Short name T347
Test name
Test status
Simulation time 108540821 ps
CPU time 0.83 seconds
Started Jan 07 12:57:43 PM PST 24
Finished Jan 07 12:59:01 PM PST 24
Peak memory 199380 kb
Host smart-388d58d7-3ac3-4121-9d22-7559063ae0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818203594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.3818203594
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.3784871105
Short name T314
Test name
Test status
Simulation time 66247531 ps
CPU time 0.71 seconds
Started Jan 07 12:58:17 PM PST 24
Finished Jan 07 12:59:44 PM PST 24
Peak memory 199172 kb
Host smart-322584fb-5ebf-42df-a03e-f8a055841484
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784871105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.3784871105
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.851406972
Short name T346
Test name
Test status
Simulation time 244405016 ps
CPU time 1.01 seconds
Started Jan 07 12:57:46 PM PST 24
Finished Jan 07 12:59:26 PM PST 24
Peak memory 216564 kb
Host smart-caf0aa49-04e3-4ba9-9802-1dd4d6f469c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851406972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.851406972
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.3935508708
Short name T21
Test name
Test status
Simulation time 219745841 ps
CPU time 0.88 seconds
Started Jan 07 12:57:52 PM PST 24
Finished Jan 07 12:59:30 PM PST 24
Peak memory 199176 kb
Host smart-3c08e8d6-4069-4608-8a32-bca78eaa1922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935508708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.3935508708
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.4147739389
Short name T45
Test name
Test status
Simulation time 888616933 ps
CPU time 4.8 seconds
Started Jan 07 12:58:17 PM PST 24
Finished Jan 07 12:59:52 PM PST 24
Peak memory 199528 kb
Host smart-bdf53067-f379-45a1-bce8-7f760e68c811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147739389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.4147739389
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.3013933736
Short name T135
Test name
Test status
Simulation time 106832708 ps
CPU time 0.93 seconds
Started Jan 07 12:58:20 PM PST 24
Finished Jan 07 12:59:52 PM PST 24
Peak memory 199392 kb
Host smart-ae5a1eaa-3e60-4f69-a3f2-bf5bab96517c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013933736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.3013933736
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.1837596183
Short name T270
Test name
Test status
Simulation time 119198846 ps
CPU time 1.16 seconds
Started Jan 07 12:57:43 PM PST 24
Finished Jan 07 12:59:03 PM PST 24
Peak memory 199532 kb
Host smart-7200c4ec-54a0-4c9f-aa35-c9f8e5a2bf21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837596183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.1837596183
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.86549049
Short name T282
Test name
Test status
Simulation time 2171333116 ps
CPU time 8.49 seconds
Started Jan 07 12:57:47 PM PST 24
Finished Jan 07 12:59:16 PM PST 24
Peak memory 199528 kb
Host smart-c8c56417-fc0e-452a-8536-157d0f88afed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86549049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.86549049
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.1588049364
Short name T311
Test name
Test status
Simulation time 365875501 ps
CPU time 2.33 seconds
Started Jan 07 12:57:51 PM PST 24
Finished Jan 07 12:59:28 PM PST 24
Peak memory 199308 kb
Host smart-150d9f8b-148e-4104-b384-5ba3cbc5cd04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588049364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.1588049364
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.2965787006
Short name T542
Test name
Test status
Simulation time 66654272 ps
CPU time 0.69 seconds
Started Jan 07 12:57:47 PM PST 24
Finished Jan 07 12:59:33 PM PST 24
Peak memory 199124 kb
Host smart-78555aed-ec7b-48a2-94e5-62419cb6b158
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965787006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.2965787006
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.623022707
Short name T38
Test name
Test status
Simulation time 1231258279 ps
CPU time 5.2 seconds
Started Jan 07 12:58:10 PM PST 24
Finished Jan 07 12:59:38 PM PST 24
Peak memory 221332 kb
Host smart-9ad30aa3-14b2-431f-a89d-416cc646ae9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623022707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.623022707
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.2418791820
Short name T211
Test name
Test status
Simulation time 245240265 ps
CPU time 1.06 seconds
Started Jan 07 12:58:16 PM PST 24
Finished Jan 07 12:59:46 PM PST 24
Peak memory 216464 kb
Host smart-aea2534d-2c7c-4591-b060-ec704f083c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418791820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.2418791820
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.2124974212
Short name T371
Test name
Test status
Simulation time 85040772 ps
CPU time 0.72 seconds
Started Jan 07 12:57:54 PM PST 24
Finished Jan 07 12:59:31 PM PST 24
Peak memory 199160 kb
Host smart-286a3596-365b-4156-8f90-a1c02323452a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124974212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.2124974212
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.2219482909
Short name T132
Test name
Test status
Simulation time 108742272 ps
CPU time 0.94 seconds
Started Jan 07 12:58:15 PM PST 24
Finished Jan 07 12:59:53 PM PST 24
Peak memory 199252 kb
Host smart-19bca325-2448-47bf-b6b6-b433e8bbd730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219482909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.2219482909
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.1375413284
Short name T210
Test name
Test status
Simulation time 398832344 ps
CPU time 2.36 seconds
Started Jan 07 12:58:00 PM PST 24
Finished Jan 07 12:59:25 PM PST 24
Peak memory 199400 kb
Host smart-8fac3c78-6e0a-4c2a-b853-7a0d094695d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375413284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.1375413284
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.53994373
Short name T459
Test name
Test status
Simulation time 388203375 ps
CPU time 2.31 seconds
Started Jan 07 12:58:04 PM PST 24
Finished Jan 07 12:59:34 PM PST 24
Peak memory 199320 kb
Host smart-b6d9e293-ffdb-4f6d-9853-00820d87a8e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53994373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.53994373
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.3628598045
Short name T205
Test name
Test status
Simulation time 225498639 ps
CPU time 1.39 seconds
Started Jan 07 12:57:49 PM PST 24
Finished Jan 07 12:59:25 PM PST 24
Peak memory 199336 kb
Host smart-28915154-c82d-4499-9e19-1e3208541b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628598045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.3628598045
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.1036182889
Short name T448
Test name
Test status
Simulation time 75242169 ps
CPU time 0.74 seconds
Started Jan 07 12:58:11 PM PST 24
Finished Jan 07 12:59:37 PM PST 24
Peak memory 199248 kb
Host smart-f08f20a3-330d-4503-8aea-247f9b96d6de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036182889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.1036182889
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.3551135583
Short name T487
Test name
Test status
Simulation time 1894628316 ps
CPU time 7.39 seconds
Started Jan 07 12:58:15 PM PST 24
Finished Jan 07 12:59:53 PM PST 24
Peak memory 217316 kb
Host smart-7e503007-0197-46ef-92dd-d624063cd20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551135583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.3551135583
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.2882250661
Short name T237
Test name
Test status
Simulation time 244447067 ps
CPU time 1.1 seconds
Started Jan 07 12:58:22 PM PST 24
Finished Jan 07 12:59:55 PM PST 24
Peak memory 216464 kb
Host smart-d1bdb60a-9c83-45e6-bddc-0387a06a3859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882250661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.2882250661
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.3390712306
Short name T26
Test name
Test status
Simulation time 144565491 ps
CPU time 0.82 seconds
Started Jan 07 12:57:46 PM PST 24
Finished Jan 07 12:59:16 PM PST 24
Peak memory 199108 kb
Host smart-b5c46316-de9c-4af1-bce2-60cb802b11cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390712306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.3390712306
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.1995066344
Short name T108
Test name
Test status
Simulation time 1150293523 ps
CPU time 4.94 seconds
Started Jan 07 12:58:17 PM PST 24
Finished Jan 07 12:59:49 PM PST 24
Peak memory 199516 kb
Host smart-ad158840-f514-4f69-8c48-20911eee6a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995066344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.1995066344
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.677196876
Short name T533
Test name
Test status
Simulation time 175000290 ps
CPU time 1.16 seconds
Started Jan 07 12:57:45 PM PST 24
Finished Jan 07 12:59:06 PM PST 24
Peak memory 199412 kb
Host smart-a40fca86-9392-44bf-97f4-6f563c74c179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677196876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.677196876
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.3967859898
Short name T300
Test name
Test status
Simulation time 208109993 ps
CPU time 1.38 seconds
Started Jan 07 12:57:50 PM PST 24
Finished Jan 07 12:59:17 PM PST 24
Peak memory 199500 kb
Host smart-aaa8e0d5-78dd-4464-af14-44537404812d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967859898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.3967859898
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.868795169
Short name T446
Test name
Test status
Simulation time 3018435214 ps
CPU time 10.99 seconds
Started Jan 07 12:57:38 PM PST 24
Finished Jan 07 12:59:27 PM PST 24
Peak memory 199540 kb
Host smart-f67a60b1-5a45-400f-b4bb-d1618ebb10d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868795169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.868795169
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.3594973002
Short name T383
Test name
Test status
Simulation time 262109904 ps
CPU time 1.7 seconds
Started Jan 07 12:57:59 PM PST 24
Finished Jan 07 12:59:25 PM PST 24
Peak memory 199320 kb
Host smart-321db4a7-8f36-4eba-b7a2-c3d03803de50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594973002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.3594973002
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.448786825
Short name T421
Test name
Test status
Simulation time 71780190 ps
CPU time 0.81 seconds
Started Jan 07 12:58:14 PM PST 24
Finished Jan 07 12:59:44 PM PST 24
Peak memory 199384 kb
Host smart-f7afc08b-c7d9-4ccd-b3fe-8d6f33cc50f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448786825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.448786825
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.3298058302
Short name T207
Test name
Test status
Simulation time 204289485 ps
CPU time 1.01 seconds
Started Jan 07 12:56:04 PM PST 24
Finished Jan 07 12:57:57 PM PST 24
Peak memory 199084 kb
Host smart-0a28163b-66e6-4e9f-b82b-d99f611c02c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298058302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.3298058302
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.64808492
Short name T471
Test name
Test status
Simulation time 1237448500 ps
CPU time 5.82 seconds
Started Jan 07 12:56:11 PM PST 24
Finished Jan 07 12:57:53 PM PST 24
Peak memory 217340 kb
Host smart-bbde4d42-01f4-42db-a3c1-9c0a1a0d8812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64808492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.64808492
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.712615175
Short name T468
Test name
Test status
Simulation time 243532692 ps
CPU time 1.07 seconds
Started Jan 07 12:56:16 PM PST 24
Finished Jan 07 12:57:54 PM PST 24
Peak memory 216584 kb
Host smart-fd22765e-9daf-4055-9e90-70a457c78d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712615175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.712615175
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.1090851911
Short name T507
Test name
Test status
Simulation time 147620019 ps
CPU time 0.78 seconds
Started Jan 07 12:56:30 PM PST 24
Finished Jan 07 12:58:18 PM PST 24
Peak memory 199132 kb
Host smart-2c6ac42c-8067-49dc-ba92-c8a6438613bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090851911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.1090851911
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.2469447020
Short name T5
Test name
Test status
Simulation time 1077130870 ps
CPU time 4.84 seconds
Started Jan 07 12:56:18 PM PST 24
Finished Jan 07 12:57:53 PM PST 24
Peak memory 199516 kb
Host smart-4bd519a5-dfac-4046-bf39-60d01e20511f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469447020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.2469447020
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.416671159
Short name T235
Test name
Test status
Simulation time 240160568 ps
CPU time 1.4 seconds
Started Jan 07 12:56:17 PM PST 24
Finished Jan 07 12:58:04 PM PST 24
Peak memory 199472 kb
Host smart-059877dc-1545-4061-ab6c-d2c64a8a7f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416671159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.416671159
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.137105960
Short name T355
Test name
Test status
Simulation time 118616279 ps
CPU time 1.48 seconds
Started Jan 07 12:56:07 PM PST 24
Finished Jan 07 12:58:00 PM PST 24
Peak memory 199388 kb
Host smart-89ea4f43-040e-4cb9-9e85-cd959f46bec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137105960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.137105960
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.760429755
Short name T482
Test name
Test status
Simulation time 185944050 ps
CPU time 1.13 seconds
Started Jan 07 12:56:11 PM PST 24
Finished Jan 07 12:57:44 PM PST 24
Peak memory 199316 kb
Host smart-e5b6fad6-74b6-4d2f-b0d7-113cb4f11f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760429755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.760429755
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.3940898862
Short name T539
Test name
Test status
Simulation time 66607862 ps
CPU time 0.71 seconds
Started Jan 07 12:56:14 PM PST 24
Finished Jan 07 12:57:46 PM PST 24
Peak memory 199176 kb
Host smart-1fd36e11-7533-4bee-b25d-b31146d07a1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940898862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.3940898862
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.1547286284
Short name T34
Test name
Test status
Simulation time 1890588811 ps
CPU time 7.44 seconds
Started Jan 07 12:56:39 PM PST 24
Finished Jan 07 12:58:08 PM PST 24
Peak memory 216176 kb
Host smart-d1dc0960-8690-4560-a62b-d296f1f3139b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547286284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.1547286284
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.2461923906
Short name T133
Test name
Test status
Simulation time 246449051 ps
CPU time 1.01 seconds
Started Jan 07 12:56:35 PM PST 24
Finished Jan 07 12:58:40 PM PST 24
Peak memory 215596 kb
Host smart-c8472d19-99c8-4afd-a08f-e06fbeaef17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461923906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.2461923906
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_reset.2532234303
Short name T44
Test name
Test status
Simulation time 686279773 ps
CPU time 3.61 seconds
Started Jan 07 12:56:08 PM PST 24
Finished Jan 07 12:57:51 PM PST 24
Peak memory 199520 kb
Host smart-dbf59d4c-2836-4269-8f0d-4a9a435b14ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532234303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.2532234303
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.2522183
Short name T286
Test name
Test status
Simulation time 155249475 ps
CPU time 1.08 seconds
Started Jan 07 12:56:36 PM PST 24
Finished Jan 07 12:58:14 PM PST 24
Peak memory 199200 kb
Host smart-ea9cd3b7-d087-479d-bda7-df8d0925e58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.2522183
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.1203211850
Short name T15
Test name
Test status
Simulation time 6680335856 ps
CPU time 24.21 seconds
Started Jan 07 12:56:56 PM PST 24
Finished Jan 07 12:58:56 PM PST 24
Peak memory 199552 kb
Host smart-76039699-3cc9-4fe8-ad03-4835e5dd7299
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203211850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.1203211850
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.2710377820
Short name T380
Test name
Test status
Simulation time 125907470 ps
CPU time 1.38 seconds
Started Jan 07 12:56:11 PM PST 24
Finished Jan 07 12:57:44 PM PST 24
Peak memory 199292 kb
Host smart-3d944e62-b40e-4ad7-949c-23013f535f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710377820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.2710377820
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.1029806660
Short name T323
Test name
Test status
Simulation time 55063598 ps
CPU time 0.68 seconds
Started Jan 07 12:56:47 PM PST 24
Finished Jan 07 12:58:17 PM PST 24
Peak memory 199228 kb
Host smart-1d95a439-e4b6-4207-ba78-24b12c8075ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029806660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.1029806660
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.855381545
Short name T64
Test name
Test status
Simulation time 1886797095 ps
CPU time 6.59 seconds
Started Jan 07 12:56:10 PM PST 24
Finished Jan 07 12:57:52 PM PST 24
Peak memory 216784 kb
Host smart-710cae0f-682a-42ed-aa46-8c07a1897969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855381545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.855381545
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.2383060228
Short name T516
Test name
Test status
Simulation time 243742164 ps
CPU time 1.1 seconds
Started Jan 07 12:56:39 PM PST 24
Finished Jan 07 12:58:01 PM PST 24
Peak memory 216420 kb
Host smart-b1bc1576-1982-4855-a2e9-47b5c2fc8dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383060228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.2383060228
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.1962038914
Short name T251
Test name
Test status
Simulation time 220494362 ps
CPU time 0.85 seconds
Started Jan 07 12:56:20 PM PST 24
Finished Jan 07 12:57:55 PM PST 24
Peak memory 199124 kb
Host smart-ebc180c3-d1e0-4f6c-a3ad-d587014e57d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962038914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.1962038914
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.53748323
Short name T254
Test name
Test status
Simulation time 1294160592 ps
CPU time 5.16 seconds
Started Jan 07 12:56:23 PM PST 24
Finished Jan 07 12:58:04 PM PST 24
Peak memory 199456 kb
Host smart-88ec583a-fee4-4a47-9e98-cf0a262a8c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53748323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.53748323
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.2154732697
Short name T324
Test name
Test status
Simulation time 177700791 ps
CPU time 1.09 seconds
Started Jan 07 12:56:48 PM PST 24
Finished Jan 07 12:58:31 PM PST 24
Peak memory 199344 kb
Host smart-254bd428-3db9-4d4a-bf4d-cfd505b421cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154732697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.2154732697
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.2296811221
Short name T512
Test name
Test status
Simulation time 203148238 ps
CPU time 1.29 seconds
Started Jan 07 12:56:15 PM PST 24
Finished Jan 07 12:57:46 PM PST 24
Peak memory 199500 kb
Host smart-c1102431-9b13-43d3-8d72-89e8dbf7196a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296811221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.2296811221
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.53439631
Short name T229
Test name
Test status
Simulation time 267487042 ps
CPU time 1.79 seconds
Started Jan 07 12:56:39 PM PST 24
Finished Jan 07 12:58:27 PM PST 24
Peak memory 199328 kb
Host smart-51f20183-66af-4cf5-93e0-edc680f8582d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53439631 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.53439631
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.3859941368
Short name T130
Test name
Test status
Simulation time 229827728 ps
CPU time 1.38 seconds
Started Jan 07 12:56:35 PM PST 24
Finished Jan 07 12:58:22 PM PST 24
Peak memory 199340 kb
Host smart-a4a0d8e2-9bff-4327-9c67-3de63fe7bbe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859941368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.3859941368
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.4012212851
Short name T368
Test name
Test status
Simulation time 52941761 ps
CPU time 0.7 seconds
Started Jan 07 12:56:07 PM PST 24
Finished Jan 07 12:57:51 PM PST 24
Peak memory 199200 kb
Host smart-32e0b70e-da9d-4858-be84-a6dcb35ee98c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012212851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.4012212851
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.1070055171
Short name T398
Test name
Test status
Simulation time 244321804 ps
CPU time 1.05 seconds
Started Jan 07 12:56:38 PM PST 24
Finished Jan 07 12:58:31 PM PST 24
Peak memory 216672 kb
Host smart-2853ae35-4c36-446e-ba06-14a7c19f3143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070055171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.1070055171
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.2231623479
Short name T427
Test name
Test status
Simulation time 86576471 ps
CPU time 0.7 seconds
Started Jan 07 12:56:23 PM PST 24
Finished Jan 07 12:58:04 PM PST 24
Peak memory 199156 kb
Host smart-3376d668-9a37-464d-989f-e0f7f9447153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231623479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.2231623479
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.3476566366
Short name T443
Test name
Test status
Simulation time 2092878172 ps
CPU time 7.86 seconds
Started Jan 07 12:56:45 PM PST 24
Finished Jan 07 12:58:25 PM PST 24
Peak memory 199468 kb
Host smart-c7b662a3-4027-4217-8bcc-fa74c677bf6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476566366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.3476566366
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.1132785083
Short name T310
Test name
Test status
Simulation time 97858034 ps
CPU time 0.93 seconds
Started Jan 07 12:56:36 PM PST 24
Finished Jan 07 12:58:33 PM PST 24
Peak memory 199408 kb
Host smart-53f4d23f-d45b-44ef-9e0e-adf8edd11c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132785083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.1132785083
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.340721279
Short name T271
Test name
Test status
Simulation time 202027802 ps
CPU time 1.31 seconds
Started Jan 07 12:56:18 PM PST 24
Finished Jan 07 12:57:59 PM PST 24
Peak memory 199528 kb
Host smart-d51655e1-aec1-4d47-8d8f-447053959a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340721279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.340721279
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.1599938247
Short name T545
Test name
Test status
Simulation time 7235098275 ps
CPU time 30.65 seconds
Started Jan 07 12:56:38 PM PST 24
Finished Jan 07 12:58:50 PM PST 24
Peak memory 199516 kb
Host smart-74c680da-94d5-4168-8e48-a1b980269923
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599938247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.1599938247
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.1650301796
Short name T476
Test name
Test status
Simulation time 144106154 ps
CPU time 1.76 seconds
Started Jan 07 12:56:20 PM PST 24
Finished Jan 07 12:58:05 PM PST 24
Peak memory 199316 kb
Host smart-622fa1e0-f56b-4b70-a262-765e19ae0176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650301796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.1650301796
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.772527730
Short name T139
Test name
Test status
Simulation time 61497201 ps
CPU time 0.71 seconds
Started Jan 07 12:56:21 PM PST 24
Finished Jan 07 12:57:47 PM PST 24
Peak memory 199104 kb
Host smart-6e9d60b3-cd37-4f3a-b370-93d42a28ada7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772527730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.772527730
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.2105484841
Short name T51
Test name
Test status
Simulation time 1225453222 ps
CPU time 5.77 seconds
Started Jan 07 12:56:39 PM PST 24
Finished Jan 07 12:58:22 PM PST 24
Peak memory 216740 kb
Host smart-d44eea69-a6e7-4320-9267-f6201f5c4b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105484841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.2105484841
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.1439741704
Short name T503
Test name
Test status
Simulation time 244233881 ps
CPU time 1.06 seconds
Started Jan 07 12:56:39 PM PST 24
Finished Jan 07 12:58:28 PM PST 24
Peak memory 216480 kb
Host smart-608a506a-aad6-426f-977f-d017c96f956c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439741704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.1439741704
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.147677655
Short name T138
Test name
Test status
Simulation time 103541490 ps
CPU time 0.94 seconds
Started Jan 07 12:56:38 PM PST 24
Finished Jan 07 12:58:31 PM PST 24
Peak memory 199324 kb
Host smart-c8a37307-722d-455d-881d-67b2e8cd4f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147677655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.147677655
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.24592792
Short name T312
Test name
Test status
Simulation time 200826284 ps
CPU time 1.33 seconds
Started Jan 07 12:56:08 PM PST 24
Finished Jan 07 12:57:41 PM PST 24
Peak memory 199504 kb
Host smart-1e6015f7-c4af-41eb-b634-403e06f67fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24592792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.24592792
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.3031101678
Short name T259
Test name
Test status
Simulation time 2412832957 ps
CPU time 8.5 seconds
Started Jan 07 12:56:38 PM PST 24
Finished Jan 07 12:58:18 PM PST 24
Peak memory 199544 kb
Host smart-31fc90ff-b8d8-471d-9142-44c80881a922
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031101678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.3031101678
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.1888942913
Short name T444
Test name
Test status
Simulation time 382918739 ps
CPU time 2.29 seconds
Started Jan 07 12:56:39 PM PST 24
Finished Jan 07 12:58:18 PM PST 24
Peak memory 199304 kb
Host smart-f2fe2459-d888-4dc5-a663-2c13efd19261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888942913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.1888942913
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.268105210
Short name T222
Test name
Test status
Simulation time 298996464 ps
CPU time 1.6 seconds
Started Jan 07 12:56:39 PM PST 24
Finished Jan 07 12:58:13 PM PST 24
Peak memory 199404 kb
Host smart-a990cb1d-17e0-434a-bec3-0c7ae6dd9e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268105210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.268105210
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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