Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8293

1

T1

35

T2

10

T3

183

auto[1]

11241

1

T1

20

T2

1

T3

199

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5997	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6663	1			T1	18		T2	1		T3	132
reset_info_cp[2]	2997	1			T1	10		T3	61		T4	1
reset_info_cp[4]	3961	1			T1	12		T3	82		T4	1
reset_info_cp[8]	88	1			T5	1		T6	1		T91	1
reset_info_cp[16]	104	1			T6	1		T7	1		T24	2
reset_info_cp[32]	121	1			T3	2		T5	1		T91	1
reset_info_cp[64]	121	1			T3	2		T7	1		T88	1
reset_info_cp[128]	102	1			T3	1		T91	1		T23	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3186	1			T1	9		T3	62		T6	6
reset_info_cp[1]	auto[1]	2857	1			T1	8		T3	69		T4	1
reset_info_cp[2]	auto[0]	962	1			T1	5		T3	28		T6	4
reset_info_cp[2]	auto[1]	2035	1			T1	5		T3	33		T4	1
reset_info_cp[4]	auto[0]	1423	1			T1	9		T3	35		T6	7
reset_info_cp[4]	auto[1]	2538	1			T1	3		T3	47		T4	1
reset_info_cp[8]	auto[0]	37	1			T5	1		T6	1		T91	1
reset_info_cp[8]	auto[1]	51	1			T28	1		T32	1		T34	1
reset_info_cp[16]	auto[0]	38	1			T6	1		T7	1		T24	1
reset_info_cp[16]	auto[1]	66	1			T24	1		T26	1		T29	1
reset_info_cp[32]	auto[0]	55	1			T3	1		T5	1		T91	1
reset_info_cp[32]	auto[1]	66	1			T3	1		T28	1		T29	1
reset_info_cp[64]	auto[0]	39	1			T3	1		T7	1		T30	1
reset_info_cp[64]	auto[1]	82	1			T3	1		T88	1		T27	2
reset_info_cp[128]	auto[0]	45	1			T91	1		T24	1		T30	1
reset_info_cp[128]	auto[1]	57	1			T3	1		T23	1		T24	1