Group : rstmgr_env_pkg::rstmgr_env_cov::reset_stretcher_cg
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Group : rstmgr_env_pkg::rstmgr_env_cov::reset_stretcher_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv



Summary for Group rstmgr_env_pkg::rstmgr_env_cov::reset_stretcher_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00


Variables for Group rstmgr_env_pkg::rstmgr_env_cov::reset_stretcher_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
count_cp 4 0 4 100.00 100 1 1 0
length_cp 8 0 8 100.00 100 1 1 0


Summary for Variable count_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for count_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
others 10206 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
cb[0] 1294 1 T1 3 T2 1 T3 3
cb[1] 1140 1 T1 4 T3 4 T6 4
cb[2] 1082 1 T1 4 T3 4 T6 2
cb[3] 1015 1 T1 4 T3 4 T8 4



Summary for Variable length_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for length_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
others 11985 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
lb[0] 399 1 T3 1 T12 2 T57 3
lb[1] 350 1 T1 1 T3 3 T88 1
lb[2] 354 1 T3 2 T8 2 T57 2
lb[3] 349 1 T3 5 T11 1 T57 4
lb[4] 335 1 T3 2 T57 1 T13 4
lb[5] 333 1 T3 1 T6 1 T8 1
lb[6] 359 1 T1 2 T3 1 T57 5
lb[7] 273 1 T3 5 T6 1 T57 8

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