Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8256 |
1 |
|
|
T1 |
22 |
|
T2 |
10 |
|
T3 |
196 |
auto[1] |
11278 |
1 |
|
|
T1 |
33 |
|
T2 |
1 |
|
T3 |
186 |
Summary for Variable reset_info_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for reset_info_cp
Excluded/Illegal bins
NAME | COUNT | STATUS |
others |
5997 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
reset_info_cp[1] |
6663 |
1 |
|
|
T1 |
18 |
|
T2 |
1 |
|
T3 |
132 |
reset_info_cp[2] |
2997 |
1 |
|
|
T1 |
10 |
|
T3 |
61 |
|
T4 |
1 |
reset_info_cp[4] |
3961 |
1 |
|
|
T1 |
12 |
|
T3 |
82 |
|
T4 |
1 |
reset_info_cp[8] |
88 |
1 |
|
|
T5 |
1 |
|
T6 |
1 |
|
T91 |
1 |
reset_info_cp[16] |
104 |
1 |
|
|
T6 |
1 |
|
T7 |
1 |
|
T24 |
2 |
reset_info_cp[32] |
121 |
1 |
|
|
T3 |
2 |
|
T5 |
1 |
|
T91 |
1 |
reset_info_cp[64] |
121 |
1 |
|
|
T3 |
2 |
|
T7 |
1 |
|
T88 |
1 |
reset_info_cp[128] |
102 |
1 |
|
|
T3 |
1 |
|
T91 |
1 |
|
T23 |
1 |
Summary for Cross capture_cross
Samples crossed: reset_info_cp enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
16 |
0 |
16 |
100.00 |
|
Automatically Generated Cross Bins for capture_cross
Bins
reset_info_cp | enable_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
reset_info_cp[1] |
auto[0] |
3183 |
1 |
|
|
T1 |
8 |
|
T3 |
63 |
|
T6 |
7 |
reset_info_cp[1] |
auto[1] |
2860 |
1 |
|
|
T1 |
9 |
|
T3 |
68 |
|
T4 |
1 |
reset_info_cp[2] |
auto[0] |
934 |
1 |
|
|
T1 |
3 |
|
T3 |
28 |
|
T6 |
6 |
reset_info_cp[2] |
auto[1] |
2063 |
1 |
|
|
T1 |
7 |
|
T3 |
33 |
|
T4 |
1 |
reset_info_cp[4] |
auto[0] |
1431 |
1 |
|
|
T1 |
2 |
|
T3 |
40 |
|
T6 |
5 |
reset_info_cp[4] |
auto[1] |
2530 |
1 |
|
|
T1 |
10 |
|
T3 |
42 |
|
T4 |
1 |
reset_info_cp[8] |
auto[0] |
35 |
1 |
|
|
T5 |
1 |
|
T91 |
1 |
|
T134 |
1 |
reset_info_cp[8] |
auto[1] |
53 |
1 |
|
|
T6 |
1 |
|
T24 |
1 |
|
T28 |
1 |
reset_info_cp[16] |
auto[0] |
42 |
1 |
|
|
T6 |
1 |
|
T7 |
1 |
|
T24 |
1 |
reset_info_cp[16] |
auto[1] |
62 |
1 |
|
|
T24 |
1 |
|
T26 |
1 |
|
T29 |
1 |
reset_info_cp[32] |
auto[0] |
46 |
1 |
|
|
T3 |
1 |
|
T5 |
1 |
|
T91 |
1 |
reset_info_cp[32] |
auto[1] |
75 |
1 |
|
|
T3 |
1 |
|
T24 |
1 |
|
T28 |
1 |
reset_info_cp[64] |
auto[0] |
43 |
1 |
|
|
T7 |
1 |
|
T88 |
1 |
|
T27 |
1 |
reset_info_cp[64] |
auto[1] |
78 |
1 |
|
|
T3 |
2 |
|
T27 |
1 |
|
T28 |
2 |
reset_info_cp[128] |
auto[0] |
38 |
1 |
|
|
T3 |
1 |
|
T91 |
1 |
|
T24 |
2 |
reset_info_cp[128] |
auto[1] |
64 |
1 |
|
|
T23 |
1 |
|
T27 |
1 |
|
T29 |
1 |