Group : rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg
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Group : rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv



Summary for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 16 0 16 100.00


Variables for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
enable_cp 2 0 2 100.00 100 1 1 2
reset_info_cp 8 0 8 100.00 100 1 1 0


Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
capture_cross 16 0 16 100.00 100 1 1 0


Summary for Variable enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8256 1 T1 22 T2 10 T3 196
auto[1] 11278 1 T1 33 T2 1 T3 186



Summary for Variable reset_info_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for reset_info_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
others 5997 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
reset_info_cp[1] 6663 1 T1 18 T2 1 T3 132
reset_info_cp[2] 2997 1 T1 10 T3 61 T4 1
reset_info_cp[4] 3961 1 T1 12 T3 82 T4 1
reset_info_cp[8] 88 1 T5 1 T6 1 T91 1
reset_info_cp[16] 104 1 T6 1 T7 1 T24 2
reset_info_cp[32] 121 1 T3 2 T5 1 T91 1
reset_info_cp[64] 121 1 T3 2 T7 1 T88 1
reset_info_cp[128] 102 1 T3 1 T91 1 T23 1



Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for capture_cross

Bins
reset_info_cpenable_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
reset_info_cp[1] auto[0] 3183 1 T1 8 T3 63 T6 7
reset_info_cp[1] auto[1] 2860 1 T1 9 T3 68 T4 1
reset_info_cp[2] auto[0] 934 1 T1 3 T3 28 T6 6
reset_info_cp[2] auto[1] 2063 1 T1 7 T3 33 T4 1
reset_info_cp[4] auto[0] 1431 1 T1 2 T3 40 T6 5
reset_info_cp[4] auto[1] 2530 1 T1 10 T3 42 T4 1
reset_info_cp[8] auto[0] 35 1 T5 1 T91 1 T134 1
reset_info_cp[8] auto[1] 53 1 T6 1 T24 1 T28 1
reset_info_cp[16] auto[0] 42 1 T6 1 T7 1 T24 1
reset_info_cp[16] auto[1] 62 1 T24 1 T26 1 T29 1
reset_info_cp[32] auto[0] 46 1 T3 1 T5 1 T91 1
reset_info_cp[32] auto[1] 75 1 T3 1 T24 1 T28 1
reset_info_cp[64] auto[0] 43 1 T7 1 T88 1 T27 1
reset_info_cp[64] auto[1] 78 1 T3 2 T27 1 T28 2
reset_info_cp[128] auto[0] 38 1 T3 1 T91 1 T24 2
reset_info_cp[128] auto[1] 64 1 T23 1 T27 1 T29 1

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