Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.88 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T503 /workspace/coverage/default/30.rstmgr_sw_rst.3711561658 Jan 14 01:29:15 PM PST 24 Jan 14 01:29:18 PM PST 24 469405191 ps
T504 /workspace/coverage/default/44.rstmgr_sw_rst.1029446666 Jan 14 01:29:59 PM PST 24 Jan 14 01:30:01 PM PST 24 117328713 ps
T505 /workspace/coverage/default/16.rstmgr_stress_all.2312021011 Jan 14 01:28:40 PM PST 24 Jan 14 01:28:42 PM PST 24 206067603 ps
T506 /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.1801375578 Jan 14 01:28:43 PM PST 24 Jan 14 01:28:44 PM PST 24 243910190 ps
T507 /workspace/coverage/default/1.rstmgr_por_stretcher.1984164105 Jan 14 01:26:56 PM PST 24 Jan 14 01:27:00 PM PST 24 194040208 ps
T508 /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.1450329800 Jan 14 01:27:08 PM PST 24 Jan 14 01:27:11 PM PST 24 163038883 ps
T509 /workspace/coverage/default/29.rstmgr_sw_rst.3671700805 Jan 14 01:29:17 PM PST 24 Jan 14 01:29:20 PM PST 24 120194239 ps
T510 /workspace/coverage/default/25.rstmgr_alert_test.663400458 Jan 14 01:29:10 PM PST 24 Jan 14 01:29:13 PM PST 24 66693464 ps
T511 /workspace/coverage/default/49.rstmgr_stress_all.3809869607 Jan 14 01:30:18 PM PST 24 Jan 14 01:30:31 PM PST 24 3075686501 ps
T512 /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.3717405138 Jan 14 01:27:39 PM PST 24 Jan 14 01:27:41 PM PST 24 243910961 ps
T513 /workspace/coverage/default/36.rstmgr_reset.2635606436 Jan 14 01:29:35 PM PST 24 Jan 14 01:29:42 PM PST 24 919953815 ps
T514 /workspace/coverage/default/11.rstmgr_stress_all.1856052891 Jan 14 01:28:06 PM PST 24 Jan 14 01:28:25 PM PST 24 4859494846 ps
T515 /workspace/coverage/default/28.rstmgr_reset.3978998641 Jan 14 01:29:10 PM PST 24 Jan 14 01:29:17 PM PST 24 800456102 ps
T516 /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.1165516135 Jan 14 01:28:49 PM PST 24 Jan 14 01:28:51 PM PST 24 106609224 ps
T517 /workspace/coverage/default/28.rstmgr_alert_test.440952460 Jan 14 01:29:08 PM PST 24 Jan 14 01:29:11 PM PST 24 78657303 ps
T518 /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.1085229614 Jan 14 01:28:02 PM PST 24 Jan 14 01:28:10 PM PST 24 2166750081 ps
T519 /workspace/coverage/default/32.rstmgr_por_stretcher.1870807615 Jan 14 01:29:29 PM PST 24 Jan 14 01:29:34 PM PST 24 151907791 ps
T520 /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.1274980152 Jan 14 01:27:43 PM PST 24 Jan 14 01:27:45 PM PST 24 164787220 ps
T521 /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.1131102845 Jan 14 01:28:17 PM PST 24 Jan 14 01:28:19 PM PST 24 246080871 ps
T522 /workspace/coverage/default/45.rstmgr_reset.475569100 Jan 14 01:30:07 PM PST 24 Jan 14 01:30:13 PM PST 24 864123266 ps
T523 /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.4183609584 Jan 14 01:28:30 PM PST 24 Jan 14 01:28:31 PM PST 24 106778687 ps
T524 /workspace/coverage/default/24.rstmgr_smoke.2651209884 Jan 14 01:28:57 PM PST 24 Jan 14 01:28:59 PM PST 24 258124177 ps
T525 /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.3416398319 Jan 14 01:30:09 PM PST 24 Jan 14 01:30:17 PM PST 24 1897747986 ps
T526 /workspace/coverage/default/12.rstmgr_reset.2398535059 Jan 14 01:28:16 PM PST 24 Jan 14 01:28:23 PM PST 24 1553367272 ps
T527 /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.2299595397 Jan 14 01:27:51 PM PST 24 Jan 14 01:27:53 PM PST 24 144740636 ps
T528 /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.1062414054 Jan 14 01:29:48 PM PST 24 Jan 14 01:29:49 PM PST 24 182651767 ps
T529 /workspace/coverage/default/35.rstmgr_smoke.5792470 Jan 14 01:29:31 PM PST 24 Jan 14 01:29:39 PM PST 24 246249762 ps
T530 /workspace/coverage/default/29.rstmgr_alert_test.1946520731 Jan 14 01:29:14 PM PST 24 Jan 14 01:29:15 PM PST 24 67322813 ps
T531 /workspace/coverage/default/12.rstmgr_stress_all.1310437713 Jan 14 01:28:15 PM PST 24 Jan 14 01:28:17 PM PST 24 225112573 ps
T532 /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.2895365316 Jan 14 01:28:56 PM PST 24 Jan 14 01:28:57 PM PST 24 246415641 ps
T533 /workspace/coverage/default/25.rstmgr_smoke.4264724922 Jan 14 01:29:10 PM PST 24 Jan 14 01:29:14 PM PST 24 118275140 ps
T534 /workspace/coverage/default/5.rstmgr_alert_test.1496439841 Jan 14 01:27:44 PM PST 24 Jan 14 01:27:45 PM PST 24 57445671 ps
T535 /workspace/coverage/default/24.rstmgr_alert_test.4136896344 Jan 14 01:29:10 PM PST 24 Jan 14 01:29:13 PM PST 24 77108701 ps
T536 /workspace/coverage/default/27.rstmgr_reset.2612135288 Jan 14 01:29:08 PM PST 24 Jan 14 01:29:17 PM PST 24 1910536672 ps
T537 /workspace/coverage/default/38.rstmgr_stress_all.3078771180 Jan 14 01:29:55 PM PST 24 Jan 14 01:30:28 PM PST 24 8493273870 ps
T538 /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.2653702118 Jan 14 01:29:13 PM PST 24 Jan 14 01:29:15 PM PST 24 171330754 ps
T539 /workspace/coverage/default/40.rstmgr_por_stretcher.248580836 Jan 14 01:29:55 PM PST 24 Jan 14 01:29:57 PM PST 24 157903560 ps
T540 /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.264262766 Jan 14 01:29:29 PM PST 24 Jan 14 01:29:33 PM PST 24 138081795 ps
T541 /workspace/coverage/default/1.rstmgr_sw_rst.870412698 Jan 14 01:26:55 PM PST 24 Jan 14 01:26:58 PM PST 24 158147713 ps
T542 /workspace/coverage/default/29.rstmgr_smoke.1926505756 Jan 14 01:29:10 PM PST 24 Jan 14 01:29:14 PM PST 24 255940782 ps
T543 /workspace/coverage/default/37.rstmgr_reset.1753681833 Jan 14 01:29:31 PM PST 24 Jan 14 01:29:42 PM PST 24 861416154 ps
T544 /workspace/coverage/default/11.rstmgr_sw_rst.3245949360 Jan 14 01:28:06 PM PST 24 Jan 14 01:28:09 PM PST 24 437000771 ps
T545 /workspace/coverage/default/27.rstmgr_por_stretcher.1760898268 Jan 14 01:29:10 PM PST 24 Jan 14 01:29:14 PM PST 24 86941500 ps
T546 /workspace/coverage/default/37.rstmgr_sw_rst.1467201667 Jan 14 01:29:53 PM PST 24 Jan 14 01:29:56 PM PST 24 128250085 ps
T547 /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.2919451541 Jan 14 01:29:03 PM PST 24 Jan 14 01:29:09 PM PST 24 171913783 ps
T548 /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.3438599434 Jan 14 01:28:42 PM PST 24 Jan 14 01:28:44 PM PST 24 147407878 ps
T549 /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.4236930753 Jan 14 01:29:55 PM PST 24 Jan 14 01:30:02 PM PST 24 1226370899 ps
T550 /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.1550978706 Jan 14 01:28:25 PM PST 24 Jan 14 01:28:27 PM PST 24 244361807 ps
T551 /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.2607184618 Jan 14 01:30:04 PM PST 24 Jan 14 01:30:07 PM PST 24 124482503 ps
T552 /workspace/coverage/default/7.rstmgr_sw_rst.585004614 Jan 14 01:27:43 PM PST 24 Jan 14 01:27:46 PM PST 24 344952557 ps
T553 /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.1913179684 Jan 14 01:30:00 PM PST 24 Jan 14 01:30:03 PM PST 24 170193284 ps
T554 /workspace/coverage/default/26.rstmgr_reset.4292961170 Jan 14 01:29:13 PM PST 24 Jan 14 01:29:18 PM PST 24 959797297 ps
T555 /workspace/coverage/default/42.rstmgr_stress_all.3994323578 Jan 14 01:29:56 PM PST 24 Jan 14 01:30:28 PM PST 24 8452853786 ps
T556 /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.1641835713 Jan 14 01:28:34 PM PST 24 Jan 14 01:28:36 PM PST 24 244500107 ps
T557 /workspace/coverage/default/49.rstmgr_alert_test.3219068534 Jan 14 01:30:12 PM PST 24 Jan 14 01:30:13 PM PST 24 67206099 ps
T558 /workspace/coverage/default/32.rstmgr_sw_rst.3967298335 Jan 14 01:29:23 PM PST 24 Jan 14 01:29:25 PM PST 24 119533025 ps
T559 /workspace/coverage/default/23.rstmgr_alert_test.1200752322 Jan 14 01:28:58 PM PST 24 Jan 14 01:28:59 PM PST 24 59495300 ps
T560 /workspace/coverage/default/8.rstmgr_por_stretcher.3688098705 Jan 14 01:27:52 PM PST 24 Jan 14 01:27:54 PM PST 24 107533667 ps
T561 /workspace/coverage/default/22.rstmgr_stress_all.3034795697 Jan 14 01:29:06 PM PST 24 Jan 14 01:29:48 PM PST 24 11105623337 ps
T562 /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.3008532071 Jan 14 01:28:56 PM PST 24 Jan 14 01:29:02 PM PST 24 1229539309 ps
T563 /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.932781637 Jan 14 01:27:24 PM PST 24 Jan 14 01:27:31 PM PST 24 1223913929 ps
T564 /workspace/coverage/default/8.rstmgr_reset.4193465691 Jan 14 01:27:52 PM PST 24 Jan 14 01:27:57 PM PST 24 1372075725 ps
T565 /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.3286904797 Jan 14 01:30:09 PM PST 24 Jan 14 01:30:11 PM PST 24 160458222 ps
T566 /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.1940450412 Jan 14 01:29:34 PM PST 24 Jan 14 01:29:45 PM PST 24 1911744620 ps
T567 /workspace/coverage/default/0.rstmgr_sw_rst.3720972833 Jan 14 01:26:51 PM PST 24 Jan 14 01:26:57 PM PST 24 292373973 ps
T568 /workspace/coverage/default/48.rstmgr_por_stretcher.3050339368 Jan 14 01:30:09 PM PST 24 Jan 14 01:30:11 PM PST 24 163159982 ps
T569 /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.1298255628 Jan 14 01:27:44 PM PST 24 Jan 14 01:27:46 PM PST 24 175874623 ps
T570 /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.2576406335 Jan 14 01:29:03 PM PST 24 Jan 14 01:29:04 PM PST 24 84442088 ps
T571 /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.3812085136 Jan 14 01:29:02 PM PST 24 Jan 14 01:29:04 PM PST 24 243567461 ps
T572 /workspace/coverage/default/31.rstmgr_sw_rst.790980711 Jan 14 01:29:23 PM PST 24 Jan 14 01:29:27 PM PST 24 545067528 ps
T573 /workspace/coverage/default/4.rstmgr_reset.3822365232 Jan 14 01:27:31 PM PST 24 Jan 14 01:27:37 PM PST 24 1339006917 ps
T574 /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.3085940458 Jan 14 01:29:17 PM PST 24 Jan 14 01:29:19 PM PST 24 172190479 ps
T575 /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.1074255508 Jan 14 01:29:32 PM PST 24 Jan 14 01:29:45 PM PST 24 2371472593 ps
T576 /workspace/coverage/default/10.rstmgr_stress_all.1112037838 Jan 14 01:28:08 PM PST 24 Jan 14 01:28:11 PM PST 24 459244397 ps
T577 /workspace/coverage/default/47.rstmgr_smoke.2205869770 Jan 14 01:30:06 PM PST 24 Jan 14 01:30:08 PM PST 24 111535924 ps
T578 /workspace/coverage/default/31.rstmgr_stress_all.110932736 Jan 14 01:29:26 PM PST 24 Jan 14 01:30:05 PM PST 24 9423681830 ps
T579 /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.2226201802 Jan 14 01:29:57 PM PST 24 Jan 14 01:29:59 PM PST 24 108023098 ps
T580 /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.3619940930 Jan 14 01:28:52 PM PST 24 Jan 14 01:28:54 PM PST 24 244623863 ps
T581 /workspace/coverage/default/44.rstmgr_smoke.1543205479 Jan 14 01:30:03 PM PST 24 Jan 14 01:30:06 PM PST 24 253116035 ps
T582 /workspace/coverage/default/46.rstmgr_alert_test.1051826112 Jan 14 01:30:06 PM PST 24 Jan 14 01:30:08 PM PST 24 62023601 ps
T583 /workspace/coverage/default/22.rstmgr_smoke.376985540 Jan 14 01:28:47 PM PST 24 Jan 14 01:28:48 PM PST 24 232653262 ps
T584 /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.3826909270 Jan 14 01:28:58 PM PST 24 Jan 14 01:29:00 PM PST 24 243864006 ps
T585 /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.2342614001 Jan 14 01:30:06 PM PST 24 Jan 14 01:30:09 PM PST 24 110232023 ps
T586 /workspace/coverage/default/5.rstmgr_stress_all.2235549290 Jan 14 01:27:43 PM PST 24 Jan 14 01:28:03 PM PST 24 5406234491 ps
T587 /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.2255456974 Jan 14 01:30:06 PM PST 24 Jan 14 01:30:13 PM PST 24 1220005230 ps
T588 /workspace/coverage/default/13.rstmgr_smoke.1075108120 Jan 14 01:28:16 PM PST 24 Jan 14 01:28:18 PM PST 24 247401151 ps
T589 /workspace/coverage/default/37.rstmgr_alert_test.1787130995 Jan 14 01:30:00 PM PST 24 Jan 14 01:30:02 PM PST 24 60492194 ps
T590 /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.1318083707 Jan 14 01:26:51 PM PST 24 Jan 14 01:26:56 PM PST 24 101656066 ps
T591 /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.3841205000 Jan 14 01:27:50 PM PST 24 Jan 14 01:27:52 PM PST 24 244441459 ps
T592 /workspace/coverage/default/46.rstmgr_stress_all.2222901515 Jan 14 01:30:07 PM PST 24 Jan 14 01:30:36 PM PST 24 7497418039 ps
T593 /workspace/coverage/default/19.rstmgr_reset.4204714391 Jan 14 01:28:42 PM PST 24 Jan 14 01:28:48 PM PST 24 1619497056 ps
T594 /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.2946838876 Jan 14 01:29:55 PM PST 24 Jan 14 01:29:57 PM PST 24 155454255 ps
T595 /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.1016282970 Jan 14 01:29:57 PM PST 24 Jan 14 01:29:59 PM PST 24 241404918 ps
T596 /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.1145771567 Jan 14 01:28:31 PM PST 24 Jan 14 01:28:38 PM PST 24 1230211026 ps
T597 /workspace/coverage/default/40.rstmgr_stress_all.3163459552 Jan 14 01:29:54 PM PST 24 Jan 14 01:30:17 PM PST 24 5734525541 ps
T77 /workspace/coverage/default/4.rstmgr_sec_cm.4217044200 Jan 14 01:27:40 PM PST 24 Jan 14 01:28:07 PM PST 24 16643920402 ps
T598 /workspace/coverage/default/16.rstmgr_smoke.3646036073 Jan 14 01:28:31 PM PST 24 Jan 14 01:28:33 PM PST 24 195817821 ps
T599 /workspace/coverage/default/34.rstmgr_sw_rst.4208330994 Jan 14 01:29:30 PM PST 24 Jan 14 01:29:36 PM PST 24 366028230 ps
T600 /workspace/coverage/default/7.rstmgr_stress_all.171927699 Jan 14 01:27:52 PM PST 24 Jan 14 01:28:52 PM PST 24 17751257122 ps
T601 /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.96823277 Jan 14 01:29:23 PM PST 24 Jan 14 01:29:25 PM PST 24 171029855 ps
T602 /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.2513355744 Jan 14 01:29:17 PM PST 24 Jan 14 01:29:19 PM PST 24 247246073 ps
T603 /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.1490300746 Jan 14 01:26:54 PM PST 24 Jan 14 01:26:56 PM PST 24 149446193 ps
T78 /workspace/coverage/default/3.rstmgr_sec_cm.3740115985 Jan 14 01:27:25 PM PST 24 Jan 14 01:27:50 PM PST 24 16628170826 ps
T604 /workspace/coverage/default/46.rstmgr_por_stretcher.1227603945 Jan 14 01:30:04 PM PST 24 Jan 14 01:30:07 PM PST 24 145317832 ps
T605 /workspace/coverage/default/44.rstmgr_stress_all.405894012 Jan 14 01:30:02 PM PST 24 Jan 14 01:30:22 PM PST 24 4365231852 ps
T606 /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.171280506 Jan 14 01:27:37 PM PST 24 Jan 14 01:27:39 PM PST 24 140273506 ps
T607 /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.2652643973 Jan 14 01:26:55 PM PST 24 Jan 14 01:26:57 PM PST 24 244329713 ps
T608 /workspace/coverage/default/6.rstmgr_stress_all.164875844 Jan 14 01:27:44 PM PST 24 Jan 14 01:28:42 PM PST 24 14214844784 ps
T609 /workspace/coverage/default/38.rstmgr_reset.2924970035 Jan 14 01:29:55 PM PST 24 Jan 14 01:30:01 PM PST 24 1458797093 ps
T610 /workspace/coverage/default/9.rstmgr_sw_rst.4136844314 Jan 14 01:28:01 PM PST 24 Jan 14 01:28:03 PM PST 24 144280337 ps
T611 /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.2381228874 Jan 14 01:29:34 PM PST 24 Jan 14 01:29:39 PM PST 24 117246946 ps
T612 /workspace/coverage/default/39.rstmgr_smoke.3170288542 Jan 14 01:29:56 PM PST 24 Jan 14 01:29:59 PM PST 24 126494658 ps
T613 /workspace/coverage/default/13.rstmgr_sw_rst.864700788 Jan 14 01:28:17 PM PST 24 Jan 14 01:28:19 PM PST 24 131664354 ps
T614 /workspace/coverage/default/1.rstmgr_smoke.3195015903 Jan 14 01:26:54 PM PST 24 Jan 14 01:26:56 PM PST 24 207323372 ps
T615 /workspace/coverage/default/45.rstmgr_smoke.603012303 Jan 14 01:30:07 PM PST 24 Jan 14 01:30:10 PM PST 24 252238187 ps
T616 /workspace/coverage/default/45.rstmgr_alert_test.1122811208 Jan 14 01:30:05 PM PST 24 Jan 14 01:30:08 PM PST 24 96239898 ps
T617 /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.2810771238 Jan 14 01:29:34 PM PST 24 Jan 14 01:29:46 PM PST 24 1885207349 ps
T618 /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.226399839 Jan 14 01:28:38 PM PST 24 Jan 14 01:28:40 PM PST 24 183288463 ps
T619 /workspace/coverage/default/42.rstmgr_sw_rst.1424315998 Jan 14 01:29:59 PM PST 24 Jan 14 01:30:02 PM PST 24 127900968 ps
T620 /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.2476500713 Jan 14 01:29:56 PM PST 24 Jan 14 01:30:05 PM PST 24 1892091169 ps

Test location /workspace/coverage/default/39.rstmgr_stress_all.2665455402
Short name T3
Test name
Test status
Simulation time 13152889530 ps
CPU time 44.49 seconds
Started Jan 14 01:30:03 PM PST 24
Finished Jan 14 01:30:50 PM PST 24
Peak memory 199280 kb
Host smart-7395e79e-6762-440c-a59b-d8d9bc79327f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665455402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.2665455402
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.954934138
Short name T62
Test name
Test status
Simulation time 136398559 ps
CPU time 1.62 seconds
Started Jan 14 01:28:31 PM PST 24
Finished Jan 14 01:28:33 PM PST 24
Peak memory 199352 kb
Host smart-5e60ca1a-c3c2-4068-8884-1bf0bf1d212f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954934138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.954934138
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_reset.2247259625
Short name T6
Test name
Test status
Simulation time 1424544600 ps
CPU time 5.69 seconds
Started Jan 14 01:29:54 PM PST 24
Finished Jan 14 01:30:01 PM PST 24
Peak memory 199604 kb
Host smart-12fb93fb-6826-4439-b9a5-20ad0eda72b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247259625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.2247259625
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2622650518
Short name T95
Test name
Test status
Simulation time 106903039 ps
CPU time 1.08 seconds
Started Jan 14 12:59:07 PM PST 24
Finished Jan 14 12:59:09 PM PST 24
Peak memory 199612 kb
Host smart-e9e6be21-b437-4220-a0c0-a0bd5031ce52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622650518 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.2622650518
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.1534797478
Short name T74
Test name
Test status
Simulation time 16775713087 ps
CPU time 24.59 seconds
Started Jan 14 01:26:49 PM PST 24
Finished Jan 14 01:27:14 PM PST 24
Peak memory 217504 kb
Host smart-bab0c616-a071-4f84-a3d5-57290c2a57b7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534797478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.1534797478
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.2053150059
Short name T32
Test name
Test status
Simulation time 1230589703 ps
CPU time 5.75 seconds
Started Jan 14 01:29:26 PM PST 24
Finished Jan 14 01:29:36 PM PST 24
Peak memory 216248 kb
Host smart-4a9157e6-ff95-4859-81f4-65ef3ceae9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053150059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.2053150059
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3554557307
Short name T69
Test name
Test status
Simulation time 956622456 ps
CPU time 3.36 seconds
Started Jan 14 12:59:21 PM PST 24
Finished Jan 14 12:59:25 PM PST 24
Peak memory 199620 kb
Host smart-c36135f8-1658-4bc1-82e7-bfd0bf2b70ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554557307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.3554557307
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.1264123570
Short name T10
Test name
Test status
Simulation time 80707464 ps
CPU time 0.76 seconds
Started Jan 14 01:28:08 PM PST 24
Finished Jan 14 01:28:10 PM PST 24
Peak memory 199212 kb
Host smart-740c0182-c695-4d3c-b597-de9a634cfee9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264123570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.1264123570
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.348852074
Short name T153
Test name
Test status
Simulation time 185539785 ps
CPU time 1.18 seconds
Started Jan 14 01:28:07 PM PST 24
Finished Jan 14 01:28:10 PM PST 24
Peak memory 199328 kb
Host smart-2ca2a488-8ef0-4e45-8a01-6b0a990a6c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348852074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.348852074
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.938857989
Short name T68
Test name
Test status
Simulation time 239747262 ps
CPU time 1.93 seconds
Started Jan 14 12:59:21 PM PST 24
Finished Jan 14 12:59:23 PM PST 24
Peak memory 199712 kb
Host smart-cee34b0e-dc22-45de-913f-a2828700e080
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938857989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.938857989
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.3024388828
Short name T30
Test name
Test status
Simulation time 137278513 ps
CPU time 1.17 seconds
Started Jan 14 01:28:30 PM PST 24
Finished Jan 14 01:28:31 PM PST 24
Peak memory 199380 kb
Host smart-a1cbb3b3-f031-4d94-a040-cf4f1b1ac0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024388828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.3024388828
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.297461604
Short name T36
Test name
Test status
Simulation time 1886085845 ps
CPU time 6.99 seconds
Started Jan 14 01:29:11 PM PST 24
Finished Jan 14 01:29:20 PM PST 24
Peak memory 216876 kb
Host smart-b9aa4ea8-911e-47e4-aa59-5ed99c4b5cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297461604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.297461604
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3564159392
Short name T127
Test name
Test status
Simulation time 880864117 ps
CPU time 3.02 seconds
Started Jan 14 12:59:00 PM PST 24
Finished Jan 14 12:59:06 PM PST 24
Peak memory 199644 kb
Host smart-58dece63-eeb3-4062-b111-fc9219b63d50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564159392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.3564159392
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_reset.3101754004
Short name T134
Test name
Test status
Simulation time 849295325 ps
CPU time 4.05 seconds
Started Jan 14 01:26:49 PM PST 24
Finished Jan 14 01:26:54 PM PST 24
Peak memory 199604 kb
Host smart-4b8803d9-38b1-445a-9540-cb799fcd9dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101754004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.3101754004
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.2419571256
Short name T97
Test name
Test status
Simulation time 297458202 ps
CPU time 2.44 seconds
Started Jan 14 12:58:35 PM PST 24
Finished Jan 14 12:58:44 PM PST 24
Peak memory 207780 kb
Host smart-1102e3b5-dd83-4f58-88e0-1b5329fdc76b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419571256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.2419571256
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.3134655695
Short name T123
Test name
Test status
Simulation time 799453608 ps
CPU time 2.83 seconds
Started Jan 14 12:58:28 PM PST 24
Finished Jan 14 12:58:31 PM PST 24
Peak memory 199680 kb
Host smart-6b2bdec3-5c3d-4968-bb66-60d1e44ecbbf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134655695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.3134655695
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.942555940
Short name T116
Test name
Test status
Simulation time 132940263 ps
CPU time 1.05 seconds
Started Jan 14 12:59:37 PM PST 24
Finished Jan 14 12:59:39 PM PST 24
Peak memory 199460 kb
Host smart-d751602c-3823-44cd-9ae9-5dd037ca5416
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942555940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_sa
me_csr_outstanding.942555940
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.2584151330
Short name T21
Test name
Test status
Simulation time 91705264 ps
CPU time 0.74 seconds
Started Jan 14 01:26:49 PM PST 24
Finished Jan 14 01:26:55 PM PST 24
Peak memory 199208 kb
Host smart-0d6d331b-dc52-41ec-b83e-d47c7950759a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584151330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.2584151330
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.1675069060
Short name T38
Test name
Test status
Simulation time 1234126431 ps
CPU time 5.4 seconds
Started Jan 14 01:28:20 PM PST 24
Finished Jan 14 01:28:26 PM PST 24
Peak memory 216256 kb
Host smart-0b03de20-9ea6-4330-b6f9-f6a0c398bfa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675069060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.1675069060
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.3002164188
Short name T165
Test name
Test status
Simulation time 227108994 ps
CPU time 1.64 seconds
Started Jan 14 12:58:35 PM PST 24
Finished Jan 14 12:58:43 PM PST 24
Peak memory 199528 kb
Host smart-92015000-507f-4da8-97e8-a317bc9874a8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002164188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.3
002164188
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3317316884
Short name T202
Test name
Test status
Simulation time 2305847683 ps
CPU time 9.24 seconds
Started Jan 14 12:58:35 PM PST 24
Finished Jan 14 12:58:50 PM PST 24
Peak memory 199612 kb
Host smart-cdbfc8e0-fe6d-43cd-af4b-740c34c9ee41
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317316884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.3
317316884
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.998235545
Short name T226
Test name
Test status
Simulation time 151363228 ps
CPU time 0.92 seconds
Started Jan 14 12:58:35 PM PST 24
Finished Jan 14 12:58:42 PM PST 24
Peak memory 199512 kb
Host smart-79fd60b7-fde9-44c1-8bc4-1aeb59dd83f9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998235545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.998235545
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.753084455
Short name T212
Test name
Test status
Simulation time 181571738 ps
CPU time 1.28 seconds
Started Jan 14 12:58:32 PM PST 24
Finished Jan 14 12:58:34 PM PST 24
Peak memory 199660 kb
Host smart-7a9475a4-9161-4eae-a833-fc83a6cdf1d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753084455 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.753084455
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2700282504
Short name T179
Test name
Test status
Simulation time 85911392 ps
CPU time 0.83 seconds
Started Jan 14 12:58:34 PM PST 24
Finished Jan 14 12:58:35 PM PST 24
Peak memory 199476 kb
Host smart-9515609e-0c86-43e5-996e-fa6187a32734
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700282504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.2700282504
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1508590197
Short name T176
Test name
Test status
Simulation time 156282422 ps
CPU time 1.12 seconds
Started Jan 14 12:58:35 PM PST 24
Finished Jan 14 12:58:42 PM PST 24
Peak memory 199576 kb
Host smart-02fa000f-6624-4e4c-9abd-f08dab9956f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508590197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.1508590197
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2398118380
Short name T106
Test name
Test status
Simulation time 94738038 ps
CPU time 1.37 seconds
Started Jan 14 12:58:28 PM PST 24
Finished Jan 14 12:58:30 PM PST 24
Peak memory 199680 kb
Host smart-4814e981-6ba9-4de8-bcb0-8f2225a37f13
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398118380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.2398118380
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2641227138
Short name T224
Test name
Test status
Simulation time 97901819 ps
CPU time 1.3 seconds
Started Jan 14 12:58:48 PM PST 24
Finished Jan 14 12:58:50 PM PST 24
Peak memory 199556 kb
Host smart-93ace2a3-6130-45d1-b84a-88ca1caafd27
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641227138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.2
641227138
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.568106367
Short name T187
Test name
Test status
Simulation time 1544545345 ps
CPU time 7.77 seconds
Started Jan 14 12:58:48 PM PST 24
Finished Jan 14 12:58:56 PM PST 24
Peak memory 199596 kb
Host smart-6264ee00-ed90-448a-99cf-da492519ee93
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568106367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.568106367
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.658906739
Short name T184
Test name
Test status
Simulation time 101188344 ps
CPU time 0.81 seconds
Started Jan 14 12:58:33 PM PST 24
Finished Jan 14 12:58:35 PM PST 24
Peak memory 199552 kb
Host smart-f557c20e-ec34-48bc-9033-92360ce5bd42
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658906739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.658906739
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.1261867873
Short name T205
Test name
Test status
Simulation time 99199145 ps
CPU time 0.92 seconds
Started Jan 14 12:58:54 PM PST 24
Finished Jan 14 12:58:59 PM PST 24
Peak memory 199608 kb
Host smart-ad0c4be0-8e9b-4f1a-b7a1-87390a9662f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261867873 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.1261867873
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.961288294
Short name T222
Test name
Test status
Simulation time 63984318 ps
CPU time 0.75 seconds
Started Jan 14 12:58:45 PM PST 24
Finished Jan 14 12:58:47 PM PST 24
Peak memory 199508 kb
Host smart-cef2f293-ed45-494c-86f8-a03315008f31
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961288294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.961288294
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3691576305
Short name T236
Test name
Test status
Simulation time 212245434 ps
CPU time 1.51 seconds
Started Jan 14 12:58:53 PM PST 24
Finished Jan 14 12:58:59 PM PST 24
Peak memory 199632 kb
Host smart-4d3c6dfb-6e83-4ff0-8e29-84fa9f0047d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691576305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.3691576305
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.2085730383
Short name T216
Test name
Test status
Simulation time 498201370 ps
CPU time 1.85 seconds
Started Jan 14 12:58:36 PM PST 24
Finished Jan 14 12:58:43 PM PST 24
Peak memory 199660 kb
Host smart-bc99893c-5a05-40b6-9d1d-18d5ae1fabfc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085730383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.2085730383
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.16724753
Short name T199
Test name
Test status
Simulation time 158943536 ps
CPU time 1.41 seconds
Started Jan 14 12:59:22 PM PST 24
Finished Jan 14 12:59:24 PM PST 24
Peak memory 207852 kb
Host smart-832e90d3-7c23-41ce-bc2e-919e1662fb94
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16724753 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.16724753
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.2568819251
Short name T206
Test name
Test status
Simulation time 96038896 ps
CPU time 0.86 seconds
Started Jan 14 12:59:28 PM PST 24
Finished Jan 14 12:59:29 PM PST 24
Peak memory 199516 kb
Host smart-8764d566-e8fa-42ba-ab56-a3ae946e9b07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568819251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.2568819251
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3396575197
Short name T170
Test name
Test status
Simulation time 101871497 ps
CPU time 1.13 seconds
Started Jan 14 12:59:23 PM PST 24
Finished Jan 14 12:59:25 PM PST 24
Peak memory 199680 kb
Host smart-c113244d-0877-4241-8c9b-939d85778bf6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396575197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.3396575197
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1069140140
Short name T186
Test name
Test status
Simulation time 114648872 ps
CPU time 1.35 seconds
Started Jan 14 12:59:22 PM PST 24
Finished Jan 14 12:59:24 PM PST 24
Peak memory 207732 kb
Host smart-983d363a-e25e-4be0-a862-01fdf799fc0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069140140 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.1069140140
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.2371039534
Short name T190
Test name
Test status
Simulation time 71203110 ps
CPU time 0.82 seconds
Started Jan 14 12:59:23 PM PST 24
Finished Jan 14 12:59:24 PM PST 24
Peak memory 199460 kb
Host smart-8cb19589-7b4b-4385-8b02-37977d7b321f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371039534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.2371039534
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2195718278
Short name T240
Test name
Test status
Simulation time 124732293 ps
CPU time 1.24 seconds
Started Jan 14 12:59:24 PM PST 24
Finished Jan 14 12:59:26 PM PST 24
Peak memory 199572 kb
Host smart-9e70141a-26a1-4151-bc1f-2ab65c630aec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195718278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.2195718278
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.4256806652
Short name T209
Test name
Test status
Simulation time 178786383 ps
CPU time 2.56 seconds
Started Jan 14 12:59:22 PM PST 24
Finished Jan 14 12:59:25 PM PST 24
Peak memory 199692 kb
Host smart-2c1ce1a1-55b1-420c-a0ce-7f868487bda4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256806652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.4256806652
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.294841457
Short name T237
Test name
Test status
Simulation time 464543903 ps
CPU time 1.87 seconds
Started Jan 14 12:59:24 PM PST 24
Finished Jan 14 12:59:27 PM PST 24
Peak memory 199736 kb
Host smart-eaebb0b9-bc65-4e3b-afa2-01c07e779484
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294841457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_err
.294841457
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.285855507
Short name T223
Test name
Test status
Simulation time 183026817 ps
CPU time 1.74 seconds
Started Jan 14 12:59:38 PM PST 24
Finished Jan 14 12:59:40 PM PST 24
Peak memory 209980 kb
Host smart-13b3e4ca-9728-4c55-b0a8-2c11e73ecd97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285855507 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.285855507
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.4151838723
Short name T192
Test name
Test status
Simulation time 72192523 ps
CPU time 0.77 seconds
Started Jan 14 12:59:36 PM PST 24
Finished Jan 14 12:59:39 PM PST 24
Peak memory 199360 kb
Host smart-723c8f9e-9cb2-426e-96f1-c703f894e8ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151838723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.4151838723
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.2881299690
Short name T175
Test name
Test status
Simulation time 190951325 ps
CPU time 2.66 seconds
Started Jan 14 12:59:25 PM PST 24
Finished Jan 14 12:59:28 PM PST 24
Peak memory 207828 kb
Host smart-dcd75da1-42c7-4420-890a-40cf18757b4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881299690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.2881299690
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.2110776500
Short name T98
Test name
Test status
Simulation time 823249556 ps
CPU time 2.75 seconds
Started Jan 14 12:59:39 PM PST 24
Finished Jan 14 12:59:43 PM PST 24
Peak memory 199680 kb
Host smart-bf7468b1-cb52-4612-b165-8f0f7a4591d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110776500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.2110776500
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.629842384
Short name T171
Test name
Test status
Simulation time 177029183 ps
CPU time 1.26 seconds
Started Jan 14 12:59:38 PM PST 24
Finished Jan 14 12:59:40 PM PST 24
Peak memory 199608 kb
Host smart-d2a48f69-821d-4cc0-9c57-2ed15742499e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629842384 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.629842384
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.766376778
Short name T197
Test name
Test status
Simulation time 70115407 ps
CPU time 0.76 seconds
Started Jan 14 12:59:36 PM PST 24
Finished Jan 14 12:59:39 PM PST 24
Peak memory 199460 kb
Host smart-bc40bf34-66ab-45a2-978b-c4264447e2e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766376778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.766376778
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.3768971246
Short name T219
Test name
Test status
Simulation time 133361994 ps
CPU time 1.05 seconds
Started Jan 14 12:59:28 PM PST 24
Finished Jan 14 12:59:29 PM PST 24
Peak memory 199580 kb
Host smart-8851913e-cab2-42eb-a6f0-3e418cdef761
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768971246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.3768971246
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3816777811
Short name T182
Test name
Test status
Simulation time 196692599 ps
CPU time 1.72 seconds
Started Jan 14 12:59:26 PM PST 24
Finished Jan 14 12:59:28 PM PST 24
Peak memory 199636 kb
Host smart-513c603d-93d5-42f2-a9a1-50688ed7fbd6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816777811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.3816777811
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.897871375
Short name T126
Test name
Test status
Simulation time 513119717 ps
CPU time 1.95 seconds
Started Jan 14 12:59:37 PM PST 24
Finished Jan 14 12:59:40 PM PST 24
Peak memory 199716 kb
Host smart-a691f898-077b-40aa-9195-30620ee5ebbd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897871375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_err
.897871375
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.260940968
Short name T195
Test name
Test status
Simulation time 116861663 ps
CPU time 1.07 seconds
Started Jan 14 12:59:39 PM PST 24
Finished Jan 14 12:59:43 PM PST 24
Peak memory 199696 kb
Host smart-95daaf4d-c66f-45d2-b20e-477d4c90cb48
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260940968 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.260940968
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.1717614204
Short name T166
Test name
Test status
Simulation time 64781394 ps
CPU time 0.72 seconds
Started Jan 14 12:59:39 PM PST 24
Finished Jan 14 12:59:41 PM PST 24
Peak memory 199568 kb
Host smart-7a63a067-70da-4127-8b84-01602c80c404
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717614204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.1717614204
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2470407021
Short name T185
Test name
Test status
Simulation time 77906772 ps
CPU time 0.93 seconds
Started Jan 14 12:59:34 PM PST 24
Finished Jan 14 12:59:39 PM PST 24
Peak memory 199532 kb
Host smart-86f725ef-63e6-44a8-be09-cf6ab38e5b5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470407021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.2470407021
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.278389370
Short name T233
Test name
Test status
Simulation time 191989190 ps
CPU time 2.8 seconds
Started Jan 14 12:59:34 PM PST 24
Finished Jan 14 12:59:41 PM PST 24
Peak memory 199692 kb
Host smart-2d0f1b51-fefe-43c1-b90f-4b5e96071e75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278389370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.278389370
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.2597978380
Short name T128
Test name
Test status
Simulation time 770367173 ps
CPU time 2.62 seconds
Started Jan 14 12:59:39 PM PST 24
Finished Jan 14 12:59:45 PM PST 24
Peak memory 199768 kb
Host smart-a27aa32c-5d18-4c3b-8a45-db0474914b44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597978380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.2597978380
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.140883025
Short name T242
Test name
Test status
Simulation time 109366750 ps
CPU time 1.07 seconds
Started Jan 14 12:59:40 PM PST 24
Finished Jan 14 12:59:44 PM PST 24
Peak memory 199700 kb
Host smart-d2eb19ff-6ba2-408f-81ed-ab57e8f7b183
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140883025 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.140883025
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3246169203
Short name T207
Test name
Test status
Simulation time 55205915 ps
CPU time 0.72 seconds
Started Jan 14 12:59:41 PM PST 24
Finished Jan 14 12:59:44 PM PST 24
Peak memory 199412 kb
Host smart-88ecc631-c84f-4756-be61-3ddfba49f5e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246169203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.3246169203
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2661702244
Short name T119
Test name
Test status
Simulation time 183373525 ps
CPU time 1.46 seconds
Started Jan 14 12:59:41 PM PST 24
Finished Jan 14 12:59:44 PM PST 24
Peak memory 199652 kb
Host smart-00bdc662-8ef9-46ea-b535-f314d383bb9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661702244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.2661702244
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3620861864
Short name T204
Test name
Test status
Simulation time 121986509 ps
CPU time 1.65 seconds
Started Jan 14 12:59:41 PM PST 24
Finished Jan 14 12:59:45 PM PST 24
Peak memory 199464 kb
Host smart-f7ecf9cf-ba80-468d-8e74-e7c4e279210a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620861864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.3620861864
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3419433326
Short name T124
Test name
Test status
Simulation time 965909918 ps
CPU time 3.22 seconds
Started Jan 14 12:59:43 PM PST 24
Finished Jan 14 12:59:47 PM PST 24
Peak memory 199608 kb
Host smart-b9b8a047-1b3a-4cee-b603-6b901a299019
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419433326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.3419433326
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2655351220
Short name T213
Test name
Test status
Simulation time 125572715 ps
CPU time 1.02 seconds
Started Jan 14 12:59:42 PM PST 24
Finished Jan 14 12:59:44 PM PST 24
Peak memory 199628 kb
Host smart-91c9614c-9cdf-437e-8d20-91cdb61c2f91
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655351220 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.2655351220
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2832198263
Short name T210
Test name
Test status
Simulation time 69897567 ps
CPU time 0.74 seconds
Started Jan 14 12:59:42 PM PST 24
Finished Jan 14 12:59:44 PM PST 24
Peak memory 199408 kb
Host smart-d1cf908d-4cd8-4c83-899e-8930fb1a24c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832198263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.2832198263
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1352590429
Short name T180
Test name
Test status
Simulation time 90540950 ps
CPU time 0.96 seconds
Started Jan 14 12:59:40 PM PST 24
Finished Jan 14 12:59:43 PM PST 24
Peak memory 199512 kb
Host smart-ede9e262-cd2d-4655-b0ef-26386b2efcb5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352590429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.1352590429
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3966615055
Short name T99
Test name
Test status
Simulation time 96666207 ps
CPU time 1.26 seconds
Started Jan 14 12:59:42 PM PST 24
Finished Jan 14 12:59:44 PM PST 24
Peak memory 199588 kb
Host smart-3322dffb-e04e-450e-8a0f-4a8777603ec9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966615055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.3966615055
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3797880250
Short name T125
Test name
Test status
Simulation time 887414532 ps
CPU time 3.02 seconds
Started Jan 14 12:59:40 PM PST 24
Finished Jan 14 12:59:46 PM PST 24
Peak memory 199656 kb
Host smart-223661d8-d639-4e63-a2ac-5d9f46b88869
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797880250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.3797880250
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3732773051
Short name T198
Test name
Test status
Simulation time 181315466 ps
CPU time 1.15 seconds
Started Jan 14 12:59:52 PM PST 24
Finished Jan 14 12:59:54 PM PST 24
Peak memory 199636 kb
Host smart-c4dc7e34-50fc-44f4-bb99-470edf8837c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732773051 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.3732773051
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.1259139488
Short name T241
Test name
Test status
Simulation time 81358993 ps
CPU time 0.87 seconds
Started Jan 14 12:59:41 PM PST 24
Finished Jan 14 12:59:44 PM PST 24
Peak memory 199512 kb
Host smart-3e5ab872-628f-41c8-8649-0a18321cce3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259139488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.1259139488
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1372250176
Short name T214
Test name
Test status
Simulation time 116326920 ps
CPU time 1.26 seconds
Started Jan 14 12:59:49 PM PST 24
Finished Jan 14 12:59:51 PM PST 24
Peak memory 199716 kb
Host smart-c5b1a341-8ae8-4538-ba90-80058dd84652
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372250176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.1372250176
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2772775480
Short name T173
Test name
Test status
Simulation time 374872328 ps
CPU time 2.66 seconds
Started Jan 14 12:59:40 PM PST 24
Finished Jan 14 12:59:45 PM PST 24
Peak memory 199548 kb
Host smart-42eb6c42-86a1-4c1b-8653-c7d804557afb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772775480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.2772775480
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.617209101
Short name T211
Test name
Test status
Simulation time 435988121 ps
CPU time 1.75 seconds
Started Jan 14 12:59:40 PM PST 24
Finished Jan 14 12:59:44 PM PST 24
Peak memory 199584 kb
Host smart-77f2ac70-0bfa-415e-a2e6-afee1ad6538e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617209101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_err
.617209101
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3962699179
Short name T168
Test name
Test status
Simulation time 118952363 ps
CPU time 1.2 seconds
Started Jan 14 12:59:52 PM PST 24
Finished Jan 14 12:59:54 PM PST 24
Peak memory 199544 kb
Host smart-23834829-1a6f-4129-83f4-5232e498f5ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962699179 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.3962699179
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.1458489619
Short name T121
Test name
Test status
Simulation time 58856685 ps
CPU time 0.77 seconds
Started Jan 14 12:59:50 PM PST 24
Finished Jan 14 12:59:51 PM PST 24
Peak memory 199460 kb
Host smart-6211292d-051d-499c-9af7-8741e2004d6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458489619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.1458489619
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2270651241
Short name T203
Test name
Test status
Simulation time 201408808 ps
CPU time 1.45 seconds
Started Jan 14 12:59:52 PM PST 24
Finished Jan 14 12:59:55 PM PST 24
Peak memory 199656 kb
Host smart-fbab4bdf-bbb8-483b-bbc6-3ab52f5bd06c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270651241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.2270651241
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.549705084
Short name T172
Test name
Test status
Simulation time 182483806 ps
CPU time 2.58 seconds
Started Jan 14 12:59:49 PM PST 24
Finished Jan 14 12:59:53 PM PST 24
Peak memory 199676 kb
Host smart-ed0dfab5-0bf4-4eaa-80d1-62f51b75a56f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549705084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.549705084
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.4049429151
Short name T200
Test name
Test status
Simulation time 928611708 ps
CPU time 3.27 seconds
Started Jan 14 12:59:49 PM PST 24
Finished Jan 14 12:59:53 PM PST 24
Peak memory 199668 kb
Host smart-7b77ca61-551b-4513-8e81-a463b3e5ff8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049429151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.4049429151
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2109694656
Short name T109
Test name
Test status
Simulation time 122233942 ps
CPU time 0.99 seconds
Started Jan 14 12:59:49 PM PST 24
Finished Jan 14 12:59:51 PM PST 24
Peak memory 199512 kb
Host smart-58581d03-7dee-4075-bc65-6abd44d7250a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109694656 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.2109694656
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2169762728
Short name T108
Test name
Test status
Simulation time 67570351 ps
CPU time 0.8 seconds
Started Jan 14 12:59:54 PM PST 24
Finished Jan 14 12:59:55 PM PST 24
Peak memory 199488 kb
Host smart-a094c3aa-eab1-428f-99d8-1194b9e0314b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169762728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.2169762728
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.161785363
Short name T66
Test name
Test status
Simulation time 102528488 ps
CPU time 1.22 seconds
Started Jan 14 12:59:47 PM PST 24
Finished Jan 14 12:59:49 PM PST 24
Peak memory 199604 kb
Host smart-f9b7e3bc-3570-4d54-9e38-c1ca1a1109cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161785363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_sa
me_csr_outstanding.161785363
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.824763896
Short name T102
Test name
Test status
Simulation time 104982555 ps
CPU time 1.53 seconds
Started Jan 14 12:59:51 PM PST 24
Finished Jan 14 12:59:53 PM PST 24
Peak memory 199620 kb
Host smart-49a32a1d-8a9f-421c-a902-4af435bed819
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824763896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.824763896
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1861930864
Short name T232
Test name
Test status
Simulation time 930531710 ps
CPU time 3.12 seconds
Started Jan 14 12:59:51 PM PST 24
Finished Jan 14 12:59:55 PM PST 24
Peak memory 199632 kb
Host smart-417111eb-b9ec-40b1-b1bf-0bf548afe2ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861930864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.1861930864
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3969277436
Short name T191
Test name
Test status
Simulation time 431118056 ps
CPU time 2.71 seconds
Started Jan 14 12:58:53 PM PST 24
Finished Jan 14 12:59:01 PM PST 24
Peak memory 199504 kb
Host smart-202da6db-4b1c-4b4f-8bb0-0d122e8f3739
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969277436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.3
969277436
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3588222318
Short name T221
Test name
Test status
Simulation time 273375583 ps
CPU time 3.27 seconds
Started Jan 14 12:58:51 PM PST 24
Finished Jan 14 12:58:56 PM PST 24
Peak memory 199628 kb
Host smart-29ad5c79-d7fe-4851-9b15-49a54f0cff25
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588222318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.3
588222318
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.662697605
Short name T167
Test name
Test status
Simulation time 151276972 ps
CPU time 0.94 seconds
Started Jan 14 12:58:52 PM PST 24
Finished Jan 14 12:58:54 PM PST 24
Peak memory 199484 kb
Host smart-3c445062-a59a-4698-86ca-024f7c2953ce
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662697605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.662697605
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.4280150157
Short name T230
Test name
Test status
Simulation time 112124952 ps
CPU time 1.13 seconds
Started Jan 14 12:58:51 PM PST 24
Finished Jan 14 12:58:54 PM PST 24
Peak memory 199636 kb
Host smart-a4358a4f-a931-4957-b88f-372317d208b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280150157 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.4280150157
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.275661270
Short name T178
Test name
Test status
Simulation time 83704561 ps
CPU time 0.82 seconds
Started Jan 14 12:58:52 PM PST 24
Finished Jan 14 12:58:54 PM PST 24
Peak memory 199460 kb
Host smart-bca52854-5d5b-4485-9477-860f38eb7292
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275661270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.275661270
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1007406499
Short name T114
Test name
Test status
Simulation time 250623941 ps
CPU time 1.63 seconds
Started Jan 14 12:58:54 PM PST 24
Finished Jan 14 12:59:00 PM PST 24
Peak memory 199720 kb
Host smart-f1b59441-99ba-474a-94a2-79d5e129fcf1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007406499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.1007406499
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.3649950305
Short name T101
Test name
Test status
Simulation time 252705958 ps
CPU time 1.83 seconds
Started Jan 14 12:58:52 PM PST 24
Finished Jan 14 12:58:55 PM PST 24
Peak memory 199664 kb
Host smart-4060906c-8872-47c4-9aa3-ac724442812d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649950305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.3649950305
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.57546968
Short name T169
Test name
Test status
Simulation time 907529204 ps
CPU time 2.89 seconds
Started Jan 14 12:58:52 PM PST 24
Finished Jan 14 12:58:56 PM PST 24
Peak memory 199700 kb
Host smart-2b4efacf-b850-4cdd-a5d2-79ca38119983
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57546968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err.57546968
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.4072383603
Short name T118
Test name
Test status
Simulation time 164992878 ps
CPU time 1.96 seconds
Started Jan 14 12:58:58 PM PST 24
Finished Jan 14 12:59:03 PM PST 24
Peak memory 199632 kb
Host smart-557137b3-9cd9-4004-a13d-0587388d44c8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072383603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.4
072383603
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2125809431
Short name T177
Test name
Test status
Simulation time 2297677718 ps
CPU time 9.7 seconds
Started Jan 14 12:58:59 PM PST 24
Finished Jan 14 12:59:12 PM PST 24
Peak memory 199708 kb
Host smart-17e843be-481b-4b34-9c38-25ad04434c64
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125809431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.2
125809431
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1142107015
Short name T208
Test name
Test status
Simulation time 95819298 ps
CPU time 0.78 seconds
Started Jan 14 12:58:52 PM PST 24
Finished Jan 14 12:58:54 PM PST 24
Peak memory 199436 kb
Host smart-5af8646a-0b82-4177-bcb5-3625fbcb4f30
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142107015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.1
142107015
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.175622833
Short name T71
Test name
Test status
Simulation time 112623717 ps
CPU time 1.13 seconds
Started Jan 14 12:59:00 PM PST 24
Finished Jan 14 12:59:04 PM PST 24
Peak memory 199648 kb
Host smart-dad6a632-6e70-4355-973f-51d7913ce61f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175622833 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.175622833
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3474344794
Short name T234
Test name
Test status
Simulation time 81661981 ps
CPU time 0.82 seconds
Started Jan 14 12:58:58 PM PST 24
Finished Jan 14 12:59:00 PM PST 24
Peak memory 199568 kb
Host smart-e9f488e8-1e33-4468-988e-6ca09d7dcc57
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474344794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.3474344794
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.4143809918
Short name T189
Test name
Test status
Simulation time 137529342 ps
CPU time 1.09 seconds
Started Jan 14 12:58:59 PM PST 24
Finished Jan 14 12:59:03 PM PST 24
Peak memory 199540 kb
Host smart-9c8323a2-c50c-48f2-985f-751a00ed90e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143809918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.4143809918
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2823023549
Short name T196
Test name
Test status
Simulation time 185568725 ps
CPU time 2.58 seconds
Started Jan 14 12:58:52 PM PST 24
Finished Jan 14 12:58:56 PM PST 24
Peak memory 199504 kb
Host smart-37bc9730-50e3-41ae-87df-cb9721f5b3cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823023549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.2823023549
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.21129010
Short name T65
Test name
Test status
Simulation time 1008418680 ps
CPU time 3.22 seconds
Started Jan 14 12:58:52 PM PST 24
Finished Jan 14 12:58:56 PM PST 24
Peak memory 199640 kb
Host smart-d4d23774-33a6-48a8-9b56-5b0b57ef26d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21129010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err.21129010
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.255969502
Short name T217
Test name
Test status
Simulation time 149190683 ps
CPU time 1.94 seconds
Started Jan 14 12:59:02 PM PST 24
Finished Jan 14 12:59:06 PM PST 24
Peak memory 199568 kb
Host smart-01dce9ac-6665-47fd-a6f0-d3c6e986ff25
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255969502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.255969502
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.697686673
Short name T225
Test name
Test status
Simulation time 485331488 ps
CPU time 5.4 seconds
Started Jan 14 12:59:00 PM PST 24
Finished Jan 14 12:59:08 PM PST 24
Peak memory 199476 kb
Host smart-7fcd4307-b34d-4c6b-89fb-15df288e1442
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697686673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.697686673
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1765155010
Short name T104
Test name
Test status
Simulation time 149122590 ps
CPU time 0.89 seconds
Started Jan 14 12:58:57 PM PST 24
Finished Jan 14 12:58:59 PM PST 24
Peak memory 199436 kb
Host smart-38b36b61-ef68-4055-9ac5-a3321d9f5d22
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765155010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.1
765155010
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1048603661
Short name T70
Test name
Test status
Simulation time 157370382 ps
CPU time 1.08 seconds
Started Jan 14 12:59:01 PM PST 24
Finished Jan 14 12:59:04 PM PST 24
Peak memory 199588 kb
Host smart-35a20293-1219-42aa-917b-e875b13ffb36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048603661 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.1048603661
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.2014271830
Short name T120
Test name
Test status
Simulation time 70784356 ps
CPU time 0.84 seconds
Started Jan 14 12:59:00 PM PST 24
Finished Jan 14 12:59:04 PM PST 24
Peak memory 199480 kb
Host smart-99555f60-e35d-4b5b-bdbe-e88ef7b00e5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014271830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.2014271830
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1080402055
Short name T183
Test name
Test status
Simulation time 194566132 ps
CPU time 1.35 seconds
Started Jan 14 12:59:01 PM PST 24
Finished Jan 14 12:59:04 PM PST 24
Peak memory 199652 kb
Host smart-de5e4b3a-dc0b-449a-8254-2b706fc27720
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080402055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.1080402055
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.698349492
Short name T218
Test name
Test status
Simulation time 170318165 ps
CPU time 2.31 seconds
Started Jan 14 12:58:58 PM PST 24
Finished Jan 14 12:59:02 PM PST 24
Peak memory 215416 kb
Host smart-7914ba6a-c4e1-4c59-bf3b-c34ce7f9bb46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698349492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.698349492
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.843918639
Short name T64
Test name
Test status
Simulation time 475251575 ps
CPU time 1.85 seconds
Started Jan 14 12:58:59 PM PST 24
Finished Jan 14 12:59:04 PM PST 24
Peak memory 199684 kb
Host smart-86dec1f5-ba91-407b-a0d3-7e3eacaf7ab6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843918639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err.
843918639
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1007536274
Short name T215
Test name
Test status
Simulation time 139489734 ps
CPU time 1.05 seconds
Started Jan 14 12:58:58 PM PST 24
Finished Jan 14 12:59:02 PM PST 24
Peak memory 199572 kb
Host smart-ea285c90-284e-49eb-b1dd-6a699d88a24c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007536274 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.1007536274
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1447754409
Short name T122
Test name
Test status
Simulation time 73703538 ps
CPU time 0.83 seconds
Started Jan 14 12:59:02 PM PST 24
Finished Jan 14 12:59:05 PM PST 24
Peak memory 199556 kb
Host smart-9b58637b-b1ec-4bcf-9d65-e1da3fc67cf2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447754409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.1447754409
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3887992179
Short name T193
Test name
Test status
Simulation time 185027119 ps
CPU time 1.44 seconds
Started Jan 14 12:59:03 PM PST 24
Finished Jan 14 12:59:05 PM PST 24
Peak memory 199700 kb
Host smart-f875b1b5-a709-43e5-a3c3-8e2eacd7640a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887992179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.3887992179
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.89187706
Short name T238
Test name
Test status
Simulation time 396491897 ps
CPU time 2.9 seconds
Started Jan 14 12:58:59 PM PST 24
Finished Jan 14 12:59:05 PM PST 24
Peak memory 199524 kb
Host smart-85195617-b369-4de4-8939-cfa2f45af9e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89187706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.89187706
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2420484344
Short name T105
Test name
Test status
Simulation time 916033714 ps
CPU time 3.42 seconds
Started Jan 14 12:59:02 PM PST 24
Finished Jan 14 12:59:07 PM PST 24
Peak memory 199632 kb
Host smart-abc1514c-3b87-43af-8e74-91e2cea7e002
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420484344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.2420484344
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.3627906907
Short name T235
Test name
Test status
Simulation time 117732445 ps
CPU time 1.21 seconds
Started Jan 14 12:59:02 PM PST 24
Finished Jan 14 12:59:04 PM PST 24
Peak memory 199484 kb
Host smart-963744c0-2138-489e-8cb6-2b991d0a3d70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627906907 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.3627906907
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.920154195
Short name T174
Test name
Test status
Simulation time 76287663 ps
CPU time 0.75 seconds
Started Jan 14 12:58:58 PM PST 24
Finished Jan 14 12:59:00 PM PST 24
Peak memory 199504 kb
Host smart-d1a210d9-d0cf-4995-98f3-3871e1475dce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920154195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.920154195
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.365553769
Short name T117
Test name
Test status
Simulation time 152952202 ps
CPU time 1.17 seconds
Started Jan 14 12:59:03 PM PST 24
Finished Jan 14 12:59:05 PM PST 24
Peak memory 199544 kb
Host smart-63c72d1e-6ddf-41b4-ba90-a55ab48d78b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365553769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sam
e_csr_outstanding.365553769
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3348734805
Short name T100
Test name
Test status
Simulation time 497658201 ps
CPU time 3.27 seconds
Started Jan 14 12:59:01 PM PST 24
Finished Jan 14 12:59:06 PM PST 24
Peak memory 199624 kb
Host smart-ab46f624-943f-40d3-808b-7236dddc38a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348734805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.3348734805
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3449116712
Short name T227
Test name
Test status
Simulation time 471449984 ps
CPU time 2 seconds
Started Jan 14 12:59:00 PM PST 24
Finished Jan 14 12:59:05 PM PST 24
Peak memory 199700 kb
Host smart-1b3a66f3-58cf-4279-ac28-12f62fa06d5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449116712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.3449116712
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2217478130
Short name T188
Test name
Test status
Simulation time 73907477 ps
CPU time 0.8 seconds
Started Jan 14 12:59:09 PM PST 24
Finished Jan 14 12:59:10 PM PST 24
Peak memory 199452 kb
Host smart-6b4cc20f-2849-429a-a982-4a1211fbbf33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217478130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.2217478130
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.4205967757
Short name T220
Test name
Test status
Simulation time 224531028 ps
CPU time 1.4 seconds
Started Jan 14 12:59:08 PM PST 24
Finished Jan 14 12:59:10 PM PST 24
Peak memory 199460 kb
Host smart-13dd7ffa-1f3f-438d-b599-00065329e012
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205967757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.4205967757
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.4112590886
Short name T107
Test name
Test status
Simulation time 279249756 ps
CPU time 1.96 seconds
Started Jan 14 12:59:02 PM PST 24
Finished Jan 14 12:59:05 PM PST 24
Peak memory 199512 kb
Host smart-ec6bb78d-ca51-4fc0-a45b-2ef0445f3000
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112590886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.4112590886
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.518179378
Short name T229
Test name
Test status
Simulation time 117116297 ps
CPU time 1.15 seconds
Started Jan 14 12:59:20 PM PST 24
Finished Jan 14 12:59:22 PM PST 24
Peak memory 199620 kb
Host smart-d659c89e-82e3-4428-878d-2e730902abf8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518179378 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.518179378
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.1402303689
Short name T201
Test name
Test status
Simulation time 82112642 ps
CPU time 0.86 seconds
Started Jan 14 12:59:09 PM PST 24
Finished Jan 14 12:59:10 PM PST 24
Peak memory 199556 kb
Host smart-946c0c23-f535-4615-98e0-546c882b8b1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402303689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.1402303689
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3351335467
Short name T115
Test name
Test status
Simulation time 229575357 ps
CPU time 1.49 seconds
Started Jan 14 12:59:09 PM PST 24
Finished Jan 14 12:59:11 PM PST 24
Peak memory 199760 kb
Host smart-041edcf6-3654-4c79-9253-c415f1f68e12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351335467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.3351335467
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1364279210
Short name T96
Test name
Test status
Simulation time 176832785 ps
CPU time 2.49 seconds
Started Jan 14 12:59:06 PM PST 24
Finished Jan 14 12:59:09 PM PST 24
Peak memory 199600 kb
Host smart-2fdb626f-24a4-427d-b30d-cc37c458863e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364279210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.1364279210
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1584238357
Short name T103
Test name
Test status
Simulation time 415205449 ps
CPU time 1.7 seconds
Started Jan 14 12:59:07 PM PST 24
Finished Jan 14 12:59:09 PM PST 24
Peak memory 199580 kb
Host smart-cd2a4753-e3a4-4456-ac01-496751e75b4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584238357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.1584238357
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1910950524
Short name T239
Test name
Test status
Simulation time 135957655 ps
CPU time 1 seconds
Started Jan 14 12:59:20 PM PST 24
Finished Jan 14 12:59:22 PM PST 24
Peak memory 199520 kb
Host smart-33fb4dfc-1762-4902-ac75-fd9176538a2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910950524 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.1910950524
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.2931116507
Short name T181
Test name
Test status
Simulation time 83825290 ps
CPU time 0.82 seconds
Started Jan 14 12:59:25 PM PST 24
Finished Jan 14 12:59:26 PM PST 24
Peak memory 199444 kb
Host smart-9317f72c-0f67-4ba9-960d-daed46c33e68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931116507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.2931116507
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.822401819
Short name T228
Test name
Test status
Simulation time 261273530 ps
CPU time 1.61 seconds
Started Jan 14 12:59:21 PM PST 24
Finished Jan 14 12:59:24 PM PST 24
Peak memory 199644 kb
Host smart-7452dda2-3e5f-47a1-aec8-dec3cee88efd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822401819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sam
e_csr_outstanding.822401819
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.4194065925
Short name T194
Test name
Test status
Simulation time 268905651 ps
CPU time 1.92 seconds
Started Jan 14 12:59:23 PM PST 24
Finished Jan 14 12:59:25 PM PST 24
Peak memory 215124 kb
Host smart-f6079982-b1a4-4fb0-b63a-739af7fbaec1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194065925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.4194065925
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.431479273
Short name T231
Test name
Test status
Simulation time 476955627 ps
CPU time 1.9 seconds
Started Jan 14 12:59:21 PM PST 24
Finished Jan 14 12:59:24 PM PST 24
Peak memory 199652 kb
Host smart-75d6aba1-1c06-4879-83a2-0faa0169b1c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431479273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err.
431479273
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.4121781420
Short name T137
Test name
Test status
Simulation time 90161473 ps
CPU time 0.78 seconds
Started Jan 14 01:26:55 PM PST 24
Finished Jan 14 01:26:58 PM PST 24
Peak memory 199256 kb
Host smart-3516dc94-53b2-459e-9d31-1bace9106bd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121781420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.4121781420
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.2696055617
Short name T26
Test name
Test status
Simulation time 1225416930 ps
CPU time 6.48 seconds
Started Jan 14 01:26:50 PM PST 24
Finished Jan 14 01:27:00 PM PST 24
Peak memory 216368 kb
Host smart-daf3626a-f0ca-4df4-8c33-7e54c4d43b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696055617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.2696055617
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.3097648145
Short name T462
Test name
Test status
Simulation time 243279481 ps
CPU time 1.17 seconds
Started Jan 14 01:26:47 PM PST 24
Finished Jan 14 01:26:49 PM PST 24
Peak memory 216604 kb
Host smart-1da58ba6-a853-416f-880b-89f3edc521fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097648145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.3097648145
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.1318083707
Short name T590
Test name
Test status
Simulation time 101656066 ps
CPU time 0.99 seconds
Started Jan 14 01:26:51 PM PST 24
Finished Jan 14 01:26:56 PM PST 24
Peak memory 199404 kb
Host smart-985f57de-44c4-4a45-847d-94b5d5af9cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318083707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.1318083707
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.2165119869
Short name T284
Test name
Test status
Simulation time 122361121 ps
CPU time 1.15 seconds
Started Jan 14 01:26:50 PM PST 24
Finished Jan 14 01:26:56 PM PST 24
Peak memory 199488 kb
Host smart-6e621748-df29-484a-81ce-d5dba0d55092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165119869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.2165119869
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.1151055104
Short name T158
Test name
Test status
Simulation time 4696891708 ps
CPU time 21.8 seconds
Started Jan 14 01:26:52 PM PST 24
Finished Jan 14 01:27:17 PM PST 24
Peak memory 199480 kb
Host smart-f529d908-0905-4456-a593-0afdadaac1d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151055104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.1151055104
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.3720972833
Short name T567
Test name
Test status
Simulation time 292373973 ps
CPU time 1.84 seconds
Started Jan 14 01:26:51 PM PST 24
Finished Jan 14 01:26:57 PM PST 24
Peak memory 199428 kb
Host smart-b5eed719-1fa5-4a4d-9c9a-1395d53fdaad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720972833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.3720972833
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.1110752560
Short name T472
Test name
Test status
Simulation time 120614519 ps
CPU time 0.94 seconds
Started Jan 14 01:26:50 PM PST 24
Finished Jan 14 01:26:55 PM PST 24
Peak memory 199420 kb
Host smart-0a869308-6e37-4637-a1ce-ddf8864583a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110752560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.1110752560
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.308356398
Short name T150
Test name
Test status
Simulation time 70735721 ps
CPU time 0.75 seconds
Started Jan 14 01:27:02 PM PST 24
Finished Jan 14 01:27:04 PM PST 24
Peak memory 199244 kb
Host smart-98098d0d-b5ef-4930-9f31-c294cbf98b8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308356398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.308356398
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.938478003
Short name T339
Test name
Test status
Simulation time 1238336413 ps
CPU time 6.21 seconds
Started Jan 14 01:26:56 PM PST 24
Finished Jan 14 01:27:05 PM PST 24
Peak memory 217328 kb
Host smart-cacc45ba-4221-497d-b6b5-2b0453c7c01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938478003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.938478003
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.2652643973
Short name T607
Test name
Test status
Simulation time 244329713 ps
CPU time 0.99 seconds
Started Jan 14 01:26:55 PM PST 24
Finished Jan 14 01:26:57 PM PST 24
Peak memory 216656 kb
Host smart-158cc10a-fbe8-4897-91d3-8758966e5ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652643973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.2652643973
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.1984164105
Short name T507
Test name
Test status
Simulation time 194040208 ps
CPU time 0.84 seconds
Started Jan 14 01:26:56 PM PST 24
Finished Jan 14 01:27:00 PM PST 24
Peak memory 199164 kb
Host smart-ca632ff5-2696-4657-9b16-ed84076b0aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984164105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.1984164105
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.3522717486
Short name T338
Test name
Test status
Simulation time 1656254948 ps
CPU time 5.93 seconds
Started Jan 14 01:26:55 PM PST 24
Finished Jan 14 01:27:02 PM PST 24
Peak memory 199572 kb
Host smart-8026dd3a-6c40-415c-8e01-d58dfd5da39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522717486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.3522717486
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.1591505185
Short name T73
Test name
Test status
Simulation time 17906591726 ps
CPU time 25.38 seconds
Started Jan 14 01:27:03 PM PST 24
Finished Jan 14 01:27:30 PM PST 24
Peak memory 217528 kb
Host smart-06c5ce99-a552-4e61-aca0-e4e7fab60ec0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591505185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.1591505185
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.1490300746
Short name T603
Test name
Test status
Simulation time 149446193 ps
CPU time 1.18 seconds
Started Jan 14 01:26:54 PM PST 24
Finished Jan 14 01:26:56 PM PST 24
Peak memory 199328 kb
Host smart-13af0f39-91ee-4c3c-84e1-787c6514a49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490300746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.1490300746
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.3195015903
Short name T614
Test name
Test status
Simulation time 207323372 ps
CPU time 1.32 seconds
Started Jan 14 01:26:54 PM PST 24
Finished Jan 14 01:26:56 PM PST 24
Peak memory 199568 kb
Host smart-a5c19250-0c65-4826-bdc2-274ed5c828e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195015903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.3195015903
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.1324600318
Short name T493
Test name
Test status
Simulation time 5847952372 ps
CPU time 26.6 seconds
Started Jan 14 01:27:02 PM PST 24
Finished Jan 14 01:27:30 PM PST 24
Peak memory 199540 kb
Host smart-a15c9e67-f334-4db4-bc2b-0bfbb9122511
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324600318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.1324600318
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.870412698
Short name T541
Test name
Test status
Simulation time 158147713 ps
CPU time 1.86 seconds
Started Jan 14 01:26:55 PM PST 24
Finished Jan 14 01:26:58 PM PST 24
Peak memory 199400 kb
Host smart-b87b0fab-9da9-4dff-bdcd-715c50f94921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870412698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.870412698
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.343004982
Short name T85
Test name
Test status
Simulation time 125532362 ps
CPU time 0.95 seconds
Started Jan 14 01:26:55 PM PST 24
Finished Jan 14 01:26:58 PM PST 24
Peak memory 199392 kb
Host smart-37607834-c603-49b8-8ecf-d9da8ec83bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343004982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.343004982
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.732327646
Short name T374
Test name
Test status
Simulation time 71771806 ps
CPU time 0.74 seconds
Started Jan 14 01:28:09 PM PST 24
Finished Jan 14 01:28:11 PM PST 24
Peak memory 199252 kb
Host smart-7f354cd9-2d65-451d-96c7-05dc045ecc05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732327646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.732327646
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.1085229614
Short name T518
Test name
Test status
Simulation time 2166750081 ps
CPU time 7.44 seconds
Started Jan 14 01:28:02 PM PST 24
Finished Jan 14 01:28:10 PM PST 24
Peak memory 216364 kb
Host smart-e4d433c3-b6c3-42a1-9c96-08a50aede1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085229614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.1085229614
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.3731121760
Short name T304
Test name
Test status
Simulation time 244372357 ps
CPU time 1.09 seconds
Started Jan 14 01:28:07 PM PST 24
Finished Jan 14 01:28:10 PM PST 24
Peak memory 216508 kb
Host smart-fac19a62-a76c-4fa5-85e2-25c4a478980b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731121760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.3731121760
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.378395722
Short name T270
Test name
Test status
Simulation time 184748943 ps
CPU time 0.93 seconds
Started Jan 14 01:28:00 PM PST 24
Finished Jan 14 01:28:01 PM PST 24
Peak memory 199184 kb
Host smart-7fa8545a-a5ce-4c02-9744-9179603f3edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378395722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.378395722
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.3227559376
Short name T484
Test name
Test status
Simulation time 779912045 ps
CPU time 3.89 seconds
Started Jan 14 01:28:01 PM PST 24
Finished Jan 14 01:28:06 PM PST 24
Peak memory 199552 kb
Host smart-6554e478-7661-4aa4-943d-a1432cbc46fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227559376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.3227559376
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.1302646423
Short name T489
Test name
Test status
Simulation time 109874347 ps
CPU time 1.02 seconds
Started Jan 14 01:27:58 PM PST 24
Finished Jan 14 01:28:00 PM PST 24
Peak memory 199396 kb
Host smart-d735b46e-b0be-4434-9177-80b0d05814fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302646423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.1302646423
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.2421282454
Short name T80
Test name
Test status
Simulation time 242333361 ps
CPU time 1.38 seconds
Started Jan 14 01:27:58 PM PST 24
Finished Jan 14 01:28:00 PM PST 24
Peak memory 199516 kb
Host smart-14d61b55-4df1-42b6-8af8-63c36ece77e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421282454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.2421282454
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.1112037838
Short name T576
Test name
Test status
Simulation time 459244397 ps
CPU time 2.21 seconds
Started Jan 14 01:28:08 PM PST 24
Finished Jan 14 01:28:11 PM PST 24
Peak memory 199596 kb
Host smart-e91c8f6f-f7ec-4b33-a013-1fee607787f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112037838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.1112037838
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.3778720829
Short name T502
Test name
Test status
Simulation time 422243547 ps
CPU time 2.31 seconds
Started Jan 14 01:28:00 PM PST 24
Finished Jan 14 01:28:03 PM PST 24
Peak memory 199384 kb
Host smart-12f10ef0-5035-426a-ba50-aa190c2bce3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778720829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.3778720829
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.2066591445
Short name T268
Test name
Test status
Simulation time 124915256 ps
CPU time 1.05 seconds
Started Jan 14 01:27:57 PM PST 24
Finished Jan 14 01:27:59 PM PST 24
Peak memory 199408 kb
Host smart-19c20142-105f-4bc5-b222-ea6a1526fac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066591445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.2066591445
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.321734164
Short name T37
Test name
Test status
Simulation time 1227958947 ps
CPU time 5.79 seconds
Started Jan 14 01:28:08 PM PST 24
Finished Jan 14 01:28:15 PM PST 24
Peak memory 216276 kb
Host smart-551e6ed2-ad5f-4a9a-9b31-020ba79cc6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321734164 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.321734164
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.4167831236
Short name T397
Test name
Test status
Simulation time 243898893 ps
CPU time 1.06 seconds
Started Jan 14 01:28:09 PM PST 24
Finished Jan 14 01:28:12 PM PST 24
Peak memory 216504 kb
Host smart-3d8a67f8-34d8-4653-8116-43b781f0dd90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167831236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.4167831236
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.3580238749
Short name T22
Test name
Test status
Simulation time 80155012 ps
CPU time 0.71 seconds
Started Jan 14 01:28:06 PM PST 24
Finished Jan 14 01:28:08 PM PST 24
Peak memory 199208 kb
Host smart-407d4b15-1202-4ddc-ae0e-93a5d9952f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580238749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.3580238749
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.265678937
Short name T386
Test name
Test status
Simulation time 939962822 ps
CPU time 4.81 seconds
Started Jan 14 01:28:05 PM PST 24
Finished Jan 14 01:28:10 PM PST 24
Peak memory 199576 kb
Host smart-7b2854bd-70f8-4b9e-9ed7-780f4568302e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265678937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.265678937
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.3508076647
Short name T347
Test name
Test status
Simulation time 190457626 ps
CPU time 1.29 seconds
Started Jan 14 01:28:06 PM PST 24
Finished Jan 14 01:28:08 PM PST 24
Peak memory 199580 kb
Host smart-303cc091-53d1-4ac2-911f-ee240b15ab0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508076647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.3508076647
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.1856052891
Short name T514
Test name
Test status
Simulation time 4859494846 ps
CPU time 18.64 seconds
Started Jan 14 01:28:06 PM PST 24
Finished Jan 14 01:28:25 PM PST 24
Peak memory 199504 kb
Host smart-5039121f-1b54-4192-b69b-475e006811c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856052891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.1856052891
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.3245949360
Short name T544
Test name
Test status
Simulation time 437000771 ps
CPU time 2.42 seconds
Started Jan 14 01:28:06 PM PST 24
Finished Jan 14 01:28:09 PM PST 24
Peak memory 199352 kb
Host smart-6370c631-9dc0-4a11-a490-9b643c517eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245949360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.3245949360
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.1453250924
Short name T265
Test name
Test status
Simulation time 184315159 ps
CPU time 1.14 seconds
Started Jan 14 01:28:07 PM PST 24
Finished Jan 14 01:28:08 PM PST 24
Peak memory 199356 kb
Host smart-a6c5bc0f-a928-44e7-8a02-6f42aab76653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453250924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.1453250924
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.1053334016
Short name T164
Test name
Test status
Simulation time 78775274 ps
CPU time 0.74 seconds
Started Jan 14 01:28:16 PM PST 24
Finished Jan 14 01:28:17 PM PST 24
Peak memory 199248 kb
Host smart-e7f649f3-ebc0-4e2d-8f33-ee3d0ea5f6ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053334016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.1053334016
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.1131102845
Short name T521
Test name
Test status
Simulation time 246080871 ps
CPU time 1.07 seconds
Started Jan 14 01:28:17 PM PST 24
Finished Jan 14 01:28:19 PM PST 24
Peak memory 215772 kb
Host smart-0dd774b3-7d7f-4384-877f-cb274366090e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131102845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.1131102845
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.3705063451
Short name T273
Test name
Test status
Simulation time 145863099 ps
CPU time 0.8 seconds
Started Jan 14 01:28:16 PM PST 24
Finished Jan 14 01:28:17 PM PST 24
Peak memory 199152 kb
Host smart-eb1a6424-1220-4cd5-83bb-8f6f29230159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705063451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.3705063451
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.2398535059
Short name T526
Test name
Test status
Simulation time 1553367272 ps
CPU time 5.89 seconds
Started Jan 14 01:28:16 PM PST 24
Finished Jan 14 01:28:23 PM PST 24
Peak memory 199552 kb
Host smart-ca4c9ed2-f30d-457e-941c-0cceaec3b262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398535059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.2398535059
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.392497438
Short name T442
Test name
Test status
Simulation time 118939900 ps
CPU time 0.97 seconds
Started Jan 14 01:28:18 PM PST 24
Finished Jan 14 01:28:19 PM PST 24
Peak memory 199372 kb
Host smart-28081ab9-6966-48bf-abeb-90310c0da4a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392497438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.392497438
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.1222773859
Short name T427
Test name
Test status
Simulation time 124904938 ps
CPU time 1.29 seconds
Started Jan 14 01:28:20 PM PST 24
Finished Jan 14 01:28:23 PM PST 24
Peak memory 199560 kb
Host smart-168c0768-2cfb-43f4-9070-fbec05bccfde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222773859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.1222773859
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.1310437713
Short name T531
Test name
Test status
Simulation time 225112573 ps
CPU time 1.61 seconds
Started Jan 14 01:28:15 PM PST 24
Finished Jan 14 01:28:17 PM PST 24
Peak memory 199600 kb
Host smart-84b54b34-6b43-4134-9e79-c16fa3155478
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310437713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.1310437713
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.917070140
Short name T399
Test name
Test status
Simulation time 120456711 ps
CPU time 1.61 seconds
Started Jan 14 01:28:19 PM PST 24
Finished Jan 14 01:28:21 PM PST 24
Peak memory 199388 kb
Host smart-495fcce2-39ae-4da7-8dcb-4007cc1e1f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917070140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.917070140
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.4249219512
Short name T438
Test name
Test status
Simulation time 102871851 ps
CPU time 0.9 seconds
Started Jan 14 01:28:22 PM PST 24
Finished Jan 14 01:28:23 PM PST 24
Peak memory 199384 kb
Host smart-ac829163-185c-4b87-bc8b-1879c1bc3081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249219512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.4249219512
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.1246864719
Short name T250
Test name
Test status
Simulation time 63159538 ps
CPU time 0.7 seconds
Started Jan 14 01:28:20 PM PST 24
Finished Jan 14 01:28:21 PM PST 24
Peak memory 199208 kb
Host smart-d1da0374-f7a9-4d15-a73d-bc1c2da61582
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246864719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.1246864719
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.2886383341
Short name T419
Test name
Test status
Simulation time 2350218797 ps
CPU time 8.25 seconds
Started Jan 14 01:28:19 PM PST 24
Finished Jan 14 01:28:28 PM PST 24
Peak memory 221212 kb
Host smart-95348732-ff75-4ae7-ad53-e01a5c756f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886383341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.2886383341
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.1550978706
Short name T550
Test name
Test status
Simulation time 244361807 ps
CPU time 1.12 seconds
Started Jan 14 01:28:25 PM PST 24
Finished Jan 14 01:28:27 PM PST 24
Peak memory 216664 kb
Host smart-ad5a4e82-8870-4210-8be3-be6674a50661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550978706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.1550978706
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.2453176621
Short name T408
Test name
Test status
Simulation time 104737038 ps
CPU time 0.73 seconds
Started Jan 14 01:28:18 PM PST 24
Finished Jan 14 01:28:19 PM PST 24
Peak memory 199156 kb
Host smart-b54333dd-fe1f-4ec4-af99-2750a61418b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453176621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.2453176621
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.3982740547
Short name T491
Test name
Test status
Simulation time 1396534944 ps
CPU time 5.5 seconds
Started Jan 14 01:28:16 PM PST 24
Finished Jan 14 01:28:22 PM PST 24
Peak memory 199504 kb
Host smart-41ed68de-c41e-4269-8f4e-6cfa7b01b19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982740547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.3982740547
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.129803459
Short name T465
Test name
Test status
Simulation time 153407562 ps
CPU time 1.04 seconds
Started Jan 14 01:28:22 PM PST 24
Finished Jan 14 01:28:24 PM PST 24
Peak memory 199420 kb
Host smart-56b7e985-f469-4d09-a201-8b892a239628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129803459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.129803459
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.1075108120
Short name T588
Test name
Test status
Simulation time 247401151 ps
CPU time 1.49 seconds
Started Jan 14 01:28:16 PM PST 24
Finished Jan 14 01:28:18 PM PST 24
Peak memory 199552 kb
Host smart-aaf64cf3-e876-44e0-8573-00c374665a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075108120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.1075108120
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.1797325187
Short name T345
Test name
Test status
Simulation time 97036347 ps
CPU time 0.84 seconds
Started Jan 14 01:28:25 PM PST 24
Finished Jan 14 01:28:26 PM PST 24
Peak memory 199224 kb
Host smart-74144d3e-158b-4f85-b81d-466f9653c3bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797325187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.1797325187
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.864700788
Short name T613
Test name
Test status
Simulation time 131664354 ps
CPU time 1.57 seconds
Started Jan 14 01:28:17 PM PST 24
Finished Jan 14 01:28:19 PM PST 24
Peak memory 199424 kb
Host smart-d0875a38-4e49-422a-ab65-0bad86984a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864700788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.864700788
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.3444564909
Short name T129
Test name
Test status
Simulation time 93021750 ps
CPU time 0.84 seconds
Started Jan 14 01:28:49 PM PST 24
Finished Jan 14 01:28:50 PM PST 24
Peak memory 199396 kb
Host smart-97016825-4879-4e8c-80c5-71b68b130c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444564909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.3444564909
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.1437143305
Short name T45
Test name
Test status
Simulation time 94749446 ps
CPU time 0.78 seconds
Started Jan 14 01:28:30 PM PST 24
Finished Jan 14 01:28:32 PM PST 24
Peak memory 199216 kb
Host smart-68ea1b44-ed5a-4cfa-afe5-994cd146d1a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437143305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.1437143305
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.1145771567
Short name T596
Test name
Test status
Simulation time 1230211026 ps
CPU time 5.52 seconds
Started Jan 14 01:28:31 PM PST 24
Finished Jan 14 01:28:38 PM PST 24
Peak memory 217348 kb
Host smart-86f3fc9f-151b-4e01-9781-65f01eae11b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145771567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.1145771567
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.2666182421
Short name T450
Test name
Test status
Simulation time 244872424 ps
CPU time 1.03 seconds
Started Jan 14 01:28:34 PM PST 24
Finished Jan 14 01:28:35 PM PST 24
Peak memory 216644 kb
Host smart-5d589a50-3c43-4632-a3d5-522a3d2230bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666182421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.2666182421
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.531327945
Short name T18
Test name
Test status
Simulation time 193655385 ps
CPU time 0.89 seconds
Started Jan 14 01:28:26 PM PST 24
Finished Jan 14 01:28:27 PM PST 24
Peak memory 199208 kb
Host smart-bea35a75-cb9e-42b2-a536-efb5959f3be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531327945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.531327945
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.2755049250
Short name T449
Test name
Test status
Simulation time 765071007 ps
CPU time 4.04 seconds
Started Jan 14 01:28:26 PM PST 24
Finished Jan 14 01:28:30 PM PST 24
Peak memory 199544 kb
Host smart-9d35b52c-6492-4633-ab8a-9a752b6eda26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755049250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.2755049250
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.331596527
Short name T281
Test name
Test status
Simulation time 99619338 ps
CPU time 1.03 seconds
Started Jan 14 01:28:29 PM PST 24
Finished Jan 14 01:28:31 PM PST 24
Peak memory 199408 kb
Host smart-540f018a-4a26-480f-b5ec-0b81cbc6aa50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331596527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.331596527
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.1487600454
Short name T133
Test name
Test status
Simulation time 253489470 ps
CPU time 1.44 seconds
Started Jan 14 01:28:24 PM PST 24
Finished Jan 14 01:28:26 PM PST 24
Peak memory 199512 kb
Host smart-a22da987-9d00-4e7c-876d-e8bc2328d7f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487600454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.1487600454
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.3219241632
Short name T336
Test name
Test status
Simulation time 4453319295 ps
CPU time 19.12 seconds
Started Jan 14 01:28:31 PM PST 24
Finished Jan 14 01:28:51 PM PST 24
Peak memory 199492 kb
Host smart-440fbbec-2252-43b5-a712-c1df9ac76162
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219241632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.3219241632
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.3759975183
Short name T155
Test name
Test status
Simulation time 142033231 ps
CPU time 1.79 seconds
Started Jan 14 01:28:24 PM PST 24
Finished Jan 14 01:28:26 PM PST 24
Peak memory 199400 kb
Host smart-5f00ff08-8861-44f3-83c2-7dcd5a07572a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759975183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.3759975183
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.3971052431
Short name T90
Test name
Test status
Simulation time 141663959 ps
CPU time 1.02 seconds
Started Jan 14 01:28:22 PM PST 24
Finished Jan 14 01:28:24 PM PST 24
Peak memory 199372 kb
Host smart-f602eaf6-b92c-47ee-89b0-b39014e1cfcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971052431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.3971052431
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.2529126316
Short name T383
Test name
Test status
Simulation time 90283042 ps
CPU time 0.78 seconds
Started Jan 14 01:28:31 PM PST 24
Finished Jan 14 01:28:32 PM PST 24
Peak memory 199248 kb
Host smart-a441d288-9ed7-404a-ae12-5cafaf885c31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529126316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.2529126316
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.1203624592
Short name T342
Test name
Test status
Simulation time 1218037163 ps
CPU time 5.67 seconds
Started Jan 14 01:28:32 PM PST 24
Finished Jan 14 01:28:38 PM PST 24
Peak memory 221404 kb
Host smart-8b282f22-097b-4d02-a961-068d8155b600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203624592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.1203624592
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.1641835713
Short name T556
Test name
Test status
Simulation time 244500107 ps
CPU time 1.16 seconds
Started Jan 14 01:28:34 PM PST 24
Finished Jan 14 01:28:36 PM PST 24
Peak memory 216564 kb
Host smart-7282cbf9-2c4b-4069-bce4-aa7579c9510b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641835713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.1641835713
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.3347763854
Short name T333
Test name
Test status
Simulation time 79522039 ps
CPU time 0.7 seconds
Started Jan 14 01:28:30 PM PST 24
Finished Jan 14 01:28:32 PM PST 24
Peak memory 199188 kb
Host smart-15ed20f9-9f41-4ff6-90f6-9b53ead2e479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347763854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.3347763854
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.1873566013
Short name T255
Test name
Test status
Simulation time 875415297 ps
CPU time 4.17 seconds
Started Jan 14 01:28:31 PM PST 24
Finished Jan 14 01:28:36 PM PST 24
Peak memory 199552 kb
Host smart-1dfb966a-bba6-43c9-80da-8a30229b63fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873566013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.1873566013
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.4183609584
Short name T523
Test name
Test status
Simulation time 106778687 ps
CPU time 0.98 seconds
Started Jan 14 01:28:30 PM PST 24
Finished Jan 14 01:28:31 PM PST 24
Peak memory 199300 kb
Host smart-08869e2b-7a28-42cf-bfbd-f40537061c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183609584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.4183609584
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.401682780
Short name T56
Test name
Test status
Simulation time 110582650 ps
CPU time 1.17 seconds
Started Jan 14 01:28:32 PM PST 24
Finished Jan 14 01:28:34 PM PST 24
Peak memory 199516 kb
Host smart-dcb047a2-b130-415a-b727-be2b1795f013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401682780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.401682780
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.9544802
Short name T79
Test name
Test status
Simulation time 3282804199 ps
CPU time 16.39 seconds
Started Jan 14 01:28:33 PM PST 24
Finished Jan 14 01:28:50 PM PST 24
Peak memory 199624 kb
Host smart-8ea47de6-8e24-4a95-9ee5-b33bdc282d54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9544802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.9544802
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.1324693230
Short name T136
Test name
Test status
Simulation time 86453110 ps
CPU time 0.78 seconds
Started Jan 14 01:28:39 PM PST 24
Finished Jan 14 01:28:41 PM PST 24
Peak memory 199204 kb
Host smart-b8d16797-689c-4589-abae-a28c176cb5df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324693230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.1324693230
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.2735428232
Short name T29
Test name
Test status
Simulation time 1212873714 ps
CPU time 5.85 seconds
Started Jan 14 01:28:30 PM PST 24
Finished Jan 14 01:28:36 PM PST 24
Peak memory 216332 kb
Host smart-3dd492b0-db9f-40c4-9a35-4dcd80d4c0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735428232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.2735428232
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.3296612255
Short name T476
Test name
Test status
Simulation time 244157465 ps
CPU time 1.15 seconds
Started Jan 14 01:28:32 PM PST 24
Finished Jan 14 01:28:33 PM PST 24
Peak memory 216488 kb
Host smart-8f1d40b9-a4c9-44fa-8552-91a3416e8ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296612255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.3296612255
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.1423118013
Short name T323
Test name
Test status
Simulation time 124815468 ps
CPU time 0.79 seconds
Started Jan 14 01:28:32 PM PST 24
Finished Jan 14 01:28:34 PM PST 24
Peak memory 199140 kb
Host smart-1517e74d-425e-4f8b-b682-d7c405ee2d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423118013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.1423118013
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.2769390060
Short name T431
Test name
Test status
Simulation time 1324035351 ps
CPU time 5.11 seconds
Started Jan 14 01:28:29 PM PST 24
Finished Jan 14 01:28:35 PM PST 24
Peak memory 199568 kb
Host smart-ebc1e481-d829-4eed-b2c7-b288592ccb38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769390060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.2769390060
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.2203606710
Short name T396
Test name
Test status
Simulation time 102606944 ps
CPU time 1.03 seconds
Started Jan 14 01:28:33 PM PST 24
Finished Jan 14 01:28:34 PM PST 24
Peak memory 199404 kb
Host smart-3fe449e1-b687-4a7d-b6e8-2a519f7f433d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203606710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.2203606710
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.3646036073
Short name T598
Test name
Test status
Simulation time 195817821 ps
CPU time 1.38 seconds
Started Jan 14 01:28:31 PM PST 24
Finished Jan 14 01:28:33 PM PST 24
Peak memory 199552 kb
Host smart-88b3c32b-692d-4d8e-b59a-56aa765ce75c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646036073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.3646036073
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.2312021011
Short name T505
Test name
Test status
Simulation time 206067603 ps
CPU time 1.28 seconds
Started Jan 14 01:28:40 PM PST 24
Finished Jan 14 01:28:42 PM PST 24
Peak memory 199408 kb
Host smart-5fadfde3-c360-443b-8c97-44ddd4ddcb49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312021011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.2312021011
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.4246260401
Short name T313
Test name
Test status
Simulation time 113621554 ps
CPU time 1.57 seconds
Started Jan 14 01:28:33 PM PST 24
Finished Jan 14 01:28:35 PM PST 24
Peak memory 199344 kb
Host smart-a9f3f740-6099-4435-80b8-70692887e7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246260401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.4246260401
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.3472094018
Short name T328
Test name
Test status
Simulation time 92290214 ps
CPU time 0.85 seconds
Started Jan 14 01:28:30 PM PST 24
Finished Jan 14 01:28:32 PM PST 24
Peak memory 199276 kb
Host smart-5e0f5b36-17a7-403a-9429-24e0509e677a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472094018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.3472094018
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.3375015790
Short name T325
Test name
Test status
Simulation time 57037948 ps
CPU time 0.71 seconds
Started Jan 14 01:28:41 PM PST 24
Finished Jan 14 01:28:42 PM PST 24
Peak memory 199216 kb
Host smart-216df26d-2c40-4ac4-bf53-f1390a890216
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375015790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.3375015790
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.3338089573
Short name T311
Test name
Test status
Simulation time 2332875063 ps
CPU time 7.93 seconds
Started Jan 14 01:28:41 PM PST 24
Finished Jan 14 01:28:49 PM PST 24
Peak memory 216360 kb
Host smart-6ff9c6cd-e751-49a1-9e78-e573cebdb617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338089573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.3338089573
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.1801375578
Short name T506
Test name
Test status
Simulation time 243910190 ps
CPU time 1.1 seconds
Started Jan 14 01:28:43 PM PST 24
Finished Jan 14 01:28:44 PM PST 24
Peak memory 216488 kb
Host smart-c9eddec0-e491-4ab7-80e2-259d7db2c4ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801375578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.1801375578
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.475055879
Short name T448
Test name
Test status
Simulation time 145735075 ps
CPU time 0.8 seconds
Started Jan 14 01:28:39 PM PST 24
Finished Jan 14 01:28:40 PM PST 24
Peak memory 199148 kb
Host smart-a3f27cef-0f22-48ca-8643-a1817830c481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475055879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.475055879
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.2400401552
Short name T324
Test name
Test status
Simulation time 1378865907 ps
CPU time 5.36 seconds
Started Jan 14 01:28:38 PM PST 24
Finished Jan 14 01:28:44 PM PST 24
Peak memory 199532 kb
Host smart-51c90966-d2fe-46f2-a4f9-d9561608944c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400401552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.2400401552
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.226399839
Short name T618
Test name
Test status
Simulation time 183288463 ps
CPU time 1.19 seconds
Started Jan 14 01:28:38 PM PST 24
Finished Jan 14 01:28:40 PM PST 24
Peak memory 199384 kb
Host smart-8a6424c5-154e-4c3d-9063-e2070734669a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226399839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.226399839
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.3947962531
Short name T131
Test name
Test status
Simulation time 252280577 ps
CPU time 1.43 seconds
Started Jan 14 01:28:38 PM PST 24
Finished Jan 14 01:28:40 PM PST 24
Peak memory 199512 kb
Host smart-e495f40e-8e2c-453d-8fe2-115adc5943e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947962531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.3947962531
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.3797868475
Short name T420
Test name
Test status
Simulation time 7116874607 ps
CPU time 28.89 seconds
Started Jan 14 01:28:44 PM PST 24
Finished Jan 14 01:29:13 PM PST 24
Peak memory 199604 kb
Host smart-86d05226-9fb5-47ea-8254-771bfb813457
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797868475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.3797868475
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.4288601318
Short name T439
Test name
Test status
Simulation time 119783883 ps
CPU time 1.45 seconds
Started Jan 14 01:28:41 PM PST 24
Finished Jan 14 01:28:43 PM PST 24
Peak memory 199352 kb
Host smart-f55ce202-441a-422f-a6b4-3d6e274413d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288601318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.4288601318
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.4015117661
Short name T416
Test name
Test status
Simulation time 164248230 ps
CPU time 1.26 seconds
Started Jan 14 01:28:42 PM PST 24
Finished Jan 14 01:28:44 PM PST 24
Peak memory 199552 kb
Host smart-cefe9fe9-1ab7-4413-81a8-4e930d38ab75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015117661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.4015117661
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.4139987928
Short name T52
Test name
Test status
Simulation time 75905230 ps
CPU time 0.8 seconds
Started Jan 14 01:28:41 PM PST 24
Finished Jan 14 01:28:43 PM PST 24
Peak memory 199248 kb
Host smart-68d3cff1-89c7-441e-b018-38d1a29313cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139987928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.4139987928
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.3837498293
Short name T433
Test name
Test status
Simulation time 1897803726 ps
CPU time 7.65 seconds
Started Jan 14 01:28:41 PM PST 24
Finished Jan 14 01:28:49 PM PST 24
Peak memory 217344 kb
Host smart-aabee115-0766-47dd-9cce-2bfa0cb0300d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837498293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.3837498293
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.3104905449
Short name T252
Test name
Test status
Simulation time 245119796 ps
CPU time 1.05 seconds
Started Jan 14 01:28:41 PM PST 24
Finished Jan 14 01:28:43 PM PST 24
Peak memory 216536 kb
Host smart-00765ccf-b245-4a29-913d-abbb635b440b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104905449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.3104905449
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.1560151981
Short name T302
Test name
Test status
Simulation time 217371943 ps
CPU time 0.91 seconds
Started Jan 14 01:28:40 PM PST 24
Finished Jan 14 01:28:42 PM PST 24
Peak memory 199192 kb
Host smart-0ab7ff32-eb33-41d5-b1ec-a1e9ddc2509b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560151981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.1560151981
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.405650158
Short name T88
Test name
Test status
Simulation time 2079748090 ps
CPU time 7.38 seconds
Started Jan 14 01:28:40 PM PST 24
Finished Jan 14 01:28:48 PM PST 24
Peak memory 199580 kb
Host smart-81696a4e-fd01-4c7e-a8f3-3746c9acf1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405650158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.405650158
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.3438599434
Short name T548
Test name
Test status
Simulation time 147407878 ps
CPU time 1.09 seconds
Started Jan 14 01:28:42 PM PST 24
Finished Jan 14 01:28:44 PM PST 24
Peak memory 199272 kb
Host smart-efbc9095-4ca2-48cb-9f88-5a509f42a03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438599434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.3438599434
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.930350491
Short name T293
Test name
Test status
Simulation time 121785532 ps
CPU time 1.2 seconds
Started Jan 14 01:28:41 PM PST 24
Finished Jan 14 01:28:43 PM PST 24
Peak memory 199560 kb
Host smart-12b29b3a-baa8-47b8-8df1-25c5076cce15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930350491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.930350491
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.3932832985
Short name T110
Test name
Test status
Simulation time 8739767809 ps
CPU time 37.52 seconds
Started Jan 14 01:28:39 PM PST 24
Finished Jan 14 01:29:17 PM PST 24
Peak memory 199580 kb
Host smart-f0b73aef-204f-4d7e-998a-3800f7f5c140
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932832985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.3932832985
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.3680780469
Short name T501
Test name
Test status
Simulation time 377949597 ps
CPU time 2.12 seconds
Started Jan 14 01:28:41 PM PST 24
Finished Jan 14 01:28:44 PM PST 24
Peak memory 199288 kb
Host smart-0ae031a5-26b9-441c-bfea-83d4c43f355c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680780469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.3680780469
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.470852547
Short name T258
Test name
Test status
Simulation time 148735424 ps
CPU time 1.08 seconds
Started Jan 14 01:28:39 PM PST 24
Finished Jan 14 01:28:41 PM PST 24
Peak memory 199360 kb
Host smart-1ea09cc8-eb9b-4dc4-956a-614cc7374e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470852547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.470852547
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.2791199444
Short name T404
Test name
Test status
Simulation time 80323145 ps
CPU time 0.76 seconds
Started Jan 14 01:28:48 PM PST 24
Finished Jan 14 01:28:50 PM PST 24
Peak memory 199204 kb
Host smart-76fe4231-4204-46f8-b589-e51515e3d342
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791199444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.2791199444
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.181589561
Short name T297
Test name
Test status
Simulation time 2359924591 ps
CPU time 8.42 seconds
Started Jan 14 01:28:41 PM PST 24
Finished Jan 14 01:28:50 PM PST 24
Peak memory 217424 kb
Host smart-86b52b96-c1ff-4240-82a9-4dc8997e0ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181589561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.181589561
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.2638642824
Short name T478
Test name
Test status
Simulation time 244708992 ps
CPU time 1.07 seconds
Started Jan 14 01:28:41 PM PST 24
Finished Jan 14 01:28:43 PM PST 24
Peak memory 216500 kb
Host smart-71915692-9556-4060-a833-91c9ee629309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638642824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.2638642824
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.2764805888
Short name T458
Test name
Test status
Simulation time 139992605 ps
CPU time 0.8 seconds
Started Jan 14 01:28:41 PM PST 24
Finished Jan 14 01:28:42 PM PST 24
Peak memory 199160 kb
Host smart-0d79c3b3-69d0-4736-b219-5eaf6477438f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764805888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.2764805888
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.4204714391
Short name T593
Test name
Test status
Simulation time 1619497056 ps
CPU time 5.76 seconds
Started Jan 14 01:28:42 PM PST 24
Finished Jan 14 01:28:48 PM PST 24
Peak memory 199516 kb
Host smart-1f128a47-c7a7-470d-9b68-7c33bcae0269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204714391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.4204714391
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.73685505
Short name T145
Test name
Test status
Simulation time 139900777 ps
CPU time 1.06 seconds
Started Jan 14 01:28:41 PM PST 24
Finished Jan 14 01:28:43 PM PST 24
Peak memory 199332 kb
Host smart-9f8a70c0-ab39-4c71-b4e5-64746c7b126b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73685505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.73685505
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.190962643
Short name T322
Test name
Test status
Simulation time 242122977 ps
CPU time 1.38 seconds
Started Jan 14 01:28:47 PM PST 24
Finished Jan 14 01:28:49 PM PST 24
Peak memory 199520 kb
Host smart-15ecb8a5-568f-4e6f-8613-658ebcc34ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190962643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.190962643
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.3873903279
Short name T160
Test name
Test status
Simulation time 2264464794 ps
CPU time 10.8 seconds
Started Jan 14 01:28:48 PM PST 24
Finished Jan 14 01:28:59 PM PST 24
Peak memory 199600 kb
Host smart-5ebc2183-782b-4534-bf13-7de25d287adb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873903279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.3873903279
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.166680117
Short name T340
Test name
Test status
Simulation time 320283424 ps
CPU time 1.95 seconds
Started Jan 14 01:28:41 PM PST 24
Finished Jan 14 01:28:44 PM PST 24
Peak memory 199292 kb
Host smart-238dfb6e-ac9b-46ed-86e5-9eceb6420a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166680117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.166680117
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.2780633063
Short name T2
Test name
Test status
Simulation time 189493993 ps
CPU time 1.28 seconds
Started Jan 14 01:28:47 PM PST 24
Finished Jan 14 01:28:49 PM PST 24
Peak memory 199352 kb
Host smart-0364eb2e-7859-42db-a0a3-a287d4d72c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780633063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.2780633063
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.100949356
Short name T428
Test name
Test status
Simulation time 63576107 ps
CPU time 0.71 seconds
Started Jan 14 01:27:13 PM PST 24
Finished Jan 14 01:27:15 PM PST 24
Peak memory 199196 kb
Host smart-0c5eec0b-3d74-4a92-9adb-88735d636b70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100949356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.100949356
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.1454357943
Short name T500
Test name
Test status
Simulation time 2358165085 ps
CPU time 7.92 seconds
Started Jan 14 01:27:09 PM PST 24
Finished Jan 14 01:27:18 PM PST 24
Peak memory 217140 kb
Host smart-d8012449-bc6c-4033-95cd-050e8824deb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454357943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.1454357943
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.817719901
Short name T426
Test name
Test status
Simulation time 245529175 ps
CPU time 1.02 seconds
Started Jan 14 01:27:09 PM PST 24
Finished Jan 14 01:27:11 PM PST 24
Peak memory 216560 kb
Host smart-35077426-abb5-4771-8e0e-c3cd68eb3bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817719901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.817719901
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.1443841012
Short name T15
Test name
Test status
Simulation time 168064202 ps
CPU time 0.83 seconds
Started Jan 14 01:27:02 PM PST 24
Finished Jan 14 01:27:04 PM PST 24
Peak memory 199116 kb
Host smart-2ed539e9-8d5d-4a20-ba25-a6bf28fb3eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443841012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.1443841012
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.487720822
Short name T486
Test name
Test status
Simulation time 1734134875 ps
CPU time 7.53 seconds
Started Jan 14 01:27:03 PM PST 24
Finished Jan 14 01:27:12 PM PST 24
Peak memory 199552 kb
Host smart-9fb22f78-8d2d-419e-8d07-bd9a12eebdce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487720822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.487720822
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.3734738167
Short name T72
Test name
Test status
Simulation time 8470932143 ps
CPU time 12.52 seconds
Started Jan 14 01:27:13 PM PST 24
Finished Jan 14 01:27:27 PM PST 24
Peak memory 216296 kb
Host smart-5cec2fee-c0cc-4a36-b234-1d55b9cf6035
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734738167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.3734738167
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.1450329800
Short name T508
Test name
Test status
Simulation time 163038883 ps
CPU time 1.19 seconds
Started Jan 14 01:27:08 PM PST 24
Finished Jan 14 01:27:11 PM PST 24
Peak memory 199288 kb
Host smart-6bdf63d0-2900-427f-b068-a9d9eddbb79d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450329800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.1450329800
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.3753970214
Short name T317
Test name
Test status
Simulation time 191280827 ps
CPU time 1.31 seconds
Started Jan 14 01:27:02 PM PST 24
Finished Jan 14 01:27:04 PM PST 24
Peak memory 199484 kb
Host smart-f3762ab3-7857-4df9-8b0d-56f619749691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753970214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.3753970214
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.2075437231
Short name T378
Test name
Test status
Simulation time 4356737978 ps
CPU time 18.19 seconds
Started Jan 14 01:27:09 PM PST 24
Finished Jan 14 01:27:29 PM PST 24
Peak memory 199536 kb
Host smart-60e5bbeb-322e-48d7-b52c-a639535221c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075437231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.2075437231
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.2232324714
Short name T309
Test name
Test status
Simulation time 265150609 ps
CPU time 1.79 seconds
Started Jan 14 01:27:02 PM PST 24
Finished Jan 14 01:27:04 PM PST 24
Peak memory 199368 kb
Host smart-618c6eb1-a74a-43a0-9fa0-e7864567e7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232324714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.2232324714
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.1038239091
Short name T82
Test name
Test status
Simulation time 195489758 ps
CPU time 1.19 seconds
Started Jan 14 01:27:02 PM PST 24
Finished Jan 14 01:27:04 PM PST 24
Peak memory 199364 kb
Host smart-58ff18d7-2b8a-439f-8846-c06d405e50c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038239091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.1038239091
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.2229771258
Short name T344
Test name
Test status
Simulation time 80896941 ps
CPU time 0.76 seconds
Started Jan 14 01:28:49 PM PST 24
Finished Jan 14 01:28:51 PM PST 24
Peak memory 199244 kb
Host smart-5b4af43e-1252-4eed-8ea9-79f892995c01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229771258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.2229771258
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.20451273
Short name T393
Test name
Test status
Simulation time 1890336336 ps
CPU time 7.34 seconds
Started Jan 14 01:28:48 PM PST 24
Finished Jan 14 01:28:56 PM PST 24
Peak memory 221324 kb
Host smart-10feff15-c9b2-4835-893f-5cbd023e8acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20451273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.20451273
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.3619940930
Short name T580
Test name
Test status
Simulation time 244623863 ps
CPU time 1.08 seconds
Started Jan 14 01:28:52 PM PST 24
Finished Jan 14 01:28:54 PM PST 24
Peak memory 216488 kb
Host smart-170e7415-ef05-4ae4-8184-9c14d5caa4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619940930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.3619940930
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.3171119684
Short name T20
Test name
Test status
Simulation time 90740182 ps
CPU time 0.72 seconds
Started Jan 14 01:28:51 PM PST 24
Finished Jan 14 01:28:52 PM PST 24
Peak memory 199260 kb
Host smart-d6b09c2d-c97b-4a65-a22f-6e260ecf7afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171119684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.3171119684
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.169851776
Short name T289
Test name
Test status
Simulation time 1623880097 ps
CPU time 5.75 seconds
Started Jan 14 01:28:49 PM PST 24
Finished Jan 14 01:28:56 PM PST 24
Peak memory 199576 kb
Host smart-7c0468a2-5a9f-40a0-96ba-6484087957fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169851776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.169851776
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.1165516135
Short name T516
Test name
Test status
Simulation time 106609224 ps
CPU time 0.97 seconds
Started Jan 14 01:28:49 PM PST 24
Finished Jan 14 01:28:51 PM PST 24
Peak memory 199464 kb
Host smart-9e7772d3-b375-42d7-8572-cd0e690415cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165516135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.1165516135
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.4087899879
Short name T350
Test name
Test status
Simulation time 221958839 ps
CPU time 1.4 seconds
Started Jan 14 01:28:51 PM PST 24
Finished Jan 14 01:28:53 PM PST 24
Peak memory 199552 kb
Host smart-cab3583a-5f6c-4cf4-bb41-c61603d1e34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087899879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.4087899879
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.4077493907
Short name T276
Test name
Test status
Simulation time 3143513495 ps
CPU time 14.34 seconds
Started Jan 14 01:28:48 PM PST 24
Finished Jan 14 01:29:03 PM PST 24
Peak memory 199628 kb
Host smart-257f32d7-5fea-4e63-91a9-37d7e852972f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077493907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.4077493907
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.4162191994
Short name T454
Test name
Test status
Simulation time 353992249 ps
CPU time 2.26 seconds
Started Jan 14 01:28:52 PM PST 24
Finished Jan 14 01:28:55 PM PST 24
Peak memory 199336 kb
Host smart-f39dae70-ae26-423b-9c5a-a8141bac2fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162191994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.4162191994
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.3910003642
Short name T5
Test name
Test status
Simulation time 240826911 ps
CPU time 1.38 seconds
Started Jan 14 01:28:51 PM PST 24
Finished Jan 14 01:28:53 PM PST 24
Peak memory 199412 kb
Host smart-b33ad71f-7dec-4963-b0df-e745eda70513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910003642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.3910003642
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.1145040669
Short name T372
Test name
Test status
Simulation time 64743193 ps
CPU time 0.72 seconds
Started Jan 14 01:28:49 PM PST 24
Finished Jan 14 01:28:51 PM PST 24
Peak memory 199312 kb
Host smart-443277ea-61f4-4955-8694-adc2a3cd10b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145040669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.1145040669
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.3734395701
Short name T326
Test name
Test status
Simulation time 2174766337 ps
CPU time 7.79 seconds
Started Jan 14 01:28:46 PM PST 24
Finished Jan 14 01:28:54 PM PST 24
Peak memory 216896 kb
Host smart-0dd6e288-64aa-486f-b600-fd3d91c51cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734395701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.3734395701
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.1455563434
Short name T464
Test name
Test status
Simulation time 243914283 ps
CPU time 1.07 seconds
Started Jan 14 01:28:48 PM PST 24
Finished Jan 14 01:28:49 PM PST 24
Peak memory 216496 kb
Host smart-c3bf84ef-e39f-44f1-a570-fe7fe8fb36ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455563434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.1455563434
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.2105584763
Short name T447
Test name
Test status
Simulation time 216858070 ps
CPU time 0.91 seconds
Started Jan 14 01:28:52 PM PST 24
Finished Jan 14 01:28:54 PM PST 24
Peak memory 199204 kb
Host smart-e37fa8b2-b6ea-4d4b-b346-f904935a4ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105584763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.2105584763
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.3005161920
Short name T444
Test name
Test status
Simulation time 1102417700 ps
CPU time 5.14 seconds
Started Jan 14 01:28:49 PM PST 24
Finished Jan 14 01:28:55 PM PST 24
Peak memory 199612 kb
Host smart-e7c012b6-fd24-41ac-a0cb-934aab84faa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005161920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.3005161920
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.855501110
Short name T157
Test name
Test status
Simulation time 96786985 ps
CPU time 0.96 seconds
Started Jan 14 01:28:48 PM PST 24
Finished Jan 14 01:28:50 PM PST 24
Peak memory 199392 kb
Host smart-0d177294-dd95-451c-b538-85f5e4485fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855501110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.855501110
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.665878579
Short name T395
Test name
Test status
Simulation time 112071768 ps
CPU time 1.09 seconds
Started Jan 14 01:28:49 PM PST 24
Finished Jan 14 01:28:51 PM PST 24
Peak memory 199544 kb
Host smart-20684b8a-6b9a-4c65-9129-7d8de24c4872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665878579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.665878579
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.2794520973
Short name T154
Test name
Test status
Simulation time 1024338714 ps
CPU time 5.47 seconds
Started Jan 14 01:28:48 PM PST 24
Finished Jan 14 01:28:54 PM PST 24
Peak memory 199548 kb
Host smart-1f704894-2fa2-4005-a62d-10aff709a30e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794520973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.2794520973
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.2268102485
Short name T331
Test name
Test status
Simulation time 342000671 ps
CPU time 2.19 seconds
Started Jan 14 01:28:47 PM PST 24
Finished Jan 14 01:28:50 PM PST 24
Peak memory 199336 kb
Host smart-48859859-10b1-4621-bb46-7ea5ed834361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268102485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.2268102485
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.34010148
Short name T143
Test name
Test status
Simulation time 90069743 ps
CPU time 0.95 seconds
Started Jan 14 01:28:52 PM PST 24
Finished Jan 14 01:28:54 PM PST 24
Peak memory 199412 kb
Host smart-bdee97d0-2352-46eb-aca7-4194a0729e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34010148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.34010148
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.1180841406
Short name T391
Test name
Test status
Simulation time 66745363 ps
CPU time 0.73 seconds
Started Jan 14 01:29:11 PM PST 24
Finished Jan 14 01:29:14 PM PST 24
Peak memory 199232 kb
Host smart-d26a3858-f80e-45ab-9fbc-870a707472e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180841406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.1180841406
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.674094770
Short name T467
Test name
Test status
Simulation time 1871046492 ps
CPU time 7.72 seconds
Started Jan 14 01:29:06 PM PST 24
Finished Jan 14 01:29:16 PM PST 24
Peak memory 215964 kb
Host smart-a5397103-3199-40c5-8875-d63405b0fb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674094770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.674094770
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.4175088770
Short name T144
Test name
Test status
Simulation time 243576613 ps
CPU time 1.05 seconds
Started Jan 14 01:28:58 PM PST 24
Finished Jan 14 01:28:59 PM PST 24
Peak memory 216668 kb
Host smart-4261f93d-b20f-4923-9bf9-f423a20ca6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175088770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.4175088770
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.2677961798
Short name T330
Test name
Test status
Simulation time 88952804 ps
CPU time 0.75 seconds
Started Jan 14 01:28:59 PM PST 24
Finished Jan 14 01:29:00 PM PST 24
Peak memory 199196 kb
Host smart-fa27875c-03ce-43d1-987a-76f01f89ba2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677961798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.2677961798
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.226315803
Short name T111
Test name
Test status
Simulation time 778665009 ps
CPU time 3.82 seconds
Started Jan 14 01:29:00 PM PST 24
Finished Jan 14 01:29:04 PM PST 24
Peak memory 199536 kb
Host smart-f3cf6934-531b-4859-b862-7150d1c25651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226315803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.226315803
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.2919451541
Short name T547
Test name
Test status
Simulation time 171913783 ps
CPU time 1.11 seconds
Started Jan 14 01:29:03 PM PST 24
Finished Jan 14 01:29:09 PM PST 24
Peak memory 199396 kb
Host smart-cf493588-f2b8-48a3-ae9e-20ff732177c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919451541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.2919451541
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.376985540
Short name T583
Test name
Test status
Simulation time 232653262 ps
CPU time 1.44 seconds
Started Jan 14 01:28:47 PM PST 24
Finished Jan 14 01:28:48 PM PST 24
Peak memory 199528 kb
Host smart-134232e5-8430-420e-9bdc-acdda0f6b3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376985540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.376985540
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.3034795697
Short name T561
Test name
Test status
Simulation time 11105623337 ps
CPU time 39.82 seconds
Started Jan 14 01:29:06 PM PST 24
Finished Jan 14 01:29:48 PM PST 24
Peak memory 199604 kb
Host smart-dfaaffb9-fd88-4d61-916b-4f8865c59036
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034795697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.3034795697
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.2781057056
Short name T412
Test name
Test status
Simulation time 348405647 ps
CPU time 2.15 seconds
Started Jan 14 01:29:03 PM PST 24
Finished Jan 14 01:29:10 PM PST 24
Peak memory 199288 kb
Host smart-d3d8b885-64b8-49dc-859c-57f96914017b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781057056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.2781057056
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.227497746
Short name T495
Test name
Test status
Simulation time 138665399 ps
CPU time 1.11 seconds
Started Jan 14 01:29:10 PM PST 24
Finished Jan 14 01:29:14 PM PST 24
Peak memory 199320 kb
Host smart-b4aee135-5fc0-4eb0-9afc-3c3d1a060943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227497746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.227497746
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.1200752322
Short name T559
Test name
Test status
Simulation time 59495300 ps
CPU time 0.69 seconds
Started Jan 14 01:28:58 PM PST 24
Finished Jan 14 01:28:59 PM PST 24
Peak memory 199224 kb
Host smart-267146e4-4aa8-4d24-8868-bdc0d9090b05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200752322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.1200752322
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.3008532071
Short name T562
Test name
Test status
Simulation time 1229539309 ps
CPU time 5.36 seconds
Started Jan 14 01:28:56 PM PST 24
Finished Jan 14 01:29:02 PM PST 24
Peak memory 221400 kb
Host smart-3e8e70b0-8368-48ca-8705-f67fafdea06c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008532071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.3008532071
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.3826909270
Short name T584
Test name
Test status
Simulation time 243864006 ps
CPU time 1.08 seconds
Started Jan 14 01:28:58 PM PST 24
Finished Jan 14 01:29:00 PM PST 24
Peak memory 216608 kb
Host smart-98d37f13-baba-41c4-82d9-3cd38f1a6f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826909270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.3826909270
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.1559934497
Short name T459
Test name
Test status
Simulation time 203618737 ps
CPU time 0.89 seconds
Started Jan 14 01:28:58 PM PST 24
Finished Jan 14 01:28:59 PM PST 24
Peak memory 199204 kb
Host smart-b8a47959-47f8-4573-ad68-0d2b46273fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559934497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.1559934497
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.1510661124
Short name T437
Test name
Test status
Simulation time 923488725 ps
CPU time 5.09 seconds
Started Jan 14 01:28:57 PM PST 24
Finished Jan 14 01:29:02 PM PST 24
Peak memory 199548 kb
Host smart-fe9c3ae4-b663-4381-9c4e-b88f7e4bfeec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510661124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.1510661124
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.3911918319
Short name T327
Test name
Test status
Simulation time 149742337 ps
CPU time 1.11 seconds
Started Jan 14 01:28:58 PM PST 24
Finished Jan 14 01:29:00 PM PST 24
Peak memory 199336 kb
Host smart-ae5dae55-802b-4fbe-9046-d6d102ba5c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911918319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.3911918319
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.1326495311
Short name T272
Test name
Test status
Simulation time 112415221 ps
CPU time 1.19 seconds
Started Jan 14 01:29:05 PM PST 24
Finished Jan 14 01:29:10 PM PST 24
Peak memory 199424 kb
Host smart-a4081d51-4bda-4f33-afb2-72d10d068c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326495311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.1326495311
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.2453640933
Short name T264
Test name
Test status
Simulation time 1090329785 ps
CPU time 5.11 seconds
Started Jan 14 01:29:03 PM PST 24
Finished Jan 14 01:29:13 PM PST 24
Peak memory 199544 kb
Host smart-98acf280-890d-41ef-8d70-953c21ef2424
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453640933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.2453640933
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.2857354872
Short name T494
Test name
Test status
Simulation time 487460612 ps
CPU time 2.59 seconds
Started Jan 14 01:28:57 PM PST 24
Finished Jan 14 01:29:00 PM PST 24
Peak memory 199308 kb
Host smart-28ae0e88-b44d-4d05-83ee-f22b3c25d538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857354872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.2857354872
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.2573329355
Short name T141
Test name
Test status
Simulation time 76995869 ps
CPU time 0.81 seconds
Started Jan 14 01:29:08 PM PST 24
Finished Jan 14 01:29:11 PM PST 24
Peak memory 199288 kb
Host smart-4b5616d0-6fbf-4532-9b48-8f58ec58a1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573329355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.2573329355
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.4136896344
Short name T535
Test name
Test status
Simulation time 77108701 ps
CPU time 0.74 seconds
Started Jan 14 01:29:10 PM PST 24
Finished Jan 14 01:29:13 PM PST 24
Peak memory 199168 kb
Host smart-13d365a5-337d-44d5-a84b-aa0f10d41865
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136896344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.4136896344
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.2072867078
Short name T59
Test name
Test status
Simulation time 2337457436 ps
CPU time 7.63 seconds
Started Jan 14 01:29:10 PM PST 24
Finished Jan 14 01:29:20 PM PST 24
Peak memory 216752 kb
Host smart-9715ad35-e11c-4f76-a882-331bf25b7f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072867078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.2072867078
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.2895365316
Short name T532
Test name
Test status
Simulation time 246415641 ps
CPU time 1.04 seconds
Started Jan 14 01:28:56 PM PST 24
Finished Jan 14 01:28:57 PM PST 24
Peak memory 216524 kb
Host smart-ff81e88b-45bf-4b70-b53b-1d117c2daf5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895365316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.2895365316
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.438395064
Short name T17
Test name
Test status
Simulation time 169497201 ps
CPU time 0.81 seconds
Started Jan 14 01:29:09 PM PST 24
Finished Jan 14 01:29:13 PM PST 24
Peak memory 199168 kb
Host smart-68f8e0bc-7080-492e-9cd6-c0cd944e90e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438395064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.438395064
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.3884688807
Short name T254
Test name
Test status
Simulation time 818783757 ps
CPU time 3.97 seconds
Started Jan 14 01:29:06 PM PST 24
Finished Jan 14 01:29:12 PM PST 24
Peak memory 199492 kb
Host smart-14c8fcbf-a8fa-4327-a544-e53d32f156da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884688807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.3884688807
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.2742689181
Short name T87
Test name
Test status
Simulation time 148198094 ps
CPU time 1.13 seconds
Started Jan 14 01:29:07 PM PST 24
Finished Jan 14 01:29:10 PM PST 24
Peak memory 199404 kb
Host smart-1344838c-ac59-4f78-a658-562118ce0a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742689181 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.2742689181
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.2651209884
Short name T524
Test name
Test status
Simulation time 258124177 ps
CPU time 1.54 seconds
Started Jan 14 01:28:57 PM PST 24
Finished Jan 14 01:28:59 PM PST 24
Peak memory 199536 kb
Host smart-9fa04012-52dc-4e7f-88cf-a86a5c2c6d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651209884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.2651209884
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.3721992118
Short name T23
Test name
Test status
Simulation time 1727710248 ps
CPU time 8.18 seconds
Started Jan 14 01:29:06 PM PST 24
Finished Jan 14 01:29:17 PM PST 24
Peak memory 199556 kb
Host smart-a876bbb3-1e8e-4334-99cc-76662eae4542
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721992118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.3721992118
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.1179976371
Short name T423
Test name
Test status
Simulation time 550165423 ps
CPU time 2.79 seconds
Started Jan 14 01:29:06 PM PST 24
Finished Jan 14 01:29:11 PM PST 24
Peak memory 199408 kb
Host smart-b35ee93c-f26f-4be3-a4d6-7d255d7f794a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179976371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.1179976371
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.2576406335
Short name T570
Test name
Test status
Simulation time 84442088 ps
CPU time 0.86 seconds
Started Jan 14 01:29:03 PM PST 24
Finished Jan 14 01:29:04 PM PST 24
Peak memory 199308 kb
Host smart-bac70207-82ae-4118-b4a1-01a20371450e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576406335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.2576406335
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.663400458
Short name T510
Test name
Test status
Simulation time 66693464 ps
CPU time 0.75 seconds
Started Jan 14 01:29:10 PM PST 24
Finished Jan 14 01:29:13 PM PST 24
Peak memory 199160 kb
Host smart-c1a6576e-8c4c-4f9e-b3b5-1c7a547fb7d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663400458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.663400458
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.330841983
Short name T303
Test name
Test status
Simulation time 1873582753 ps
CPU time 7.25 seconds
Started Jan 14 01:29:06 PM PST 24
Finished Jan 14 01:29:16 PM PST 24
Peak memory 217352 kb
Host smart-d87299cc-ced8-430e-8bde-1523b2aff0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330841983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.330841983
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.3812085136
Short name T571
Test name
Test status
Simulation time 243567461 ps
CPU time 1.06 seconds
Started Jan 14 01:29:02 PM PST 24
Finished Jan 14 01:29:04 PM PST 24
Peak memory 216532 kb
Host smart-440f9f59-e430-4933-babf-60712fbd3d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812085136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.3812085136
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.1972263900
Short name T382
Test name
Test status
Simulation time 120744375 ps
CPU time 0.77 seconds
Started Jan 14 01:29:05 PM PST 24
Finished Jan 14 01:29:09 PM PST 24
Peak memory 199192 kb
Host smart-d5faadc2-11ef-49e8-b8d4-2ef483c901bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972263900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.1972263900
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.695309195
Short name T307
Test name
Test status
Simulation time 911368060 ps
CPU time 4.36 seconds
Started Jan 14 01:29:09 PM PST 24
Finished Jan 14 01:29:16 PM PST 24
Peak memory 199564 kb
Host smart-80facbbd-8e10-44d1-869a-3e68921ee02b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695309195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.695309195
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.1194328670
Short name T253
Test name
Test status
Simulation time 106869904 ps
CPU time 0.98 seconds
Started Jan 14 01:29:06 PM PST 24
Finished Jan 14 01:29:09 PM PST 24
Peak memory 199364 kb
Host smart-15e1d393-4b73-427e-8801-08fa04ae920c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194328670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.1194328670
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.4264724922
Short name T533
Test name
Test status
Simulation time 118275140 ps
CPU time 1.16 seconds
Started Jan 14 01:29:10 PM PST 24
Finished Jan 14 01:29:14 PM PST 24
Peak memory 199508 kb
Host smart-1ce13c64-c476-4bb5-af13-35d7cc97c71f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264724922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.4264724922
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.3076567218
Short name T24
Test name
Test status
Simulation time 2313683643 ps
CPU time 10.33 seconds
Started Jan 14 01:29:06 PM PST 24
Finished Jan 14 01:29:19 PM PST 24
Peak memory 199624 kb
Host smart-087f0a78-da4b-472a-bf80-99524a9b6112
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076567218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.3076567218
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.2843416563
Short name T469
Test name
Test status
Simulation time 495370744 ps
CPU time 2.69 seconds
Started Jan 14 01:29:06 PM PST 24
Finished Jan 14 01:29:11 PM PST 24
Peak memory 199348 kb
Host smart-9e2f6ead-f5c2-49f8-815d-87fe1c42c930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843416563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.2843416563
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.1569444527
Short name T361
Test name
Test status
Simulation time 167286339 ps
CPU time 1.1 seconds
Started Jan 14 01:29:11 PM PST 24
Finished Jan 14 01:29:14 PM PST 24
Peak memory 199360 kb
Host smart-daefb275-29e7-489e-988f-09e42520bbfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569444527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.1569444527
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.2958840864
Short name T422
Test name
Test status
Simulation time 68703247 ps
CPU time 0.71 seconds
Started Jan 14 01:29:07 PM PST 24
Finished Jan 14 01:29:09 PM PST 24
Peak memory 199308 kb
Host smart-708a9c2d-d8b6-486f-8bf4-f345f3e53bff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958840864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.2958840864
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.816209437
Short name T33
Test name
Test status
Simulation time 2368832812 ps
CPU time 7.99 seconds
Started Jan 14 01:29:09 PM PST 24
Finished Jan 14 01:29:20 PM PST 24
Peak memory 218196 kb
Host smart-fa8e9ee7-5a39-4de3-921e-5d9853ac2434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816209437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.816209437
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.112634006
Short name T290
Test name
Test status
Simulation time 243737888 ps
CPU time 1.01 seconds
Started Jan 14 01:29:05 PM PST 24
Finished Jan 14 01:29:09 PM PST 24
Peak memory 216564 kb
Host smart-8cb73028-889e-407e-8756-622ff853fbce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112634006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.112634006
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.2541382704
Short name T351
Test name
Test status
Simulation time 189984828 ps
CPU time 0.91 seconds
Started Jan 14 01:29:14 PM PST 24
Finished Jan 14 01:29:16 PM PST 24
Peak memory 199192 kb
Host smart-9af49c11-5424-468b-98f9-399e9f29b6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541382704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.2541382704
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.4292961170
Short name T554
Test name
Test status
Simulation time 959797297 ps
CPU time 4.32 seconds
Started Jan 14 01:29:13 PM PST 24
Finished Jan 14 01:29:18 PM PST 24
Peak memory 199556 kb
Host smart-9a458f91-2276-49e2-83fb-18919ea6c169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292961170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.4292961170
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.4115780053
Short name T371
Test name
Test status
Simulation time 171743722 ps
CPU time 1.27 seconds
Started Jan 14 01:29:05 PM PST 24
Finished Jan 14 01:29:10 PM PST 24
Peak memory 199356 kb
Host smart-9e6af6a9-fd52-4f95-a632-6a77beaf8a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115780053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.4115780053
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.2770448085
Short name T282
Test name
Test status
Simulation time 200410888 ps
CPU time 1.46 seconds
Started Jan 14 01:29:10 PM PST 24
Finished Jan 14 01:29:14 PM PST 24
Peak memory 199552 kb
Host smart-b9afe031-368a-4f95-bbd7-1c5e7efbf490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770448085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.2770448085
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.1513335466
Short name T461
Test name
Test status
Simulation time 5504831787 ps
CPU time 24.11 seconds
Started Jan 14 01:29:11 PM PST 24
Finished Jan 14 01:29:37 PM PST 24
Peak memory 199680 kb
Host smart-2c6ffec2-f256-4fe5-8da7-5d5212937481
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513335466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.1513335466
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.2384492403
Short name T280
Test name
Test status
Simulation time 515537665 ps
CPU time 2.54 seconds
Started Jan 14 01:29:10 PM PST 24
Finished Jan 14 01:29:15 PM PST 24
Peak memory 199296 kb
Host smart-2aa415de-13c8-4dad-a8ce-e78ef1113b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384492403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.2384492403
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.2653702118
Short name T538
Test name
Test status
Simulation time 171330754 ps
CPU time 1.24 seconds
Started Jan 14 01:29:13 PM PST 24
Finished Jan 14 01:29:15 PM PST 24
Peak memory 199560 kb
Host smart-f742ddeb-1cc4-43fb-a15c-ddfe28c43af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653702118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.2653702118
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.1724101723
Short name T247
Test name
Test status
Simulation time 268324833 ps
CPU time 1.14 seconds
Started Jan 14 01:29:06 PM PST 24
Finished Jan 14 01:29:10 PM PST 24
Peak memory 199256 kb
Host smart-9d0981d7-8486-4f82-8487-dd620fa15265
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724101723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.1724101723
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.1227796285
Short name T35
Test name
Test status
Simulation time 2345708157 ps
CPU time 8.55 seconds
Started Jan 14 01:29:08 PM PST 24
Finished Jan 14 01:29:18 PM PST 24
Peak memory 217080 kb
Host smart-590bd71a-bf5c-4b3b-b2fa-d71f8b2d93b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227796285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.1227796285
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.4182735185
Short name T260
Test name
Test status
Simulation time 243582554 ps
CPU time 1.05 seconds
Started Jan 14 01:29:07 PM PST 24
Finished Jan 14 01:29:09 PM PST 24
Peak memory 216624 kb
Host smart-38583990-ac4f-4156-904a-13965d8a7323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182735185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.4182735185
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.1760898268
Short name T545
Test name
Test status
Simulation time 86941500 ps
CPU time 0.73 seconds
Started Jan 14 01:29:10 PM PST 24
Finished Jan 14 01:29:14 PM PST 24
Peak memory 199152 kb
Host smart-81b01896-4272-4ddd-b94f-766132b3c765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760898268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.1760898268
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.2612135288
Short name T536
Test name
Test status
Simulation time 1910536672 ps
CPU time 7.01 seconds
Started Jan 14 01:29:08 PM PST 24
Finished Jan 14 01:29:17 PM PST 24
Peak memory 199460 kb
Host smart-770b352e-f7d1-4e7a-af6d-46b19d17b87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612135288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.2612135288
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.342554541
Short name T151
Test name
Test status
Simulation time 140323793 ps
CPU time 1.05 seconds
Started Jan 14 01:29:12 PM PST 24
Finished Jan 14 01:29:14 PM PST 24
Peak memory 199420 kb
Host smart-a75bf796-072f-4788-ab6c-eb035216dda8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342554541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.342554541
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.468957662
Short name T271
Test name
Test status
Simulation time 256290754 ps
CPU time 1.53 seconds
Started Jan 14 01:29:15 PM PST 24
Finished Jan 14 01:29:17 PM PST 24
Peak memory 199568 kb
Host smart-02ac781e-2bde-4736-8048-833943c43903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468957662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.468957662
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.1240593048
Short name T57
Test name
Test status
Simulation time 7900593361 ps
CPU time 28.3 seconds
Started Jan 14 01:29:09 PM PST 24
Finished Jan 14 01:29:40 PM PST 24
Peak memory 199624 kb
Host smart-5fe5b5b1-c115-446b-a23e-6e95a5d0cb9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240593048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.1240593048
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.2641733803
Short name T296
Test name
Test status
Simulation time 392693508 ps
CPU time 2.19 seconds
Started Jan 14 01:29:10 PM PST 24
Finished Jan 14 01:29:15 PM PST 24
Peak memory 199352 kb
Host smart-1665d30f-40d8-4f88-8c6d-3dfc45d168ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641733803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.2641733803
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.2154452127
Short name T367
Test name
Test status
Simulation time 103539718 ps
CPU time 0.96 seconds
Started Jan 14 01:29:12 PM PST 24
Finished Jan 14 01:29:14 PM PST 24
Peak memory 199416 kb
Host smart-a1842e2e-e052-4180-a98a-19cf21bf5850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154452127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.2154452127
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.440952460
Short name T517
Test name
Test status
Simulation time 78657303 ps
CPU time 0.74 seconds
Started Jan 14 01:29:08 PM PST 24
Finished Jan 14 01:29:11 PM PST 24
Peak memory 199196 kb
Host smart-613c03e5-2fea-408a-9b43-4746c694c063
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440952460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.440952460
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.2066537239
Short name T261
Test name
Test status
Simulation time 244487738 ps
CPU time 1.07 seconds
Started Jan 14 01:29:10 PM PST 24
Finished Jan 14 01:29:14 PM PST 24
Peak memory 216512 kb
Host smart-9c5f5bf8-69c6-4344-a73a-6ca637503763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066537239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.2066537239
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.566174741
Short name T466
Test name
Test status
Simulation time 170413822 ps
CPU time 0.8 seconds
Started Jan 14 01:29:11 PM PST 24
Finished Jan 14 01:29:14 PM PST 24
Peak memory 199208 kb
Host smart-4cc56fe9-af54-4183-87fe-d93050858883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566174741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.566174741
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.3978998641
Short name T515
Test name
Test status
Simulation time 800456102 ps
CPU time 4.11 seconds
Started Jan 14 01:29:10 PM PST 24
Finished Jan 14 01:29:17 PM PST 24
Peak memory 199504 kb
Host smart-ec1b55bc-77f4-43c9-9886-757662a7b6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978998641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.3978998641
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.1931293893
Short name T480
Test name
Test status
Simulation time 180658933 ps
CPU time 1.12 seconds
Started Jan 14 01:29:11 PM PST 24
Finished Jan 14 01:29:14 PM PST 24
Peak memory 199384 kb
Host smart-8282a496-f909-4f74-97ac-28d1c511b6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931293893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.1931293893
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.3147840875
Short name T298
Test name
Test status
Simulation time 190524859 ps
CPU time 1.31 seconds
Started Jan 14 01:29:12 PM PST 24
Finished Jan 14 01:29:14 PM PST 24
Peak memory 199548 kb
Host smart-3fe331d2-effb-4304-aa94-ce818b85a549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147840875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.3147840875
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.1764556080
Short name T149
Test name
Test status
Simulation time 821213008 ps
CPU time 4.26 seconds
Started Jan 14 01:29:08 PM PST 24
Finished Jan 14 01:29:15 PM PST 24
Peak memory 199556 kb
Host smart-852cfa0c-c1df-4d5d-8dcb-413287840305
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764556080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.1764556080
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.2981917706
Short name T354
Test name
Test status
Simulation time 112332760 ps
CPU time 1.35 seconds
Started Jan 14 01:29:12 PM PST 24
Finished Jan 14 01:29:15 PM PST 24
Peak memory 199372 kb
Host smart-1a805d94-0a01-48c5-b63e-866888bc8670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981917706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.2981917706
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.3550881756
Short name T48
Test name
Test status
Simulation time 106783261 ps
CPU time 0.96 seconds
Started Jan 14 01:29:14 PM PST 24
Finished Jan 14 01:29:16 PM PST 24
Peak memory 199396 kb
Host smart-bca409a1-0671-43e2-ac74-22fbc4d9d4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550881756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.3550881756
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.1946520731
Short name T530
Test name
Test status
Simulation time 67322813 ps
CPU time 0.72 seconds
Started Jan 14 01:29:14 PM PST 24
Finished Jan 14 01:29:15 PM PST 24
Peak memory 199248 kb
Host smart-65999d22-6738-43d5-808b-68c2d61afadf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946520731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.1946520731
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.4218014293
Short name T41
Test name
Test status
Simulation time 1221670234 ps
CPU time 6.06 seconds
Started Jan 14 01:29:16 PM PST 24
Finished Jan 14 01:29:23 PM PST 24
Peak memory 220968 kb
Host smart-eca8e56d-f8c5-4178-9973-77570a2ca278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218014293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.4218014293
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.2521847253
Short name T12
Test name
Test status
Simulation time 244695881 ps
CPU time 1.03 seconds
Started Jan 14 01:29:20 PM PST 24
Finished Jan 14 01:29:22 PM PST 24
Peak memory 216584 kb
Host smart-ce902da9-fc67-4249-914f-f1287e9ae502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521847253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.2521847253
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.1747493196
Short name T353
Test name
Test status
Simulation time 74862175 ps
CPU time 0.69 seconds
Started Jan 14 01:29:11 PM PST 24
Finished Jan 14 01:29:14 PM PST 24
Peak memory 199208 kb
Host smart-545b1d40-5b15-4ac9-b627-1d2299a0510e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747493196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.1747493196
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.1381296079
Short name T479
Test name
Test status
Simulation time 1023446637 ps
CPU time 4.74 seconds
Started Jan 14 01:29:51 PM PST 24
Finished Jan 14 01:29:57 PM PST 24
Peak memory 199508 kb
Host smart-d62f9005-bca3-48cf-a3d0-266008c40520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381296079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.1381296079
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.3085940458
Short name T574
Test name
Test status
Simulation time 172190479 ps
CPU time 1.11 seconds
Started Jan 14 01:29:17 PM PST 24
Finished Jan 14 01:29:19 PM PST 24
Peak memory 199304 kb
Host smart-48d48fe6-ac13-4d27-9b46-fe1ddeae8ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085940458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.3085940458
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.1926505756
Short name T542
Test name
Test status
Simulation time 255940782 ps
CPU time 1.4 seconds
Started Jan 14 01:29:10 PM PST 24
Finished Jan 14 01:29:14 PM PST 24
Peak memory 199536 kb
Host smart-54d4b70a-a025-436a-ad78-5186e165b70b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926505756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.1926505756
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.2921507600
Short name T474
Test name
Test status
Simulation time 2135789931 ps
CPU time 7.96 seconds
Started Jan 14 01:29:16 PM PST 24
Finished Jan 14 01:29:24 PM PST 24
Peak memory 199588 kb
Host smart-daa41d46-306d-4736-beb0-7899f5677ad5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921507600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.2921507600
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.3671700805
Short name T509
Test name
Test status
Simulation time 120194239 ps
CPU time 1.5 seconds
Started Jan 14 01:29:17 PM PST 24
Finished Jan 14 01:29:20 PM PST 24
Peak memory 199348 kb
Host smart-5f95a364-7af1-4fe8-b054-b63703b172d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671700805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.3671700805
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.3017947744
Short name T349
Test name
Test status
Simulation time 87988122 ps
CPU time 0.77 seconds
Started Jan 14 01:29:16 PM PST 24
Finished Jan 14 01:29:17 PM PST 24
Peak memory 199376 kb
Host smart-7fa85ae2-91f8-4e09-a0a9-fa9034dd0668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017947744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.3017947744
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.45160280
Short name T441
Test name
Test status
Simulation time 108453694 ps
CPU time 0.85 seconds
Started Jan 14 01:27:26 PM PST 24
Finished Jan 14 01:27:28 PM PST 24
Peak memory 199196 kb
Host smart-bd2bb9e2-6bb6-4efc-a2a4-596389b11301
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45160280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.45160280
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.932781637
Short name T563
Test name
Test status
Simulation time 1223913929 ps
CPU time 5.36 seconds
Started Jan 14 01:27:24 PM PST 24
Finished Jan 14 01:27:31 PM PST 24
Peak memory 220368 kb
Host smart-b6726803-ffaf-4f9a-9886-39addcfde024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932781637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.932781637
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.2849028955
Short name T445
Test name
Test status
Simulation time 244123397 ps
CPU time 1.12 seconds
Started Jan 14 01:27:27 PM PST 24
Finished Jan 14 01:27:29 PM PST 24
Peak memory 216652 kb
Host smart-dcc84ea8-1b68-4c87-bb8f-95a7611379c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849028955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.2849028955
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.3213296161
Short name T288
Test name
Test status
Simulation time 179375247 ps
CPU time 0.84 seconds
Started Jan 14 01:27:16 PM PST 24
Finished Jan 14 01:27:18 PM PST 24
Peak memory 199192 kb
Host smart-2067371a-9757-47d3-92b2-8187202bf5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213296161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.3213296161
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.986506860
Short name T11
Test name
Test status
Simulation time 1551419178 ps
CPU time 6.53 seconds
Started Jan 14 01:27:17 PM PST 24
Finished Jan 14 01:27:28 PM PST 24
Peak memory 199528 kb
Host smart-d559d45a-2cb1-4003-b5c9-130e361df9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986506860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.986506860
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.3740115985
Short name T78
Test name
Test status
Simulation time 16628170826 ps
CPU time 25.05 seconds
Started Jan 14 01:27:25 PM PST 24
Finished Jan 14 01:27:50 PM PST 24
Peak memory 217376 kb
Host smart-f8a9fdad-2cae-457c-b37c-56896800bf10
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740115985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.3740115985
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.3472509892
Short name T263
Test name
Test status
Simulation time 98105880 ps
CPU time 0.96 seconds
Started Jan 14 01:27:25 PM PST 24
Finished Jan 14 01:27:27 PM PST 24
Peak memory 199408 kb
Host smart-11ab613d-84b0-4f69-a079-4739627749b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472509892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.3472509892
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.1440128176
Short name T363
Test name
Test status
Simulation time 191481661 ps
CPU time 1.35 seconds
Started Jan 14 01:27:08 PM PST 24
Finished Jan 14 01:27:11 PM PST 24
Peak memory 199560 kb
Host smart-e568b637-f20c-4b3d-b9b2-d713620de2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440128176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.1440128176
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.3297272283
Short name T112
Test name
Test status
Simulation time 2349877608 ps
CPU time 10.62 seconds
Started Jan 14 01:27:32 PM PST 24
Finished Jan 14 01:27:43 PM PST 24
Peak memory 199604 kb
Host smart-19ec43ae-4428-4459-95aa-22889f4154c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297272283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.3297272283
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.504218084
Short name T54
Test name
Test status
Simulation time 364831116 ps
CPU time 2.28 seconds
Started Jan 14 01:27:15 PM PST 24
Finished Jan 14 01:27:18 PM PST 24
Peak memory 199312 kb
Host smart-8e9f9084-010d-45e8-b3c7-4f6577e9e2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504218084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.504218084
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.1062622919
Short name T91
Test name
Test status
Simulation time 148371182 ps
CPU time 1.16 seconds
Started Jan 14 01:27:17 PM PST 24
Finished Jan 14 01:27:22 PM PST 24
Peak memory 199360 kb
Host smart-a41b34be-0f94-4b8f-96c6-76d0c04789ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062622919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.1062622919
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.1071861918
Short name T379
Test name
Test status
Simulation time 72410043 ps
CPU time 0.83 seconds
Started Jan 14 01:29:17 PM PST 24
Finished Jan 14 01:29:19 PM PST 24
Peak memory 199212 kb
Host smart-98f15e80-34e1-4be5-84b7-1dec7527bf19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071861918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.1071861918
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.526956332
Short name T28
Test name
Test status
Simulation time 1236881228 ps
CPU time 5.48 seconds
Started Jan 14 01:29:17 PM PST 24
Finished Jan 14 01:29:23 PM PST 24
Peak memory 216808 kb
Host smart-51b93e4d-0c35-49ed-9c78-185f5404a13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526956332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.526956332
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.2513355744
Short name T602
Test name
Test status
Simulation time 247246073 ps
CPU time 1.1 seconds
Started Jan 14 01:29:17 PM PST 24
Finished Jan 14 01:29:19 PM PST 24
Peak memory 216612 kb
Host smart-4f29efcc-8440-4188-9503-53519f28c4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513355744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.2513355744
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.2772708245
Short name T278
Test name
Test status
Simulation time 216611557 ps
CPU time 1.03 seconds
Started Jan 14 01:29:21 PM PST 24
Finished Jan 14 01:29:23 PM PST 24
Peak memory 199140 kb
Host smart-b40280b0-76fe-4a08-92ad-5a72cf3b0b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772708245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.2772708245
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.1008103297
Short name T319
Test name
Test status
Simulation time 1993680878 ps
CPU time 8.16 seconds
Started Jan 14 01:29:15 PM PST 24
Finished Jan 14 01:29:24 PM PST 24
Peak memory 199512 kb
Host smart-a3148f50-59f0-40c7-8f1f-dcc8aacdcb3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008103297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.1008103297
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.3334149768
Short name T463
Test name
Test status
Simulation time 107399369 ps
CPU time 1 seconds
Started Jan 14 01:29:20 PM PST 24
Finished Jan 14 01:29:22 PM PST 24
Peak memory 199408 kb
Host smart-d1bafb8c-cec0-4b3d-838c-10b816493aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334149768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.3334149768
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.4235275627
Short name T483
Test name
Test status
Simulation time 122789573 ps
CPU time 1.23 seconds
Started Jan 14 01:29:18 PM PST 24
Finished Jan 14 01:29:20 PM PST 24
Peak memory 199552 kb
Host smart-4fc57af8-e9b6-4782-85de-4feead847bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235275627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.4235275627
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.2834405025
Short name T320
Test name
Test status
Simulation time 8100721974 ps
CPU time 28.66 seconds
Started Jan 14 01:29:16 PM PST 24
Finished Jan 14 01:29:46 PM PST 24
Peak memory 199596 kb
Host smart-986ab6b1-3d20-40c0-a528-d1d885ef8fc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834405025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.2834405025
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.3711561658
Short name T503
Test name
Test status
Simulation time 469405191 ps
CPU time 2.46 seconds
Started Jan 14 01:29:15 PM PST 24
Finished Jan 14 01:29:18 PM PST 24
Peak memory 199332 kb
Host smart-b886770a-704b-485f-80ea-c46ea841cdd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711561658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.3711561658
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.3800640843
Short name T394
Test name
Test status
Simulation time 66938971 ps
CPU time 0.73 seconds
Started Jan 14 01:29:21 PM PST 24
Finished Jan 14 01:29:23 PM PST 24
Peak memory 199344 kb
Host smart-906cf153-d414-4e71-998b-438f81f58ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800640843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.3800640843
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.1567985261
Short name T413
Test name
Test status
Simulation time 65771598 ps
CPU time 0.76 seconds
Started Jan 14 01:29:27 PM PST 24
Finished Jan 14 01:29:31 PM PST 24
Peak memory 199232 kb
Host smart-8551669f-f26c-44d7-bb63-e37b5e9077e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567985261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.1567985261
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.2446303222
Short name T58
Test name
Test status
Simulation time 1911469699 ps
CPU time 6.85 seconds
Started Jan 14 01:29:27 PM PST 24
Finished Jan 14 01:29:37 PM PST 24
Peak memory 220304 kb
Host smart-8825bcaf-b8da-4598-9dca-373bb730601a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446303222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.2446303222
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.1316813256
Short name T266
Test name
Test status
Simulation time 244374000 ps
CPU time 1.08 seconds
Started Jan 14 01:29:23 PM PST 24
Finished Jan 14 01:29:25 PM PST 24
Peak memory 216648 kb
Host smart-5f1d6b9c-4590-4ddd-aaa0-987c6f6748e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316813256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.1316813256
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.2672930679
Short name T301
Test name
Test status
Simulation time 139702758 ps
CPU time 0.84 seconds
Started Jan 14 01:29:16 PM PST 24
Finished Jan 14 01:29:18 PM PST 24
Peak memory 199192 kb
Host smart-f7b0a49b-a79c-4b5d-8ce8-0004a00c835d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672930679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.2672930679
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.782841158
Short name T321
Test name
Test status
Simulation time 1514292581 ps
CPU time 5.97 seconds
Started Jan 14 01:29:17 PM PST 24
Finished Jan 14 01:29:24 PM PST 24
Peak memory 199444 kb
Host smart-551b85c8-eddb-43ce-9184-f8f52c830681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782841158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.782841158
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.96823277
Short name T601
Test name
Test status
Simulation time 171029855 ps
CPU time 1.1 seconds
Started Jan 14 01:29:23 PM PST 24
Finished Jan 14 01:29:25 PM PST 24
Peak memory 199388 kb
Host smart-d9cfa413-8b68-4981-8a8c-050c76d4f32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96823277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.96823277
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.1016006151
Short name T246
Test name
Test status
Simulation time 196357322 ps
CPU time 1.31 seconds
Started Jan 14 01:29:19 PM PST 24
Finished Jan 14 01:29:21 PM PST 24
Peak memory 199544 kb
Host smart-3ff8c14c-fa19-4e67-b921-a6d87b202b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016006151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.1016006151
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.110932736
Short name T578
Test name
Test status
Simulation time 9423681830 ps
CPU time 34.66 seconds
Started Jan 14 01:29:26 PM PST 24
Finished Jan 14 01:30:05 PM PST 24
Peak memory 199536 kb
Host smart-20f1f2ec-7606-4c40-8151-80ab9c6c84d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110932736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.110932736
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.790980711
Short name T572
Test name
Test status
Simulation time 545067528 ps
CPU time 2.87 seconds
Started Jan 14 01:29:23 PM PST 24
Finished Jan 14 01:29:27 PM PST 24
Peak memory 199228 kb
Host smart-248e13b2-fa71-4dee-b796-c7399a664504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790980711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.790980711
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.2466419312
Short name T455
Test name
Test status
Simulation time 89397430 ps
CPU time 0.83 seconds
Started Jan 14 01:29:25 PM PST 24
Finished Jan 14 01:29:31 PM PST 24
Peak memory 199408 kb
Host smart-0a5fef36-1e00-4796-ad6d-a48fc44df267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466419312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.2466419312
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.946718782
Short name T346
Test name
Test status
Simulation time 65290300 ps
CPU time 0.73 seconds
Started Jan 14 01:29:26 PM PST 24
Finished Jan 14 01:29:31 PM PST 24
Peak memory 199180 kb
Host smart-a70f6663-1d13-41e0-8923-cd4cefe682ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946718782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.946718782
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.4712223
Short name T406
Test name
Test status
Simulation time 244196951 ps
CPU time 1.24 seconds
Started Jan 14 01:29:26 PM PST 24
Finished Jan 14 01:29:31 PM PST 24
Peak memory 216660 kb
Host smart-2f9bc884-c32b-4b8e-8980-357d063ddc3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4712223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.4712223
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.1870807615
Short name T519
Test name
Test status
Simulation time 151907791 ps
CPU time 0.84 seconds
Started Jan 14 01:29:29 PM PST 24
Finished Jan 14 01:29:34 PM PST 24
Peak memory 199116 kb
Host smart-41861b8b-fbd3-493a-b6ae-5af7a1a1dc5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870807615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.1870807615
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.4002810200
Short name T8
Test name
Test status
Simulation time 919835425 ps
CPU time 5.17 seconds
Started Jan 14 01:29:25 PM PST 24
Finished Jan 14 01:29:35 PM PST 24
Peak memory 199556 kb
Host smart-f1e7d9ff-a6da-49eb-9ef8-848a6ea55c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002810200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.4002810200
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.1868196167
Short name T81
Test name
Test status
Simulation time 105403674 ps
CPU time 0.95 seconds
Started Jan 14 01:29:26 PM PST 24
Finished Jan 14 01:29:31 PM PST 24
Peak memory 199332 kb
Host smart-89f3a5c2-46a9-4da4-b801-e336fc0ed854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868196167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.1868196167
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.1097226773
Short name T92
Test name
Test status
Simulation time 195037422 ps
CPU time 1.35 seconds
Started Jan 14 01:29:23 PM PST 24
Finished Jan 14 01:29:26 PM PST 24
Peak memory 199556 kb
Host smart-2ce09037-a8c5-4946-abe9-9b5044e4a638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097226773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.1097226773
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.1310310433
Short name T93
Test name
Test status
Simulation time 128453811 ps
CPU time 1.17 seconds
Started Jan 14 01:29:29 PM PST 24
Finished Jan 14 01:29:31 PM PST 24
Peak memory 199116 kb
Host smart-86b5b52e-aa01-4339-bbb2-6b59eef102a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310310433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.1310310433
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.3967298335
Short name T558
Test name
Test status
Simulation time 119533025 ps
CPU time 1.36 seconds
Started Jan 14 01:29:23 PM PST 24
Finished Jan 14 01:29:25 PM PST 24
Peak memory 199360 kb
Host smart-febc1878-cc67-402b-afde-9fb1a10a7e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967298335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.3967298335
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.3892429359
Short name T440
Test name
Test status
Simulation time 133856797 ps
CPU time 0.98 seconds
Started Jan 14 01:29:27 PM PST 24
Finished Jan 14 01:29:31 PM PST 24
Peak memory 199436 kb
Host smart-8dbc7454-9eee-4de9-8037-f5e213a83763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892429359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.3892429359
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.28749215
Short name T430
Test name
Test status
Simulation time 81288846 ps
CPU time 0.84 seconds
Started Jan 14 01:29:31 PM PST 24
Finished Jan 14 01:29:38 PM PST 24
Peak memory 199224 kb
Host smart-5805d92a-6c63-410f-b839-dbeb2fd035ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28749215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.28749215
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.44947512
Short name T373
Test name
Test status
Simulation time 1228825537 ps
CPU time 5.66 seconds
Started Jan 14 01:29:26 PM PST 24
Finished Jan 14 01:29:36 PM PST 24
Peak memory 216840 kb
Host smart-5b4405b4-b437-497f-a350-c4ab7bd72166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44947512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.44947512
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.892309921
Short name T161
Test name
Test status
Simulation time 243909276 ps
CPU time 1.15 seconds
Started Jan 14 01:29:27 PM PST 24
Finished Jan 14 01:29:31 PM PST 24
Peak memory 216608 kb
Host smart-85f7d867-a0bb-4571-909b-03f612ab19a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892309921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.892309921
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.3349141099
Short name T13
Test name
Test status
Simulation time 180119489 ps
CPU time 0.8 seconds
Started Jan 14 01:29:33 PM PST 24
Finished Jan 14 01:29:38 PM PST 24
Peak memory 199196 kb
Host smart-f9544a2f-c09f-4f94-9c5e-da9ae8133540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349141099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.3349141099
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.3850916349
Short name T1
Test name
Test status
Simulation time 1407210098 ps
CPU time 6.48 seconds
Started Jan 14 01:29:24 PM PST 24
Finished Jan 14 01:29:36 PM PST 24
Peak memory 199536 kb
Host smart-511d8772-d63c-4751-a87a-5288321fec84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850916349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.3850916349
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.1719636228
Short name T251
Test name
Test status
Simulation time 145653840 ps
CPU time 1.12 seconds
Started Jan 14 01:29:27 PM PST 24
Finished Jan 14 01:29:31 PM PST 24
Peak memory 199404 kb
Host smart-91505d98-855c-4ec6-b5d8-135c74f386b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719636228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.1719636228
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.4242135561
Short name T452
Test name
Test status
Simulation time 124661158 ps
CPU time 1.21 seconds
Started Jan 14 01:29:29 PM PST 24
Finished Jan 14 01:29:32 PM PST 24
Peak memory 199560 kb
Host smart-cf3ca07c-61f3-4208-8ba5-4bc284c49b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242135561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.4242135561
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.4084460600
Short name T377
Test name
Test status
Simulation time 16820781558 ps
CPU time 60.14 seconds
Started Jan 14 01:29:29 PM PST 24
Finished Jan 14 01:30:30 PM PST 24
Peak memory 199540 kb
Host smart-e38d318e-cfd3-4e13-866c-82402733dc42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084460600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.4084460600
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.3197446990
Short name T400
Test name
Test status
Simulation time 373987075 ps
CPU time 2.26 seconds
Started Jan 14 01:29:28 PM PST 24
Finished Jan 14 01:29:32 PM PST 24
Peak memory 199324 kb
Host smart-547ad627-d700-4116-b2d9-b77a53944864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197446990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.3197446990
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.238602776
Short name T380
Test name
Test status
Simulation time 105541512 ps
CPU time 0.87 seconds
Started Jan 14 01:29:30 PM PST 24
Finished Jan 14 01:29:34 PM PST 24
Peak memory 199360 kb
Host smart-5c8e4777-2bed-4f49-b53a-917313689d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238602776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.238602776
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.2061251263
Short name T475
Test name
Test status
Simulation time 79607242 ps
CPU time 0.77 seconds
Started Jan 14 01:29:43 PM PST 24
Finished Jan 14 01:29:44 PM PST 24
Peak memory 199212 kb
Host smart-2271b563-b125-45c3-9322-469eef443994
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061251263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.2061251263
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.1940450412
Short name T566
Test name
Test status
Simulation time 1911744620 ps
CPU time 7.01 seconds
Started Jan 14 01:29:34 PM PST 24
Finished Jan 14 01:29:45 PM PST 24
Peak memory 221416 kb
Host smart-60094ac7-2510-45f2-b5cd-3d1fe7a99f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940450412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.1940450412
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.511744725
Short name T410
Test name
Test status
Simulation time 244657737 ps
CPU time 1.1 seconds
Started Jan 14 01:29:32 PM PST 24
Finished Jan 14 01:29:39 PM PST 24
Peak memory 216592 kb
Host smart-20d4013d-f62b-472e-98e9-41d5cea93a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511744725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.511744725
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.3570651066
Short name T369
Test name
Test status
Simulation time 211650795 ps
CPU time 0.89 seconds
Started Jan 14 01:29:32 PM PST 24
Finished Jan 14 01:29:38 PM PST 24
Peak memory 199188 kb
Host smart-5f07a48d-6b65-4192-9cf0-7138e09e50bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570651066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.3570651066
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.2939396504
Short name T451
Test name
Test status
Simulation time 1926414908 ps
CPU time 6.93 seconds
Started Jan 14 01:29:29 PM PST 24
Finished Jan 14 01:29:39 PM PST 24
Peak memory 199484 kb
Host smart-bd1d8faa-7187-4b38-9407-85c1724bf23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939396504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.2939396504
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.264262766
Short name T540
Test name
Test status
Simulation time 138081795 ps
CPU time 1.02 seconds
Started Jan 14 01:29:29 PM PST 24
Finished Jan 14 01:29:33 PM PST 24
Peak memory 199384 kb
Host smart-192b7f2f-cb74-43cb-ae38-df0ac7cd4c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264262766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.264262766
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.326141192
Short name T343
Test name
Test status
Simulation time 118481811 ps
CPU time 1.26 seconds
Started Jan 14 01:29:31 PM PST 24
Finished Jan 14 01:29:38 PM PST 24
Peak memory 199560 kb
Host smart-1be002f8-af69-4380-ae63-0f1f80cae84e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326141192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.326141192
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.1699967578
Short name T434
Test name
Test status
Simulation time 11991712381 ps
CPU time 45.85 seconds
Started Jan 14 01:29:31 PM PST 24
Finished Jan 14 01:30:23 PM PST 24
Peak memory 199616 kb
Host smart-42bac7c5-f0d5-42e9-86db-4c0d25a2f8d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699967578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.1699967578
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.4208330994
Short name T599
Test name
Test status
Simulation time 366028230 ps
CPU time 2.49 seconds
Started Jan 14 01:29:30 PM PST 24
Finished Jan 14 01:29:36 PM PST 24
Peak memory 199348 kb
Host smart-6223a1cc-9269-4d17-8989-a9c2d1f9a93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208330994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.4208330994
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.2381228874
Short name T611
Test name
Test status
Simulation time 117246946 ps
CPU time 0.99 seconds
Started Jan 14 01:29:34 PM PST 24
Finished Jan 14 01:29:39 PM PST 24
Peak memory 199396 kb
Host smart-15418052-db8a-4b44-b2da-fa99f5748903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381228874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.2381228874
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.999607659
Short name T355
Test name
Test status
Simulation time 71739462 ps
CPU time 0.76 seconds
Started Jan 14 01:29:44 PM PST 24
Finished Jan 14 01:29:46 PM PST 24
Peak memory 199204 kb
Host smart-0533fbbd-2199-4c31-8217-c79dc2f549f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999607659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.999607659
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.1074255508
Short name T575
Test name
Test status
Simulation time 2371472593 ps
CPU time 7.91 seconds
Started Jan 14 01:29:32 PM PST 24
Finished Jan 14 01:29:45 PM PST 24
Peak memory 217388 kb
Host smart-dbf70dc6-bde1-4368-ba19-9224a2895fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074255508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.1074255508
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.3959664027
Short name T348
Test name
Test status
Simulation time 243748127 ps
CPU time 1.1 seconds
Started Jan 14 01:29:43 PM PST 24
Finished Jan 14 01:29:45 PM PST 24
Peak memory 216468 kb
Host smart-eb32d274-dd9a-4c15-b31b-651dad510fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959664027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.3959664027
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.382661777
Short name T368
Test name
Test status
Simulation time 144941721 ps
CPU time 0.8 seconds
Started Jan 14 01:29:32 PM PST 24
Finished Jan 14 01:29:38 PM PST 24
Peak memory 199204 kb
Host smart-75c7487e-2af3-409b-95be-23237c6674b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382661777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.382661777
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.388356748
Short name T49
Test name
Test status
Simulation time 974916819 ps
CPU time 5.16 seconds
Started Jan 14 01:29:43 PM PST 24
Finished Jan 14 01:29:49 PM PST 24
Peak memory 199532 kb
Host smart-a3536232-4c72-4961-9e8a-ab4463c09591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388356748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.388356748
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.4215142503
Short name T384
Test name
Test status
Simulation time 187399820 ps
CPU time 1.16 seconds
Started Jan 14 01:29:29 PM PST 24
Finished Jan 14 01:29:33 PM PST 24
Peak memory 199384 kb
Host smart-134616be-43cc-42e3-b8b1-6c95f3329bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215142503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.4215142503
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.5792470
Short name T529
Test name
Test status
Simulation time 246249762 ps
CPU time 1.5 seconds
Started Jan 14 01:29:31 PM PST 24
Finished Jan 14 01:29:39 PM PST 24
Peak memory 199472 kb
Host smart-814d03e7-2b26-4f3b-9daf-9f086fce82ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5792470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.5792470
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.2398887534
Short name T256
Test name
Test status
Simulation time 12077286379 ps
CPU time 39.39 seconds
Started Jan 14 01:29:34 PM PST 24
Finished Jan 14 01:30:17 PM PST 24
Peak memory 199600 kb
Host smart-fd5bf2f4-397a-4cec-b2b7-3ddf6073b89a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398887534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.2398887534
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.4045782024
Short name T132
Test name
Test status
Simulation time 432151421 ps
CPU time 2.34 seconds
Started Jan 14 01:29:32 PM PST 24
Finished Jan 14 01:29:40 PM PST 24
Peak memory 199368 kb
Host smart-9f57410b-11ad-4394-bb38-0a43534fcc2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045782024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.4045782024
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.2549626623
Short name T381
Test name
Test status
Simulation time 66868683 ps
CPU time 0.77 seconds
Started Jan 14 01:29:31 PM PST 24
Finished Jan 14 01:29:38 PM PST 24
Peak memory 199320 kb
Host smart-0a4173f2-4db7-4004-a11f-60f3fff94093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549626623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.2549626623
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.4046449394
Short name T43
Test name
Test status
Simulation time 91032235 ps
CPU time 0.83 seconds
Started Jan 14 01:29:34 PM PST 24
Finished Jan 14 01:29:39 PM PST 24
Peak memory 199288 kb
Host smart-e799f8f1-38f0-4fd5-a927-4baa30c396c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046449394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.4046449394
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.2810771238
Short name T617
Test name
Test status
Simulation time 1885207349 ps
CPU time 8.03 seconds
Started Jan 14 01:29:34 PM PST 24
Finished Jan 14 01:29:46 PM PST 24
Peak memory 217360 kb
Host smart-81e2d9b9-2fbb-4f55-833f-f46d1caefb45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810771238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.2810771238
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.440219284
Short name T409
Test name
Test status
Simulation time 244786830 ps
CPU time 1.04 seconds
Started Jan 14 01:29:37 PM PST 24
Finished Jan 14 01:29:39 PM PST 24
Peak memory 216484 kb
Host smart-ef8cef3a-5ba6-4e0e-9d25-47f988c3935b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440219284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.440219284
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.3227499081
Short name T16
Test name
Test status
Simulation time 195239700 ps
CPU time 0.91 seconds
Started Jan 14 01:29:34 PM PST 24
Finished Jan 14 01:29:39 PM PST 24
Peak memory 199176 kb
Host smart-22841f67-4e5b-421b-9386-ea708160e1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227499081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.3227499081
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.2635606436
Short name T513
Test name
Test status
Simulation time 919953815 ps
CPU time 4.58 seconds
Started Jan 14 01:29:35 PM PST 24
Finished Jan 14 01:29:42 PM PST 24
Peak memory 199608 kb
Host smart-8339f505-e2d5-4289-93b2-979148cfaffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635606436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.2635606436
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.2831615357
Short name T315
Test name
Test status
Simulation time 154528518 ps
CPU time 1.12 seconds
Started Jan 14 01:29:39 PM PST 24
Finished Jan 14 01:29:41 PM PST 24
Peak memory 199404 kb
Host smart-8f20c836-cf0e-43d2-84ae-23229fbcddb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831615357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.2831615357
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.4173543904
Short name T94
Test name
Test status
Simulation time 108614479 ps
CPU time 1.13 seconds
Started Jan 14 01:29:43 PM PST 24
Finished Jan 14 01:29:45 PM PST 24
Peak memory 199508 kb
Host smart-1892b144-25c3-4f8d-a913-1de71e312d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173543904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.4173543904
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.1954737393
Short name T300
Test name
Test status
Simulation time 1892585038 ps
CPU time 9.01 seconds
Started Jan 14 01:29:34 PM PST 24
Finished Jan 14 01:29:47 PM PST 24
Peak memory 199544 kb
Host smart-bf074238-875d-46e4-9ccc-07e8002dd684
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954737393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.1954737393
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.3847373352
Short name T359
Test name
Test status
Simulation time 348406139 ps
CPU time 2.22 seconds
Started Jan 14 01:29:33 PM PST 24
Finished Jan 14 01:29:40 PM PST 24
Peak memory 199196 kb
Host smart-920f0a50-d236-4c45-adf7-09e471e126bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847373352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.3847373352
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.1971001628
Short name T370
Test name
Test status
Simulation time 110908602 ps
CPU time 0.88 seconds
Started Jan 14 01:29:37 PM PST 24
Finished Jan 14 01:29:39 PM PST 24
Peak memory 199412 kb
Host smart-82783ace-036c-491e-9ef1-1ba746552f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971001628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.1971001628
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.1787130995
Short name T589
Test name
Test status
Simulation time 60492194 ps
CPU time 0.72 seconds
Started Jan 14 01:30:00 PM PST 24
Finished Jan 14 01:30:02 PM PST 24
Peak memory 199264 kb
Host smart-4bfc4bf8-ace8-4462-a30c-d8d1d090cc99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787130995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.1787130995
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.2912649126
Short name T435
Test name
Test status
Simulation time 1887430401 ps
CPU time 6.96 seconds
Started Jan 14 01:29:50 PM PST 24
Finished Jan 14 01:29:57 PM PST 24
Peak memory 217276 kb
Host smart-a8821fa9-7e58-4160-aaf0-da9ac0580470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912649126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.2912649126
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.102638593
Short name T163
Test name
Test status
Simulation time 244275343 ps
CPU time 1.15 seconds
Started Jan 14 01:29:52 PM PST 24
Finished Jan 14 01:29:54 PM PST 24
Peak memory 216700 kb
Host smart-3fb37fb0-b17c-4bfd-89e0-ccde969bcda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102638593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.102638593
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.3892474503
Short name T376
Test name
Test status
Simulation time 149413737 ps
CPU time 0.88 seconds
Started Jan 14 01:29:36 PM PST 24
Finished Jan 14 01:29:39 PM PST 24
Peak memory 199260 kb
Host smart-06e6473f-29da-45d4-9af2-5f14ecaed57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892474503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.3892474503
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.1753681833
Short name T543
Test name
Test status
Simulation time 861416154 ps
CPU time 4.48 seconds
Started Jan 14 01:29:31 PM PST 24
Finished Jan 14 01:29:42 PM PST 24
Peak memory 199544 kb
Host smart-81988507-eb46-4293-9298-396f40cc8151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753681833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.1753681833
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.221340728
Short name T443
Test name
Test status
Simulation time 173371511 ps
CPU time 1.25 seconds
Started Jan 14 01:29:53 PM PST 24
Finished Jan 14 01:29:55 PM PST 24
Peak memory 199260 kb
Host smart-fa858e8a-9552-4b49-8b7f-f7a438718e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221340728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.221340728
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.1288693274
Short name T424
Test name
Test status
Simulation time 193368007 ps
CPU time 1.38 seconds
Started Jan 14 01:29:42 PM PST 24
Finished Jan 14 01:29:44 PM PST 24
Peak memory 199492 kb
Host smart-489d7d23-2d45-4aaa-b1bf-9c9ac755e8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288693274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.1288693274
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.3447691363
Short name T334
Test name
Test status
Simulation time 4931103130 ps
CPU time 22.97 seconds
Started Jan 14 01:29:51 PM PST 24
Finished Jan 14 01:30:15 PM PST 24
Peak memory 199620 kb
Host smart-8c76af7f-7f49-4c28-9195-4af8b95fc46b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447691363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.3447691363
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.1467201667
Short name T546
Test name
Test status
Simulation time 128250085 ps
CPU time 1.56 seconds
Started Jan 14 01:29:53 PM PST 24
Finished Jan 14 01:29:56 PM PST 24
Peak memory 199356 kb
Host smart-0f0067aa-cea0-4fcb-a598-a26c220f09e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467201667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.1467201667
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.1062414054
Short name T528
Test name
Test status
Simulation time 182651767 ps
CPU time 1.1 seconds
Started Jan 14 01:29:48 PM PST 24
Finished Jan 14 01:29:49 PM PST 24
Peak memory 199380 kb
Host smart-a65adedf-f057-4e18-9e84-1c4dde07035f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062414054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.1062414054
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.644868232
Short name T407
Test name
Test status
Simulation time 69188414 ps
CPU time 0.75 seconds
Started Jan 14 01:29:56 PM PST 24
Finished Jan 14 01:29:58 PM PST 24
Peak memory 199224 kb
Host smart-89012d4a-e7e2-42e0-841c-1a7a3fe03c24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644868232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.644868232
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.2476500713
Short name T620
Test name
Test status
Simulation time 1892091169 ps
CPU time 8.14 seconds
Started Jan 14 01:29:56 PM PST 24
Finished Jan 14 01:30:05 PM PST 24
Peak memory 216556 kb
Host smart-b68b90fa-a6d8-453a-8353-2dbcb8b42c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476500713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.2476500713
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.2405945770
Short name T411
Test name
Test status
Simulation time 243875571 ps
CPU time 1.12 seconds
Started Jan 14 01:29:52 PM PST 24
Finished Jan 14 01:29:54 PM PST 24
Peak memory 216428 kb
Host smart-11d44a6b-c2ab-4dad-a806-a6d3c45e46f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405945770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.2405945770
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.57197069
Short name T259
Test name
Test status
Simulation time 197360593 ps
CPU time 0.83 seconds
Started Jan 14 01:29:46 PM PST 24
Finished Jan 14 01:29:47 PM PST 24
Peak memory 199116 kb
Host smart-b11077b4-1adf-4b58-87e9-0469cf2ccf7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57197069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.57197069
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.2924970035
Short name T609
Test name
Test status
Simulation time 1458797093 ps
CPU time 5.45 seconds
Started Jan 14 01:29:55 PM PST 24
Finished Jan 14 01:30:01 PM PST 24
Peak memory 199548 kb
Host smart-3eed119e-27f2-425c-a62b-ec68f28eef2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924970035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.2924970035
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.416512702
Short name T364
Test name
Test status
Simulation time 110825037 ps
CPU time 0.99 seconds
Started Jan 14 01:29:59 PM PST 24
Finished Jan 14 01:30:01 PM PST 24
Peak memory 199464 kb
Host smart-b0751c9c-9808-4454-ad9e-1d0de73691fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416512702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.416512702
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.3298257642
Short name T83
Test name
Test status
Simulation time 110565479 ps
CPU time 1.13 seconds
Started Jan 14 01:29:59 PM PST 24
Finished Jan 14 01:30:02 PM PST 24
Peak memory 199560 kb
Host smart-ed2a2827-deb9-4886-8c1c-63cbba773f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298257642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.3298257642
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.3078771180
Short name T537
Test name
Test status
Simulation time 8493273870 ps
CPU time 31.29 seconds
Started Jan 14 01:29:55 PM PST 24
Finished Jan 14 01:30:28 PM PST 24
Peak memory 199612 kb
Host smart-1b93bc7e-c401-412a-bbf5-24ba7c5236d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078771180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.3078771180
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.3402041026
Short name T67
Test name
Test status
Simulation time 121702458 ps
CPU time 1.42 seconds
Started Jan 14 01:29:58 PM PST 24
Finished Jan 14 01:30:00 PM PST 24
Peak memory 199344 kb
Host smart-e82ce683-a933-4c6a-bc91-2d9c8a3e1cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402041026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.3402041026
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.1675302817
Short name T415
Test name
Test status
Simulation time 291282455 ps
CPU time 1.47 seconds
Started Jan 14 01:29:53 PM PST 24
Finished Jan 14 01:29:55 PM PST 24
Peak memory 199376 kb
Host smart-63fa9acf-0a9e-44d8-a605-d92d2df9cf2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675302817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.1675302817
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.1031363601
Short name T135
Test name
Test status
Simulation time 73870461 ps
CPU time 0.71 seconds
Started Jan 14 01:29:55 PM PST 24
Finished Jan 14 01:29:57 PM PST 24
Peak memory 199204 kb
Host smart-cae8bf82-c7dc-4ecb-9445-fde0865a7bb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031363601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.1031363601
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.3668626246
Short name T418
Test name
Test status
Simulation time 1229669808 ps
CPU time 5.71 seconds
Started Jan 14 01:29:56 PM PST 24
Finished Jan 14 01:30:03 PM PST 24
Peak memory 220392 kb
Host smart-70b24c28-7e5f-4aaa-90f7-3787d81c9861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668626246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.3668626246
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.2086323867
Short name T356
Test name
Test status
Simulation time 244207861 ps
CPU time 1.04 seconds
Started Jan 14 01:29:54 PM PST 24
Finished Jan 14 01:29:57 PM PST 24
Peak memory 216524 kb
Host smart-842f0d17-4740-4310-a573-eec8168100d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086323867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.2086323867
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.1371144443
Short name T366
Test name
Test status
Simulation time 177237291 ps
CPU time 0.85 seconds
Started Jan 14 01:30:02 PM PST 24
Finished Jan 14 01:30:05 PM PST 24
Peak memory 199208 kb
Host smart-a6170972-aae5-4ad5-bac1-80ed9fd535bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371144443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.1371144443
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.3293260232
Short name T389
Test name
Test status
Simulation time 895695426 ps
CPU time 4.46 seconds
Started Jan 14 01:30:03 PM PST 24
Finished Jan 14 01:30:09 PM PST 24
Peak memory 199136 kb
Host smart-60b81272-4dec-451a-befa-a069b4d41280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293260232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.3293260232
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.1185393138
Short name T84
Test name
Test status
Simulation time 106159241 ps
CPU time 0.98 seconds
Started Jan 14 01:30:02 PM PST 24
Finished Jan 14 01:30:04 PM PST 24
Peak memory 199404 kb
Host smart-f94c26ef-6225-4ee4-9d7f-61e6a8fc2c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185393138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.1185393138
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.3170288542
Short name T612
Test name
Test status
Simulation time 126494658 ps
CPU time 1.19 seconds
Started Jan 14 01:29:56 PM PST 24
Finished Jan 14 01:29:59 PM PST 24
Peak memory 199500 kb
Host smart-839709e5-e00e-44f5-a7fc-2529b493a422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170288542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.3170288542
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.614360767
Short name T130
Test name
Test status
Simulation time 433236357 ps
CPU time 2.3 seconds
Started Jan 14 01:29:55 PM PST 24
Finished Jan 14 01:29:59 PM PST 24
Peak memory 199396 kb
Host smart-8a7b4f22-9292-4e4a-92a5-9f91e9de0ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614360767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.614360767
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.2868105523
Short name T294
Test name
Test status
Simulation time 129700381 ps
CPU time 1.06 seconds
Started Jan 14 01:29:59 PM PST 24
Finished Jan 14 01:30:02 PM PST 24
Peak memory 199412 kb
Host smart-bebbe4e7-4f37-4b12-ba0f-b1cfc98db7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868105523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.2868105523
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.2148529064
Short name T138
Test name
Test status
Simulation time 83073814 ps
CPU time 0.8 seconds
Started Jan 14 01:27:39 PM PST 24
Finished Jan 14 01:27:41 PM PST 24
Peak memory 199260 kb
Host smart-c2cea8df-d7d3-4210-afc2-6278da732ec9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148529064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.2148529064
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.2315999197
Short name T436
Test name
Test status
Simulation time 2167711975 ps
CPU time 7.73 seconds
Started Jan 14 01:27:31 PM PST 24
Finished Jan 14 01:27:39 PM PST 24
Peak memory 217388 kb
Host smart-45bd4cb9-3501-45de-883c-31d91f2cf1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315999197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.2315999197
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.3717405138
Short name T512
Test name
Test status
Simulation time 243910961 ps
CPU time 1.05 seconds
Started Jan 14 01:27:39 PM PST 24
Finished Jan 14 01:27:41 PM PST 24
Peak memory 216520 kb
Host smart-7efd8ea0-9911-4951-9b08-a750b8598ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717405138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.3717405138
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.1347832114
Short name T14
Test name
Test status
Simulation time 191364112 ps
CPU time 0.86 seconds
Started Jan 14 01:27:32 PM PST 24
Finished Jan 14 01:27:33 PM PST 24
Peak memory 199156 kb
Host smart-77e58f9e-b1b7-4114-8460-6c9316b576e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347832114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.1347832114
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.3822365232
Short name T573
Test name
Test status
Simulation time 1339006917 ps
CPU time 5.7 seconds
Started Jan 14 01:27:31 PM PST 24
Finished Jan 14 01:27:37 PM PST 24
Peak memory 199408 kb
Host smart-6c1c03d6-dadc-43d1-8d5e-ec35f18bdfee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822365232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.3822365232
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.4217044200
Short name T77
Test name
Test status
Simulation time 16643920402 ps
CPU time 25.85 seconds
Started Jan 14 01:27:40 PM PST 24
Finished Jan 14 01:28:07 PM PST 24
Peak memory 217492 kb
Host smart-bced13c6-8bfb-4fdc-bb88-8aadc246931b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217044200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.4217044200
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.4101099658
Short name T286
Test name
Test status
Simulation time 171694821 ps
CPU time 1.12 seconds
Started Jan 14 01:27:37 PM PST 24
Finished Jan 14 01:27:39 PM PST 24
Peak memory 199420 kb
Host smart-0246a372-9195-4c1d-a401-c3ac4c6fdf17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101099658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.4101099658
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.3094478899
Short name T385
Test name
Test status
Simulation time 126911955 ps
CPU time 1.17 seconds
Started Jan 14 01:27:35 PM PST 24
Finished Jan 14 01:27:37 PM PST 24
Peak memory 199536 kb
Host smart-d796a437-871e-4de0-8519-e09afd228945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094478899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.3094478899
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.931386953
Short name T27
Test name
Test status
Simulation time 9262482767 ps
CPU time 33.02 seconds
Started Jan 14 01:27:39 PM PST 24
Finished Jan 14 01:28:13 PM PST 24
Peak memory 199620 kb
Host smart-e73297f1-2fa9-4b04-ba5e-6f9aca4c9410
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931386953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.931386953
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.3688641256
Short name T388
Test name
Test status
Simulation time 382154168 ps
CPU time 2.21 seconds
Started Jan 14 01:27:37 PM PST 24
Finished Jan 14 01:27:40 PM PST 24
Peak memory 199388 kb
Host smart-d725827e-21f3-47b1-9201-232fcfc9e43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688641256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.3688641256
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.3029017884
Short name T468
Test name
Test status
Simulation time 133198830 ps
CPU time 1.08 seconds
Started Jan 14 01:27:37 PM PST 24
Finished Jan 14 01:27:39 PM PST 24
Peak memory 199412 kb
Host smart-ecf82653-d31e-4593-8946-8d1687d3f78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029017884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.3029017884
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.2468732309
Short name T76
Test name
Test status
Simulation time 93318546 ps
CPU time 0.78 seconds
Started Jan 14 01:29:55 PM PST 24
Finished Jan 14 01:29:57 PM PST 24
Peak memory 199240 kb
Host smart-63707442-e6c5-4c9c-8f15-2c00540c43ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468732309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.2468732309
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.2298418433
Short name T51
Test name
Test status
Simulation time 1904883706 ps
CPU time 7.35 seconds
Started Jan 14 01:30:00 PM PST 24
Finished Jan 14 01:30:09 PM PST 24
Peak memory 220884 kb
Host smart-05408c1a-7113-452d-aa10-cee06092d2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298418433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.2298418433
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.149693423
Short name T139
Test name
Test status
Simulation time 244492927 ps
CPU time 1.08 seconds
Started Jan 14 01:29:58 PM PST 24
Finished Jan 14 01:30:00 PM PST 24
Peak memory 216580 kb
Host smart-af411382-8e3c-499d-ba61-9c259b2da2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149693423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.149693423
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.248580836
Short name T539
Test name
Test status
Simulation time 157903560 ps
CPU time 0.8 seconds
Started Jan 14 01:29:55 PM PST 24
Finished Jan 14 01:29:57 PM PST 24
Peak memory 199204 kb
Host smart-d43b21c9-c8c1-47d1-ab9e-043345380d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248580836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.248580836
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.2016910212
Short name T335
Test name
Test status
Simulation time 144071784 ps
CPU time 1.08 seconds
Started Jan 14 01:29:54 PM PST 24
Finished Jan 14 01:29:56 PM PST 24
Peak memory 199360 kb
Host smart-4b25bf9b-05db-402e-ab7c-1f765d5f41f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016910212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.2016910212
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.161118122
Short name T63
Test name
Test status
Simulation time 220535152 ps
CPU time 1.43 seconds
Started Jan 14 01:29:55 PM PST 24
Finished Jan 14 01:29:58 PM PST 24
Peak memory 199588 kb
Host smart-57a94e79-3be2-4c45-b940-64bde94963b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161118122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.161118122
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.3163459552
Short name T597
Test name
Test status
Simulation time 5734525541 ps
CPU time 22.37 seconds
Started Jan 14 01:29:54 PM PST 24
Finished Jan 14 01:30:17 PM PST 24
Peak memory 199636 kb
Host smart-0590f95c-dded-4e2d-a702-a0c19110a8e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163459552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.3163459552
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.711418149
Short name T390
Test name
Test status
Simulation time 139741198 ps
CPU time 1.66 seconds
Started Jan 14 01:29:55 PM PST 24
Finished Jan 14 01:29:58 PM PST 24
Peak memory 199348 kb
Host smart-8c1f6fbd-b073-482b-89a9-df05f3e09c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711418149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.711418149
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.506839451
Short name T357
Test name
Test status
Simulation time 200942505 ps
CPU time 1.32 seconds
Started Jan 14 01:29:56 PM PST 24
Finished Jan 14 01:29:58 PM PST 24
Peak memory 199408 kb
Host smart-3daa1378-7c7b-42d9-8557-c09a841872e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506839451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.506839451
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.2692936873
Short name T360
Test name
Test status
Simulation time 63999115 ps
CPU time 0.74 seconds
Started Jan 14 01:29:59 PM PST 24
Finished Jan 14 01:30:01 PM PST 24
Peak memory 199252 kb
Host smart-c53dbe11-8bab-4089-b568-423dbbe9c4d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692936873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.2692936873
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.4236930753
Short name T549
Test name
Test status
Simulation time 1226370899 ps
CPU time 5.6 seconds
Started Jan 14 01:29:55 PM PST 24
Finished Jan 14 01:30:02 PM PST 24
Peak memory 220312 kb
Host smart-ef91167c-f871-47fe-926f-cf376b662e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236930753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.4236930753
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.460404016
Short name T318
Test name
Test status
Simulation time 243822799 ps
CPU time 1.15 seconds
Started Jan 14 01:29:52 PM PST 24
Finished Jan 14 01:29:54 PM PST 24
Peak memory 216364 kb
Host smart-6589c551-c221-4af8-a310-0b06f002afc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460404016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.460404016
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.1574297232
Short name T482
Test name
Test status
Simulation time 123026022 ps
CPU time 0.83 seconds
Started Jan 14 01:29:55 PM PST 24
Finished Jan 14 01:29:57 PM PST 24
Peak memory 199212 kb
Host smart-565ed508-a7e8-42af-b096-b05554082cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574297232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.1574297232
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.2695847372
Short name T417
Test name
Test status
Simulation time 1827845039 ps
CPU time 6.98 seconds
Started Jan 14 01:29:55 PM PST 24
Finished Jan 14 01:30:03 PM PST 24
Peak memory 199544 kb
Host smart-9d76c39f-383c-4917-8a49-79c39e20c382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695847372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.2695847372
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.3306502740
Short name T156
Test name
Test status
Simulation time 107189773 ps
CPU time 0.97 seconds
Started Jan 14 01:29:51 PM PST 24
Finished Jan 14 01:29:53 PM PST 24
Peak memory 199288 kb
Host smart-17da658a-63ad-4750-94fa-34bb04f0e922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306502740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.3306502740
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.675260679
Short name T61
Test name
Test status
Simulation time 125865613 ps
CPU time 1.11 seconds
Started Jan 14 01:29:53 PM PST 24
Finished Jan 14 01:29:55 PM PST 24
Peak memory 199548 kb
Host smart-7b47de83-b680-4b48-913c-18197aeb90d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675260679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.675260679
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.188370114
Short name T471
Test name
Test status
Simulation time 398201773 ps
CPU time 2.05 seconds
Started Jan 14 01:29:53 PM PST 24
Finished Jan 14 01:29:57 PM PST 24
Peak memory 199556 kb
Host smart-d5f6a1ec-72dc-4fa5-992a-d4dba99096f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188370114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.188370114
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.2259897069
Short name T292
Test name
Test status
Simulation time 145692262 ps
CPU time 1.71 seconds
Started Jan 14 01:29:50 PM PST 24
Finished Jan 14 01:29:52 PM PST 24
Peak memory 199336 kb
Host smart-58cec6cf-23d9-475c-84eb-5c69d4d86617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259897069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.2259897069
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.1016282970
Short name T595
Test name
Test status
Simulation time 241404918 ps
CPU time 1.33 seconds
Started Jan 14 01:29:57 PM PST 24
Finished Jan 14 01:29:59 PM PST 24
Peak memory 199336 kb
Host smart-fb9a88ba-3511-489e-abfd-d116ef5a1f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016282970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.1016282970
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.600597114
Short name T425
Test name
Test status
Simulation time 69495299 ps
CPU time 0.79 seconds
Started Jan 14 01:29:52 PM PST 24
Finished Jan 14 01:29:54 PM PST 24
Peak memory 199204 kb
Host smart-1e5467d0-cf73-4864-8ac5-b1b58e1eb449
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600597114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.600597114
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.1230780024
Short name T279
Test name
Test status
Simulation time 2376266386 ps
CPU time 8.6 seconds
Started Jan 14 01:29:56 PM PST 24
Finished Jan 14 01:30:06 PM PST 24
Peak memory 218204 kb
Host smart-a7cf769c-c511-4e88-b9d7-360d4d01375a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230780024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.1230780024
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.2771219758
Short name T287
Test name
Test status
Simulation time 243609034 ps
CPU time 1.09 seconds
Started Jan 14 01:29:53 PM PST 24
Finished Jan 14 01:29:55 PM PST 24
Peak memory 216660 kb
Host smart-1cbba953-b8b1-473f-96a5-068f01b8f7ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771219758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.2771219758
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.3902470248
Short name T275
Test name
Test status
Simulation time 210613268 ps
CPU time 0.9 seconds
Started Jan 14 01:29:54 PM PST 24
Finished Jan 14 01:29:56 PM PST 24
Peak memory 199192 kb
Host smart-ebb39168-6e66-4dca-8f90-5314c97c3c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902470248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.3902470248
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.1216580793
Short name T269
Test name
Test status
Simulation time 1844710031 ps
CPU time 7.38 seconds
Started Jan 14 01:29:59 PM PST 24
Finished Jan 14 01:30:07 PM PST 24
Peak memory 199612 kb
Host smart-7149a183-2f68-4007-b2ad-324fb832c204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216580793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.1216580793
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.1913179684
Short name T553
Test name
Test status
Simulation time 170193284 ps
CPU time 1.2 seconds
Started Jan 14 01:30:00 PM PST 24
Finished Jan 14 01:30:03 PM PST 24
Peak memory 199412 kb
Host smart-275b36e9-185e-4bd9-8361-2f34557fbeee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913179684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.1913179684
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.2923182767
Short name T55
Test name
Test status
Simulation time 198904359 ps
CPU time 1.34 seconds
Started Jan 14 01:29:52 PM PST 24
Finished Jan 14 01:29:54 PM PST 24
Peak memory 199548 kb
Host smart-4ccd63f3-51ea-4475-9520-c75ddff81c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923182767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.2923182767
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.3994323578
Short name T555
Test name
Test status
Simulation time 8452853786 ps
CPU time 30.58 seconds
Started Jan 14 01:29:56 PM PST 24
Finished Jan 14 01:30:28 PM PST 24
Peak memory 199556 kb
Host smart-ca33f34e-a636-43c3-8926-dbb2e35447ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994323578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.3994323578
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.1424315998
Short name T619
Test name
Test status
Simulation time 127900968 ps
CPU time 1.66 seconds
Started Jan 14 01:29:59 PM PST 24
Finished Jan 14 01:30:02 PM PST 24
Peak memory 199456 kb
Host smart-28c0d0c9-3948-425a-92e4-26af5f22f3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424315998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.1424315998
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.54325056
Short name T352
Test name
Test status
Simulation time 71734857 ps
CPU time 0.76 seconds
Started Jan 14 01:29:53 PM PST 24
Finished Jan 14 01:29:55 PM PST 24
Peak memory 199376 kb
Host smart-d9470110-71b9-4f5c-913f-3d12a62568f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54325056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.54325056
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.3509731984
Short name T75
Test name
Test status
Simulation time 66326976 ps
CPU time 0.7 seconds
Started Jan 14 01:29:54 PM PST 24
Finished Jan 14 01:29:56 PM PST 24
Peak memory 199192 kb
Host smart-9af201f2-055f-4c6a-9ee1-6a2566100956
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509731984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.3509731984
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.3778680344
Short name T44
Test name
Test status
Simulation time 1226163952 ps
CPU time 5.89 seconds
Started Jan 14 01:29:54 PM PST 24
Finished Jan 14 01:30:01 PM PST 24
Peak memory 229148 kb
Host smart-5ee9daa6-ac42-44d6-bb86-48986cff2c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778680344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.3778680344
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.250918046
Short name T89
Test name
Test status
Simulation time 262739121 ps
CPU time 1.06 seconds
Started Jan 14 01:30:03 PM PST 24
Finished Jan 14 01:30:06 PM PST 24
Peak memory 216252 kb
Host smart-3dfdbb90-b5bb-4b01-b9c3-8366698ac15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250918046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.250918046
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.2752742106
Short name T460
Test name
Test status
Simulation time 150285949 ps
CPU time 0.87 seconds
Started Jan 14 01:29:59 PM PST 24
Finished Jan 14 01:30:02 PM PST 24
Peak memory 199208 kb
Host smart-a64acf06-c0e2-4c78-9b7c-119a50b479b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752742106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.2752742106
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.2777135975
Short name T421
Test name
Test status
Simulation time 1528671297 ps
CPU time 5.8 seconds
Started Jan 14 01:29:58 PM PST 24
Finished Jan 14 01:30:05 PM PST 24
Peak memory 199612 kb
Host smart-5f597bd1-0710-41b7-9e50-c017eb8cb124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777135975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.2777135975
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.2226201802
Short name T579
Test name
Test status
Simulation time 108023098 ps
CPU time 1.01 seconds
Started Jan 14 01:29:57 PM PST 24
Finished Jan 14 01:29:59 PM PST 24
Peak memory 199380 kb
Host smart-3806b3e2-3c6b-4235-a75c-17d340b0654a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226201802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.2226201802
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.4121342666
Short name T402
Test name
Test status
Simulation time 201064223 ps
CPU time 1.45 seconds
Started Jan 14 01:30:03 PM PST 24
Finished Jan 14 01:30:07 PM PST 24
Peak memory 199552 kb
Host smart-f598197a-5862-4220-931b-d36dc9a1a250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121342666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.4121342666
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.1691950693
Short name T53
Test name
Test status
Simulation time 5190356359 ps
CPU time 18.02 seconds
Started Jan 14 01:29:56 PM PST 24
Finished Jan 14 01:30:15 PM PST 24
Peak memory 199592 kb
Host smart-4b010256-7926-4780-9bd7-2c9b4d3d51c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691950693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.1691950693
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.4261375234
Short name T453
Test name
Test status
Simulation time 370398892 ps
CPU time 2.48 seconds
Started Jan 14 01:29:59 PM PST 24
Finished Jan 14 01:30:03 PM PST 24
Peak memory 199328 kb
Host smart-12faf521-1990-47b6-91f0-5ed718f0f3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261375234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.4261375234
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.2112224358
Short name T267
Test name
Test status
Simulation time 152317814 ps
CPU time 1.05 seconds
Started Jan 14 01:29:54 PM PST 24
Finished Jan 14 01:29:56 PM PST 24
Peak memory 199340 kb
Host smart-3a09d38a-5767-4bfb-9679-20b474975dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112224358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.2112224358
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.994774408
Short name T245
Test name
Test status
Simulation time 58985411 ps
CPU time 0.74 seconds
Started Jan 14 01:30:03 PM PST 24
Finished Jan 14 01:30:06 PM PST 24
Peak memory 199212 kb
Host smart-ef99acd3-13b8-4865-bba5-f278744e570d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994774408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.994774408
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.3788599884
Short name T39
Test name
Test status
Simulation time 1215824336 ps
CPU time 5.44 seconds
Started Jan 14 01:30:08 PM PST 24
Finished Jan 14 01:30:14 PM PST 24
Peak memory 217380 kb
Host smart-5a2ac1c7-6bc4-487b-a198-3fc332a04f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788599884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.3788599884
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.3096714902
Short name T146
Test name
Test status
Simulation time 244524679 ps
CPU time 1.05 seconds
Started Jan 14 01:30:01 PM PST 24
Finished Jan 14 01:30:04 PM PST 24
Peak memory 216588 kb
Host smart-5ac0f0a9-e099-45dd-9eb5-37e0ed83331d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096714902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.3096714902
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.1648884573
Short name T277
Test name
Test status
Simulation time 159784501 ps
CPU time 0.8 seconds
Started Jan 14 01:30:00 PM PST 24
Finished Jan 14 01:30:03 PM PST 24
Peak memory 199212 kb
Host smart-04e92ea9-c779-4ea9-a98c-8d76c865711a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648884573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.1648884573
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.120362662
Short name T46
Test name
Test status
Simulation time 775120491 ps
CPU time 3.89 seconds
Started Jan 14 01:29:54 PM PST 24
Finished Jan 14 01:29:59 PM PST 24
Peak memory 199512 kb
Host smart-2c79365c-3ae7-4fe2-b3bb-ebbfa278e38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120362662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.120362662
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.3370529184
Short name T332
Test name
Test status
Simulation time 100566069 ps
CPU time 1 seconds
Started Jan 14 01:30:02 PM PST 24
Finished Jan 14 01:30:04 PM PST 24
Peak memory 199412 kb
Host smart-6266d2c4-749a-436d-b87b-3b3cf57cb236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370529184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.3370529184
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.1543205479
Short name T581
Test name
Test status
Simulation time 253116035 ps
CPU time 1.62 seconds
Started Jan 14 01:30:03 PM PST 24
Finished Jan 14 01:30:06 PM PST 24
Peak memory 199212 kb
Host smart-006ff9bf-e7a1-4283-871c-40fa37555f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543205479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.1543205479
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.405894012
Short name T605
Test name
Test status
Simulation time 4365231852 ps
CPU time 19.08 seconds
Started Jan 14 01:30:02 PM PST 24
Finished Jan 14 01:30:22 PM PST 24
Peak memory 199608 kb
Host smart-1ed4b009-01d3-4d28-aff2-dc4418130ef2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405894012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.405894012
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.1029446666
Short name T504
Test name
Test status
Simulation time 117328713 ps
CPU time 1.37 seconds
Started Jan 14 01:29:59 PM PST 24
Finished Jan 14 01:30:01 PM PST 24
Peak memory 199368 kb
Host smart-c62c1ebc-905e-4c60-b478-bfc6fbe073ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029446666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.1029446666
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.2946838876
Short name T594
Test name
Test status
Simulation time 155454255 ps
CPU time 1 seconds
Started Jan 14 01:29:55 PM PST 24
Finished Jan 14 01:29:57 PM PST 24
Peak memory 199396 kb
Host smart-4a1e2234-44e0-411d-8350-ec05051d8ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946838876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.2946838876
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.1122811208
Short name T616
Test name
Test status
Simulation time 96239898 ps
CPU time 0.86 seconds
Started Jan 14 01:30:05 PM PST 24
Finished Jan 14 01:30:08 PM PST 24
Peak memory 199256 kb
Host smart-bf0494de-3b1c-4b7e-b9d1-dfde9d98b51e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122811208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.1122811208
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.4278342407
Short name T40
Test name
Test status
Simulation time 2352669677 ps
CPU time 9.52 seconds
Started Jan 14 01:30:03 PM PST 24
Finished Jan 14 01:30:15 PM PST 24
Peak memory 221468 kb
Host smart-2696a6fe-14aa-49df-a374-ecfb656ad6f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278342407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.4278342407
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.3343112762
Short name T392
Test name
Test status
Simulation time 244330418 ps
CPU time 1.09 seconds
Started Jan 14 01:30:02 PM PST 24
Finished Jan 14 01:30:04 PM PST 24
Peak memory 216460 kb
Host smart-882fdb74-b5a6-4ca6-a9cb-1d5dac1ddf8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343112762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.3343112762
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.3167951169
Short name T365
Test name
Test status
Simulation time 206778577 ps
CPU time 0.91 seconds
Started Jan 14 01:30:02 PM PST 24
Finished Jan 14 01:30:05 PM PST 24
Peak memory 199204 kb
Host smart-de9b70a1-8985-408a-b565-0fb99f7ea746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167951169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.3167951169
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.475569100
Short name T522
Test name
Test status
Simulation time 864123266 ps
CPU time 4.2 seconds
Started Jan 14 01:30:07 PM PST 24
Finished Jan 14 01:30:13 PM PST 24
Peak memory 199524 kb
Host smart-250943cf-5ed5-495c-837d-0c4f36d4febb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475569100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.475569100
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.2342614001
Short name T585
Test name
Test status
Simulation time 110232023 ps
CPU time 1 seconds
Started Jan 14 01:30:06 PM PST 24
Finished Jan 14 01:30:09 PM PST 24
Peak memory 199396 kb
Host smart-77cc8dde-0bca-469d-8964-9444c801c90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342614001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.2342614001
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.603012303
Short name T615
Test name
Test status
Simulation time 252238187 ps
CPU time 1.47 seconds
Started Jan 14 01:30:07 PM PST 24
Finished Jan 14 01:30:10 PM PST 24
Peak memory 199580 kb
Host smart-d0989ea5-ee88-4707-b6ed-e0a1a9b5c42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603012303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.603012303
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.975989762
Short name T312
Test name
Test status
Simulation time 215500703 ps
CPU time 1.16 seconds
Started Jan 14 01:30:07 PM PST 24
Finished Jan 14 01:30:10 PM PST 24
Peak memory 199412 kb
Host smart-01359fae-c0c0-4fff-904b-0de2566a9880
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975989762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.975989762
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.752485448
Short name T446
Test name
Test status
Simulation time 362363583 ps
CPU time 2.43 seconds
Started Jan 14 01:30:01 PM PST 24
Finished Jan 14 01:30:05 PM PST 24
Peak memory 199376 kb
Host smart-fc83a8df-7c25-46d5-b885-cbb0712e33b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752485448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.752485448
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.3136011809
Short name T306
Test name
Test status
Simulation time 151745455 ps
CPU time 1.12 seconds
Started Jan 14 01:30:05 PM PST 24
Finished Jan 14 01:30:08 PM PST 24
Peak memory 199364 kb
Host smart-698e320b-ccea-4e9e-bc2f-06074b78f365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136011809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.3136011809
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.1051826112
Short name T582
Test name
Test status
Simulation time 62023601 ps
CPU time 0.71 seconds
Started Jan 14 01:30:06 PM PST 24
Finished Jan 14 01:30:08 PM PST 24
Peak memory 199244 kb
Host smart-8d5a8136-32db-455c-a226-b5236e7c70b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051826112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.1051826112
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.1337742096
Short name T244
Test name
Test status
Simulation time 1224993022 ps
CPU time 6.02 seconds
Started Jan 14 01:30:06 PM PST 24
Finished Jan 14 01:30:13 PM PST 24
Peak memory 217352 kb
Host smart-3e0777c6-b00b-4cb5-8b09-4b1115218b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337742096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.1337742096
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.3246673846
Short name T358
Test name
Test status
Simulation time 245493534 ps
CPU time 1.03 seconds
Started Jan 14 01:30:05 PM PST 24
Finished Jan 14 01:30:08 PM PST 24
Peak memory 216644 kb
Host smart-9889bd91-9547-43ca-9152-948db0d8ace9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246673846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.3246673846
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.1227603945
Short name T604
Test name
Test status
Simulation time 145317832 ps
CPU time 0.8 seconds
Started Jan 14 01:30:04 PM PST 24
Finished Jan 14 01:30:07 PM PST 24
Peak memory 199156 kb
Host smart-7ada5e2f-6d0b-4b73-bb01-bf1f820a2b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227603945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.1227603945
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.3954035887
Short name T305
Test name
Test status
Simulation time 1733049344 ps
CPU time 6.03 seconds
Started Jan 14 01:30:04 PM PST 24
Finished Jan 14 01:30:12 PM PST 24
Peak memory 199552 kb
Host smart-543b8a66-3e6d-4628-b2f5-4d28931d117e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954035887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.3954035887
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.2067037728
Short name T310
Test name
Test status
Simulation time 170408472 ps
CPU time 1.14 seconds
Started Jan 14 01:30:04 PM PST 24
Finished Jan 14 01:30:07 PM PST 24
Peak memory 199376 kb
Host smart-56d4cac6-0436-4425-9fc3-65d093fc6455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067037728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.2067037728
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.4151445854
Short name T142
Test name
Test status
Simulation time 121820567 ps
CPU time 1.15 seconds
Started Jan 14 01:30:03 PM PST 24
Finished Jan 14 01:30:06 PM PST 24
Peak memory 199548 kb
Host smart-d36aad4b-cc16-4867-a202-4804d5874732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151445854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.4151445854
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.2222901515
Short name T592
Test name
Test status
Simulation time 7497418039 ps
CPU time 27.7 seconds
Started Jan 14 01:30:07 PM PST 24
Finished Jan 14 01:30:36 PM PST 24
Peak memory 199576 kb
Host smart-330f31a3-5b6b-4891-9735-c652b2e73b9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222901515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.2222901515
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.3988583838
Short name T262
Test name
Test status
Simulation time 367235937 ps
CPU time 2.65 seconds
Started Jan 14 01:30:07 PM PST 24
Finished Jan 14 01:30:11 PM PST 24
Peak memory 199344 kb
Host smart-31e65f1c-a456-4ae1-88ad-b911a4f456cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988583838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.3988583838
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.2607184618
Short name T551
Test name
Test status
Simulation time 124482503 ps
CPU time 0.94 seconds
Started Jan 14 01:30:04 PM PST 24
Finished Jan 14 01:30:07 PM PST 24
Peak memory 199252 kb
Host smart-d9ecb532-bd36-46fd-b654-14c8eff906ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607184618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.2607184618
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.1040691311
Short name T362
Test name
Test status
Simulation time 62857645 ps
CPU time 0.72 seconds
Started Jan 14 01:30:09 PM PST 24
Finished Jan 14 01:30:11 PM PST 24
Peak memory 199196 kb
Host smart-ddf58387-09b4-46f0-874a-b5ca33214269
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040691311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.1040691311
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.2255456974
Short name T587
Test name
Test status
Simulation time 1220005230 ps
CPU time 5.44 seconds
Started Jan 14 01:30:06 PM PST 24
Finished Jan 14 01:30:13 PM PST 24
Peak memory 217400 kb
Host smart-dbfeb29f-d8b6-4048-bbe6-1bdefc08db8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255456974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.2255456974
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.184764206
Short name T248
Test name
Test status
Simulation time 244148410 ps
CPU time 1.07 seconds
Started Jan 14 01:30:10 PM PST 24
Finished Jan 14 01:30:12 PM PST 24
Peak memory 216576 kb
Host smart-ab83c74e-e8a7-41a6-9c39-220fa5a0388e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184764206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.184764206
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.2370834576
Short name T308
Test name
Test status
Simulation time 212194668 ps
CPU time 0.93 seconds
Started Jan 14 01:30:08 PM PST 24
Finished Jan 14 01:30:10 PM PST 24
Peak memory 199208 kb
Host smart-1fa71507-342e-4135-a13f-fdd8a3993762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370834576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.2370834576
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.476527816
Short name T329
Test name
Test status
Simulation time 2020080879 ps
CPU time 6.85 seconds
Started Jan 14 01:30:07 PM PST 24
Finished Jan 14 01:30:15 PM PST 24
Peak memory 199552 kb
Host smart-e83bc292-470c-4566-8195-0a9c851206bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476527816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.476527816
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.3286904797
Short name T565
Test name
Test status
Simulation time 160458222 ps
CPU time 1.12 seconds
Started Jan 14 01:30:09 PM PST 24
Finished Jan 14 01:30:11 PM PST 24
Peak memory 199340 kb
Host smart-253e4323-148a-4d37-904b-3cf2796565cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286904797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.3286904797
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.2205869770
Short name T577
Test name
Test status
Simulation time 111535924 ps
CPU time 1.18 seconds
Started Jan 14 01:30:06 PM PST 24
Finished Jan 14 01:30:08 PM PST 24
Peak memory 199544 kb
Host smart-4f222cb4-9014-4825-9dd6-d132cd6b08f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205869770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.2205869770
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.2411471632
Short name T470
Test name
Test status
Simulation time 8116770194 ps
CPU time 30.22 seconds
Started Jan 14 01:30:06 PM PST 24
Finished Jan 14 01:30:38 PM PST 24
Peak memory 199572 kb
Host smart-6703664b-1cb7-4dd1-8150-1dcf66b4794c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411471632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.2411471632
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.3367294783
Short name T249
Test name
Test status
Simulation time 456834480 ps
CPU time 2.41 seconds
Started Jan 14 01:30:06 PM PST 24
Finished Jan 14 01:30:10 PM PST 24
Peak memory 199320 kb
Host smart-0e7f953a-3ebf-4b69-9254-650c4b4115e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367294783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.3367294783
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.2152059428
Short name T7
Test name
Test status
Simulation time 118866891 ps
CPU time 1.07 seconds
Started Jan 14 01:30:04 PM PST 24
Finished Jan 14 01:30:07 PM PST 24
Peak memory 199408 kb
Host smart-830b5bf3-46ea-45fb-9cb8-deae5f726240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152059428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.2152059428
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.814265070
Short name T496
Test name
Test status
Simulation time 105078388 ps
CPU time 0.81 seconds
Started Jan 14 01:30:08 PM PST 24
Finished Jan 14 01:30:10 PM PST 24
Peak memory 199148 kb
Host smart-d8a4d0e8-faf9-4095-907f-64ad84659464
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814265070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.814265070
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.3416398319
Short name T525
Test name
Test status
Simulation time 1897747986 ps
CPU time 7.07 seconds
Started Jan 14 01:30:09 PM PST 24
Finished Jan 14 01:30:17 PM PST 24
Peak memory 216316 kb
Host smart-90c32b7e-ac83-499c-9cb4-79f2c6cf0759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416398319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.3416398319
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.2110360808
Short name T47
Test name
Test status
Simulation time 243661060 ps
CPU time 1.14 seconds
Started Jan 14 01:30:09 PM PST 24
Finished Jan 14 01:30:11 PM PST 24
Peak memory 216544 kb
Host smart-aedec8f7-375a-4d54-acc4-4ec35f6dd688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110360808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.2110360808
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.3050339368
Short name T568
Test name
Test status
Simulation time 163159982 ps
CPU time 0.77 seconds
Started Jan 14 01:30:09 PM PST 24
Finished Jan 14 01:30:11 PM PST 24
Peak memory 199116 kb
Host smart-1644f065-517b-4825-b7e8-b8cb68b33b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050339368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.3050339368
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.3574432356
Short name T113
Test name
Test status
Simulation time 679447353 ps
CPU time 3.62 seconds
Started Jan 14 01:30:10 PM PST 24
Finished Jan 14 01:30:15 PM PST 24
Peak memory 199208 kb
Host smart-c87c8c74-793c-4fff-bb60-ce49a67d1c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574432356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.3574432356
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.2178187819
Short name T31
Test name
Test status
Simulation time 154743395 ps
CPU time 1.11 seconds
Started Jan 14 01:30:10 PM PST 24
Finished Jan 14 01:30:12 PM PST 24
Peak memory 199336 kb
Host smart-d019dc59-2e9e-4798-a107-3f999a5073fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178187819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.2178187819
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.572836581
Short name T414
Test name
Test status
Simulation time 108703868 ps
CPU time 1.21 seconds
Started Jan 14 01:30:10 PM PST 24
Finished Jan 14 01:30:12 PM PST 24
Peak memory 199168 kb
Host smart-87af25ac-3317-4f34-8551-9ceda4dcfcda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572836581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.572836581
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.1196816130
Short name T429
Test name
Test status
Simulation time 1232323594 ps
CPU time 5.66 seconds
Started Jan 14 01:30:09 PM PST 24
Finished Jan 14 01:30:15 PM PST 24
Peak memory 199560 kb
Host smart-654389b6-5402-4ec9-a654-ff7b72a1236a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196816130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.1196816130
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.3432927429
Short name T457
Test name
Test status
Simulation time 142566463 ps
CPU time 1.62 seconds
Started Jan 14 01:30:08 PM PST 24
Finished Jan 14 01:30:11 PM PST 24
Peak memory 199352 kb
Host smart-a26da99f-b8f1-4b55-bf08-e1a2d63d2e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432927429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.3432927429
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.2993946030
Short name T159
Test name
Test status
Simulation time 94079141 ps
CPU time 0.85 seconds
Started Jan 14 01:30:09 PM PST 24
Finished Jan 14 01:30:10 PM PST 24
Peak memory 199364 kb
Host smart-104e27c9-8fee-46fc-87fc-3699e52ffa97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993946030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.2993946030
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.3219068534
Short name T557
Test name
Test status
Simulation time 67206099 ps
CPU time 0.7 seconds
Started Jan 14 01:30:12 PM PST 24
Finished Jan 14 01:30:13 PM PST 24
Peak memory 199260 kb
Host smart-ae2320a8-8842-4402-bede-e835cdc78aca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219068534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.3219068534
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.2296834119
Short name T432
Test name
Test status
Simulation time 2373427664 ps
CPU time 8.05 seconds
Started Jan 14 01:30:10 PM PST 24
Finished Jan 14 01:30:19 PM PST 24
Peak memory 229464 kb
Host smart-6e4db758-4c86-45f9-be74-aeaab2bf05cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296834119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.2296834119
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.1193726189
Short name T403
Test name
Test status
Simulation time 243829147 ps
CPU time 1.17 seconds
Started Jan 14 01:30:14 PM PST 24
Finished Jan 14 01:30:16 PM PST 24
Peak memory 216508 kb
Host smart-e4afe83e-52e6-4941-adaa-e76be0dfab97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193726189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.1193726189
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.900324664
Short name T19
Test name
Test status
Simulation time 104537840 ps
CPU time 0.73 seconds
Started Jan 14 01:30:07 PM PST 24
Finished Jan 14 01:30:09 PM PST 24
Peak memory 199188 kb
Host smart-723b3a6d-de98-40a1-9130-443f19aeea8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900324664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.900324664
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.1240395888
Short name T140
Test name
Test status
Simulation time 1709421021 ps
CPU time 7.42 seconds
Started Jan 14 01:30:08 PM PST 24
Finished Jan 14 01:30:16 PM PST 24
Peak memory 199452 kb
Host smart-9b147f1c-8903-4ef3-9bc1-bdc6dbe5d987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240395888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.1240395888
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.272456937
Short name T257
Test name
Test status
Simulation time 101575234 ps
CPU time 0.98 seconds
Started Jan 14 01:30:11 PM PST 24
Finished Jan 14 01:30:13 PM PST 24
Peak memory 199384 kb
Host smart-c057d039-3c03-4381-921b-4653abd0e995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272456937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.272456937
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.2888003019
Short name T162
Test name
Test status
Simulation time 194115134 ps
CPU time 1.39 seconds
Started Jan 14 01:30:09 PM PST 24
Finished Jan 14 01:30:12 PM PST 24
Peak memory 199492 kb
Host smart-32b85d63-9d43-4802-b639-1c72477ab47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888003019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.2888003019
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.3809869607
Short name T511
Test name
Test status
Simulation time 3075686501 ps
CPU time 12.76 seconds
Started Jan 14 01:30:18 PM PST 24
Finished Jan 14 01:30:31 PM PST 24
Peak memory 199664 kb
Host smart-fc340498-5348-4439-a320-616ca7165952
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809869607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.3809869607
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.2466444305
Short name T283
Test name
Test status
Simulation time 127787899 ps
CPU time 1.53 seconds
Started Jan 14 01:30:13 PM PST 24
Finished Jan 14 01:30:15 PM PST 24
Peak memory 199336 kb
Host smart-85b2a7b7-3040-4b01-a845-0ccea2dc7604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466444305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.2466444305
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.1898685205
Short name T60
Test name
Test status
Simulation time 164192481 ps
CPU time 1.18 seconds
Started Jan 14 01:30:12 PM PST 24
Finished Jan 14 01:30:14 PM PST 24
Peak memory 199248 kb
Host smart-365a0d3d-9f6b-4347-98b3-c1e1566813f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898685205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.1898685205
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.1496439841
Short name T534
Test name
Test status
Simulation time 57445671 ps
CPU time 0.72 seconds
Started Jan 14 01:27:44 PM PST 24
Finished Jan 14 01:27:45 PM PST 24
Peak memory 199216 kb
Host smart-5587d52b-858f-4029-9772-a33de2a1b0b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496439841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.1496439841
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.3698275260
Short name T50
Test name
Test status
Simulation time 1895828592 ps
CPU time 7.15 seconds
Started Jan 14 01:27:37 PM PST 24
Finished Jan 14 01:27:45 PM PST 24
Peak memory 216700 kb
Host smart-d2522060-bc41-46dd-b8c0-66532ebf33d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698275260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.3698275260
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.903605599
Short name T456
Test name
Test status
Simulation time 245190921 ps
CPU time 1.03 seconds
Started Jan 14 01:27:45 PM PST 24
Finished Jan 14 01:27:47 PM PST 24
Peak memory 216552 kb
Host smart-23e4bc48-3587-4bdd-9529-85a69a0efcca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903605599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.903605599
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.165568804
Short name T401
Test name
Test status
Simulation time 224281512 ps
CPU time 0.98 seconds
Started Jan 14 01:27:42 PM PST 24
Finished Jan 14 01:27:43 PM PST 24
Peak memory 199176 kb
Host smart-d3b100f9-0e6a-4b7d-b632-b289c9d75425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165568804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.165568804
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.547172233
Short name T499
Test name
Test status
Simulation time 967991315 ps
CPU time 4.77 seconds
Started Jan 14 01:27:43 PM PST 24
Finished Jan 14 01:27:49 PM PST 24
Peak memory 199576 kb
Host smart-91bb4d3e-a192-41a5-a4ca-2826f7dff5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547172233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.547172233
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.2479909116
Short name T316
Test name
Test status
Simulation time 105735886 ps
CPU time 0.92 seconds
Started Jan 14 01:27:39 PM PST 24
Finished Jan 14 01:27:40 PM PST 24
Peak memory 199424 kb
Host smart-ee157610-5cf0-4d00-935a-6a9edc67bca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479909116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.2479909116
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.1425123360
Short name T9
Test name
Test status
Simulation time 112443563 ps
CPU time 1.12 seconds
Started Jan 14 01:27:36 PM PST 24
Finished Jan 14 01:27:38 PM PST 24
Peak memory 199556 kb
Host smart-3f1142aa-a1b6-4753-b864-dd87a83bd6f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425123360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.1425123360
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.2235549290
Short name T586
Test name
Test status
Simulation time 5406234491 ps
CPU time 19.45 seconds
Started Jan 14 01:27:43 PM PST 24
Finished Jan 14 01:28:03 PM PST 24
Peak memory 199616 kb
Host smart-fc843573-74a0-4b49-ae89-a74a25706102
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235549290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.2235549290
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.827258579
Short name T473
Test name
Test status
Simulation time 140666551 ps
CPU time 1.72 seconds
Started Jan 14 01:27:39 PM PST 24
Finished Jan 14 01:27:41 PM PST 24
Peak memory 199372 kb
Host smart-b74114b9-6c4b-44b1-a88e-eeaabeba6a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827258579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.827258579
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.171280506
Short name T606
Test name
Test status
Simulation time 140273506 ps
CPU time 0.98 seconds
Started Jan 14 01:27:37 PM PST 24
Finished Jan 14 01:27:39 PM PST 24
Peak memory 199412 kb
Host smart-9732fe6a-d14d-4e26-9e64-795e113d6532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171280506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.171280506
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.1100823765
Short name T398
Test name
Test status
Simulation time 81330084 ps
CPU time 0.79 seconds
Started Jan 14 01:27:43 PM PST 24
Finished Jan 14 01:27:44 PM PST 24
Peak memory 199164 kb
Host smart-e0b469e9-2a64-4508-b5a2-aeca4cf7b5a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100823765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.1100823765
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.980435019
Short name T341
Test name
Test status
Simulation time 2366214574 ps
CPU time 8.13 seconds
Started Jan 14 01:27:45 PM PST 24
Finished Jan 14 01:27:54 PM PST 24
Peak memory 220708 kb
Host smart-98c0450a-b07e-4822-9acb-44ceddb224d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980435019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.980435019
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.77307352
Short name T25
Test name
Test status
Simulation time 244693751 ps
CPU time 1.13 seconds
Started Jan 14 01:27:44 PM PST 24
Finished Jan 14 01:27:46 PM PST 24
Peak memory 216620 kb
Host smart-f8ba37cc-4ebf-486c-8e3b-4551a473bd22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77307352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.77307352
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.3474450988
Short name T291
Test name
Test status
Simulation time 181081277 ps
CPU time 0.92 seconds
Started Jan 14 01:27:44 PM PST 24
Finished Jan 14 01:27:45 PM PST 24
Peak memory 199188 kb
Host smart-3281b1ef-4fac-4e49-ba9f-079741998a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474450988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.3474450988
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.3073022579
Short name T274
Test name
Test status
Simulation time 1937178093 ps
CPU time 6.67 seconds
Started Jan 14 01:27:46 PM PST 24
Finished Jan 14 01:27:53 PM PST 24
Peak memory 199560 kb
Host smart-5d01316a-2141-4138-9bac-80b79f8f3fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073022579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.3073022579
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.1298255628
Short name T569
Test name
Test status
Simulation time 175874623 ps
CPU time 1.12 seconds
Started Jan 14 01:27:44 PM PST 24
Finished Jan 14 01:27:46 PM PST 24
Peak memory 199416 kb
Host smart-07a24fba-65fc-42a1-bcc4-a802d7617c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298255628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.1298255628
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.2154686659
Short name T375
Test name
Test status
Simulation time 127027927 ps
CPU time 1.16 seconds
Started Jan 14 01:27:44 PM PST 24
Finished Jan 14 01:27:45 PM PST 24
Peak memory 199468 kb
Host smart-4495300c-2c25-4ba2-986f-726d45cf94ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154686659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.2154686659
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.164875844
Short name T608
Test name
Test status
Simulation time 14214844784 ps
CPU time 56.75 seconds
Started Jan 14 01:27:44 PM PST 24
Finished Jan 14 01:28:42 PM PST 24
Peak memory 199556 kb
Host smart-bbc9ba38-dbe2-47be-b89b-2119c818d2ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164875844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.164875844
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.4286501962
Short name T337
Test name
Test status
Simulation time 253822850 ps
CPU time 1.76 seconds
Started Jan 14 01:27:45 PM PST 24
Finished Jan 14 01:27:48 PM PST 24
Peak memory 199384 kb
Host smart-3ae3aab5-00f3-4805-add5-ed7e4e8aeb63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286501962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.4286501962
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.2972947524
Short name T497
Test name
Test status
Simulation time 119106983 ps
CPU time 0.93 seconds
Started Jan 14 01:27:43 PM PST 24
Finished Jan 14 01:27:45 PM PST 24
Peak memory 199404 kb
Host smart-1c33ccee-6639-45b5-b35d-97bba00814b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972947524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.2972947524
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.2536747182
Short name T148
Test name
Test status
Simulation time 74403205 ps
CPU time 0.75 seconds
Started Jan 14 01:27:55 PM PST 24
Finished Jan 14 01:27:56 PM PST 24
Peak memory 199260 kb
Host smart-116d6ed7-48dd-4593-8f8a-1aebb233fcd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536747182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.2536747182
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.2073004938
Short name T498
Test name
Test status
Simulation time 1224449510 ps
CPU time 5.58 seconds
Started Jan 14 01:27:55 PM PST 24
Finished Jan 14 01:28:01 PM PST 24
Peak memory 216924 kb
Host smart-339d4164-ae6e-4a28-90f8-a2a891040803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073004938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.2073004938
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.846836077
Short name T314
Test name
Test status
Simulation time 244367606 ps
CPU time 1.2 seconds
Started Jan 14 01:27:52 PM PST 24
Finished Jan 14 01:27:54 PM PST 24
Peak memory 216468 kb
Host smart-2ee22567-15c0-46b3-9c70-c690c36d56ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846836077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.846836077
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.3229752557
Short name T492
Test name
Test status
Simulation time 198314694 ps
CPU time 0.88 seconds
Started Jan 14 01:27:45 PM PST 24
Finished Jan 14 01:27:47 PM PST 24
Peak memory 199200 kb
Host smart-99b84d11-b0f6-4af7-92b2-e8a004f4c8fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229752557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.3229752557
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.2456079424
Short name T387
Test name
Test status
Simulation time 1317417408 ps
CPU time 5.35 seconds
Started Jan 14 01:27:45 PM PST 24
Finished Jan 14 01:27:51 PM PST 24
Peak memory 199536 kb
Host smart-c9be369f-9093-4a24-88ab-8d1815d8e82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456079424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.2456079424
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.2299595397
Short name T527
Test name
Test status
Simulation time 144740636 ps
CPU time 1.07 seconds
Started Jan 14 01:27:51 PM PST 24
Finished Jan 14 01:27:53 PM PST 24
Peak memory 199332 kb
Host smart-800086f2-274d-41dd-bdf9-54f99f1ae455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299595397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.2299595397
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.2743409619
Short name T488
Test name
Test status
Simulation time 125321997 ps
CPU time 1.18 seconds
Started Jan 14 01:27:47 PM PST 24
Finished Jan 14 01:27:48 PM PST 24
Peak memory 199568 kb
Host smart-482dc2f3-a919-49e6-97b1-4e58a9492b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743409619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.2743409619
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.171927699
Short name T600
Test name
Test status
Simulation time 17751257122 ps
CPU time 60.09 seconds
Started Jan 14 01:27:52 PM PST 24
Finished Jan 14 01:28:52 PM PST 24
Peak memory 199616 kb
Host smart-2d83ef4b-e59d-4e5b-a29e-397a28721187
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171927699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.171927699
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.585004614
Short name T552
Test name
Test status
Simulation time 344952557 ps
CPU time 1.98 seconds
Started Jan 14 01:27:43 PM PST 24
Finished Jan 14 01:27:46 PM PST 24
Peak memory 199332 kb
Host smart-205ce992-3afa-407f-a754-0b72e822e8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585004614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.585004614
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.1274980152
Short name T520
Test name
Test status
Simulation time 164787220 ps
CPU time 1.27 seconds
Started Jan 14 01:27:43 PM PST 24
Finished Jan 14 01:27:45 PM PST 24
Peak memory 199560 kb
Host smart-3ab9b7ad-33a6-49b9-89a9-bad7572d6e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274980152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.1274980152
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.1131469775
Short name T485
Test name
Test status
Simulation time 63825751 ps
CPU time 0.73 seconds
Started Jan 14 01:27:54 PM PST 24
Finished Jan 14 01:27:55 PM PST 24
Peak memory 199212 kb
Host smart-317bed85-cba3-49f4-ba00-a0eb1028b290
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131469775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.1131469775
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.3749254156
Short name T34
Test name
Test status
Simulation time 2369554826 ps
CPU time 8.35 seconds
Started Jan 14 01:27:52 PM PST 24
Finished Jan 14 01:28:01 PM PST 24
Peak memory 221240 kb
Host smart-5e70db15-253d-485e-9d96-417a3b35bcb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749254156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.3749254156
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.3841205000
Short name T591
Test name
Test status
Simulation time 244441459 ps
CPU time 1.04 seconds
Started Jan 14 01:27:50 PM PST 24
Finished Jan 14 01:27:52 PM PST 24
Peak memory 216416 kb
Host smart-58d4bffb-1fcf-4817-8284-e1464e7ea504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841205000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.3841205000
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.3688098705
Short name T560
Test name
Test status
Simulation time 107533667 ps
CPU time 0.73 seconds
Started Jan 14 01:27:52 PM PST 24
Finished Jan 14 01:27:54 PM PST 24
Peak memory 199116 kb
Host smart-94dac5de-87ca-45ae-9b39-45bbf5288b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688098705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.3688098705
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.4193465691
Short name T564
Test name
Test status
Simulation time 1372075725 ps
CPU time 5.35 seconds
Started Jan 14 01:27:52 PM PST 24
Finished Jan 14 01:27:57 PM PST 24
Peak memory 199492 kb
Host smart-0cedd604-c151-49e7-9e56-f9d8afba67cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193465691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.4193465691
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.2690689345
Short name T4
Test name
Test status
Simulation time 178080000 ps
CPU time 1.22 seconds
Started Jan 14 01:27:52 PM PST 24
Finished Jan 14 01:27:54 PM PST 24
Peak memory 199356 kb
Host smart-5bbd3f98-1125-41fe-9eeb-c49eacb46084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690689345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.2690689345
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.3053925308
Short name T295
Test name
Test status
Simulation time 249911215 ps
CPU time 1.52 seconds
Started Jan 14 01:27:50 PM PST 24
Finished Jan 14 01:27:53 PM PST 24
Peak memory 199512 kb
Host smart-89e19f4f-18c9-431b-8e1e-caf851112571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053925308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.3053925308
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.1514509409
Short name T490
Test name
Test status
Simulation time 10930126733 ps
CPU time 35.3 seconds
Started Jan 14 01:27:51 PM PST 24
Finished Jan 14 01:28:27 PM PST 24
Peak memory 199576 kb
Host smart-1d9fca96-fcfe-4968-b8f1-1cfac73b738d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514509409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.1514509409
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.4085523681
Short name T285
Test name
Test status
Simulation time 361785206 ps
CPU time 2.26 seconds
Started Jan 14 01:27:52 PM PST 24
Finished Jan 14 01:27:55 PM PST 24
Peak memory 199292 kb
Host smart-c36b5e9f-91f0-4b82-8a6e-b2e64479478e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085523681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.4085523681
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.4141723989
Short name T42
Test name
Test status
Simulation time 134954068 ps
CPU time 1.1 seconds
Started Jan 14 01:27:55 PM PST 24
Finished Jan 14 01:27:57 PM PST 24
Peak memory 199420 kb
Host smart-3ee29081-d746-4832-9e87-de0618a825e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141723989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.4141723989
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.4035898031
Short name T477
Test name
Test status
Simulation time 65616768 ps
CPU time 0.74 seconds
Started Jan 14 01:28:00 PM PST 24
Finished Jan 14 01:28:01 PM PST 24
Peak memory 199264 kb
Host smart-6475293c-c18c-4354-912b-42da6f94a2d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035898031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.4035898031
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.1390146861
Short name T299
Test name
Test status
Simulation time 1900287691 ps
CPU time 7.4 seconds
Started Jan 14 01:27:58 PM PST 24
Finished Jan 14 01:28:06 PM PST 24
Peak memory 220844 kb
Host smart-d567a1f8-65e4-4ee6-90eb-488ac7ae034b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390146861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.1390146861
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.3574801360
Short name T243
Test name
Test status
Simulation time 243660416 ps
CPU time 1.03 seconds
Started Jan 14 01:27:57 PM PST 24
Finished Jan 14 01:27:59 PM PST 24
Peak memory 216516 kb
Host smart-8f471668-9855-454c-a8b1-de046ff7b61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574801360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.3574801360
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.316220082
Short name T481
Test name
Test status
Simulation time 206411020 ps
CPU time 0.91 seconds
Started Jan 14 01:27:56 PM PST 24
Finished Jan 14 01:27:57 PM PST 24
Peak memory 199076 kb
Host smart-4d43ac75-602e-4623-bdd2-ae608239c218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316220082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.316220082
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.570968028
Short name T405
Test name
Test status
Simulation time 1066297437 ps
CPU time 4.17 seconds
Started Jan 14 01:27:59 PM PST 24
Finished Jan 14 01:28:03 PM PST 24
Peak memory 199568 kb
Host smart-46358b14-9786-48ec-96dc-df4092365636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570968028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.570968028
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.2829528435
Short name T487
Test name
Test status
Simulation time 108699625 ps
CPU time 0.97 seconds
Started Jan 14 01:27:59 PM PST 24
Finished Jan 14 01:28:00 PM PST 24
Peak memory 199372 kb
Host smart-93d0e7a6-6000-4182-a2a3-7784499f17f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829528435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.2829528435
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.753433632
Short name T152
Test name
Test status
Simulation time 186448064 ps
CPU time 1.42 seconds
Started Jan 14 01:27:58 PM PST 24
Finished Jan 14 01:28:01 PM PST 24
Peak memory 199552 kb
Host smart-de056611-5787-4e55-802e-e5b1144a72cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753433632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.753433632
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.2851299783
Short name T86
Test name
Test status
Simulation time 5726781167 ps
CPU time 26.29 seconds
Started Jan 14 01:27:59 PM PST 24
Finished Jan 14 01:28:26 PM PST 24
Peak memory 199660 kb
Host smart-92aa5db4-32ba-4aa5-ab0c-587f17d0a7c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851299783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.2851299783
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.4136844314
Short name T610
Test name
Test status
Simulation time 144280337 ps
CPU time 1.77 seconds
Started Jan 14 01:28:01 PM PST 24
Finished Jan 14 01:28:03 PM PST 24
Peak memory 199388 kb
Host smart-54ae748e-55d4-4f2d-a924-b35b282b7257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136844314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.4136844314
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.3768155472
Short name T147
Test name
Test status
Simulation time 286445314 ps
CPU time 1.41 seconds
Started Jan 14 01:27:58 PM PST 24
Finished Jan 14 01:28:00 PM PST 24
Peak memory 199404 kb
Host smart-6bf58266-8029-472e-ab0d-f95f1172aad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768155472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.3768155472
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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