Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7761

1

T1

15

T3

20

T6

18

auto[1]

10690

1

T1

86

T3

81

T6

1

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5717	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6292	1			T1	27		T2	1		T3	27
reset_info_cp[2]	2813	1			T1	17		T3	18		T7	8
reset_info_cp[4]	3718	1			T1	19		T3	13		T7	12
reset_info_cp[8]	116	1			T1	1		T7	1		T21	2
reset_info_cp[16]	106	1			T6	2		T9	1		T23	2
reset_info_cp[32]	105	1			T3	1		T6	1		T9	2
reset_info_cp[64]	107	1			T3	2		T8	1		T21	2
reset_info_cp[128]	97	1			T1	1		T21	1		T23	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3027	1			T1	15		T3	20		T7	3
reset_info_cp[1]	auto[1]	2645	1			T1	11		T3	6		T7	16
reset_info_cp[2]	auto[0]	856	1			T7	4		T78	3		T79	3
reset_info_cp[2]	auto[1]	1957	1			T1	17		T3	18		T7	4
reset_info_cp[4]	auto[0]	1326	1			T7	7		T78	7		T79	9
reset_info_cp[4]	auto[1]	2392	1			T1	19		T3	13		T7	5
reset_info_cp[8]	auto[0]	41	1			T7	1		T43	1		T144	1
reset_info_cp[8]	auto[1]	75	1			T1	1		T21	2		T23	1
reset_info_cp[16]	auto[0]	32	1			T6	2		T146	1		T109	1
reset_info_cp[16]	auto[1]	74	1			T9	1		T23	2		T79	1
reset_info_cp[32]	auto[0]	48	1			T6	1		T79	1		T101	1
reset_info_cp[32]	auto[1]	57	1			T3	1		T9	2		T48	1
reset_info_cp[64]	auto[0]	34	1			T82	2		T145	3		T136	1
reset_info_cp[64]	auto[1]	73	1			T3	2		T8	1		T21	2
reset_info_cp[128]	auto[0]	32	1			T80	1		T124	1		T101	1
reset_info_cp[128]	auto[1]	65	1			T1	1		T21	1		T23	1