Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.88 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T502 /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.62455908 Jan 21 03:32:40 PM PST 24 Jan 21 03:32:41 PM PST 24 74154989 ps
T503 /workspace/coverage/default/36.rstmgr_por_stretcher.1031536149 Jan 21 03:32:37 PM PST 24 Jan 21 03:32:38 PM PST 24 178958735 ps
T504 /workspace/coverage/default/17.rstmgr_stress_all.371461593 Jan 21 03:31:36 PM PST 24 Jan 21 03:31:54 PM PST 24 3747943826 ps
T505 /workspace/coverage/default/43.rstmgr_reset.545444285 Jan 21 03:33:03 PM PST 24 Jan 21 03:33:25 PM PST 24 2119463202 ps
T506 /workspace/coverage/default/4.rstmgr_sw_rst.2933800923 Jan 21 03:30:22 PM PST 24 Jan 21 03:30:26 PM PST 24 335780999 ps
T507 /workspace/coverage/default/0.rstmgr_por_stretcher.2982262249 Jan 21 03:29:59 PM PST 24 Jan 21 03:30:08 PM PST 24 150205443 ps
T508 /workspace/coverage/default/18.rstmgr_sw_rst.2540614053 Jan 21 03:31:41 PM PST 24 Jan 21 03:31:45 PM PST 24 135944440 ps
T509 /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.448467925 Jan 21 03:30:58 PM PST 24 Jan 21 03:31:02 PM PST 24 186365115 ps
T510 /workspace/coverage/default/37.rstmgr_smoke.3861958786 Jan 21 03:32:36 PM PST 24 Jan 21 03:32:38 PM PST 24 200581391 ps
T511 /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.3604355406 Jan 21 03:31:32 PM PST 24 Jan 21 03:31:34 PM PST 24 244153574 ps
T512 /workspace/coverage/default/14.rstmgr_reset.4121960214 Jan 21 03:31:33 PM PST 24 Jan 21 03:31:39 PM PST 24 1432457852 ps
T513 /workspace/coverage/default/1.rstmgr_por_stretcher.3030871793 Jan 21 03:29:56 PM PST 24 Jan 21 03:30:08 PM PST 24 99361014 ps
T514 /workspace/coverage/default/39.rstmgr_stress_all.586196564 Jan 21 03:32:46 PM PST 24 Jan 21 03:33:14 PM PST 24 6928326963 ps
T515 /workspace/coverage/default/40.rstmgr_stress_all.2393180491 Jan 21 03:32:45 PM PST 24 Jan 21 03:33:00 PM PST 24 3266178311 ps
T516 /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.234060128 Jan 21 03:33:27 PM PST 24 Jan 21 03:33:30 PM PST 24 154197390 ps
T517 /workspace/coverage/default/9.rstmgr_stress_all.1897241978 Jan 21 03:31:22 PM PST 24 Jan 21 03:31:29 PM PST 24 1284950612 ps
T518 /workspace/coverage/default/45.rstmgr_reset.3216059537 Jan 21 03:33:17 PM PST 24 Jan 21 03:33:26 PM PST 24 761698619 ps
T519 /workspace/coverage/default/40.rstmgr_smoke.1398227426 Jan 21 03:32:56 PM PST 24 Jan 21 03:33:10 PM PST 24 205833171 ps
T520 /workspace/coverage/default/42.rstmgr_sw_rst.2766912934 Jan 21 03:32:55 PM PST 24 Jan 21 03:33:11 PM PST 24 332167179 ps
T521 /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.559245139 Jan 21 03:31:22 PM PST 24 Jan 21 03:31:25 PM PST 24 287874748 ps
T522 /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.2226213912 Jan 21 03:32:12 PM PST 24 Jan 21 03:32:20 PM PST 24 1892503968 ps
T523 /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.3095405924 Jan 21 03:32:26 PM PST 24 Jan 21 03:32:28 PM PST 24 244033189 ps
T524 /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.1976804019 Jan 21 03:33:26 PM PST 24 Jan 21 03:33:37 PM PST 24 1885541847 ps
T525 /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.2583847691 Jan 21 03:32:08 PM PST 24 Jan 21 03:32:09 PM PST 24 245652320 ps
T526 /workspace/coverage/default/23.rstmgr_alert_test.1070158356 Jan 21 03:31:49 PM PST 24 Jan 21 03:31:51 PM PST 24 80027431 ps
T527 /workspace/coverage/default/38.rstmgr_stress_all.1909390062 Jan 21 03:32:56 PM PST 24 Jan 21 03:33:32 PM PST 24 5798737962 ps
T528 /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.736609130 Jan 21 03:31:46 PM PST 24 Jan 21 03:31:49 PM PST 24 156861586 ps
T529 /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.114237951 Jan 21 03:33:03 PM PST 24 Jan 21 03:33:18 PM PST 24 141150456 ps
T530 /workspace/coverage/default/34.rstmgr_alert_test.1926083503 Jan 21 03:32:39 PM PST 24 Jan 21 03:32:40 PM PST 24 81283971 ps
T531 /workspace/coverage/default/3.rstmgr_alert_test.754459030 Jan 21 03:30:23 PM PST 24 Jan 21 03:30:30 PM PST 24 68900202 ps
T532 /workspace/coverage/default/27.rstmgr_por_stretcher.2009217400 Jan 21 03:32:05 PM PST 24 Jan 21 03:32:07 PM PST 24 135330585 ps
T533 /workspace/coverage/default/33.rstmgr_stress_all.925305527 Jan 21 03:32:40 PM PST 24 Jan 21 03:33:08 PM PST 24 5960211977 ps
T534 /workspace/coverage/default/29.rstmgr_sw_rst.2470215713 Jan 21 03:32:21 PM PST 24 Jan 21 03:32:24 PM PST 24 149914852 ps
T535 /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.2894025831 Jan 21 03:31:38 PM PST 24 Jan 21 03:31:42 PM PST 24 168071019 ps
T536 /workspace/coverage/default/14.rstmgr_stress_all.2960575261 Jan 21 03:31:33 PM PST 24 Jan 21 03:31:46 PM PST 24 2427306855 ps
T537 /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.741292387 Jan 21 03:31:49 PM PST 24 Jan 21 03:31:52 PM PST 24 254157460 ps
T538 /workspace/coverage/default/7.rstmgr_reset.2981152214 Jan 21 03:30:56 PM PST 24 Jan 21 03:31:02 PM PST 24 1272383692 ps
T539 /workspace/coverage/default/13.rstmgr_por_stretcher.249048379 Jan 21 03:31:16 PM PST 24 Jan 21 03:31:18 PM PST 24 123524765 ps
T540 /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.3382409767 Jan 21 03:31:51 PM PST 24 Jan 21 03:32:00 PM PST 24 1886095246 ps
T541 /workspace/coverage/default/0.rstmgr_reset.1929413599 Jan 21 03:29:49 PM PST 24 Jan 21 03:30:01 PM PST 24 1629841674 ps
T542 /workspace/coverage/default/48.rstmgr_alert_test.1896332082 Jan 21 03:33:21 PM PST 24 Jan 21 03:33:27 PM PST 24 87522754 ps
T543 /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.4084741021 Jan 21 03:31:27 PM PST 24 Jan 21 03:31:29 PM PST 24 103523523 ps
T544 /workspace/coverage/default/46.rstmgr_smoke.4137504585 Jan 21 03:33:13 PM PST 24 Jan 21 03:33:23 PM PST 24 238913825 ps
T545 /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.622905635 Jan 21 03:32:46 PM PST 24 Jan 21 03:32:52 PM PST 24 243406081 ps
T546 /workspace/coverage/default/43.rstmgr_por_stretcher.2691451319 Jan 21 03:32:58 PM PST 24 Jan 21 03:33:10 PM PST 24 193487853 ps
T547 /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.3918717540 Jan 21 03:33:21 PM PST 24 Jan 21 03:33:27 PM PST 24 74231516 ps
T548 /workspace/coverage/default/18.rstmgr_alert_test.629108593 Jan 21 03:31:42 PM PST 24 Jan 21 03:31:45 PM PST 24 60659388 ps
T549 /workspace/coverage/default/1.rstmgr_sw_rst.943841860 Jan 21 03:30:07 PM PST 24 Jan 21 03:30:13 PM PST 24 129032705 ps
T550 /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.1149812357 Jan 21 03:32:31 PM PST 24 Jan 21 03:32:33 PM PST 24 164325633 ps
T551 /workspace/coverage/default/32.rstmgr_sw_rst.901168914 Jan 21 03:32:31 PM PST 24 Jan 21 03:32:34 PM PST 24 126411296 ps
T552 /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.3906623249 Jan 21 03:31:40 PM PST 24 Jan 21 03:31:43 PM PST 24 245749570 ps
T553 /workspace/coverage/default/14.rstmgr_smoke.2472645338 Jan 21 03:31:24 PM PST 24 Jan 21 03:31:26 PM PST 24 200911262 ps
T70 /workspace/coverage/default/3.rstmgr_sec_cm.1912939427 Jan 21 03:30:26 PM PST 24 Jan 21 03:30:48 PM PST 24 8298139229 ps
T554 /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.997662675 Jan 21 03:31:06 PM PST 24 Jan 21 03:31:09 PM PST 24 112456117 ps
T555 /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.1565029646 Jan 21 03:30:32 PM PST 24 Jan 21 03:30:35 PM PST 24 244618725 ps
T556 /workspace/coverage/default/22.rstmgr_reset.3967923331 Jan 21 03:31:46 PM PST 24 Jan 21 03:31:52 PM PST 24 815707711 ps
T557 /workspace/coverage/default/42.rstmgr_por_stretcher.1228402259 Jan 21 03:32:59 PM PST 24 Jan 21 03:33:10 PM PST 24 163241000 ps
T558 /workspace/coverage/default/30.rstmgr_smoke.1037459811 Jan 21 03:32:25 PM PST 24 Jan 21 03:32:27 PM PST 24 197625081 ps
T559 /workspace/coverage/default/25.rstmgr_por_stretcher.2933899600 Jan 21 03:31:55 PM PST 24 Jan 21 03:31:58 PM PST 24 114582046 ps
T560 /workspace/coverage/default/44.rstmgr_sw_rst.3831632956 Jan 21 03:33:11 PM PST 24 Jan 21 03:33:22 PM PST 24 326574637 ps
T561 /workspace/coverage/default/47.rstmgr_stress_all.3511378915 Jan 21 03:33:28 PM PST 24 Jan 21 03:33:37 PM PST 24 1251288168 ps
T562 /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.2803707093 Jan 21 03:33:27 PM PST 24 Jan 21 03:33:31 PM PST 24 149783489 ps
T563 /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.2270585432 Jan 21 03:30:49 PM PST 24 Jan 21 03:30:51 PM PST 24 165497740 ps
T564 /workspace/coverage/default/35.rstmgr_por_stretcher.723154867 Jan 21 03:32:40 PM PST 24 Jan 21 03:32:42 PM PST 24 116450121 ps
T565 /workspace/coverage/default/21.rstmgr_reset.3334307850 Jan 21 03:31:36 PM PST 24 Jan 21 03:31:45 PM PST 24 1018330286 ps
T566 /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.2718807745 Jan 21 03:31:18 PM PST 24 Jan 21 03:31:20 PM PST 24 243613307 ps
T567 /workspace/coverage/default/26.rstmgr_stress_all.3701696086 Jan 21 03:32:04 PM PST 24 Jan 21 03:32:33 PM PST 24 7029000786 ps
T568 /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.3750014186 Jan 21 03:31:52 PM PST 24 Jan 21 03:31:55 PM PST 24 120530256 ps
T569 /workspace/coverage/default/15.rstmgr_por_stretcher.1248099983 Jan 21 03:31:35 PM PST 24 Jan 21 03:31:38 PM PST 24 156458599 ps
T570 /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.4160512397 Jan 21 03:32:54 PM PST 24 Jan 21 03:33:07 PM PST 24 245245309 ps
T571 /workspace/coverage/default/28.rstmgr_reset.1085229360 Jan 21 03:32:12 PM PST 24 Jan 21 03:32:18 PM PST 24 1329133187 ps
T572 /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.1636302091 Jan 21 03:32:05 PM PST 24 Jan 21 03:32:07 PM PST 24 95150798 ps
T573 /workspace/coverage/default/41.rstmgr_alert_test.1121019659 Jan 21 03:32:51 PM PST 24 Jan 21 03:32:55 PM PST 24 69123933 ps
T574 /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.3548712357 Jan 21 03:29:52 PM PST 24 Jan 21 03:30:04 PM PST 24 244241057 ps
T575 /workspace/coverage/default/7.rstmgr_alert_test.2335134828 Jan 21 03:30:59 PM PST 24 Jan 21 03:31:02 PM PST 24 79248094 ps
T576 /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.4282920736 Jan 21 03:31:24 PM PST 24 Jan 21 03:31:26 PM PST 24 114610015 ps
T577 /workspace/coverage/default/23.rstmgr_reset.765908433 Jan 21 03:31:55 PM PST 24 Jan 21 03:32:04 PM PST 24 1975708862 ps
T578 /workspace/coverage/default/34.rstmgr_por_stretcher.1302188510 Jan 21 03:32:40 PM PST 24 Jan 21 03:32:41 PM PST 24 90484861 ps
T579 /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.1280402691 Jan 21 03:33:13 PM PST 24 Jan 21 03:33:22 PM PST 24 66277363 ps
T580 /workspace/coverage/default/0.rstmgr_stress_all.2360496779 Jan 21 03:29:59 PM PST 24 Jan 21 03:30:33 PM PST 24 7183714125 ps
T581 /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.2239015165 Jan 21 03:31:30 PM PST 24 Jan 21 03:31:33 PM PST 24 244314961 ps
T582 /workspace/coverage/default/8.rstmgr_reset.1478496838 Jan 21 03:30:56 PM PST 24 Jan 21 03:31:03 PM PST 24 1427132373 ps
T583 /workspace/coverage/default/12.rstmgr_smoke.2320541438 Jan 21 03:31:05 PM PST 24 Jan 21 03:31:09 PM PST 24 203707080 ps
T584 /workspace/coverage/default/4.rstmgr_stress_all.2814264044 Jan 21 03:30:30 PM PST 24 Jan 21 03:30:46 PM PST 24 3110178796 ps
T585 /workspace/coverage/default/21.rstmgr_por_stretcher.2393763715 Jan 21 03:31:35 PM PST 24 Jan 21 03:31:36 PM PST 24 192458455 ps
T586 /workspace/coverage/default/4.rstmgr_reset.1865093288 Jan 21 03:30:26 PM PST 24 Jan 21 03:30:36 PM PST 24 1259007543 ps
T587 /workspace/coverage/default/12.rstmgr_alert_test.2960012421 Jan 21 03:31:15 PM PST 24 Jan 21 03:31:18 PM PST 24 88616729 ps
T588 /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.361864021 Jan 21 03:30:29 PM PST 24 Jan 21 03:30:34 PM PST 24 161236997 ps
T589 /workspace/coverage/default/27.rstmgr_alert_test.4174580916 Jan 21 03:32:18 PM PST 24 Jan 21 03:32:22 PM PST 24 55902500 ps
T590 /workspace/coverage/default/1.rstmgr_reset.3112769599 Jan 21 03:29:55 PM PST 24 Jan 21 03:30:10 PM PST 24 1781747899 ps
T591 /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.3119632331 Jan 21 03:31:49 PM PST 24 Jan 21 03:31:52 PM PST 24 244068378 ps
T592 /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.4268885501 Jan 21 03:31:44 PM PST 24 Jan 21 03:31:46 PM PST 24 143108349 ps
T593 /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.107517994 Jan 21 03:30:41 PM PST 24 Jan 21 03:30:51 PM PST 24 2183381589 ps
T594 /workspace/coverage/default/11.rstmgr_sw_rst.3195559119 Jan 21 05:00:22 PM PST 24 Jan 21 05:00:25 PM PST 24 143028002 ps
T595 /workspace/coverage/default/20.rstmgr_sw_rst.2911507551 Jan 21 03:31:47 PM PST 24 Jan 21 03:31:51 PM PST 24 405949708 ps
T596 /workspace/coverage/default/29.rstmgr_alert_test.3055374930 Jan 21 03:32:25 PM PST 24 Jan 21 03:32:26 PM PST 24 94649684 ps
T597 /workspace/coverage/default/4.rstmgr_smoke.4069854328 Jan 21 03:30:22 PM PST 24 Jan 21 03:30:24 PM PST 24 129900997 ps
T598 /workspace/coverage/default/37.rstmgr_alert_test.4054597090 Jan 21 03:32:49 PM PST 24 Jan 21 03:32:54 PM PST 24 61773078 ps
T599 /workspace/coverage/default/17.rstmgr_reset.4021772488 Jan 21 03:31:30 PM PST 24 Jan 21 03:31:38 PM PST 24 1731584329 ps
T600 /workspace/coverage/default/13.rstmgr_sw_rst.2904476212 Jan 21 03:31:18 PM PST 24 Jan 21 03:31:21 PM PST 24 116115997 ps
T601 /workspace/coverage/default/18.rstmgr_stress_all.2136145636 Jan 21 03:31:42 PM PST 24 Jan 21 03:32:04 PM PST 24 6237325385 ps
T602 /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.2134481467 Jan 21 03:33:13 PM PST 24 Jan 21 03:33:22 PM PST 24 168397756 ps
T603 /workspace/coverage/default/32.rstmgr_stress_all.1328445417 Jan 21 03:32:33 PM PST 24 Jan 21 03:32:45 PM PST 24 2006666906 ps
T604 /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.3394081564 Jan 21 03:31:54 PM PST 24 Jan 21 03:32:04 PM PST 24 2359721006 ps
T605 /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.2429052345 Jan 21 03:31:50 PM PST 24 Jan 21 03:31:52 PM PST 24 142372033 ps
T606 /workspace/coverage/default/44.rstmgr_smoke.2208489193 Jan 21 03:33:03 PM PST 24 Jan 21 03:33:18 PM PST 24 201692339 ps
T607 /workspace/coverage/default/19.rstmgr_alert_test.524572352 Jan 21 03:31:36 PM PST 24 Jan 21 03:31:40 PM PST 24 67487499 ps
T608 /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.857575433 Jan 21 03:30:39 PM PST 24 Jan 21 03:30:42 PM PST 24 151198363 ps
T609 /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.2112074675 Jan 21 03:31:05 PM PST 24 Jan 21 03:31:08 PM PST 24 95396958 ps
T610 /workspace/coverage/default/9.rstmgr_por_stretcher.376141798 Jan 21 03:30:59 PM PST 24 Jan 21 03:31:02 PM PST 24 140950489 ps
T611 /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.2002993749 Jan 21 03:32:31 PM PST 24 Jan 21 03:32:34 PM PST 24 245816546 ps
T612 /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.1724267053 Jan 21 03:31:27 PM PST 24 Jan 21 03:31:29 PM PST 24 245747718 ps
T613 /workspace/coverage/default/33.rstmgr_reset.3071451100 Jan 21 03:32:37 PM PST 24 Jan 21 03:32:43 PM PST 24 1104005567 ps
T614 /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.4215073370 Jan 21 03:32:11 PM PST 24 Jan 21 03:32:13 PM PST 24 98537891 ps
T615 /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.1116961271 Jan 21 03:32:43 PM PST 24 Jan 21 03:32:45 PM PST 24 174902072 ps
T616 /workspace/coverage/default/32.rstmgr_smoke.2620058641 Jan 21 03:32:26 PM PST 24 Jan 21 03:32:28 PM PST 24 253241387 ps
T617 /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.3421027352 Jan 21 03:32:06 PM PST 24 Jan 21 03:32:08 PM PST 24 168577398 ps
T618 /workspace/coverage/default/36.rstmgr_stress_all.238145681 Jan 21 03:32:40 PM PST 24 Jan 21 03:32:45 PM PST 24 1062864739 ps
T619 /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.1496926309 Jan 21 03:29:55 PM PST 24 Jan 21 03:30:13 PM PST 24 1222291083 ps
T620 /workspace/coverage/default/36.rstmgr_reset.1832552766 Jan 21 03:32:57 PM PST 24 Jan 21 03:33:14 PM PST 24 939447565 ps

Test location /workspace/coverage/default/7.rstmgr_smoke.2693527587
Short name T8
Test name
Test status
Simulation time 209075509 ps
CPU time 1.4 seconds
Started Jan 21 03:30:48 PM PST 24
Finished Jan 21 03:30:51 PM PST 24
Peak memory 199744 kb
Host smart-ec9abb2f-753a-47ba-816f-bbeaae0aca38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693527587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.2693527587
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.4080853724
Short name T51
Test name
Test status
Simulation time 112776961 ps
CPU time 1.38 seconds
Started Jan 21 03:30:18 PM PST 24
Finished Jan 21 03:30:21 PM PST 24
Peak memory 199652 kb
Host smart-cbe79b03-c141-47a6-b791-6c190fea7497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080853724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.4080853724
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.1132038298
Short name T23
Test name
Test status
Simulation time 1231671659 ps
CPU time 5.66 seconds
Started Jan 21 03:31:39 PM PST 24
Finished Jan 21 03:31:47 PM PST 24
Peak memory 217236 kb
Host smart-dce168e2-919e-46e6-9b23-0acc50b5a6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132038298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.1132038298
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2618986199
Short name T63
Test name
Test status
Simulation time 825078407 ps
CPU time 2.72 seconds
Started Jan 21 03:03:20 PM PST 24
Finished Jan 21 03:03:23 PM PST 24
Peak memory 199748 kb
Host smart-2cbc2092-b6a9-4f06-a822-d930af43edba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618986199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.2618986199
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.856769594
Short name T66
Test name
Test status
Simulation time 16523666412 ps
CPU time 29.32 seconds
Started Jan 21 03:29:57 PM PST 24
Finished Jan 21 03:30:37 PM PST 24
Peak memory 217664 kb
Host smart-d6827006-a345-4ac7-9270-755461439d15
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856769594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.856769594
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.2347428474
Short name T43
Test name
Test status
Simulation time 13330438932 ps
CPU time 45.28 seconds
Started Jan 21 03:32:10 PM PST 24
Finished Jan 21 03:32:56 PM PST 24
Peak memory 199852 kb
Host smart-1e39af2f-8df3-48c1-8e18-25cf9ce96819
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347428474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.2347428474
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3081526914
Short name T94
Test name
Test status
Simulation time 386488445 ps
CPU time 2.75 seconds
Started Jan 21 03:03:18 PM PST 24
Finished Jan 21 03:03:22 PM PST 24
Peak memory 199824 kb
Host smart-5d53fa58-38fd-40f5-a17d-ea856e5f0646
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081526914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.3081526914
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.3602307069
Short name T4
Test name
Test status
Simulation time 89359817 ps
CPU time 0.8 seconds
Started Jan 21 03:31:29 PM PST 24
Finished Jan 21 03:31:30 PM PST 24
Peak memory 199516 kb
Host smart-92bb97c0-ed0e-408e-9e37-c9e3cafa034f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602307069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.3602307069
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1131708931
Short name T60
Test name
Test status
Simulation time 169027975 ps
CPU time 1.15 seconds
Started Jan 21 03:03:19 PM PST 24
Finished Jan 21 03:03:21 PM PST 24
Peak memory 199648 kb
Host smart-b34f81a6-50a2-42ff-bf07-cc0ade0e78e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131708931 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.1131708931
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.1754212062
Short name T281
Test name
Test status
Simulation time 8558853849 ps
CPU time 39.33 seconds
Started Jan 21 03:31:42 PM PST 24
Finished Jan 21 03:32:23 PM PST 24
Peak memory 199848 kb
Host smart-7e59e52f-6dac-4d7b-8caa-fd2970fe52af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754212062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.1754212062
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.3210718944
Short name T46
Test name
Test status
Simulation time 104820864 ps
CPU time 0.99 seconds
Started Jan 21 03:31:16 PM PST 24
Finished Jan 21 03:31:18 PM PST 24
Peak memory 199464 kb
Host smart-86cb6c36-a7fb-440c-a7de-3f8faf6f8465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210718944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.3210718944
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.2673986673
Short name T24
Test name
Test status
Simulation time 1218582794 ps
CPU time 5.49 seconds
Started Jan 21 03:32:16 PM PST 24
Finished Jan 21 03:32:23 PM PST 24
Peak memory 218140 kb
Host smart-058322cb-ed0e-4999-95e9-bc526702fb27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673986673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.2673986673
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.727826574
Short name T125
Test name
Test status
Simulation time 927948530 ps
CPU time 3.25 seconds
Started Jan 21 03:03:31 PM PST 24
Finished Jan 21 03:03:35 PM PST 24
Peak memory 199856 kb
Host smart-33bb2bc0-db0e-447b-9038-1c10f1de5ee8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727826574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_err
.727826574
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.3265038125
Short name T111
Test name
Test status
Simulation time 6587294557 ps
CPU time 33.02 seconds
Started Jan 21 03:32:02 PM PST 24
Finished Jan 21 03:32:36 PM PST 24
Peak memory 199896 kb
Host smart-75a4a3f1-0aef-4754-97e3-8adaf73169bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265038125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.3265038125
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.4006728009
Short name T28
Test name
Test status
Simulation time 1215499279 ps
CPU time 5.91 seconds
Started Jan 21 03:31:07 PM PST 24
Finished Jan 21 03:31:14 PM PST 24
Peak memory 220576 kb
Host smart-4bbb4244-af88-4781-8010-a74e0aa46720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006728009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.4006728009
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.631786287
Short name T129
Test name
Test status
Simulation time 877866361 ps
CPU time 3.14 seconds
Started Jan 21 03:03:39 PM PST 24
Finished Jan 21 03:03:49 PM PST 24
Peak memory 199868 kb
Host smart-f3a7f4a9-fe21-4f1b-b8c8-59c9b37b2d72
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631786287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_err
.631786287
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.4127862106
Short name T145
Test name
Test status
Simulation time 173539678 ps
CPU time 1.34 seconds
Started Jan 21 03:31:35 PM PST 24
Finished Jan 21 03:31:38 PM PST 24
Peak memory 199764 kb
Host smart-ca48d0ce-8258-41c9-9123-35ea9fa82152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127862106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.4127862106
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.3288798535
Short name T64
Test name
Test status
Simulation time 168456753 ps
CPU time 2.36 seconds
Started Jan 21 03:03:10 PM PST 24
Finished Jan 21 03:03:14 PM PST 24
Peak memory 199844 kb
Host smart-4e421f27-5b01-49a0-bf46-074a92bd21ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288798535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.3288798535
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2536415389
Short name T123
Test name
Test status
Simulation time 272244449 ps
CPU time 1.51 seconds
Started Jan 21 03:02:52 PM PST 24
Finished Jan 21 03:02:55 PM PST 24
Peak memory 199812 kb
Host smart-5e7f9b90-db2d-4010-9b04-4d21d63948f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536415389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.2536415389
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.1294760220
Short name T17
Test name
Test status
Simulation time 192236197 ps
CPU time 0.85 seconds
Started Jan 21 03:31:05 PM PST 24
Finished Jan 21 03:31:08 PM PST 24
Peak memory 199400 kb
Host smart-1d4a56fe-c90b-4a91-bac1-c1812af9be66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294760220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.1294760220
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.271027786
Short name T108
Test name
Test status
Simulation time 245083062 ps
CPU time 1.06 seconds
Started Jan 21 04:05:13 PM PST 24
Finished Jan 21 04:05:16 PM PST 24
Peak memory 216932 kb
Host smart-8265cca7-7749-48b9-ba59-ff7807af0bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271027786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.271027786
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.1041419218
Short name T128
Test name
Test status
Simulation time 467237787 ps
CPU time 1.75 seconds
Started Jan 21 03:02:58 PM PST 24
Finished Jan 21 03:03:00 PM PST 24
Peak memory 199824 kb
Host smart-6aaae73c-c491-4cc8-8d65-1b32ffa27b4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041419218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.1041419218
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2459215429
Short name T177
Test name
Test status
Simulation time 106910712 ps
CPU time 1.3 seconds
Started Jan 21 03:11:56 PM PST 24
Finished Jan 21 03:11:58 PM PST 24
Peak memory 199752 kb
Host smart-70b5c7e2-560e-47da-88a1-0a1c0ecf0a35
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459215429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.2
459215429
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.4110945993
Short name T203
Test name
Test status
Simulation time 1197407264 ps
CPU time 5.01 seconds
Started Jan 21 03:02:55 PM PST 24
Finished Jan 21 03:03:00 PM PST 24
Peak memory 199688 kb
Host smart-6bca0c34-2e51-46b4-af6c-f2b9d38833a6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110945993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.4
110945993
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.4229405110
Short name T175
Test name
Test status
Simulation time 132690715 ps
CPU time 0.86 seconds
Started Jan 21 03:03:03 PM PST 24
Finished Jan 21 03:03:04 PM PST 24
Peak memory 199684 kb
Host smart-d6a06f0f-ebf8-4f7e-b6dd-616be1c61c2a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229405110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.4
229405110
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.781544637
Short name T226
Test name
Test status
Simulation time 106701720 ps
CPU time 0.96 seconds
Started Jan 21 03:03:00 PM PST 24
Finished Jan 21 03:03:02 PM PST 24
Peak memory 199648 kb
Host smart-73440c40-24a4-4dc1-830d-bbf65b915540
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781544637 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.781544637
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.1580300625
Short name T100
Test name
Test status
Simulation time 71831851 ps
CPU time 0.81 seconds
Started Jan 21 03:02:48 PM PST 24
Finished Jan 21 03:02:49 PM PST 24
Peak memory 199684 kb
Host smart-374d9509-e7b2-4f05-8955-4488e2a7594c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580300625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.1580300625
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.45618441
Short name T239
Test name
Test status
Simulation time 91023011 ps
CPU time 1.13 seconds
Started Jan 21 03:13:54 PM PST 24
Finished Jan 21 03:13:56 PM PST 24
Peak memory 199612 kb
Host smart-35f1b50d-3f69-4419-8ef2-abfdfaaf05a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45618441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.45618441
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2697765259
Short name T131
Test name
Test status
Simulation time 907876243 ps
CPU time 2.98 seconds
Started Jan 21 03:11:20 PM PST 24
Finished Jan 21 03:11:24 PM PST 24
Peak memory 199760 kb
Host smart-2f412b3b-15cf-4abd-a1c3-312bc9d2fd36
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697765259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.2697765259
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2964074778
Short name T114
Test name
Test status
Simulation time 105574639 ps
CPU time 1.32 seconds
Started Jan 21 03:02:57 PM PST 24
Finished Jan 21 03:02:59 PM PST 24
Peak memory 199708 kb
Host smart-a2aca19b-9c34-41e4-af76-1decfd3d5afc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964074778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.2
964074778
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1706730024
Short name T236
Test name
Test status
Simulation time 2298333101 ps
CPU time 9.5 seconds
Started Jan 21 03:02:51 PM PST 24
Finished Jan 21 03:03:02 PM PST 24
Peak memory 199880 kb
Host smart-5e504029-5928-4349-baeb-1aa201f2641f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706730024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.1
706730024
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.3409851505
Short name T113
Test name
Test status
Simulation time 93699882 ps
CPU time 0.8 seconds
Started Jan 21 03:03:11 PM PST 24
Finished Jan 21 03:03:12 PM PST 24
Peak memory 199672 kb
Host smart-13265b03-2b33-4fce-a2f2-7f7583859fc6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409851505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.3
409851505
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.1027181281
Short name T223
Test name
Test status
Simulation time 98898685 ps
CPU time 0.87 seconds
Started Jan 21 03:03:11 PM PST 24
Finished Jan 21 03:03:13 PM PST 24
Peak memory 199692 kb
Host smart-d36da6c8-9455-492b-ac28-b39f4cfea7c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027181281 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.1027181281
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.3934457102
Short name T176
Test name
Test status
Simulation time 88358365 ps
CPU time 0.82 seconds
Started Jan 21 03:03:00 PM PST 24
Finished Jan 21 03:03:01 PM PST 24
Peak memory 199580 kb
Host smart-ab9af7bd-99fd-4994-ac0a-91780895cf12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934457102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.3934457102
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3344975010
Short name T222
Test name
Test status
Simulation time 279161086 ps
CPU time 1.53 seconds
Started Jan 21 03:03:11 PM PST 24
Finished Jan 21 03:03:14 PM PST 24
Peak memory 199860 kb
Host smart-f6bc5157-246d-4285-82a6-e8042694bd37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344975010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.3344975010
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3072216255
Short name T201
Test name
Test status
Simulation time 422071145 ps
CPU time 1.87 seconds
Started Jan 21 03:03:00 PM PST 24
Finished Jan 21 03:03:03 PM PST 24
Peak memory 199880 kb
Host smart-32b3ea71-b95f-4eed-a865-baccfff7f7f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072216255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.3072216255
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1184248577
Short name T196
Test name
Test status
Simulation time 131447200 ps
CPU time 1.41 seconds
Started Jan 21 03:03:30 PM PST 24
Finished Jan 21 03:03:32 PM PST 24
Peak memory 199708 kb
Host smart-dd969901-d4c4-44b1-a529-50495c1eeeb5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184248577 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.1184248577
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.3703467466
Short name T205
Test name
Test status
Simulation time 70955064 ps
CPU time 0.75 seconds
Started Jan 21 03:03:30 PM PST 24
Finished Jan 21 03:03:32 PM PST 24
Peak memory 199696 kb
Host smart-9819f920-6811-4aca-bcfb-d0f9769986ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703467466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.3703467466
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1041011905
Short name T118
Test name
Test status
Simulation time 98942359 ps
CPU time 1.27 seconds
Started Jan 21 03:03:34 PM PST 24
Finished Jan 21 03:03:39 PM PST 24
Peak memory 199812 kb
Host smart-20283a16-8c16-45db-903f-758be44e6001
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041011905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.1041011905
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.4215355030
Short name T210
Test name
Test status
Simulation time 173815497 ps
CPU time 2.58 seconds
Started Jan 21 03:03:29 PM PST 24
Finished Jan 21 03:03:32 PM PST 24
Peak memory 208096 kb
Host smart-0c3eaa7f-9fed-4149-bef5-b84dc3d86509
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215355030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.4215355030
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3070540430
Short name T197
Test name
Test status
Simulation time 148244826 ps
CPU time 1.45 seconds
Started Jan 21 03:03:48 PM PST 24
Finished Jan 21 03:03:53 PM PST 24
Peak memory 209488 kb
Host smart-9e0fdbb0-53c7-46d7-90b4-753368331998
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070540430 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.3070540430
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.329189793
Short name T229
Test name
Test status
Simulation time 72993395 ps
CPU time 0.75 seconds
Started Jan 21 03:03:48 PM PST 24
Finished Jan 21 03:03:53 PM PST 24
Peak memory 199524 kb
Host smart-e2f3bc8d-2d7c-49fc-bc8b-e104097436b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329189793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.329189793
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.4192588223
Short name T121
Test name
Test status
Simulation time 132616084 ps
CPU time 1.03 seconds
Started Jan 21 03:03:49 PM PST 24
Finished Jan 21 03:03:53 PM PST 24
Peak memory 199420 kb
Host smart-2535454c-78b7-4134-a297-241d8a7cc4d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192588223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.4192588223
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.212392199
Short name T238
Test name
Test status
Simulation time 372821144 ps
CPU time 2.77 seconds
Started Jan 21 03:03:31 PM PST 24
Finished Jan 21 03:03:35 PM PST 24
Peak memory 199848 kb
Host smart-8513e033-0d95-4a4a-834d-a3b526af3c08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212392199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.212392199
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.2522480766
Short name T193
Test name
Test status
Simulation time 425783491 ps
CPU time 1.78 seconds
Started Jan 21 03:03:47 PM PST 24
Finished Jan 21 03:03:52 PM PST 24
Peak memory 199780 kb
Host smart-47a562e9-1c1d-428a-b14e-91560e9a5533
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522480766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.2522480766
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.3040338840
Short name T214
Test name
Test status
Simulation time 113857028 ps
CPU time 0.93 seconds
Started Jan 21 03:03:48 PM PST 24
Finished Jan 21 03:03:53 PM PST 24
Peak memory 199500 kb
Host smart-4263741f-f3a1-4350-8961-5f2dc1e781bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040338840 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.3040338840
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.1133653237
Short name T172
Test name
Test status
Simulation time 64398369 ps
CPU time 0.78 seconds
Started Jan 21 03:03:48 PM PST 24
Finished Jan 21 03:03:53 PM PST 24
Peak memory 199580 kb
Host smart-e9400969-4cb8-47b2-99fe-fa1b46eef954
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133653237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.1133653237
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1730807714
Short name T183
Test name
Test status
Simulation time 138117561 ps
CPU time 1.15 seconds
Started Jan 21 03:03:41 PM PST 24
Finished Jan 21 03:03:48 PM PST 24
Peak memory 199548 kb
Host smart-6662e2da-aa88-4938-aca5-011b70145cf6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730807714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.1730807714
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3872985113
Short name T185
Test name
Test status
Simulation time 199902960 ps
CPU time 2.87 seconds
Started Jan 21 03:03:50 PM PST 24
Finished Jan 21 03:03:55 PM PST 24
Peak memory 199940 kb
Host smart-dace5985-89ce-43e3-8a23-ed785e1e8fa5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872985113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.3872985113
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.1248823428
Short name T182
Test name
Test status
Simulation time 130284923 ps
CPU time 1.1 seconds
Started Jan 21 03:03:47 PM PST 24
Finished Jan 21 03:03:51 PM PST 24
Peak memory 199716 kb
Host smart-8ae37b3c-5fbe-4607-8126-38fbffabd2ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248823428 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.1248823428
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.1389208601
Short name T186
Test name
Test status
Simulation time 72401252 ps
CPU time 0.76 seconds
Started Jan 21 03:03:48 PM PST 24
Finished Jan 21 03:03:53 PM PST 24
Peak memory 199596 kb
Host smart-68695e53-4286-4efa-bd78-235ca3a787ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389208601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.1389208601
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.803547606
Short name T181
Test name
Test status
Simulation time 203655390 ps
CPU time 1.45 seconds
Started Jan 21 03:03:46 PM PST 24
Finished Jan 21 03:03:51 PM PST 24
Peak memory 199780 kb
Host smart-d09cf9d6-338d-475e-b856-3ac8cdb350d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803547606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_sa
me_csr_outstanding.803547606
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3390671324
Short name T200
Test name
Test status
Simulation time 208917280 ps
CPU time 3.07 seconds
Started Jan 21 03:03:39 PM PST 24
Finished Jan 21 03:03:48 PM PST 24
Peak memory 199832 kb
Host smart-31906c9e-63a3-44f2-9af8-c742d6ea3d18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390671324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.3390671324
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1891896856
Short name T142
Test name
Test status
Simulation time 414780447 ps
CPU time 1.96 seconds
Started Jan 21 03:03:42 PM PST 24
Finished Jan 21 03:03:48 PM PST 24
Peak memory 199768 kb
Host smart-44030751-92f1-460c-b6ea-5c60dbac2034
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891896856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.1891896856
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2696705523
Short name T61
Test name
Test status
Simulation time 187235869 ps
CPU time 1.33 seconds
Started Jan 21 03:03:48 PM PST 24
Finished Jan 21 03:03:54 PM PST 24
Peak memory 199732 kb
Host smart-bbd17c5d-b188-4e29-82fb-e48451fa6ce1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696705523 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.2696705523
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3040302448
Short name T230
Test name
Test status
Simulation time 72617952 ps
CPU time 0.85 seconds
Started Jan 21 03:03:42 PM PST 24
Finished Jan 21 03:03:47 PM PST 24
Peak memory 199632 kb
Host smart-ff806f0b-5374-42c7-8add-d15a892107b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040302448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.3040302448
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.970324048
Short name T119
Test name
Test status
Simulation time 72450244 ps
CPU time 0.92 seconds
Started Jan 21 03:03:50 PM PST 24
Finished Jan 21 03:03:56 PM PST 24
Peak memory 199696 kb
Host smart-fb9a4acf-a7a2-4bd2-824c-250d1db04b80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970324048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_sa
me_csr_outstanding.970324048
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.269342778
Short name T95
Test name
Test status
Simulation time 240374480 ps
CPU time 1.99 seconds
Started Jan 21 03:03:47 PM PST 24
Finished Jan 21 03:03:54 PM PST 24
Peak memory 208100 kb
Host smart-85d16c6c-337e-400a-b052-5abea83ca632
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269342778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.269342778
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.68664217
Short name T213
Test name
Test status
Simulation time 485196998 ps
CPU time 1.91 seconds
Started Jan 21 03:03:50 PM PST 24
Finished Jan 21 03:03:55 PM PST 24
Peak memory 199844 kb
Host smart-a1470935-8654-4f1b-b5be-e297dcb606a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68664217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_err.68664217
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2367521285
Short name T235
Test name
Test status
Simulation time 135564704 ps
CPU time 1.48 seconds
Started Jan 21 03:03:54 PM PST 24
Finished Jan 21 03:04:02 PM PST 24
Peak memory 208620 kb
Host smart-b5284aed-beda-4acc-ac9e-5bdc68350f7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367521285 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.2367521285
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.1603691381
Short name T216
Test name
Test status
Simulation time 69954257 ps
CPU time 0.82 seconds
Started Jan 21 03:03:49 PM PST 24
Finished Jan 21 03:03:53 PM PST 24
Peak memory 199696 kb
Host smart-fd56c5fa-71b6-4993-b72b-2abda3d27b5a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603691381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.1603691381
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3870618261
Short name T232
Test name
Test status
Simulation time 196122011 ps
CPU time 1.44 seconds
Started Jan 21 03:03:47 PM PST 24
Finished Jan 21 03:03:52 PM PST 24
Peak memory 199832 kb
Host smart-2dc3042d-2c26-48b4-ba68-74b20a4be6f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870618261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.3870618261
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.1605501514
Short name T224
Test name
Test status
Simulation time 514359877 ps
CPU time 3.29 seconds
Started Jan 21 03:03:48 PM PST 24
Finished Jan 21 03:03:56 PM PST 24
Peak memory 208076 kb
Host smart-d84f5999-b087-4a27-b006-bb21d620c7e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605501514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.1605501514
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.2101146067
Short name T99
Test name
Test status
Simulation time 885122188 ps
CPU time 3.45 seconds
Started Jan 21 03:03:48 PM PST 24
Finished Jan 21 03:03:56 PM PST 24
Peak memory 199836 kb
Host smart-b6f4aa57-8b75-45a4-8904-e0d89e1ea1b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101146067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.2101146067
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.1408947204
Short name T212
Test name
Test status
Simulation time 119860587 ps
CPU time 1.37 seconds
Started Jan 21 03:03:53 PM PST 24
Finished Jan 21 03:04:01 PM PST 24
Peak memory 208060 kb
Host smart-8709cb6c-4eee-4cc8-b937-5b53c625998e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408947204 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.1408947204
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.3995122386
Short name T218
Test name
Test status
Simulation time 82449953 ps
CPU time 0.81 seconds
Started Jan 21 03:46:41 PM PST 24
Finished Jan 21 03:46:44 PM PST 24
Peak memory 199712 kb
Host smart-f5ab7cb6-1597-466c-9095-dbcd44096cc2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995122386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.3995122386
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1974309301
Short name T133
Test name
Test status
Simulation time 242988943 ps
CPU time 1.53 seconds
Started Jan 21 03:03:54 PM PST 24
Finished Jan 21 03:04:02 PM PST 24
Peak memory 199720 kb
Host smart-0e1b9f44-8e5f-457c-a5cd-50173a7397a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974309301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.1974309301
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3191399367
Short name T97
Test name
Test status
Simulation time 443830575 ps
CPU time 3.31 seconds
Started Jan 21 03:03:53 PM PST 24
Finished Jan 21 03:04:03 PM PST 24
Peak memory 215448 kb
Host smart-3dcd210b-3791-4b7c-8188-a66e32604af2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191399367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.3191399367
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3217761013
Short name T127
Test name
Test status
Simulation time 784701361 ps
CPU time 3.01 seconds
Started Jan 21 03:03:51 PM PST 24
Finished Jan 21 03:03:58 PM PST 24
Peak memory 199688 kb
Host smart-1fd193ea-a0e9-4d73-a6f7-cac019378083
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217761013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.3217761013
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2093913272
Short name T62
Test name
Test status
Simulation time 122070352 ps
CPU time 1 seconds
Started Jan 21 03:03:57 PM PST 24
Finished Jan 21 03:04:06 PM PST 24
Peak memory 199620 kb
Host smart-3b87d929-31c7-4f59-83f1-22c35c5a3537
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093913272 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.2093913272
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.1637774942
Short name T115
Test name
Test status
Simulation time 84198159 ps
CPU time 1 seconds
Started Jan 21 04:46:48 PM PST 24
Finished Jan 21 04:46:55 PM PST 24
Peak memory 199716 kb
Host smart-ad191a28-283b-413e-a57d-a1d2f898ebfe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637774942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.1637774942
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2743073299
Short name T240
Test name
Test status
Simulation time 120568380 ps
CPU time 1.04 seconds
Started Jan 21 03:03:52 PM PST 24
Finished Jan 21 03:03:56 PM PST 24
Peak memory 199568 kb
Host smart-6942db0f-ac27-4813-8bdc-91e11855071a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743073299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.2743073299
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2936676017
Short name T204
Test name
Test status
Simulation time 174248910 ps
CPU time 2.52 seconds
Started Jan 21 03:04:02 PM PST 24
Finished Jan 21 03:04:11 PM PST 24
Peak memory 199868 kb
Host smart-f54cd651-1a09-42e5-8f67-8e112ef02644
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936676017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.2936676017
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2902282072
Short name T206
Test name
Test status
Simulation time 488543942 ps
CPU time 2.12 seconds
Started Jan 21 03:03:59 PM PST 24
Finished Jan 21 03:04:08 PM PST 24
Peak memory 199856 kb
Host smart-388701b6-7196-43bc-8e0e-6f0623597ed2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902282072 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.2902282072
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1380818382
Short name T233
Test name
Test status
Simulation time 144690473 ps
CPU time 1.03 seconds
Started Jan 21 03:04:03 PM PST 24
Finished Jan 21 03:04:10 PM PST 24
Peak memory 199756 kb
Host smart-b409062c-cae7-4d69-848e-9ee452047c59
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380818382 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.1380818382
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3020401881
Short name T53
Test name
Test status
Simulation time 55782897 ps
CPU time 0.74 seconds
Started Jan 21 03:04:03 PM PST 24
Finished Jan 21 03:04:09 PM PST 24
Peak memory 199672 kb
Host smart-a61d71f9-e6a5-4cd9-9ef7-f5d5d211216b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020401881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.3020401881
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.404267568
Short name T179
Test name
Test status
Simulation time 117157117 ps
CPU time 1.02 seconds
Started Jan 21 03:04:03 PM PST 24
Finished Jan 21 03:04:10 PM PST 24
Peak memory 199704 kb
Host smart-7e030bef-a1dd-43d1-baaa-ffe95cbb4538
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404267568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_sa
me_csr_outstanding.404267568
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.646835395
Short name T198
Test name
Test status
Simulation time 291571990 ps
CPU time 2.15 seconds
Started Jan 21 03:03:54 PM PST 24
Finished Jan 21 03:04:03 PM PST 24
Peak memory 199952 kb
Host smart-4c71aed3-22b8-4976-9e87-c4008025220d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646835395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.646835395
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.207015896
Short name T231
Test name
Test status
Simulation time 497866754 ps
CPU time 1.96 seconds
Started Jan 21 04:02:44 PM PST 24
Finished Jan 21 04:02:49 PM PST 24
Peak memory 199856 kb
Host smart-f22c0c0e-479c-43d5-ac3a-9d864eb2c618
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207015896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_err
.207015896
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3116787603
Short name T174
Test name
Test status
Simulation time 143651821 ps
CPU time 1.32 seconds
Started Jan 21 03:04:06 PM PST 24
Finished Jan 21 03:04:10 PM PST 24
Peak memory 199892 kb
Host smart-54d8b854-3a91-48c7-ac46-96612697cd70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116787603 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.3116787603
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.3177395786
Short name T56
Test name
Test status
Simulation time 79281875 ps
CPU time 0.84 seconds
Started Jan 21 03:04:11 PM PST 24
Finished Jan 21 03:04:13 PM PST 24
Peak memory 199684 kb
Host smart-4c080f36-7b0b-45b1-b9c5-432177a53da1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177395786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.3177395786
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.819113659
Short name T225
Test name
Test status
Simulation time 143041814 ps
CPU time 1.11 seconds
Started Jan 21 03:04:12 PM PST 24
Finished Jan 21 03:04:14 PM PST 24
Peak memory 199688 kb
Host smart-4da8b1c2-442e-4336-9f30-59cc19342a37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819113659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_sa
me_csr_outstanding.819113659
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.1168676670
Short name T93
Test name
Test status
Simulation time 196155596 ps
CPU time 2.75 seconds
Started Jan 21 03:04:14 PM PST 24
Finished Jan 21 03:04:19 PM PST 24
Peak memory 199828 kb
Host smart-94d719c3-8d72-4014-93f5-d548a5547e97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168676670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.1168676670
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2610438634
Short name T143
Test name
Test status
Simulation time 425364233 ps
CPU time 1.64 seconds
Started Jan 21 03:04:02 PM PST 24
Finished Jan 21 03:04:10 PM PST 24
Peak memory 199844 kb
Host smart-00d2e88a-2a92-4a78-af2e-e1064158f26a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610438634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.2610438634
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.395842976
Short name T211
Test name
Test status
Simulation time 399200641 ps
CPU time 2.53 seconds
Started Jan 21 03:09:20 PM PST 24
Finished Jan 21 03:09:23 PM PST 24
Peak memory 199816 kb
Host smart-4971b6b0-7c81-4828-8a7f-d7a881949908
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395842976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.395842976
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.2231194595
Short name T58
Test name
Test status
Simulation time 799871199 ps
CPU time 4.46 seconds
Started Jan 21 03:03:06 PM PST 24
Finished Jan 21 03:03:13 PM PST 24
Peak memory 199728 kb
Host smart-3feef500-37ad-44dd-86d3-aad47ba3f460
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231194595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.2
231194595
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1736440817
Short name T55
Test name
Test status
Simulation time 123150468 ps
CPU time 0.88 seconds
Started Jan 21 03:03:10 PM PST 24
Finished Jan 21 03:03:12 PM PST 24
Peak memory 199712 kb
Host smart-ff4864aa-1938-4c26-a579-644cdebca024
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736440817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.1
736440817
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.872462054
Short name T191
Test name
Test status
Simulation time 177034556 ps
CPU time 1.18 seconds
Started Jan 21 03:26:20 PM PST 24
Finished Jan 21 03:26:22 PM PST 24
Peak memory 199764 kb
Host smart-8ad9a4f0-48e1-4efe-9960-676941af159e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872462054 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.872462054
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3767907491
Short name T189
Test name
Test status
Simulation time 65780537 ps
CPU time 0.75 seconds
Started Jan 21 03:03:06 PM PST 24
Finished Jan 21 03:03:09 PM PST 24
Peak memory 199676 kb
Host smart-ca41e925-74aa-44d0-a37d-47451f058c3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767907491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.3767907491
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.3800728742
Short name T173
Test name
Test status
Simulation time 104291066 ps
CPU time 1.25 seconds
Started Jan 21 03:03:08 PM PST 24
Finished Jan 21 03:03:10 PM PST 24
Peak memory 199872 kb
Host smart-bba6629a-8a97-4aaa-b665-0548b02f2379
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800728742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.3800728742
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.3511427559
Short name T96
Test name
Test status
Simulation time 135611004 ps
CPU time 1.72 seconds
Started Jan 21 03:03:08 PM PST 24
Finished Jan 21 03:03:11 PM PST 24
Peak memory 199860 kb
Host smart-51c1ad60-6227-4a2b-b208-8d4d2a0017d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511427559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.3511427559
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3150637685
Short name T130
Test name
Test status
Simulation time 471239485 ps
CPU time 1.84 seconds
Started Jan 21 03:03:00 PM PST 24
Finished Jan 21 03:03:03 PM PST 24
Peak memory 199684 kb
Host smart-60da4ce0-2e33-4f46-940e-39f06548b028
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150637685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.3150637685
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.2012063546
Short name T112
Test name
Test status
Simulation time 106029356 ps
CPU time 1.32 seconds
Started Jan 21 03:23:06 PM PST 24
Finished Jan 21 03:23:09 PM PST 24
Peak memory 199852 kb
Host smart-53620b4c-b269-4c1d-a1c2-b26fe3d8860e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012063546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.2
012063546
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.3139618437
Short name T215
Test name
Test status
Simulation time 268532684 ps
CPU time 3.08 seconds
Started Jan 21 03:19:22 PM PST 24
Finished Jan 21 03:19:26 PM PST 24
Peak memory 199804 kb
Host smart-0c8dc88a-f6d3-41f3-9faa-d1cd83d51ffc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139618437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.3
139618437
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1188318149
Short name T234
Test name
Test status
Simulation time 148537023 ps
CPU time 0.92 seconds
Started Jan 21 03:23:10 PM PST 24
Finished Jan 21 03:23:12 PM PST 24
Peak memory 199676 kb
Host smart-dbb58beb-b9dc-458a-9c17-f479cf0263ca
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188318149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.1
188318149
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.2767320831
Short name T178
Test name
Test status
Simulation time 75275568 ps
CPU time 0.8 seconds
Started Jan 21 03:03:07 PM PST 24
Finished Jan 21 03:03:10 PM PST 24
Peak memory 199576 kb
Host smart-5d183e9d-70df-4bf7-9dc2-566c338b742a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767320831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.2767320831
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1295039518
Short name T202
Test name
Test status
Simulation time 74488815 ps
CPU time 0.92 seconds
Started Jan 21 03:03:01 PM PST 24
Finished Jan 21 03:03:03 PM PST 24
Peak memory 199696 kb
Host smart-0c5c7eec-f2a0-4398-8d7f-fda7edba254f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295039518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.1295039518
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.3458715829
Short name T180
Test name
Test status
Simulation time 137277725 ps
CPU time 1.98 seconds
Started Jan 21 03:03:04 PM PST 24
Finished Jan 21 03:03:07 PM PST 24
Peak memory 199840 kb
Host smart-d6ea7eba-b86d-4160-adae-777c158fde0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458715829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.3458715829
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.569088656
Short name T171
Test name
Test status
Simulation time 361399481 ps
CPU time 2.39 seconds
Started Jan 21 03:03:11 PM PST 24
Finished Jan 21 03:03:14 PM PST 24
Peak memory 199804 kb
Host smart-efe710f6-00fb-4df5-9f9b-da4dd601c68d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569088656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.569088656
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1183496441
Short name T184
Test name
Test status
Simulation time 1548259851 ps
CPU time 9.07 seconds
Started Jan 21 03:03:08 PM PST 24
Finished Jan 21 03:03:19 PM PST 24
Peak memory 199632 kb
Host smart-a1e77f2c-85e0-4f6c-bb1b-37a6dd899a6f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183496441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.1
183496441
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1095611737
Short name T207
Test name
Test status
Simulation time 130704968 ps
CPU time 0.95 seconds
Started Jan 21 03:03:08 PM PST 24
Finished Jan 21 03:03:10 PM PST 24
Peak memory 199604 kb
Host smart-ace33986-abb5-401c-a43e-87b40411ae9f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095611737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.1
095611737
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.4135564733
Short name T190
Test name
Test status
Simulation time 168784565 ps
CPU time 1.13 seconds
Started Jan 21 03:03:08 PM PST 24
Finished Jan 21 03:03:11 PM PST 24
Peak memory 199748 kb
Host smart-4192f0a3-2876-467f-bf80-be01bee3da7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135564733 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.4135564733
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.4125845266
Short name T237
Test name
Test status
Simulation time 59617712 ps
CPU time 0.74 seconds
Started Jan 21 03:03:09 PM PST 24
Finished Jan 21 03:03:10 PM PST 24
Peak memory 199632 kb
Host smart-91dd7620-38da-4881-ac2a-2298342fe3b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125845266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.4125845266
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3152280730
Short name T208
Test name
Test status
Simulation time 186664740 ps
CPU time 1.44 seconds
Started Jan 21 03:03:11 PM PST 24
Finished Jan 21 03:03:13 PM PST 24
Peak memory 199724 kb
Host smart-6d139248-121f-4d51-b858-6459c9ccd64d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152280730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.3152280730
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.2836034896
Short name T91
Test name
Test status
Simulation time 114406337 ps
CPU time 1.74 seconds
Started Jan 21 03:03:17 PM PST 24
Finished Jan 21 03:03:20 PM PST 24
Peak memory 199872 kb
Host smart-98c101e0-ead6-49e5-896f-2f7fcbd32531
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836034896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.2836034896
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2882070274
Short name T126
Test name
Test status
Simulation time 491908568 ps
CPU time 2.05 seconds
Started Jan 21 03:03:09 PM PST 24
Finished Jan 21 03:03:12 PM PST 24
Peak memory 199824 kb
Host smart-69b71c86-19ca-471e-a1e6-5469b971d7f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882070274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.2882070274
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3768436316
Short name T134
Test name
Test status
Simulation time 146192696 ps
CPU time 1.04 seconds
Started Jan 21 03:03:22 PM PST 24
Finished Jan 21 03:03:24 PM PST 24
Peak memory 199640 kb
Host smart-cf8cce47-e6df-4560-abce-cf527e659494
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768436316 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.3768436316
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1733212142
Short name T187
Test name
Test status
Simulation time 73940405 ps
CPU time 0.88 seconds
Started Jan 21 03:03:21 PM PST 24
Finished Jan 21 03:03:23 PM PST 24
Peak memory 199556 kb
Host smart-75511e3f-b791-4110-ae87-7e0524adee29
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733212142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.1733212142
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3924578717
Short name T195
Test name
Test status
Simulation time 87232000 ps
CPU time 0.95 seconds
Started Jan 21 03:03:21 PM PST 24
Finished Jan 21 03:03:23 PM PST 24
Peak memory 198768 kb
Host smart-ba6ffda6-a912-41bf-97d8-a0b673dfe662
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924578717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.3924578717
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.3304440268
Short name T188
Test name
Test status
Simulation time 287289128 ps
CPU time 1.89 seconds
Started Jan 21 03:03:24 PM PST 24
Finished Jan 21 03:03:27 PM PST 24
Peak memory 207996 kb
Host smart-8fc1a825-54c3-4aaa-85b8-ba6c0d2f480c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304440268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.3304440268
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.319498308
Short name T220
Test name
Test status
Simulation time 128950561 ps
CPU time 1.06 seconds
Started Jan 21 03:03:24 PM PST 24
Finished Jan 21 03:03:26 PM PST 24
Peak memory 199644 kb
Host smart-7da30e32-1035-44bd-8e28-a8bc7b5c7066
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319498308 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.319498308
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.2396153776
Short name T132
Test name
Test status
Simulation time 79571449 ps
CPU time 0.81 seconds
Started Jan 21 03:03:21 PM PST 24
Finished Jan 21 03:03:23 PM PST 24
Peak memory 199620 kb
Host smart-944506f3-ca35-46dc-8f17-5f4297bd7b05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396153776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.2396153776
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.4017323202
Short name T194
Test name
Test status
Simulation time 141025434 ps
CPU time 1.14 seconds
Started Jan 21 03:03:28 PM PST 24
Finished Jan 21 03:03:30 PM PST 24
Peak memory 199712 kb
Host smart-738b7a44-f3ec-4d81-a1d9-1f136aa983c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017323202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.4017323202
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.30345848
Short name T85
Test name
Test status
Simulation time 774329342 ps
CPU time 2.73 seconds
Started Jan 21 03:03:23 PM PST 24
Finished Jan 21 03:03:27 PM PST 24
Peak memory 199824 kb
Host smart-d526da50-3d84-46f0-b227-87e22e7d8466
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30345848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err.30345848
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1978790027
Short name T209
Test name
Test status
Simulation time 156822508 ps
CPU time 1.51 seconds
Started Jan 21 03:03:34 PM PST 24
Finished Jan 21 03:03:39 PM PST 24
Peak memory 199880 kb
Host smart-fd151e64-27c5-4350-b6c0-aa2eda48869b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978790027 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.1978790027
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.1952632508
Short name T54
Test name
Test status
Simulation time 90204881 ps
CPU time 0.81 seconds
Started Jan 21 03:03:25 PM PST 24
Finished Jan 21 03:03:26 PM PST 24
Peak memory 199580 kb
Host smart-e00f2abe-8603-459b-b2ad-c958638ee1d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952632508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.1952632508
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3520146142
Short name T120
Test name
Test status
Simulation time 136408257 ps
CPU time 1.09 seconds
Started Jan 21 03:03:17 PM PST 24
Finished Jan 21 03:03:19 PM PST 24
Peak memory 199636 kb
Host smart-9e67b8af-3c50-416d-a11a-c18a2a6a1bf6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520146142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.3520146142
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.1855805708
Short name T92
Test name
Test status
Simulation time 445743580 ps
CPU time 3.19 seconds
Started Jan 21 03:03:18 PM PST 24
Finished Jan 21 03:03:23 PM PST 24
Peak memory 208060 kb
Host smart-b696873e-78a4-4f2c-823c-0ed8955d8082
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855805708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.1855805708
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.1831158364
Short name T57
Test name
Test status
Simulation time 467824368 ps
CPU time 1.9 seconds
Started Jan 21 03:03:23 PM PST 24
Finished Jan 21 03:03:26 PM PST 24
Peak memory 199784 kb
Host smart-3d41a139-355b-4255-a5bb-3b8b58582b80
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831158364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.1831158364
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2009560912
Short name T217
Test name
Test status
Simulation time 103276572 ps
CPU time 0.93 seconds
Started Jan 21 03:03:19 PM PST 24
Finished Jan 21 03:03:21 PM PST 24
Peak memory 199740 kb
Host smart-5e9832ff-9b82-4542-b2da-15e4b00d9531
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009560912 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.2009560912
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.1667015040
Short name T227
Test name
Test status
Simulation time 75123380 ps
CPU time 0.79 seconds
Started Jan 21 03:03:19 PM PST 24
Finished Jan 21 03:03:21 PM PST 24
Peak memory 199668 kb
Host smart-83125026-250d-408d-9bc5-e106c2070094
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667015040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.1667015040
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3349866486
Short name T122
Test name
Test status
Simulation time 193122989 ps
CPU time 1.48 seconds
Started Jan 21 03:03:34 PM PST 24
Finished Jan 21 03:03:39 PM PST 24
Peak memory 199856 kb
Host smart-ba7811e1-0537-40b2-9e5c-4204d2608c7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349866486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.3349866486
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.3426694589
Short name T228
Test name
Test status
Simulation time 412700207 ps
CPU time 3.09 seconds
Started Jan 21 03:03:24 PM PST 24
Finished Jan 21 03:03:28 PM PST 24
Peak memory 199904 kb
Host smart-6e81e188-918c-4085-8a9e-614c4e82ecbb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426694589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.3426694589
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.385679225
Short name T192
Test name
Test status
Simulation time 428536486 ps
CPU time 2 seconds
Started Jan 21 03:03:21 PM PST 24
Finished Jan 21 03:03:24 PM PST 24
Peak memory 199128 kb
Host smart-23cfeb24-8d9a-45e8-aeda-7bd502011084
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385679225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err.
385679225
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.3297287191
Short name T241
Test name
Test status
Simulation time 176776666 ps
CPU time 1.23 seconds
Started Jan 21 03:03:30 PM PST 24
Finished Jan 21 03:03:32 PM PST 24
Peak memory 199756 kb
Host smart-90c6ae5e-8c5e-4808-9c5f-e5e6d11f628e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297287191 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.3297287191
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1682599673
Short name T221
Test name
Test status
Simulation time 58229985 ps
CPU time 0.76 seconds
Started Jan 21 03:03:34 PM PST 24
Finished Jan 21 03:03:38 PM PST 24
Peak memory 199708 kb
Host smart-274f2979-6396-4831-bedc-531c0352e592
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682599673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.1682599673
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.1521944682
Short name T98
Test name
Test status
Simulation time 260375479 ps
CPU time 1.56 seconds
Started Jan 21 03:03:28 PM PST 24
Finished Jan 21 03:03:30 PM PST 24
Peak memory 199696 kb
Host smart-91e6a9f4-8fd5-46ce-a17e-314bce3a181a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521944682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.1521944682
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2043955988
Short name T199
Test name
Test status
Simulation time 244025442 ps
CPU time 1.85 seconds
Started Jan 21 03:03:27 PM PST 24
Finished Jan 21 03:03:30 PM PST 24
Peak memory 199860 kb
Host smart-c1a97fca-da2b-41c5-a338-a587da40a1a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043955988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.2043955988
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1590775508
Short name T219
Test name
Test status
Simulation time 499776304 ps
CPU time 1.89 seconds
Started Jan 21 03:03:29 PM PST 24
Finished Jan 21 03:03:32 PM PST 24
Peak memory 199824 kb
Host smart-7ac091cc-37fd-4dd0-8549-917002633be4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590775508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.1590775508
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.822801107
Short name T159
Test name
Test status
Simulation time 65063814 ps
CPU time 0.71 seconds
Started Jan 21 03:29:56 PM PST 24
Finished Jan 21 03:30:08 PM PST 24
Peak memory 199480 kb
Host smart-9989b976-1cac-48b9-942c-506aaf7d2995
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822801107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.822801107
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.1496926309
Short name T619
Test name
Test status
Simulation time 1222291083 ps
CPU time 5.66 seconds
Started Jan 21 03:29:55 PM PST 24
Finished Jan 21 03:30:13 PM PST 24
Peak memory 220536 kb
Host smart-ceb25cd5-916a-43f6-bbbf-5923041979ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496926309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.1496926309
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.3548712357
Short name T574
Test name
Test status
Simulation time 244241057 ps
CPU time 1.05 seconds
Started Jan 21 03:29:52 PM PST 24
Finished Jan 21 03:30:04 PM PST 24
Peak memory 216684 kb
Host smart-91645a02-afde-4325-bc7e-338fb17dab0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548712357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.3548712357
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.2982262249
Short name T507
Test name
Test status
Simulation time 150205443 ps
CPU time 0.76 seconds
Started Jan 21 03:29:59 PM PST 24
Finished Jan 21 03:30:08 PM PST 24
Peak memory 199316 kb
Host smart-681b6d17-2495-402a-88d6-88a570d27ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982262249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.2982262249
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.1929413599
Short name T541
Test name
Test status
Simulation time 1629841674 ps
CPU time 5.89 seconds
Started Jan 21 03:29:49 PM PST 24
Finished Jan 21 03:30:01 PM PST 24
Peak memory 199836 kb
Host smart-53cd9ad5-ccfb-4f5e-b019-1c0e1eb82d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929413599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.1929413599
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.1115609329
Short name T472
Test name
Test status
Simulation time 100148475 ps
CPU time 0.94 seconds
Started Jan 21 03:29:58 PM PST 24
Finished Jan 21 03:30:08 PM PST 24
Peak memory 199604 kb
Host smart-015f79c0-144e-40ad-80bd-a1053e9b3e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115609329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.1115609329
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.556840690
Short name T244
Test name
Test status
Simulation time 234407157 ps
CPU time 1.47 seconds
Started Jan 21 03:29:46 PM PST 24
Finished Jan 21 03:29:48 PM PST 24
Peak memory 199788 kb
Host smart-efcf153d-132c-42a9-9684-73217db35f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556840690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.556840690
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.2360496779
Short name T580
Test name
Test status
Simulation time 7183714125 ps
CPU time 25.64 seconds
Started Jan 21 03:29:59 PM PST 24
Finished Jan 21 03:30:33 PM PST 24
Peak memory 199764 kb
Host smart-9e718d4c-f646-46b2-850d-e4d1f02f0ef9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360496779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.2360496779
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.2041808694
Short name T446
Test name
Test status
Simulation time 450625087 ps
CPU time 2.82 seconds
Started Jan 21 03:29:48 PM PST 24
Finished Jan 21 03:29:52 PM PST 24
Peak memory 199652 kb
Host smart-d720cd10-0c2e-4dca-9317-bf5c82701718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041808694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.2041808694
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.3257544041
Short name T469
Test name
Test status
Simulation time 133283481 ps
CPU time 1.06 seconds
Started Jan 21 03:29:47 PM PST 24
Finished Jan 21 03:29:50 PM PST 24
Peak memory 199600 kb
Host smart-d0a4e1ed-34a8-4ff7-8f29-23efc7168661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257544041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.3257544041
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.3135073985
Short name T314
Test name
Test status
Simulation time 80205688 ps
CPU time 0.81 seconds
Started Jan 21 03:30:02 PM PST 24
Finished Jan 21 03:30:10 PM PST 24
Peak memory 199576 kb
Host smart-91aa4d5e-01e0-44eb-8fab-20b51df4a4a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135073985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.3135073985
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.1661932721
Short name T27
Test name
Test status
Simulation time 2173847640 ps
CPU time 7.51 seconds
Started Jan 21 03:30:05 PM PST 24
Finished Jan 21 03:30:18 PM PST 24
Peak memory 217608 kb
Host smart-729d409c-0685-418f-a61f-d9577342f3ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661932721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.1661932721
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.2350797202
Short name T414
Test name
Test status
Simulation time 243984172 ps
CPU time 1.09 seconds
Started Jan 21 03:30:03 PM PST 24
Finished Jan 21 03:30:10 PM PST 24
Peak memory 216736 kb
Host smart-1cd5667d-9a8e-486e-b5c1-f2b9582cf368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350797202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.2350797202
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.3030871793
Short name T513
Test name
Test status
Simulation time 99361014 ps
CPU time 0.75 seconds
Started Jan 21 03:29:56 PM PST 24
Finished Jan 21 03:30:08 PM PST 24
Peak memory 199304 kb
Host smart-67413eac-b321-4a57-b761-300c2475b4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030871793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.3030871793
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.3112769599
Short name T590
Test name
Test status
Simulation time 1781747899 ps
CPU time 6.62 seconds
Started Jan 21 03:29:55 PM PST 24
Finished Jan 21 03:30:10 PM PST 24
Peak memory 199780 kb
Host smart-6ac2dca8-535f-4dc4-a6f4-5186d494ec94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112769599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.3112769599
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.3708794133
Short name T65
Test name
Test status
Simulation time 16529297729 ps
CPU time 28.05 seconds
Started Jan 21 03:30:05 PM PST 24
Finished Jan 21 03:30:38 PM PST 24
Peak memory 217652 kb
Host smart-00546837-8c56-4384-be5f-6f8135c9bd18
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708794133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.3708794133
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.2171301881
Short name T250
Test name
Test status
Simulation time 152860272 ps
CPU time 1.15 seconds
Started Jan 21 03:30:03 PM PST 24
Finished Jan 21 03:30:11 PM PST 24
Peak memory 199608 kb
Host smart-93db6829-b41d-4d43-9d2e-b95967be6cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171301881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.2171301881
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.2652138554
Short name T90
Test name
Test status
Simulation time 259443923 ps
CPU time 1.69 seconds
Started Jan 21 03:29:57 PM PST 24
Finished Jan 21 03:30:09 PM PST 24
Peak memory 199992 kb
Host smart-5cce4b4f-0ee5-4b97-9377-9e81392cda20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652138554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.2652138554
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.1603272315
Short name T262
Test name
Test status
Simulation time 2297709242 ps
CPU time 9.82 seconds
Started Jan 21 03:30:03 PM PST 24
Finished Jan 21 03:30:19 PM PST 24
Peak memory 199764 kb
Host smart-92e859be-6fc0-4d5b-a549-623816537150
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603272315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.1603272315
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.943841860
Short name T549
Test name
Test status
Simulation time 129032705 ps
CPU time 1.62 seconds
Started Jan 21 03:30:07 PM PST 24
Finished Jan 21 03:30:13 PM PST 24
Peak memory 199580 kb
Host smart-81da4417-9e0c-49dc-84c2-7a82e59e4806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943841860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.943841860
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.3405172081
Short name T341
Test name
Test status
Simulation time 164156974 ps
CPU time 1.07 seconds
Started Jan 21 03:29:59 PM PST 24
Finished Jan 21 03:30:08 PM PST 24
Peak memory 199512 kb
Host smart-c259c014-d8cb-4450-9040-b87783b1d30f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405172081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.3405172081
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.4228065458
Short name T374
Test name
Test status
Simulation time 73912542 ps
CPU time 0.8 seconds
Started Jan 21 03:31:09 PM PST 24
Finished Jan 21 03:31:11 PM PST 24
Peak memory 199500 kb
Host smart-e1cf2c15-4095-4f13-83ad-346ec3c791e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228065458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.4228065458
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.3463827663
Short name T394
Test name
Test status
Simulation time 1219546977 ps
CPU time 5.93 seconds
Started Jan 21 03:31:06 PM PST 24
Finished Jan 21 03:31:13 PM PST 24
Peak memory 216492 kb
Host smart-894a9af9-9006-409d-b1f5-ef1c2bcdc87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463827663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.3463827663
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_reset.3866787764
Short name T102
Test name
Test status
Simulation time 727004729 ps
CPU time 4 seconds
Started Jan 21 03:31:08 PM PST 24
Finished Jan 21 03:31:13 PM PST 24
Peak memory 199820 kb
Host smart-9b3a1ae1-5ce0-4f4d-b852-86bde81fd2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866787764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.3866787764
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.2112074675
Short name T609
Test name
Test status
Simulation time 95396958 ps
CPU time 1.02 seconds
Started Jan 21 03:31:05 PM PST 24
Finished Jan 21 03:31:08 PM PST 24
Peak memory 199588 kb
Host smart-295f29da-70ec-4d76-92a1-5d9b5e3c4434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112074675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.2112074675
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.1618875521
Short name T135
Test name
Test status
Simulation time 257397989 ps
CPU time 1.52 seconds
Started Jan 21 03:31:06 PM PST 24
Finished Jan 21 03:31:09 PM PST 24
Peak memory 199736 kb
Host smart-ebea5080-93f9-46e0-9783-a53b35a116c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618875521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.1618875521
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.3787715658
Short name T332
Test name
Test status
Simulation time 9079598078 ps
CPU time 38.48 seconds
Started Jan 21 03:31:03 PM PST 24
Finished Jan 21 03:31:43 PM PST 24
Peak memory 199880 kb
Host smart-4bf7c84b-ea42-4b42-8e5f-a69a3aa442b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787715658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.3787715658
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.220935401
Short name T89
Test name
Test status
Simulation time 450624732 ps
CPU time 2.66 seconds
Started Jan 21 03:31:05 PM PST 24
Finished Jan 21 03:31:10 PM PST 24
Peak memory 199648 kb
Host smart-340d4670-ad89-45a4-b64a-83e9b4fbc23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220935401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.220935401
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.559245139
Short name T521
Test name
Test status
Simulation time 287874748 ps
CPU time 1.55 seconds
Started Jan 21 03:31:22 PM PST 24
Finished Jan 21 03:31:25 PM PST 24
Peak memory 199552 kb
Host smart-0e984071-17d0-4b42-a529-1f74ad26d1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559245139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.559245139
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.4291682179
Short name T419
Test name
Test status
Simulation time 62540316 ps
CPU time 0.71 seconds
Started Jan 21 03:31:22 PM PST 24
Finished Jan 21 03:31:23 PM PST 24
Peak memory 199544 kb
Host smart-43ca13ec-f556-4c7c-8b47-08ce582c2883
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291682179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.4291682179
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.2670195957
Short name T258
Test name
Test status
Simulation time 244567959 ps
CPU time 1.21 seconds
Started Jan 21 03:31:07 PM PST 24
Finished Jan 21 03:31:09 PM PST 24
Peak memory 216908 kb
Host smart-fbde8beb-ccc0-4179-af75-43e12589505a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670195957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.2670195957
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.1717845623
Short name T310
Test name
Test status
Simulation time 183856883 ps
CPU time 0.97 seconds
Started Jan 21 03:31:22 PM PST 24
Finished Jan 21 03:31:24 PM PST 24
Peak memory 199372 kb
Host smart-5d240b05-e101-40c5-a40d-783c66c67937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717845623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.1717845623
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.2885796657
Short name T280
Test name
Test status
Simulation time 1202546585 ps
CPU time 5.04 seconds
Started Jan 21 03:31:05 PM PST 24
Finished Jan 21 03:31:12 PM PST 24
Peak memory 199708 kb
Host smart-1ba7585b-75fc-4abc-b153-ce7057243fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885796657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.2885796657
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.997662675
Short name T554
Test name
Test status
Simulation time 112456117 ps
CPU time 1.03 seconds
Started Jan 21 03:31:06 PM PST 24
Finished Jan 21 03:31:09 PM PST 24
Peak memory 199196 kb
Host smart-82b55e9d-d61a-4e96-9063-a775f27aceff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997662675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.997662675
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.2947439749
Short name T372
Test name
Test status
Simulation time 254167247 ps
CPU time 1.63 seconds
Started Jan 21 03:31:02 PM PST 24
Finished Jan 21 03:31:05 PM PST 24
Peak memory 199696 kb
Host smart-c0009ace-350e-4c1e-8dea-9fee9526af7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947439749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.2947439749
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.3167345549
Short name T390
Test name
Test status
Simulation time 3739226107 ps
CPU time 16.38 seconds
Started Jan 21 03:31:06 PM PST 24
Finished Jan 21 03:31:24 PM PST 24
Peak memory 199404 kb
Host smart-4c842303-6016-434d-837c-7e5bbb5ea735
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167345549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.3167345549
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.3195559119
Short name T594
Test name
Test status
Simulation time 143028002 ps
CPU time 2.02 seconds
Started Jan 21 05:00:22 PM PST 24
Finished Jan 21 05:00:25 PM PST 24
Peak memory 199776 kb
Host smart-4e25a7ca-4edd-4927-bd4c-9a8760e0b043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195559119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.3195559119
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.3450435792
Short name T471
Test name
Test status
Simulation time 106329957 ps
CPU time 1.21 seconds
Started Jan 21 03:31:03 PM PST 24
Finished Jan 21 03:31:06 PM PST 24
Peak memory 199604 kb
Host smart-adac0cc2-2f47-4564-8c14-02187626bab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450435792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.3450435792
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.2960012421
Short name T587
Test name
Test status
Simulation time 88616729 ps
CPU time 0.83 seconds
Started Jan 21 03:31:15 PM PST 24
Finished Jan 21 03:31:18 PM PST 24
Peak memory 199580 kb
Host smart-4750f743-3a3e-48a7-ad6f-c4fdcdf362a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960012421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.2960012421
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.46907011
Short name T360
Test name
Test status
Simulation time 1220880775 ps
CPU time 5.64 seconds
Started Jan 21 03:31:20 PM PST 24
Finished Jan 21 03:31:27 PM PST 24
Peak memory 220340 kb
Host smart-24cee76d-4d10-4d90-8dbc-6c688153ca97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46907011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.46907011
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.3185701411
Short name T309
Test name
Test status
Simulation time 245625869 ps
CPU time 1.05 seconds
Started Jan 21 03:31:15 PM PST 24
Finished Jan 21 03:31:18 PM PST 24
Peak memory 216872 kb
Host smart-c0d51eef-eeda-42f8-ac57-75b6639ee27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185701411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.3185701411
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.3028806778
Short name T494
Test name
Test status
Simulation time 136113962 ps
CPU time 0.86 seconds
Started Jan 21 03:31:22 PM PST 24
Finished Jan 21 03:31:24 PM PST 24
Peak memory 199340 kb
Host smart-a0aa29e0-09e4-4aee-b077-3ce034cbb315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028806778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.3028806778
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.1468409979
Short name T274
Test name
Test status
Simulation time 1556826994 ps
CPU time 6.48 seconds
Started Jan 21 03:31:21 PM PST 24
Finished Jan 21 03:31:29 PM PST 24
Peak memory 199756 kb
Host smart-ec5d6353-2508-4723-890c-624fa93d0963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468409979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.1468409979
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.2320541438
Short name T583
Test name
Test status
Simulation time 203707080 ps
CPU time 1.42 seconds
Started Jan 21 03:31:05 PM PST 24
Finished Jan 21 03:31:09 PM PST 24
Peak memory 199776 kb
Host smart-912d5955-b051-44b9-a633-eb6a45847fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320541438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.2320541438
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.2858786567
Short name T357
Test name
Test status
Simulation time 4947897474 ps
CPU time 18.18 seconds
Started Jan 21 03:31:20 PM PST 24
Finished Jan 21 03:31:40 PM PST 24
Peak memory 198628 kb
Host smart-81d6bcce-07dc-423c-9448-922e6b85d34c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858786567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.2858786567
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.1093753695
Short name T437
Test name
Test status
Simulation time 140827879 ps
CPU time 1.61 seconds
Started Jan 21 04:02:33 PM PST 24
Finished Jan 21 04:02:43 PM PST 24
Peak memory 199664 kb
Host smart-885e89ae-a47e-4f08-92a3-e3c326fc6f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093753695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.1093753695
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.901261567
Short name T271
Test name
Test status
Simulation time 175614809 ps
CPU time 1.21 seconds
Started Jan 21 03:31:15 PM PST 24
Finished Jan 21 03:31:18 PM PST 24
Peak memory 199540 kb
Host smart-f8d11ef7-e0ad-4fbf-84ac-7921b31106b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901261567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.901261567
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.2752883709
Short name T47
Test name
Test status
Simulation time 85905740 ps
CPU time 0.79 seconds
Started Jan 21 03:31:17 PM PST 24
Finished Jan 21 03:31:19 PM PST 24
Peak memory 199560 kb
Host smart-4330233e-0d25-4e28-94e6-197cd60448f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752883709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.2752883709
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.2031168824
Short name T467
Test name
Test status
Simulation time 1234003754 ps
CPU time 5.65 seconds
Started Jan 21 03:31:24 PM PST 24
Finished Jan 21 03:31:30 PM PST 24
Peak memory 217304 kb
Host smart-dabc40d4-c05d-4f27-84b5-fbe24509dafd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031168824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.2031168824
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.2718807745
Short name T566
Test name
Test status
Simulation time 243613307 ps
CPU time 1.16 seconds
Started Jan 21 03:31:18 PM PST 24
Finished Jan 21 03:31:20 PM PST 24
Peak memory 216784 kb
Host smart-395a5226-dc55-478b-bac6-c1ae8114a718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718807745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.2718807745
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.249048379
Short name T539
Test name
Test status
Simulation time 123524765 ps
CPU time 0.83 seconds
Started Jan 21 03:31:16 PM PST 24
Finished Jan 21 03:31:18 PM PST 24
Peak memory 199328 kb
Host smart-eee8a8c0-96f7-43ef-afe9-f5e8fe829e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249048379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.249048379
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.59497403
Short name T301
Test name
Test status
Simulation time 794418161 ps
CPU time 3.99 seconds
Started Jan 21 03:31:16 PM PST 24
Finished Jan 21 03:31:21 PM PST 24
Peak memory 199804 kb
Host smart-8948da46-a407-49cf-b983-edc23776c765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59497403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.59497403
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.2132732155
Short name T286
Test name
Test status
Simulation time 99438261 ps
CPU time 0.94 seconds
Started Jan 21 03:31:17 PM PST 24
Finished Jan 21 03:31:18 PM PST 24
Peak memory 199568 kb
Host smart-1bd03a27-9913-4154-9b36-1d00e1abea0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132732155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.2132732155
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.2077854190
Short name T163
Test name
Test status
Simulation time 201998523 ps
CPU time 1.44 seconds
Started Jan 21 03:31:24 PM PST 24
Finished Jan 21 03:31:26 PM PST 24
Peak memory 199720 kb
Host smart-22da50b1-20f6-4488-b97f-1fc2a26a4c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077854190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.2077854190
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.3406965130
Short name T288
Test name
Test status
Simulation time 11661877054 ps
CPU time 40.53 seconds
Started Jan 21 03:31:18 PM PST 24
Finished Jan 21 03:32:00 PM PST 24
Peak memory 199852 kb
Host smart-d914bfc7-0e66-4847-b6f4-5aad4e547075
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406965130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.3406965130
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.2904476212
Short name T600
Test name
Test status
Simulation time 116115997 ps
CPU time 1.42 seconds
Started Jan 21 03:31:18 PM PST 24
Finished Jan 21 03:31:21 PM PST 24
Peak memory 199688 kb
Host smart-b90d70b8-7319-4b34-b275-a5521c2aad4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904476212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.2904476212
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.4282920736
Short name T576
Test name
Test status
Simulation time 114610015 ps
CPU time 0.96 seconds
Started Jan 21 03:31:24 PM PST 24
Finished Jan 21 03:31:26 PM PST 24
Peak memory 199396 kb
Host smart-77e918e5-6b81-46a0-953d-d3b9edb8a00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282920736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.4282920736
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.660243001
Short name T382
Test name
Test status
Simulation time 61706179 ps
CPU time 0.75 seconds
Started Jan 21 03:31:34 PM PST 24
Finished Jan 21 03:31:36 PM PST 24
Peak memory 199540 kb
Host smart-3822e55a-4b90-48b1-8b90-08c4dcc1e3ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660243001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.660243001
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.3245215023
Short name T450
Test name
Test status
Simulation time 1880132213 ps
CPU time 7.23 seconds
Started Jan 21 03:31:36 PM PST 24
Finished Jan 21 03:31:47 PM PST 24
Peak memory 216536 kb
Host smart-2dc2a9b0-15c0-498c-9a5c-e6d0ee56cc54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245215023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.3245215023
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.2239015165
Short name T581
Test name
Test status
Simulation time 244314961 ps
CPU time 1.13 seconds
Started Jan 21 03:31:30 PM PST 24
Finished Jan 21 03:31:33 PM PST 24
Peak memory 216824 kb
Host smart-e85f757d-5ae6-4ff1-9895-d95faece7a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239015165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.2239015165
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.2185200126
Short name T410
Test name
Test status
Simulation time 111041584 ps
CPU time 0.78 seconds
Started Jan 21 03:31:17 PM PST 24
Finished Jan 21 03:31:18 PM PST 24
Peak memory 199388 kb
Host smart-6d96a364-fc75-4494-aab9-0fd568d0c15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185200126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.2185200126
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.4121960214
Short name T512
Test name
Test status
Simulation time 1432457852 ps
CPU time 5.56 seconds
Started Jan 21 03:31:33 PM PST 24
Finished Jan 21 03:31:39 PM PST 24
Peak memory 199840 kb
Host smart-a4d19a07-2df7-451c-a925-347e44c453d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121960214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.4121960214
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.3190641222
Short name T335
Test name
Test status
Simulation time 112279291 ps
CPU time 0.99 seconds
Started Jan 21 03:31:29 PM PST 24
Finished Jan 21 03:31:31 PM PST 24
Peak memory 199592 kb
Host smart-f8808844-7758-471b-bf97-c926815ccd4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190641222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.3190641222
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.2472645338
Short name T553
Test name
Test status
Simulation time 200911262 ps
CPU time 1.4 seconds
Started Jan 21 03:31:24 PM PST 24
Finished Jan 21 03:31:26 PM PST 24
Peak memory 199720 kb
Host smart-4402c5d9-ff50-48b5-89b0-13822142ac91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472645338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.2472645338
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.2960575261
Short name T536
Test name
Test status
Simulation time 2427306855 ps
CPU time 11.6 seconds
Started Jan 21 03:31:33 PM PST 24
Finished Jan 21 03:31:46 PM PST 24
Peak memory 199840 kb
Host smart-8bc63ff9-2a4d-4246-b23d-c54afe8bb79b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960575261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.2960575261
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.524204972
Short name T413
Test name
Test status
Simulation time 252403196 ps
CPU time 1.74 seconds
Started Jan 21 03:31:30 PM PST 24
Finished Jan 21 03:31:33 PM PST 24
Peak memory 199612 kb
Host smart-2733e3dd-7512-42af-9fa7-415a07d6b839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524204972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.524204972
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.3563767282
Short name T501
Test name
Test status
Simulation time 172316472 ps
CPU time 1.33 seconds
Started Jan 21 03:31:30 PM PST 24
Finished Jan 21 03:31:33 PM PST 24
Peak memory 199808 kb
Host smart-3d161f52-fe66-4866-b257-bf786dc7e00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563767282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.3563767282
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.2976336089
Short name T449
Test name
Test status
Simulation time 1222078856 ps
CPU time 5.92 seconds
Started Jan 21 03:31:30 PM PST 24
Finished Jan 21 03:31:38 PM PST 24
Peak memory 221620 kb
Host smart-295d9b15-179b-4bc8-8226-9b74180070f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976336089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.2976336089
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.1724267053
Short name T612
Test name
Test status
Simulation time 245747718 ps
CPU time 1.03 seconds
Started Jan 21 03:31:27 PM PST 24
Finished Jan 21 03:31:29 PM PST 24
Peak memory 216760 kb
Host smart-b653e39b-e8fe-4eaf-89df-08e19c92d8bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724267053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.1724267053
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.1248099983
Short name T569
Test name
Test status
Simulation time 156458599 ps
CPU time 0.85 seconds
Started Jan 21 03:31:35 PM PST 24
Finished Jan 21 03:31:38 PM PST 24
Peak memory 199388 kb
Host smart-c710da6f-3aa5-407c-9ede-2cdb2310b685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248099983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.1248099983
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.4053259427
Short name T278
Test name
Test status
Simulation time 1504332101 ps
CPU time 6.21 seconds
Started Jan 21 03:31:30 PM PST 24
Finished Jan 21 03:31:38 PM PST 24
Peak memory 199760 kb
Host smart-41e2e3fe-669a-4739-8614-e40fb5d8788d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053259427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.4053259427
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.4084741021
Short name T543
Test name
Test status
Simulation time 103523523 ps
CPU time 0.99 seconds
Started Jan 21 03:31:27 PM PST 24
Finished Jan 21 03:31:29 PM PST 24
Peak memory 199548 kb
Host smart-ecb7ad4a-30f4-4a37-8319-2292ba31af02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084741021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.4084741021
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.1589173261
Short name T148
Test name
Test status
Simulation time 126024459 ps
CPU time 1.23 seconds
Started Jan 21 03:31:35 PM PST 24
Finished Jan 21 03:31:37 PM PST 24
Peak memory 199760 kb
Host smart-87debe95-7613-4024-8162-d549403ebea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589173261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.1589173261
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.1410348591
Short name T356
Test name
Test status
Simulation time 7581626801 ps
CPU time 28.2 seconds
Started Jan 21 03:31:31 PM PST 24
Finished Jan 21 03:32:00 PM PST 24
Peak memory 199692 kb
Host smart-732a22d1-ccfa-468e-9ac6-fd87b2bcf3a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410348591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.1410348591
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.3999567928
Short name T350
Test name
Test status
Simulation time 509320617 ps
CPU time 2.66 seconds
Started Jan 21 03:31:33 PM PST 24
Finished Jan 21 03:31:37 PM PST 24
Peak memory 199656 kb
Host smart-784b5aef-44cb-44f2-b2a3-7b7ee1581c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999567928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.3999567928
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.1764614749
Short name T68
Test name
Test status
Simulation time 75984353 ps
CPU time 0.79 seconds
Started Jan 21 03:31:42 PM PST 24
Finished Jan 21 03:31:44 PM PST 24
Peak memory 199388 kb
Host smart-8e037a18-7277-4903-84dc-5b38c11131d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764614749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.1764614749
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.2600482411
Short name T35
Test name
Test status
Simulation time 1906870766 ps
CPU time 8.24 seconds
Started Jan 21 03:31:37 PM PST 24
Finished Jan 21 03:31:48 PM PST 24
Peak memory 216740 kb
Host smart-9a471643-a4bc-41de-8f4f-785ab81cf3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600482411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.2600482411
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.3604355406
Short name T511
Test name
Test status
Simulation time 244153574 ps
CPU time 1.1 seconds
Started Jan 21 03:31:32 PM PST 24
Finished Jan 21 03:31:34 PM PST 24
Peak memory 216824 kb
Host smart-5e3e912e-eec4-4816-b09a-70a9e589ba04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604355406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.3604355406
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.994829800
Short name T421
Test name
Test status
Simulation time 137830034 ps
CPU time 0.75 seconds
Started Jan 21 03:31:37 PM PST 24
Finished Jan 21 03:31:40 PM PST 24
Peak memory 199408 kb
Host smart-c10c5967-8d28-4e69-aa15-82c1e7a2d0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994829800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.994829800
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.736677979
Short name T457
Test name
Test status
Simulation time 826654832 ps
CPU time 4.19 seconds
Started Jan 21 03:31:40 PM PST 24
Finished Jan 21 03:31:46 PM PST 24
Peak memory 199860 kb
Host smart-08671dae-ddda-40f2-ac7a-ae1480a0e9dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736677979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.736677979
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.35198823
Short name T141
Test name
Test status
Simulation time 109406361 ps
CPU time 1.08 seconds
Started Jan 21 03:31:41 PM PST 24
Finished Jan 21 03:31:44 PM PST 24
Peak memory 199372 kb
Host smart-3c823e4c-80b6-4812-9282-7d55c66aa6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35198823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.35198823
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.4243460286
Short name T442
Test name
Test status
Simulation time 121779536 ps
CPU time 1.13 seconds
Started Jan 21 03:31:41 PM PST 24
Finished Jan 21 03:31:43 PM PST 24
Peak memory 199792 kb
Host smart-9af619b6-05a7-402d-8429-a4f7ad90afde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243460286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.4243460286
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.946552991
Short name T169
Test name
Test status
Simulation time 120581323 ps
CPU time 1.57 seconds
Started Jan 21 03:31:31 PM PST 24
Finished Jan 21 03:31:34 PM PST 24
Peak memory 199628 kb
Host smart-c9070886-b209-49fc-9368-773f716f0b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946552991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.946552991
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.3699336304
Short name T261
Test name
Test status
Simulation time 99122779 ps
CPU time 0.88 seconds
Started Jan 21 03:31:29 PM PST 24
Finished Jan 21 03:31:31 PM PST 24
Peak memory 199584 kb
Host smart-0681af3c-7a92-4c0d-aba4-b7bbefcdb592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699336304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.3699336304
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.2571615076
Short name T492
Test name
Test status
Simulation time 70660140 ps
CPU time 0.78 seconds
Started Jan 21 03:31:42 PM PST 24
Finished Jan 21 03:31:45 PM PST 24
Peak memory 199576 kb
Host smart-3e66b076-efda-434f-96da-8efa013df201
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571615076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.2571615076
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.2887896982
Short name T34
Test name
Test status
Simulation time 1223909785 ps
CPU time 5.35 seconds
Started Jan 21 03:31:49 PM PST 24
Finished Jan 21 03:31:56 PM PST 24
Peak memory 220492 kb
Host smart-7489328b-25ab-4441-9577-d2b5b5b5ae0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887896982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.2887896982
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.3906623249
Short name T552
Test name
Test status
Simulation time 245749570 ps
CPU time 1.13 seconds
Started Jan 21 03:31:40 PM PST 24
Finished Jan 21 03:31:43 PM PST 24
Peak memory 216960 kb
Host smart-4716744a-2d65-403b-8088-1a1db509e1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906623249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.3906623249
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.3862588942
Short name T403
Test name
Test status
Simulation time 113664088 ps
CPU time 0.8 seconds
Started Jan 21 03:31:31 PM PST 24
Finished Jan 21 03:31:33 PM PST 24
Peak memory 199336 kb
Host smart-2dcdccd8-282a-4683-b29b-3b5b52df9f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862588942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.3862588942
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.4021772488
Short name T599
Test name
Test status
Simulation time 1731584329 ps
CPU time 6.53 seconds
Started Jan 21 03:31:30 PM PST 24
Finished Jan 21 03:31:38 PM PST 24
Peak memory 199728 kb
Host smart-f69ca5f9-4e58-4fe1-bf9b-164b3758206d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021772488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.4021772488
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.2429052345
Short name T605
Test name
Test status
Simulation time 142372033 ps
CPU time 1.22 seconds
Started Jan 21 03:31:50 PM PST 24
Finished Jan 21 03:31:52 PM PST 24
Peak memory 199528 kb
Host smart-5e2d9668-0d6b-45c8-9014-459674b507dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429052345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.2429052345
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.35355445
Short name T441
Test name
Test status
Simulation time 125317884 ps
CPU time 1.19 seconds
Started Jan 21 03:31:30 PM PST 24
Finished Jan 21 03:31:33 PM PST 24
Peak memory 199776 kb
Host smart-67b5546e-db13-4a74-b578-c04e811d3466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35355445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.35355445
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.371461593
Short name T504
Test name
Test status
Simulation time 3747943826 ps
CPU time 15.76 seconds
Started Jan 21 03:31:36 PM PST 24
Finished Jan 21 03:31:54 PM PST 24
Peak memory 199852 kb
Host smart-5cacc2f0-6e3e-47ae-937e-58e34ee49cb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371461593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.371461593
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.3769764471
Short name T418
Test name
Test status
Simulation time 141706708 ps
CPU time 1.69 seconds
Started Jan 21 03:31:46 PM PST 24
Finished Jan 21 03:31:50 PM PST 24
Peak memory 199700 kb
Host smart-75c36597-0a40-4356-9524-4fcb5a112014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769764471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.3769764471
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.3782033240
Short name T272
Test name
Test status
Simulation time 150029552 ps
CPU time 1.16 seconds
Started Jan 21 03:31:42 PM PST 24
Finished Jan 21 03:31:45 PM PST 24
Peak memory 199468 kb
Host smart-500f0e4e-c1c9-4951-956c-99835f4ec049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782033240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.3782033240
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.629108593
Short name T548
Test name
Test status
Simulation time 60659388 ps
CPU time 0.74 seconds
Started Jan 21 03:31:42 PM PST 24
Finished Jan 21 03:31:45 PM PST 24
Peak memory 199572 kb
Host smart-27f64b97-0ef0-4e30-9d4b-097488c22fe3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629108593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.629108593
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.1479931768
Short name T435
Test name
Test status
Simulation time 2189296640 ps
CPU time 7.53 seconds
Started Jan 21 03:31:48 PM PST 24
Finished Jan 21 03:31:57 PM PST 24
Peak memory 216568 kb
Host smart-0d211fce-393f-4b23-a4ea-61ff08556a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479931768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.1479931768
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.3465859555
Short name T324
Test name
Test status
Simulation time 244567749 ps
CPU time 1.03 seconds
Started Jan 21 03:31:42 PM PST 24
Finished Jan 21 03:31:44 PM PST 24
Peak memory 216912 kb
Host smart-6f962349-8edc-4a9e-a629-ebbf67cf42a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465859555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.3465859555
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.336377398
Short name T2
Test name
Test status
Simulation time 126538912 ps
CPU time 0.76 seconds
Started Jan 21 03:31:40 PM PST 24
Finished Jan 21 03:31:42 PM PST 24
Peak memory 199448 kb
Host smart-cef2597e-fffd-4b82-8034-d6aec78b4ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336377398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.336377398
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.3664679666
Short name T312
Test name
Test status
Simulation time 787194711 ps
CPU time 4.06 seconds
Started Jan 21 03:31:40 PM PST 24
Finished Jan 21 03:31:45 PM PST 24
Peak memory 199844 kb
Host smart-10b4171b-2c25-44a0-8a60-ad0607919f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664679666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.3664679666
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.681840455
Short name T37
Test name
Test status
Simulation time 106523555 ps
CPU time 0.99 seconds
Started Jan 21 03:31:38 PM PST 24
Finished Jan 21 03:31:42 PM PST 24
Peak memory 199548 kb
Host smart-9a23b239-21c3-4f7d-bbb9-c3a6ff769932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681840455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.681840455
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.238031453
Short name T86
Test name
Test status
Simulation time 210910166 ps
CPU time 1.36 seconds
Started Jan 21 03:31:39 PM PST 24
Finished Jan 21 03:31:42 PM PST 24
Peak memory 199856 kb
Host smart-671ba996-06e2-46e0-96e5-005b27b7b00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238031453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.238031453
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.2136145636
Short name T601
Test name
Test status
Simulation time 6237325385 ps
CPU time 21.1 seconds
Started Jan 21 03:31:42 PM PST 24
Finished Jan 21 03:32:04 PM PST 24
Peak memory 199860 kb
Host smart-c9b33ad5-984b-4967-8dae-25ff78467986
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136145636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.2136145636
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.2540614053
Short name T508
Test name
Test status
Simulation time 135944440 ps
CPU time 1.66 seconds
Started Jan 21 03:31:41 PM PST 24
Finished Jan 21 03:31:45 PM PST 24
Peak memory 199464 kb
Host smart-7fd05c51-b853-4a87-a7b3-863f4887ede6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540614053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.2540614053
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.741292387
Short name T537
Test name
Test status
Simulation time 254157460 ps
CPU time 1.4 seconds
Started Jan 21 03:31:49 PM PST 24
Finished Jan 21 03:31:52 PM PST 24
Peak memory 199488 kb
Host smart-892cc0d2-cf35-4028-b6de-081e930d7d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741292387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.741292387
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.524572352
Short name T607
Test name
Test status
Simulation time 67487499 ps
CPU time 0.83 seconds
Started Jan 21 03:31:36 PM PST 24
Finished Jan 21 03:31:40 PM PST 24
Peak memory 199568 kb
Host smart-db8529e4-1733-43d5-ac0c-4f80cc2ca869
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524572352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.524572352
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.3119632331
Short name T591
Test name
Test status
Simulation time 244068378 ps
CPU time 1.13 seconds
Started Jan 21 03:31:49 PM PST 24
Finished Jan 21 03:31:52 PM PST 24
Peak memory 216816 kb
Host smart-e573f384-902d-481e-bc7a-75231799d3ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119632331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.3119632331
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.2050020525
Short name T253
Test name
Test status
Simulation time 129489586 ps
CPU time 0.86 seconds
Started Jan 21 03:31:34 PM PST 24
Finished Jan 21 03:31:36 PM PST 24
Peak memory 199340 kb
Host smart-d9c15229-c98e-410a-99f0-10d643e93df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050020525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.2050020525
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.2540914403
Short name T432
Test name
Test status
Simulation time 1310207186 ps
CPU time 5.35 seconds
Started Jan 21 03:31:38 PM PST 24
Finished Jan 21 03:31:46 PM PST 24
Peak memory 199804 kb
Host smart-0eb28ea8-005b-40a2-8f4a-3986228f5a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540914403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.2540914403
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.1230801030
Short name T328
Test name
Test status
Simulation time 154905172 ps
CPU time 1.14 seconds
Started Jan 21 03:31:49 PM PST 24
Finished Jan 21 03:31:52 PM PST 24
Peak memory 199496 kb
Host smart-f21cd17e-6de8-43c1-a0da-1756aa17949c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230801030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.1230801030
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.2445166631
Short name T304
Test name
Test status
Simulation time 248826092 ps
CPU time 1.4 seconds
Started Jan 21 03:31:47 PM PST 24
Finished Jan 21 03:31:50 PM PST 24
Peak memory 199788 kb
Host smart-317425fe-9783-41a4-a091-7425c932896f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445166631 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.2445166631
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.2227352808
Short name T110
Test name
Test status
Simulation time 5165645621 ps
CPU time 18.72 seconds
Started Jan 21 03:31:46 PM PST 24
Finished Jan 21 03:32:07 PM PST 24
Peak memory 199856 kb
Host smart-d5042d4a-4161-4f66-8355-1a863589f600
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227352808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.2227352808
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.629679897
Short name T138
Test name
Test status
Simulation time 360579743 ps
CPU time 2.01 seconds
Started Jan 21 03:31:49 PM PST 24
Finished Jan 21 03:31:52 PM PST 24
Peak memory 199588 kb
Host smart-449ff111-4cbf-4223-baea-edc6b090d524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629679897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.629679897
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.4052435377
Short name T303
Test name
Test status
Simulation time 136071033 ps
CPU time 0.97 seconds
Started Jan 21 03:31:33 PM PST 24
Finished Jan 21 03:31:35 PM PST 24
Peak memory 199540 kb
Host smart-1d6c6631-1996-4110-8dd8-d66ff7905924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052435377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.4052435377
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.1910639831
Short name T298
Test name
Test status
Simulation time 85999746 ps
CPU time 0.83 seconds
Started Jan 21 03:30:23 PM PST 24
Finished Jan 21 03:30:29 PM PST 24
Peak memory 199480 kb
Host smart-04cc9139-04d0-4abf-bffc-170e4b5d5970
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910639831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.1910639831
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.1040459632
Short name T434
Test name
Test status
Simulation time 1219743767 ps
CPU time 6.1 seconds
Started Jan 21 03:30:13 PM PST 24
Finished Jan 21 03:30:20 PM PST 24
Peak memory 220440 kb
Host smart-392afb9e-1f17-423d-aaf5-776171cc2476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040459632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.1040459632
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.111885388
Short name T162
Test name
Test status
Simulation time 243788751 ps
CPU time 1.11 seconds
Started Jan 21 03:30:17 PM PST 24
Finished Jan 21 03:30:19 PM PST 24
Peak memory 216912 kb
Host smart-56d0b869-2379-4f09-9aee-aa25cf7822d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111885388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.111885388
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.4043269474
Short name T76
Test name
Test status
Simulation time 141237849 ps
CPU time 0.81 seconds
Started Jan 21 03:30:07 PM PST 24
Finished Jan 21 03:30:12 PM PST 24
Peak memory 199324 kb
Host smart-31143722-8705-40fd-a614-e9b9ac488b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043269474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.4043269474
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.2886325529
Short name T320
Test name
Test status
Simulation time 696614378 ps
CPU time 3.81 seconds
Started Jan 21 03:30:02 PM PST 24
Finished Jan 21 03:30:13 PM PST 24
Peak memory 199704 kb
Host smart-a4fea1d1-f15a-4d6e-9715-6e4e186a8bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886325529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.2886325529
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.100195819
Short name T67
Test name
Test status
Simulation time 8291558583 ps
CPU time 14.73 seconds
Started Jan 21 03:30:19 PM PST 24
Finished Jan 21 03:30:35 PM PST 24
Peak memory 220620 kb
Host smart-9f4072cc-bc30-402d-b674-894d2a198b55
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100195819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.100195819
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.3365174837
Short name T105
Test name
Test status
Simulation time 99615907 ps
CPU time 1.02 seconds
Started Jan 21 03:30:22 PM PST 24
Finished Jan 21 03:30:29 PM PST 24
Peak memory 199508 kb
Host smart-e27aa82a-83c8-4ad6-a323-a4ff98d36a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365174837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.3365174837
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.1477693368
Short name T156
Test name
Test status
Simulation time 112526700 ps
CPU time 1.17 seconds
Started Jan 21 03:30:00 PM PST 24
Finished Jan 21 03:30:09 PM PST 24
Peak memory 199780 kb
Host smart-38833bba-3394-47d6-b037-67eb80e3722a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477693368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.1477693368
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.2287516030
Short name T476
Test name
Test status
Simulation time 3290595703 ps
CPU time 11.78 seconds
Started Jan 21 03:30:17 PM PST 24
Finished Jan 21 03:30:29 PM PST 24
Peak memory 199868 kb
Host smart-b08cdfc5-0f25-47be-b47e-a78cdca44dbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287516030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.2287516030
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.1767660654
Short name T12
Test name
Test status
Simulation time 139748507 ps
CPU time 1.8 seconds
Started Jan 21 03:30:04 PM PST 24
Finished Jan 21 03:30:12 PM PST 24
Peak memory 199632 kb
Host smart-e53a96dd-33b3-4e10-9a5e-7398770b11e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767660654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.1767660654
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.4226746294
Short name T144
Test name
Test status
Simulation time 229333327 ps
CPU time 1.54 seconds
Started Jan 21 03:30:01 PM PST 24
Finished Jan 21 03:30:10 PM PST 24
Peak memory 199616 kb
Host smart-35cb3a78-2f78-4732-9732-3138e6312a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226746294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.4226746294
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.2158892075
Short name T351
Test name
Test status
Simulation time 79822869 ps
CPU time 0.81 seconds
Started Jan 21 03:31:50 PM PST 24
Finished Jan 21 03:31:52 PM PST 24
Peak memory 199496 kb
Host smart-81ba7227-095d-480e-a14e-43ca892deca3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158892075 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.2158892075
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.3251159224
Short name T29
Test name
Test status
Simulation time 1878456686 ps
CPU time 7.77 seconds
Started Jan 21 03:31:39 PM PST 24
Finished Jan 21 03:31:49 PM PST 24
Peak memory 217536 kb
Host smart-942beaa2-4c8b-45da-9a00-e688fedfa5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251159224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.3251159224
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.2857932252
Short name T84
Test name
Test status
Simulation time 244539702 ps
CPU time 1.08 seconds
Started Jan 21 03:31:50 PM PST 24
Finished Jan 21 03:31:52 PM PST 24
Peak memory 216820 kb
Host smart-a42966c7-15ce-4f34-b478-194e6bcb3255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857932252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.2857932252
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.516053492
Short name T285
Test name
Test status
Simulation time 158328294 ps
CPU time 0.95 seconds
Started Jan 21 03:31:50 PM PST 24
Finished Jan 21 03:31:52 PM PST 24
Peak memory 199328 kb
Host smart-b9a10071-5f7e-40e5-a86f-fb3f4dfc69d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516053492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.516053492
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.316197179
Short name T78
Test name
Test status
Simulation time 973787320 ps
CPU time 4.58 seconds
Started Jan 21 03:31:36 PM PST 24
Finished Jan 21 03:31:44 PM PST 24
Peak memory 199708 kb
Host smart-bab0f06f-b3a4-44e7-938b-3af011b492a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316197179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.316197179
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.736609130
Short name T528
Test name
Test status
Simulation time 156861586 ps
CPU time 1.13 seconds
Started Jan 21 03:31:46 PM PST 24
Finished Jan 21 03:31:49 PM PST 24
Peak memory 199604 kb
Host smart-73705b35-53db-4349-928f-68bf2c4e4f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736609130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.736609130
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.1439599877
Short name T149
Test name
Test status
Simulation time 205442786 ps
CPU time 1.39 seconds
Started Jan 21 03:31:47 PM PST 24
Finished Jan 21 03:31:50 PM PST 24
Peak memory 199796 kb
Host smart-100e34f9-f2ad-4ae5-b299-ee92ec3db71a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439599877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.1439599877
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.2575462620
Short name T500
Test name
Test status
Simulation time 2510509797 ps
CPU time 11.64 seconds
Started Jan 21 03:31:39 PM PST 24
Finished Jan 21 03:31:53 PM PST 24
Peak memory 200108 kb
Host smart-1bde0772-8344-438b-a5bf-fe1e188bcdef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575462620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.2575462620
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.2911507551
Short name T595
Test name
Test status
Simulation time 405949708 ps
CPU time 2.24 seconds
Started Jan 21 03:31:47 PM PST 24
Finished Jan 21 03:31:51 PM PST 24
Peak memory 199676 kb
Host smart-bd28cc5a-6b9b-4b71-ac06-e295541cfe5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911507551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.2911507551
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.703406623
Short name T283
Test name
Test status
Simulation time 280244752 ps
CPU time 1.55 seconds
Started Jan 21 03:31:39 PM PST 24
Finished Jan 21 03:31:43 PM PST 24
Peak memory 199624 kb
Host smart-7597e060-2700-47d1-b60a-944aadb96ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703406623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.703406623
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.3540206226
Short name T376
Test name
Test status
Simulation time 61747041 ps
CPU time 0.83 seconds
Started Jan 21 03:31:44 PM PST 24
Finished Jan 21 03:31:46 PM PST 24
Peak memory 199564 kb
Host smart-a75a8e73-860c-4e72-b6b0-75fa78b50893
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540206226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.3540206226
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.2845077498
Short name T426
Test name
Test status
Simulation time 1227495593 ps
CPU time 5.53 seconds
Started Jan 21 03:31:38 PM PST 24
Finished Jan 21 03:31:46 PM PST 24
Peak memory 221704 kb
Host smart-3533015a-683f-4c4a-911e-32f090f7bc38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845077498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.2845077498
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.451814010
Short name T460
Test name
Test status
Simulation time 243532222 ps
CPU time 1.05 seconds
Started Jan 21 03:31:48 PM PST 24
Finished Jan 21 03:31:50 PM PST 24
Peak memory 216820 kb
Host smart-45ee982b-178d-42f6-83c3-26046b98b9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451814010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.451814010
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.2393763715
Short name T585
Test name
Test status
Simulation time 192458455 ps
CPU time 0.85 seconds
Started Jan 21 03:31:35 PM PST 24
Finished Jan 21 03:31:36 PM PST 24
Peak memory 199380 kb
Host smart-07db2af5-15af-48ed-a8ec-d8287a377124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393763715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.2393763715
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.3334307850
Short name T565
Test name
Test status
Simulation time 1018330286 ps
CPU time 5.05 seconds
Started Jan 21 03:31:36 PM PST 24
Finished Jan 21 03:31:45 PM PST 24
Peak memory 199756 kb
Host smart-f887b27b-6055-4239-a87a-e5f4a6a8e8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334307850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.3334307850
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.2894025831
Short name T535
Test name
Test status
Simulation time 168071019 ps
CPU time 1.17 seconds
Started Jan 21 03:31:38 PM PST 24
Finished Jan 21 03:31:42 PM PST 24
Peak memory 199520 kb
Host smart-16f36634-1ea4-4311-ab7f-40d90a0432f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894025831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.2894025831
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.3115475947
Short name T59
Test name
Test status
Simulation time 117691184 ps
CPU time 1.18 seconds
Started Jan 21 03:31:39 PM PST 24
Finished Jan 21 03:31:42 PM PST 24
Peak memory 200008 kb
Host smart-f127d576-8278-41ea-b0ed-9d3132e494f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115475947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.3115475947
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.3739313913
Short name T438
Test name
Test status
Simulation time 3037647749 ps
CPU time 13.86 seconds
Started Jan 21 03:31:51 PM PST 24
Finished Jan 21 03:32:07 PM PST 24
Peak memory 199784 kb
Host smart-01c5a947-a8cd-4640-ae1e-59d09dcbcf7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739313913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.3739313913
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.1987256046
Short name T52
Test name
Test status
Simulation time 551459134 ps
CPU time 3.02 seconds
Started Jan 21 03:31:39 PM PST 24
Finished Jan 21 03:31:44 PM PST 24
Peak memory 199868 kb
Host smart-61a59288-2e20-4a45-801c-14e24e1e5322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987256046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.1987256046
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.3294994301
Short name T354
Test name
Test status
Simulation time 225655418 ps
CPU time 1.31 seconds
Started Jan 21 03:31:49 PM PST 24
Finished Jan 21 03:31:52 PM PST 24
Peak memory 199500 kb
Host smart-a75d824b-da5d-434c-94e1-302ff37f2ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294994301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.3294994301
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.1219793617
Short name T489
Test name
Test status
Simulation time 63655172 ps
CPU time 0.76 seconds
Started Jan 21 03:31:45 PM PST 24
Finished Jan 21 03:31:47 PM PST 24
Peak memory 199520 kb
Host smart-95e121f3-fc19-42bb-951d-7e7b43d433a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219793617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.1219793617
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.3382409767
Short name T540
Test name
Test status
Simulation time 1886095246 ps
CPU time 7.13 seconds
Started Jan 21 03:31:51 PM PST 24
Finished Jan 21 03:32:00 PM PST 24
Peak memory 220572 kb
Host smart-5d60719c-185f-4f40-9574-3246ab6207e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382409767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.3382409767
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.172836809
Short name T490
Test name
Test status
Simulation time 246866718 ps
CPU time 1.08 seconds
Started Jan 21 03:31:43 PM PST 24
Finished Jan 21 03:31:46 PM PST 24
Peak memory 216912 kb
Host smart-c9fe587e-87f2-4c69-931f-346cb2e82d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172836809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.172836809
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.2191118397
Short name T13
Test name
Test status
Simulation time 73980211 ps
CPU time 0.74 seconds
Started Jan 21 03:31:44 PM PST 24
Finished Jan 21 03:31:46 PM PST 24
Peak memory 199400 kb
Host smart-41d9ad48-29ae-4580-9ae1-d8ea223e47f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191118397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.2191118397
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.3967923331
Short name T556
Test name
Test status
Simulation time 815707711 ps
CPU time 4.2 seconds
Started Jan 21 03:31:46 PM PST 24
Finished Jan 21 03:31:52 PM PST 24
Peak memory 199788 kb
Host smart-ef5133df-ffa0-4b31-bbfb-d39e30554d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967923331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.3967923331
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.4268885501
Short name T592
Test name
Test status
Simulation time 143108349 ps
CPU time 1.12 seconds
Started Jan 21 03:31:44 PM PST 24
Finished Jan 21 03:31:46 PM PST 24
Peak memory 199604 kb
Host smart-8228987c-d803-425b-afdf-e70bdb0e6c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268885501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.4268885501
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.1016901940
Short name T431
Test name
Test status
Simulation time 195774385 ps
CPU time 1.31 seconds
Started Jan 21 03:31:46 PM PST 24
Finished Jan 21 03:31:49 PM PST 24
Peak memory 199816 kb
Host smart-9b2694bc-2faa-4383-8a9c-4472b920ad35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016901940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.1016901940
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.4259595646
Short name T486
Test name
Test status
Simulation time 4106277798 ps
CPU time 13.79 seconds
Started Jan 21 03:31:44 PM PST 24
Finished Jan 21 03:31:59 PM PST 24
Peak memory 199812 kb
Host smart-589b0c35-b692-4043-a408-6236392d6390
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259595646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.4259595646
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.2709278021
Short name T436
Test name
Test status
Simulation time 391652842 ps
CPU time 2.06 seconds
Started Jan 21 03:31:45 PM PST 24
Finished Jan 21 03:31:48 PM PST 24
Peak memory 199492 kb
Host smart-773f084d-ee41-45a9-89b4-dd566a02bd9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709278021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.2709278021
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.721917727
Short name T417
Test name
Test status
Simulation time 130197742 ps
CPU time 1.07 seconds
Started Jan 21 03:31:53 PM PST 24
Finished Jan 21 03:31:55 PM PST 24
Peak memory 199568 kb
Host smart-5f53cf6a-c04d-4e8a-a113-e81aa2584450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721917727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.721917727
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.1070158356
Short name T526
Test name
Test status
Simulation time 80027431 ps
CPU time 0.76 seconds
Started Jan 21 03:31:49 PM PST 24
Finished Jan 21 03:31:51 PM PST 24
Peak memory 199560 kb
Host smart-ffd9f251-4c61-4483-a486-22d9d1fdccce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070158356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.1070158356
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.3394081564
Short name T604
Test name
Test status
Simulation time 2359721006 ps
CPU time 9.18 seconds
Started Jan 21 03:31:54 PM PST 24
Finished Jan 21 03:32:04 PM PST 24
Peak memory 217432 kb
Host smart-3d05ea96-91e2-492f-b09c-d8de13d78130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394081564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.3394081564
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.4135744151
Short name T415
Test name
Test status
Simulation time 246040013 ps
CPU time 1.12 seconds
Started Jan 21 03:31:55 PM PST 24
Finished Jan 21 03:31:58 PM PST 24
Peak memory 217000 kb
Host smart-23d4b9f9-565d-4c1c-bef9-568ad6d5021e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135744151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.4135744151
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.2124386091
Short name T256
Test name
Test status
Simulation time 146579579 ps
CPU time 0.87 seconds
Started Jan 21 03:31:54 PM PST 24
Finished Jan 21 03:31:57 PM PST 24
Peak memory 199380 kb
Host smart-1342f7b4-3f97-4268-9757-825b7b873728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124386091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.2124386091
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.765908433
Short name T577
Test name
Test status
Simulation time 1975708862 ps
CPU time 7.03 seconds
Started Jan 21 03:31:55 PM PST 24
Finished Jan 21 03:32:04 PM PST 24
Peak memory 199812 kb
Host smart-0270a0ce-9fbc-4970-a885-de14c1c3027b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765908433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.765908433
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.3561728108
Short name T267
Test name
Test status
Simulation time 170742632 ps
CPU time 1.15 seconds
Started Jan 21 03:31:51 PM PST 24
Finished Jan 21 03:31:54 PM PST 24
Peak memory 199512 kb
Host smart-fe4c1a61-c6cb-4ee2-b5bd-2f2ae5b652b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561728108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.3561728108
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.2261190449
Short name T11
Test name
Test status
Simulation time 200691333 ps
CPU time 1.34 seconds
Started Jan 21 03:31:45 PM PST 24
Finished Jan 21 03:31:48 PM PST 24
Peak memory 199812 kb
Host smart-013fc540-3051-4ded-b3ca-6d4ca6689b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261190449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.2261190449
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.1688684177
Short name T263
Test name
Test status
Simulation time 281699876 ps
CPU time 1.73 seconds
Started Jan 21 03:31:55 PM PST 24
Finished Jan 21 03:31:59 PM PST 24
Peak memory 199760 kb
Host smart-ddc6e6d7-6181-4949-89de-0ed419f560cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688684177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.1688684177
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.1769655341
Short name T344
Test name
Test status
Simulation time 329446832 ps
CPU time 2.13 seconds
Started Jan 21 03:31:54 PM PST 24
Finished Jan 21 03:31:58 PM PST 24
Peak memory 199600 kb
Host smart-5ae529cc-bfc6-457b-8f93-c2d1d42c1620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769655341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.1769655341
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.4018647807
Short name T358
Test name
Test status
Simulation time 190657542 ps
CPU time 1.27 seconds
Started Jan 21 03:31:52 PM PST 24
Finished Jan 21 03:31:55 PM PST 24
Peak memory 199604 kb
Host smart-aa98c392-2faf-4235-af6e-a5786e6179ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018647807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.4018647807
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.2187402766
Short name T373
Test name
Test status
Simulation time 78578104 ps
CPU time 0.81 seconds
Started Jan 21 03:31:51 PM PST 24
Finished Jan 21 03:31:53 PM PST 24
Peak memory 199544 kb
Host smart-152b2368-3c7f-4293-9452-a7b9f80108a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187402766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.2187402766
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.2905848004
Short name T398
Test name
Test status
Simulation time 2369307189 ps
CPU time 9.76 seconds
Started Jan 21 03:31:54 PM PST 24
Finished Jan 21 03:32:05 PM PST 24
Peak memory 217408 kb
Host smart-cea0798a-8fcf-4e38-9b9e-1d56037dec08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905848004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.2905848004
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.2938495629
Short name T473
Test name
Test status
Simulation time 243905869 ps
CPU time 1.1 seconds
Started Jan 21 03:31:55 PM PST 24
Finished Jan 21 03:31:58 PM PST 24
Peak memory 216904 kb
Host smart-6db6d2f7-666b-4f23-b17e-a347a47625f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938495629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.2938495629
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.297523637
Short name T5
Test name
Test status
Simulation time 130701604 ps
CPU time 0.79 seconds
Started Jan 21 03:31:52 PM PST 24
Finished Jan 21 03:31:54 PM PST 24
Peak memory 199396 kb
Host smart-daeb9e90-0ba3-4a85-b2b9-7cd1e25cce71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297523637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.297523637
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.564402422
Short name T499
Test name
Test status
Simulation time 2045216042 ps
CPU time 7.42 seconds
Started Jan 21 03:31:50 PM PST 24
Finished Jan 21 03:31:59 PM PST 24
Peak memory 199812 kb
Host smart-e5f0b177-da0b-4e88-b151-7f61320518ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564402422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.564402422
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.1491306145
Short name T497
Test name
Test status
Simulation time 146775971 ps
CPU time 1.09 seconds
Started Jan 21 03:31:58 PM PST 24
Finished Jan 21 03:32:01 PM PST 24
Peak memory 199604 kb
Host smart-ec5832ae-da8c-46d5-bfa3-bd7cb011f8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491306145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.1491306145
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.102262159
Short name T290
Test name
Test status
Simulation time 182664512 ps
CPU time 1.35 seconds
Started Jan 21 03:31:55 PM PST 24
Finished Jan 21 03:31:57 PM PST 24
Peak memory 199804 kb
Host smart-afb1cdcd-95cd-4af5-b257-3fc9f16d42b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102262159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.102262159
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.1565969028
Short name T287
Test name
Test status
Simulation time 1389498006 ps
CPU time 6.26 seconds
Started Jan 21 03:31:52 PM PST 24
Finished Jan 21 03:31:59 PM PST 24
Peak memory 199848 kb
Host smart-465f0b20-3fe9-4544-9954-2e63b7ff5baf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565969028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.1565969028
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.531565299
Short name T150
Test name
Test status
Simulation time 320992350 ps
CPU time 2.19 seconds
Started Jan 21 03:31:54 PM PST 24
Finished Jan 21 03:31:57 PM PST 24
Peak memory 199632 kb
Host smart-e1ca39a9-70a5-4cd9-a497-0459b1af9f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531565299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.531565299
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.3750014186
Short name T568
Test name
Test status
Simulation time 120530256 ps
CPU time 0.96 seconds
Started Jan 21 03:31:52 PM PST 24
Finished Jan 21 03:31:55 PM PST 24
Peak memory 199604 kb
Host smart-771a7780-8a70-412a-b42e-8f5f4a853ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750014186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.3750014186
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.127591079
Short name T161
Test name
Test status
Simulation time 72705671 ps
CPU time 0.78 seconds
Started Jan 21 03:32:02 PM PST 24
Finished Jan 21 03:32:03 PM PST 24
Peak memory 199536 kb
Host smart-cde94831-c55a-42d9-b4ca-e64a31061256
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127591079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.127591079
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.2122181230
Short name T248
Test name
Test status
Simulation time 243987958 ps
CPU time 1.08 seconds
Started Jan 21 03:32:12 PM PST 24
Finished Jan 21 03:32:14 PM PST 24
Peak memory 216800 kb
Host smart-360e863d-fa0a-4716-810c-5ef08989746a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122181230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.2122181230
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.2933899600
Short name T559
Test name
Test status
Simulation time 114582046 ps
CPU time 0.78 seconds
Started Jan 21 03:31:55 PM PST 24
Finished Jan 21 03:31:58 PM PST 24
Peak memory 199404 kb
Host smart-88a4c3e1-fce3-4b24-8982-08e2c2283a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933899600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.2933899600
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.618591841
Short name T80
Test name
Test status
Simulation time 1524700298 ps
CPU time 5.96 seconds
Started Jan 21 03:31:52 PM PST 24
Finished Jan 21 03:31:59 PM PST 24
Peak memory 199736 kb
Host smart-fb1351a2-0053-46f9-836b-62b89d8f8145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618591841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.618591841
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.3421027352
Short name T617
Test name
Test status
Simulation time 168577398 ps
CPU time 1.16 seconds
Started Jan 21 03:32:06 PM PST 24
Finished Jan 21 03:32:08 PM PST 24
Peak memory 199624 kb
Host smart-91a4a548-5a5e-468b-a520-91e144f86220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421027352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.3421027352
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.3249815005
Short name T361
Test name
Test status
Simulation time 202779921 ps
CPU time 1.5 seconds
Started Jan 21 03:31:54 PM PST 24
Finished Jan 21 03:31:56 PM PST 24
Peak memory 199696 kb
Host smart-75136c1d-13fd-48b8-b8db-24edad0c2944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249815005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.3249815005
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.1183843420
Short name T333
Test name
Test status
Simulation time 321656615 ps
CPU time 1.96 seconds
Started Jan 21 03:32:03 PM PST 24
Finished Jan 21 03:32:06 PM PST 24
Peak memory 199476 kb
Host smart-f6702884-4b81-435a-a9e1-b938acdd9dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183843420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.1183843420
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.4215073370
Short name T614
Test name
Test status
Simulation time 98537891 ps
CPU time 0.91 seconds
Started Jan 21 03:32:11 PM PST 24
Finished Jan 21 03:32:13 PM PST 24
Peak memory 199596 kb
Host smart-3804be03-0ad0-47fc-9723-ea5aaa333445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215073370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.4215073370
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.3985026645
Short name T295
Test name
Test status
Simulation time 68034150 ps
CPU time 0.74 seconds
Started Jan 21 03:32:02 PM PST 24
Finished Jan 21 03:32:04 PM PST 24
Peak memory 199544 kb
Host smart-8d7e425b-18e9-42be-92d7-376dac06f9ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985026645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.3985026645
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.2226213912
Short name T522
Test name
Test status
Simulation time 1892503968 ps
CPU time 7.15 seconds
Started Jan 21 03:32:12 PM PST 24
Finished Jan 21 03:32:20 PM PST 24
Peak memory 220696 kb
Host smart-d21e7682-2d0c-47b5-9538-ff2c2e78c643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226213912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.2226213912
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.2093948471
Short name T305
Test name
Test status
Simulation time 244490973 ps
CPU time 1.02 seconds
Started Jan 21 03:32:06 PM PST 24
Finished Jan 21 03:32:08 PM PST 24
Peak memory 216928 kb
Host smart-2b18740a-85d0-49a8-8707-3a4d26f3068b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093948471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.2093948471
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.3056385980
Short name T363
Test name
Test status
Simulation time 212740295 ps
CPU time 0.94 seconds
Started Jan 21 03:32:02 PM PST 24
Finished Jan 21 03:32:04 PM PST 24
Peak memory 199388 kb
Host smart-8ded8df2-8e2c-4a4a-82b4-97f34b43a5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056385980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.3056385980
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.475358980
Short name T478
Test name
Test status
Simulation time 918297516 ps
CPU time 5 seconds
Started Jan 21 03:32:12 PM PST 24
Finished Jan 21 03:32:18 PM PST 24
Peak memory 199688 kb
Host smart-d4f62580-bd4f-4b9d-bb69-9a659eaedf1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475358980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.475358980
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.784529680
Short name T308
Test name
Test status
Simulation time 143411340 ps
CPU time 1.1 seconds
Started Jan 21 03:32:04 PM PST 24
Finished Jan 21 03:32:06 PM PST 24
Peak memory 199608 kb
Host smart-1ad56686-6ad1-4cb5-b511-5937044b633e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784529680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.784529680
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.4289405658
Short name T291
Test name
Test status
Simulation time 130021935 ps
CPU time 1.19 seconds
Started Jan 21 03:32:02 PM PST 24
Finished Jan 21 03:32:04 PM PST 24
Peak memory 199732 kb
Host smart-a002a522-787c-4e68-bedb-80daf362a0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289405658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.4289405658
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.3701696086
Short name T567
Test name
Test status
Simulation time 7029000786 ps
CPU time 28.29 seconds
Started Jan 21 03:32:04 PM PST 24
Finished Jan 21 03:32:33 PM PST 24
Peak memory 199828 kb
Host smart-d61bc8d1-211d-4071-89fd-eed27b861692
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701696086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.3701696086
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.2817457146
Short name T422
Test name
Test status
Simulation time 141361520 ps
CPU time 1.71 seconds
Started Jan 21 03:32:03 PM PST 24
Finished Jan 21 03:32:06 PM PST 24
Peak memory 199652 kb
Host smart-5d78ec5d-0228-445b-ac81-6067365c739b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817457146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.2817457146
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.2227766204
Short name T165
Test name
Test status
Simulation time 107733161 ps
CPU time 0.89 seconds
Started Jan 21 03:32:12 PM PST 24
Finished Jan 21 03:32:14 PM PST 24
Peak memory 199596 kb
Host smart-2301edf2-c6c3-47e7-a296-31cecb4b6df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227766204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.2227766204
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.4174580916
Short name T589
Test name
Test status
Simulation time 55902500 ps
CPU time 0.68 seconds
Started Jan 21 03:32:18 PM PST 24
Finished Jan 21 03:32:22 PM PST 24
Peak memory 199508 kb
Host smart-ad11722b-eb88-43a0-be4e-026c38a83ff7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174580916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.4174580916
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.658260919
Short name T386
Test name
Test status
Simulation time 1226663217 ps
CPU time 5.77 seconds
Started Jan 21 03:32:12 PM PST 24
Finished Jan 21 03:32:19 PM PST 24
Peak memory 218052 kb
Host smart-cb31838d-c6b0-451e-8c09-f822cb1751c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658260919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.658260919
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.2583847691
Short name T525
Test name
Test status
Simulation time 245652320 ps
CPU time 0.99 seconds
Started Jan 21 03:32:08 PM PST 24
Finished Jan 21 03:32:09 PM PST 24
Peak memory 216888 kb
Host smart-5d3dbe4a-7f4a-4731-a31b-70ca778ab584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583847691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.2583847691
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.2009217400
Short name T532
Test name
Test status
Simulation time 135330585 ps
CPU time 0.79 seconds
Started Jan 21 03:32:05 PM PST 24
Finished Jan 21 03:32:07 PM PST 24
Peak memory 199412 kb
Host smart-cfcc9e82-b5bd-47a3-b33a-08b5b96daf79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009217400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.2009217400
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.498848303
Short name T242
Test name
Test status
Simulation time 1260884144 ps
CPU time 5.66 seconds
Started Jan 21 03:32:04 PM PST 24
Finished Jan 21 03:32:11 PM PST 24
Peak memory 199812 kb
Host smart-3e7bdb73-8bcf-4228-a592-e4cc8b199cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498848303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.498848303
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.2489435279
Short name T266
Test name
Test status
Simulation time 157239268 ps
CPU time 1.13 seconds
Started Jan 21 03:32:11 PM PST 24
Finished Jan 21 03:32:13 PM PST 24
Peak memory 199620 kb
Host smart-11aa805e-fb47-44fe-b958-d3b3886d8aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489435279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.2489435279
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.210996845
Short name T317
Test name
Test status
Simulation time 258702753 ps
CPU time 1.41 seconds
Started Jan 21 03:32:02 PM PST 24
Finished Jan 21 03:32:04 PM PST 24
Peak memory 199744 kb
Host smart-71a19550-bd4f-4459-974f-f753c22d857a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210996845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.210996845
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.3092243370
Short name T397
Test name
Test status
Simulation time 133778760 ps
CPU time 1.66 seconds
Started Jan 21 03:32:11 PM PST 24
Finished Jan 21 03:32:14 PM PST 24
Peak memory 199652 kb
Host smart-313be50b-2060-4e8f-aeb4-de4c44d0e498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092243370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.3092243370
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.1636302091
Short name T572
Test name
Test status
Simulation time 95150798 ps
CPU time 0.82 seconds
Started Jan 21 03:32:05 PM PST 24
Finished Jan 21 03:32:07 PM PST 24
Peak memory 199512 kb
Host smart-c3a1ec15-f936-4bc6-94fa-07900a59dd2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636302091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.1636302091
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.3815709088
Short name T257
Test name
Test status
Simulation time 64782097 ps
CPU time 0.76 seconds
Started Jan 21 03:32:21 PM PST 24
Finished Jan 21 03:32:24 PM PST 24
Peak memory 199520 kb
Host smart-eecb4e3c-1fb4-4aa9-b919-e92f21f33a35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815709088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.3815709088
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.490674253
Short name T48
Test name
Test status
Simulation time 1229838585 ps
CPU time 5.8 seconds
Started Jan 21 03:32:10 PM PST 24
Finished Jan 21 03:32:16 PM PST 24
Peak memory 217624 kb
Host smart-751985c3-6777-493e-9d6b-700e94c8e8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490674253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.490674253
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.288771146
Short name T279
Test name
Test status
Simulation time 243527244 ps
CPU time 1.1 seconds
Started Jan 21 03:32:11 PM PST 24
Finished Jan 21 03:32:13 PM PST 24
Peak memory 216900 kb
Host smart-aec0ab6d-e020-4fbb-a6ed-757f104335de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288771146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.288771146
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.1783122677
Short name T362
Test name
Test status
Simulation time 160568017 ps
CPU time 0.83 seconds
Started Jan 21 03:32:09 PM PST 24
Finished Jan 21 03:32:10 PM PST 24
Peak memory 199340 kb
Host smart-293903b9-2190-49f9-8ae0-13bfe7194f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783122677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.1783122677
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.1085229360
Short name T571
Test name
Test status
Simulation time 1329133187 ps
CPU time 5.48 seconds
Started Jan 21 03:32:12 PM PST 24
Finished Jan 21 03:32:18 PM PST 24
Peak memory 199788 kb
Host smart-411a505b-e665-4527-a5f6-b7d8463f68eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085229360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.1085229360
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.2396275154
Short name T346
Test name
Test status
Simulation time 171199867 ps
CPU time 1.12 seconds
Started Jan 21 03:32:13 PM PST 24
Finished Jan 21 03:32:15 PM PST 24
Peak memory 199604 kb
Host smart-0011f0f4-b9ba-415a-ab8b-034322d6cefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396275154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.2396275154
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.3247326902
Short name T251
Test name
Test status
Simulation time 253951966 ps
CPU time 1.55 seconds
Started Jan 21 03:32:14 PM PST 24
Finished Jan 21 03:32:16 PM PST 24
Peak memory 199792 kb
Host smart-7ddaa504-6058-475d-b8ce-9ba5041d5fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247326902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.3247326902
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.1618660857
Short name T109
Test name
Test status
Simulation time 3667940457 ps
CPU time 13.23 seconds
Started Jan 21 03:32:14 PM PST 24
Finished Jan 21 03:32:28 PM PST 24
Peak memory 199784 kb
Host smart-9dfb6ea5-0826-4d78-a542-2f8be95a579f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618660857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.1618660857
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.2304657835
Short name T319
Test name
Test status
Simulation time 478455747 ps
CPU time 2.57 seconds
Started Jan 21 03:32:15 PM PST 24
Finished Jan 21 03:32:19 PM PST 24
Peak memory 199660 kb
Host smart-4a3b5280-827f-48ae-9f50-14e2cf88d797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304657835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.2304657835
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.1084716680
Short name T488
Test name
Test status
Simulation time 117788215 ps
CPU time 1.07 seconds
Started Jan 21 03:32:14 PM PST 24
Finished Jan 21 03:32:16 PM PST 24
Peak memory 199520 kb
Host smart-6cce7a85-63be-4162-aca2-623c81db79c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084716680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.1084716680
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.3055374930
Short name T596
Test name
Test status
Simulation time 94649684 ps
CPU time 0.82 seconds
Started Jan 21 03:32:25 PM PST 24
Finished Jan 21 03:32:26 PM PST 24
Peak memory 199492 kb
Host smart-616b5a19-2d9c-4835-a20b-a95213f180a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055374930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.3055374930
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.1597122061
Short name T349
Test name
Test status
Simulation time 1902752124 ps
CPU time 7.23 seconds
Started Jan 21 03:32:21 PM PST 24
Finished Jan 21 03:32:30 PM PST 24
Peak memory 221736 kb
Host smart-9147828f-b6bb-4b9f-9d0b-c28b1c9ac70e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597122061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.1597122061
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.3612816252
Short name T493
Test name
Test status
Simulation time 243539731 ps
CPU time 1.08 seconds
Started Jan 21 03:32:23 PM PST 24
Finished Jan 21 03:32:26 PM PST 24
Peak memory 216892 kb
Host smart-6c226c92-bc00-4fdf-ad53-1848442224fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612816252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.3612816252
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.3063777446
Short name T424
Test name
Test status
Simulation time 223405460 ps
CPU time 0.89 seconds
Started Jan 21 03:32:25 PM PST 24
Finished Jan 21 03:32:26 PM PST 24
Peak memory 199308 kb
Host smart-18a61d87-aebc-4764-90b9-a33285029d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063777446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.3063777446
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.979950944
Short name T82
Test name
Test status
Simulation time 897208944 ps
CPU time 4.59 seconds
Started Jan 21 03:32:22 PM PST 24
Finished Jan 21 03:32:28 PM PST 24
Peak memory 199768 kb
Host smart-df4864cc-f7ab-4d8f-9ebb-b67bfb983b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979950944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.979950944
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.469685525
Short name T44
Test name
Test status
Simulation time 144366352 ps
CPU time 1.14 seconds
Started Jan 21 03:32:25 PM PST 24
Finished Jan 21 03:32:27 PM PST 24
Peak memory 199572 kb
Host smart-06ac4925-6abf-4d92-a3aa-4afc561d056c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469685525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.469685525
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.2753387578
Short name T259
Test name
Test status
Simulation time 229201153 ps
CPU time 1.53 seconds
Started Jan 21 03:32:22 PM PST 24
Finished Jan 21 03:32:25 PM PST 24
Peak memory 199784 kb
Host smart-d9655119-d92c-42f2-b85d-0ebd7dfa8e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753387578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.2753387578
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.2064858535
Short name T491
Test name
Test status
Simulation time 1710958151 ps
CPU time 7.63 seconds
Started Jan 21 03:32:24 PM PST 24
Finished Jan 21 03:32:33 PM PST 24
Peak memory 199756 kb
Host smart-06740072-017c-4cff-9538-3a6692d59946
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064858535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.2064858535
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.2470215713
Short name T534
Test name
Test status
Simulation time 149914852 ps
CPU time 1.9 seconds
Started Jan 21 03:32:21 PM PST 24
Finished Jan 21 03:32:24 PM PST 24
Peak memory 199644 kb
Host smart-10d50073-a50f-4818-b09a-6bca6e8f12f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470215713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.2470215713
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.3229871294
Short name T430
Test name
Test status
Simulation time 101579678 ps
CPU time 0.91 seconds
Started Jan 21 03:32:23 PM PST 24
Finished Jan 21 03:32:26 PM PST 24
Peak memory 199564 kb
Host smart-1bf68f61-a0e3-4de8-a38c-22cf823952a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229871294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.3229871294
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.754459030
Short name T531
Test name
Test status
Simulation time 68900202 ps
CPU time 0.73 seconds
Started Jan 21 03:30:23 PM PST 24
Finished Jan 21 03:30:30 PM PST 24
Peak memory 199784 kb
Host smart-522872b7-8ccf-4a8e-8204-e11d75b8bbcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754459030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.754459030
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.952172287
Short name T50
Test name
Test status
Simulation time 2351557930 ps
CPU time 8.67 seconds
Started Jan 21 03:30:16 PM PST 24
Finished Jan 21 03:30:25 PM PST 24
Peak memory 218504 kb
Host smart-96e01da5-30d6-443e-8544-de26c241b6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952172287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.952172287
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.459327152
Short name T468
Test name
Test status
Simulation time 243825379 ps
CPU time 1.1 seconds
Started Jan 21 03:30:24 PM PST 24
Finished Jan 21 03:30:31 PM PST 24
Peak memory 216824 kb
Host smart-0605b2b4-a086-4edb-8cdc-92f8c637e7ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459327152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.459327152
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.1587875366
Short name T447
Test name
Test status
Simulation time 130493662 ps
CPU time 0.76 seconds
Started Jan 21 03:30:17 PM PST 24
Finished Jan 21 03:30:19 PM PST 24
Peak memory 199400 kb
Host smart-d32c241f-c00a-48ab-b838-d4e53204e5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587875366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.1587875366
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.2428840077
Short name T166
Test name
Test status
Simulation time 951339183 ps
CPU time 4.87 seconds
Started Jan 21 03:30:17 PM PST 24
Finished Jan 21 03:30:23 PM PST 24
Peak memory 199620 kb
Host smart-242c7e89-8ebe-4557-9363-534b1c799ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428840077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.2428840077
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.1912939427
Short name T70
Test name
Test status
Simulation time 8298139229 ps
CPU time 17.12 seconds
Started Jan 21 03:30:26 PM PST 24
Finished Jan 21 03:30:48 PM PST 24
Peak memory 216508 kb
Host smart-df66a52e-b2e8-47e4-b3d2-679e8af45764
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912939427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.1912939427
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.3585972281
Short name T440
Test name
Test status
Simulation time 184203072 ps
CPU time 1.17 seconds
Started Jan 21 03:30:23 PM PST 24
Finished Jan 21 03:30:31 PM PST 24
Peak memory 199808 kb
Host smart-a6a874db-de9b-4d84-b67d-b18c80469f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585972281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.3585972281
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.3039376417
Short name T408
Test name
Test status
Simulation time 115985724 ps
CPU time 1.25 seconds
Started Jan 21 03:30:21 PM PST 24
Finished Jan 21 03:30:24 PM PST 24
Peak memory 199728 kb
Host smart-b52e1dda-11da-4483-bda7-323278502f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039376417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.3039376417
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.1696443617
Short name T479
Test name
Test status
Simulation time 13817634163 ps
CPU time 48.12 seconds
Started Jan 21 03:30:22 PM PST 24
Finished Jan 21 03:31:12 PM PST 24
Peak memory 199844 kb
Host smart-65eec5f5-25d3-4b96-ab05-d439015070ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696443617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.1696443617
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.699770084
Short name T370
Test name
Test status
Simulation time 202233794 ps
CPU time 1.23 seconds
Started Jan 21 03:30:22 PM PST 24
Finished Jan 21 03:30:25 PM PST 24
Peak memory 199596 kb
Host smart-b9cecba5-b0e2-4282-857c-e9533ce663cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699770084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.699770084
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.2970129385
Short name T315
Test name
Test status
Simulation time 70902981 ps
CPU time 0.78 seconds
Started Jan 21 03:32:33 PM PST 24
Finished Jan 21 03:32:36 PM PST 24
Peak memory 199492 kb
Host smart-fb0b9d5a-2a5f-4443-9cf4-6696e2151ce4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970129385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.2970129385
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.3974999889
Short name T36
Test name
Test status
Simulation time 1893626086 ps
CPU time 7.74 seconds
Started Jan 21 03:32:33 PM PST 24
Finished Jan 21 03:32:43 PM PST 24
Peak memory 217216 kb
Host smart-8313dfa1-a1a4-4f39-a962-bef0c2a97dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974999889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.3974999889
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.3293746251
Short name T334
Test name
Test status
Simulation time 244618217 ps
CPU time 1.05 seconds
Started Jan 21 03:32:32 PM PST 24
Finished Jan 21 03:32:35 PM PST 24
Peak memory 207120 kb
Host smart-6684ffa8-9019-49f2-8d70-7ec5ae113997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293746251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.3293746251
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.790598090
Short name T461
Test name
Test status
Simulation time 105980755 ps
CPU time 0.76 seconds
Started Jan 21 03:32:25 PM PST 24
Finished Jan 21 03:32:26 PM PST 24
Peak memory 199332 kb
Host smart-88e1ca75-aec6-407e-8e7c-f762efde8c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790598090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.790598090
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.1318219183
Short name T352
Test name
Test status
Simulation time 850366078 ps
CPU time 4.11 seconds
Started Jan 21 03:32:25 PM PST 24
Finished Jan 21 03:32:30 PM PST 24
Peak memory 199796 kb
Host smart-05c473ab-a14f-4cdd-b303-2ef63c0499a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318219183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.1318219183
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.1013531253
Short name T255
Test name
Test status
Simulation time 155565271 ps
CPU time 1.12 seconds
Started Jan 21 03:32:25 PM PST 24
Finished Jan 21 03:32:27 PM PST 24
Peak memory 199624 kb
Host smart-98392931-ae58-489b-8a1d-706a8c0f056f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013531253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.1013531253
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.1037459811
Short name T558
Test name
Test status
Simulation time 197625081 ps
CPU time 1.44 seconds
Started Jan 21 03:32:25 PM PST 24
Finished Jan 21 03:32:27 PM PST 24
Peak memory 199816 kb
Host smart-51709c0b-cafd-4a4e-ad07-5609cae494b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037459811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.1037459811
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.1955240626
Short name T439
Test name
Test status
Simulation time 1607953916 ps
CPU time 6.88 seconds
Started Jan 21 03:32:31 PM PST 24
Finished Jan 21 03:32:39 PM PST 24
Peak memory 199432 kb
Host smart-0fdf0cc5-f119-474c-b38c-f000e89bb98c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955240626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.1955240626
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.1516754482
Short name T245
Test name
Test status
Simulation time 137999068 ps
CPU time 1.65 seconds
Started Jan 21 03:32:21 PM PST 24
Finished Jan 21 03:32:24 PM PST 24
Peak memory 199608 kb
Host smart-6740b679-1fea-4052-99f9-30e066a8115b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516754482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.1516754482
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.16825060
Short name T496
Test name
Test status
Simulation time 147064775 ps
CPU time 1.22 seconds
Started Jan 21 03:32:21 PM PST 24
Finished Jan 21 03:32:24 PM PST 24
Peak memory 199780 kb
Host smart-6a0de758-e31a-42c6-988a-20cc9b6ebb63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16825060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.16825060
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.2423124039
Short name T10
Test name
Test status
Simulation time 64081120 ps
CPU time 0.73 seconds
Started Jan 21 03:32:30 PM PST 24
Finished Jan 21 03:32:33 PM PST 24
Peak memory 199572 kb
Host smart-3518febb-c436-4475-8fd2-a3fa2d63ca90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423124039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.2423124039
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.777351807
Short name T307
Test name
Test status
Simulation time 2175553801 ps
CPU time 8.07 seconds
Started Jan 21 03:32:33 PM PST 24
Finished Jan 21 03:32:43 PM PST 24
Peak memory 217596 kb
Host smart-2187c655-6f40-4f00-bcb1-fc245611c06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777351807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.777351807
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.3095405924
Short name T523
Test name
Test status
Simulation time 244033189 ps
CPU time 1.17 seconds
Started Jan 21 03:32:26 PM PST 24
Finished Jan 21 03:32:28 PM PST 24
Peak memory 216740 kb
Host smart-a8d6c1ac-40b1-4560-861e-d1e91610d4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095405924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.3095405924
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.1804288975
Short name T289
Test name
Test status
Simulation time 173163477 ps
CPU time 0.82 seconds
Started Jan 21 03:32:27 PM PST 24
Finished Jan 21 03:32:29 PM PST 24
Peak memory 199408 kb
Host smart-02365cb2-b568-4667-b679-34e9c0840752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804288975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.1804288975
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.2501731703
Short name T465
Test name
Test status
Simulation time 698544363 ps
CPU time 3.85 seconds
Started Jan 21 03:32:28 PM PST 24
Finished Jan 21 03:32:33 PM PST 24
Peak memory 199780 kb
Host smart-61d25cab-fa00-4253-9c06-6962b8f8dc22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501731703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.2501731703
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.3647730740
Short name T282
Test name
Test status
Simulation time 148909202 ps
CPU time 1.14 seconds
Started Jan 21 03:32:33 PM PST 24
Finished Jan 21 03:32:36 PM PST 24
Peak memory 199664 kb
Host smart-713b8074-d67b-4c6b-9b95-210205c7b44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647730740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.3647730740
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.2488674896
Short name T483
Test name
Test status
Simulation time 123608047 ps
CPU time 1.2 seconds
Started Jan 21 03:32:28 PM PST 24
Finished Jan 21 03:32:30 PM PST 24
Peak memory 199776 kb
Host smart-c7b466cf-17a5-4269-8de5-ec928b49c539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488674896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.2488674896
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.4289467414
Short name T342
Test name
Test status
Simulation time 7022799667 ps
CPU time 27.13 seconds
Started Jan 21 03:32:36 PM PST 24
Finished Jan 21 03:33:04 PM PST 24
Peak memory 199964 kb
Host smart-8118a2d4-00b3-490c-8966-2590de6f08ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289467414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.4289467414
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.764673215
Short name T443
Test name
Test status
Simulation time 117568741 ps
CPU time 1.52 seconds
Started Jan 21 03:32:30 PM PST 24
Finished Jan 21 03:32:34 PM PST 24
Peak memory 199680 kb
Host smart-bade1620-ee24-49ca-a20b-af5cce894677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764673215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.764673215
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.1149812357
Short name T550
Test name
Test status
Simulation time 164325633 ps
CPU time 1.12 seconds
Started Jan 21 03:32:31 PM PST 24
Finished Jan 21 03:32:33 PM PST 24
Peak memory 199164 kb
Host smart-1051b908-d470-4d6c-be8f-3c84f0a084ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149812357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.1149812357
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.3449908816
Short name T353
Test name
Test status
Simulation time 71236825 ps
CPU time 0.76 seconds
Started Jan 21 03:32:33 PM PST 24
Finished Jan 21 03:32:36 PM PST 24
Peak memory 199496 kb
Host smart-f1b0ffbf-56e3-4afd-a9c0-087fac9f3fd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449908816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.3449908816
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.358911448
Short name T25
Test name
Test status
Simulation time 2184842820 ps
CPU time 8.02 seconds
Started Jan 21 03:32:27 PM PST 24
Finished Jan 21 03:32:37 PM PST 24
Peak memory 217960 kb
Host smart-cc4eaa0c-309d-437d-bfc5-6b3b2dab7c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358911448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.358911448
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.2002993749
Short name T611
Test name
Test status
Simulation time 245816546 ps
CPU time 1.06 seconds
Started Jan 21 03:32:31 PM PST 24
Finished Jan 21 03:32:34 PM PST 24
Peak memory 216796 kb
Host smart-9904b00b-d95d-4daf-858c-6278715a14e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002993749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.2002993749
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.3394105078
Short name T246
Test name
Test status
Simulation time 107063528 ps
CPU time 0.74 seconds
Started Jan 21 03:32:28 PM PST 24
Finished Jan 21 03:32:30 PM PST 24
Peak memory 199400 kb
Host smart-2bf1b7dc-fcc1-4a3a-aa68-081ce656dd36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394105078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.3394105078
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.593902745
Short name T146
Test name
Test status
Simulation time 1478496274 ps
CPU time 5.61 seconds
Started Jan 21 03:32:26 PM PST 24
Finished Jan 21 03:32:33 PM PST 24
Peak memory 199716 kb
Host smart-2abbe9c3-d591-4f9d-93cf-4f3501a35f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593902745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.593902745
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.1725941332
Short name T401
Test name
Test status
Simulation time 184207333 ps
CPU time 1.2 seconds
Started Jan 21 03:32:29 PM PST 24
Finished Jan 21 03:32:31 PM PST 24
Peak memory 199572 kb
Host smart-e4561e9d-92a5-46fc-a2c5-0fd0c77e4d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725941332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.1725941332
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.2620058641
Short name T616
Test name
Test status
Simulation time 253241387 ps
CPU time 1.43 seconds
Started Jan 21 03:32:26 PM PST 24
Finished Jan 21 03:32:28 PM PST 24
Peak memory 199796 kb
Host smart-31780bbb-ec99-4ecb-b0bf-843a54f86d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620058641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.2620058641
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.1328445417
Short name T603
Test name
Test status
Simulation time 2006666906 ps
CPU time 9.6 seconds
Started Jan 21 03:32:33 PM PST 24
Finished Jan 21 03:32:45 PM PST 24
Peak memory 199716 kb
Host smart-eb21cde8-66da-4a92-8f72-5faffe3b69e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328445417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.1328445417
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.901168914
Short name T551
Test name
Test status
Simulation time 126411296 ps
CPU time 1.7 seconds
Started Jan 21 03:32:31 PM PST 24
Finished Jan 21 03:32:34 PM PST 24
Peak memory 199716 kb
Host smart-ae14315e-997c-4b83-ac5e-319684dd78d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901168914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.901168914
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.960315844
Short name T355
Test name
Test status
Simulation time 159106976 ps
CPU time 1.21 seconds
Started Jan 21 03:32:30 PM PST 24
Finished Jan 21 03:32:33 PM PST 24
Peak memory 199604 kb
Host smart-c5570c3d-9d12-4b89-ad51-f6ce5be3355e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960315844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.960315844
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.2113158102
Short name T474
Test name
Test status
Simulation time 78280997 ps
CPU time 0.76 seconds
Started Jan 21 03:32:43 PM PST 24
Finished Jan 21 03:32:45 PM PST 24
Peak memory 199576 kb
Host smart-69d2f0fd-87f7-4342-94c1-9194363ee1e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113158102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.2113158102
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.688089710
Short name T387
Test name
Test status
Simulation time 1227258292 ps
CPU time 5.7 seconds
Started Jan 21 03:32:43 PM PST 24
Finished Jan 21 03:32:49 PM PST 24
Peak memory 216544 kb
Host smart-33fbf604-e315-40f2-bb23-d886fa886234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688089710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.688089710
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.1275445084
Short name T338
Test name
Test status
Simulation time 244125322 ps
CPU time 1.13 seconds
Started Jan 21 03:32:36 PM PST 24
Finished Jan 21 03:32:38 PM PST 24
Peak memory 217000 kb
Host smart-6fb0180f-9a6e-4b94-a9a1-271be5534261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275445084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.1275445084
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.1435941746
Short name T16
Test name
Test status
Simulation time 205112499 ps
CPU time 0.96 seconds
Started Jan 21 03:32:57 PM PST 24
Finished Jan 21 03:33:10 PM PST 24
Peak memory 199336 kb
Host smart-60cc58dc-33a0-41f0-8e3f-4dc7ce4382f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435941746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.1435941746
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.3071451100
Short name T613
Test name
Test status
Simulation time 1104005567 ps
CPU time 4.57 seconds
Started Jan 21 03:32:37 PM PST 24
Finished Jan 21 03:32:43 PM PST 24
Peak memory 199760 kb
Host smart-d3ae8ca5-a8b5-41ea-9d7b-807ef7e9b076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071451100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.3071451100
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.603150317
Short name T297
Test name
Test status
Simulation time 170574995 ps
CPU time 1.16 seconds
Started Jan 21 03:32:36 PM PST 24
Finished Jan 21 03:32:38 PM PST 24
Peak memory 199812 kb
Host smart-d77ba517-5a6c-41d9-8ae3-48999f45db04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603150317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.603150317
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.2191349239
Short name T326
Test name
Test status
Simulation time 118609612 ps
CPU time 1.18 seconds
Started Jan 21 03:32:37 PM PST 24
Finished Jan 21 03:32:39 PM PST 24
Peak memory 199832 kb
Host smart-946ebfe4-db26-4f2a-8845-8fcdc62e47fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191349239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.2191349239
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.925305527
Short name T533
Test name
Test status
Simulation time 5960211977 ps
CPU time 26.73 seconds
Started Jan 21 03:32:40 PM PST 24
Finished Jan 21 03:33:08 PM PST 24
Peak memory 199780 kb
Host smart-78f51af5-d418-4af6-b2c0-278c09a99bba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925305527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.925305527
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.3086063208
Short name T87
Test name
Test status
Simulation time 149320755 ps
CPU time 1.84 seconds
Started Jan 21 03:32:49 PM PST 24
Finished Jan 21 03:32:54 PM PST 24
Peak memory 199512 kb
Host smart-60f7dd0e-226f-40f4-a1cb-82679b794b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086063208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.3086063208
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.1907183241
Short name T368
Test name
Test status
Simulation time 81832939 ps
CPU time 0.81 seconds
Started Jan 21 03:32:40 PM PST 24
Finished Jan 21 03:32:42 PM PST 24
Peak memory 199604 kb
Host smart-403828cc-104e-4940-974e-6e55c7ca9922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907183241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.1907183241
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.1926083503
Short name T530
Test name
Test status
Simulation time 81283971 ps
CPU time 0.85 seconds
Started Jan 21 03:32:39 PM PST 24
Finished Jan 21 03:32:40 PM PST 24
Peak memory 199480 kb
Host smart-995cfc99-1772-4313-9fb2-4c93582c8954
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926083503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.1926083503
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.3566783148
Short name T366
Test name
Test status
Simulation time 1236173157 ps
CPU time 5.73 seconds
Started Jan 21 03:32:43 PM PST 24
Finished Jan 21 03:32:49 PM PST 24
Peak memory 217044 kb
Host smart-cbcdc8c6-cca9-4321-a44a-fd13030d2430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566783148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.3566783148
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.2092386134
Short name T495
Test name
Test status
Simulation time 244162693 ps
CPU time 1.04 seconds
Started Jan 21 03:32:38 PM PST 24
Finished Jan 21 03:32:40 PM PST 24
Peak memory 216896 kb
Host smart-3e2502bc-8e85-44cc-988b-45414317f3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092386134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.2092386134
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.1302188510
Short name T578
Test name
Test status
Simulation time 90484861 ps
CPU time 0.78 seconds
Started Jan 21 03:32:40 PM PST 24
Finished Jan 21 03:32:41 PM PST 24
Peak memory 199400 kb
Host smart-9611cdb3-68eb-4086-b48f-cc667d3923c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302188510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.1302188510
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.3641770670
Short name T117
Test name
Test status
Simulation time 843627409 ps
CPU time 4.07 seconds
Started Jan 21 03:32:43 PM PST 24
Finished Jan 21 03:32:48 PM PST 24
Peak memory 199876 kb
Host smart-c6446c54-a77b-4d25-9b8e-4cc3ed8b6452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641770670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.3641770670
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.1702336238
Short name T311
Test name
Test status
Simulation time 145874238 ps
CPU time 1.07 seconds
Started Jan 21 03:32:35 PM PST 24
Finished Jan 21 03:32:37 PM PST 24
Peak memory 199464 kb
Host smart-a5ad17a2-99b0-42bf-8bcb-699ed273ab6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702336238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.1702336238
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.3486060290
Short name T137
Test name
Test status
Simulation time 244030895 ps
CPU time 1.44 seconds
Started Jan 21 03:32:57 PM PST 24
Finished Jan 21 03:33:10 PM PST 24
Peak memory 199672 kb
Host smart-5f04dca7-17eb-4b64-85c7-4e029fed7e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486060290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.3486060290
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.1634197388
Short name T365
Test name
Test status
Simulation time 3554061933 ps
CPU time 16.03 seconds
Started Jan 21 03:32:39 PM PST 24
Finished Jan 21 03:32:56 PM PST 24
Peak memory 199848 kb
Host smart-374beb7a-499c-46e6-ba02-5ce8f4e525df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634197388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.1634197388
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.2922949067
Short name T407
Test name
Test status
Simulation time 305861672 ps
CPU time 1.97 seconds
Started Jan 21 03:32:37 PM PST 24
Finished Jan 21 03:32:39 PM PST 24
Peak memory 199580 kb
Host smart-eb968d72-b820-4fb9-b81a-5eab82acb301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922949067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.2922949067
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.62455908
Short name T502
Test name
Test status
Simulation time 74154989 ps
CPU time 0.82 seconds
Started Jan 21 03:32:40 PM PST 24
Finished Jan 21 03:32:41 PM PST 24
Peak memory 199600 kb
Host smart-771813b2-1469-40da-8992-73d8a66f8076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62455908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.62455908
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.404817894
Short name T107
Test name
Test status
Simulation time 70990553 ps
CPU time 0.77 seconds
Started Jan 21 03:32:40 PM PST 24
Finished Jan 21 03:32:41 PM PST 24
Peak memory 199496 kb
Host smart-6560e294-a093-4a7c-9bfa-f72f2ae47a03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404817894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.404817894
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.821854564
Short name T31
Test name
Test status
Simulation time 1220703789 ps
CPU time 6.02 seconds
Started Jan 21 03:32:49 PM PST 24
Finished Jan 21 03:32:58 PM PST 24
Peak memory 216988 kb
Host smart-b9808d83-680a-4e57-aa67-e4e0f7c90bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821854564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.821854564
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.136334794
Short name T249
Test name
Test status
Simulation time 244952617 ps
CPU time 1.12 seconds
Started Jan 21 03:32:39 PM PST 24
Finished Jan 21 03:32:41 PM PST 24
Peak memory 216864 kb
Host smart-3dc0c080-8ac0-462f-82c4-e0b7c2be9b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136334794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.136334794
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.723154867
Short name T564
Test name
Test status
Simulation time 116450121 ps
CPU time 0.75 seconds
Started Jan 21 03:32:40 PM PST 24
Finished Jan 21 03:32:42 PM PST 24
Peak memory 199412 kb
Host smart-5c1c7fef-ec65-4468-af43-0d84d546bd40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723154867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.723154867
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.2336863494
Short name T393
Test name
Test status
Simulation time 993989663 ps
CPU time 4.96 seconds
Started Jan 21 03:32:43 PM PST 24
Finished Jan 21 03:32:49 PM PST 24
Peak memory 200004 kb
Host smart-128d7e8a-b4c4-4bfe-893e-e9ccec36382a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336863494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.2336863494
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.1116961271
Short name T615
Test name
Test status
Simulation time 174902072 ps
CPU time 1.22 seconds
Started Jan 21 03:32:43 PM PST 24
Finished Jan 21 03:32:45 PM PST 24
Peak memory 199628 kb
Host smart-3c2eff17-1900-40b1-a11c-c92543bf4113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116961271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.1116961271
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.1368484427
Short name T151
Test name
Test status
Simulation time 120821962 ps
CPU time 1.15 seconds
Started Jan 21 03:32:37 PM PST 24
Finished Jan 21 03:32:39 PM PST 24
Peak memory 199780 kb
Host smart-21a7eeee-2fa1-4017-a95b-02bc69f0b7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368484427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.1368484427
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.1542847655
Short name T247
Test name
Test status
Simulation time 1022072320 ps
CPU time 4.71 seconds
Started Jan 21 03:32:57 PM PST 24
Finished Jan 21 03:33:14 PM PST 24
Peak memory 199692 kb
Host smart-5e9a19ef-5491-4053-9b51-059b513d3559
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542847655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.1542847655
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.3855876104
Short name T300
Test name
Test status
Simulation time 250915909 ps
CPU time 1.77 seconds
Started Jan 21 03:33:10 PM PST 24
Finished Jan 21 03:33:22 PM PST 24
Peak memory 199628 kb
Host smart-a3e8cb30-f4d4-43fc-80c1-9a78db59c5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855876104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.3855876104
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.4024755756
Short name T448
Test name
Test status
Simulation time 89114570 ps
CPU time 0.82 seconds
Started Jan 21 03:32:35 PM PST 24
Finished Jan 21 03:32:36 PM PST 24
Peak memory 199560 kb
Host smart-ff4b84fd-f092-4912-8883-85135e0f95e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024755756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.4024755756
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.988873604
Short name T321
Test name
Test status
Simulation time 62330966 ps
CPU time 0.72 seconds
Started Jan 21 03:32:37 PM PST 24
Finished Jan 21 03:32:39 PM PST 24
Peak memory 199576 kb
Host smart-62dea17d-2bb9-4328-9df3-2c72dec83311
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988873604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.988873604
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.2110719691
Short name T32
Test name
Test status
Simulation time 2169764715 ps
CPU time 7.93 seconds
Started Jan 21 03:32:40 PM PST 24
Finished Jan 21 03:32:49 PM PST 24
Peak memory 216808 kb
Host smart-59d31e78-c9f2-4348-9c58-60026f152fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110719691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.2110719691
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.3618838086
Short name T385
Test name
Test status
Simulation time 244149060 ps
CPU time 1.07 seconds
Started Jan 21 03:32:41 PM PST 24
Finished Jan 21 03:32:43 PM PST 24
Peak memory 216788 kb
Host smart-5c61d093-db2b-41b1-b246-81f5bc7fb935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618838086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.3618838086
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.1031536149
Short name T503
Test name
Test status
Simulation time 178958735 ps
CPU time 0.88 seconds
Started Jan 21 03:32:37 PM PST 24
Finished Jan 21 03:32:38 PM PST 24
Peak memory 199388 kb
Host smart-742b7a22-c4f7-4b6b-bc1b-9ea1098312e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031536149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.1031536149
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.1832552766
Short name T620
Test name
Test status
Simulation time 939447565 ps
CPU time 4.94 seconds
Started Jan 21 03:32:57 PM PST 24
Finished Jan 21 03:33:14 PM PST 24
Peak memory 199764 kb
Host smart-3827937e-69c0-4d72-89f2-bd0616c2c13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832552766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.1832552766
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.1040822149
Short name T409
Test name
Test status
Simulation time 161999378 ps
CPU time 1.1 seconds
Started Jan 21 03:32:43 PM PST 24
Finished Jan 21 03:32:45 PM PST 24
Peak memory 199600 kb
Host smart-683a2fb6-86ce-4ce9-afe6-acf51a6e3a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040822149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.1040822149
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.3703128727
Short name T359
Test name
Test status
Simulation time 246907080 ps
CPU time 1.57 seconds
Started Jan 21 03:32:35 PM PST 24
Finished Jan 21 03:32:37 PM PST 24
Peak memory 199732 kb
Host smart-5682af34-facb-4f5b-bc93-140733537273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703128727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.3703128727
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.238145681
Short name T618
Test name
Test status
Simulation time 1062864739 ps
CPU time 4.76 seconds
Started Jan 21 03:32:40 PM PST 24
Finished Jan 21 03:32:45 PM PST 24
Peak memory 199800 kb
Host smart-ffdfe7a1-94b7-4658-9298-35ff26c8c1f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238145681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.238145681
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.1497434486
Short name T88
Test name
Test status
Simulation time 144485899 ps
CPU time 1.81 seconds
Started Jan 21 03:32:36 PM PST 24
Finished Jan 21 03:32:39 PM PST 24
Peak memory 199636 kb
Host smart-d0e2aea0-a463-4da7-b6dc-c108eca706b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497434486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.1497434486
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.3477680482
Short name T369
Test name
Test status
Simulation time 137328759 ps
CPU time 1.11 seconds
Started Jan 21 03:32:43 PM PST 24
Finished Jan 21 03:32:45 PM PST 24
Peak memory 199624 kb
Host smart-ca1a1dd6-b378-4bbd-9dc4-38451be9487d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477680482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.3477680482
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.4054597090
Short name T598
Test name
Test status
Simulation time 61773078 ps
CPU time 0.75 seconds
Started Jan 21 03:32:49 PM PST 24
Finished Jan 21 03:32:54 PM PST 24
Peak memory 199584 kb
Host smart-a2d2ce54-fe7d-44a8-90bc-b4d49e57635c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054597090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.4054597090
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.1974170990
Short name T26
Test name
Test status
Simulation time 1233490614 ps
CPU time 5.53 seconds
Started Jan 21 03:32:57 PM PST 24
Finished Jan 21 03:33:14 PM PST 24
Peak memory 217048 kb
Host smart-bd3a497f-b84c-43d2-a743-a7725bbb5695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974170990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.1974170990
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.1000701700
Short name T74
Test name
Test status
Simulation time 244819135 ps
CPU time 1.05 seconds
Started Jan 21 03:32:46 PM PST 24
Finished Jan 21 03:32:51 PM PST 24
Peak memory 216900 kb
Host smart-4b187d5b-e42f-4862-af25-6fba70600eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000701700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.1000701700
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.11070710
Short name T14
Test name
Test status
Simulation time 158949712 ps
CPU time 0.85 seconds
Started Jan 21 03:32:41 PM PST 24
Finished Jan 21 03:32:43 PM PST 24
Peak memory 199396 kb
Host smart-af679135-7f3e-4331-95e3-427b90d84eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11070710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.11070710
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.3154306196
Short name T101
Test name
Test status
Simulation time 1682753739 ps
CPU time 6.11 seconds
Started Jan 21 03:32:49 PM PST 24
Finished Jan 21 03:32:58 PM PST 24
Peak memory 199536 kb
Host smart-a6fd7a4c-5bfc-4320-b368-a6148218bfe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154306196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.3154306196
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.518586191
Short name T451
Test name
Test status
Simulation time 110363191 ps
CPU time 1.04 seconds
Started Jan 21 03:32:57 PM PST 24
Finished Jan 21 03:33:10 PM PST 24
Peak memory 199488 kb
Host smart-dff07c1e-727f-4453-a52d-6c39956a2b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518586191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.518586191
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.3861958786
Short name T510
Test name
Test status
Simulation time 200581391 ps
CPU time 1.37 seconds
Started Jan 21 03:32:36 PM PST 24
Finished Jan 21 03:32:38 PM PST 24
Peak memory 199788 kb
Host smart-9730af3f-c32d-48fc-a7c3-e72e6ef15d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861958786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.3861958786
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.4233776007
Short name T395
Test name
Test status
Simulation time 9595898644 ps
CPU time 34.5 seconds
Started Jan 21 03:32:52 PM PST 24
Finished Jan 21 03:33:36 PM PST 24
Peak memory 199848 kb
Host smart-f4ec91bd-b5dc-423b-bdba-a7de2738a86c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233776007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.4233776007
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.3459785856
Short name T264
Test name
Test status
Simulation time 261774843 ps
CPU time 1.81 seconds
Started Jan 21 03:32:56 PM PST 24
Finished Jan 21 03:33:11 PM PST 24
Peak memory 199432 kb
Host smart-59ec5b63-9319-4df9-b28d-64c742bfb009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459785856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.3459785856
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.959477526
Short name T399
Test name
Test status
Simulation time 119647755 ps
CPU time 1.08 seconds
Started Jan 21 03:32:57 PM PST 24
Finished Jan 21 03:33:10 PM PST 24
Peak memory 199536 kb
Host smart-e67a88a6-e199-42a0-9fca-89eac21eee6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959477526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.959477526
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.2367502119
Short name T428
Test name
Test status
Simulation time 77290601 ps
CPU time 0.86 seconds
Started Jan 21 03:32:48 PM PST 24
Finished Jan 21 03:32:52 PM PST 24
Peak memory 199540 kb
Host smart-4f97ddca-0c18-44da-bf1b-421e3aa8d6a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367502119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.2367502119
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.3359867255
Short name T464
Test name
Test status
Simulation time 1890958898 ps
CPU time 7.01 seconds
Started Jan 21 03:32:54 PM PST 24
Finished Jan 21 03:33:15 PM PST 24
Peak memory 221212 kb
Host smart-9dae8561-aecd-4a0d-8019-03f6f6f90b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359867255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.3359867255
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.3281375242
Short name T425
Test name
Test status
Simulation time 244073441 ps
CPU time 1.07 seconds
Started Jan 21 03:32:46 PM PST 24
Finished Jan 21 03:32:52 PM PST 24
Peak memory 216736 kb
Host smart-3c8d3114-5da6-4e0c-8ab2-a015a47f4d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281375242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.3281375242
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.1483450913
Short name T452
Test name
Test status
Simulation time 76699261 ps
CPU time 0.76 seconds
Started Jan 21 03:32:57 PM PST 24
Finished Jan 21 03:33:10 PM PST 24
Peak memory 199372 kb
Host smart-fc761855-7581-440d-9dbb-b844df8c8fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483450913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.1483450913
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.322652254
Short name T429
Test name
Test status
Simulation time 1166045305 ps
CPU time 4.86 seconds
Started Jan 21 03:32:48 PM PST 24
Finished Jan 21 03:32:56 PM PST 24
Peak memory 200004 kb
Host smart-9e296960-7e80-4cf2-a5bc-e18d6f0173f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322652254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.322652254
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.1331377690
Short name T81
Test name
Test status
Simulation time 99986641 ps
CPU time 1.04 seconds
Started Jan 21 03:32:49 PM PST 24
Finished Jan 21 03:32:53 PM PST 24
Peak memory 199596 kb
Host smart-b53d1584-045a-42df-9e58-cdaad2807bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331377690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.1331377690
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.2367314546
Short name T384
Test name
Test status
Simulation time 197156963 ps
CPU time 1.41 seconds
Started Jan 21 03:32:52 PM PST 24
Finished Jan 21 03:33:02 PM PST 24
Peak memory 199804 kb
Host smart-0cd31690-1dc5-419e-9b79-14887b5d91f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367314546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.2367314546
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.1909390062
Short name T527
Test name
Test status
Simulation time 5798737962 ps
CPU time 22.91 seconds
Started Jan 21 03:32:56 PM PST 24
Finished Jan 21 03:33:32 PM PST 24
Peak memory 199784 kb
Host smart-de78d712-f12e-4b5c-a6ad-052b05fdc1aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909390062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.1909390062
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.4136923049
Short name T160
Test name
Test status
Simulation time 126531533 ps
CPU time 1.53 seconds
Started Jan 21 03:32:45 PM PST 24
Finished Jan 21 03:32:49 PM PST 24
Peak memory 199672 kb
Host smart-c6c5a2a7-ae87-452c-abf3-63814c969e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136923049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.4136923049
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.270248427
Short name T336
Test name
Test status
Simulation time 150706520 ps
CPU time 1.19 seconds
Started Jan 21 03:32:58 PM PST 24
Finished Jan 21 03:33:11 PM PST 24
Peak memory 199600 kb
Host smart-75082af8-c105-479a-a589-1429392609fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270248427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.270248427
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.2964801359
Short name T296
Test name
Test status
Simulation time 83111647 ps
CPU time 0.83 seconds
Started Jan 21 03:32:46 PM PST 24
Finished Jan 21 03:32:52 PM PST 24
Peak memory 199568 kb
Host smart-c92448ba-19d8-4f16-97bb-4f13e8a29b6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964801359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.2964801359
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.3742486886
Short name T3
Test name
Test status
Simulation time 1236490014 ps
CPU time 5.93 seconds
Started Jan 21 03:32:53 PM PST 24
Finished Jan 21 03:33:08 PM PST 24
Peak memory 217028 kb
Host smart-1f63999d-08a8-4342-b8ff-03aa894a9398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742486886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.3742486886
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.4160512397
Short name T570
Test name
Test status
Simulation time 245245309 ps
CPU time 1.03 seconds
Started Jan 21 03:32:54 PM PST 24
Finished Jan 21 03:33:07 PM PST 24
Peak memory 216892 kb
Host smart-8261b695-2600-4efb-bbae-a4a7598ac24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160512397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.4160512397
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.1152943397
Short name T318
Test name
Test status
Simulation time 129778005 ps
CPU time 0.81 seconds
Started Jan 21 03:32:50 PM PST 24
Finished Jan 21 03:32:54 PM PST 24
Peak memory 199344 kb
Host smart-574480f9-cf82-4bfe-a682-dec3811aeb85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152943397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.1152943397
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.2949177791
Short name T7
Test name
Test status
Simulation time 1490825928 ps
CPU time 6.23 seconds
Started Jan 21 03:32:49 PM PST 24
Finished Jan 21 03:32:58 PM PST 24
Peak memory 199732 kb
Host smart-ddcd8d6c-721f-4f65-adaa-f6bb57989aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949177791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.2949177791
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.2736133520
Short name T445
Test name
Test status
Simulation time 172190212 ps
CPU time 1.14 seconds
Started Jan 21 03:32:48 PM PST 24
Finished Jan 21 03:32:52 PM PST 24
Peak memory 199544 kb
Host smart-896d6b7b-86d7-4981-9a96-d3697e50938e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736133520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.2736133520
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.3316189168
Short name T153
Test name
Test status
Simulation time 204531010 ps
CPU time 1.34 seconds
Started Jan 21 03:32:52 PM PST 24
Finished Jan 21 03:33:03 PM PST 24
Peak memory 199788 kb
Host smart-88a14fbf-3703-4ef6-a397-b729cfd57e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316189168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.3316189168
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.586196564
Short name T514
Test name
Test status
Simulation time 6928326963 ps
CPU time 25.67 seconds
Started Jan 21 03:32:46 PM PST 24
Finished Jan 21 03:33:14 PM PST 24
Peak memory 199844 kb
Host smart-395206fc-31a1-43b7-9307-ef019c84a81f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586196564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.586196564
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.2571625167
Short name T252
Test name
Test status
Simulation time 358865293 ps
CPU time 2.22 seconds
Started Jan 21 03:32:58 PM PST 24
Finished Jan 21 03:33:12 PM PST 24
Peak memory 199688 kb
Host smart-9cc8d199-0d31-4276-aaee-386d56ad599c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571625167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.2571625167
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.3031377933
Short name T404
Test name
Test status
Simulation time 158947417 ps
CPU time 1.19 seconds
Started Jan 21 03:32:53 PM PST 24
Finished Jan 21 03:33:03 PM PST 24
Peak memory 199780 kb
Host smart-03a875bb-3317-4c8e-93ea-9134dae0095c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031377933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.3031377933
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.895463022
Short name T39
Test name
Test status
Simulation time 81369148 ps
CPU time 0.82 seconds
Started Jan 21 03:30:30 PM PST 24
Finished Jan 21 03:30:34 PM PST 24
Peak memory 199544 kb
Host smart-3520ac4f-9267-428f-b1b3-1eac4972d93c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895463022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.895463022
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.1189283613
Short name T9
Test name
Test status
Simulation time 2335299375 ps
CPU time 8.06 seconds
Started Jan 21 03:30:30 PM PST 24
Finished Jan 21 03:30:42 PM PST 24
Peak memory 216812 kb
Host smart-a3c3ce88-de42-4b36-8bec-0cc21e309e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189283613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.1189283613
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.1565029646
Short name T555
Test name
Test status
Simulation time 244618725 ps
CPU time 1.19 seconds
Started Jan 21 03:30:32 PM PST 24
Finished Jan 21 03:30:35 PM PST 24
Peak memory 216780 kb
Host smart-b87f51bd-26fe-4e6c-8995-3e05824bb75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565029646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.1565029646
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.2924193006
Short name T367
Test name
Test status
Simulation time 80450677 ps
CPU time 0.71 seconds
Started Jan 21 03:30:20 PM PST 24
Finished Jan 21 03:30:22 PM PST 24
Peak memory 199380 kb
Host smart-bcf0528a-321d-4905-b281-78be3297ecfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924193006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.2924193006
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.1865093288
Short name T586
Test name
Test status
Simulation time 1259007543 ps
CPU time 5.69 seconds
Started Jan 21 03:30:26 PM PST 24
Finished Jan 21 03:30:36 PM PST 24
Peak memory 199776 kb
Host smart-7e07c0b0-ed7c-46d8-8a0c-f3b47fc49d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865093288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.1865093288
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.3304627118
Short name T69
Test name
Test status
Simulation time 8288420761 ps
CPU time 15.73 seconds
Started Jan 21 04:55:44 PM PST 24
Finished Jan 21 04:56:01 PM PST 24
Peak memory 216716 kb
Host smart-34ec673c-7b97-4c49-b865-352ce101e96d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304627118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.3304627118
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.361864021
Short name T588
Test name
Test status
Simulation time 161236997 ps
CPU time 1.11 seconds
Started Jan 21 03:30:29 PM PST 24
Finished Jan 21 03:30:34 PM PST 24
Peak memory 199604 kb
Host smart-a241c91a-826d-48c0-9782-6311c6c1cd18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361864021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.361864021
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.4069854328
Short name T597
Test name
Test status
Simulation time 129900997 ps
CPU time 1.11 seconds
Started Jan 21 03:30:22 PM PST 24
Finished Jan 21 03:30:24 PM PST 24
Peak memory 199776 kb
Host smart-367777c9-1545-4b94-9152-b445f12d7387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069854328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.4069854328
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.2814264044
Short name T584
Test name
Test status
Simulation time 3110178796 ps
CPU time 11.88 seconds
Started Jan 21 03:30:30 PM PST 24
Finished Jan 21 03:30:46 PM PST 24
Peak memory 199800 kb
Host smart-b7b9a9f5-dc70-404a-9b4b-3f5eca7ee043
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814264044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.2814264044
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.2933800923
Short name T506
Test name
Test status
Simulation time 335780999 ps
CPU time 2.07 seconds
Started Jan 21 03:30:22 PM PST 24
Finished Jan 21 03:30:26 PM PST 24
Peak memory 199644 kb
Host smart-515e40d5-1f79-4149-a765-25a5ea90ff4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933800923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.2933800923
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.2462310757
Short name T375
Test name
Test status
Simulation time 99521868 ps
CPU time 0.99 seconds
Started Jan 21 03:30:25 PM PST 24
Finished Jan 21 03:30:32 PM PST 24
Peak memory 199588 kb
Host smart-795a4537-8bc2-4eab-bc86-82694e9817c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462310757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.2462310757
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.1084397834
Short name T254
Test name
Test status
Simulation time 66738719 ps
CPU time 0.74 seconds
Started Jan 21 03:32:54 PM PST 24
Finished Jan 21 03:33:07 PM PST 24
Peak memory 199548 kb
Host smart-d597eb70-da75-4ea1-bff3-3f205ebc5d79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084397834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.1084397834
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.1811000094
Short name T406
Test name
Test status
Simulation time 1235085036 ps
CPU time 5.36 seconds
Started Jan 21 03:32:58 PM PST 24
Finished Jan 21 03:33:14 PM PST 24
Peak memory 216528 kb
Host smart-07ac9203-e25d-4777-99b8-cf4514cad901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811000094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.1811000094
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.622905635
Short name T545
Test name
Test status
Simulation time 243406081 ps
CPU time 1.03 seconds
Started Jan 21 03:32:46 PM PST 24
Finished Jan 21 03:32:52 PM PST 24
Peak memory 216932 kb
Host smart-6684ffde-660f-4203-88a9-8147f96aa18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622905635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.622905635
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.80490841
Short name T487
Test name
Test status
Simulation time 156163490 ps
CPU time 0.8 seconds
Started Jan 21 03:33:25 PM PST 24
Finished Jan 21 03:33:30 PM PST 24
Peak memory 199348 kb
Host smart-fdec4623-4b62-4970-966f-73d8ecea522c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80490841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.80490841
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.4035347450
Short name T444
Test name
Test status
Simulation time 892820153 ps
CPU time 4.54 seconds
Started Jan 21 03:32:58 PM PST 24
Finished Jan 21 03:33:14 PM PST 24
Peak memory 199728 kb
Host smart-567a3c55-585d-421c-beb2-a7a6c4df46ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035347450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.4035347450
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.178726387
Short name T268
Test name
Test status
Simulation time 108246636 ps
CPU time 1.01 seconds
Started Jan 21 03:32:45 PM PST 24
Finished Jan 21 03:32:47 PM PST 24
Peak memory 199620 kb
Host smart-28c147f9-ba6d-4746-86af-b70ed1542a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178726387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.178726387
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.1398227426
Short name T519
Test name
Test status
Simulation time 205833171 ps
CPU time 1.42 seconds
Started Jan 21 03:32:56 PM PST 24
Finished Jan 21 03:33:10 PM PST 24
Peak memory 199708 kb
Host smart-1b12908e-b935-43cd-90c6-85aaa3d3dfa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398227426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.1398227426
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.2393180491
Short name T515
Test name
Test status
Simulation time 3266178311 ps
CPU time 12.79 seconds
Started Jan 21 03:32:45 PM PST 24
Finished Jan 21 03:33:00 PM PST 24
Peak memory 199892 kb
Host smart-0a78a250-2ccc-4c27-811a-5f40233c0a6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393180491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.2393180491
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.102686219
Short name T75
Test name
Test status
Simulation time 370405210 ps
CPU time 2.53 seconds
Started Jan 21 03:32:53 PM PST 24
Finished Jan 21 03:33:07 PM PST 24
Peak memory 199636 kb
Host smart-aed2403a-cf89-42ff-8853-398f01f859b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102686219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.102686219
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.983598927
Short name T136
Test name
Test status
Simulation time 209360048 ps
CPU time 1.26 seconds
Started Jan 21 03:32:52 PM PST 24
Finished Jan 21 03:33:03 PM PST 24
Peak memory 199616 kb
Host smart-34610985-faf2-450b-ace3-025dde9fd79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983598927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.983598927
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.1121019659
Short name T573
Test name
Test status
Simulation time 69123933 ps
CPU time 0.84 seconds
Started Jan 21 03:32:51 PM PST 24
Finished Jan 21 03:32:55 PM PST 24
Peak memory 199544 kb
Host smart-cc42afa3-aefb-49bf-a399-b896c7eb3ba0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121019659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.1121019659
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.2807736981
Short name T30
Test name
Test status
Simulation time 1879702859 ps
CPU time 7.6 seconds
Started Jan 21 03:32:57 PM PST 24
Finished Jan 21 03:33:17 PM PST 24
Peak memory 217592 kb
Host smart-68fe03fe-9386-4821-a919-7e493e4071de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807736981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.2807736981
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.1833857059
Short name T380
Test name
Test status
Simulation time 245948722 ps
CPU time 1.11 seconds
Started Jan 21 03:32:52 PM PST 24
Finished Jan 21 03:33:03 PM PST 24
Peak memory 216900 kb
Host smart-d05813e4-1682-452a-8e87-3be75cb6b705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833857059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.1833857059
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.4159603184
Short name T18
Test name
Test status
Simulation time 160703504 ps
CPU time 0.85 seconds
Started Jan 21 03:32:58 PM PST 24
Finished Jan 21 03:33:10 PM PST 24
Peak memory 199384 kb
Host smart-d36fba5a-abd6-4208-bbb2-4255a3cb17cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159603184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.4159603184
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.813454270
Short name T269
Test name
Test status
Simulation time 955332724 ps
CPU time 4.67 seconds
Started Jan 21 03:33:11 PM PST 24
Finished Jan 21 03:33:25 PM PST 24
Peak memory 199416 kb
Host smart-ebb15b32-22b1-4330-8675-ae361c902544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813454270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.813454270
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.3659767777
Short name T316
Test name
Test status
Simulation time 143949250 ps
CPU time 1.13 seconds
Started Jan 21 03:32:58 PM PST 24
Finished Jan 21 03:33:11 PM PST 24
Peak memory 199652 kb
Host smart-90c2b24b-0a68-4cc9-9778-6ddfe02e25d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659767777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.3659767777
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.952058326
Short name T466
Test name
Test status
Simulation time 114365810 ps
CPU time 1.14 seconds
Started Jan 21 03:32:52 PM PST 24
Finished Jan 21 03:33:03 PM PST 24
Peak memory 199768 kb
Host smart-b36881c4-d845-4cc8-8721-b280bbd0c61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952058326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.952058326
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.2417956944
Short name T481
Test name
Test status
Simulation time 9657323287 ps
CPU time 36 seconds
Started Jan 21 03:32:56 PM PST 24
Finished Jan 21 03:33:45 PM PST 24
Peak memory 199796 kb
Host smart-8a94d9d0-c990-46ec-97d3-9a8a2572aa01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417956944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.2417956944
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.4190739000
Short name T158
Test name
Test status
Simulation time 358832225 ps
CPU time 2.49 seconds
Started Jan 21 03:33:00 PM PST 24
Finished Jan 21 03:33:12 PM PST 24
Peak memory 199652 kb
Host smart-f775dd10-86de-428f-939f-2f517e5eab29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190739000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.4190739000
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.2812816875
Short name T364
Test name
Test status
Simulation time 131573020 ps
CPU time 0.9 seconds
Started Jan 21 03:33:02 PM PST 24
Finished Jan 21 03:33:17 PM PST 24
Peak memory 199612 kb
Host smart-60bc5c66-37ac-4f1f-9b47-b061b79e5593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812816875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.2812816875
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.3556717409
Short name T482
Test name
Test status
Simulation time 72206827 ps
CPU time 0.73 seconds
Started Jan 21 03:33:12 PM PST 24
Finished Jan 21 03:33:22 PM PST 24
Peak memory 199480 kb
Host smart-4bb3e1ba-3804-42c7-8211-265d4febec12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556717409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.3556717409
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.3995050881
Short name T392
Test name
Test status
Simulation time 1233120301 ps
CPU time 5.46 seconds
Started Jan 21 03:32:56 PM PST 24
Finished Jan 21 03:33:14 PM PST 24
Peak memory 217552 kb
Host smart-fa1cf3a1-ad28-4114-8c44-9aaa2cd236a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995050881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.3995050881
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.2816226681
Short name T455
Test name
Test status
Simulation time 245912473 ps
CPU time 1.05 seconds
Started Jan 21 03:32:58 PM PST 24
Finished Jan 21 03:33:11 PM PST 24
Peak memory 216916 kb
Host smart-8afdcd77-d1bb-4fd6-826f-0dcfb3b69c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816226681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.2816226681
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.1228402259
Short name T557
Test name
Test status
Simulation time 163241000 ps
CPU time 0.9 seconds
Started Jan 21 03:32:59 PM PST 24
Finished Jan 21 03:33:10 PM PST 24
Peak memory 199368 kb
Host smart-a7749f4f-75cd-465c-97a5-a7d949f7aba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228402259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.1228402259
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.1483130151
Short name T379
Test name
Test status
Simulation time 1903888411 ps
CPU time 6.85 seconds
Started Jan 21 03:33:11 PM PST 24
Finished Jan 21 03:33:27 PM PST 24
Peak memory 199700 kb
Host smart-48420ab9-6a42-4534-a909-9596041a48db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483130151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.1483130151
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.909440886
Short name T299
Test name
Test status
Simulation time 95867765 ps
CPU time 0.95 seconds
Started Jan 21 03:32:53 PM PST 24
Finished Jan 21 03:33:05 PM PST 24
Peak memory 199604 kb
Host smart-4227d858-7844-4afb-9096-56c9bcb07167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909440886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.909440886
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.3459088185
Short name T327
Test name
Test status
Simulation time 125574375 ps
CPU time 1.19 seconds
Started Jan 21 03:32:59 PM PST 24
Finished Jan 21 03:33:11 PM PST 24
Peak memory 199796 kb
Host smart-6ddb053e-3541-4e7b-9113-9a1850b74438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459088185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.3459088185
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.2093935183
Short name T383
Test name
Test status
Simulation time 2956717418 ps
CPU time 13.96 seconds
Started Jan 21 03:32:54 PM PST 24
Finished Jan 21 03:33:20 PM PST 24
Peak memory 199844 kb
Host smart-5ce5830a-4e0f-4212-bcd8-2ac385a2e00d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093935183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.2093935183
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.2766912934
Short name T520
Test name
Test status
Simulation time 332167179 ps
CPU time 2.12 seconds
Started Jan 21 03:32:55 PM PST 24
Finished Jan 21 03:33:11 PM PST 24
Peak memory 199668 kb
Host smart-fae0eede-3228-4458-8902-95a280ae5c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766912934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.2766912934
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.4083922007
Short name T484
Test name
Test status
Simulation time 198534271 ps
CPU time 1.21 seconds
Started Jan 21 03:33:03 PM PST 24
Finished Jan 21 03:33:18 PM PST 24
Peak memory 199612 kb
Host smart-aaad85e2-be8d-40e2-9e83-af5ad0f6043c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083922007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.4083922007
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.41244193
Short name T154
Test name
Test status
Simulation time 86619698 ps
CPU time 0.79 seconds
Started Jan 21 03:33:13 PM PST 24
Finished Jan 21 03:33:22 PM PST 24
Peak memory 199472 kb
Host smart-53ed005c-ad57-4187-bc22-a42cea1e0b64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41244193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.41244193
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.1368435325
Short name T463
Test name
Test status
Simulation time 1898662759 ps
CPU time 8.05 seconds
Started Jan 21 03:33:00 PM PST 24
Finished Jan 21 03:33:18 PM PST 24
Peak memory 217112 kb
Host smart-bff53cc8-7c6c-4887-84e7-0f6af2accbba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368435325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.1368435325
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.1826335811
Short name T400
Test name
Test status
Simulation time 246653260 ps
CPU time 1.08 seconds
Started Jan 21 03:33:02 PM PST 24
Finished Jan 21 03:33:16 PM PST 24
Peak memory 216896 kb
Host smart-00006fa4-3225-4597-a7b1-5581d4233b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826335811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.1826335811
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.2691451319
Short name T546
Test name
Test status
Simulation time 193487853 ps
CPU time 0.88 seconds
Started Jan 21 03:32:58 PM PST 24
Finished Jan 21 03:33:10 PM PST 24
Peak memory 199336 kb
Host smart-e14b9cc8-98ec-4946-bc24-562c1b022165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691451319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.2691451319
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.545444285
Short name T505
Test name
Test status
Simulation time 2119463202 ps
CPU time 7.95 seconds
Started Jan 21 03:33:03 PM PST 24
Finished Jan 21 03:33:25 PM PST 24
Peak memory 199744 kb
Host smart-be4a8c0f-c0f6-4562-94e7-8262137befeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545444285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.545444285
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.2172610064
Short name T420
Test name
Test status
Simulation time 189985007 ps
CPU time 1.22 seconds
Started Jan 21 03:33:03 PM PST 24
Finished Jan 21 03:33:18 PM PST 24
Peak memory 199628 kb
Host smart-c3af0207-e293-4e09-950d-7e03f8ff4ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172610064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.2172610064
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.1979933441
Short name T498
Test name
Test status
Simulation time 118082266 ps
CPU time 1.16 seconds
Started Jan 21 03:33:03 PM PST 24
Finished Jan 21 03:33:18 PM PST 24
Peak memory 199812 kb
Host smart-a337b9bc-e1dd-4f29-802e-a6aba9a08492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979933441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.1979933441
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.2840457198
Short name T104
Test name
Test status
Simulation time 4702408763 ps
CPU time 19.26 seconds
Started Jan 21 03:33:02 PM PST 24
Finished Jan 21 03:33:35 PM PST 24
Peak memory 199872 kb
Host smart-54896857-2d25-4d19-853a-5ce3481c4b4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840457198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.2840457198
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.2717927622
Short name T423
Test name
Test status
Simulation time 123033614 ps
CPU time 1.44 seconds
Started Jan 21 03:33:03 PM PST 24
Finished Jan 21 03:33:18 PM PST 24
Peak memory 199264 kb
Host smart-718ec8be-7e8a-42b0-aaa7-eefa99cc5a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717927622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.2717927622
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.114237951
Short name T529
Test name
Test status
Simulation time 141150456 ps
CPU time 1.09 seconds
Started Jan 21 03:33:03 PM PST 24
Finished Jan 21 03:33:18 PM PST 24
Peak memory 199540 kb
Host smart-288efc55-a6b7-4a15-8d2b-cb8ceee1a3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114237951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.114237951
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.2383539427
Short name T389
Test name
Test status
Simulation time 58706261 ps
CPU time 0.73 seconds
Started Jan 21 03:33:13 PM PST 24
Finished Jan 21 03:33:22 PM PST 24
Peak memory 199560 kb
Host smart-858cdccd-656d-4704-ae9a-71872cc79f2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383539427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.2383539427
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.1754770836
Short name T348
Test name
Test status
Simulation time 1234790212 ps
CPU time 5.96 seconds
Started Jan 21 03:33:06 PM PST 24
Finished Jan 21 03:33:24 PM PST 24
Peak memory 217072 kb
Host smart-1d7f58f5-ef05-4798-905f-099ef6dc14f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754770836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.1754770836
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.1780983569
Short name T454
Test name
Test status
Simulation time 244618193 ps
CPU time 1.04 seconds
Started Jan 21 03:32:59 PM PST 24
Finished Jan 21 03:33:11 PM PST 24
Peak memory 216780 kb
Host smart-fbae0f08-5b29-4571-97be-fc5a9b41ee5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780983569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.1780983569
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.4219771639
Short name T19
Test name
Test status
Simulation time 151406786 ps
CPU time 0.79 seconds
Started Jan 21 03:33:02 PM PST 24
Finished Jan 21 03:33:17 PM PST 24
Peak memory 199392 kb
Host smart-73504107-8751-40f3-b9aa-e98d7b5977f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219771639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.4219771639
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.3319586665
Short name T124
Test name
Test status
Simulation time 1422034519 ps
CPU time 5.65 seconds
Started Jan 21 03:33:01 PM PST 24
Finished Jan 21 03:33:17 PM PST 24
Peak memory 199760 kb
Host smart-4619ff47-b693-4c5d-9f15-59d855ad5985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319586665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.3319586665
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.68546336
Short name T22
Test name
Test status
Simulation time 109816081 ps
CPU time 0.97 seconds
Started Jan 21 03:33:12 PM PST 24
Finished Jan 21 03:33:22 PM PST 24
Peak memory 199508 kb
Host smart-86935b28-0d4c-4f25-8c87-6b525cf1248e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68546336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.68546336
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.2208489193
Short name T606
Test name
Test status
Simulation time 201692339 ps
CPU time 1.36 seconds
Started Jan 21 03:33:03 PM PST 24
Finished Jan 21 03:33:18 PM PST 24
Peak memory 199376 kb
Host smart-57425905-5377-4d10-ba74-362de76579a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208489193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.2208489193
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.3342557212
Short name T72
Test name
Test status
Simulation time 3133635133 ps
CPU time 12.83 seconds
Started Jan 21 03:33:12 PM PST 24
Finished Jan 21 03:33:34 PM PST 24
Peak memory 199792 kb
Host smart-17229a19-51dd-435a-aa21-3635e7d06dbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342557212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.3342557212
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.3831632956
Short name T560
Test name
Test status
Simulation time 326574637 ps
CPU time 1.97 seconds
Started Jan 21 03:33:11 PM PST 24
Finished Jan 21 03:33:22 PM PST 24
Peak memory 199364 kb
Host smart-6582f83a-e879-4133-a72d-92827221aa1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831632956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.3831632956
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.1280402691
Short name T579
Test name
Test status
Simulation time 66277363 ps
CPU time 0.79 seconds
Started Jan 21 03:33:13 PM PST 24
Finished Jan 21 03:33:22 PM PST 24
Peak memory 199500 kb
Host smart-51f36a7e-3bb2-4c11-a9cd-ae8d9aa3f796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280402691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.1280402691
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.2356406668
Short name T83
Test name
Test status
Simulation time 57659685 ps
CPU time 0.68 seconds
Started Jan 21 03:33:17 PM PST 24
Finished Jan 21 03:33:23 PM PST 24
Peak memory 199572 kb
Host smart-712a5559-28e4-4520-bdff-7e3fc672c590
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356406668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.2356406668
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.1095030310
Short name T347
Test name
Test status
Simulation time 2183134841 ps
CPU time 8.5 seconds
Started Jan 21 03:33:17 PM PST 24
Finished Jan 21 03:33:31 PM PST 24
Peak memory 221720 kb
Host smart-e5963550-3166-4efa-b7d1-ee3b2f29481b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095030310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.1095030310
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.1149558845
Short name T381
Test name
Test status
Simulation time 244991715 ps
CPU time 1.03 seconds
Started Jan 21 03:33:17 PM PST 24
Finished Jan 21 03:33:24 PM PST 24
Peak memory 216924 kb
Host smart-cb45fd05-22d1-4f2e-936a-b62405ff5044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149558845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.1149558845
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.3037476815
Short name T155
Test name
Test status
Simulation time 89786872 ps
CPU time 0.75 seconds
Started Jan 21 03:33:17 PM PST 24
Finished Jan 21 03:33:23 PM PST 24
Peak memory 199356 kb
Host smart-485611dd-e55c-4d43-8544-5b4309132fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037476815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.3037476815
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.3216059537
Short name T518
Test name
Test status
Simulation time 761698619 ps
CPU time 3.8 seconds
Started Jan 21 03:33:17 PM PST 24
Finished Jan 21 03:33:26 PM PST 24
Peak memory 199796 kb
Host smart-193db505-27f1-464a-a81f-859459c771f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216059537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.3216059537
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.2134481467
Short name T602
Test name
Test status
Simulation time 168397756 ps
CPU time 1.11 seconds
Started Jan 21 03:33:13 PM PST 24
Finished Jan 21 03:33:22 PM PST 24
Peak memory 199612 kb
Host smart-e15e8bee-0d30-450b-b667-5ed2518a36b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134481467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.2134481467
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.3442658433
Short name T462
Test name
Test status
Simulation time 197790564 ps
CPU time 1.33 seconds
Started Jan 21 03:33:19 PM PST 24
Finished Jan 21 03:33:24 PM PST 24
Peak memory 199784 kb
Host smart-a73e54fa-8f80-4ed8-81bd-d81d92eb6849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442658433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.3442658433
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.3470309191
Short name T427
Test name
Test status
Simulation time 13879634040 ps
CPU time 52.19 seconds
Started Jan 21 03:33:10 PM PST 24
Finished Jan 21 03:34:12 PM PST 24
Peak memory 199800 kb
Host smart-7b7dfb0c-e84b-441f-9183-93bec09afd0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470309191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.3470309191
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.2088454840
Short name T152
Test name
Test status
Simulation time 124540785 ps
CPU time 1.45 seconds
Started Jan 21 03:33:12 PM PST 24
Finished Jan 21 03:33:23 PM PST 24
Peak memory 199672 kb
Host smart-53b07864-cd13-43aa-9878-7094513cbca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088454840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.2088454840
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.3412300954
Short name T313
Test name
Test status
Simulation time 230606680 ps
CPU time 1.48 seconds
Started Jan 21 03:33:12 PM PST 24
Finished Jan 21 03:33:23 PM PST 24
Peak memory 199516 kb
Host smart-877172f0-2669-45d9-bf5e-34ca3741326b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412300954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.3412300954
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.3865996111
Short name T371
Test name
Test status
Simulation time 67744541 ps
CPU time 0.79 seconds
Started Jan 21 03:33:22 PM PST 24
Finished Jan 21 03:33:27 PM PST 24
Peak memory 199544 kb
Host smart-9636a076-711b-4b1c-8b84-b6d00fc7fcd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865996111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.3865996111
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.1976804019
Short name T524
Test name
Test status
Simulation time 1885541847 ps
CPU time 8.19 seconds
Started Jan 21 03:33:26 PM PST 24
Finished Jan 21 03:33:37 PM PST 24
Peak memory 216512 kb
Host smart-b678336d-3adb-4cbf-8f22-9caad514aac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976804019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.1976804019
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.1196848236
Short name T157
Test name
Test status
Simulation time 244030921 ps
CPU time 1.1 seconds
Started Jan 21 03:33:25 PM PST 24
Finished Jan 21 03:33:30 PM PST 24
Peak memory 216860 kb
Host smart-aa6aea12-41b6-4ff6-852d-4420cb289c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196848236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.1196848236
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.275511608
Short name T292
Test name
Test status
Simulation time 167993420 ps
CPU time 0.9 seconds
Started Jan 21 03:33:10 PM PST 24
Finished Jan 21 03:33:21 PM PST 24
Peak memory 199332 kb
Host smart-8315a5be-94ef-477a-983f-d3f8065bfd83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275511608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.275511608
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.2015912815
Short name T391
Test name
Test status
Simulation time 1930385873 ps
CPU time 6.63 seconds
Started Jan 21 03:33:14 PM PST 24
Finished Jan 21 03:33:28 PM PST 24
Peak memory 199716 kb
Host smart-1a71383c-987d-4b55-9aed-c5ac2930bf7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015912815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.2015912815
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.234060128
Short name T516
Test name
Test status
Simulation time 154197390 ps
CPU time 1.2 seconds
Started Jan 21 03:33:27 PM PST 24
Finished Jan 21 03:33:30 PM PST 24
Peak memory 199596 kb
Host smart-8d04cc1c-6e76-4988-96c1-81c1b4435e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234060128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.234060128
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.4137504585
Short name T544
Test name
Test status
Simulation time 238913825 ps
CPU time 1.45 seconds
Started Jan 21 03:33:13 PM PST 24
Finished Jan 21 03:33:23 PM PST 24
Peak memory 199740 kb
Host smart-db73a6e7-7c8d-4909-b70f-a9823c591e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137504585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.4137504585
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.1837594591
Short name T265
Test name
Test status
Simulation time 3797347519 ps
CPU time 14.96 seconds
Started Jan 21 03:33:29 PM PST 24
Finished Jan 21 03:33:47 PM PST 24
Peak memory 199780 kb
Host smart-24b472ad-ff3b-4095-96bc-76abdb94e3bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837594591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.1837594591
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.3594931276
Short name T433
Test name
Test status
Simulation time 317407256 ps
CPU time 2.05 seconds
Started Jan 21 03:33:21 PM PST 24
Finished Jan 21 03:33:28 PM PST 24
Peak memory 199696 kb
Host smart-ab67ace4-b971-4915-a1fa-be230110eb01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594931276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.3594931276
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.576230327
Short name T411
Test name
Test status
Simulation time 117414905 ps
CPU time 0.91 seconds
Started Jan 21 03:33:23 PM PST 24
Finished Jan 21 03:33:28 PM PST 24
Peak memory 199568 kb
Host smart-f2a5fbd8-98a9-4c68-9153-c2174f10183b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576230327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.576230327
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.2150877259
Short name T470
Test name
Test status
Simulation time 82823289 ps
CPU time 0.81 seconds
Started Jan 21 03:33:20 PM PST 24
Finished Jan 21 03:33:25 PM PST 24
Peak memory 199576 kb
Host smart-cb514a0f-34e6-4512-8eda-8b1433e64877
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150877259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.2150877259
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.1776938542
Short name T343
Test name
Test status
Simulation time 1234711866 ps
CPU time 5.76 seconds
Started Jan 21 03:33:20 PM PST 24
Finished Jan 21 03:33:32 PM PST 24
Peak memory 221088 kb
Host smart-3cf78d42-9056-4ec0-8e02-79518af4e404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776938542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.1776938542
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.1883732809
Short name T41
Test name
Test status
Simulation time 244319750 ps
CPU time 1.06 seconds
Started Jan 21 03:33:29 PM PST 24
Finished Jan 21 03:33:32 PM PST 24
Peak memory 216908 kb
Host smart-d9078e66-3fbb-4667-a5d6-bf732578cd18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883732809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.1883732809
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.3261955799
Short name T480
Test name
Test status
Simulation time 176659963 ps
CPU time 1 seconds
Started Jan 21 03:33:30 PM PST 24
Finished Jan 21 03:33:33 PM PST 24
Peak memory 199388 kb
Host smart-01311d9d-ae9e-4721-bdab-d6784119787c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261955799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.3261955799
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.2145350533
Short name T331
Test name
Test status
Simulation time 1214633375 ps
CPU time 4.64 seconds
Started Jan 21 03:33:23 PM PST 24
Finished Jan 21 03:33:33 PM PST 24
Peak memory 199812 kb
Host smart-8310aa92-fc21-43fa-967f-a4f7938f741f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145350533 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.2145350533
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.920753208
Short name T170
Test name
Test status
Simulation time 174570662 ps
CPU time 1.17 seconds
Started Jan 21 03:33:26 PM PST 24
Finished Jan 21 03:33:30 PM PST 24
Peak memory 199572 kb
Host smart-698b4d3f-d35b-447e-9da2-54faed678786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920753208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.920753208
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.651121029
Short name T325
Test name
Test status
Simulation time 190939494 ps
CPU time 1.34 seconds
Started Jan 21 03:33:35 PM PST 24
Finished Jan 21 03:33:37 PM PST 24
Peak memory 199696 kb
Host smart-39599949-ca41-4770-8c14-bd3efce84ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651121029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.651121029
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.3511378915
Short name T561
Test name
Test status
Simulation time 1251288168 ps
CPU time 6.68 seconds
Started Jan 21 03:33:28 PM PST 24
Finished Jan 21 03:33:37 PM PST 24
Peak memory 199792 kb
Host smart-cd04955d-ec78-4f69-87c1-494d2287f2d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511378915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.3511378915
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.3844214175
Short name T277
Test name
Test status
Simulation time 145530145 ps
CPU time 1.94 seconds
Started Jan 21 03:33:23 PM PST 24
Finished Jan 21 03:33:30 PM PST 24
Peak memory 199588 kb
Host smart-af9550f1-ae3f-46bb-9c56-1147061449b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844214175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.3844214175
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.3446121928
Short name T377
Test name
Test status
Simulation time 158692969 ps
CPU time 1.08 seconds
Started Jan 21 03:33:26 PM PST 24
Finished Jan 21 03:33:30 PM PST 24
Peak memory 199596 kb
Host smart-9764f7b0-ec00-44b2-8b23-d9751efac65f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446121928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.3446121928
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.1896332082
Short name T542
Test name
Test status
Simulation time 87522754 ps
CPU time 0.83 seconds
Started Jan 21 03:33:21 PM PST 24
Finished Jan 21 03:33:27 PM PST 24
Peak memory 199576 kb
Host smart-695e2557-761b-42ce-a28a-9cfab9b01c68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896332082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.1896332082
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.436360151
Short name T459
Test name
Test status
Simulation time 1235033155 ps
CPU time 5.4 seconds
Started Jan 21 03:33:23 PM PST 24
Finished Jan 21 03:33:34 PM PST 24
Peak memory 216988 kb
Host smart-1413b043-2c8d-41b5-abc8-b3898df004cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436360151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.436360151
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.1293095936
Short name T405
Test name
Test status
Simulation time 244707016 ps
CPU time 1.2 seconds
Started Jan 21 03:33:28 PM PST 24
Finished Jan 21 03:33:31 PM PST 24
Peak memory 216912 kb
Host smart-529102e1-57a6-41c5-91e8-ae0fe4ddaa17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293095936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.1293095936
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.757223756
Short name T330
Test name
Test status
Simulation time 141606905 ps
CPU time 0.86 seconds
Started Jan 21 03:33:29 PM PST 24
Finished Jan 21 03:33:33 PM PST 24
Peak memory 199392 kb
Host smart-3cb2a6c1-ee0c-45b9-aa5b-e7fb3fdd52b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757223756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.757223756
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.1848239502
Short name T79
Test name
Test status
Simulation time 931571050 ps
CPU time 4.39 seconds
Started Jan 21 03:33:24 PM PST 24
Finished Jan 21 03:33:33 PM PST 24
Peak memory 199792 kb
Host smart-3ccb49cd-1ed5-4ca0-8da0-9b80ce3ac1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848239502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.1848239502
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.2803707093
Short name T562
Test name
Test status
Simulation time 149783489 ps
CPU time 1.15 seconds
Started Jan 21 03:33:27 PM PST 24
Finished Jan 21 03:33:31 PM PST 24
Peak memory 199528 kb
Host smart-451c8ad4-0191-4c63-8f3d-f7a44a76dc0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803707093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.2803707093
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.802042433
Short name T458
Test name
Test status
Simulation time 229409703 ps
CPU time 1.42 seconds
Started Jan 21 03:33:21 PM PST 24
Finished Jan 21 03:33:28 PM PST 24
Peak memory 199868 kb
Host smart-0b2d54bd-253b-4d9f-8701-627762b818d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802042433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.802042433
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.617609415
Short name T106
Test name
Test status
Simulation time 10821285549 ps
CPU time 39.72 seconds
Started Jan 21 03:33:24 PM PST 24
Finished Jan 21 03:34:09 PM PST 24
Peak memory 199828 kb
Host smart-6abcdb7e-e9d6-4130-9a03-4e6ff28d0c5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617609415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.617609415
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.2294444087
Short name T40
Test name
Test status
Simulation time 391443308 ps
CPU time 2.2 seconds
Started Jan 21 03:33:23 PM PST 24
Finished Jan 21 03:33:31 PM PST 24
Peak memory 199652 kb
Host smart-58609eb6-d522-4697-a388-e712f1a32ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294444087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.2294444087
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.3224777007
Short name T412
Test name
Test status
Simulation time 127610700 ps
CPU time 1.12 seconds
Started Jan 21 03:33:21 PM PST 24
Finished Jan 21 03:33:27 PM PST 24
Peak memory 199592 kb
Host smart-d44ddba6-8a94-42c9-9ed6-239fbfa341e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224777007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.3224777007
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.3808557067
Short name T396
Test name
Test status
Simulation time 71746404 ps
CPU time 0.77 seconds
Started Jan 21 03:33:29 PM PST 24
Finished Jan 21 03:33:33 PM PST 24
Peak memory 199544 kb
Host smart-42465c10-2ed1-4788-93ef-f7d62e879122
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808557067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.3808557067
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.1020561656
Short name T33
Test name
Test status
Simulation time 1228092163 ps
CPU time 5.63 seconds
Started Jan 21 03:33:32 PM PST 24
Finished Jan 21 03:33:39 PM PST 24
Peak memory 221688 kb
Host smart-8daed680-c828-4dcf-9b6a-fbc4bbc61c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020561656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.1020561656
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.62907098
Short name T456
Test name
Test status
Simulation time 244237045 ps
CPU time 1.1 seconds
Started Jan 21 03:33:41 PM PST 24
Finished Jan 21 03:33:45 PM PST 24
Peak memory 216908 kb
Host smart-607d9b28-b4ad-4f5c-92bc-d57d0b6fed5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62907098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.62907098
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.1126059776
Short name T329
Test name
Test status
Simulation time 122664004 ps
CPU time 0.77 seconds
Started Jan 21 03:33:36 PM PST 24
Finished Jan 21 03:33:38 PM PST 24
Peak memory 199300 kb
Host smart-70285eed-d19e-42d9-83e6-ebf395164636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126059776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.1126059776
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.316392168
Short name T340
Test name
Test status
Simulation time 1941916001 ps
CPU time 7.55 seconds
Started Jan 21 03:33:24 PM PST 24
Finished Jan 21 03:33:36 PM PST 24
Peak memory 199780 kb
Host smart-a1da5af1-dac3-4b24-a202-3bf0705c4e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316392168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.316392168
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.2122851139
Short name T168
Test name
Test status
Simulation time 154825969 ps
CPU time 1.13 seconds
Started Jan 21 03:33:31 PM PST 24
Finished Jan 21 03:33:34 PM PST 24
Peak memory 199528 kb
Host smart-b7c90485-5af7-4392-8c0a-afb379a94a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122851139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.2122851139
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.186147767
Short name T306
Test name
Test status
Simulation time 193866223 ps
CPU time 1.45 seconds
Started Jan 21 03:33:23 PM PST 24
Finished Jan 21 03:33:30 PM PST 24
Peak memory 199732 kb
Host smart-27a91f49-7494-4623-a109-b42732bfd902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186147767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.186147767
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.1441745066
Short name T475
Test name
Test status
Simulation time 2227551053 ps
CPU time 8.17 seconds
Started Jan 21 03:33:31 PM PST 24
Finished Jan 21 03:33:41 PM PST 24
Peak memory 199768 kb
Host smart-411c0006-5d82-429a-a2f6-d7e79556b846
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441745066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.1441745066
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.287917802
Short name T38
Test name
Test status
Simulation time 285124870 ps
CPU time 2.02 seconds
Started Jan 21 03:33:37 PM PST 24
Finished Jan 21 03:33:40 PM PST 24
Peak memory 199872 kb
Host smart-e1158b60-19ce-4382-afd7-dbb3dce08589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287917802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.287917802
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.3918717540
Short name T547
Test name
Test status
Simulation time 74231516 ps
CPU time 0.8 seconds
Started Jan 21 03:33:21 PM PST 24
Finished Jan 21 03:33:27 PM PST 24
Peak memory 199588 kb
Host smart-4a3fcafd-0721-4457-8e75-a334f57c38aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918717540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.3918717540
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.2988339787
Short name T323
Test name
Test status
Simulation time 64067819 ps
CPU time 0.73 seconds
Started Jan 21 03:30:42 PM PST 24
Finished Jan 21 03:30:44 PM PST 24
Peak memory 199580 kb
Host smart-25f9d5ac-fc9e-4d43-8f68-71716d33fd28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988339787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.2988339787
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.107517994
Short name T593
Test name
Test status
Simulation time 2183381589 ps
CPU time 8.34 seconds
Started Jan 21 03:30:41 PM PST 24
Finished Jan 21 03:30:51 PM PST 24
Peak memory 221708 kb
Host smart-c637e905-e9bc-4218-8cdc-abf0c9cfdca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107517994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.107517994
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.1729151622
Short name T416
Test name
Test status
Simulation time 244321737 ps
CPU time 1.08 seconds
Started Jan 21 03:30:39 PM PST 24
Finished Jan 21 03:30:41 PM PST 24
Peak memory 216808 kb
Host smart-356b7116-5d42-4a0f-ad04-1b712587d7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729151622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.1729151622
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.1192227711
Short name T378
Test name
Test status
Simulation time 184623699 ps
CPU time 0.9 seconds
Started Jan 21 03:30:31 PM PST 24
Finished Jan 21 03:30:35 PM PST 24
Peak memory 199400 kb
Host smart-05c3cf0f-2abc-4c9a-912b-da9ae46bd3d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192227711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.1192227711
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.39865662
Short name T116
Test name
Test status
Simulation time 888948763 ps
CPU time 4.61 seconds
Started Jan 21 03:30:31 PM PST 24
Finished Jan 21 03:30:39 PM PST 24
Peak memory 199856 kb
Host smart-e5718b22-ecdc-42f7-81c9-ed151050fd51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39865662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.39865662
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.857575433
Short name T608
Test name
Test status
Simulation time 151198363 ps
CPU time 1.14 seconds
Started Jan 21 03:30:39 PM PST 24
Finished Jan 21 03:30:42 PM PST 24
Peak memory 199604 kb
Host smart-3afb14e9-624c-44c7-8f73-e850728ae7c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857575433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.857575433
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.1510194494
Short name T260
Test name
Test status
Simulation time 114910574 ps
CPU time 1.2 seconds
Started Jan 21 03:30:29 PM PST 24
Finished Jan 21 03:30:34 PM PST 24
Peak memory 199712 kb
Host smart-2f73dd16-1a7e-4df1-b3cc-9c4cbf674cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510194494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.1510194494
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.242287268
Short name T293
Test name
Test status
Simulation time 1358300395 ps
CPU time 5.94 seconds
Started Jan 21 03:30:42 PM PST 24
Finished Jan 21 03:30:49 PM PST 24
Peak memory 199796 kb
Host smart-7d4056d6-2f12-4584-b5b1-9679e2c7c54e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242287268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.242287268
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.2729528961
Short name T402
Test name
Test status
Simulation time 281482904 ps
CPU time 1.85 seconds
Started Jan 21 03:30:38 PM PST 24
Finished Jan 21 03:30:40 PM PST 24
Peak memory 199648 kb
Host smart-e3879aaa-16c2-4b4f-828e-59bc5a8b8923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729528961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.2729528961
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.3270065801
Short name T294
Test name
Test status
Simulation time 121073845 ps
CPU time 0.94 seconds
Started Jan 21 03:55:13 PM PST 24
Finished Jan 21 03:55:17 PM PST 24
Peak memory 199552 kb
Host smart-51f9dac9-147f-4066-b95c-2950761709f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270065801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.3270065801
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.3304618820
Short name T139
Test name
Test status
Simulation time 61196428 ps
CPU time 0.75 seconds
Started Jan 21 03:30:51 PM PST 24
Finished Jan 21 03:30:53 PM PST 24
Peak memory 199576 kb
Host smart-563d071b-1af4-49e0-acc0-6ee40d9f1179
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304618820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.3304618820
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.1619944627
Short name T21
Test name
Test status
Simulation time 1230127964 ps
CPU time 5.95 seconds
Started Jan 21 03:30:51 PM PST 24
Finished Jan 21 03:30:58 PM PST 24
Peak memory 221664 kb
Host smart-4ef70f3f-8518-498a-b85c-460f75967ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619944627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.1619944627
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.2643802080
Short name T388
Test name
Test status
Simulation time 244149652 ps
CPU time 1.06 seconds
Started Jan 21 03:30:50 PM PST 24
Finished Jan 21 03:30:53 PM PST 24
Peak memory 216860 kb
Host smart-6800c33e-2222-489b-85dd-fb6e4ec5b484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643802080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.2643802080
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.3698358318
Short name T275
Test name
Test status
Simulation time 139158873 ps
CPU time 0.75 seconds
Started Jan 21 03:30:43 PM PST 24
Finished Jan 21 03:30:45 PM PST 24
Peak memory 199300 kb
Host smart-451864df-657e-4994-8e94-b688df71609c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698358318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.3698358318
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.2542546871
Short name T270
Test name
Test status
Simulation time 976587912 ps
CPU time 4.58 seconds
Started Jan 21 03:30:54 PM PST 24
Finished Jan 21 03:31:00 PM PST 24
Peak memory 199844 kb
Host smart-4f253eff-5ba3-46da-8e40-e1f1d2ac5fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542546871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.2542546871
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.2270585432
Short name T563
Test name
Test status
Simulation time 165497740 ps
CPU time 1.18 seconds
Started Jan 21 03:30:49 PM PST 24
Finished Jan 21 03:30:51 PM PST 24
Peak memory 199608 kb
Host smart-da285906-dc0c-4567-b83b-628501222e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270585432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.2270585432
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.2760496995
Short name T453
Test name
Test status
Simulation time 119785800 ps
CPU time 1.16 seconds
Started Jan 21 03:30:42 PM PST 24
Finished Jan 21 03:30:45 PM PST 24
Peak memory 199736 kb
Host smart-72397775-f69f-4b91-b122-130835333704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760496995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.2760496995
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.2887587694
Short name T147
Test name
Test status
Simulation time 495030471 ps
CPU time 2.42 seconds
Started Jan 21 03:30:51 PM PST 24
Finished Jan 21 03:30:55 PM PST 24
Peak memory 199800 kb
Host smart-a102140f-2faa-4c2b-94d4-41861819eedc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887587694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.2887587694
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.2915060856
Short name T42
Test name
Test status
Simulation time 307376318 ps
CPU time 2.2 seconds
Started Jan 21 03:30:50 PM PST 24
Finished Jan 21 03:30:54 PM PST 24
Peak memory 199632 kb
Host smart-184c727c-6d20-4bb2-890a-fa14f10fa072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915060856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.2915060856
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.2715092630
Short name T6
Test name
Test status
Simulation time 283109914 ps
CPU time 1.49 seconds
Started Jan 21 03:30:50 PM PST 24
Finished Jan 21 03:30:54 PM PST 24
Peak memory 199544 kb
Host smart-1fbeb830-010b-4f65-88c9-a7863175ab6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715092630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.2715092630
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.2335134828
Short name T575
Test name
Test status
Simulation time 79248094 ps
CPU time 0.81 seconds
Started Jan 21 03:30:59 PM PST 24
Finished Jan 21 03:31:02 PM PST 24
Peak memory 199492 kb
Host smart-c890f0a8-f88f-433f-a73e-901fe311d4cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335134828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.2335134828
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.220819365
Short name T1
Test name
Test status
Simulation time 1899379108 ps
CPU time 8.18 seconds
Started Jan 21 03:30:57 PM PST 24
Finished Jan 21 03:31:06 PM PST 24
Peak memory 217656 kb
Host smart-8a23228a-2bff-45ef-b061-3e9348d4160d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220819365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.220819365
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.2051743643
Short name T276
Test name
Test status
Simulation time 244703751 ps
CPU time 1.09 seconds
Started Jan 21 03:31:01 PM PST 24
Finished Jan 21 03:31:04 PM PST 24
Peak memory 216908 kb
Host smart-dd69b8d0-156e-41fc-8abb-1fc99d522c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051743643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.2051743643
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.1608894404
Short name T15
Test name
Test status
Simulation time 197996435 ps
CPU time 0.91 seconds
Started Jan 21 03:30:48 PM PST 24
Finished Jan 21 03:30:51 PM PST 24
Peak memory 199412 kb
Host smart-3727afe2-d224-4305-b2ee-af14447fa337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608894404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.1608894404
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.2981152214
Short name T538
Test name
Test status
Simulation time 1272383692 ps
CPU time 5.91 seconds
Started Jan 21 03:30:56 PM PST 24
Finished Jan 21 03:31:02 PM PST 24
Peak memory 199992 kb
Host smart-5a715679-2457-4d89-bfd4-9fd7bdd232e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981152214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.2981152214
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.221087759
Short name T140
Test name
Test status
Simulation time 109191298 ps
CPU time 1.05 seconds
Started Jan 21 03:31:00 PM PST 24
Finished Jan 21 03:31:03 PM PST 24
Peak memory 199612 kb
Host smart-947481a7-7216-4373-95da-12913d8a6d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221087759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.221087759
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.3574574386
Short name T103
Test name
Test status
Simulation time 2296839857 ps
CPU time 8.4 seconds
Started Jan 21 03:30:55 PM PST 24
Finished Jan 21 03:31:04 PM PST 24
Peak memory 199900 kb
Host smart-a33cd1ec-b241-46cf-8e8e-c695d800bb13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574574386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.3574574386
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.3084949085
Short name T339
Test name
Test status
Simulation time 304451335 ps
CPU time 2.07 seconds
Started Jan 21 03:31:00 PM PST 24
Finished Jan 21 03:31:05 PM PST 24
Peak memory 199652 kb
Host smart-43fc39ba-4974-44dd-bb7d-ddcf41c38344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084949085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.3084949085
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.448467925
Short name T509
Test name
Test status
Simulation time 186365115 ps
CPU time 1.27 seconds
Started Jan 21 03:30:58 PM PST 24
Finished Jan 21 03:31:02 PM PST 24
Peak memory 199576 kb
Host smart-c93fc9ba-f52b-498e-950f-57d69fa461a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448467925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.448467925
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.1856066515
Short name T45
Test name
Test status
Simulation time 71329009 ps
CPU time 0.77 seconds
Started Jan 21 03:30:59 PM PST 24
Finished Jan 21 03:31:02 PM PST 24
Peak memory 199492 kb
Host smart-bf3fd2f9-61e6-4bd4-935a-b6ca03956f5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856066515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.1856066515
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.1201022250
Short name T49
Test name
Test status
Simulation time 1221907001 ps
CPU time 6 seconds
Started Jan 21 03:30:58 PM PST 24
Finished Jan 21 03:31:06 PM PST 24
Peak memory 218032 kb
Host smart-4f731596-ff63-40c6-a5e2-76f0a71b75fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201022250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.1201022250
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.3713084249
Short name T164
Test name
Test status
Simulation time 251996586 ps
CPU time 1.07 seconds
Started Jan 21 03:31:10 PM PST 24
Finished Jan 21 03:31:12 PM PST 24
Peak memory 216904 kb
Host smart-49b3f98d-aed5-44a2-803e-3ff3418e492f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713084249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.3713084249
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.2556678264
Short name T20
Test name
Test status
Simulation time 154409758 ps
CPU time 0.84 seconds
Started Jan 21 03:30:58 PM PST 24
Finished Jan 21 03:31:01 PM PST 24
Peak memory 199388 kb
Host smart-f57d8948-df98-4329-90a3-19afb7e69b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556678264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.2556678264
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.1478496838
Short name T582
Test name
Test status
Simulation time 1427132373 ps
CPU time 5.22 seconds
Started Jan 21 03:30:56 PM PST 24
Finished Jan 21 03:31:03 PM PST 24
Peak memory 199684 kb
Host smart-eb845191-b9c8-43c6-a910-699eca8affb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478496838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.1478496838
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.499352936
Short name T302
Test name
Test status
Simulation time 144492872 ps
CPU time 1.1 seconds
Started Jan 21 03:30:57 PM PST 24
Finished Jan 21 03:30:59 PM PST 24
Peak memory 199440 kb
Host smart-5c2ea05b-5282-40c8-89d5-2f442bd9d5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499352936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.499352936
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.3290494079
Short name T243
Test name
Test status
Simulation time 251525217 ps
CPU time 1.49 seconds
Started Jan 21 03:30:57 PM PST 24
Finished Jan 21 03:30:59 PM PST 24
Peak memory 199740 kb
Host smart-e26383c1-ebfa-4f4d-b536-fdecafea5f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290494079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.3290494079
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.425639304
Short name T477
Test name
Test status
Simulation time 3496432146 ps
CPU time 16.97 seconds
Started Jan 21 03:31:00 PM PST 24
Finished Jan 21 03:31:19 PM PST 24
Peak memory 199892 kb
Host smart-c3e695cb-affb-4e78-bdc3-e8c12b484210
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425639304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.425639304
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.922651577
Short name T337
Test name
Test status
Simulation time 425653335 ps
CPU time 2.52 seconds
Started Jan 21 03:31:10 PM PST 24
Finished Jan 21 03:31:14 PM PST 24
Peak memory 199660 kb
Host smart-f1895f04-8ba8-4f44-8d6c-502ff7e9eb80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922651577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.922651577
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.152251286
Short name T273
Test name
Test status
Simulation time 155819312 ps
CPU time 1.08 seconds
Started Jan 21 03:31:10 PM PST 24
Finished Jan 21 03:31:12 PM PST 24
Peak memory 199592 kb
Host smart-c4cd7d07-4f04-4f91-8c28-759c97adf105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152251286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.152251286
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.4239310034
Short name T284
Test name
Test status
Simulation time 68787643 ps
CPU time 0.75 seconds
Started Jan 21 03:31:06 PM PST 24
Finished Jan 21 03:31:08 PM PST 24
Peak memory 199488 kb
Host smart-8066a1f9-8c57-491e-b12c-09d6fd25e35f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239310034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.4239310034
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.3932722827
Short name T77
Test name
Test status
Simulation time 1226043247 ps
CPU time 5.42 seconds
Started Jan 21 03:50:20 PM PST 24
Finished Jan 21 03:50:28 PM PST 24
Peak memory 216492 kb
Host smart-b2a8906b-4ea8-4262-b557-f973ebfa10a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932722827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.3932722827
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.3880147748
Short name T71
Test name
Test status
Simulation time 243703091 ps
CPU time 1.14 seconds
Started Jan 21 03:31:22 PM PST 24
Finished Jan 21 03:31:24 PM PST 24
Peak memory 216756 kb
Host smart-5cc2893a-a416-4b5d-a485-6c4916fbf17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880147748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.3880147748
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.376141798
Short name T610
Test name
Test status
Simulation time 140950489 ps
CPU time 0.81 seconds
Started Jan 21 03:30:59 PM PST 24
Finished Jan 21 03:31:02 PM PST 24
Peak memory 199412 kb
Host smart-743af1e0-a3ad-4627-a608-482d95a98c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376141798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.376141798
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.2255521735
Short name T345
Test name
Test status
Simulation time 1487157878 ps
CPU time 5.94 seconds
Started Jan 21 03:31:00 PM PST 24
Finished Jan 21 03:31:09 PM PST 24
Peak memory 199732 kb
Host smart-de2391ea-ef81-46b2-bba3-eeec94ac29cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255521735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.2255521735
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.1647149656
Short name T73
Test name
Test status
Simulation time 107779978 ps
CPU time 1.02 seconds
Started Jan 21 03:30:58 PM PST 24
Finished Jan 21 03:31:01 PM PST 24
Peak memory 199584 kb
Host smart-b0ded52d-57ed-4a99-9c17-1cf8f8ef9fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647149656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.1647149656
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.1070060055
Short name T485
Test name
Test status
Simulation time 124945899 ps
CPU time 1.14 seconds
Started Jan 21 03:31:00 PM PST 24
Finished Jan 21 03:31:03 PM PST 24
Peak memory 199800 kb
Host smart-cc879fb0-b4d6-4af2-b790-da47774feefc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070060055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.1070060055
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.1897241978
Short name T517
Test name
Test status
Simulation time 1284950612 ps
CPU time 6.23 seconds
Started Jan 21 03:31:22 PM PST 24
Finished Jan 21 03:31:29 PM PST 24
Peak memory 199764 kb
Host smart-c135f499-8064-4f6d-ad30-9557dbba6787
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897241978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.1897241978
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.1059387417
Short name T322
Test name
Test status
Simulation time 142870156 ps
CPU time 1.75 seconds
Started Jan 21 03:30:56 PM PST 24
Finished Jan 21 03:30:58 PM PST 24
Peak memory 199676 kb
Host smart-ae33052d-45a9-4040-a35b-aea210cc530f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059387417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.1059387417
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.1263083094
Short name T167
Test name
Test status
Simulation time 100488942 ps
CPU time 0.91 seconds
Started Jan 21 03:30:58 PM PST 24
Finished Jan 21 03:31:01 PM PST 24
Peak memory 199540 kb
Host smart-ecc36e75-cbb3-4e7a-90fa-e49bd97b3ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263083094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.1263083094
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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