RSTMGR Simulation Results

Friday May 20 2022 08:02:50 UTC

GitHub Revision: `60490355a`
Foundry Revision: `60490355a`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1970734642

Test Results

Milestone	Name	Tests	Passing	Total	Pass Rate
V1	smoke	rstmgr_smoke	50	50	100.00
V1	csr_hw_reset	rstmgr_csr_hw_reset	5	5	100.00
V1	csr_rw	rstmgr_csr_rw	20	20	100.00
V1	csr_bit_bash	rstmgr_csr_bit_bash	5	5	100.00
V1	csr_aliasing	rstmgr_csr_aliasing	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rstmgr_csr_mem_rw_with_rand_reset	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rstmgr_csr_rw	20	20	100.00
		rstmgr_csr_aliasing	5	5	100.00
V1		TOTAL	105	105	100.00
V2	reset_stretcher	rstmgr_por_stretcher	50	50	100.00
V2	sw_rst	rstmgr_sw_rst	50	50	100.00
V2	sw_rst_reset_race	rstmgr_sw_rst_reset_race	50	50	100.00
V2	reset_info	rstmgr_reset	50	50	100.00
V2	cpu_info	rstmgr_reset	50	50	100.00
V2	alert_info	rstmgr_reset	50	50	100.00
V2	reset_info_capture	rstmgr_reset	50	50	100.00
V2	stress_all	rstmgr_stress_all	50	50	100.00
V2	alert_test	rstmgr_alert_test	50	50	100.00
V2	tl_d_oob_addr_access	rstmgr_tl_errors	20	20	100.00
V2	tl_d_illegal_access	rstmgr_tl_errors	20	20	100.00
V2	tl_d_outstanding_access	rstmgr_csr_hw_reset	5	5	100.00
		rstmgr_csr_rw	20	20	100.00
		rstmgr_csr_aliasing	5	5	100.00
		rstmgr_same_csr_outstanding	20	20	100.00
V2	tl_d_partial_access	rstmgr_csr_hw_reset	5	5	100.00
		rstmgr_csr_rw	20	20	100.00
		rstmgr_csr_aliasing	5	5	100.00
		rstmgr_same_csr_outstanding	20	20	100.00
V2		TOTAL	340	340	100.00
V2S	tl_intg_err	rstmgr_tl_intg_err	20	20	100.00
V2S	prim_count_check	rstmgr_sec_cm	0	5	0.00
V2S	prim_fsm_check	rstmgr_sec_cm	0	5	0.00
V2S	sec_cm_bus_integrity	rstmgr_tl_intg_err	20	20	100.00
V2S	sec_cm_scan_intersig_mubi	rstmgr_sec_cm_scan_intersig_mubi	46	50	92.00
V2S	sec_cm_leaf_rst_bkgn_chk	rstmgr_leaf_rst_cnsty	50	50	100.00
V2S	sec_cm_leaf_rst_shadow	rstmgr_leaf_rst_shadow_attack	0	50	0.00
V2S	sec_cm_leaf_fsm_sparse	rstmgr_sec_cm	0	5	0.00
V2S	sec_cm_sw_rst_config_regwen	rstmgr_csr_rw	20	20	100.00
V2S	sec_cm_dump_ctrl_config_regwen	rstmgr_csr_rw	20	20	100.00
V2S		TOTAL	116	175	66.29
V3	stress_all_with_rand_reset	rstmgr_stress_all_with_rand_reset	49	50	98.00
V3		TOTAL	49	50	98.00
		TOTAL	610	670	91.04

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	5	5	2	40.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.96	99.19	80.65	97.34	--	99.79	94.19	92.59

Failure Buckets

UVM_ERROR (rstmgr_leaf_rst_shadow_attack_vseq.sv:65) [rstmgr_leaf_rst_shadow_attack_vseq] Check failed (uvm_hdl_release(epath)) has 50 failures:

Test rstmgr_leaf_rst_shadow_attack has 50 failures.

0.rstmgr_leaf_rst_shadow_attack.2431293737
Line 71, in log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/0.rstmgr_leaf_rst_shadow_attack/out/run.log

  UVM_ERROR @  28348023 ps: (rstmgr_leaf_rst_shadow_attack_vseq.sv:65) [uvm_test_top.env.virtual_sequencer.rstmgr_leaf_rst_shadow_attack_vseq] Check failed (uvm_hdl_release(epath))
  UVM_INFO @  28348023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.rstmgr_leaf_rst_shadow_attack.930301286
Line 71, in log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/1.rstmgr_leaf_rst_shadow_attack/out/run.log

  UVM_ERROR @  28702437 ps: (rstmgr_leaf_rst_shadow_attack_vseq.sv:65) [uvm_test_top.env.virtual_sequencer.rstmgr_leaf_rst_shadow_attack_vseq] Check failed (uvm_hdl_release(epath))
  UVM_INFO @  28702437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 48 more failures.

UVM_ERROR (cip_base_vseq.sv:597) virtual_sequencer [rstmgr_common_vseq] expect alert:fatal_fault to fire has 4 failures:

Test rstmgr_sec_cm has 4 failures.

0.rstmgr_sec_cm.946264962
Line 77, in log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/0.rstmgr_sec_cm/out/run.log

  UVM_ERROR @  27415456 ps: (cip_base_vseq.sv:597) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.rstmgr_common_vseq] expect alert:fatal_fault to fire
  UVM_INFO @  27415456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.rstmgr_sec_cm.2043139277
Line 77, in log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/2.rstmgr_sec_cm/out/run.log

  UVM_ERROR @  27328598 ps: (cip_base_vseq.sv:597) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.rstmgr_common_vseq] expect alert:fatal_fault to fire
  UVM_INFO @  27328598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (csr_utils_pkg.sv:431) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: rstmgr_reg_block.reset_info expected reset_info to be POR for scan reset has 4 failures:

Test rstmgr_sec_cm_scan_intersig_mubi has 4 failures.

18.rstmgr_sec_cm_scan_intersig_mubi.3538284515
Line 72, in log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/18.rstmgr_sec_cm_scan_intersig_mubi/out/run.log

  UVM_ERROR @  28685015 ps: (csr_utils_pkg.sv:431) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: rstmgr_reg_block.reset_info expected reset_info to be POR for scan reset
  UVM_INFO @  28685015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

26.rstmgr_sec_cm_scan_intersig_mubi.1762563165
Line 72, in log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/26.rstmgr_sec_cm_scan_intersig_mubi/out/run.log

  UVM_ERROR @  31596009 ps: (csr_utils_pkg.sv:431) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: rstmgr_reg_block.reset_info expected reset_info to be POR for scan reset
  UVM_INFO @  31596009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Offending '(state_q === rstmgr_cnsty_chk.u_state_regs.state_o)' has 1 failures:

Test rstmgr_sec_cm has 1 failures.

1.rstmgr_sec_cm.1138199536
Line 76, in log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/1.rstmgr_sec_cm/out/run.log

      Offending '(state_q === rstmgr_cnsty_chk.u_state_regs.state_o)'
  UVM_ERROR @  27428824 ps: (rstmgr_cnsty_chk.sv:112) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @  27428824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test rstmgr_stress_all_with_rand_reset has 1 failures.
  - 9.rstmgr_stress_all_with_rand_reset.4214709478
    Line 1819, in log /container/opentitan-public/scratch/os_regression/rstmgr-sim-vcs/9.rstmgr_stress_all_with_rand_reset/out/run.log
```
  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```