RSTMGR Simulation Results

Friday May 20 2022 08:02:50 UTC

GitHub Revision: 60490355a
Foundry Revision: 60490355a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1970734642

Test Results

Milestone Name Tests Passing Total Pass Rate
V1 smoke rstmgr_smoke 50 50 100.00
V1 csr_hw_reset rstmgr_csr_hw_reset 5 5 100.00
V1 csr_rw rstmgr_csr_rw 20 20 100.00
V1 csr_bit_bash rstmgr_csr_bit_bash 5 5 100.00
V1 csr_aliasing rstmgr_csr_aliasing 5 5 100.00
V1 csr_mem_rw_with_rand_reset rstmgr_csr_mem_rw_with_rand_reset 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rstmgr_csr_rw 20 20 100.00
rstmgr_csr_aliasing 5 5 100.00
V1 TOTAL 105 105 100.00
V2 reset_stretcher rstmgr_por_stretcher 50 50 100.00
V2 sw_rst rstmgr_sw_rst 50 50 100.00
V2 sw_rst_reset_race rstmgr_sw_rst_reset_race 50 50 100.00
V2 reset_info rstmgr_reset 50 50 100.00
V2 cpu_info rstmgr_reset 50 50 100.00
V2 alert_info rstmgr_reset 50 50 100.00
V2 reset_info_capture rstmgr_reset 50 50 100.00
V2 stress_all rstmgr_stress_all 50 50 100.00
V2 alert_test rstmgr_alert_test 50 50 100.00
V2 tl_d_oob_addr_access rstmgr_tl_errors 20 20 100.00
V2 tl_d_illegal_access rstmgr_tl_errors 20 20 100.00
V2 tl_d_outstanding_access rstmgr_csr_hw_reset 5 5 100.00
rstmgr_csr_rw 20 20 100.00
rstmgr_csr_aliasing 5 5 100.00
rstmgr_same_csr_outstanding 20 20 100.00
V2 tl_d_partial_access rstmgr_csr_hw_reset 5 5 100.00
rstmgr_csr_rw 20 20 100.00
rstmgr_csr_aliasing 5 5 100.00
rstmgr_same_csr_outstanding 20 20 100.00
V2 TOTAL 340 340 100.00
V2S tl_intg_err rstmgr_tl_intg_err 20 20 100.00
V2S prim_count_check rstmgr_sec_cm 0 5 0.00
V2S prim_fsm_check rstmgr_sec_cm 0 5 0.00
V2S sec_cm_bus_integrity rstmgr_tl_intg_err 20 20 100.00
V2S sec_cm_scan_intersig_mubi rstmgr_sec_cm_scan_intersig_mubi 46 50 92.00
V2S sec_cm_leaf_rst_bkgn_chk rstmgr_leaf_rst_cnsty 50 50 100.00
V2S sec_cm_leaf_rst_shadow rstmgr_leaf_rst_shadow_attack 0 50 0.00
V2S sec_cm_leaf_fsm_sparse rstmgr_sec_cm 0 5 0.00
V2S sec_cm_sw_rst_config_regwen rstmgr_csr_rw 20 20 100.00
V2S sec_cm_dump_ctrl_config_regwen rstmgr_csr_rw 20 20 100.00
V2S TOTAL 116 175 66.29
V3 stress_all_with_rand_reset rstmgr_stress_all_with_rand_reset 49 50 98.00
V3 TOTAL 49 50 98.00
TOTAL 610 670 91.04

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 8 8 8 100.00
V2S 5 5 2 40.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
93.96 99.19 80.65 97.34 -- 99.79 94.19 92.59

Failure Buckets

Past Results