RSTMGR_CNSTY_CHK Simulation Results

Wednesday November 22 2023 20:02:38 UTC

GitHub Revision: 4002b28ec4

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56541452733628775295814943325285397402671097056517970046183331126493552547969

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 TOTAL 0 0 --
V2 TOTAL 0 0 --
V2S unexpected_child_reset_activity rstmgr_cnsty_chk_smoke 0 0 --
V2S child_reset_asserts_late child_reset_asserts_late 0 0 --
V2S child_reset_releases_late child_reset_releases_late 0 0 --
V2S parent_reset_asserts_late parent_reset_asserts_late 0 0 --
V2S parent_reset_releases_late parent_reset_releases_late 0 0 --
V2S TOTAL 0 0 --
V3 TOTAL 0 0 --
Unmapped tests rstmgr_cnsty_chk_test 2.800s 9.684ms 10 10 100.00
TOTAL 10 10 100.00

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 1 100.00
V2S 5 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT
95.87 98.41 86.21 100.00 92.31 98.31 100.00

Past Results