9969cbe9c| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rv_dm_smoke | 1.270s | 221.094us | 2 | 2 | 100.00 |
| V1 | jtag_dtm_csr_hw_reset | rv_dm_jtag_dtm_csr_hw_reset | 0.770s | 61.359us | 5 | 5 | 100.00 |
| V1 | jtag_dtm_csr_rw | rv_dm_jtag_dtm_csr_rw | 0.930s | 116.982us | 20 | 20 | 100.00 |
| V1 | jtag_dtm_csr_bit_bash | rv_dm_jtag_dtm_csr_bit_bash | 12.120s | 3.999ms | 5 | 5 | 100.00 |
| V1 | jtag_dtm_csr_aliasing | rv_dm_jtag_dtm_csr_aliasing | 0.920s | 219.996us | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_hw_reset | rv_dm_jtag_dmi_csr_hw_reset | 3.120s | 883.645us | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_rw | rv_dm_jtag_dmi_csr_rw | 3.880s | 1.187ms | 20 | 20 | 100.00 |
| V1 | jtag_dmi_csr_bit_bash | rv_dm_jtag_dmi_csr_bit_bash | 51.070s | 17.009ms | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_aliasing | rv_dm_jtag_dmi_csr_aliasing | 21.500s | 11.838ms | 5 | 5 | 100.00 |
| V1 | csr_hw_reset | rv_dm_csr_hw_reset | 1.560s | 306.979us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_dm_csr_rw | 2.420s | 731.565us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_dm_csr_bit_bash | 1.188m | 13.100ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_dm_csr_aliasing | 1.216m | 47.525ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_dm_csr_mem_rw_with_rand_reset | 9.840s | 5.217ms | 13 | 20 | 65.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_dm_csr_rw | 2.420s | 731.565us | 20 | 20 | 100.00 |
| rv_dm_csr_aliasing | 1.216m | 47.525ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | rv_dm_mem_walk | 0.630s | 19.165us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rv_dm_mem_partial_access | 0.650s | 23.983us | 5 | 5 | 100.00 |
| V1 | TOTAL | 130 | 137 | 94.89 | |||
| V2 | idcode | rv_dm_smoke | 1.270s | 221.094us | 2 | 2 | 100.00 |
| V2 | jtag_dtm_hard_reset | jtag_dtm_hard_reset | 0 | 0 | -- | ||
| V2 | jtag_dtm_idle_hint | jtag_dtm_idle_hint | 0 | 0 | -- | ||
| V2 | jtag_dmi_failed_op | jtag_dmi_failed_op | 0 | 0 | -- | ||
| V2 | jtag_dmi_dm_inactive | jtag_dmi_dm_inactive | 0 | 0 | -- | ||
| V2 | sba | rv_dm_sba_tl_access | 22.240s | 6.421ms | 20 | 20 | 100.00 |
| rv_dm_delayed_resp_sba_tl_access | 40.360s | 13.683ms | 20 | 20 | 100.00 | ||
| V2 | bad_sba | rv_dm_bad_sba_tl_access | 17.410s | 5.121ms | 20 | 20 | 100.00 |
| V2 | sba_autoincrement | rv_dm_autoincr_sba_tl_access | 1.978m | 42.170ms | 16 | 20 | 80.00 |
| V2 | jtag_dmi_debug_disabled | jtag_dmi_debug_disabled | 0 | 0 | -- | ||
| V2 | sba_debug_disabled | sba_debug_disabled | 0 | 0 | -- | ||
| V2 | ndmreset_req | ndmreset_req | 0 | 0 | -- | ||
| V2 | hart_unavail | hart_unavail | 0 | 0 | -- | ||
| V2 | tap_ctrl_transitions | tap_ctrl_transitions | 0 | 0 | -- | ||
| V2 | stress_all | rv_dm_stress_all | 0.590s | 0 | 50 | 0.00 | |
| V2 | alert_test | rv_dm_alert_test | 0.730s | 18.196us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_dm_tl_errors | 6.690s | 343.143us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_dm_tl_errors | 6.690s | 343.143us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_dm_csr_hw_reset | 1.560s | 306.979us | 5 | 5 | 100.00 |
| rv_dm_csr_rw | 2.420s | 731.565us | 20 | 20 | 100.00 | ||
| rv_dm_csr_aliasing | 1.216m | 47.525ms | 5 | 5 | 100.00 | ||
| rv_dm_same_csr_outstanding | 9.220s | 6.256ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_dm_csr_hw_reset | 1.560s | 306.979us | 5 | 5 | 100.00 |
| rv_dm_csr_rw | 2.420s | 731.565us | 20 | 20 | 100.00 | ||
| rv_dm_csr_aliasing | 1.216m | 47.525ms | 5 | 5 | 100.00 | ||
| rv_dm_same_csr_outstanding | 9.220s | 6.256ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 166 | 220 | 75.45 | |||
| V2S | tl_intg_err | rv_dm_sec_cm | 1.360s | 291.020us | 5 | 5 | 100.00 |
| rv_dm_tl_intg_err | 20.810s | 6.518ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | sec_cm_bus_integrity | 0 | 0 | -- | ||
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sec_cm_lc_hw_debug_en_intersig_mubi | 0 | 0 | -- | ||
| V2S | sec_cm_dm_en_ctrl_lc_gated | sec_cm_dm_en_ctrl_lc_gated | 0 | 0 | -- | ||
| V2S | sec_cm_sba_tl_lc_gate_fsm_sparse | sec_cm_sba_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | sec_cm_mem_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
| V2S | sec_cm_exec_ctrl_mubi | sec_cm_exec_ctrl_mubi | 0 | 0 | -- | ||
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_dm_stress_all_with_rand_reset | 0.670s | 5.411us | 0 | 50 | 0.00 |
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 321 | 432 | 74.31 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 16 | 16 | 15 | 93.75 |
| V2 | 17 | 8 | 6 | 35.29 |
| V2S | 8 | 2 | 2 | 25.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 76.97 | 83.23 | 61.69 | 87.95 | 46.15 | 66.67 | 97.75 | 95.34 |
UVM_WARNING [BDTYP] Cannot create an object of type 'rv_dm_stress_all_vseq' because it is not registered with the factory. has 100 failures:
0.rv_dm_stress_all_with_rand_reset.2348659932
Line 230, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_WARNING @ 5575632 ps: [BDTYP] Cannot create an object of type 'rv_dm_stress_all_vseq' because it is not registered with the factory.
UVM_INFO @ 5575632 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
1.rv_dm_stress_all_with_rand_reset.4173652112
Line 230, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_WARNING @ 3476218 ps: [BDTYP] Cannot create an object of type 'rv_dm_stress_all_vseq' because it is not registered with the factory.
UVM_INFO @ 3476218 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
... and 48 more failures.
0.rv_dm_stress_all.1384288976
Line 230, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all/latest/run.log
UVM_WARNING @ 0 ps: [BDTYP] Cannot create an object of type 'rv_dm_stress_all_vseq' because it is not registered with the factory.
UVM_INFO @ 0 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
1.rv_dm_stress_all.3891496856
Line 230, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all/latest/run.log
UVM_WARNING @ 0 ps: [BDTYP] Cannot create an object of type 'rv_dm_stress_all_vseq' because it is not registered with the factory.
UVM_INFO @ 0 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
... and 48 more failures.
UVM_ERROR (cip_base_vseq.sv:717) [rv_dm_common_vseq] Check failed has_outstanding_access() == * (* [*] vs * [*]) No CSR outstanding items after reset! has 7 failures:
4.rv_dm_csr_mem_rw_with_rand_reset.983829750
Line 240, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 796671931 ps: (cip_base_vseq.sv:717) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed has_outstanding_access() == 0 (1 [0x1] vs 0 [0x0]) No CSR outstanding items after reset!
UVM_INFO @ 796671931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.rv_dm_csr_mem_rw_with_rand_reset.1887473112
Line 234, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/10.rv_dm_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 20147247 ps: (cip_base_vseq.sv:717) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed has_outstanding_access() == 0 (1 [0x1] vs 0 [0x0]) No CSR outstanding items after reset!
UVM_INFO @ 20147247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
1.rv_dm_autoincr_sba_tl_access.74693185
Line 308, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.rv_dm_autoincr_sba_tl_access.205002602
Line 641, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (jtag_rv_debugger.sv:1108) [debugger] Check failed is_busy == * (* [*] vs * [*]) has 1 failures:
6.rv_dm_autoincr_sba_tl_access.2752801291
Line 275, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 301522089 ps: (jtag_rv_debugger.sv:1108) [debugger] Check failed is_busy == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 301522089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_sba_tl_access_vseq_lib.sv:120) [rv_dm_autoincr_sba_tl_access_vseq] Check failed (!req.timed_out) has 1 failures:
14.rv_dm_autoincr_sba_tl_access.3017114910
Line 241, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/14.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 38305062 ps: (rv_dm_sba_tl_access_vseq_lib.sv:120) [uvm_test_top.env.virtual_sequencer.rv_dm_autoincr_sba_tl_access_vseq] Check failed (!req.timed_out)
UVM_INFO @ 38305062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---