5e125d790| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rv_dm_smoke | 1.160s | 591.350us | 2 | 2 | 100.00 |
| V1 | jtag_dtm_csr_hw_reset | rv_dm_jtag_dtm_csr_hw_reset | 0.690s | 62.915us | 5 | 5 | 100.00 |
| V1 | jtag_dtm_csr_rw | rv_dm_jtag_dtm_csr_rw | 0.890s | 93.561us | 20 | 20 | 100.00 |
| V1 | jtag_dtm_csr_bit_bash | rv_dm_jtag_dtm_csr_bit_bash | 8.070s | 2.605ms | 5 | 5 | 100.00 |
| V1 | jtag_dtm_csr_aliasing | rv_dm_jtag_dtm_csr_aliasing | 0.840s | 83.055us | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_hw_reset | rv_dm_jtag_dmi_csr_hw_reset | 2.570s | 674.926us | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_rw | rv_dm_jtag_dmi_csr_rw | 4.040s | 1.163ms | 20 | 20 | 100.00 |
| V1 | jtag_dmi_csr_bit_bash | rv_dm_jtag_dmi_csr_bit_bash | 1.578m | 50.000ms | 4 | 5 | 80.00 |
| V1 | jtag_dmi_csr_aliasing | rv_dm_jtag_dmi_csr_aliasing | 41.030s | 12.513ms | 5 | 5 | 100.00 |
| V1 | csr_hw_reset | rv_dm_csr_hw_reset | 2.130s | 53.005us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_dm_csr_rw | 2.270s | 311.591us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_dm_csr_bit_bash | 1.090m | 10.111ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_dm_csr_aliasing | 32.010s | 2.074ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_dm_csr_mem_rw_with_rand_reset | 8.990s | 3.330ms | 17 | 20 | 85.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_dm_csr_rw | 2.270s | 311.591us | 20 | 20 | 100.00 |
| rv_dm_csr_aliasing | 32.010s | 2.074ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | rv_dm_mem_walk | 0.700s | 21.661us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rv_dm_mem_partial_access | 0.660s | 29.860us | 5 | 5 | 100.00 |
| V1 | TOTAL | 133 | 137 | 97.08 | |||
| V2 | idcode | rv_dm_smoke | 1.160s | 591.350us | 2 | 2 | 100.00 |
| V2 | jtag_dtm_hard_reset | jtag_dtm_hard_reset | 0 | 0 | -- | ||
| V2 | jtag_dtm_idle_hint | jtag_dtm_idle_hint | 0 | 0 | -- | ||
| V2 | jtag_dmi_failed_op | jtag_dmi_failed_op | 0 | 0 | -- | ||
| V2 | jtag_dmi_dm_inactive | jtag_dmi_dm_inactive | 0 | 0 | -- | ||
| V2 | sba | rv_dm_sba_tl_access | 27.810s | 7.567ms | 20 | 20 | 100.00 |
| rv_dm_delayed_resp_sba_tl_access | 20.590s | 5.869ms | 20 | 20 | 100.00 | ||
| V2 | bad_sba | rv_dm_bad_sba_tl_access | 22.580s | 12.001ms | 20 | 20 | 100.00 |
| V2 | sba_autoincrement | rv_dm_autoincr_sba_tl_access | 2.261m | 38.942ms | 16 | 20 | 80.00 |
| V2 | jtag_dmi_debug_disabled | jtag_dmi_debug_disabled | 0 | 0 | -- | ||
| V2 | sba_debug_disabled | sba_debug_disabled | 0 | 0 | -- | ||
| V2 | ndmreset_req | ndmreset_req | 0 | 0 | -- | ||
| V2 | hart_unavail | hart_unavail | 0 | 0 | -- | ||
| V2 | tap_ctrl_transitions | tap_ctrl_transitions | 0 | 0 | -- | ||
| V2 | stress_all | rv_dm_stress_all | 0.620s | 0 | 50 | 0.00 | |
| V2 | alert_test | rv_dm_alert_test | 0.710s | 34.351us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_dm_tl_errors | 5.860s | 876.564us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_dm_tl_errors | 5.860s | 876.564us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_dm_csr_hw_reset | 2.130s | 53.005us | 5 | 5 | 100.00 |
| rv_dm_csr_rw | 2.270s | 311.591us | 20 | 20 | 100.00 | ||
| rv_dm_csr_aliasing | 32.010s | 2.074ms | 5 | 5 | 100.00 | ||
| rv_dm_same_csr_outstanding | 8.390s | 534.480us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_dm_csr_hw_reset | 2.130s | 53.005us | 5 | 5 | 100.00 |
| rv_dm_csr_rw | 2.270s | 311.591us | 20 | 20 | 100.00 | ||
| rv_dm_csr_aliasing | 32.010s | 2.074ms | 5 | 5 | 100.00 | ||
| rv_dm_same_csr_outstanding | 8.390s | 534.480us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 166 | 220 | 75.45 | |||
| V2S | tl_intg_err | rv_dm_sec_cm | 1.160s | 295.205us | 5 | 5 | 100.00 |
| rv_dm_tl_intg_err | 20.290s | 4.868ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | sec_cm_bus_integrity | 0 | 0 | -- | ||
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sec_cm_lc_hw_debug_en_intersig_mubi | 0 | 0 | -- | ||
| V2S | sec_cm_dm_en_ctrl_lc_gated | sec_cm_dm_en_ctrl_lc_gated | 0 | 0 | -- | ||
| V2S | sec_cm_sba_tl_lc_gate_fsm_sparse | sec_cm_sba_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | sec_cm_mem_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
| V2S | sec_cm_exec_ctrl_mubi | sec_cm_exec_ctrl_mubi | 0 | 0 | -- | ||
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_dm_stress_all_with_rand_reset | 0.680s | 12.743us | 0 | 50 | 0.00 |
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 324 | 432 | 75.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 16 | 16 | 14 | 87.50 |
| V2 | 17 | 8 | 6 | 35.29 |
| V2S | 8 | 2 | 2 | 25.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 76.97 | 83.23 | 61.69 | 87.95 | 46.15 | 66.67 | 97.75 | 95.34 |
UVM_WARNING [BDTYP] Cannot create an object of type 'rv_dm_stress_all_vseq' because it is not registered with the factory. has 100 failures:
0.rv_dm_stress_all_with_rand_reset.1448625216
Line 230, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_WARNING @ 5566971 ps: [BDTYP] Cannot create an object of type 'rv_dm_stress_all_vseq' because it is not registered with the factory.
UVM_INFO @ 5566971 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
1.rv_dm_stress_all_with_rand_reset.3989326129
Line 230, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_WARNING @ 4438761 ps: [BDTYP] Cannot create an object of type 'rv_dm_stress_all_vseq' because it is not registered with the factory.
UVM_INFO @ 4438761 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
... and 48 more failures.
0.rv_dm_stress_all.2324315460
Line 230, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all/latest/run.log
UVM_WARNING @ 0 ps: [BDTYP] Cannot create an object of type 'rv_dm_stress_all_vseq' because it is not registered with the factory.
UVM_INFO @ 0 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
1.rv_dm_stress_all.462132252
Line 230, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all/latest/run.log
UVM_WARNING @ 0 ps: [BDTYP] Cannot create an object of type 'rv_dm_stress_all_vseq' because it is not registered with the factory.
UVM_INFO @ 0 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
... and 48 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
Test rv_dm_jtag_dmi_csr_bit_bash has 1 failures.
0.rv_dm_jtag_dmi_csr_bit_bash.2240788506
Line 232, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_bit_bash/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_autoincr_sba_tl_access has 3 failures.
1.rv_dm_autoincr_sba_tl_access.1445368575
Line 239, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.rv_dm_autoincr_sba_tl_access.2456724163
Line 443, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:717) [rv_dm_common_vseq] Check failed has_outstanding_access() == * (* [*] vs * [*]) No CSR outstanding items after reset! has 3 failures:
7.rv_dm_csr_mem_rw_with_rand_reset.2200178110
Line 234, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 4024458412 ps: (cip_base_vseq.sv:717) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed has_outstanding_access() == 0 (1 [0x1] vs 0 [0x0]) No CSR outstanding items after reset!
UVM_INFO @ 4024458412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.rv_dm_csr_mem_rw_with_rand_reset.937110851
Line 234, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/11.rv_dm_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 6792563 ps: (cip_base_vseq.sv:717) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed has_outstanding_access() == 0 (1 [0x1] vs 0 [0x0]) No CSR outstanding items after reset!
UVM_INFO @ 6792563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (jtag_rv_debugger.sv:1108) [debugger] Check failed is_busy == * (* [*] vs * [*]) has 1 failures:
8.rv_dm_autoincr_sba_tl_access.3301233266
Line 245, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 51258375 ps: (jtag_rv_debugger.sv:1108) [debugger] Check failed is_busy == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 51258375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---