41c521d28| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rv_dm_smoke | 1.180s | 750.035us | 2 | 2 | 100.00 |
| V1 | jtag_dtm_csr_hw_reset | rv_dm_jtag_dtm_csr_hw_reset | 0.790s | 174.644us | 5 | 5 | 100.00 |
| V1 | jtag_dtm_csr_rw | rv_dm_jtag_dtm_csr_rw | 0.800s | 97.454us | 20 | 20 | 100.00 |
| V1 | jtag_dtm_csr_bit_bash | rv_dm_jtag_dtm_csr_bit_bash | 3.700s | 3.375ms | 4 | 5 | 80.00 |
| V1 | jtag_dtm_csr_aliasing | rv_dm_jtag_dtm_csr_aliasing | 1.060s | 144.043us | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_hw_reset | rv_dm_jtag_dmi_csr_hw_reset | 1.800s | 760.355us | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_rw | rv_dm_jtag_dmi_csr_rw | 4.240s | 1.339ms | 20 | 20 | 100.00 |
| V1 | jtag_dmi_csr_bit_bash | rv_dm_jtag_dmi_csr_bit_bash | 2.379m | 49.021ms | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_aliasing | rv_dm_jtag_dmi_csr_aliasing | 26.960s | 9.356ms | 5 | 5 | 100.00 |
| V1 | csr_hw_reset | rv_dm_csr_hw_reset | 2.370s | 55.247us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_dm_csr_rw | 2.420s | 208.536us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_dm_csr_bit_bash | 1.132m | 12.968ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_dm_csr_aliasing | 1.153m | 18.052ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_dm_csr_mem_rw_with_rand_reset | 7.150s | 3.259ms | 15 | 20 | 75.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_dm_csr_rw | 2.420s | 208.536us | 20 | 20 | 100.00 |
| rv_dm_csr_aliasing | 1.153m | 18.052ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | rv_dm_mem_walk | 0.770s | 27.566us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rv_dm_mem_partial_access | 0.650s | 18.277us | 5 | 5 | 100.00 |
| V1 | TOTAL | 131 | 137 | 95.62 | |||
| V2 | idcode | rv_dm_smoke | 1.180s | 750.035us | 2 | 2 | 100.00 |
| V2 | jtag_dtm_hard_reset | jtag_dtm_hard_reset | 0 | 0 | -- | ||
| V2 | jtag_dtm_idle_hint | jtag_dtm_idle_hint | 0 | 0 | -- | ||
| V2 | jtag_dmi_failed_op | jtag_dmi_failed_op | 0 | 0 | -- | ||
| V2 | jtag_dmi_dm_inactive | jtag_dmi_dm_inactive | 0 | 0 | -- | ||
| V2 | sba | rv_dm_sba_tl_access | 24.380s | 8.869ms | 20 | 20 | 100.00 |
| rv_dm_delayed_resp_sba_tl_access | 16.880s | 4.963ms | 20 | 20 | 100.00 | ||
| V2 | bad_sba | rv_dm_bad_sba_tl_access | 22.150s | 11.175ms | 20 | 20 | 100.00 |
| V2 | sba_autoincrement | rv_dm_autoincr_sba_tl_access | 1.095m | 27.366ms | 17 | 20 | 85.00 |
| V2 | jtag_dmi_debug_disabled | jtag_dmi_debug_disabled | 0 | 0 | -- | ||
| V2 | sba_debug_disabled | sba_debug_disabled | 0 | 0 | -- | ||
| V2 | ndmreset_req | ndmreset_req | 0 | 0 | -- | ||
| V2 | hart_unavail | hart_unavail | 0 | 0 | -- | ||
| V2 | tap_ctrl_transitions | tap_ctrl_transitions | 0 | 0 | -- | ||
| V2 | stress_all | rv_dm_stress_all | 0.590s | 0 | 50 | 0.00 | |
| V2 | alert_test | rv_dm_alert_test | 0.760s | 65.593us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_dm_tl_errors | 5.310s | 346.985us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_dm_tl_errors | 5.310s | 346.985us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_dm_csr_hw_reset | 2.370s | 55.247us | 5 | 5 | 100.00 |
| rv_dm_csr_rw | 2.420s | 208.536us | 20 | 20 | 100.00 | ||
| rv_dm_csr_aliasing | 1.153m | 18.052ms | 5 | 5 | 100.00 | ||
| rv_dm_same_csr_outstanding | 7.360s | 566.683us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_dm_csr_hw_reset | 2.370s | 55.247us | 5 | 5 | 100.00 |
| rv_dm_csr_rw | 2.420s | 208.536us | 20 | 20 | 100.00 | ||
| rv_dm_csr_aliasing | 1.153m | 18.052ms | 5 | 5 | 100.00 | ||
| rv_dm_same_csr_outstanding | 7.360s | 566.683us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 167 | 220 | 75.91 | |||
| V2S | tl_intg_err | rv_dm_sec_cm | 1.250s | 245.669us | 5 | 5 | 100.00 |
| rv_dm_tl_intg_err | 19.220s | 1.292ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | sec_cm_bus_integrity | 0 | 0 | -- | ||
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sec_cm_lc_hw_debug_en_intersig_mubi | 0 | 0 | -- | ||
| V2S | sec_cm_dm_en_ctrl_lc_gated | sec_cm_dm_en_ctrl_lc_gated | 0 | 0 | -- | ||
| V2S | sec_cm_sba_tl_lc_gate_fsm_sparse | sec_cm_sba_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | sec_cm_mem_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
| V2S | sec_cm_exec_ctrl_mubi | sec_cm_exec_ctrl_mubi | 0 | 0 | -- | ||
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_dm_stress_all_with_rand_reset | 0.670s | 11.661us | 0 | 50 | 0.00 |
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 323 | 432 | 74.77 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 16 | 16 | 14 | 87.50 |
| V2 | 17 | 8 | 6 | 35.29 |
| V2S | 8 | 2 | 2 | 25.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 77.33 | 83.23 | 61.69 | 87.95 | 48.72 | 66.67 | 97.75 | 95.34 |
UVM_WARNING [BDTYP] Cannot create an object of type 'rv_dm_stress_all_vseq' because it is not registered with the factory. has 100 failures:
0.rv_dm_stress_all_with_rand_reset.106740758
Line 230, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_WARNING @ 6752421 ps: [BDTYP] Cannot create an object of type 'rv_dm_stress_all_vseq' because it is not registered with the factory.
UVM_INFO @ 6752421 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
1.rv_dm_stress_all_with_rand_reset.3945858521
Line 230, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_WARNING @ 13207685 ps: [BDTYP] Cannot create an object of type 'rv_dm_stress_all_vseq' because it is not registered with the factory.
UVM_INFO @ 13207685 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
... and 48 more failures.
0.rv_dm_stress_all.220351990
Line 230, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all/latest/run.log
UVM_WARNING @ 0 ps: [BDTYP] Cannot create an object of type 'rv_dm_stress_all_vseq' because it is not registered with the factory.
UVM_INFO @ 0 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
1.rv_dm_stress_all.4280946420
Line 230, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all/latest/run.log
UVM_WARNING @ 0 ps: [BDTYP] Cannot create an object of type 'rv_dm_stress_all_vseq' because it is not registered with the factory.
UVM_INFO @ 0 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
... and 48 more failures.
UVM_ERROR (cip_base_vseq.sv:717) [rv_dm_common_vseq] Check failed has_outstanding_access() == * (* [*] vs * [*]) No CSR outstanding items after reset! has 5 failures:
4.rv_dm_csr_mem_rw_with_rand_reset.821127034
Line 234, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 8886250 ps: (cip_base_vseq.sv:717) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed has_outstanding_access() == 0 (1 [0x1] vs 0 [0x0]) No CSR outstanding items after reset!
UVM_INFO @ 8886250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.rv_dm_csr_mem_rw_with_rand_reset.1403009570
Line 234, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 4246802455 ps: (cip_base_vseq.sv:717) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed has_outstanding_access() == 0 (1 [0x1] vs 0 [0x0]) No CSR outstanding items after reset!
UVM_INFO @ 4246802455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
0.rv_dm_autoincr_sba_tl_access.1759884690
Line 284, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.rv_dm_autoincr_sba_tl_access.4215753778
Line 623, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: jtag_dtm_ral.dtmcs reset value: * Wrote jtag_dtm_ral.dtmcs[*]: * has 1 failures:
2.rv_dm_jtag_dtm_csr_bit_bash.3459210492
Line 231, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_jtag_dtm_csr_bit_bash/latest/run.log
UVM_ERROR @ 74382116 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (7281 [0x1c71] vs 4209 [0x1071]) Regname: jtag_dtm_ral.dtmcs reset value: 0x1071 Wrote jtag_dtm_ral.dtmcs[0]: 0
UVM_INFO @ 74382116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---