57d0a212f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rv_dm_smoke | 1.210s | 452.537us | 2 | 2 | 100.00 |
| V1 | jtag_dtm_csr_hw_reset | rv_dm_jtag_dtm_csr_hw_reset | 0.690s | 273.567us | 5 | 5 | 100.00 |
| V1 | jtag_dtm_csr_rw | rv_dm_jtag_dtm_csr_rw | 0.780s | 66.071us | 20 | 20 | 100.00 |
| V1 | jtag_dtm_csr_bit_bash | rv_dm_jtag_dtm_csr_bit_bash | 10.440s | 3.640ms | 5 | 5 | 100.00 |
| V1 | jtag_dtm_csr_aliasing | rv_dm_jtag_dtm_csr_aliasing | 1.050s | 326.852us | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_hw_reset | rv_dm_jtag_dmi_csr_hw_reset | 2.290s | 512.708us | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_rw | rv_dm_jtag_dmi_csr_rw | 2.000s | 828.311us | 20 | 20 | 100.00 |
| V1 | jtag_dmi_csr_bit_bash | rv_dm_jtag_dmi_csr_bit_bash | 2.154m | 47.908ms | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_aliasing | rv_dm_jtag_dmi_csr_aliasing | 13.380s | 11.247ms | 5 | 5 | 100.00 |
| V1 | csr_hw_reset | rv_dm_csr_hw_reset | 2.310s | 182.353us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_dm_csr_rw | 2.320s | 221.898us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_dm_csr_bit_bash | 53.020s | 2.789ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_dm_csr_aliasing | 1.165m | 14.001ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_dm_csr_mem_rw_with_rand_reset | 5.420s | 4.192ms | 14 | 20 | 70.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_dm_csr_rw | 2.320s | 221.898us | 20 | 20 | 100.00 |
| rv_dm_csr_aliasing | 1.165m | 14.001ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | rv_dm_mem_walk | 0.630s | 21.163us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rv_dm_mem_partial_access | 0.650s | 51.415us | 5 | 5 | 100.00 |
| V1 | TOTAL | 131 | 137 | 95.62 | |||
| V2 | idcode | rv_dm_smoke | 1.210s | 452.537us | 2 | 2 | 100.00 |
| V2 | jtag_dtm_hard_reset | jtag_dtm_hard_reset | 0 | 0 | -- | ||
| V2 | jtag_dtm_idle_hint | jtag_dtm_idle_hint | 0 | 0 | -- | ||
| V2 | jtag_dmi_failed_op | jtag_dmi_failed_op | 0 | 0 | -- | ||
| V2 | jtag_dmi_dm_inactive | jtag_dmi_dm_inactive | 0 | 0 | -- | ||
| V2 | sba | rv_dm_sba_tl_access | 37.890s | 12.775ms | 20 | 20 | 100.00 |
| rv_dm_delayed_resp_sba_tl_access | 27.320s | 9.545ms | 20 | 20 | 100.00 | ||
| V2 | bad_sba | rv_dm_bad_sba_tl_access | 29.720s | 10.072ms | 20 | 20 | 100.00 |
| V2 | sba_autoincrement | rv_dm_autoincr_sba_tl_access | 2.421m | 50.000ms | 18 | 20 | 90.00 |
| V2 | jtag_dmi_debug_disabled | jtag_dmi_debug_disabled | 0 | 0 | -- | ||
| V2 | sba_debug_disabled | sba_debug_disabled | 0 | 0 | -- | ||
| V2 | ndmreset_req | ndmreset_req | 0 | 0 | -- | ||
| V2 | hart_unavail | hart_unavail | 0 | 0 | -- | ||
| V2 | tap_ctrl_transitions | tap_ctrl_transitions | 0 | 0 | -- | ||
| V2 | stress_all | rv_dm_stress_all | 0.730s | 0 | 50 | 0.00 | |
| V2 | alert_test | rv_dm_alert_test | 0.800s | 143.386us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_dm_tl_errors | 5.070s | 909.761us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_dm_tl_errors | 5.070s | 909.761us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_dm_csr_hw_reset | 2.310s | 182.353us | 5 | 5 | 100.00 |
| rv_dm_csr_rw | 2.320s | 221.898us | 20 | 20 | 100.00 | ||
| rv_dm_csr_aliasing | 1.165m | 14.001ms | 5 | 5 | 100.00 | ||
| rv_dm_same_csr_outstanding | 7.570s | 1.271ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_dm_csr_hw_reset | 2.310s | 182.353us | 5 | 5 | 100.00 |
| rv_dm_csr_rw | 2.320s | 221.898us | 20 | 20 | 100.00 | ||
| rv_dm_csr_aliasing | 1.165m | 14.001ms | 5 | 5 | 100.00 | ||
| rv_dm_same_csr_outstanding | 7.570s | 1.271ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 168 | 220 | 76.36 | |||
| V2S | tl_intg_err | rv_dm_sec_cm | 1.590s | 318.501us | 5 | 5 | 100.00 |
| rv_dm_tl_intg_err | 19.720s | 2.005ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | sec_cm_bus_integrity | 0 | 0 | -- | ||
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sec_cm_lc_hw_debug_en_intersig_mubi | 0 | 0 | -- | ||
| V2S | sec_cm_dm_en_ctrl_lc_gated | sec_cm_dm_en_ctrl_lc_gated | 0 | 0 | -- | ||
| V2S | sec_cm_sba_tl_lc_gate_fsm_sparse | sec_cm_sba_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | sec_cm_mem_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
| V2S | sec_cm_exec_ctrl_mubi | sec_cm_exec_ctrl_mubi | 0 | 0 | -- | ||
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_dm_stress_all_with_rand_reset | 0.710s | 14.072us | 0 | 50 | 0.00 |
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 324 | 432 | 75.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 16 | 16 | 15 | 93.75 |
| V2 | 17 | 8 | 6 | 35.29 |
| V2S | 8 | 2 | 2 | 25.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 76.97 | 83.23 | 61.69 | 87.95 | 46.15 | 66.67 | 97.75 | 95.34 |
UVM_WARNING [BDTYP] Cannot create an object of type 'rv_dm_stress_all_vseq' because it is not registered with the factory. has 100 failures:
0.rv_dm_stress_all_with_rand_reset.110570475
Line 230, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_WARNING @ 8293236 ps: [BDTYP] Cannot create an object of type 'rv_dm_stress_all_vseq' because it is not registered with the factory.
UVM_INFO @ 8293236 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
1.rv_dm_stress_all_with_rand_reset.382623130
Line 230, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_WARNING @ 2035671 ps: [BDTYP] Cannot create an object of type 'rv_dm_stress_all_vseq' because it is not registered with the factory.
UVM_INFO @ 2035671 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
... and 48 more failures.
0.rv_dm_stress_all.4040240589
Line 230, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all/latest/run.log
UVM_WARNING @ 0 ps: [BDTYP] Cannot create an object of type 'rv_dm_stress_all_vseq' because it is not registered with the factory.
UVM_INFO @ 0 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
1.rv_dm_stress_all.4096219281
Line 230, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all/latest/run.log
UVM_WARNING @ 0 ps: [BDTYP] Cannot create an object of type 'rv_dm_stress_all_vseq' because it is not registered with the factory.
UVM_INFO @ 0 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
... and 48 more failures.
UVM_ERROR (cip_base_vseq.sv:717) [rv_dm_common_vseq] Check failed has_outstanding_access() == * (* [*] vs * [*]) No CSR outstanding items after reset! has 6 failures:
4.rv_dm_csr_mem_rw_with_rand_reset.183584292
Line 234, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 3785837 ps: (cip_base_vseq.sv:717) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed has_outstanding_access() == 0 (1 [0x1] vs 0 [0x0]) No CSR outstanding items after reset!
UVM_INFO @ 3785837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.rv_dm_csr_mem_rw_with_rand_reset.925248537
Line 234, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 12804150 ps: (cip_base_vseq.sv:717) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed has_outstanding_access() == 0 (1 [0x1] vs 0 [0x0]) No CSR outstanding items after reset!
UVM_INFO @ 12804150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
15.rv_dm_autoincr_sba_tl_access.3228924577
Line 590, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/15.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.rv_dm_autoincr_sba_tl_access.2771331723
Line 386, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/19.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---