e2dc6dd56| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rv_dm_smoke | 1.500s | 301.419us | 2 | 2 | 100.00 |
| V1 | jtag_dtm_csr_hw_reset | rv_dm_jtag_dtm_csr_hw_reset | 1.010s | 126.791us | 5 | 5 | 100.00 |
| V1 | jtag_dtm_csr_rw | rv_dm_jtag_dtm_csr_rw | 0.930s | 131.234us | 20 | 20 | 100.00 |
| V1 | jtag_dtm_csr_bit_bash | rv_dm_jtag_dtm_csr_bit_bash | 4.800s | 2.510ms | 5 | 5 | 100.00 |
| V1 | jtag_dtm_csr_aliasing | rv_dm_jtag_dtm_csr_aliasing | 0.860s | 67.752us | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_hw_reset | rv_dm_jtag_dmi_csr_hw_reset | 5.210s | 1.537ms | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_rw | rv_dm_jtag_dmi_csr_rw | 2.380s | 1.183ms | 20 | 20 | 100.00 |
| V1 | jtag_dmi_csr_bit_bash | rv_dm_jtag_dmi_csr_bit_bash | 40.270s | 41.950ms | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_aliasing | rv_dm_jtag_dmi_csr_aliasing | 26.970s | 9.289ms | 5 | 5 | 100.00 |
| V1 | csr_hw_reset | rv_dm_csr_hw_reset | 2.330s | 116.907us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_dm_csr_rw | 2.220s | 91.840us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_dm_csr_bit_bash | 1.153m | 6.416ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_dm_csr_aliasing | 1.260m | 6.643ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_dm_csr_mem_rw_with_rand_reset | 6.170s | 3.669ms | 13 | 20 | 65.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_dm_csr_rw | 2.220s | 91.840us | 20 | 20 | 100.00 |
| rv_dm_csr_aliasing | 1.260m | 6.643ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | rv_dm_mem_walk | 0.650s | 34.890us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rv_dm_mem_partial_access | 0.640s | 73.016us | 5 | 5 | 100.00 |
| V1 | TOTAL | 130 | 137 | 94.89 | |||
| V2 | idcode | rv_dm_smoke | 1.500s | 301.419us | 2 | 2 | 100.00 |
| V2 | jtag_dtm_hard_reset | jtag_dtm_hard_reset | 0 | 0 | -- | ||
| V2 | jtag_dtm_idle_hint | jtag_dtm_idle_hint | 0 | 0 | -- | ||
| V2 | jtag_dmi_failed_op | jtag_dmi_failed_op | 0 | 0 | -- | ||
| V2 | jtag_dmi_dm_inactive | jtag_dmi_dm_inactive | 0 | 0 | -- | ||
| V2 | sba | rv_dm_sba_tl_access | 21.880s | 8.521ms | 20 | 20 | 100.00 |
| rv_dm_delayed_resp_sba_tl_access | 25.790s | 8.668ms | 20 | 20 | 100.00 | ||
| V2 | bad_sba | rv_dm_bad_sba_tl_access | 23.770s | 7.342ms | 20 | 20 | 100.00 |
| V2 | sba_autoincrement | rv_dm_autoincr_sba_tl_access | 1.352m | 23.405ms | 19 | 20 | 95.00 |
| V2 | jtag_dmi_debug_disabled | jtag_dmi_debug_disabled | 0 | 0 | -- | ||
| V2 | sba_debug_disabled | sba_debug_disabled | 0 | 0 | -- | ||
| V2 | ndmreset_req | ndmreset_req | 0 | 0 | -- | ||
| V2 | hart_unavail | hart_unavail | 0 | 0 | -- | ||
| V2 | tap_ctrl_transitions | tap_ctrl_transitions | 0 | 0 | -- | ||
| V2 | stress_all | rv_dm_stress_all | 0.590s | 0 | 50 | 0.00 | |
| V2 | alert_test | rv_dm_alert_test | 0.730s | 26.562us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_dm_tl_errors | 5.940s | 245.798us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_dm_tl_errors | 5.940s | 245.798us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_dm_csr_hw_reset | 2.330s | 116.907us | 5 | 5 | 100.00 |
| rv_dm_csr_rw | 2.220s | 91.840us | 20 | 20 | 100.00 | ||
| rv_dm_csr_aliasing | 1.260m | 6.643ms | 5 | 5 | 100.00 | ||
| rv_dm_same_csr_outstanding | 9.330s | 6.680ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_dm_csr_hw_reset | 2.330s | 116.907us | 5 | 5 | 100.00 |
| rv_dm_csr_rw | 2.220s | 91.840us | 20 | 20 | 100.00 | ||
| rv_dm_csr_aliasing | 1.260m | 6.643ms | 5 | 5 | 100.00 | ||
| rv_dm_same_csr_outstanding | 9.330s | 6.680ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 169 | 220 | 76.82 | |||
| V2S | tl_intg_err | rv_dm_sec_cm | 1.240s | 456.171us | 5 | 5 | 100.00 |
| rv_dm_tl_intg_err | 19.350s | 1.178ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | sec_cm_bus_integrity | 0 | 0 | -- | ||
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sec_cm_lc_hw_debug_en_intersig_mubi | 0 | 0 | -- | ||
| V2S | sec_cm_dm_en_ctrl_lc_gated | sec_cm_dm_en_ctrl_lc_gated | 0 | 0 | -- | ||
| V2S | sec_cm_sba_tl_lc_gate_fsm_sparse | sec_cm_sba_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | sec_cm_mem_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
| V2S | sec_cm_exec_ctrl_mubi | sec_cm_exec_ctrl_mubi | 0 | 0 | -- | ||
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_dm_stress_all_with_rand_reset | 0.650s | 7.137us | 0 | 50 | 0.00 |
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 324 | 432 | 75.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 16 | 16 | 15 | 93.75 |
| V2 | 17 | 8 | 6 | 35.29 |
| V2S | 8 | 2 | 2 | 25.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 77.02 | 83.29 | 61.83 | 87.95 | 46.15 | 66.84 | 97.75 | 95.34 |
UVM_WARNING [BDTYP] Cannot create an object of type 'rv_dm_stress_all_vseq' because it is not registered with the factory. has 100 failures:
0.rv_dm_stress_all_with_rand_reset.717663364
Line 230, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_WARNING @ 13537516 ps: [BDTYP] Cannot create an object of type 'rv_dm_stress_all_vseq' because it is not registered with the factory.
UVM_INFO @ 13537516 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
1.rv_dm_stress_all_with_rand_reset.1965421451
Line 230, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_WARNING @ 7910202 ps: [BDTYP] Cannot create an object of type 'rv_dm_stress_all_vseq' because it is not registered with the factory.
UVM_INFO @ 7910202 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
... and 48 more failures.
0.rv_dm_stress_all.2985953531
Line 230, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all/latest/run.log
UVM_WARNING @ 0 ps: [BDTYP] Cannot create an object of type 'rv_dm_stress_all_vseq' because it is not registered with the factory.
UVM_INFO @ 0 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
1.rv_dm_stress_all.2346731020
Line 230, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all/latest/run.log
UVM_WARNING @ 0 ps: [BDTYP] Cannot create an object of type 'rv_dm_stress_all_vseq' because it is not registered with the factory.
UVM_INFO @ 0 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
... and 48 more failures.
UVM_ERROR (cip_base_vseq.sv:717) [rv_dm_common_vseq] Check failed has_outstanding_access() == * (* [*] vs * [*]) No CSR outstanding items after reset! has 7 failures:
1.rv_dm_csr_mem_rw_with_rand_reset.2441079518
Line 234, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 19808380 ps: (cip_base_vseq.sv:717) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed has_outstanding_access() == 0 (1 [0x1] vs 0 [0x0]) No CSR outstanding items after reset!
UVM_INFO @ 19808380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.rv_dm_csr_mem_rw_with_rand_reset.2685188048
Line 240, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 27261312 ps: (cip_base_vseq.sv:717) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed has_outstanding_access() == 0 (1 [0x1] vs 0 [0x0]) No CSR outstanding items after reset!
UVM_INFO @ 27261312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_ERROR (jtag_rv_debugger.sv:1108) [debugger] Check failed is_busy == * (* [*] vs * [*]) has 1 failures:
12.rv_dm_autoincr_sba_tl_access.3880862058
Line 239, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 2335300370 ps: (jtag_rv_debugger.sv:1108) [debugger] Check failed is_busy == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 2335300370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---