Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
87.73 92.73 78.40 89.36 78.21 82.30 97.75 95.34


Total test records in report: 358
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html
T102 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1547259525 Feb 04 12:54:10 PM PST 24 Feb 04 12:54:12 PM PST 24 417220643 ps
T118 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.884339049 Feb 04 12:54:34 PM PST 24 Feb 04 12:54:43 PM PST 24 85305981 ps
T269 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.1985653352 Feb 04 12:54:15 PM PST 24 Feb 04 12:54:19 PM PST 24 385947013 ps
T270 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.4029733149 Feb 04 12:54:44 PM PST 24 Feb 04 12:54:48 PM PST 24 60232074 ps
T271 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.344108196 Feb 04 12:54:33 PM PST 24 Feb 04 12:54:36 PM PST 24 33120358 ps
T272 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.213359653 Feb 04 12:54:55 PM PST 24 Feb 04 12:54:57 PM PST 24 123866839 ps
T143 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.1641405003 Feb 04 12:54:39 PM PST 24 Feb 04 12:54:52 PM PST 24 251064894 ps
T273 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.1398022776 Feb 04 12:54:38 PM PST 24 Feb 04 12:54:47 PM PST 24 155282801 ps
T274 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.1278352021 Feb 04 12:54:37 PM PST 24 Feb 04 12:54:44 PM PST 24 193398532 ps
T275 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.3296352092 Feb 04 12:54:03 PM PST 24 Feb 04 12:54:05 PM PST 24 50293878 ps
T276 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.3601455747 Feb 04 12:53:54 PM PST 24 Feb 04 12:54:00 PM PST 24 186262039 ps
T277 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.1186598500 Feb 04 12:54:35 PM PST 24 Feb 04 12:54:43 PM PST 24 39793649 ps
T132 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.2336677521 Feb 04 12:54:53 PM PST 24 Feb 04 12:54:56 PM PST 24 129353701 ps
T278 /workspace/coverage/cover_reg_top/23.rv_dm_tap_fsm_rand_reset.3459981815 Feb 04 12:54:45 PM PST 24 Feb 04 12:54:57 PM PST 24 4955159536 ps
T279 /workspace/coverage/cover_reg_top/35.rv_dm_tap_fsm_rand_reset.1153911 Feb 04 12:54:58 PM PST 24 Feb 04 12:55:11 PM PST 24 5297548550 ps
T280 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3266809723 Feb 04 12:54:33 PM PST 24 Feb 04 12:54:37 PM PST 24 346463682 ps
T281 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.218006343 Feb 04 12:55:00 PM PST 24 Feb 04 12:55:09 PM PST 24 76930850 ps
T282 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3793500306 Feb 04 12:54:02 PM PST 24 Feb 04 12:54:04 PM PST 24 178969594 ps
T283 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.4121312643 Feb 04 12:54:13 PM PST 24 Feb 04 12:54:14 PM PST 24 29431569 ps
T112 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2247446380 Feb 04 12:54:53 PM PST 24 Feb 04 12:55:01 PM PST 24 1130980684 ps
T284 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1185556763 Feb 04 12:54:20 PM PST 24 Feb 04 12:54:31 PM PST 24 136508690 ps
T285 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.145230555 Feb 04 12:54:40 PM PST 24 Feb 04 12:54:49 PM PST 24 2603032061 ps
T286 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1313384226 Feb 04 12:54:21 PM PST 24 Feb 04 12:54:30 PM PST 24 830077590 ps
T287 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1330860951 Feb 04 12:54:35 PM PST 24 Feb 04 12:54:45 PM PST 24 708786839 ps
T288 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.3994088243 Feb 04 12:54:38 PM PST 24 Feb 04 12:54:44 PM PST 24 43480507 ps
T136 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3345924799 Feb 04 12:54:32 PM PST 24 Feb 04 12:54:49 PM PST 24 445126722 ps
T289 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2086800750 Feb 04 12:54:02 PM PST 24 Feb 04 12:54:06 PM PST 24 959208049 ps
T290 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3301365669 Feb 04 12:54:35 PM PST 24 Feb 04 12:54:48 PM PST 24 251323476 ps
T135 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.45417879 Feb 04 12:54:35 PM PST 24 Feb 04 12:55:02 PM PST 24 6837586942 ps
T291 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1511320862 Feb 04 12:54:19 PM PST 24 Feb 04 12:54:45 PM PST 24 2221866772 ps
T292 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.2246001127 Feb 04 12:54:39 PM PST 24 Feb 04 12:54:45 PM PST 24 716265113 ps
T293 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1560779550 Feb 04 12:54:50 PM PST 24 Feb 04 12:55:07 PM PST 24 753888600 ps
T119 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.3815792981 Feb 04 12:54:39 PM PST 24 Feb 04 12:54:44 PM PST 24 98511365 ps
T294 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.3937812430 Feb 04 12:54:37 PM PST 24 Feb 04 12:54:45 PM PST 24 176060149 ps
T295 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1466872469 Feb 04 12:54:07 PM PST 24 Feb 04 12:54:09 PM PST 24 584791611 ps
T120 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.4211846197 Feb 04 12:54:35 PM PST 24 Feb 04 12:54:44 PM PST 24 38712292 ps
T121 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.4099342334 Feb 04 12:54:35 PM PST 24 Feb 04 12:54:43 PM PST 24 94504366 ps
T296 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2064794668 Feb 04 12:54:42 PM PST 24 Feb 04 12:54:48 PM PST 24 189785105 ps
T297 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.4073947538 Feb 04 12:54:43 PM PST 24 Feb 04 12:54:51 PM PST 24 141801968 ps
T298 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3881661871 Feb 04 12:54:40 PM PST 24 Feb 04 12:54:47 PM PST 24 166645513 ps
T140 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.4092159674 Feb 04 12:54:31 PM PST 24 Feb 04 12:54:42 PM PST 24 451300672 ps
T299 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.2659011529 Feb 04 12:54:18 PM PST 24 Feb 04 12:54:28 PM PST 24 6132676460 ps
T300 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.2316339200 Feb 04 12:54:04 PM PST 24 Feb 04 12:54:37 PM PST 24 2419219083 ps
T301 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.456981676 Feb 04 12:54:16 PM PST 24 Feb 04 12:55:14 PM PST 24 34111831925 ps
T302 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.1397432301 Feb 04 12:54:35 PM PST 24 Feb 04 12:54:45 PM PST 24 551452714 ps
T127 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.2146743403 Feb 04 12:54:34 PM PST 24 Feb 04 12:54:48 PM PST 24 416805371 ps
T303 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.403045208 Feb 04 12:54:35 PM PST 24 Feb 04 12:54:42 PM PST 24 120319116 ps
T304 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.915416994 Feb 04 12:54:04 PM PST 24 Feb 04 12:54:06 PM PST 24 219822065 ps
T141 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.1305087913 Feb 04 12:54:12 PM PST 24 Feb 04 12:54:31 PM PST 24 985243672 ps
T305 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.3915290629 Feb 04 12:54:35 PM PST 24 Feb 04 12:54:44 PM PST 24 169358015 ps
T306 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.845514313 Feb 04 12:54:16 PM PST 24 Feb 04 12:54:19 PM PST 24 26390578 ps
T307 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.212563860 Feb 04 12:54:40 PM PST 24 Feb 04 12:54:44 PM PST 24 217893522 ps
T308 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.1271163262 Feb 04 12:54:44 PM PST 24 Feb 04 12:54:50 PM PST 24 46395300 ps
T309 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1820886903 Feb 04 12:54:44 PM PST 24 Feb 04 12:55:03 PM PST 24 1389371785 ps
T310 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.2441322135 Feb 04 12:54:34 PM PST 24 Feb 04 12:54:45 PM PST 24 292442869 ps
T123 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.3454522315 Feb 04 12:54:31 PM PST 24 Feb 04 12:54:36 PM PST 24 165445260 ps
T311 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3502432996 Feb 04 12:54:48 PM PST 24 Feb 04 12:54:54 PM PST 24 311751845 ps
T312 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3118458925 Feb 04 12:54:15 PM PST 24 Feb 04 12:54:17 PM PST 24 127996230 ps
T313 /workspace/coverage/cover_reg_top/36.rv_dm_tap_fsm_rand_reset.1623134825 Feb 04 12:54:58 PM PST 24 Feb 04 12:55:13 PM PST 24 5887883569 ps
T137 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2484231955 Feb 04 12:54:58 PM PST 24 Feb 04 12:55:10 PM PST 24 536578074 ps
T314 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.2588676244 Feb 04 12:53:53 PM PST 24 Feb 04 12:54:01 PM PST 24 176360298 ps
T315 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.3068261383 Feb 04 12:54:53 PM PST 24 Feb 04 12:54:56 PM PST 24 749865554 ps
T316 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.2563852406 Feb 04 12:54:37 PM PST 24 Feb 04 12:54:44 PM PST 24 57338976 ps
T317 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.778233417 Feb 04 12:54:40 PM PST 24 Feb 04 12:54:51 PM PST 24 505963909 ps
T318 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2071245713 Feb 04 12:54:48 PM PST 24 Feb 04 12:54:52 PM PST 24 113134204 ps
T319 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.1032968546 Feb 04 12:54:44 PM PST 24 Feb 04 12:54:52 PM PST 24 3382474412 ps
T320 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.4056365520 Feb 04 12:54:30 PM PST 24 Feb 04 12:55:52 PM PST 24 26603712420 ps
T321 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.1655866950 Feb 04 12:54:31 PM PST 24 Feb 04 12:55:44 PM PST 24 14550469454 ps
T322 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1447936212 Feb 04 12:54:43 PM PST 24 Feb 04 12:54:57 PM PST 24 615035847 ps
T323 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.1163568818 Feb 04 12:54:39 PM PST 24 Feb 04 12:54:47 PM PST 24 107613824 ps
T324 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1151908543 Feb 04 12:54:44 PM PST 24 Feb 04 12:54:54 PM PST 24 167679283 ps
T325 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.351367572 Feb 04 12:54:54 PM PST 24 Feb 04 12:54:57 PM PST 24 61633208 ps
T326 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2923874716 Feb 04 12:54:32 PM PST 24 Feb 04 12:54:39 PM PST 24 2316203503 ps
T327 /workspace/coverage/cover_reg_top/37.rv_dm_tap_fsm_rand_reset.2165881833 Feb 04 12:54:45 PM PST 24 Feb 04 12:54:57 PM PST 24 9337509830 ps
T328 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.3255938741 Feb 04 12:54:20 PM PST 24 Feb 04 12:54:27 PM PST 24 301984237 ps
T329 /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.385107863 Feb 04 12:54:29 PM PST 24 Feb 04 12:54:40 PM PST 24 8863986983 ps
T330 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.415652243 Feb 04 12:54:12 PM PST 24 Feb 04 12:54:13 PM PST 24 107972830 ps
T331 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.2511755981 Feb 04 12:54:34 PM PST 24 Feb 04 12:54:41 PM PST 24 130240387 ps
T332 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1949838295 Feb 04 12:54:35 PM PST 24 Feb 04 12:54:43 PM PST 24 27674940 ps
T333 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3203042087 Feb 04 12:54:02 PM PST 24 Feb 04 12:54:04 PM PST 24 67305586 ps
T334 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.2316449041 Feb 04 12:54:12 PM PST 24 Feb 04 12:54:13 PM PST 24 117159662 ps
T138 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.527968295 Feb 04 12:54:20 PM PST 24 Feb 04 12:54:45 PM PST 24 1666434342 ps
T335 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.4070789240 Feb 04 12:54:37 PM PST 24 Feb 04 12:54:45 PM PST 24 998138790 ps
T336 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.437889482 Feb 04 12:54:43 PM PST 24 Feb 04 12:54:51 PM PST 24 224243894 ps
T337 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.3096509003 Feb 04 12:54:35 PM PST 24 Feb 04 12:54:56 PM PST 24 9948705422 ps
T338 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1698603097 Feb 04 12:54:35 PM PST 24 Feb 04 12:54:42 PM PST 24 34901145 ps
T103 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.1756216743 Feb 04 12:54:15 PM PST 24 Feb 04 12:54:20 PM PST 24 2737140708 ps
T339 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.312801204 Feb 04 12:54:11 PM PST 24 Feb 04 12:54:13 PM PST 24 108150409 ps
T340 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2750229771 Feb 04 12:54:47 PM PST 24 Feb 04 12:54:51 PM PST 24 54829798 ps
T341 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1580645449 Feb 04 12:54:01 PM PST 24 Feb 04 12:54:04 PM PST 24 239962236 ps
T342 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.802688339 Feb 04 12:54:45 PM PST 24 Feb 04 12:54:49 PM PST 24 41366564 ps
T343 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2042723773 Feb 04 12:54:35 PM PST 24 Feb 04 12:54:43 PM PST 24 155688742 ps
T344 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.239356202 Feb 04 12:54:37 PM PST 24 Feb 04 12:54:44 PM PST 24 28950220 ps
T345 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.1072204792 Feb 04 12:55:00 PM PST 24 Feb 04 12:55:06 PM PST 24 696353532 ps
T346 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.917729907 Feb 04 12:54:21 PM PST 24 Feb 04 12:54:28 PM PST 24 494006656 ps
T347 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.203739639 Feb 04 12:54:55 PM PST 24 Feb 04 12:55:01 PM PST 24 1232464887 ps
T348 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.514892824 Feb 04 12:54:35 PM PST 24 Feb 04 12:54:53 PM PST 24 5650141278 ps
T349 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.3681825666 Feb 04 12:54:34 PM PST 24 Feb 04 12:54:43 PM PST 24 526834396 ps
T142 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.322569716 Feb 04 12:54:53 PM PST 24 Feb 04 12:55:13 PM PST 24 1105532747 ps
T350 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.3226461349 Feb 04 12:54:03 PM PST 24 Feb 04 12:54:31 PM PST 24 716394313 ps
T351 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2296392000 Feb 04 12:54:31 PM PST 24 Feb 04 12:54:37 PM PST 24 188054318 ps
T352 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2535949414 Feb 04 12:54:58 PM PST 24 Feb 04 12:55:03 PM PST 24 988289308 ps
T353 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.3828197243 Feb 04 12:54:20 PM PST 24 Feb 04 12:54:27 PM PST 24 191206098 ps
T354 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.271545788 Feb 04 12:54:35 PM PST 24 Feb 04 12:54:45 PM PST 24 192705340 ps
T355 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.3479598983 Feb 04 12:54:12 PM PST 24 Feb 04 12:55:25 PM PST 24 7553504337 ps
T356 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.4277743850 Feb 04 12:54:34 PM PST 24 Feb 04 12:54:45 PM PST 24 1680648146 ps
T357 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.301708931 Feb 04 12:54:02 PM PST 24 Feb 04 12:54:04 PM PST 24 45243001 ps
T358 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.2317250387 Feb 04 12:54:35 PM PST 24 Feb 04 12:54:42 PM PST 24 26230835 ps

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.1395795095
Short name T1
Test name
Test status
Simulation time 7962636502 ps
CPU time 7.72 seconds
Started Feb 04 12:55:56 PM PST 24
Finished Feb 04 12:56:06 PM PST 24
Peak memory 204168 kb
Host smart-ec2df46f-631a-464a-ad7f-6f0ded91381d
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1395795095 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t
l_access.1395795095
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/22.rv_dm_stress_all.2832575979
Short name T9
Test name
Test status
Simulation time 2853438544 ps
CPU time 9.37 seconds
Started Feb 04 12:56:30 PM PST 24
Finished Feb 04 12:56:44 PM PST 24
Peak memory 204028 kb
Host smart-aa88d8c0-58c9-4944-88ff-ec3a39e32030
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832575979 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.2832575979
Directory /workspace/22.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.1653208212
Short name T81
Test name
Test status
Simulation time 7111358189 ps
CPU time 12.41 seconds
Started Feb 04 12:54:38 PM PST 24
Finished Feb 04 12:54:56 PM PST 24
Peak memory 219520 kb
Host smart-71a879af-374f-40a6-9edc-329fc40f1a07
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653208212 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.1653208212
Directory /workspace/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.1404247812
Short name T46
Test name
Test status
Simulation time 62194058 ps
CPU time 0.62 seconds
Started Feb 04 12:56:00 PM PST 24
Finished Feb 04 12:56:03 PM PST 24
Peak memory 203648 kb
Host smart-8e0f718c-76b9-4669-8286-bd87bc3a950a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404247812 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.1404247812
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3708226444
Short name T39
Test name
Test status
Simulation time 3243740841 ps
CPU time 18.43 seconds
Started Feb 04 12:54:38 PM PST 24
Finished Feb 04 12:55:02 PM PST 24
Peak memory 215820 kb
Host smart-ff7a2a5f-a361-4dc0-9d27-a17e5acbb376
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708226444 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.3
708226444
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.4217646986
Short name T131
Test name
Test status
Simulation time 7005816789 ps
CPU time 27.4 seconds
Started Feb 04 12:56:04 PM PST 24
Finished Feb 04 12:56:33 PM PST 24
Peak memory 204060 kb
Host smart-b4e8652f-5d3c-4650-b1cd-b84a8a0d627f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217646986 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.4217646986
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/28.rv_dm_stress_all.4266378709
Short name T62
Test name
Test status
Simulation time 4588755536 ps
CPU time 3.4 seconds
Started Feb 04 12:56:26 PM PST 24
Finished Feb 04 12:56:36 PM PST 24
Peak memory 204176 kb
Host smart-4b294809-1ac2-46a9-93db-ed31c1a32209
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266378709 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.4266378709
Directory /workspace/28.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.2997544619
Short name T109
Test name
Test status
Simulation time 4092201203 ps
CPU time 73.13 seconds
Started Feb 04 12:54:03 PM PST 24
Finished Feb 04 12:55:17 PM PST 24
Peak memory 203680 kb
Host smart-e9fe72db-3518-4460-b4b3-c74d4396315c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997544619 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.2997544619
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/default/10.rv_dm_stress_all.2853365314
Short name T21
Test name
Test status
Simulation time 401804664 ps
CPU time 1.94 seconds
Started Feb 04 12:56:23 PM PST 24
Finished Feb 04 12:56:27 PM PST 24
Peak memory 203948 kb
Host smart-dfd0991f-38c1-4a63-b0d7-1fea7140a628
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853365314 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.2853365314
Directory /workspace/10.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tap_fsm_rand_reset.2233497554
Short name T42
Test name
Test status
Simulation time 5901525489 ps
CPU time 20.45 seconds
Started Feb 04 12:54:38 PM PST 24
Finished Feb 04 12:55:04 PM PST 24
Peak memory 211916 kb
Host smart-79def329-fb0a-49d4-a30d-f438b50d52e9
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233497554 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rv_dm_tap_fsm_rand_reset.2233497554
Directory /workspace/12.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1295611126
Short name T74
Test name
Test status
Simulation time 2484491228 ps
CPU time 3.64 seconds
Started Feb 04 12:54:03 PM PST 24
Finished Feb 04 12:54:08 PM PST 24
Peak memory 211996 kb
Host smart-0f3900ac-2be4-473f-a551-5aca4d660346
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295611126 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.1295611126
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.3390811486
Short name T83
Test name
Test status
Simulation time 250852886 ps
CPU time 4.23 seconds
Started Feb 04 12:54:41 PM PST 24
Finished Feb 04 12:54:49 PM PST 24
Peak memory 203608 kb
Host smart-ff779300-09fd-4b83-aa46-638e38a87900
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390811486 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.3390811486
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.1305087913
Short name T141
Test name
Test status
Simulation time 985243672 ps
CPU time 18.24 seconds
Started Feb 04 12:54:12 PM PST 24
Finished Feb 04 12:54:31 PM PST 24
Peak memory 214816 kb
Host smart-1ccc2f4d-dbab-4bfa-b599-6772eb6d37e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305087913 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.1305087913
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.1486503100
Short name T7
Test name
Test status
Simulation time 244457111 ps
CPU time 0.83 seconds
Started Feb 04 12:56:01 PM PST 24
Finished Feb 04 12:56:04 PM PST 24
Peak memory 203648 kb
Host smart-9729561c-8f48-441c-a199-f616c228ce66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486503100 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.1486503100
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.2119526354
Short name T66
Test name
Test status
Simulation time 241992444 ps
CPU time 0.94 seconds
Started Feb 04 12:56:04 PM PST 24
Finished Feb 04 12:56:07 PM PST 24
Peak memory 219592 kb
Host smart-85a6de9d-6c44-4c97-886b-d95447bbf15f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119526354 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.2119526354
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.4012949781
Short name T72
Test name
Test status
Simulation time 36446674 ps
CPU time 0.72 seconds
Started Feb 04 12:56:55 PM PST 24
Finished Feb 04 12:56:58 PM PST 24
Peak memory 203668 kb
Host smart-cc0beab1-bc76-49b2-8ea7-31a32379795d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012949781 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.4012949781
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1185556763
Short name T284
Test name
Test status
Simulation time 136508690 ps
CPU time 4.6 seconds
Started Feb 04 12:54:20 PM PST 24
Finished Feb 04 12:54:31 PM PST 24
Peak memory 211844 kb
Host smart-6ff03b8c-2c2e-4fd1-b7e6-1d1b4e92456a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185556763 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.1185556763
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.321628339
Short name T53
Test name
Test status
Simulation time 76826836 ps
CPU time 3.28 seconds
Started Feb 04 12:54:29 PM PST 24
Finished Feb 04 12:54:35 PM PST 24
Peak memory 203568 kb
Host smart-d257d351-2e3b-41d5-bd3e-00aec87186ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321628339 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_c
sr_outstanding.321628339
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.2798664933
Short name T6
Test name
Test status
Simulation time 1055798558 ps
CPU time 3.98 seconds
Started Feb 04 12:55:54 PM PST 24
Finished Feb 04 12:56:00 PM PST 24
Peak memory 203928 kb
Host smart-8d426831-0d0e-4559-9031-667d24c5652e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798664933 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.2798664933
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.45417879
Short name T135
Test name
Test status
Simulation time 6837586942 ps
CPU time 20.5 seconds
Started Feb 04 12:54:35 PM PST 24
Finished Feb 04 12:55:02 PM PST 24
Peak memory 216636 kb
Host smart-7e69a84e-1d6e-4e16-bdc1-dd99922190e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45417879 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.45417879
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.106095482
Short name T65
Test name
Test status
Simulation time 13147165254 ps
CPU time 25.24 seconds
Started Feb 04 12:56:33 PM PST 24
Finished Feb 04 12:57:01 PM PST 24
Peak memory 203964 kb
Host smart-d0cf0a60-23a7-4d3a-9e19-b45f89a0d969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106095482 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.106095482
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.3848613596
Short name T98
Test name
Test status
Simulation time 3020489574 ps
CPU time 9.78 seconds
Started Feb 04 12:54:01 PM PST 24
Finished Feb 04 12:54:13 PM PST 24
Peak memory 203596 kb
Host smart-4cca1ff3-68bc-4b72-b5b7-d5474461d872
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848613596 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.3848613596
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.527968295
Short name T138
Test name
Test status
Simulation time 1666434342 ps
CPU time 18.92 seconds
Started Feb 04 12:54:20 PM PST 24
Finished Feb 04 12:54:45 PM PST 24
Peak memory 214784 kb
Host smart-174b483d-84dd-4dab-9d2c-470a6b171de2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527968295 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.527968295
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2369505617
Short name T101
Test name
Test status
Simulation time 655662986 ps
CPU time 1.81 seconds
Started Feb 04 12:54:03 PM PST 24
Finished Feb 04 12:54:06 PM PST 24
Peak memory 203532 kb
Host smart-2405090e-547d-4c45-9fbd-ff70d024cd85
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369505617 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.2369505617
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.2654341951
Short name T15
Test name
Test status
Simulation time 3906802576 ps
CPU time 9.24 seconds
Started Feb 04 12:56:00 PM PST 24
Finished Feb 04 12:56:12 PM PST 24
Peak memory 203956 kb
Host smart-3594bb97-cfb2-458d-914c-f7f6b1fefb61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654341951 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.2654341951
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.3712065618
Short name T26
Test name
Test status
Simulation time 90911041 ps
CPU time 0.74 seconds
Started Feb 04 12:55:52 PM PST 24
Finished Feb 04 12:55:56 PM PST 24
Peak memory 203596 kb
Host smart-818796b0-7077-4c8b-896e-4cc872770d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712065618 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.3712065618
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.3226461349
Short name T350
Test name
Test status
Simulation time 716394313 ps
CPU time 27.03 seconds
Started Feb 04 12:54:03 PM PST 24
Finished Feb 04 12:54:31 PM PST 24
Peak memory 203360 kb
Host smart-33fa38b2-49b5-4663-aa66-90532b6d628a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226461349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.3226461349
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.2588676244
Short name T314
Test name
Test status
Simulation time 176360298 ps
CPU time 2.07 seconds
Started Feb 04 12:53:53 PM PST 24
Finished Feb 04 12:54:01 PM PST 24
Peak memory 203588 kb
Host smart-01d27e30-887b-4b1f-8005-563f5481c66e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588676244 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.2588676244
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.312801204
Short name T339
Test name
Test status
Simulation time 108150409 ps
CPU time 1.39 seconds
Started Feb 04 12:54:11 PM PST 24
Finished Feb 04 12:54:13 PM PST 24
Peak memory 203540 kb
Host smart-910e6eca-0abd-471a-bee1-b377d00f6b98
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312801204 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.312801204
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.2659011529
Short name T299
Test name
Test status
Simulation time 6132676460 ps
CPU time 8.71 seconds
Started Feb 04 12:54:18 PM PST 24
Finished Feb 04 12:54:28 PM PST 24
Peak memory 203600 kb
Host smart-ba35fe84-4d8c-4e49-af68-525e63d1e6c1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659011529 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.2659011529
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1722651357
Short name T245
Test name
Test status
Simulation time 47534432795 ps
CPU time 143.17 seconds
Started Feb 04 12:54:02 PM PST 24
Finished Feb 04 12:56:26 PM PST 24
Peak memory 203468 kb
Host smart-42aaa02f-0249-4dbf-a142-61da1c68516c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722651357 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_bit_bash.1722651357
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3793500306
Short name T282
Test name
Test status
Simulation time 178969594 ps
CPU time 1.02 seconds
Started Feb 04 12:54:02 PM PST 24
Finished Feb 04 12:54:04 PM PST 24
Peak memory 203320 kb
Host smart-2d103d55-ce1b-4600-8feb-34766b787455
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793500306 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.3
793500306
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3203042087
Short name T333
Test name
Test status
Simulation time 67305586 ps
CPU time 0.85 seconds
Started Feb 04 12:54:02 PM PST 24
Finished Feb 04 12:54:04 PM PST 24
Peak memory 203324 kb
Host smart-16b2eb30-2419-43bf-82b7-a99b1660871f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203042087 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.3203042087
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.1122643953
Short name T268
Test name
Test status
Simulation time 38590138 ps
CPU time 0.72 seconds
Started Feb 04 12:54:02 PM PST 24
Finished Feb 04 12:54:04 PM PST 24
Peak memory 203172 kb
Host smart-68407d4b-cef2-4554-8ea6-da128d6c8498
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122643953 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.1122643953
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1580645449
Short name T341
Test name
Test status
Simulation time 239962236 ps
CPU time 0.66 seconds
Started Feb 04 12:54:01 PM PST 24
Finished Feb 04 12:54:04 PM PST 24
Peak memory 203328 kb
Host smart-2c9034c7-de0d-419c-ace3-a5d0b7dc8a30
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580645449 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.1
580645449
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.3296352092
Short name T275
Test name
Test status
Simulation time 50293878 ps
CPU time 0.65 seconds
Started Feb 04 12:54:03 PM PST 24
Finished Feb 04 12:54:05 PM PST 24
Peak memory 203248 kb
Host smart-5a971817-d982-498e-b30e-c4800bf51395
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296352092 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.3296352092
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.3625095090
Short name T257
Test name
Test status
Simulation time 37852812 ps
CPU time 0.66 seconds
Started Feb 04 12:54:09 PM PST 24
Finished Feb 04 12:54:10 PM PST 24
Peak memory 203328 kb
Host smart-46a31370-9ebe-4763-8c8d-9a35630eae76
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625095090 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.3625095090
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1966591364
Short name T54
Test name
Test status
Simulation time 773178889 ps
CPU time 4.53 seconds
Started Feb 04 12:54:13 PM PST 24
Finished Feb 04 12:54:19 PM PST 24
Peak memory 203424 kb
Host smart-d5ddb1a6-fd03-4a01-911c-c1d1eca43ddf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966591364 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.1966591364
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.4231894909
Short name T84
Test name
Test status
Simulation time 247527600 ps
CPU time 3.01 seconds
Started Feb 04 12:54:02 PM PST 24
Finished Feb 04 12:54:06 PM PST 24
Peak memory 203600 kb
Host smart-da9d3652-6866-4e19-b492-e7ab1a6980ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231894909 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.4231894909
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3952930917
Short name T47
Test name
Test status
Simulation time 854761765 ps
CPU time 10.12 seconds
Started Feb 04 12:53:50 PM PST 24
Finished Feb 04 12:54:02 PM PST 24
Peak memory 211868 kb
Host smart-c071e31e-d29f-42ee-aa77-ee02c5b7e9d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952930917 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.3952930917
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.2316339200
Short name T300
Test name
Test status
Simulation time 2419219083 ps
CPU time 31.5 seconds
Started Feb 04 12:54:04 PM PST 24
Finished Feb 04 12:54:37 PM PST 24
Peak memory 202488 kb
Host smart-b3acf174-64a6-4673-ad51-32422c699c63
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316339200 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.2316339200
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2362822397
Short name T93
Test name
Test status
Simulation time 2805302595 ps
CPU time 28.14 seconds
Started Feb 04 12:54:14 PM PST 24
Finished Feb 04 12:54:44 PM PST 24
Peak memory 203548 kb
Host smart-b7064b3d-a7f2-4321-a24a-239caf6da3df
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362822397 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.2362822397
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.1364345429
Short name T92
Test name
Test status
Simulation time 361423367 ps
CPU time 1.54 seconds
Started Feb 04 12:54:17 PM PST 24
Finished Feb 04 12:54:21 PM PST 24
Peak memory 203480 kb
Host smart-c9993d65-ed3f-4d62-9463-5f2b309ac45b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364345429 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.1364345429
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.3828197243
Short name T353
Test name
Test status
Simulation time 191206098 ps
CPU time 1.41 seconds
Started Feb 04 12:54:20 PM PST 24
Finished Feb 04 12:54:27 PM PST 24
Peak memory 211740 kb
Host smart-1bb2d3c9-4708-4de5-9373-934a316cbb21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828197243 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.3828197243
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.3673652530
Short name T116
Test name
Test status
Simulation time 11416787057 ps
CPU time 39.53 seconds
Started Feb 04 12:54:04 PM PST 24
Finished Feb 04 12:54:45 PM PST 24
Peak memory 202584 kb
Host smart-4bbf4f4b-d1d4-4c24-9e9a-a43f12638cf4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673652530 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.3673652530
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.391212081
Short name T248
Test name
Test status
Simulation time 37648367251 ps
CPU time 85.18 seconds
Started Feb 04 12:54:16 PM PST 24
Finished Feb 04 12:55:42 PM PST 24
Peak memory 203320 kb
Host smart-aacb40b6-9dfb-4494-b8de-ef4bf1259b34
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391212081 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr
_bit_bash.391212081
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1547259525
Short name T102
Test name
Test status
Simulation time 417220643 ps
CPU time 1.58 seconds
Started Feb 04 12:54:10 PM PST 24
Finished Feb 04 12:54:12 PM PST 24
Peak memory 203464 kb
Host smart-07a33c6c-5dbc-4651-809f-4cf1407b34dc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547259525 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.1547259525
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1466872469
Short name T295
Test name
Test status
Simulation time 584791611 ps
CPU time 1.28 seconds
Started Feb 04 12:54:07 PM PST 24
Finished Feb 04 12:54:09 PM PST 24
Peak memory 203544 kb
Host smart-60e41dbd-25b5-49e0-8e2d-454a805b32aa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466872469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.1
466872469
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.915416994
Short name T304
Test name
Test status
Simulation time 219822065 ps
CPU time 0.81 seconds
Started Feb 04 12:54:04 PM PST 24
Finished Feb 04 12:54:06 PM PST 24
Peak memory 203088 kb
Host smart-2857f863-e683-436f-a03b-f4b8c9166354
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915416994 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_aliasing.915416994
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2086800750
Short name T289
Test name
Test status
Simulation time 959208049 ps
CPU time 2.61 seconds
Started Feb 04 12:54:02 PM PST 24
Finished Feb 04 12:54:06 PM PST 24
Peak memory 203340 kb
Host smart-e41b283d-3e0e-4910-a2ec-795a3bff4bee
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086800750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.2086800750
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.3601455747
Short name T276
Test name
Test status
Simulation time 186262039 ps
CPU time 0.87 seconds
Started Feb 04 12:53:54 PM PST 24
Finished Feb 04 12:54:00 PM PST 24
Peak memory 203316 kb
Host smart-aa5ebb29-78ef-4dd0-9e28-d756baada777
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601455747 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.3601455747
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.301708931
Short name T357
Test name
Test status
Simulation time 45243001 ps
CPU time 0.75 seconds
Started Feb 04 12:54:02 PM PST 24
Finished Feb 04 12:54:04 PM PST 24
Peak memory 203188 kb
Host smart-6ffe18b3-ce4d-4dfe-8df9-02cf085211ff
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301708931 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.301708931
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3712526414
Short name T253
Test name
Test status
Simulation time 25279683 ps
CPU time 0.72 seconds
Started Feb 04 12:54:13 PM PST 24
Finished Feb 04 12:54:15 PM PST 24
Peak memory 203388 kb
Host smart-bb47caae-3398-4213-a37d-ca66b735353e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712526414 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.3712526414
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.845514313
Short name T306
Test name
Test status
Simulation time 26390578 ps
CPU time 0.64 seconds
Started Feb 04 12:54:16 PM PST 24
Finished Feb 04 12:54:19 PM PST 24
Peak memory 203248 kb
Host smart-ecf89bb5-9d39-47af-b32b-c903241108fe
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845514313 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.845514313
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.145230555
Short name T285
Test name
Test status
Simulation time 2603032061 ps
CPU time 5.28 seconds
Started Feb 04 12:54:40 PM PST 24
Finished Feb 04 12:54:49 PM PST 24
Peak memory 214064 kb
Host smart-04fe046e-f4da-4d66-b65f-ed36a1a845ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145230555 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.145230555
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.3915290629
Short name T305
Test name
Test status
Simulation time 169358015 ps
CPU time 2.34 seconds
Started Feb 04 12:54:35 PM PST 24
Finished Feb 04 12:54:44 PM PST 24
Peak memory 211740 kb
Host smart-78fa8626-62cd-448a-8be8-42e9d2f26d36
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915290629 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.3915290629
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2064794668
Short name T296
Test name
Test status
Simulation time 189785105 ps
CPU time 1.32 seconds
Started Feb 04 12:54:42 PM PST 24
Finished Feb 04 12:54:48 PM PST 24
Peak memory 203388 kb
Host smart-03b1a965-a72a-40d5-a297-d34625709bed
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064794668 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
2064794668
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.4029733149
Short name T270
Test name
Test status
Simulation time 60232074 ps
CPU time 0.73 seconds
Started Feb 04 12:54:44 PM PST 24
Finished Feb 04 12:54:48 PM PST 24
Peak memory 203332 kb
Host smart-25205bf5-3f2b-4ef8-ad5b-bacddf69e720
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029733149 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
4029733149
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.1876667218
Short name T125
Test name
Test status
Simulation time 561969376 ps
CPU time 7.73 seconds
Started Feb 04 12:54:34 PM PST 24
Finished Feb 04 12:54:43 PM PST 24
Peak memory 203652 kb
Host smart-8c7e4316-9b6a-4bdf-bb5e-efc26245a2cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876667218 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.1876667218
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3301365669
Short name T290
Test name
Test status
Simulation time 251323476 ps
CPU time 5.63 seconds
Started Feb 04 12:54:35 PM PST 24
Finished Feb 04 12:54:48 PM PST 24
Peak memory 211904 kb
Host smart-872fe0d3-9c4d-4971-ada1-58b3c7909e1b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301365669 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.3301365669
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1447936212
Short name T322
Test name
Test status
Simulation time 615035847 ps
CPU time 10.15 seconds
Started Feb 04 12:54:43 PM PST 24
Finished Feb 04 12:54:57 PM PST 24
Peak memory 212028 kb
Host smart-9eef4b42-8547-465b-9018-e4a8c676b7d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447936212 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.1
447936212
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3881661871
Short name T298
Test name
Test status
Simulation time 166645513 ps
CPU time 3.13 seconds
Started Feb 04 12:54:40 PM PST 24
Finished Feb 04 12:54:47 PM PST 24
Peak memory 215260 kb
Host smart-6baacc30-5240-4892-af8a-18d3e5a62fd3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881661871 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.3881661871
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.3681825666
Short name T349
Test name
Test status
Simulation time 526834396 ps
CPU time 1.46 seconds
Started Feb 04 12:54:34 PM PST 24
Finished Feb 04 12:54:43 PM PST 24
Peak memory 203564 kb
Host smart-dd476879-22de-430a-a812-11172591dbd9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681825666 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.3681825666
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.212563860
Short name T307
Test name
Test status
Simulation time 217893522 ps
CPU time 0.96 seconds
Started Feb 04 12:54:40 PM PST 24
Finished Feb 04 12:54:44 PM PST 24
Peak memory 203456 kb
Host smart-a3dad628-bbe7-4c7f-8dc9-2f25ea19e5d5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212563860 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.212563860
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.321758484
Short name T263
Test name
Test status
Simulation time 120251935 ps
CPU time 0.66 seconds
Started Feb 04 12:54:34 PM PST 24
Finished Feb 04 12:54:36 PM PST 24
Peak memory 203112 kb
Host smart-8ba8414b-5256-4b52-8011-f8b6e65ee62d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321758484 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.321758484
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.2540001974
Short name T267
Test name
Test status
Simulation time 1022793414 ps
CPU time 4.06 seconds
Started Feb 04 12:54:42 PM PST 24
Finished Feb 04 12:54:50 PM PST 24
Peak memory 203508 kb
Host smart-63fbf8ca-d651-4e03-bee9-89c7836506d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540001974 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same
_csr_outstanding.2540001974
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1330860951
Short name T287
Test name
Test status
Simulation time 708786839 ps
CPU time 2.98 seconds
Started Feb 04 12:54:35 PM PST 24
Finished Feb 04 12:54:45 PM PST 24
Peak memory 211864 kb
Host smart-b45d82d5-c20f-4768-9494-c637ca99758c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330860951 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.1330860951
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.378999893
Short name T41
Test name
Test status
Simulation time 841030424 ps
CPU time 15.28 seconds
Started Feb 04 12:54:32 PM PST 24
Finished Feb 04 12:54:50 PM PST 24
Peak memory 211728 kb
Host smart-d352bc94-4331-4bd9-8974-d076cdfd6edc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378999893 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.378999893
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.2146862341
Short name T52
Test name
Test status
Simulation time 1299005705 ps
CPU time 3.41 seconds
Started Feb 04 12:54:35 PM PST 24
Finished Feb 04 12:54:45 PM PST 24
Peak memory 214628 kb
Host smart-32f34aa4-e93a-4608-9393-77ba11755b45
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146862341 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.2146862341
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.4211846197
Short name T120
Test name
Test status
Simulation time 38712292 ps
CPU time 2.13 seconds
Started Feb 04 12:54:35 PM PST 24
Finished Feb 04 12:54:44 PM PST 24
Peak memory 203520 kb
Host smart-e2d2b46d-5b87-4b4f-9400-aec01df71b1e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211846197 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.4211846197
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.2340819457
Short name T264
Test name
Test status
Simulation time 273176339 ps
CPU time 1.54 seconds
Started Feb 04 12:54:37 PM PST 24
Finished Feb 04 12:54:44 PM PST 24
Peak memory 203528 kb
Host smart-1cf36773-c1ed-4c5f-939a-c818c9812480
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340819457 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
2340819457
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2367750566
Short name T249
Test name
Test status
Simulation time 44775592 ps
CPU time 0.66 seconds
Started Feb 04 12:54:42 PM PST 24
Finished Feb 04 12:54:47 PM PST 24
Peak memory 203236 kb
Host smart-4003c93f-a423-491b-8685-b9f0ad5d86fe
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367750566 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
2367750566
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.778233417
Short name T317
Test name
Test status
Simulation time 505963909 ps
CPU time 7.55 seconds
Started Feb 04 12:54:40 PM PST 24
Finished Feb 04 12:54:51 PM PST 24
Peak memory 203580 kb
Host smart-b03acdf6-365b-4669-ba8a-21f0fb51554b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778233417 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same_
csr_outstanding.778233417
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.1712885055
Short name T97
Test name
Test status
Simulation time 628655350 ps
CPU time 3.47 seconds
Started Feb 04 12:54:40 PM PST 24
Finished Feb 04 12:54:47 PM PST 24
Peak memory 203568 kb
Host smart-9fa86f15-4469-4d5a-b888-d5de13c26b0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712885055 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.1712885055
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.2354544972
Short name T55
Test name
Test status
Simulation time 6032808399 ps
CPU time 5.87 seconds
Started Feb 04 12:54:54 PM PST 24
Finished Feb 04 12:55:01 PM PST 24
Peak memory 219528 kb
Host smart-5fe14866-480c-44ba-89e1-c71f2e245e66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354544972 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.2354544972
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.3875951466
Short name T108
Test name
Test status
Simulation time 126711434 ps
CPU time 2.22 seconds
Started Feb 04 12:54:50 PM PST 24
Finished Feb 04 12:54:54 PM PST 24
Peak memory 211788 kb
Host smart-31c385e7-814a-41be-a5c2-6f917745bdee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875951466 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.3875951466
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.1700713772
Short name T104
Test name
Test status
Simulation time 296210752 ps
CPU time 1.61 seconds
Started Feb 04 12:54:42 PM PST 24
Finished Feb 04 12:54:48 PM PST 24
Peak memory 203448 kb
Host smart-1b0a8f12-7f07-444d-b76f-d44492f27a9f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700713772 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
1700713772
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1832617607
Short name T86
Test name
Test status
Simulation time 40942722 ps
CPU time 0.71 seconds
Started Feb 04 12:54:37 PM PST 24
Finished Feb 04 12:54:44 PM PST 24
Peak memory 203240 kb
Host smart-5fb248f9-fbcc-49ca-b9f5-1659a21417b2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832617607 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
1832617607
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.449248381
Short name T126
Test name
Test status
Simulation time 159977099 ps
CPU time 3.83 seconds
Started Feb 04 12:54:43 PM PST 24
Finished Feb 04 12:54:51 PM PST 24
Peak memory 203576 kb
Host smart-3ddedf28-38c8-4b23-8b3c-9504f04ca9e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449248381 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same_
csr_outstanding.449248381
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.759348901
Short name T44
Test name
Test status
Simulation time 361706019 ps
CPU time 2.42 seconds
Started Feb 04 12:54:48 PM PST 24
Finished Feb 04 12:54:53 PM PST 24
Peak memory 203428 kb
Host smart-25d7f7ca-944f-468b-9631-7421be1134dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759348901 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.759348901
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1560779550
Short name T293
Test name
Test status
Simulation time 753888600 ps
CPU time 14.85 seconds
Started Feb 04 12:54:50 PM PST 24
Finished Feb 04 12:55:07 PM PST 24
Peak memory 211928 kb
Host smart-1ba11bf2-58ef-443a-93c0-77c21c8401d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560779550 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.1
560779550
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3164527072
Short name T261
Test name
Test status
Simulation time 5005649429 ps
CPU time 6.01 seconds
Started Feb 04 12:55:00 PM PST 24
Finished Feb 04 12:55:11 PM PST 24
Peak memory 220116 kb
Host smart-712fa6d7-97f0-4bda-969f-a5b04ca3a37c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164527072 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.3164527072
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.1817540221
Short name T111
Test name
Test status
Simulation time 553570592 ps
CPU time 2.24 seconds
Started Feb 04 12:54:43 PM PST 24
Finished Feb 04 12:54:49 PM PST 24
Peak memory 203508 kb
Host smart-44c2300f-c0a1-427d-ba1b-11d6caab8099
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817540221 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.1817540221
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.378667968
Short name T247
Test name
Test status
Simulation time 201227611 ps
CPU time 0.98 seconds
Started Feb 04 12:54:54 PM PST 24
Finished Feb 04 12:54:56 PM PST 24
Peak memory 203472 kb
Host smart-d20acd44-87c8-4a56-a173-a471ed79d247
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378667968 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.378667968
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2750229771
Short name T340
Test name
Test status
Simulation time 54829798 ps
CPU time 0.78 seconds
Started Feb 04 12:54:47 PM PST 24
Finished Feb 04 12:54:51 PM PST 24
Peak memory 203280 kb
Host smart-bb4bfd70-ac19-4bb6-ad09-3f7a145a6e73
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750229771 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
2750229771
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.437889482
Short name T336
Test name
Test status
Simulation time 224243894 ps
CPU time 4.21 seconds
Started Feb 04 12:54:43 PM PST 24
Finished Feb 04 12:54:51 PM PST 24
Peak memory 203560 kb
Host smart-468d92cd-ff18-4231-a0e2-d0e174086eca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437889482 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same_
csr_outstanding.437889482
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.4073947538
Short name T297
Test name
Test status
Simulation time 141801968 ps
CPU time 3.69 seconds
Started Feb 04 12:54:43 PM PST 24
Finished Feb 04 12:54:51 PM PST 24
Peak memory 211940 kb
Host smart-826451c1-a882-4b13-9f11-be59e1ebc1de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073947538 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.4073947538
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1820886903
Short name T309
Test name
Test status
Simulation time 1389371785 ps
CPU time 15.27 seconds
Started Feb 04 12:54:44 PM PST 24
Finished Feb 04 12:55:03 PM PST 24
Peak memory 211800 kb
Host smart-652153e3-5d19-4fd8-b9ef-b9decade9fd7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820886903 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.1
820886903
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.41555073
Short name T80
Test name
Test status
Simulation time 142001354 ps
CPU time 1.81 seconds
Started Feb 04 12:54:43 PM PST 24
Finished Feb 04 12:54:49 PM PST 24
Peak memory 219992 kb
Host smart-a201861e-b71a-49f0-b849-f2a666ab0cd3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41555073 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.41555073
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2522507050
Short name T117
Test name
Test status
Simulation time 282126597 ps
CPU time 2.44 seconds
Started Feb 04 12:54:45 PM PST 24
Finished Feb 04 12:54:51 PM PST 24
Peak memory 203520 kb
Host smart-05cd7bff-4046-466b-b2c6-0d7bf4703869
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522507050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.2522507050
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3445749352
Short name T241
Test name
Test status
Simulation time 617896473 ps
CPU time 1.51 seconds
Started Feb 04 12:54:45 PM PST 24
Finished Feb 04 12:54:50 PM PST 24
Peak memory 203444 kb
Host smart-96b92c90-edd0-4356-87c0-7e51033a5c16
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445749352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
3445749352
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3931738491
Short name T262
Test name
Test status
Simulation time 52217758 ps
CPU time 0.69 seconds
Started Feb 04 12:55:00 PM PST 24
Finished Feb 04 12:55:05 PM PST 24
Peak memory 203084 kb
Host smart-bc243aa7-197e-439b-896b-0b587e245cb5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931738491 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
3931738491
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.2095352022
Short name T124
Test name
Test status
Simulation time 219826973 ps
CPU time 4.12 seconds
Started Feb 04 12:54:48 PM PST 24
Finished Feb 04 12:54:54 PM PST 24
Peak memory 203616 kb
Host smart-a5d227e7-0528-49b1-8071-2f9bd98da536
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095352022 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.2095352022
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.203739639
Short name T347
Test name
Test status
Simulation time 1232464887 ps
CPU time 5.9 seconds
Started Feb 04 12:54:55 PM PST 24
Finished Feb 04 12:55:01 PM PST 24
Peak memory 211892 kb
Host smart-ef4d09a9-4269-493a-abdb-985b93390dca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203739639 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.203739639
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.1701601417
Short name T40
Test name
Test status
Simulation time 425702951 ps
CPU time 7.57 seconds
Started Feb 04 12:54:54 PM PST 24
Finished Feb 04 12:55:02 PM PST 24
Peak memory 211720 kb
Host smart-3c647afd-93d8-430a-8f4f-6425fe12cef1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701601417 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.1
701601417
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.213359653
Short name T272
Test name
Test status
Simulation time 123866839 ps
CPU time 1.79 seconds
Started Feb 04 12:54:55 PM PST 24
Finished Feb 04 12:54:57 PM PST 24
Peak memory 211868 kb
Host smart-c6a7e67d-b69d-4dc6-b005-074b7e6afdf3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213359653 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.213359653
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2071245713
Short name T318
Test name
Test status
Simulation time 113134204 ps
CPU time 1.46 seconds
Started Feb 04 12:54:48 PM PST 24
Finished Feb 04 12:54:52 PM PST 24
Peak memory 203312 kb
Host smart-d03bf569-9852-44c4-b770-b125ffcb5bb2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071245713 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.2071245713
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.1072204792
Short name T345
Test name
Test status
Simulation time 696353532 ps
CPU time 1.59 seconds
Started Feb 04 12:55:00 PM PST 24
Finished Feb 04 12:55:06 PM PST 24
Peak memory 203292 kb
Host smart-81e934a6-b1cb-459d-902a-5dd554ea6ab7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072204792 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
1072204792
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.1626545596
Short name T77
Test name
Test status
Simulation time 56436500 ps
CPU time 0.69 seconds
Started Feb 04 12:54:45 PM PST 24
Finished Feb 04 12:54:49 PM PST 24
Peak memory 203320 kb
Host smart-970a12b5-158d-451f-b4ee-473c071655cc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626545596 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
1626545596
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.320512605
Short name T45
Test name
Test status
Simulation time 798228513 ps
CPU time 3.79 seconds
Started Feb 04 12:54:48 PM PST 24
Finished Feb 04 12:54:54 PM PST 24
Peak memory 203656 kb
Host smart-af61b950-99ef-46d1-b6bd-d0d0357f8cc4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320512605 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same_
csr_outstanding.320512605
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.2336677521
Short name T132
Test name
Test status
Simulation time 129353701 ps
CPU time 2.21 seconds
Started Feb 04 12:54:53 PM PST 24
Finished Feb 04 12:54:56 PM PST 24
Peak memory 203404 kb
Host smart-b60cd0ef-8f26-4bcd-8ca6-af02ab5d6fec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336677521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.2336677521
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.322569716
Short name T142
Test name
Test status
Simulation time 1105532747 ps
CPU time 19.13 seconds
Started Feb 04 12:54:53 PM PST 24
Finished Feb 04 12:55:13 PM PST 24
Peak memory 213544 kb
Host smart-95a396df-7432-4bfb-8005-51edcd33d7db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322569716 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.322569716
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.1032968546
Short name T319
Test name
Test status
Simulation time 3382474412 ps
CPU time 4.47 seconds
Started Feb 04 12:54:44 PM PST 24
Finished Feb 04 12:54:52 PM PST 24
Peak memory 211920 kb
Host smart-2750625b-5d69-4155-b408-90e781ef1e5b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032968546 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.1032968546
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.4227579014
Short name T259
Test name
Test status
Simulation time 83463846 ps
CPU time 1.4 seconds
Started Feb 04 12:55:00 PM PST 24
Finished Feb 04 12:55:06 PM PST 24
Peak memory 203588 kb
Host smart-7edef4e1-a32f-4261-b580-cf4fa40a2bf5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227579014 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.4227579014
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.3068261383
Short name T315
Test name
Test status
Simulation time 749865554 ps
CPU time 2.09 seconds
Started Feb 04 12:54:53 PM PST 24
Finished Feb 04 12:54:56 PM PST 24
Peak memory 203200 kb
Host smart-6d19a447-47fd-4c3d-bc8b-d38f465a7cd1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068261383 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
3068261383
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.593126651
Short name T243
Test name
Test status
Simulation time 46866546 ps
CPU time 0.66 seconds
Started Feb 04 12:54:41 PM PST 24
Finished Feb 04 12:54:47 PM PST 24
Peak memory 203256 kb
Host smart-da3c9228-c172-4084-9fb9-11fbeaaff606
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593126651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.593126651
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2247446380
Short name T112
Test name
Test status
Simulation time 1130980684 ps
CPU time 7.45 seconds
Started Feb 04 12:54:53 PM PST 24
Finished Feb 04 12:55:01 PM PST 24
Peak memory 203624 kb
Host smart-373d0064-7bc0-4532-aac6-428bd60810a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247446380 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.2247446380
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.218006343
Short name T281
Test name
Test status
Simulation time 76930850 ps
CPU time 4.37 seconds
Started Feb 04 12:55:00 PM PST 24
Finished Feb 04 12:55:09 PM PST 24
Peak memory 212256 kb
Host smart-23b4ed06-3c2e-4626-a256-71220b82640e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218006343 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.218006343
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.725578481
Short name T139
Test name
Test status
Simulation time 6135861531 ps
CPU time 20.32 seconds
Started Feb 04 12:54:51 PM PST 24
Finished Feb 04 12:55:12 PM PST 24
Peak memory 215548 kb
Host smart-7c23acb9-b29c-4258-b8fb-da2d6cd078de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725578481 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.725578481
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.351367572
Short name T325
Test name
Test status
Simulation time 61633208 ps
CPU time 2.17 seconds
Started Feb 04 12:54:54 PM PST 24
Finished Feb 04 12:54:57 PM PST 24
Peak memory 203544 kb
Host smart-2ac5e124-0068-4af4-aafa-a8b8e83a4669
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351367572 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.351367572
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2406185223
Short name T258
Test name
Test status
Simulation time 1302383308 ps
CPU time 4.45 seconds
Started Feb 04 12:54:49 PM PST 24
Finished Feb 04 12:54:55 PM PST 24
Peak memory 203516 kb
Host smart-0534120a-7b4c-441f-9c7a-2e399c5301c7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406185223 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
2406185223
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.1582605642
Short name T244
Test name
Test status
Simulation time 42480931 ps
CPU time 0.73 seconds
Started Feb 04 12:54:45 PM PST 24
Finished Feb 04 12:54:49 PM PST 24
Peak memory 203244 kb
Host smart-5bf4a870-5dd6-4eed-bb20-56949fd0c80f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582605642 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
1582605642
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3502432996
Short name T311
Test name
Test status
Simulation time 311751845 ps
CPU time 3.77 seconds
Started Feb 04 12:54:48 PM PST 24
Finished Feb 04 12:54:54 PM PST 24
Peak memory 203588 kb
Host smart-eb309fea-ca5f-4747-b022-1f253cc302fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502432996 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.3502432996
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.1235395230
Short name T266
Test name
Test status
Simulation time 420642891 ps
CPU time 7.52 seconds
Started Feb 04 12:55:00 PM PST 24
Finished Feb 04 12:55:12 PM PST 24
Peak memory 211864 kb
Host smart-13831788-aeab-4251-9035-d3361618f2cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235395230 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.1
235395230
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2535949414
Short name T352
Test name
Test status
Simulation time 988289308 ps
CPU time 2.99 seconds
Started Feb 04 12:54:58 PM PST 24
Finished Feb 04 12:55:03 PM PST 24
Peak memory 212924 kb
Host smart-9b8895cb-99fc-4327-8a4e-165640b5ec49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535949414 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.2535949414
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.1271163262
Short name T308
Test name
Test status
Simulation time 46395300 ps
CPU time 2.12 seconds
Started Feb 04 12:54:44 PM PST 24
Finished Feb 04 12:54:50 PM PST 24
Peak memory 211660 kb
Host smart-28cf0820-0a91-46b8-8945-dfda4886141b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271163262 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.1271163262
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2476062748
Short name T265
Test name
Test status
Simulation time 173337424 ps
CPU time 1.06 seconds
Started Feb 04 12:54:44 PM PST 24
Finished Feb 04 12:54:49 PM PST 24
Peak memory 203460 kb
Host smart-fbe9a369-01a8-4fff-bbd5-a4fe0e8d139b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476062748 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
2476062748
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.802688339
Short name T342
Test name
Test status
Simulation time 41366564 ps
CPU time 0.65 seconds
Started Feb 04 12:54:45 PM PST 24
Finished Feb 04 12:54:49 PM PST 24
Peak memory 203244 kb
Host smart-ebfe7440-aed6-4358-9c64-5b2d61078e88
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802688339 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.802688339
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1151908543
Short name T324
Test name
Test status
Simulation time 167679283 ps
CPU time 6.24 seconds
Started Feb 04 12:54:44 PM PST 24
Finished Feb 04 12:54:54 PM PST 24
Peak memory 203524 kb
Host smart-0d76291e-12bf-40bd-9a75-c3cf76807d58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151908543 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.1151908543
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.4217927552
Short name T82
Test name
Test status
Simulation time 291362719 ps
CPU time 5.75 seconds
Started Feb 04 12:54:58 PM PST 24
Finished Feb 04 12:55:06 PM PST 24
Peak memory 211864 kb
Host smart-6b688885-e622-4a8f-a965-7e1fdb2a82fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217927552 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.4217927552
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2484231955
Short name T137
Test name
Test status
Simulation time 536578074 ps
CPU time 9.6 seconds
Started Feb 04 12:54:58 PM PST 24
Finished Feb 04 12:55:10 PM PST 24
Peak memory 211820 kb
Host smart-362589d2-7c61-473e-a19f-d2d90303ac89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484231955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.2
484231955
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1511320862
Short name T291
Test name
Test status
Simulation time 2221866772 ps
CPU time 25.25 seconds
Started Feb 04 12:54:19 PM PST 24
Finished Feb 04 12:54:45 PM PST 24
Peak memory 203564 kb
Host smart-49159a94-7ab4-44ea-bc03-a06c4836a431
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511320862 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.1511320862
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.3479598983
Short name T355
Test name
Test status
Simulation time 7553504337 ps
CPU time 71.63 seconds
Started Feb 04 12:54:12 PM PST 24
Finished Feb 04 12:55:25 PM PST 24
Peak memory 203628 kb
Host smart-4b16dab8-1986-4e11-a525-bf3c1e4ca309
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479598983 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.3479598983
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3523835386
Short name T106
Test name
Test status
Simulation time 64439419 ps
CPU time 1.61 seconds
Started Feb 04 12:54:16 PM PST 24
Finished Feb 04 12:54:20 PM PST 24
Peak memory 203568 kb
Host smart-8060199f-4b8f-4acb-913a-2e80395a55f2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523835386 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.3523835386
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3777744981
Short name T43
Test name
Test status
Simulation time 2750536568 ps
CPU time 3.86 seconds
Started Feb 04 12:54:13 PM PST 24
Finished Feb 04 12:54:17 PM PST 24
Peak memory 219940 kb
Host smart-77e149d8-e909-4e7f-b558-2cc859b4511b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777744981 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.3777744981
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.2781662540
Short name T107
Test name
Test status
Simulation time 31617095 ps
CPU time 1.33 seconds
Started Feb 04 12:54:21 PM PST 24
Finished Feb 04 12:54:28 PM PST 24
Peak memory 203512 kb
Host smart-ef4b2bdc-0f3a-48e0-bb21-3a65e0fb630c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781662540 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.2781662540
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.775709745
Short name T242
Test name
Test status
Simulation time 4828534540 ps
CPU time 5.65 seconds
Started Feb 04 12:54:19 PM PST 24
Finished Feb 04 12:54:26 PM PST 24
Peak memory 203552 kb
Host smart-58fc31a0-87e5-45b0-8a6c-8fd0355e241a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775709745 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr
_aliasing.775709745
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.463757034
Short name T246
Test name
Test status
Simulation time 13775149136 ps
CPU time 10.56 seconds
Started Feb 04 12:54:13 PM PST 24
Finished Feb 04 12:54:24 PM PST 24
Peak memory 203532 kb
Host smart-b6dcb919-cbcb-4d3b-9f2e-d6f0f6c34b18
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463757034 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr
_bit_bash.463757034
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.917729907
Short name T346
Test name
Test status
Simulation time 494006656 ps
CPU time 1.04 seconds
Started Feb 04 12:54:21 PM PST 24
Finished Feb 04 12:54:28 PM PST 24
Peak memory 203384 kb
Host smart-4120e542-186b-4ba7-af0f-ecf0f77d529c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917729907 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr
_hw_reset.917729907
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.3255938741
Short name T328
Test name
Test status
Simulation time 301984237 ps
CPU time 1.38 seconds
Started Feb 04 12:54:20 PM PST 24
Finished Feb 04 12:54:27 PM PST 24
Peak memory 203492 kb
Host smart-005d6212-eeff-4ea6-9753-980f4bd07c63
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255938741 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.3
255938741
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.2316449041
Short name T334
Test name
Test status
Simulation time 117159662 ps
CPU time 0.89 seconds
Started Feb 04 12:54:12 PM PST 24
Finished Feb 04 12:54:13 PM PST 24
Peak memory 203176 kb
Host smart-a1a44de6-5975-4aea-94a5-f8e233f87965
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316449041 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_aliasing.2316449041
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.196777137
Short name T115
Test name
Test status
Simulation time 2737539025 ps
CPU time 8.81 seconds
Started Feb 04 12:54:15 PM PST 24
Finished Feb 04 12:54:26 PM PST 24
Peak memory 203492 kb
Host smart-e5fe265d-e5fc-4e3f-96ac-fb9c5ae7f1a0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196777137 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_bit_bash.196777137
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3118458925
Short name T312
Test name
Test status
Simulation time 127996230 ps
CPU time 0.73 seconds
Started Feb 04 12:54:15 PM PST 24
Finished Feb 04 12:54:17 PM PST 24
Peak memory 203220 kb
Host smart-8207c7f9-2445-4b0e-8ac0-97bec3ee360f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118458925 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.3118458925
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.4121312643
Short name T283
Test name
Test status
Simulation time 29431569 ps
CPU time 0.74 seconds
Started Feb 04 12:54:13 PM PST 24
Finished Feb 04 12:54:14 PM PST 24
Peak memory 203332 kb
Host smart-aaf1c119-4956-4fd8-bc73-28a9bc4d97dd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121312643 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.4
121312643
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.130312594
Short name T88
Test name
Test status
Simulation time 22965457 ps
CPU time 0.67 seconds
Started Feb 04 12:54:21 PM PST 24
Finished Feb 04 12:54:27 PM PST 24
Peak memory 203356 kb
Host smart-489cac8f-47f5-47a9-aae4-ef62fc6a1d0a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130312594 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_part
ial_access.130312594
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.2337553651
Short name T250
Test name
Test status
Simulation time 17731985 ps
CPU time 0.63 seconds
Started Feb 04 12:54:20 PM PST 24
Finished Feb 04 12:54:26 PM PST 24
Peak memory 203292 kb
Host smart-dc22e60c-5ba6-4467-b2df-ab6e0a1379db
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337553651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.2337553651
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.2442123196
Short name T110
Test name
Test status
Simulation time 3067962535 ps
CPU time 7.9 seconds
Started Feb 04 12:54:21 PM PST 24
Finished Feb 04 12:54:35 PM PST 24
Peak memory 203580 kb
Host smart-baefbf12-f231-4e66-bee5-97ff13e01946
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442123196 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.2442123196
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.385107863
Short name T329
Test name
Test status
Simulation time 8863986983 ps
CPU time 8.35 seconds
Started Feb 04 12:54:29 PM PST 24
Finished Feb 04 12:54:40 PM PST 24
Peak memory 214464 kb
Host smart-612f019c-f278-489e-a9bd-44dc01a828d9
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385107863 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.385107863
Directory /workspace/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.1985653352
Short name T269
Test name
Test status
Simulation time 385947013 ps
CPU time 2.79 seconds
Started Feb 04 12:54:15 PM PST 24
Finished Feb 04 12:54:19 PM PST 24
Peak memory 203716 kb
Host smart-184f3eea-2a2f-47e0-9496-81222b267e86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985653352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.1985653352
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/23.rv_dm_tap_fsm_rand_reset.3459981815
Short name T278
Test name
Test status
Simulation time 4955159536 ps
CPU time 9.21 seconds
Started Feb 04 12:54:45 PM PST 24
Finished Feb 04 12:54:57 PM PST 24
Peak memory 215608 kb
Host smart-8a498892-0e98-4fc5-b964-20a34c1855a1
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459981815 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 23.rv_dm_tap_fsm_rand_reset.3459981815
Directory /workspace/23.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/28.rv_dm_tap_fsm_rand_reset.2882111978
Short name T59
Test name
Test status
Simulation time 11044383482 ps
CPU time 8.98 seconds
Started Feb 04 12:54:49 PM PST 24
Finished Feb 04 12:55:00 PM PST 24
Peak memory 211928 kb
Host smart-3e48b45f-7bda-41f4-8730-435a938a3632
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882111978 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 28.rv_dm_tap_fsm_rand_reset.2882111978
Directory /workspace/28.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2682987948
Short name T105
Test name
Test status
Simulation time 5339985049 ps
CPU time 30.22 seconds
Started Feb 04 12:54:27 PM PST 24
Finished Feb 04 12:54:58 PM PST 24
Peak memory 203644 kb
Host smart-9bedc035-de2f-4643-81bd-26aeb8a361aa
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682987948 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.2682987948
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1938600856
Short name T122
Test name
Test status
Simulation time 9906338079 ps
CPU time 62.42 seconds
Started Feb 04 12:54:33 PM PST 24
Finished Feb 04 12:55:37 PM PST 24
Peak memory 203628 kb
Host smart-2d3c4f70-2583-48ef-925b-f6b3d0739b36
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938600856 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.1938600856
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.2511755981
Short name T331
Test name
Test status
Simulation time 130240387 ps
CPU time 1.57 seconds
Started Feb 04 12:54:34 PM PST 24
Finished Feb 04 12:54:41 PM PST 24
Peak memory 203504 kb
Host smart-086adec8-c7e0-43c4-9b66-c5ef940d8241
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511755981 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.2511755981
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.4099342334
Short name T121
Test name
Test status
Simulation time 94504366 ps
CPU time 1.55 seconds
Started Feb 04 12:54:35 PM PST 24
Finished Feb 04 12:54:43 PM PST 24
Peak memory 203544 kb
Host smart-af39219c-8ee6-4c6e-808d-71d88b6e3b9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099342334 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.4099342334
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.456981676
Short name T301
Test name
Test status
Simulation time 34111831925 ps
CPU time 55.95 seconds
Started Feb 04 12:54:16 PM PST 24
Finished Feb 04 12:55:14 PM PST 24
Peak memory 203492 kb
Host smart-44938da0-8b2f-424f-b25f-4557fd122717
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456981676 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr
_aliasing.456981676
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.4270203211
Short name T256
Test name
Test status
Simulation time 14513220944 ps
CPU time 20.64 seconds
Started Feb 04 12:54:15 PM PST 24
Finished Feb 04 12:54:37 PM PST 24
Peak memory 203372 kb
Host smart-11081dd4-bd85-4412-9af9-06933a12cb78
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270203211 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_bit_bash.4270203211
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.1756216743
Short name T103
Test name
Test status
Simulation time 2737140708 ps
CPU time 3.58 seconds
Started Feb 04 12:54:15 PM PST 24
Finished Feb 04 12:54:20 PM PST 24
Peak memory 203640 kb
Host smart-13d79908-b227-447c-a54e-fc7b6ce70161
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756216743 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.1756216743
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1217881821
Short name T251
Test name
Test status
Simulation time 1731308635 ps
CPU time 3.46 seconds
Started Feb 04 12:54:16 PM PST 24
Finished Feb 04 12:54:22 PM PST 24
Peak memory 203496 kb
Host smart-d7f0479d-ca74-4ebd-ab76-aae14114f224
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217881821 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.1
217881821
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3245694396
Short name T114
Test name
Test status
Simulation time 67190372 ps
CPU time 0.87 seconds
Started Feb 04 12:54:20 PM PST 24
Finished Feb 04 12:54:27 PM PST 24
Peak memory 203252 kb
Host smart-f27c56dc-0c1b-4990-a18e-63faef86b46f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245694396 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.3245694396
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1313384226
Short name T286
Test name
Test status
Simulation time 830077590 ps
CPU time 3.45 seconds
Started Feb 04 12:54:21 PM PST 24
Finished Feb 04 12:54:30 PM PST 24
Peak memory 203176 kb
Host smart-9c89e91f-9859-498e-a72d-4a20551a1d49
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313384226 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.1313384226
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.468288691
Short name T260
Test name
Test status
Simulation time 99532058 ps
CPU time 0.91 seconds
Started Feb 04 12:54:15 PM PST 24
Finished Feb 04 12:54:17 PM PST 24
Peak memory 203308 kb
Host smart-956b570e-4dad-43f0-beb9-4022433cae1e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468288691 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr
_hw_reset.468288691
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.415652243
Short name T330
Test name
Test status
Simulation time 107972830 ps
CPU time 0.7 seconds
Started Feb 04 12:54:12 PM PST 24
Finished Feb 04 12:54:13 PM PST 24
Peak memory 203168 kb
Host smart-63e58503-5cce-4626-9783-98bb50e055b9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415652243 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.415652243
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.239356202
Short name T344
Test name
Test status
Simulation time 28950220 ps
CPU time 0.68 seconds
Started Feb 04 12:54:37 PM PST 24
Finished Feb 04 12:54:44 PM PST 24
Peak memory 203356 kb
Host smart-0aabb52d-1854-4500-aa4e-dbebd285868c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239356202 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_part
ial_access.239356202
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1698603097
Short name T338
Test name
Test status
Simulation time 34901145 ps
CPU time 0.66 seconds
Started Feb 04 12:54:35 PM PST 24
Finished Feb 04 12:54:42 PM PST 24
Peak memory 203316 kb
Host smart-72fd367c-cb86-4359-83e0-2f55fd19d525
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698603097 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.1698603097
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2155063817
Short name T56
Test name
Test status
Simulation time 245883134 ps
CPU time 4.17 seconds
Started Feb 04 12:54:29 PM PST 24
Finished Feb 04 12:54:35 PM PST 24
Peak memory 203644 kb
Host smart-bd911745-1174-4287-a0dd-07180e86bb08
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155063817 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.2155063817
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.3937812430
Short name T294
Test name
Test status
Simulation time 176060149 ps
CPU time 2.2 seconds
Started Feb 04 12:54:37 PM PST 24
Finished Feb 04 12:54:45 PM PST 24
Peak memory 203612 kb
Host smart-2b68039b-7590-4cb5-9ce6-ea9edf3025b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937812430 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.3937812430
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.1641405003
Short name T143
Test name
Test status
Simulation time 251064894 ps
CPU time 8.57 seconds
Started Feb 04 12:54:39 PM PST 24
Finished Feb 04 12:54:52 PM PST 24
Peak memory 211688 kb
Host smart-ece82eb3-f02f-47b3-bba6-b4523bfb970a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641405003 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.1641405003
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/35.rv_dm_tap_fsm_rand_reset.1153911
Short name T279
Test name
Test status
Simulation time 5297548550 ps
CPU time 10.76 seconds
Started Feb 04 12:54:58 PM PST 24
Finished Feb 04 12:55:11 PM PST 24
Peak memory 220088 kb
Host smart-d4c846db-3cc7-4b2d-8b95-793f336b4bd3
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153911 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 35.rv_dm_tap_fsm_rand_reset.1153911
Directory /workspace/35.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/36.rv_dm_tap_fsm_rand_reset.1623134825
Short name T313
Test name
Test status
Simulation time 5887883569 ps
CPU time 12.11 seconds
Started Feb 04 12:54:58 PM PST 24
Finished Feb 04 12:55:13 PM PST 24
Peak memory 219816 kb
Host smart-dd98611f-3675-49c2-918d-a5538918f496
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623134825 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 36.rv_dm_tap_fsm_rand_reset.1623134825
Directory /workspace/36.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/37.rv_dm_tap_fsm_rand_reset.2165881833
Short name T327
Test name
Test status
Simulation time 9337509830 ps
CPU time 9.33 seconds
Started Feb 04 12:54:45 PM PST 24
Finished Feb 04 12:54:57 PM PST 24
Peak memory 216904 kb
Host smart-176118d0-68ec-411b-b3c7-d779c9696187
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165881833 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 37.rv_dm_tap_fsm_rand_reset.2165881833
Directory /workspace/37.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.4056365520
Short name T320
Test name
Test status
Simulation time 26603712420 ps
CPU time 79.26 seconds
Started Feb 04 12:54:30 PM PST 24
Finished Feb 04 12:55:52 PM PST 24
Peak memory 203676 kb
Host smart-36718e24-453e-499a-aaff-53b7b07cf9e9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056365520 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.4056365520
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.1655866950
Short name T321
Test name
Test status
Simulation time 14550469454 ps
CPU time 70.37 seconds
Started Feb 04 12:54:31 PM PST 24
Finished Feb 04 12:55:44 PM PST 24
Peak memory 203644 kb
Host smart-950e3c38-9c1e-4b1b-a061-b6d6f9c47458
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655866950 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.1655866950
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.1136434283
Short name T94
Test name
Test status
Simulation time 101037624 ps
CPU time 1.41 seconds
Started Feb 04 12:54:35 PM PST 24
Finished Feb 04 12:54:43 PM PST 24
Peak memory 203604 kb
Host smart-9e1f6dbf-b6b9-4303-99fb-e7fffa2ad803
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136434283 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.1136434283
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.1278352021
Short name T274
Test name
Test status
Simulation time 193398532 ps
CPU time 1.47 seconds
Started Feb 04 12:54:37 PM PST 24
Finished Feb 04 12:54:44 PM PST 24
Peak memory 203564 kb
Host smart-bf91dd70-240b-434c-b67f-3fa9dc04c056
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278352021 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.1278352021
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.3096509003
Short name T337
Test name
Test status
Simulation time 9948705422 ps
CPU time 14.44 seconds
Started Feb 04 12:54:35 PM PST 24
Finished Feb 04 12:54:56 PM PST 24
Peak memory 203588 kb
Host smart-9f2d6a3e-5f01-415c-a9f8-d53b7c7ac448
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096509003 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.3096509003
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.514892824
Short name T348
Test name
Test status
Simulation time 5650141278 ps
CPU time 11.44 seconds
Started Feb 04 12:54:35 PM PST 24
Finished Feb 04 12:54:53 PM PST 24
Peak memory 203448 kb
Host smart-67b6dda6-cddb-4bb7-bce9-0eca94878d8a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514892824 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr
_bit_bash.514892824
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.1059987170
Short name T89
Test name
Test status
Simulation time 491162870 ps
CPU time 1.17 seconds
Started Feb 04 12:54:38 PM PST 24
Finished Feb 04 12:54:44 PM PST 24
Peak memory 203344 kb
Host smart-f24aff41-2d6d-49b5-8ab6-8f5ed2a2a8bf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059987170 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.1059987170
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.4070789240
Short name T335
Test name
Test status
Simulation time 998138790 ps
CPU time 1.83 seconds
Started Feb 04 12:54:37 PM PST 24
Finished Feb 04 12:54:45 PM PST 24
Peak memory 203504 kb
Host smart-11d1a411-2a04-480a-a4e1-d9bdc1ba043e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070789240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.4
070789240
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.2563852406
Short name T316
Test name
Test status
Simulation time 57338976 ps
CPU time 0.82 seconds
Started Feb 04 12:54:37 PM PST 24
Finished Feb 04 12:54:44 PM PST 24
Peak memory 203304 kb
Host smart-da5d2fa8-7a89-4eaf-98fe-74d53653e06c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563852406 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.2563852406
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2923874716
Short name T326
Test name
Test status
Simulation time 2316203503 ps
CPU time 4.5 seconds
Started Feb 04 12:54:32 PM PST 24
Finished Feb 04 12:54:39 PM PST 24
Peak memory 203476 kb
Host smart-d4741eca-72c6-4a3b-bbb8-caf5677b7157
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923874716 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.2923874716
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.457134745
Short name T76
Test name
Test status
Simulation time 36285860 ps
CPU time 0.73 seconds
Started Feb 04 12:54:29 PM PST 24
Finished Feb 04 12:54:32 PM PST 24
Peak memory 203324 kb
Host smart-01c87bc9-a39f-4320-9636-84914af49d87
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457134745 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr
_hw_reset.457134745
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.1186598500
Short name T277
Test name
Test status
Simulation time 39793649 ps
CPU time 0.68 seconds
Started Feb 04 12:54:35 PM PST 24
Finished Feb 04 12:54:43 PM PST 24
Peak memory 203296 kb
Host smart-bb6886a4-0fae-41af-8c30-30e786b76892
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186598500 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.1
186598500
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1949838295
Short name T332
Test name
Test status
Simulation time 27674940 ps
CPU time 0.69 seconds
Started Feb 04 12:54:35 PM PST 24
Finished Feb 04 12:54:43 PM PST 24
Peak memory 202960 kb
Host smart-23ebc2fd-3291-4cdb-b9f1-61ef3e6023e9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949838295 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.1949838295
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.3994088243
Short name T288
Test name
Test status
Simulation time 43480507 ps
CPU time 0.64 seconds
Started Feb 04 12:54:38 PM PST 24
Finished Feb 04 12:54:44 PM PST 24
Peak memory 203324 kb
Host smart-398b57fa-6f70-401a-898b-ec2c982b0867
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994088243 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.3994088243
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.2441322135
Short name T310
Test name
Test status
Simulation time 292442869 ps
CPU time 4.41 seconds
Started Feb 04 12:54:34 PM PST 24
Finished Feb 04 12:54:45 PM PST 24
Peak memory 203556 kb
Host smart-84a5fb94-8a92-4779-810a-fedbe514a99f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441322135 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.2441322135
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.271545788
Short name T354
Test name
Test status
Simulation time 192705340 ps
CPU time 3.32 seconds
Started Feb 04 12:54:35 PM PST 24
Finished Feb 04 12:54:45 PM PST 24
Peak memory 211912 kb
Host smart-d862a261-2755-4838-9a1d-8b52b55fcb26
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271545788 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.271545788
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.283405113
Short name T133
Test name
Test status
Simulation time 326866318 ps
CPU time 8.08 seconds
Started Feb 04 12:54:33 PM PST 24
Finished Feb 04 12:54:43 PM PST 24
Peak memory 211740 kb
Host smart-4d0541d9-1771-4fc1-aca7-8345fa6b0b90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283405113 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.283405113
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.884339049
Short name T118
Test name
Test status
Simulation time 85305981 ps
CPU time 2.12 seconds
Started Feb 04 12:54:34 PM PST 24
Finished Feb 04 12:54:43 PM PST 24
Peak memory 203580 kb
Host smart-cfe627f6-fc15-4225-95fe-077e842dbe3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884339049 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.884339049
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.2246001127
Short name T292
Test name
Test status
Simulation time 716265113 ps
CPU time 2.51 seconds
Started Feb 04 12:54:39 PM PST 24
Finished Feb 04 12:54:45 PM PST 24
Peak memory 203348 kb
Host smart-837c9f89-0a27-4c18-bdc9-32c9b521597f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246001127 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.2
246001127
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.700931424
Short name T61
Test name
Test status
Simulation time 28744109 ps
CPU time 0.65 seconds
Started Feb 04 12:54:37 PM PST 24
Finished Feb 04 12:54:44 PM PST 24
Peak memory 203252 kb
Host smart-fd31dc7b-5471-42db-92f8-8cac63e3e566
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700931424 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.700931424
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.302987406
Short name T95
Test name
Test status
Simulation time 595162678 ps
CPU time 6.23 seconds
Started Feb 04 12:54:40 PM PST 24
Finished Feb 04 12:54:50 PM PST 24
Peak memory 203584 kb
Host smart-8746668f-4dc2-4e9c-b2ca-6b8e8508e001
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302987406 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_c
sr_outstanding.302987406
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.1885872722
Short name T99
Test name
Test status
Simulation time 222955736 ps
CPU time 4.09 seconds
Started Feb 04 12:54:37 PM PST 24
Finished Feb 04 12:54:47 PM PST 24
Peak memory 203608 kb
Host smart-d66275e8-3a6a-4900-a5e4-6f5fcba6594c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885872722 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.1885872722
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3345924799
Short name T136
Test name
Test status
Simulation time 445126722 ps
CPU time 15.04 seconds
Started Feb 04 12:54:32 PM PST 24
Finished Feb 04 12:54:49 PM PST 24
Peak memory 211840 kb
Host smart-e7e94edb-7a72-4792-86df-4482a8ca44ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345924799 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.3345924799
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2042723773
Short name T343
Test name
Test status
Simulation time 155688742 ps
CPU time 1.89 seconds
Started Feb 04 12:54:35 PM PST 24
Finished Feb 04 12:54:43 PM PST 24
Peak memory 211748 kb
Host smart-48f4eb47-4deb-4376-8007-c3b36418918e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042723773 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.2042723773
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.2970827185
Short name T255
Test name
Test status
Simulation time 314161064 ps
CPU time 2.37 seconds
Started Feb 04 12:54:34 PM PST 24
Finished Feb 04 12:54:43 PM PST 24
Peak memory 211700 kb
Host smart-76a0c23f-9735-4482-94e6-b096dbbb1abd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970827185 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.2970827185
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.1819719757
Short name T87
Test name
Test status
Simulation time 345786787 ps
CPU time 1.86 seconds
Started Feb 04 12:54:38 PM PST 24
Finished Feb 04 12:54:45 PM PST 24
Peak memory 203380 kb
Host smart-7a0a3789-26f5-444b-a4e5-6944f97787ee
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819719757 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.1
819719757
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.330170606
Short name T252
Test name
Test status
Simulation time 145281533 ps
CPU time 0.71 seconds
Started Feb 04 12:54:37 PM PST 24
Finished Feb 04 12:54:44 PM PST 24
Peak memory 203296 kb
Host smart-9ad1843d-d2cb-407b-80af-d1ffd579337a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330170606 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.330170606
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.4055556160
Short name T85
Test name
Test status
Simulation time 135289947 ps
CPU time 6.09 seconds
Started Feb 04 12:54:33 PM PST 24
Finished Feb 04 12:54:41 PM PST 24
Peak memory 203548 kb
Host smart-6b9b1681-0d2b-4706-a695-54208b227ed2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055556160 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.4055556160
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.3024208555
Short name T96
Test name
Test status
Simulation time 201087179 ps
CPU time 4.22 seconds
Started Feb 04 12:54:39 PM PST 24
Finished Feb 04 12:54:47 PM PST 24
Peak memory 203704 kb
Host smart-745448a9-b162-4df5-9d0a-f33ba76a4b11
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024208555 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.3024208555
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1159651212
Short name T144
Test name
Test status
Simulation time 1051636952 ps
CPU time 10.44 seconds
Started Feb 04 12:54:37 PM PST 24
Finished Feb 04 12:54:53 PM PST 24
Peak memory 212012 kb
Host smart-289adb0c-2322-4762-9b2f-e30b0a66d8b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159651212 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.1159651212
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.3815792981
Short name T119
Test name
Test status
Simulation time 98511365 ps
CPU time 1.34 seconds
Started Feb 04 12:54:39 PM PST 24
Finished Feb 04 12:54:44 PM PST 24
Peak memory 203424 kb
Host smart-06e9b1a4-ed44-408d-bb26-b61fffb732a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815792981 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.3815792981
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.1397432301
Short name T302
Test name
Test status
Simulation time 551452714 ps
CPU time 2.79 seconds
Started Feb 04 12:54:35 PM PST 24
Finished Feb 04 12:54:45 PM PST 24
Peak memory 203076 kb
Host smart-b42f41eb-f0dc-4e12-bf46-c581b61594d6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397432301 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.1
397432301
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.2317250387
Short name T358
Test name
Test status
Simulation time 26230835 ps
CPU time 0.66 seconds
Started Feb 04 12:54:35 PM PST 24
Finished Feb 04 12:54:42 PM PST 24
Peak memory 203316 kb
Host smart-a0659b38-5692-4975-80da-0427d5eb4ae4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317250387 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.2
317250387
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.2146743403
Short name T127
Test name
Test status
Simulation time 416805371 ps
CPU time 7.32 seconds
Started Feb 04 12:54:34 PM PST 24
Finished Feb 04 12:54:48 PM PST 24
Peak memory 203644 kb
Host smart-70b88d70-4abe-4684-be5f-45dbd1e1dca8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146743403 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.2146743403
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.1163568818
Short name T323
Test name
Test status
Simulation time 107613824 ps
CPU time 3.38 seconds
Started Feb 04 12:54:39 PM PST 24
Finished Feb 04 12:54:47 PM PST 24
Peak memory 203704 kb
Host smart-798db5fb-e823-4a26-bec9-80595b9dabfe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163568818 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.1163568818
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.4277743850
Short name T356
Test name
Test status
Simulation time 1680648146 ps
CPU time 3.2 seconds
Started Feb 04 12:54:34 PM PST 24
Finished Feb 04 12:54:45 PM PST 24
Peak memory 220056 kb
Host smart-30322982-27d8-46a3-a965-3cb992910c26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277743850 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.4277743850
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.3454522315
Short name T123
Test name
Test status
Simulation time 165445260 ps
CPU time 2.23 seconds
Started Feb 04 12:54:31 PM PST 24
Finished Feb 04 12:54:36 PM PST 24
Peak memory 203512 kb
Host smart-0f3bb768-c5d5-4f6a-9d69-ff909f92bbd2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454522315 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.3454522315
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.270274022
Short name T254
Test name
Test status
Simulation time 234704375 ps
CPU time 1.41 seconds
Started Feb 04 12:54:38 PM PST 24
Finished Feb 04 12:54:45 PM PST 24
Peak memory 203524 kb
Host smart-8620381d-3853-4836-967c-c73ddb8f10bb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270274022 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.270274022
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.403045208
Short name T303
Test name
Test status
Simulation time 120319116 ps
CPU time 0.7 seconds
Started Feb 04 12:54:35 PM PST 24
Finished Feb 04 12:54:42 PM PST 24
Peak memory 203296 kb
Host smart-3513edb3-d21d-4e28-8da3-a3be11763a13
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403045208 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.403045208
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2998562630
Short name T90
Test name
Test status
Simulation time 510318711 ps
CPU time 6.3 seconds
Started Feb 04 12:54:35 PM PST 24
Finished Feb 04 12:54:48 PM PST 24
Peak memory 203620 kb
Host smart-37e2c23d-1725-4b9a-acb3-b88a43fde176
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998562630 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_
csr_outstanding.2998562630
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2296392000
Short name T351
Test name
Test status
Simulation time 188054318 ps
CPU time 2.82 seconds
Started Feb 04 12:54:31 PM PST 24
Finished Feb 04 12:54:37 PM PST 24
Peak memory 203712 kb
Host smart-096a9efc-bfe0-40e8-8d42-9e01a11ee5b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296392000 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.2296392000
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.4092159674
Short name T140
Test name
Test status
Simulation time 451300672 ps
CPU time 8.56 seconds
Started Feb 04 12:54:31 PM PST 24
Finished Feb 04 12:54:42 PM PST 24
Peak memory 211856 kb
Host smart-742ea784-d95f-43ca-9fbd-234134c87813
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092159674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.4092159674
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.1833862882
Short name T75
Test name
Test status
Simulation time 7259275852 ps
CPU time 14.33 seconds
Started Feb 04 12:54:44 PM PST 24
Finished Feb 04 12:55:02 PM PST 24
Peak memory 220140 kb
Host smart-b09ea843-d1d6-4cbb-8527-2770e47098b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833862882 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.1833862882
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.344108196
Short name T271
Test name
Test status
Simulation time 33120358 ps
CPU time 1.38 seconds
Started Feb 04 12:54:33 PM PST 24
Finished Feb 04 12:54:36 PM PST 24
Peak memory 203588 kb
Host smart-feafbab4-e29b-47d5-afea-4997bd6b0315
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344108196 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.344108196
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3266809723
Short name T280
Test name
Test status
Simulation time 346463682 ps
CPU time 1.68 seconds
Started Feb 04 12:54:33 PM PST 24
Finished Feb 04 12:54:37 PM PST 24
Peak memory 203520 kb
Host smart-8fc8aa17-1c74-47bf-99ee-88db88c45146
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266809723 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.3
266809723
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.2893374307
Short name T113
Test name
Test status
Simulation time 40568641 ps
CPU time 0.68 seconds
Started Feb 04 12:54:36 PM PST 24
Finished Feb 04 12:54:44 PM PST 24
Peak memory 203264 kb
Host smart-691504aa-aff0-453c-9085-39eca23e3f2d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893374307 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.2
893374307
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.1398022776
Short name T273
Test name
Test status
Simulation time 155282801 ps
CPU time 3.48 seconds
Started Feb 04 12:54:38 PM PST 24
Finished Feb 04 12:54:47 PM PST 24
Peak memory 203660 kb
Host smart-95ec5e0b-1642-4eee-8984-cfb57005adcd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398022776 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.1398022776
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.3849180330
Short name T145
Test name
Test status
Simulation time 239708748 ps
CPU time 5.19 seconds
Started Feb 04 12:54:30 PM PST 24
Finished Feb 04 12:54:38 PM PST 24
Peak memory 211688 kb
Host smart-48bd922d-edf1-47c5-8357-7263c3d07174
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849180330 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.3849180330
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.911282660
Short name T134
Test name
Test status
Simulation time 1348661351 ps
CPU time 18.25 seconds
Started Feb 04 12:54:43 PM PST 24
Finished Feb 04 12:55:06 PM PST 24
Peak memory 213752 kb
Host smart-1a29835e-3150-4276-9064-19dc33011f86
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911282660 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.911282660
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.532996176
Short name T51
Test name
Test status
Simulation time 43765551 ps
CPU time 0.67 seconds
Started Feb 04 12:55:55 PM PST 24
Finished Feb 04 12:55:59 PM PST 24
Peak memory 203652 kb
Host smart-3c2c11e8-2db4-481f-b59b-4972a36d4957
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532996176 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.532996176
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.3779065352
Short name T196
Test name
Test status
Simulation time 48975814691 ps
CPU time 86.05 seconds
Started Feb 04 12:55:53 PM PST 24
Finished Feb 04 12:57:22 PM PST 24
Peak memory 204080 kb
Host smart-2f64ac83-37ef-4b1b-887a-d473904ec6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779065352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.3779065352
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.2361290125
Short name T222
Test name
Test status
Simulation time 6464806102 ps
CPU time 8.38 seconds
Started Feb 04 12:55:58 PM PST 24
Finished Feb 04 12:56:09 PM PST 24
Peak memory 204100 kb
Host smart-ce626aeb-94ed-475c-9841-76a41079d605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361290125 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.2361290125
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.437041163
Short name T14
Test name
Test status
Simulation time 3073357676 ps
CPU time 5.37 seconds
Started Feb 04 12:55:57 PM PST 24
Finished Feb 04 12:56:04 PM PST 24
Peak memory 203988 kb
Host smart-7fc66b62-9853-4021-980d-897c741555e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437041163 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.437041163
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.1266851002
Short name T5
Test name
Test status
Simulation time 502684546 ps
CPU time 1.08 seconds
Started Feb 04 12:55:57 PM PST 24
Finished Feb 04 12:56:00 PM PST 24
Peak memory 203684 kb
Host smart-489efbae-2c3f-44ac-bc77-1cc5353c8684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266851002 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.1266851002
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.331849798
Short name T4
Test name
Test status
Simulation time 999887639 ps
CPU time 3.33 seconds
Started Feb 04 12:55:59 PM PST 24
Finished Feb 04 12:56:04 PM PST 24
Peak memory 203896 kb
Host smart-7c7ffb5d-5df4-4d83-8654-379baf149515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331849798 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.331849798
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.290063502
Short name T227
Test name
Test status
Simulation time 107573107 ps
CPU time 0.68 seconds
Started Feb 04 12:55:52 PM PST 24
Finished Feb 04 12:55:56 PM PST 24
Peak memory 203696 kb
Host smart-f52b4acd-f128-40cc-9715-817693548b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290063502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.290063502
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.2290589683
Short name T218
Test name
Test status
Simulation time 265589513 ps
CPU time 1.2 seconds
Started Feb 04 12:55:54 PM PST 24
Finished Feb 04 12:55:57 PM PST 24
Peak memory 204016 kb
Host smart-982c17f0-90ab-4bbc-8195-e63cb33f4669
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2290589683 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t
l_access.2290589683
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.1549219673
Short name T31
Test name
Test status
Simulation time 807755518 ps
CPU time 3.33 seconds
Started Feb 04 12:55:54 PM PST 24
Finished Feb 04 12:56:00 PM PST 24
Peak memory 203888 kb
Host smart-9170b43e-8ce5-48f0-a74c-c5c456d54085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549219673 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.1549219673
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.1688142241
Short name T22
Test name
Test status
Simulation time 74861110 ps
CPU time 0.75 seconds
Started Feb 04 12:55:59 PM PST 24
Finished Feb 04 12:56:02 PM PST 24
Peak memory 203340 kb
Host smart-f359a434-fbc9-4807-8b6b-a7852c9123bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688142241 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.1688142241
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.2467385378
Short name T33
Test name
Test status
Simulation time 62590135 ps
CPU time 0.78 seconds
Started Feb 04 12:56:00 PM PST 24
Finished Feb 04 12:56:03 PM PST 24
Peak memory 203296 kb
Host smart-0cfdcf52-fb1c-456a-8450-e2cd9d2a4380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467385378 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.2467385378
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.3785653426
Short name T224
Test name
Test status
Simulation time 71595849 ps
CPU time 0.87 seconds
Started Feb 04 12:56:00 PM PST 24
Finished Feb 04 12:56:04 PM PST 24
Peak memory 203332 kb
Host smart-663294eb-263d-472f-a5d7-c71dd75cc158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785653426 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.3785653426
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.1930558909
Short name T57
Test name
Test status
Simulation time 391995957 ps
CPU time 1.03 seconds
Started Feb 04 12:56:04 PM PST 24
Finished Feb 04 12:56:07 PM PST 24
Peak memory 203676 kb
Host smart-d74dd56f-61d4-429f-9337-f8376040a8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930558909 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.1930558909
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.339560940
Short name T28
Test name
Test status
Simulation time 58048158 ps
CPU time 0.72 seconds
Started Feb 04 12:55:59 PM PST 24
Finished Feb 04 12:56:02 PM PST 24
Peak memory 203584 kb
Host smart-19702f7e-4e06-4d71-895b-3d2401c82c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339560940 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.339560940
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.1417999135
Short name T79
Test name
Test status
Simulation time 366383452 ps
CPU time 1.14 seconds
Started Feb 04 12:56:00 PM PST 24
Finished Feb 04 12:56:04 PM PST 24
Peak memory 203652 kb
Host smart-5078464c-d010-4d63-89d0-ea79d54059d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417999135 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.1417999135
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.3042331548
Short name T27
Test name
Test status
Simulation time 476189882 ps
CPU time 1.06 seconds
Started Feb 04 12:55:58 PM PST 24
Finished Feb 04 12:56:01 PM PST 24
Peak memory 203500 kb
Host smart-82094a4d-2742-43ae-9bf2-6eff4fa2ecfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042331548 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.3042331548
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.155659311
Short name T19
Test name
Test status
Simulation time 791737319 ps
CPU time 3.12 seconds
Started Feb 04 12:55:59 PM PST 24
Finished Feb 04 12:56:04 PM PST 24
Peak memory 203880 kb
Host smart-b9fb239e-9dca-490a-84f6-d174020582b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155659311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.155659311
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.2828285466
Short name T201
Test name
Test status
Simulation time 2138355164 ps
CPU time 5.43 seconds
Started Feb 04 12:55:58 PM PST 24
Finished Feb 04 12:56:05 PM PST 24
Peak memory 204000 kb
Host smart-082091a9-51b0-4426-855a-e7e923f6562e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828285466 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.2828285466
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.3088881056
Short name T234
Test name
Test status
Simulation time 562172103 ps
CPU time 1.02 seconds
Started Feb 04 12:56:00 PM PST 24
Finished Feb 04 12:56:03 PM PST 24
Peak memory 203592 kb
Host smart-0647e642-1ad4-4be0-86cb-2fd417a176e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088881056 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.3088881056
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.3328760011
Short name T58
Test name
Test status
Simulation time 2242855973 ps
CPU time 2.61 seconds
Started Feb 04 12:55:53 PM PST 24
Finished Feb 04 12:55:58 PM PST 24
Peak memory 203984 kb
Host smart-9f024ada-88da-49af-aa24-06905e57742e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328760011 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.3328760011
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.1069491851
Short name T70
Test name
Test status
Simulation time 19894331 ps
CPU time 0.72 seconds
Started Feb 04 12:56:44 PM PST 24
Finished Feb 04 12:56:48 PM PST 24
Peak memory 203608 kb
Host smart-feba8bb2-aeae-41cb-8eee-1d3032fcc4bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069491851 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.1069491851
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.2096860509
Short name T10
Test name
Test status
Simulation time 323535652 ps
CPU time 1.08 seconds
Started Feb 04 12:55:58 PM PST 24
Finished Feb 04 12:56:01 PM PST 24
Peak memory 203584 kb
Host smart-7e83ce08-c42a-4415-9767-07dd5edc481f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096860509 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.2096860509
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.3301132094
Short name T24
Test name
Test status
Simulation time 26559027 ps
CPU time 0.68 seconds
Started Feb 04 12:56:05 PM PST 24
Finished Feb 04 12:56:07 PM PST 24
Peak memory 203712 kb
Host smart-97afb6f7-2448-4ac7-8b10-44b53a92493a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301132094 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.3301132094
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.1491003158
Short name T210
Test name
Test status
Simulation time 575947216 ps
CPU time 3.08 seconds
Started Feb 04 12:56:05 PM PST 24
Finished Feb 04 12:56:10 PM PST 24
Peak memory 203292 kb
Host smart-5a47156b-c9dd-4017-ab9d-3d4639abcd69
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1491003158 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.1491003158
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.2299835164
Short name T18
Test name
Test status
Simulation time 1008080391 ps
CPU time 3.87 seconds
Started Feb 04 12:56:03 PM PST 24
Finished Feb 04 12:56:09 PM PST 24
Peak memory 203964 kb
Host smart-a265d4bd-3d49-4630-b7b6-2136124ef3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299835164 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.2299835164
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.2830835709
Short name T236
Test name
Test status
Simulation time 137631366 ps
CPU time 0.74 seconds
Started Feb 04 12:56:18 PM PST 24
Finished Feb 04 12:56:21 PM PST 24
Peak memory 203180 kb
Host smart-71292033-43b8-4a37-8e7a-9788f2833c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830835709 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.2830835709
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.370988605
Short name T32
Test name
Test status
Simulation time 143774260 ps
CPU time 0.74 seconds
Started Feb 04 12:56:31 PM PST 24
Finished Feb 04 12:56:35 PM PST 24
Peak memory 203568 kb
Host smart-7d3fec31-3c95-4dfd-a71c-9e2b487ad195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370988605 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.370988605
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.1497557565
Short name T233
Test name
Test status
Simulation time 94495447 ps
CPU time 0.77 seconds
Started Feb 04 12:56:16 PM PST 24
Finished Feb 04 12:56:19 PM PST 24
Peak memory 203180 kb
Host smart-1529ed07-21d5-41aa-a2e3-2b6babf42502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497557565 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.1497557565
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.1947549926
Short name T11
Test name
Test status
Simulation time 388798080 ps
CPU time 0.88 seconds
Started Feb 04 12:56:07 PM PST 24
Finished Feb 04 12:56:09 PM PST 24
Peak memory 203580 kb
Host smart-6a395533-8bf2-4eeb-a309-c4a333a01e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947549926 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.1947549926
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.2619594438
Short name T60
Test name
Test status
Simulation time 43596662 ps
CPU time 0.68 seconds
Started Feb 04 12:56:48 PM PST 24
Finished Feb 04 12:56:55 PM PST 24
Peak memory 203592 kb
Host smart-5aa18dd9-4b20-4e42-9688-1605a01c47f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619594438 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.2619594438
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.1498831695
Short name T78
Test name
Test status
Simulation time 34160127 ps
CPU time 0.67 seconds
Started Feb 04 12:55:51 PM PST 24
Finished Feb 04 12:55:55 PM PST 24
Peak memory 203596 kb
Host smart-a8d1b670-a78c-43ac-baec-53b201ea8849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498831695 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.1498831695
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.3317038772
Short name T20
Test name
Test status
Simulation time 920641756 ps
CPU time 1.36 seconds
Started Feb 04 12:56:16 PM PST 24
Finished Feb 04 12:56:19 PM PST 24
Peak memory 203812 kb
Host smart-e17dc2c7-fef2-48fb-b9d3-1fa885d0a6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317038772 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.3317038772
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.2008229580
Short name T177
Test name
Test status
Simulation time 972822906 ps
CPU time 2.95 seconds
Started Feb 04 12:56:02 PM PST 24
Finished Feb 04 12:56:07 PM PST 24
Peak memory 204044 kb
Host smart-98ad9717-8f0f-4a42-8ab0-49f2a94d34ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008229580 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.2008229580
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.2554391276
Short name T38
Test name
Test status
Simulation time 332555506 ps
CPU time 1.2 seconds
Started Feb 04 12:56:13 PM PST 24
Finished Feb 04 12:56:16 PM PST 24
Peak memory 219892 kb
Host smart-d2942a47-5105-4f9c-9d1a-ae327d0ef6ba
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554391276 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.2554391276
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.419784466
Short name T25
Test name
Test status
Simulation time 267502094 ps
CPU time 1.47 seconds
Started Feb 04 12:56:03 PM PST 24
Finished Feb 04 12:56:06 PM PST 24
Peak memory 203476 kb
Host smart-396d3326-5c6c-47db-9460-44d12da33541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419784466 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.419784466
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.3583360310
Short name T230
Test name
Test status
Simulation time 21971164 ps
CPU time 0.64 seconds
Started Feb 04 12:56:13 PM PST 24
Finished Feb 04 12:56:15 PM PST 24
Peak memory 203668 kb
Host smart-39c78853-251b-430d-b077-39389af7ed66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583360310 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.3583360310
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.2836376564
Short name T186
Test name
Test status
Simulation time 4846167671 ps
CPU time 8.55 seconds
Started Feb 04 12:56:16 PM PST 24
Finished Feb 04 12:56:27 PM PST 24
Peak memory 204052 kb
Host smart-bca08bfc-5624-4216-8d85-f95059b53967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836376564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.2836376564
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.2499483962
Short name T183
Test name
Test status
Simulation time 1466886226 ps
CPU time 3.31 seconds
Started Feb 04 12:56:12 PM PST 24
Finished Feb 04 12:56:16 PM PST 24
Peak memory 204000 kb
Host smart-ddef3720-9ac7-4030-81bf-a724e379b804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499483962 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.2499483962
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.616051000
Short name T235
Test name
Test status
Simulation time 3034149722 ps
CPU time 13.12 seconds
Started Feb 04 12:56:16 PM PST 24
Finished Feb 04 12:56:31 PM PST 24
Peak memory 203832 kb
Host smart-504e5ea6-97f8-400a-bfc5-6b69e3eb6d08
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=616051000 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_t
l_access.616051000
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.1336672719
Short name T217
Test name
Test status
Simulation time 2598085731 ps
CPU time 12.13 seconds
Started Feb 04 12:56:16 PM PST 24
Finished Feb 04 12:56:30 PM PST 24
Peak memory 203972 kb
Host smart-92fc47ae-7795-446a-96cc-8b9f3944ce55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336672719 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.1336672719
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.2566525513
Short name T30
Test name
Test status
Simulation time 245219128 ps
CPU time 0.72 seconds
Started Feb 04 12:56:06 PM PST 24
Finished Feb 04 12:56:08 PM PST 24
Peak memory 203636 kb
Host smart-2b4f9754-b8b1-4c36-af21-2ad80cb112e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566525513 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.2566525513
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.3173054053
Short name T238
Test name
Test status
Simulation time 3545076050 ps
CPU time 6.69 seconds
Started Feb 04 12:56:23 PM PST 24
Finished Feb 04 12:56:32 PM PST 24
Peak memory 204140 kb
Host smart-9919696b-3d81-4bdc-b033-f31e5e6d9d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173054053 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.3173054053
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.2704678632
Short name T192
Test name
Test status
Simulation time 5306810813 ps
CPU time 9.27 seconds
Started Feb 04 12:56:40 PM PST 24
Finished Feb 04 12:56:50 PM PST 24
Peak memory 204176 kb
Host smart-4ce1abc8-1686-4218-9597-384baee18708
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2704678632 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_
tl_access.2704678632
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.2161717581
Short name T152
Test name
Test status
Simulation time 36717512 ps
CPU time 0.73 seconds
Started Feb 04 12:56:18 PM PST 24
Finished Feb 04 12:56:22 PM PST 24
Peak memory 203656 kb
Host smart-25b58368-e2c9-44bd-8b34-3d3e8f3cc5b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161717581 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.2161717581
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.2490553795
Short name T207
Test name
Test status
Simulation time 13169584153 ps
CPU time 20.44 seconds
Started Feb 04 12:56:44 PM PST 24
Finished Feb 04 12:57:08 PM PST 24
Peak memory 204108 kb
Host smart-ace80817-fa30-4b70-9560-a93e66198b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490553795 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.2490553795
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.2644441090
Short name T208
Test name
Test status
Simulation time 2745865347 ps
CPU time 6.55 seconds
Started Feb 04 12:56:33 PM PST 24
Finished Feb 04 12:56:43 PM PST 24
Peak memory 204136 kb
Host smart-a82deb9d-4481-45cc-8ec1-9aa888d51cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644441090 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.2644441090
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.3216900306
Short name T213
Test name
Test status
Simulation time 1890337691 ps
CPU time 8.89 seconds
Started Feb 04 12:56:23 PM PST 24
Finished Feb 04 12:56:34 PM PST 24
Peak memory 204020 kb
Host smart-e5e6f96e-aea5-4a39-a401-e59c8c98a415
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3216900306 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.3216900306
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.1855554987
Short name T193
Test name
Test status
Simulation time 5244478802 ps
CPU time 4.79 seconds
Started Feb 04 12:56:12 PM PST 24
Finished Feb 04 12:56:19 PM PST 24
Peak memory 204172 kb
Host smart-0a5f9800-c2b0-4bd7-90c1-a2594815f5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855554987 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.1855554987
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_stress_all.2542668506
Short name T91
Test name
Test status
Simulation time 2290786775 ps
CPU time 4.37 seconds
Started Feb 04 12:56:12 PM PST 24
Finished Feb 04 12:56:17 PM PST 24
Peak memory 204044 kb
Host smart-408fc859-7840-4998-aeb1-9180671c7d89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542668506 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.2542668506
Directory /workspace/12.rv_dm_stress_all/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.2167358495
Short name T162
Test name
Test status
Simulation time 159720912 ps
CPU time 0.67 seconds
Started Feb 04 12:56:12 PM PST 24
Finished Feb 04 12:56:14 PM PST 24
Peak memory 203668 kb
Host smart-163e868e-af92-43e8-b861-4dda25ad6855
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167358495 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.2167358495
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.814322128
Short name T220
Test name
Test status
Simulation time 3712976663 ps
CPU time 6.69 seconds
Started Feb 04 12:56:20 PM PST 24
Finished Feb 04 12:56:29 PM PST 24
Peak memory 204016 kb
Host smart-8dff92f0-3e46-4aa2-a3e1-d8a3cfcc9885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814322128 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.814322128
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.3912251433
Short name T203
Test name
Test status
Simulation time 4140253269 ps
CPU time 14.64 seconds
Started Feb 04 12:56:05 PM PST 24
Finished Feb 04 12:56:21 PM PST 24
Peak memory 203964 kb
Host smart-64f25286-419b-4b46-b0f4-c49e202ecb18
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3912251433 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_
tl_access.3912251433
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.2918104482
Short name T100
Test name
Test status
Simulation time 1576514713 ps
CPU time 6.86 seconds
Started Feb 04 12:56:42 PM PST 24
Finished Feb 04 12:56:51 PM PST 24
Peak memory 203896 kb
Host smart-3df0288c-e822-4569-9b9a-179e5a696718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918104482 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.2918104482
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.1149277736
Short name T170
Test name
Test status
Simulation time 55822204 ps
CPU time 0.71 seconds
Started Feb 04 12:56:44 PM PST 24
Finished Feb 04 12:56:48 PM PST 24
Peak memory 203628 kb
Host smart-10ec9b03-f97e-4875-b019-d685681ce423
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149277736 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.1149277736
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.3909192622
Short name T240
Test name
Test status
Simulation time 1059626169 ps
CPU time 2.1 seconds
Started Feb 04 12:56:12 PM PST 24
Finished Feb 04 12:56:16 PM PST 24
Peak memory 204012 kb
Host smart-b68644fc-4f62-4ef7-a04f-175d34bb3531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909192622 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.3909192622
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.1876409567
Short name T187
Test name
Test status
Simulation time 1166406044 ps
CPU time 6.1 seconds
Started Feb 04 12:56:14 PM PST 24
Finished Feb 04 12:56:22 PM PST 24
Peak memory 204060 kb
Host smart-1355286c-f9c6-460c-87f7-cde0b4afe389
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1876409567 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.1876409567
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.1047643922
Short name T176
Test name
Test status
Simulation time 1602633774 ps
CPU time 3.58 seconds
Started Feb 04 12:56:12 PM PST 24
Finished Feb 04 12:56:18 PM PST 24
Peak memory 203928 kb
Host smart-0f5e6a19-c5c0-4e42-be37-d82fdc27540e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047643922 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.1047643922
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.1665622024
Short name T48
Test name
Test status
Simulation time 59250888 ps
CPU time 0.62 seconds
Started Feb 04 12:56:15 PM PST 24
Finished Feb 04 12:56:18 PM PST 24
Peak memory 203644 kb
Host smart-5ed95f97-3dfb-4449-8a8b-ab063d6d3e91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665622024 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.1665622024
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.1910305209
Short name T16
Test name
Test status
Simulation time 36812342783 ps
CPU time 37.2 seconds
Started Feb 04 12:56:15 PM PST 24
Finished Feb 04 12:56:55 PM PST 24
Peak memory 204116 kb
Host smart-d8e972ea-dbd1-46a5-9b99-045261b6cb12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910305209 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.1910305209
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.975574264
Short name T199
Test name
Test status
Simulation time 4604298274 ps
CPU time 5.21 seconds
Started Feb 04 12:56:10 PM PST 24
Finished Feb 04 12:56:16 PM PST 24
Peak memory 204156 kb
Host smart-df048f4b-4e5b-4679-8f9a-f107d9e0c57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975574264 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.975574264
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.1588974422
Short name T71
Test name
Test status
Simulation time 3515728123 ps
CPU time 7.48 seconds
Started Feb 04 12:56:09 PM PST 24
Finished Feb 04 12:56:18 PM PST 24
Peak memory 204096 kb
Host smart-6002870e-4fb0-4ef8-a303-673f0510a6dc
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1588974422 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_
tl_access.1588974422
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.1770800564
Short name T237
Test name
Test status
Simulation time 434848719 ps
CPU time 1.5 seconds
Started Feb 04 12:56:13 PM PST 24
Finished Feb 04 12:56:16 PM PST 24
Peak memory 204040 kb
Host smart-a7b2efbc-2f30-44af-a220-4c974ffe2c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770800564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.1770800564
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.2113596725
Short name T128
Test name
Test status
Simulation time 17069975 ps
CPU time 0.71 seconds
Started Feb 04 12:56:15 PM PST 24
Finished Feb 04 12:56:18 PM PST 24
Peak memory 203648 kb
Host smart-9b48e968-01a6-40e5-bc71-39a26c188c3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113596725 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.2113596725
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.905729627
Short name T204
Test name
Test status
Simulation time 1943848178 ps
CPU time 7.72 seconds
Started Feb 04 12:56:10 PM PST 24
Finished Feb 04 12:56:19 PM PST 24
Peak memory 203996 kb
Host smart-e991b43e-6be5-4b3d-b9e1-c20fec797b21
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=905729627 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_t
l_access.905729627
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.3346602930
Short name T229
Test name
Test status
Simulation time 3522759096 ps
CPU time 10.92 seconds
Started Feb 04 12:56:14 PM PST 24
Finished Feb 04 12:56:27 PM PST 24
Peak memory 204120 kb
Host smart-6b9be094-f8e3-44cb-8693-e7404fff1ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346602930 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.3346602930
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.679874062
Short name T165
Test name
Test status
Simulation time 24178563 ps
CPU time 0.71 seconds
Started Feb 04 12:56:25 PM PST 24
Finished Feb 04 12:56:33 PM PST 24
Peak memory 203764 kb
Host smart-f55a2dd3-b1e9-4bb6-b541-47388b473fd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679874062 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.679874062
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.2561962328
Short name T200
Test name
Test status
Simulation time 265400329 ps
CPU time 2.07 seconds
Started Feb 04 12:56:23 PM PST 24
Finished Feb 04 12:56:27 PM PST 24
Peak memory 204016 kb
Host smart-8988549c-d0aa-4d2b-a0c5-a9492087ed22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561962328 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.2561962328
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.3489037896
Short name T184
Test name
Test status
Simulation time 6097468896 ps
CPU time 8.84 seconds
Started Feb 04 12:56:26 PM PST 24
Finished Feb 04 12:56:42 PM PST 24
Peak memory 204120 kb
Host smart-9732600a-39f1-498b-bf4f-96990e3c9f4a
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3489037896 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_
tl_access.3489037896
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.4211947665
Short name T12
Test name
Test status
Simulation time 1889589056 ps
CPU time 4.95 seconds
Started Feb 04 12:56:11 PM PST 24
Finished Feb 04 12:56:17 PM PST 24
Peak memory 204004 kb
Host smart-e8e598f5-aa68-458d-821e-b945b0dad3c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211947665 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.4211947665
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.3517261132
Short name T148
Test name
Test status
Simulation time 21776506 ps
CPU time 0.68 seconds
Started Feb 04 12:56:09 PM PST 24
Finished Feb 04 12:56:10 PM PST 24
Peak memory 203680 kb
Host smart-dfca5d5e-8202-439c-be56-f734f7cc3598
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517261132 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.3517261132
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.3070504152
Short name T17
Test name
Test status
Simulation time 8641896506 ps
CPU time 19.48 seconds
Started Feb 04 12:56:25 PM PST 24
Finished Feb 04 12:56:51 PM PST 24
Peak memory 204208 kb
Host smart-8dff8034-7578-45f4-93c5-ff16ac4350ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070504152 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.3070504152
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.1088777551
Short name T73
Test name
Test status
Simulation time 1403095305 ps
CPU time 4.45 seconds
Started Feb 04 12:56:14 PM PST 24
Finished Feb 04 12:56:20 PM PST 24
Peak memory 203976 kb
Host smart-70aae50b-c47f-4413-b8b6-db46510e5b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088777551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.1088777551
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.53476018
Short name T13
Test name
Test status
Simulation time 5320696782 ps
CPU time 6.9 seconds
Started Feb 04 12:56:24 PM PST 24
Finished Feb 04 12:56:33 PM PST 24
Peak memory 204136 kb
Host smart-2f23d0a4-d3ea-46ca-b4fe-9830540524f1
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=53476018 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_tl
_access.53476018
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.3157397464
Short name T182
Test name
Test status
Simulation time 1270922407 ps
CPU time 3.9 seconds
Started Feb 04 12:56:27 PM PST 24
Finished Feb 04 12:56:38 PM PST 24
Peak memory 204024 kb
Host smart-5326b2c9-6fc3-4815-b502-2c6dca59dc35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157397464 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.3157397464
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.3701103455
Short name T146
Test name
Test status
Simulation time 34605924 ps
CPU time 0.69 seconds
Started Feb 04 12:56:25 PM PST 24
Finished Feb 04 12:56:33 PM PST 24
Peak memory 203740 kb
Host smart-f5ea2dee-f3d3-4e7a-8a4e-5e0319de8903
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701103455 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.3701103455
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.102211116
Short name T232
Test name
Test status
Simulation time 5027803252 ps
CPU time 12.19 seconds
Started Feb 04 12:56:11 PM PST 24
Finished Feb 04 12:56:24 PM PST 24
Peak memory 204148 kb
Host smart-67404d69-048f-4d81-884c-e862a61630c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102211116 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.102211116
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.2408662576
Short name T223
Test name
Test status
Simulation time 2228891291 ps
CPU time 9.95 seconds
Started Feb 04 12:56:18 PM PST 24
Finished Feb 04 12:56:30 PM PST 24
Peak memory 204080 kb
Host smart-e5fe90bb-48ac-4407-a13d-ab3848b63c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408662576 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.2408662576
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.2920343767
Short name T69
Test name
Test status
Simulation time 2415897215 ps
CPU time 13.26 seconds
Started Feb 04 12:56:25 PM PST 24
Finished Feb 04 12:56:45 PM PST 24
Peak memory 204216 kb
Host smart-4b682f27-63da-4e39-818f-c159ffc7e5a5
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2920343767 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_
tl_access.2920343767
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.2395885891
Short name T239
Test name
Test status
Simulation time 4717277134 ps
CPU time 13.07 seconds
Started Feb 04 12:56:12 PM PST 24
Finished Feb 04 12:56:27 PM PST 24
Peak memory 204072 kb
Host smart-2e29aae5-557d-4342-a4f1-128a38a122db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395885891 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.2395885891
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.3175366666
Short name T147
Test name
Test status
Simulation time 63510869 ps
CPU time 0.67 seconds
Started Feb 04 12:55:55 PM PST 24
Finished Feb 04 12:55:57 PM PST 24
Peak memory 203632 kb
Host smart-fc9dc5a1-8307-4237-823f-cad8a82a7e47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175366666 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.3175366666
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.2695858118
Short name T189
Test name
Test status
Simulation time 3846963688 ps
CPU time 8.54 seconds
Started Feb 04 12:56:10 PM PST 24
Finished Feb 04 12:56:19 PM PST 24
Peak memory 204084 kb
Host smart-f695eee3-0f7a-4046-a1df-5a157f9e498e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695858118 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.2695858118
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.1049401617
Short name T214
Test name
Test status
Simulation time 2421190516 ps
CPU time 7.93 seconds
Started Feb 04 12:56:03 PM PST 24
Finished Feb 04 12:56:13 PM PST 24
Peak memory 204216 kb
Host smart-2c9be29d-6876-4874-951f-2b48d5ed7cb4
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1049401617 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.1049401617
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.4154238350
Short name T185
Test name
Test status
Simulation time 101051423 ps
CPU time 0.87 seconds
Started Feb 04 12:56:13 PM PST 24
Finished Feb 04 12:56:16 PM PST 24
Peak memory 203516 kb
Host smart-f1aaaaaa-ee60-4d85-973d-0f4f5150a9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154238350 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.4154238350
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.3394610175
Short name T194
Test name
Test status
Simulation time 2189325117 ps
CPU time 6.02 seconds
Started Feb 04 12:56:15 PM PST 24
Finished Feb 04 12:56:23 PM PST 24
Peak memory 204096 kb
Host smart-b19cb81c-d368-4bdc-9504-1a4172cbb07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394610175 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.3394610175
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.1777241770
Short name T36
Test name
Test status
Simulation time 149357409 ps
CPU time 0.98 seconds
Started Feb 04 12:55:53 PM PST 24
Finished Feb 04 12:55:57 PM PST 24
Peak memory 219720 kb
Host smart-39eafac1-51bc-4bad-8975-2f3a77eb362a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777241770 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.1777241770
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.1440662189
Short name T161
Test name
Test status
Simulation time 49749307 ps
CPU time 0.65 seconds
Started Feb 04 12:56:25 PM PST 24
Finished Feb 04 12:56:27 PM PST 24
Peak memory 203640 kb
Host smart-2dc079bf-290f-4703-b7a6-70c5be871a7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440662189 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.1440662189
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.5521425
Short name T168
Test name
Test status
Simulation time 23314206 ps
CPU time 0.62 seconds
Started Feb 04 12:56:22 PM PST 24
Finished Feb 04 12:56:25 PM PST 24
Peak memory 203652 kb
Host smart-b665d6ab-abde-4ff9-ab57-ef9047d8c487
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5521425 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.5521425
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.1757053070
Short name T29
Test name
Test status
Simulation time 53003894 ps
CPU time 0.69 seconds
Started Feb 04 12:56:32 PM PST 24
Finished Feb 04 12:56:35 PM PST 24
Peak memory 203676 kb
Host smart-5d2b2da3-9166-402d-b3e1-883a7a909b1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757053070 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.1757053070
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.3578514886
Short name T155
Test name
Test status
Simulation time 34866003 ps
CPU time 0.66 seconds
Started Feb 04 12:56:27 PM PST 24
Finished Feb 04 12:56:35 PM PST 24
Peak memory 203652 kb
Host smart-d807f21a-2167-4262-bee4-6d45ba0a9040
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578514886 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.3578514886
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.3210972338
Short name T225
Test name
Test status
Simulation time 28191449 ps
CPU time 0.69 seconds
Started Feb 04 12:56:23 PM PST 24
Finished Feb 04 12:56:26 PM PST 24
Peak memory 203640 kb
Host smart-84a48a96-0ef5-4668-ad1c-f745d08473fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210972338 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.3210972338
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.3794918905
Short name T167
Test name
Test status
Simulation time 22667067 ps
CPU time 0.71 seconds
Started Feb 04 12:56:24 PM PST 24
Finished Feb 04 12:56:27 PM PST 24
Peak memory 203564 kb
Host smart-de89532a-9ff4-4f95-9ce4-9fbf5499072b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794918905 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.3794918905
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.1094208436
Short name T181
Test name
Test status
Simulation time 43268708 ps
CPU time 0.65 seconds
Started Feb 04 12:56:28 PM PST 24
Finished Feb 04 12:56:35 PM PST 24
Peak memory 203632 kb
Host smart-e2809005-790c-4c4b-8d2d-bff948cd38f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094208436 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.1094208436
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.96292237
Short name T159
Test name
Test status
Simulation time 69634240 ps
CPU time 0.67 seconds
Started Feb 04 12:56:23 PM PST 24
Finished Feb 04 12:56:26 PM PST 24
Peak memory 203608 kb
Host smart-f3a6146b-4031-487b-86d3-3b98b430f83d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96292237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.96292237
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.4250890666
Short name T212
Test name
Test status
Simulation time 29880790 ps
CPU time 0.69 seconds
Started Feb 04 12:56:28 PM PST 24
Finished Feb 04 12:56:35 PM PST 24
Peak memory 203648 kb
Host smart-b927ecd5-2229-4cf7-ac84-79584f0c1593
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250890666 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.4250890666
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.3530278006
Short name T216
Test name
Test status
Simulation time 105643887 ps
CPU time 0.66 seconds
Started Feb 04 12:56:29 PM PST 24
Finished Feb 04 12:56:35 PM PST 24
Peak memory 203628 kb
Host smart-3839261e-a926-41dc-8d63-3d3b2c644651
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530278006 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.3530278006
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.3226368222
Short name T23
Test name
Test status
Simulation time 23578090503 ps
CPU time 46.62 seconds
Started Feb 04 12:55:58 PM PST 24
Finished Feb 04 12:56:47 PM PST 24
Peak memory 204068 kb
Host smart-fb210c46-b0a9-42a8-9b20-31961c47fa07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226368222 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.3226368222
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.2889345358
Short name T198
Test name
Test status
Simulation time 9854889433 ps
CPU time 9.75 seconds
Started Feb 04 12:55:50 PM PST 24
Finished Feb 04 12:56:03 PM PST 24
Peak memory 204156 kb
Host smart-90342ca9-8ce9-4b10-9c61-c49690b10a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889345358 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.2889345358
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.1425126951
Short name T190
Test name
Test status
Simulation time 3731658244 ps
CPU time 14.9 seconds
Started Feb 04 12:55:59 PM PST 24
Finished Feb 04 12:56:17 PM PST 24
Peak memory 204068 kb
Host smart-46bfc344-71d0-43d8-8918-63d4a01b870a
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1425126951 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.1425126951
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.1772496427
Short name T178
Test name
Test status
Simulation time 62548839 ps
CPU time 0.8 seconds
Started Feb 04 12:55:58 PM PST 24
Finished Feb 04 12:56:00 PM PST 24
Peak memory 203592 kb
Host smart-d5a2554c-f43c-4d2b-84ba-d99909d6dd4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772496427 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.1772496427
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.3162397214
Short name T197
Test name
Test status
Simulation time 2025247845 ps
CPU time 9.39 seconds
Started Feb 04 12:55:59 PM PST 24
Finished Feb 04 12:56:10 PM PST 24
Peak memory 203948 kb
Host smart-0238e48f-004e-4434-8894-067d1e8aaac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162397214 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.3162397214
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.2963464948
Short name T67
Test name
Test status
Simulation time 100613247 ps
CPU time 1 seconds
Started Feb 04 12:55:56 PM PST 24
Finished Feb 04 12:56:00 PM PST 24
Peak memory 219740 kb
Host smart-dacabb75-4588-4514-bf34-fa5d88e2d29a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963464948 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.2963464948
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.1675211788
Short name T153
Test name
Test status
Simulation time 55229560 ps
CPU time 0.63 seconds
Started Feb 04 12:56:34 PM PST 24
Finished Feb 04 12:56:37 PM PST 24
Peak memory 203672 kb
Host smart-95ef5152-69ab-4715-bac0-4db44f17c83c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675211788 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.1675211788
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.3437519110
Short name T149
Test name
Test status
Simulation time 31591466 ps
CPU time 0.76 seconds
Started Feb 04 12:56:57 PM PST 24
Finished Feb 04 12:56:59 PM PST 24
Peak memory 203668 kb
Host smart-69d49023-098e-4875-9981-aad5d0d736da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437519110 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.3437519110
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.639322003
Short name T174
Test name
Test status
Simulation time 23581234 ps
CPU time 0.7 seconds
Started Feb 04 12:56:24 PM PST 24
Finished Feb 04 12:56:26 PM PST 24
Peak memory 203612 kb
Host smart-0da77199-3505-443b-b6b3-71dd6383730f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639322003 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.639322003
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.1064239168
Short name T175
Test name
Test status
Simulation time 44772305 ps
CPU time 0.65 seconds
Started Feb 04 12:56:29 PM PST 24
Finished Feb 04 12:56:35 PM PST 24
Peak memory 203600 kb
Host smart-61f6dd57-b43a-4e65-83dc-a3e6804cbe07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064239168 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.1064239168
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.19434534
Short name T180
Test name
Test status
Simulation time 28686994 ps
CPU time 0.69 seconds
Started Feb 04 12:56:55 PM PST 24
Finished Feb 04 12:56:58 PM PST 24
Peak memory 203672 kb
Host smart-4dc21d41-5847-4af1-98d0-af09900aeb98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19434534 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.19434534
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.3374972116
Short name T171
Test name
Test status
Simulation time 39507798 ps
CPU time 0.66 seconds
Started Feb 04 12:56:55 PM PST 24
Finished Feb 04 12:56:58 PM PST 24
Peak memory 203668 kb
Host smart-84f09601-50cb-440f-8d6e-971fadb29e95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374972116 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.3374972116
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.2422191603
Short name T150
Test name
Test status
Simulation time 37744793 ps
CPU time 0.68 seconds
Started Feb 04 12:56:47 PM PST 24
Finished Feb 04 12:56:50 PM PST 24
Peak memory 203624 kb
Host smart-954fc3c9-da8d-4265-825c-d58968d459e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422191603 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.2422191603
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.2393422405
Short name T173
Test name
Test status
Simulation time 38033172 ps
CPU time 0.65 seconds
Started Feb 04 12:56:34 PM PST 24
Finished Feb 04 12:56:37 PM PST 24
Peak memory 203668 kb
Host smart-f99dc964-90e1-4afd-947f-187d86b44199
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393422405 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.2393422405
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.2819957414
Short name T164
Test name
Test status
Simulation time 40951766 ps
CPU time 0.68 seconds
Started Feb 04 12:56:35 PM PST 24
Finished Feb 04 12:56:38 PM PST 24
Peak memory 203600 kb
Host smart-cba0c708-efcc-486d-a8d6-95e3bc427565
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819957414 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.2819957414
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.144838441
Short name T49
Test name
Test status
Simulation time 30301307 ps
CPU time 0.71 seconds
Started Feb 04 12:56:05 PM PST 24
Finished Feb 04 12:56:07 PM PST 24
Peak memory 203560 kb
Host smart-fd09d6a3-bac2-4803-ab81-806a5e46baf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144838441 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.144838441
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.2896916179
Short name T130
Test name
Test status
Simulation time 11696696229 ps
CPU time 41.54 seconds
Started Feb 04 12:55:55 PM PST 24
Finished Feb 04 12:56:39 PM PST 24
Peak memory 204100 kb
Host smart-ee234353-0ac0-4a53-8e33-b89eddacc03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896916179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.2896916179
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.4182259760
Short name T219
Test name
Test status
Simulation time 2725549044 ps
CPU time 6.64 seconds
Started Feb 04 12:56:00 PM PST 24
Finished Feb 04 12:56:09 PM PST 24
Peak memory 204108 kb
Host smart-8c8d6771-7c4b-41d4-9eef-24471282017a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182259760 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.4182259760
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.67508259
Short name T228
Test name
Test status
Simulation time 9731846881 ps
CPU time 12.39 seconds
Started Feb 04 12:55:59 PM PST 24
Finished Feb 04 12:56:14 PM PST 24
Peak memory 204140 kb
Host smart-99f0e54c-4b48-42cb-b687-d251bc1efd63
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=67508259 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_tl_
access.67508259
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.1450826283
Short name T206
Test name
Test status
Simulation time 29375146 ps
CPU time 0.65 seconds
Started Feb 04 12:55:53 PM PST 24
Finished Feb 04 12:55:56 PM PST 24
Peak memory 203552 kb
Host smart-c06687e9-9893-46b0-80bf-51149ed5d681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450826283 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.1450826283
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.14531685
Short name T63
Test name
Test status
Simulation time 2413304265 ps
CPU time 9.21 seconds
Started Feb 04 12:56:01 PM PST 24
Finished Feb 04 12:56:13 PM PST 24
Peak memory 204124 kb
Host smart-f7fb27f6-5434-4efa-88fb-860fe10c573b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14531685 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.14531685
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.2111028213
Short name T37
Test name
Test status
Simulation time 719038542 ps
CPU time 1.22 seconds
Started Feb 04 12:55:59 PM PST 24
Finished Feb 04 12:56:03 PM PST 24
Peak memory 219944 kb
Host smart-fdf4acdd-171e-4cc9-86d9-c176a5256063
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111028213 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.2111028213
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.2048225117
Short name T34
Test name
Test status
Simulation time 38732875 ps
CPU time 0.68 seconds
Started Feb 04 12:56:33 PM PST 24
Finished Feb 04 12:56:36 PM PST 24
Peak memory 203628 kb
Host smart-4676b72f-2c7e-4667-a115-174eeb5cbfeb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048225117 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.2048225117
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.3573324484
Short name T163
Test name
Test status
Simulation time 55861333 ps
CPU time 0.64 seconds
Started Feb 04 12:56:38 PM PST 24
Finished Feb 04 12:56:40 PM PST 24
Peak memory 203584 kb
Host smart-ea05b3aa-f5ab-4c70-88ba-44da7e8ecab1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573324484 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.3573324484
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.648169237
Short name T151
Test name
Test status
Simulation time 17019484 ps
CPU time 0.67 seconds
Started Feb 04 12:56:33 PM PST 24
Finished Feb 04 12:56:37 PM PST 24
Peak memory 203628 kb
Host smart-b4cdb70b-6c63-4465-a97a-bc63b58e3a1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648169237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.648169237
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.3978675261
Short name T166
Test name
Test status
Simulation time 35334262 ps
CPU time 0.66 seconds
Started Feb 04 12:56:51 PM PST 24
Finished Feb 04 12:56:56 PM PST 24
Peak memory 203496 kb
Host smart-431c0ba8-07f5-44c1-830c-9dd587fcb65a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978675261 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.3978675261
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.2933129794
Short name T154
Test name
Test status
Simulation time 38685017 ps
CPU time 0.66 seconds
Started Feb 04 12:56:47 PM PST 24
Finished Feb 04 12:56:50 PM PST 24
Peak memory 203632 kb
Host smart-431fadd8-d7dc-4976-bc3a-6e49f09aeb20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933129794 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.2933129794
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.484531992
Short name T3
Test name
Test status
Simulation time 34382240 ps
CPU time 0.65 seconds
Started Feb 04 12:56:46 PM PST 24
Finished Feb 04 12:56:49 PM PST 24
Peak memory 203660 kb
Host smart-edecaafe-8e13-43aa-8421-088f9d6253ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484531992 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.484531992
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.1346207419
Short name T172
Test name
Test status
Simulation time 61873040 ps
CPU time 0.68 seconds
Started Feb 04 12:56:45 PM PST 24
Finished Feb 04 12:56:49 PM PST 24
Peak memory 203652 kb
Host smart-4c96ec12-4bfe-4c1b-a005-b1a2c6d58670
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346207419 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.1346207419
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.2216000277
Short name T156
Test name
Test status
Simulation time 187881422 ps
CPU time 0.66 seconds
Started Feb 04 12:56:51 PM PST 24
Finished Feb 04 12:56:56 PM PST 24
Peak memory 203652 kb
Host smart-4ecf60fa-a9b8-413f-bcd0-50cdd8063b8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216000277 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.2216000277
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.3027731266
Short name T158
Test name
Test status
Simulation time 118575345 ps
CPU time 0.73 seconds
Started Feb 04 12:56:53 PM PST 24
Finished Feb 04 12:56:57 PM PST 24
Peak memory 203640 kb
Host smart-7b92120c-d23b-4230-956e-0f4cfce89b53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027731266 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.3027731266
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.1750333713
Short name T157
Test name
Test status
Simulation time 20590899 ps
CPU time 0.66 seconds
Started Feb 04 12:56:48 PM PST 24
Finished Feb 04 12:56:54 PM PST 24
Peak memory 203624 kb
Host smart-3a5c925c-4d93-4ccf-9186-e5de01fceca6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750333713 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.1750333713
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.664314891
Short name T169
Test name
Test status
Simulation time 104479384 ps
CPU time 0.65 seconds
Started Feb 04 12:55:50 PM PST 24
Finished Feb 04 12:55:54 PM PST 24
Peak memory 203592 kb
Host smart-80b8737e-8fc0-453e-a98f-08bca6811905
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664314891 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.664314891
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.2384072223
Short name T191
Test name
Test status
Simulation time 6826239984 ps
CPU time 25.42 seconds
Started Feb 04 12:55:55 PM PST 24
Finished Feb 04 12:56:23 PM PST 24
Peak memory 204160 kb
Host smart-56acf555-80cf-4243-85c2-73d571061bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384072223 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.2384072223
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.1159276797
Short name T129
Test name
Test status
Simulation time 16463145582 ps
CPU time 7.89 seconds
Started Feb 04 12:55:55 PM PST 24
Finished Feb 04 12:56:06 PM PST 24
Peak memory 204120 kb
Host smart-efe8f0e8-3cdf-448a-a7eb-bbc483d347c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159276797 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.1159276797
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.3852401084
Short name T68
Test name
Test status
Simulation time 3427147129 ps
CPU time 7.47 seconds
Started Feb 04 12:55:56 PM PST 24
Finished Feb 04 12:56:06 PM PST 24
Peak memory 204160 kb
Host smart-9a4d211e-f165-4990-8972-6e9091fab914
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3852401084 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t
l_access.3852401084
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.3072809059
Short name T231
Test name
Test status
Simulation time 5009792056 ps
CPU time 9.17 seconds
Started Feb 04 12:56:01 PM PST 24
Finished Feb 04 12:56:13 PM PST 24
Peak memory 204120 kb
Host smart-d310a4a3-3a20-48d1-a910-9a3500188a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072809059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.3072809059
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.2436408960
Short name T160
Test name
Test status
Simulation time 18817860 ps
CPU time 0.67 seconds
Started Feb 04 12:56:10 PM PST 24
Finished Feb 04 12:56:11 PM PST 24
Peak memory 203672 kb
Host smart-ca2fed26-ea63-4126-84ad-ddb7f60b6390
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436408960 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.2436408960
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.499662698
Short name T215
Test name
Test status
Simulation time 7907627002 ps
CPU time 8.34 seconds
Started Feb 04 12:56:05 PM PST 24
Finished Feb 04 12:56:15 PM PST 24
Peak memory 203528 kb
Host smart-038f9ed9-77b0-4333-ae40-ad295df09981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499662698 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.499662698
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.2338164223
Short name T221
Test name
Test status
Simulation time 3738852140 ps
CPU time 4.31 seconds
Started Feb 04 12:56:05 PM PST 24
Finished Feb 04 12:56:11 PM PST 24
Peak memory 204164 kb
Host smart-79ed0773-190d-43f2-81aa-3ba00eee9279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338164223 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.2338164223
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.118401495
Short name T179
Test name
Test status
Simulation time 4908803562 ps
CPU time 6.96 seconds
Started Feb 04 12:56:02 PM PST 24
Finished Feb 04 12:56:11 PM PST 24
Peak memory 204180 kb
Host smart-80248411-874a-4a8f-a468-fffbad2a2da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118401495 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.118401495
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.2515734263
Short name T50
Test name
Test status
Simulation time 46165873 ps
CPU time 0.64 seconds
Started Feb 04 12:56:14 PM PST 24
Finished Feb 04 12:56:18 PM PST 24
Peak memory 203652 kb
Host smart-6fa522f2-e976-46d3-a08c-623daa553621
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515734263 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.2515734263
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.3153539986
Short name T188
Test name
Test status
Simulation time 8820970660 ps
CPU time 6.84 seconds
Started Feb 04 12:56:24 PM PST 24
Finished Feb 04 12:56:32 PM PST 24
Peak memory 204164 kb
Host smart-61eafccf-0109-4be2-9fb5-737cfd97d0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153539986 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.3153539986
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.3218945875
Short name T202
Test name
Test status
Simulation time 2593473137 ps
CPU time 12.31 seconds
Started Feb 04 12:56:31 PM PST 24
Finished Feb 04 12:56:47 PM PST 24
Peak memory 203960 kb
Host smart-c6b8c9d5-0bae-47a4-804a-7bce753eb617
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3218945875 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.3218945875
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.3738186344
Short name T209
Test name
Test status
Simulation time 2487714210 ps
CPU time 10.23 seconds
Started Feb 04 12:56:10 PM PST 24
Finished Feb 04 12:56:21 PM PST 24
Peak memory 204180 kb
Host smart-ecda3230-34df-457f-b1b4-62a8634c5bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738186344 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.3738186344
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.2035556467
Short name T2
Test name
Test status
Simulation time 33648713 ps
CPU time 0.64 seconds
Started Feb 04 12:56:23 PM PST 24
Finished Feb 04 12:56:26 PM PST 24
Peak memory 203680 kb
Host smart-fd1b2f0a-0be4-4461-a76b-e8c63b601c62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035556467 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.2035556467
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.806011755
Short name T226
Test name
Test status
Simulation time 336023841 ps
CPU time 1.22 seconds
Started Feb 04 12:56:16 PM PST 24
Finished Feb 04 12:56:19 PM PST 24
Peak memory 204056 kb
Host smart-adcbb4d0-fe09-4bb4-ac9c-8314cfc8ed23
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=806011755 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_tl
_access.806011755
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.3353379802
Short name T35
Test name
Test status
Simulation time 10816172423 ps
CPU time 12.47 seconds
Started Feb 04 12:56:13 PM PST 24
Finished Feb 04 12:56:27 PM PST 24
Peak memory 204132 kb
Host smart-94c48b32-4308-4fa8-8bc6-5e051fcb4487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353379802 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.3353379802
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_stress_all.44886023
Short name T8
Test name
Test status
Simulation time 1966251674 ps
CPU time 6.09 seconds
Started Feb 04 12:56:24 PM PST 24
Finished Feb 04 12:56:32 PM PST 24
Peak memory 203924 kb
Host smart-b65daaec-d4f8-4fb3-8a70-6297b8d3feb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44886023 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.44886023
Directory /workspace/8.rv_dm_stress_all/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.3755281849
Short name T64
Test name
Test status
Simulation time 45927513 ps
CPU time 0.65 seconds
Started Feb 04 12:56:24 PM PST 24
Finished Feb 04 12:56:26 PM PST 24
Peak memory 203672 kb
Host smart-e0d1ecfc-8ccf-4aab-95ca-c2751d93c0f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755281849 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.3755281849
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.177948029
Short name T195
Test name
Test status
Simulation time 25966494278 ps
CPU time 21.53 seconds
Started Feb 04 12:56:03 PM PST 24
Finished Feb 04 12:56:26 PM PST 24
Peak memory 204176 kb
Host smart-c64d1334-51ce-4bcd-ad68-1527df21d5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177948029 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.177948029
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.1339457261
Short name T211
Test name
Test status
Simulation time 1906188276 ps
CPU time 4.08 seconds
Started Feb 04 12:56:10 PM PST 24
Finished Feb 04 12:56:15 PM PST 24
Peak memory 204040 kb
Host smart-6ec5fdf1-3b0c-4768-932a-3f6f1c24d710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339457261 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.1339457261
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.148740106
Short name T205
Test name
Test status
Simulation time 5528662833 ps
CPU time 18.97 seconds
Started Feb 04 12:56:44 PM PST 24
Finished Feb 04 12:57:06 PM PST 24
Peak memory 204096 kb
Host smart-db4b08fe-2566-4805-8d3f-d44556fc7e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148740106 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.148740106
Directory /workspace/9.rv_dm_sba_tl_access/latest
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