Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
87.80 92.79 78.70 89.36 78.21 82.48 97.75 95.34


Total test records in report: 361
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html
T119 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.3087367249 Feb 18 01:56:40 PM PST 24 Feb 18 01:56:52 PM PST 24 697818830 ps
T129 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.1198378000 Feb 18 01:56:46 PM PST 24 Feb 18 01:56:56 PM PST 24 231442004 ps
T271 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.2542595407 Feb 18 01:56:38 PM PST 24 Feb 18 01:56:53 PM PST 24 805918819 ps
T272 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3700444112 Feb 18 01:56:32 PM PST 24 Feb 18 01:56:40 PM PST 24 58453257 ps
T273 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.851716882 Feb 18 01:56:47 PM PST 24 Feb 18 01:56:51 PM PST 24 733261272 ps
T120 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1655610756 Feb 18 01:56:42 PM PST 24 Feb 18 01:56:49 PM PST 24 718605536 ps
T274 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.3562653696 Feb 18 01:56:30 PM PST 24 Feb 18 01:56:40 PM PST 24 179311394 ps
T275 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.922046183 Feb 18 01:56:25 PM PST 24 Feb 18 01:56:35 PM PST 24 364436814 ps
T276 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2389612780 Feb 18 01:56:41 PM PST 24 Feb 18 01:56:45 PM PST 24 68571800 ps
T277 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.2313512011 Feb 18 01:56:23 PM PST 24 Feb 18 01:56:37 PM PST 24 151381923 ps
T278 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2992697359 Feb 18 01:56:20 PM PST 24 Feb 18 01:56:33 PM PST 24 325850189 ps
T279 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.4165966431 Feb 18 01:56:43 PM PST 24 Feb 18 01:56:47 PM PST 24 145580791 ps
T280 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.244841771 Feb 18 01:56:44 PM PST 24 Feb 18 01:56:48 PM PST 24 452993844 ps
T281 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2474975011 Feb 18 01:56:19 PM PST 24 Feb 18 01:56:31 PM PST 24 411129207 ps
T282 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.3546840372 Feb 18 01:56:20 PM PST 24 Feb 18 01:56:29 PM PST 24 393342033 ps
T105 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.3573444794 Feb 18 01:56:22 PM PST 24 Feb 18 01:56:34 PM PST 24 300812535 ps
T283 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3472780482 Feb 18 01:56:22 PM PST 24 Feb 18 01:56:39 PM PST 24 1816071791 ps
T284 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.4144213158 Feb 18 01:56:16 PM PST 24 Feb 18 01:56:26 PM PST 24 266615850 ps
T285 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.512976361 Feb 18 01:56:15 PM PST 24 Feb 18 01:56:24 PM PST 24 40470575 ps
T106 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.4156605109 Feb 18 01:56:21 PM PST 24 Feb 18 01:56:35 PM PST 24 566603006 ps
T131 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.3791156123 Feb 18 01:56:20 PM PST 24 Feb 18 01:56:37 PM PST 24 1661400309 ps
T286 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.3018548535 Feb 18 01:56:34 PM PST 24 Feb 18 01:56:41 PM PST 24 52962810 ps
T107 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.3837862520 Feb 18 01:56:20 PM PST 24 Feb 18 01:56:32 PM PST 24 149167124 ps
T287 /workspace/coverage/cover_reg_top/13.rv_dm_tap_fsm_rand_reset.667145016 Feb 18 01:56:24 PM PST 24 Feb 18 01:56:51 PM PST 24 9582998219 ps
T288 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2517867810 Feb 18 01:56:22 PM PST 24 Feb 18 01:56:35 PM PST 24 316669526 ps
T132 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.102625371 Feb 18 01:56:43 PM PST 24 Feb 18 01:57:05 PM PST 24 1187518374 ps
T289 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.1908145502 Feb 18 01:56:43 PM PST 24 Feb 18 01:56:51 PM PST 24 734108643 ps
T290 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.3504039145 Feb 18 01:56:22 PM PST 24 Feb 18 01:56:31 PM PST 24 24973200 ps
T291 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3334081756 Feb 18 01:56:22 PM PST 24 Feb 18 01:56:31 PM PST 24 170845799 ps
T292 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.858353352 Feb 18 01:56:19 PM PST 24 Feb 18 01:56:28 PM PST 24 186088495 ps
T293 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.3680597397 Feb 18 01:56:20 PM PST 24 Feb 18 01:56:29 PM PST 24 88297333 ps
T294 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.2096866591 Feb 18 01:56:27 PM PST 24 Feb 18 01:56:44 PM PST 24 386457008 ps
T295 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.2254189939 Feb 18 01:56:20 PM PST 24 Feb 18 01:56:29 PM PST 24 16290857 ps
T130 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.3390777831 Feb 18 01:56:30 PM PST 24 Feb 18 01:56:57 PM PST 24 5062205054 ps
T108 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3531701518 Feb 18 01:56:22 PM PST 24 Feb 18 01:56:34 PM PST 24 208184289 ps
T296 /workspace/coverage/cover_reg_top/20.rv_dm_tap_fsm_rand_reset.3498435664 Feb 18 01:56:45 PM PST 24 Feb 18 01:56:58 PM PST 24 12988920238 ps
T297 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.2713013313 Feb 18 01:56:09 PM PST 24 Feb 18 01:56:15 PM PST 24 71682183 ps
T298 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.1839782463 Feb 18 01:56:26 PM PST 24 Feb 18 01:56:40 PM PST 24 94965044 ps
T299 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1080555025 Feb 18 01:56:21 PM PST 24 Feb 18 01:56:30 PM PST 24 116649047 ps
T98 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.3502334186 Feb 18 01:56:19 PM PST 24 Feb 18 01:56:28 PM PST 24 876274942 ps
T300 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1370633921 Feb 18 01:56:29 PM PST 24 Feb 18 01:56:40 PM PST 24 216383170 ps
T301 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.751253819 Feb 18 01:56:25 PM PST 24 Feb 18 01:56:44 PM PST 24 3334965271 ps
T302 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1395510308 Feb 18 01:56:31 PM PST 24 Feb 18 01:56:40 PM PST 24 57372044 ps
T303 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.2209222293 Feb 18 01:56:11 PM PST 24 Feb 18 01:56:19 PM PST 24 94966243 ps
T304 /workspace/coverage/cover_reg_top/16.rv_dm_tap_fsm_rand_reset.1454488950 Feb 18 01:56:47 PM PST 24 Feb 18 01:57:14 PM PST 24 32693128064 ps
T305 /workspace/coverage/cover_reg_top/11.rv_dm_tap_fsm_rand_reset.214859265 Feb 18 01:56:32 PM PST 24 Feb 18 01:57:00 PM PST 24 6397358900 ps
T306 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2889977038 Feb 18 01:56:24 PM PST 24 Feb 18 01:56:35 PM PST 24 539701410 ps
T307 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.200813668 Feb 18 01:56:23 PM PST 24 Feb 18 01:56:31 PM PST 24 60575429 ps
T308 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.4020862485 Feb 18 01:56:11 PM PST 24 Feb 18 01:56:28 PM PST 24 566024351 ps
T309 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.971195593 Feb 18 01:56:24 PM PST 24 Feb 18 01:56:35 PM PST 24 266331592 ps
T136 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.4229097535 Feb 18 01:56:15 PM PST 24 Feb 18 01:56:33 PM PST 24 1032003897 ps
T310 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2060840866 Feb 18 01:56:22 PM PST 24 Feb 18 01:56:31 PM PST 24 32883649 ps
T135 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3383214374 Feb 18 01:56:24 PM PST 24 Feb 18 01:56:42 PM PST 24 629231855 ps
T311 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3304203741 Feb 18 01:56:17 PM PST 24 Feb 18 01:56:28 PM PST 24 366471130 ps
T312 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.191791415 Feb 18 01:56:40 PM PST 24 Feb 18 01:56:47 PM PST 24 110271537 ps
T109 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.1768462867 Feb 18 01:56:23 PM PST 24 Feb 18 01:56:38 PM PST 24 1160140447 ps
T313 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2155364206 Feb 18 01:56:12 PM PST 24 Feb 18 01:57:01 PM PST 24 12387402736 ps
T314 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.1572014516 Feb 18 01:56:30 PM PST 24 Feb 18 01:56:40 PM PST 24 61357410 ps
T315 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.3071040342 Feb 18 01:56:32 PM PST 24 Feb 18 01:56:40 PM PST 24 111340766 ps
T316 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.137639460 Feb 18 01:56:22 PM PST 24 Feb 18 01:56:45 PM PST 24 990208429 ps
T127 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.3069482819 Feb 18 01:56:45 PM PST 24 Feb 18 01:56:52 PM PST 24 1029896735 ps
T317 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1654504590 Feb 18 01:56:15 PM PST 24 Feb 18 01:56:58 PM PST 24 10494829541 ps
T318 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.907264100 Feb 18 01:56:16 PM PST 24 Feb 18 01:57:11 PM PST 24 11930471523 ps
T319 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.3219623079 Feb 18 01:56:43 PM PST 24 Feb 18 01:56:52 PM PST 24 1567050531 ps
T320 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3701053331 Feb 18 01:56:44 PM PST 24 Feb 18 01:56:54 PM PST 24 465105058 ps
T321 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.2086226158 Feb 18 01:56:23 PM PST 24 Feb 18 01:58:24 PM PST 24 33953193332 ps
T322 /workspace/coverage/cover_reg_top/38.rv_dm_tap_fsm_rand_reset.2419089154 Feb 18 01:56:52 PM PST 24 Feb 18 01:57:08 PM PST 24 9005250639 ps
T323 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.29511305 Feb 18 01:56:43 PM PST 24 Feb 18 01:56:50 PM PST 24 201144628 ps
T324 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.4098715876 Feb 18 01:56:22 PM PST 24 Feb 18 01:56:50 PM PST 24 7312335451 ps
T325 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.1688102962 Feb 18 01:56:20 PM PST 24 Feb 18 01:56:45 PM PST 24 6655743244 ps
T326 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.3221088498 Feb 18 01:56:20 PM PST 24 Feb 18 01:56:30 PM PST 24 237753934 ps
T327 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.408120966 Feb 18 01:56:43 PM PST 24 Feb 18 01:56:46 PM PST 24 166329459 ps
T328 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.4200717654 Feb 18 01:56:17 PM PST 24 Feb 18 01:56:28 PM PST 24 353143894 ps
T329 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.3341159862 Feb 18 01:56:20 PM PST 24 Feb 18 01:56:29 PM PST 24 23498679 ps
T330 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1660083886 Feb 18 01:56:23 PM PST 24 Feb 18 01:56:32 PM PST 24 29691991 ps
T331 /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.2584394729 Feb 18 01:56:16 PM PST 24 Feb 18 01:56:36 PM PST 24 14201978596 ps
T133 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2417206815 Feb 18 01:56:19 PM PST 24 Feb 18 01:56:42 PM PST 24 532413152 ps
T332 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.2228528654 Feb 18 01:56:14 PM PST 24 Feb 18 01:56:23 PM PST 24 24532030 ps
T134 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.334846378 Feb 18 01:56:23 PM PST 24 Feb 18 01:56:41 PM PST 24 983346409 ps
T333 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.941816451 Feb 18 01:56:16 PM PST 24 Feb 18 01:56:31 PM PST 24 316181892 ps
T334 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.1241307999 Feb 18 01:56:33 PM PST 24 Feb 18 01:56:45 PM PST 24 121614495 ps
T335 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2062003285 Feb 18 01:56:23 PM PST 24 Feb 18 01:56:33 PM PST 24 471086079 ps
T336 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3919394248 Feb 18 01:56:18 PM PST 24 Feb 18 01:56:28 PM PST 24 88250355 ps
T99 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2123141739 Feb 18 01:56:10 PM PST 24 Feb 18 01:56:16 PM PST 24 292092892 ps
T337 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.387956819 Feb 18 01:56:33 PM PST 24 Feb 18 01:56:42 PM PST 24 465342329 ps
T338 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.2309108786 Feb 18 01:56:14 PM PST 24 Feb 18 01:56:23 PM PST 24 49458413 ps
T339 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.4157944570 Feb 18 01:56:19 PM PST 24 Feb 18 01:56:55 PM PST 24 5008859225 ps
T340 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.3380610974 Feb 18 01:56:26 PM PST 24 Feb 18 01:56:36 PM PST 24 47196048 ps
T341 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3677581119 Feb 18 01:56:56 PM PST 24 Feb 18 01:56:58 PM PST 24 84006102 ps
T342 /workspace/coverage/cover_reg_top/37.rv_dm_tap_fsm_rand_reset.1935796701 Feb 18 01:56:57 PM PST 24 Feb 18 01:57:24 PM PST 24 27528470249 ps
T343 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.3449327474 Feb 18 01:56:28 PM PST 24 Feb 18 01:57:34 PM PST 24 2792459810 ps
T344 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.1868413470 Feb 18 01:56:15 PM PST 24 Feb 18 01:56:25 PM PST 24 16913647 ps
T345 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.618830437 Feb 18 01:56:24 PM PST 24 Feb 18 01:56:33 PM PST 24 56878072 ps
T346 /workspace/coverage/cover_reg_top/36.rv_dm_tap_fsm_rand_reset.1368735730 Feb 18 01:56:55 PM PST 24 Feb 18 01:57:17 PM PST 24 6416677215 ps
T347 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.719786459 Feb 18 01:56:23 PM PST 24 Feb 18 01:56:33 PM PST 24 314990254 ps
T100 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.3022013561 Feb 18 01:56:21 PM PST 24 Feb 18 01:56:31 PM PST 24 2572520167 ps
T348 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3826056161 Feb 18 01:56:28 PM PST 24 Feb 18 01:56:40 PM PST 24 1757772735 ps
T349 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2184175167 Feb 18 01:56:12 PM PST 24 Feb 18 01:57:00 PM PST 24 26116149820 ps
T350 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.970883978 Feb 18 01:56:27 PM PST 24 Feb 18 01:56:40 PM PST 24 111834009 ps
T351 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2817081140 Feb 18 01:56:27 PM PST 24 Feb 18 01:56:38 PM PST 24 67957665 ps
T352 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.3021331378 Feb 18 01:56:13 PM PST 24 Feb 18 01:56:49 PM PST 24 764614436 ps
T353 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1382166981 Feb 18 01:56:24 PM PST 24 Feb 18 01:57:05 PM PST 24 4481314387 ps
T354 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1912446992 Feb 18 01:56:22 PM PST 24 Feb 18 01:56:33 PM PST 24 100200572 ps
T101 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.3007254831 Feb 18 01:56:14 PM PST 24 Feb 18 01:56:26 PM PST 24 1639691955 ps
T355 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2527333633 Feb 18 01:56:17 PM PST 24 Feb 18 01:56:27 PM PST 24 456689361 ps
T356 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1153420973 Feb 18 01:56:15 PM PST 24 Feb 18 01:56:28 PM PST 24 893445009 ps
T357 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3417073286 Feb 18 01:56:44 PM PST 24 Feb 18 01:56:54 PM PST 24 961754040 ps
T358 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.2702776477 Feb 18 01:56:23 PM PST 24 Feb 18 01:56:33 PM PST 24 196405065 ps
T359 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.191592598 Feb 18 01:56:20 PM PST 24 Feb 18 01:56:30 PM PST 24 803378827 ps
T360 /workspace/coverage/cover_reg_top/17.rv_dm_tap_fsm_rand_reset.331856817 Feb 18 01:56:51 PM PST 24 Feb 18 01:57:16 PM PST 24 14071647757 ps
T361 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.1710027078 Feb 18 01:56:46 PM PST 24 Feb 18 01:56:50 PM PST 24 81997119 ps

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.2551196830
Short name T1
Test name
Test status
Simulation time 17045948898 ps
CPU time 33.19 seconds
Started Feb 18 02:25:43 PM PST 24
Finished Feb 18 02:26:18 PM PST 24
Peak memory 204000 kb
Host smart-d7996b16-d5d9-433c-b647-de25bcc1a187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551196830 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.2551196830
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tap_fsm_rand_reset.2658807728
Short name T44
Test name
Test status
Simulation time 10593997197 ps
CPU time 8.68 seconds
Started Feb 18 01:56:36 PM PST 24
Finished Feb 18 01:56:51 PM PST 24
Peak memory 219812 kb
Host smart-b4140d85-5fab-4af1-9e09-51b0303ea5c0
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658807728 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rv_dm_tap_fsm_rand_reset.2658807728
Directory /workspace/12.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/7.rv_dm_stress_all.395792839
Short name T27
Test name
Test status
Simulation time 3030755364 ps
CPU time 2.95 seconds
Started Feb 18 02:25:38 PM PST 24
Finished Feb 18 02:25:43 PM PST 24
Peak memory 203900 kb
Host smart-abcd3b8c-1c92-4cba-a9c3-4346b2022da7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395792839 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.395792839
Directory /workspace/7.rv_dm_stress_all/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.3986533170
Short name T33
Test name
Test status
Simulation time 24001133 ps
CPU time 0.7 seconds
Started Feb 18 02:25:37 PM PST 24
Finished Feb 18 02:25:41 PM PST 24
Peak memory 203588 kb
Host smart-7fec7a76-a490-4387-9bf2-ba0e9de2cad9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986533170 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.3986533170
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tap_fsm_rand_reset.1569078549
Short name T74
Test name
Test status
Simulation time 5197898700 ps
CPU time 13.96 seconds
Started Feb 18 01:56:40 PM PST 24
Finished Feb 18 01:56:58 PM PST 24
Peak memory 220292 kb
Host smart-4a5b3f9c-2a08-4148-b651-31a29cdef9fe
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569078549 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rv_dm_tap_fsm_rand_reset.1569078549
Directory /workspace/14.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.2368976667
Short name T40
Test name
Test status
Simulation time 524909604 ps
CPU time 9.85 seconds
Started Feb 18 01:56:31 PM PST 24
Finished Feb 18 01:56:49 PM PST 24
Peak memory 211896 kb
Host smart-dce16b53-9d76-4325-ab17-050a7db144ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368976667 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.2
368976667
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all.2988879172
Short name T4
Test name
Test status
Simulation time 12478871746 ps
CPU time 11.77 seconds
Started Feb 18 02:25:03 PM PST 24
Finished Feb 18 02:25:17 PM PST 24
Peak memory 203912 kb
Host smart-5acb9464-30c4-4d2a-b950-a1aaba392ea7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988879172 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.2988879172
Directory /workspace/1.rv_dm_stress_all/latest

Test location /workspace/coverage/default/44.rv_dm_stress_all.3086359613
Short name T35
Test name
Test status
Simulation time 5260420671 ps
CPU time 5.19 seconds
Started Feb 18 02:26:59 PM PST 24
Finished Feb 18 02:27:08 PM PST 24
Peak memory 203868 kb
Host smart-526eb3f2-75fd-4bd1-a7b5-c6199affb288
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086359613 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.3086359613
Directory /workspace/44.rv_dm_stress_all/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.1350523985
Short name T15
Test name
Test status
Simulation time 6927189066 ps
CPU time 19.74 seconds
Started Feb 18 02:25:58 PM PST 24
Finished Feb 18 02:26:20 PM PST 24
Peak memory 203988 kb
Host smart-49f213bc-7255-47da-ad37-53933d8c6b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350523985 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.1350523985
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.1155938615
Short name T77
Test name
Test status
Simulation time 7100100873 ps
CPU time 20.48 seconds
Started Feb 18 01:56:51 PM PST 24
Finished Feb 18 01:57:13 PM PST 24
Peak memory 216040 kb
Host smart-b634245e-0f06-4716-bfc6-2c90f11b8a26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155938615 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.1
155938615
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2992697359
Short name T278
Test name
Test status
Simulation time 325850189 ps
CPU time 5.12 seconds
Started Feb 18 01:56:20 PM PST 24
Finished Feb 18 01:56:33 PM PST 24
Peak memory 212012 kb
Host smart-4efb6124-ccf9-4e45-9964-e972ae1e693c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992697359 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.2992697359
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.1618104494
Short name T48
Test name
Test status
Simulation time 52468915 ps
CPU time 1.52 seconds
Started Feb 18 01:56:46 PM PST 24
Finished Feb 18 01:56:49 PM PST 24
Peak memory 203680 kb
Host smart-4b11233d-0d76-4a5a-ac90-73407e001370
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618104494 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.1618104494
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/default/10.rv_dm_stress_all.2971576755
Short name T21
Test name
Test status
Simulation time 2954314878 ps
CPU time 10.02 seconds
Started Feb 18 02:25:44 PM PST 24
Finished Feb 18 02:25:55 PM PST 24
Peak memory 203764 kb
Host smart-7cf7123a-7282-4597-85d4-4cf3f9ee6b4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971576755 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.2971576755
Directory /workspace/10.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.2074974943
Short name T69
Test name
Test status
Simulation time 579709764 ps
CPU time 0.91 seconds
Started Feb 18 02:24:54 PM PST 24
Finished Feb 18 02:25:02 PM PST 24
Peak memory 218832 kb
Host smart-e292374c-ab96-4a85-aa7e-2b14df0036d0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074974943 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.2074974943
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.3077128047
Short name T128
Test name
Test status
Simulation time 1214396674 ps
CPU time 18.5 seconds
Started Feb 18 01:56:26 PM PST 24
Finished Feb 18 01:56:54 PM PST 24
Peak memory 213924 kb
Host smart-7f434be7-a6b1-4245-bf76-2b5e1e89d3cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077128047 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.3
077128047
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.3998371087
Short name T6
Test name
Test status
Simulation time 214600184 ps
CPU time 0.99 seconds
Started Feb 18 02:24:35 PM PST 24
Finished Feb 18 02:24:40 PM PST 24
Peak memory 203608 kb
Host smart-9653b640-ba8f-4a0f-b283-2b0746517a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998371087 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.3998371087
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.2524877035
Short name T61
Test name
Test status
Simulation time 173126181 ps
CPU time 0.69 seconds
Started Feb 18 02:26:34 PM PST 24
Finished Feb 18 02:26:38 PM PST 24
Peak memory 203600 kb
Host smart-9a6a9e65-32b4-4083-8e3d-f9ad36c3f2cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524877035 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.2524877035
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.2166542650
Short name T24
Test name
Test status
Simulation time 698412782 ps
CPU time 2.83 seconds
Started Feb 18 02:24:35 PM PST 24
Finished Feb 18 02:24:41 PM PST 24
Peak memory 203804 kb
Host smart-bea495ac-8d62-4644-84e2-87f37c6fe8d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166542650 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.2166542650
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.2891821832
Short name T60
Test name
Test status
Simulation time 141896885 ps
CPU time 6.68 seconds
Started Feb 18 01:56:38 PM PST 24
Finished Feb 18 01:56:50 PM PST 24
Peak memory 203744 kb
Host smart-488e7c7f-b30b-4bee-88de-c02ae1a23ad4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891821832 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.2891821832
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.3896591852
Short name T235
Test name
Test status
Simulation time 543966211 ps
CPU time 1.51 seconds
Started Feb 18 01:56:19 PM PST 24
Finished Feb 18 01:56:28 PM PST 24
Peak memory 203580 kb
Host smart-9a18ee5f-3162-48be-881a-a9503416879d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896591852 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.3896591852
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.2144640784
Short name T13
Test name
Test status
Simulation time 1054220491 ps
CPU time 4 seconds
Started Feb 18 02:24:37 PM PST 24
Finished Feb 18 02:24:44 PM PST 24
Peak memory 203808 kb
Host smart-e6a4ed04-f8f8-4f3c-9a34-55abed7ecba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144640784 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.2144640784
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3383214374
Short name T135
Test name
Test status
Simulation time 629231855 ps
CPU time 9.17 seconds
Started Feb 18 01:56:24 PM PST 24
Finished Feb 18 01:56:42 PM PST 24
Peak memory 211984 kb
Host smart-8f7f0c59-7868-4ea0-8b8e-fbb50babf76e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383214374 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.3
383214374
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.3069482819
Short name T127
Test name
Test status
Simulation time 1029896735 ps
CPU time 4.79 seconds
Started Feb 18 01:56:45 PM PST 24
Finished Feb 18 01:56:52 PM PST 24
Peak memory 219176 kb
Host smart-94c2d0cf-7209-4dba-975b-5be1e8e92293
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069482819 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.3069482819
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.102625371
Short name T132
Test name
Test status
Simulation time 1187518374 ps
CPU time 19.35 seconds
Started Feb 18 01:56:43 PM PST 24
Finished Feb 18 01:57:05 PM PST 24
Peak memory 214020 kb
Host smart-ea52ce1e-61c5-4ddf-9720-a8eb9ef12cf2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102625371 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.102625371
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.1360788708
Short name T93
Test name
Test status
Simulation time 60522449 ps
CPU time 0.68 seconds
Started Feb 18 02:25:44 PM PST 24
Finished Feb 18 02:25:46 PM PST 24
Peak memory 203608 kb
Host smart-eb41a1ef-edf8-40ed-9720-c4ec610a9db0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360788708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.1360788708
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2123141739
Short name T99
Test name
Test status
Simulation time 292092892 ps
CPU time 1.16 seconds
Started Feb 18 01:56:10 PM PST 24
Finished Feb 18 01:56:16 PM PST 24
Peak memory 203656 kb
Host smart-1de73dfa-f265-40ab-b856-63528ade4d5a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123141739 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.2123141739
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.3938419395
Short name T28
Test name
Test status
Simulation time 1073244641 ps
CPU time 1.18 seconds
Started Feb 18 02:24:46 PM PST 24
Finished Feb 18 02:24:51 PM PST 24
Peak memory 203356 kb
Host smart-aa64fd6d-5da8-4e1c-8d66-c45cfe59db71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938419395 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.3938419395
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.2460172047
Short name T112
Test name
Test status
Simulation time 2092682724 ps
CPU time 30.24 seconds
Started Feb 18 01:56:11 PM PST 24
Finished Feb 18 01:56:49 PM PST 24
Peak memory 203692 kb
Host smart-89ae05b4-89e9-470b-9478-90c1538ed54e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460172047 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.2460172047
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.3085826176
Short name T46
Test name
Test status
Simulation time 4841091694 ps
CPU time 65.47 seconds
Started Feb 18 01:56:15 PM PST 24
Finished Feb 18 01:57:30 PM PST 24
Peak memory 203820 kb
Host smart-903fe72c-8189-4c2f-942e-a5535d4c2637
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085826176 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.3085826176
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.2209222293
Short name T303
Test name
Test status
Simulation time 94966243 ps
CPU time 2.16 seconds
Started Feb 18 01:56:11 PM PST 24
Finished Feb 18 01:56:19 PM PST 24
Peak memory 211872 kb
Host smart-280789f9-e8bf-4d10-9adb-38ed492e69d4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209222293 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.2209222293
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.360344156
Short name T57
Test name
Test status
Simulation time 271675900 ps
CPU time 2.32 seconds
Started Feb 18 01:56:09 PM PST 24
Finished Feb 18 01:56:17 PM PST 24
Peak memory 211508 kb
Host smart-42a3cb4c-019d-4bfc-a970-eb58d64ebf5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360344156 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.360344156
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.4052529701
Short name T246
Test name
Test status
Simulation time 2998101811 ps
CPU time 6.16 seconds
Started Feb 18 01:56:24 PM PST 24
Finished Feb 18 01:56:38 PM PST 24
Peak memory 203768 kb
Host smart-178c4428-ffcc-4d9c-bd7e-1dc18041de00
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052529701 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.4052529701
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.907264100
Short name T318
Test name
Test status
Simulation time 11930471523 ps
CPU time 46.52 seconds
Started Feb 18 01:56:16 PM PST 24
Finished Feb 18 01:57:11 PM PST 24
Peak memory 203700 kb
Host smart-0de6842f-809c-4d18-b4b3-f7763d049049
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907264100 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr
_bit_bash.907264100
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.1567780753
Short name T241
Test name
Test status
Simulation time 331729055 ps
CPU time 1.18 seconds
Started Feb 18 01:56:14 PM PST 24
Finished Feb 18 01:56:23 PM PST 24
Peak memory 203580 kb
Host smart-0544072b-76fb-4c36-aaa3-90a99338384a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567780753 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.1
567780753
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.663060604
Short name T268
Test name
Test status
Simulation time 99444060 ps
CPU time 0.69 seconds
Started Feb 18 01:56:07 PM PST 24
Finished Feb 18 01:56:13 PM PST 24
Peak memory 203480 kb
Host smart-154cd606-c0cd-4c7f-8ff7-f8a0f1d26483
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663060604 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr
_aliasing.663060604
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.153875826
Short name T252
Test name
Test status
Simulation time 2932010650 ps
CPU time 5.53 seconds
Started Feb 18 01:56:12 PM PST 24
Finished Feb 18 01:56:24 PM PST 24
Peak memory 203760 kb
Host smart-46cee1a5-c316-425d-b8ec-454f26748486
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153875826 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr
_bit_bash.153875826
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3814301175
Short name T254
Test name
Test status
Simulation time 34596399 ps
CPU time 0.73 seconds
Started Feb 18 01:56:11 PM PST 24
Finished Feb 18 01:56:20 PM PST 24
Peak memory 203476 kb
Host smart-e07654fa-23bb-45e2-ac13-3c7d5109e50d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814301175 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.3814301175
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1687856896
Short name T244
Test name
Test status
Simulation time 159885645 ps
CPU time 0.72 seconds
Started Feb 18 01:56:16 PM PST 24
Finished Feb 18 01:56:25 PM PST 24
Peak memory 203440 kb
Host smart-d81c1c4d-e4bc-4426-817b-6612a10c88d8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687856896 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.1
687856896
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.2811525847
Short name T260
Test name
Test status
Simulation time 28114183 ps
CPU time 0.64 seconds
Started Feb 18 01:56:12 PM PST 24
Finished Feb 18 01:56:20 PM PST 24
Peak memory 203580 kb
Host smart-7366e756-5068-4d3f-af78-085b6541fc85
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811525847 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.2811525847
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.2228528654
Short name T332
Test name
Test status
Simulation time 24532030 ps
CPU time 0.64 seconds
Started Feb 18 01:56:14 PM PST 24
Finished Feb 18 01:56:23 PM PST 24
Peak memory 203500 kb
Host smart-181b5db5-a48e-428e-8e62-c9671fa87695
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228528654 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.2228528654
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.3045693582
Short name T59
Test name
Test status
Simulation time 394942521 ps
CPU time 3.52 seconds
Started Feb 18 01:56:17 PM PST 24
Finished Feb 18 01:56:30 PM PST 24
Peak memory 203704 kb
Host smart-09ab308a-d07a-4e6c-959b-50eaff1a8608
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045693582 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.3045693582
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.1567058685
Short name T63
Test name
Test status
Simulation time 1595549542 ps
CPU time 3.88 seconds
Started Feb 18 01:56:17 PM PST 24
Finished Feb 18 01:56:30 PM PST 24
Peak memory 203832 kb
Host smart-96ee979e-1ad9-46d8-990f-9a78550db5ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567058685 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.1567058685
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.4020862485
Short name T308
Test name
Test status
Simulation time 566024351 ps
CPU time 9.9 seconds
Started Feb 18 01:56:11 PM PST 24
Finished Feb 18 01:56:28 PM PST 24
Peak memory 211988 kb
Host smart-4476b988-27a3-44f8-9ad2-e2b9b636867e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020862485 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.4020862485
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3479202430
Short name T121
Test name
Test status
Simulation time 8560604357 ps
CPU time 32.3 seconds
Started Feb 18 01:56:17 PM PST 24
Finished Feb 18 01:56:58 PM PST 24
Peak memory 203736 kb
Host smart-a48bfd87-d1cc-4e9d-9cbd-4c43d2b5ed1b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479202430 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.3479202430
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2184175167
Short name T349
Test name
Test status
Simulation time 26116149820 ps
CPU time 40.47 seconds
Started Feb 18 01:56:12 PM PST 24
Finished Feb 18 01:57:00 PM PST 24
Peak memory 203828 kb
Host smart-dcc36f25-804b-422c-9c34-44f487f4fc1e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184175167 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.2184175167
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.4200717654
Short name T328
Test name
Test status
Simulation time 353143894 ps
CPU time 2.33 seconds
Started Feb 18 01:56:17 PM PST 24
Finished Feb 18 01:56:28 PM PST 24
Peak memory 203660 kb
Host smart-ae854c14-60bd-460b-9aa0-ffdd3ec1c574
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200717654 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.4200717654
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.230305543
Short name T81
Test name
Test status
Simulation time 2821750326 ps
CPU time 7.56 seconds
Started Feb 18 01:56:15 PM PST 24
Finished Feb 18 01:56:31 PM PST 24
Peak memory 220240 kb
Host smart-10216426-5a98-4b2f-a1d2-a8757884dd0b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230305543 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.230305543
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.1913666101
Short name T111
Test name
Test status
Simulation time 74810477 ps
CPU time 2.08 seconds
Started Feb 18 01:56:28 PM PST 24
Finished Feb 18 01:56:40 PM PST 24
Peak memory 211840 kb
Host smart-018db8cd-17de-47b7-a451-3a2a31c1e355
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913666101 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.1913666101
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2155364206
Short name T313
Test name
Test status
Simulation time 12387402736 ps
CPU time 42.03 seconds
Started Feb 18 01:56:12 PM PST 24
Finished Feb 18 01:57:01 PM PST 24
Peak memory 203764 kb
Host smart-92d06640-0e21-4b16-b83b-9edf1834c228
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155364206 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.2155364206
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2877580351
Short name T256
Test name
Test status
Simulation time 6396737303 ps
CPU time 12.43 seconds
Started Feb 18 01:56:10 PM PST 24
Finished Feb 18 01:56:27 PM PST 24
Peak memory 203720 kb
Host smart-eef51efe-9cea-4476-9540-a67364fd7b90
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877580351 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_bit_bash.2877580351
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2527333633
Short name T355
Test name
Test status
Simulation time 456689361 ps
CPU time 1.41 seconds
Started Feb 18 01:56:17 PM PST 24
Finished Feb 18 01:56:27 PM PST 24
Peak memory 203544 kb
Host smart-ea09e7bb-f5ee-4967-9bb3-35132b6eb1e7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527333633 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.2527333633
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.4144213158
Short name T284
Test name
Test status
Simulation time 266615850 ps
CPU time 1.52 seconds
Started Feb 18 01:56:16 PM PST 24
Finished Feb 18 01:56:26 PM PST 24
Peak memory 203668 kb
Host smart-b2bde468-630b-4456-a4c8-85eac911ca8c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144213158 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.4
144213158
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3304203741
Short name T311
Test name
Test status
Simulation time 366471130 ps
CPU time 1.72 seconds
Started Feb 18 01:56:17 PM PST 24
Finished Feb 18 01:56:28 PM PST 24
Peak memory 203400 kb
Host smart-5ed15d12-f650-430c-8d75-223687420f8d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304203741 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.3304203741
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1805038497
Short name T76
Test name
Test status
Simulation time 153007101 ps
CPU time 0.68 seconds
Started Feb 18 01:56:13 PM PST 24
Finished Feb 18 01:56:21 PM PST 24
Peak memory 203500 kb
Host smart-c09c9064-ac23-43cb-85f9-3b32cae8671d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805038497 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.1805038497
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.2713013313
Short name T297
Test name
Test status
Simulation time 71682183 ps
CPU time 0.66 seconds
Started Feb 18 01:56:09 PM PST 24
Finished Feb 18 01:56:15 PM PST 24
Peak memory 203512 kb
Host smart-1e60928d-6438-4f35-af1e-4bd02d3127ce
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713013313 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.2
713013313
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.618830437
Short name T345
Test name
Test status
Simulation time 56878072 ps
CPU time 0.63 seconds
Started Feb 18 01:56:24 PM PST 24
Finished Feb 18 01:56:33 PM PST 24
Peak memory 203552 kb
Host smart-8ad11655-1cea-4d5b-a5c8-c9db6dda82f6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618830437 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_part
ial_access.618830437
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.1868413470
Short name T344
Test name
Test status
Simulation time 16913647 ps
CPU time 0.65 seconds
Started Feb 18 01:56:15 PM PST 24
Finished Feb 18 01:56:25 PM PST 24
Peak memory 203504 kb
Host smart-65cf82b2-1810-40ca-bbb0-54d07a2f2c59
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868413470 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.1868413470
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.1006555434
Short name T116
Test name
Test status
Simulation time 158997358 ps
CPU time 3.68 seconds
Started Feb 18 01:56:09 PM PST 24
Finished Feb 18 01:56:18 PM PST 24
Peak memory 203384 kb
Host smart-2f24e375-b475-4774-a6a2-3dc7fb41828c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006555434 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_
csr_outstanding.1006555434
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.941816451
Short name T333
Test name
Test status
Simulation time 316181892 ps
CPU time 4.93 seconds
Started Feb 18 01:56:16 PM PST 24
Finished Feb 18 01:56:31 PM PST 24
Peak memory 203972 kb
Host smart-de01eee1-3428-4d57-9776-69556a9a2c07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941816451 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.941816451
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.334846378
Short name T134
Test name
Test status
Simulation time 983346409 ps
CPU time 10.43 seconds
Started Feb 18 01:56:23 PM PST 24
Finished Feb 18 01:56:41 PM PST 24
Peak memory 212060 kb
Host smart-030f8202-359b-4e6a-ad9c-7c1a6c490da4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334846378 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.334846378
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.922046183
Short name T275
Test name
Test status
Simulation time 364436814 ps
CPU time 2.43 seconds
Started Feb 18 01:56:25 PM PST 24
Finished Feb 18 01:56:35 PM PST 24
Peak memory 203656 kb
Host smart-f09d6dc2-44c8-46b6-8090-a7e6255ba2b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922046183 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.922046183
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.387956819
Short name T337
Test name
Test status
Simulation time 465342329 ps
CPU time 1.09 seconds
Started Feb 18 01:56:33 PM PST 24
Finished Feb 18 01:56:42 PM PST 24
Peak memory 203648 kb
Host smart-023d2466-4be1-4c35-ac27-70279e5c5938
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387956819 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.387956819
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1395510308
Short name T302
Test name
Test status
Simulation time 57372044 ps
CPU time 0.65 seconds
Started Feb 18 01:56:31 PM PST 24
Finished Feb 18 01:56:40 PM PST 24
Peak memory 203440 kb
Host smart-67aa89ce-aad1-43c3-9783-f63942489823
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395510308 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
1395510308
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3826056161
Short name T348
Test name
Test status
Simulation time 1757772735 ps
CPU time 2.99 seconds
Started Feb 18 01:56:28 PM PST 24
Finished Feb 18 01:56:40 PM PST 24
Peak memory 212152 kb
Host smart-2f8b0d31-cc46-4c4d-b7a8-42e563238b89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826056161 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.3826056161
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.1572014516
Short name T314
Test name
Test status
Simulation time 61357410 ps
CPU time 1.53 seconds
Started Feb 18 01:56:30 PM PST 24
Finished Feb 18 01:56:40 PM PST 24
Peak memory 203724 kb
Host smart-460ff904-65be-4a9d-bcc0-48799c5d776e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572014516 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.1572014516
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3504349914
Short name T236
Test name
Test status
Simulation time 1753212644 ps
CPU time 5.71 seconds
Started Feb 18 01:56:28 PM PST 24
Finished Feb 18 01:56:43 PM PST 24
Peak memory 203652 kb
Host smart-b65b1ce7-7eff-462e-9e8e-9f4e651eec2a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504349914 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
3504349914
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.841963069
Short name T238
Test name
Test status
Simulation time 30841734 ps
CPU time 0.66 seconds
Started Feb 18 01:56:24 PM PST 24
Finished Feb 18 01:56:33 PM PST 24
Peak memory 203568 kb
Host smart-6b0bdff9-2161-4db1-9bba-03eab9e8cd25
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841963069 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.841963069
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.2096866591
Short name T294
Test name
Test status
Simulation time 386457008 ps
CPU time 7.17 seconds
Started Feb 18 01:56:27 PM PST 24
Finished Feb 18 01:56:44 PM PST 24
Peak memory 203700 kb
Host smart-9dab9d2e-d3d4-41fb-beef-afe56f65a619
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096866591 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same
_csr_outstanding.2096866591
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tap_fsm_rand_reset.214859265
Short name T305
Test name
Test status
Simulation time 6397358900 ps
CPU time 20.5 seconds
Started Feb 18 01:56:32 PM PST 24
Finished Feb 18 01:57:00 PM PST 24
Peak memory 219332 kb
Host smart-3ffffe17-468f-4f7a-817e-0e55f6da8f21
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214859265 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.rv_dm_tap_fsm_rand_reset.214859265
Directory /workspace/11.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.2215680498
Short name T161
Test name
Test status
Simulation time 626813375 ps
CPU time 3.57 seconds
Started Feb 18 01:56:29 PM PST 24
Finished Feb 18 01:56:42 PM PST 24
Peak memory 203908 kb
Host smart-03a566a9-4cdb-40f3-a967-3070814fbf80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215680498 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.2215680498
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.2542595407
Short name T271
Test name
Test status
Simulation time 805918819 ps
CPU time 9.35 seconds
Started Feb 18 01:56:38 PM PST 24
Finished Feb 18 01:56:53 PM PST 24
Peak memory 211992 kb
Host smart-0a321416-243a-438c-ae2f-9a6452326290
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542595407 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.2
542595407
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.3342572004
Short name T110
Test name
Test status
Simulation time 194836762 ps
CPU time 2.3 seconds
Started Feb 18 01:56:34 PM PST 24
Finished Feb 18 01:56:43 PM PST 24
Peak memory 203656 kb
Host smart-cf9bd5ee-53a5-4105-a090-83f70c77c91d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342572004 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.3342572004
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.3562653696
Short name T274
Test name
Test status
Simulation time 179311394 ps
CPU time 1.29 seconds
Started Feb 18 01:56:30 PM PST 24
Finished Feb 18 01:56:40 PM PST 24
Peak memory 203648 kb
Host smart-3b412d04-53cd-4bc0-9eb7-08328eaf7af9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562653696 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
3562653696
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3700444112
Short name T272
Test name
Test status
Simulation time 58453257 ps
CPU time 0.7 seconds
Started Feb 18 01:56:32 PM PST 24
Finished Feb 18 01:56:40 PM PST 24
Peak memory 203436 kb
Host smart-707b39b5-1d21-442f-b090-b86a3b3f4ed9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700444112 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
3700444112
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3701053331
Short name T320
Test name
Test status
Simulation time 465105058 ps
CPU time 7.49 seconds
Started Feb 18 01:56:44 PM PST 24
Finished Feb 18 01:56:54 PM PST 24
Peak memory 203704 kb
Host smart-26ff0b19-3b1b-4bf3-8658-07c4f48e710c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701053331 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.3701053331
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.3736596710
Short name T145
Test name
Test status
Simulation time 211946320 ps
CPU time 4.76 seconds
Started Feb 18 01:56:31 PM PST 24
Finished Feb 18 01:56:44 PM PST 24
Peak memory 212012 kb
Host smart-cb2a6208-26d2-471f-b2f9-8c8adb8ba0c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736596710 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.3736596710
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.751253819
Short name T301
Test name
Test status
Simulation time 3334965271 ps
CPU time 10.53 seconds
Started Feb 18 01:56:25 PM PST 24
Finished Feb 18 01:56:44 PM PST 24
Peak memory 213068 kb
Host smart-74bd83ef-bcd7-4271-a582-37261990964a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751253819 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.751253819
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.438862852
Short name T89
Test name
Test status
Simulation time 28089800 ps
CPU time 1.39 seconds
Started Feb 18 01:56:47 PM PST 24
Finished Feb 18 01:56:50 PM PST 24
Peak memory 203720 kb
Host smart-5f9a5036-b009-42c3-acb5-299d8a2427dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438862852 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.438862852
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.408120966
Short name T327
Test name
Test status
Simulation time 166329459 ps
CPU time 0.91 seconds
Started Feb 18 01:56:43 PM PST 24
Finished Feb 18 01:56:46 PM PST 24
Peak memory 203588 kb
Host smart-8c9bef51-5efa-4e82-a973-b55503d00ef8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408120966 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.408120966
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2389612780
Short name T276
Test name
Test status
Simulation time 68571800 ps
CPU time 0.67 seconds
Started Feb 18 01:56:41 PM PST 24
Finished Feb 18 01:56:45 PM PST 24
Peak memory 203488 kb
Host smart-853beac0-772e-4d64-8520-d6083fae79b1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389612780 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
2389612780
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.1932521495
Short name T115
Test name
Test status
Simulation time 210075376 ps
CPU time 3.97 seconds
Started Feb 18 01:56:42 PM PST 24
Finished Feb 18 01:56:49 PM PST 24
Peak memory 203700 kb
Host smart-2da1680c-31ab-45e8-ab17-8d9fa26049a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932521495 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.1932521495
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tap_fsm_rand_reset.667145016
Short name T287
Test name
Test status
Simulation time 9582998219 ps
CPU time 18.33 seconds
Started Feb 18 01:56:24 PM PST 24
Finished Feb 18 01:56:51 PM PST 24
Peak memory 212092 kb
Host smart-3c76c46f-f400-4a77-ae65-5088b822bdac
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667145016 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.rv_dm_tap_fsm_rand_reset.667145016
Directory /workspace/13.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.970883978
Short name T350
Test name
Test status
Simulation time 111834009 ps
CPU time 2.42 seconds
Started Feb 18 01:56:27 PM PST 24
Finished Feb 18 01:56:40 PM PST 24
Peak memory 203784 kb
Host smart-c54ebc9d-4643-45b9-ac7b-c0bed9fdb95e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970883978 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.970883978
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.722035270
Short name T247
Test name
Test status
Simulation time 170193903 ps
CPU time 0.93 seconds
Started Feb 18 01:56:33 PM PST 24
Finished Feb 18 01:56:41 PM PST 24
Peak memory 203612 kb
Host smart-ea0434e1-87e1-48ed-bc64-cb85a644e50f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722035270 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.722035270
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.3071040342
Short name T315
Test name
Test status
Simulation time 111340766 ps
CPU time 0.67 seconds
Started Feb 18 01:56:32 PM PST 24
Finished Feb 18 01:56:40 PM PST 24
Peak memory 203500 kb
Host smart-f697013c-830d-4472-af93-34090778c761
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071040342 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
3071040342
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1639654199
Short name T88
Test name
Test status
Simulation time 566553772 ps
CPU time 3.36 seconds
Started Feb 18 01:56:29 PM PST 24
Finished Feb 18 01:56:42 PM PST 24
Peak memory 203748 kb
Host smart-e9660f52-551d-42af-9c75-def5aa9ca2e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639654199 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.1639654199
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.1241307999
Short name T334
Test name
Test status
Simulation time 121614495 ps
CPU time 4.17 seconds
Started Feb 18 01:56:33 PM PST 24
Finished Feb 18 01:56:45 PM PST 24
Peak memory 212020 kb
Host smart-f01136c3-1b24-46e6-a56b-1c9d6f96b33e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241307999 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.1241307999
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.2498458645
Short name T262
Test name
Test status
Simulation time 563968169 ps
CPU time 16.52 seconds
Started Feb 18 01:56:44 PM PST 24
Finished Feb 18 01:57:03 PM PST 24
Peak memory 211980 kb
Host smart-1f4c770e-24ed-4117-a48d-984f43218ca1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498458645 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.2
498458645
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.273905814
Short name T266
Test name
Test status
Simulation time 2955509659 ps
CPU time 12.73 seconds
Started Feb 18 01:56:45 PM PST 24
Finished Feb 18 01:57:00 PM PST 24
Peak memory 212076 kb
Host smart-6f3ce9d3-03d4-4abf-be0e-b77621b3a4f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273905814 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.273905814
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.1555094553
Short name T58
Test name
Test status
Simulation time 125107416 ps
CPU time 1.48 seconds
Started Feb 18 01:56:29 PM PST 24
Finished Feb 18 01:56:40 PM PST 24
Peak memory 211972 kb
Host smart-e3f7ea09-bc0c-4e39-a670-6ed370b4201e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555094553 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.1555094553
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.916005597
Short name T258
Test name
Test status
Simulation time 528243590 ps
CPU time 1.22 seconds
Started Feb 18 01:56:39 PM PST 24
Finished Feb 18 01:56:45 PM PST 24
Peak memory 203492 kb
Host smart-7f81b110-d242-48e1-b8d4-2da8255d3105
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916005597 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.916005597
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.4165966431
Short name T279
Test name
Test status
Simulation time 145580791 ps
CPU time 0.71 seconds
Started Feb 18 01:56:43 PM PST 24
Finished Feb 18 01:56:47 PM PST 24
Peak memory 203488 kb
Host smart-34bd7e5e-8cb4-4970-b31c-b08fe0e9f0f6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165966431 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
4165966431
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.3087367249
Short name T119
Test name
Test status
Simulation time 697818830 ps
CPU time 7.73 seconds
Started Feb 18 01:56:40 PM PST 24
Finished Feb 18 01:56:52 PM PST 24
Peak memory 203628 kb
Host smart-b60b8aba-84a1-492f-a6bb-a203bde3d543
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087367249 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.3087367249
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tap_fsm_rand_reset.1643370612
Short name T97
Test name
Test status
Simulation time 10718042943 ps
CPU time 30.38 seconds
Started Feb 18 01:56:33 PM PST 24
Finished Feb 18 01:57:11 PM PST 24
Peak memory 220008 kb
Host smart-41b1fd10-3efb-4da0-8dd9-3853ade2677b
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643370612 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rv_dm_tap_fsm_rand_reset.1643370612
Directory /workspace/15.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.1908145502
Short name T289
Test name
Test status
Simulation time 734108643 ps
CPU time 5.73 seconds
Started Feb 18 01:56:43 PM PST 24
Finished Feb 18 01:56:51 PM PST 24
Peak memory 212084 kb
Host smart-4b5d5feb-31df-4c94-ada6-1757c52cb7b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908145502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.1908145502
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3707120894
Short name T41
Test name
Test status
Simulation time 1454127832 ps
CPU time 10.27 seconds
Started Feb 18 01:56:32 PM PST 24
Finished Feb 18 01:56:50 PM PST 24
Peak memory 212368 kb
Host smart-af9a7e90-539f-4f7c-aa37-2bfe3c16055a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707120894 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.3
707120894
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.3664622894
Short name T264
Test name
Test status
Simulation time 43729950 ps
CPU time 2.2 seconds
Started Feb 18 01:56:42 PM PST 24
Finished Feb 18 01:56:47 PM PST 24
Peak memory 211836 kb
Host smart-c619452b-f28f-456e-be65-69bbd1f2e411
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664622894 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.3664622894
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.3956463507
Short name T242
Test name
Test status
Simulation time 451930370 ps
CPU time 1.15 seconds
Started Feb 18 01:56:39 PM PST 24
Finished Feb 18 01:56:45 PM PST 24
Peak memory 203636 kb
Host smart-d17ee6f0-46d2-4f4d-84e3-8692275f67ea
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956463507 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
3956463507
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3634757471
Short name T251
Test name
Test status
Simulation time 46930800 ps
CPU time 0.74 seconds
Started Feb 18 01:56:37 PM PST 24
Finished Feb 18 01:56:43 PM PST 24
Peak memory 203500 kb
Host smart-6ebcd1a4-36d3-4e9c-b585-6209645cd087
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634757471 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
3634757471
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1655610756
Short name T120
Test name
Test status
Simulation time 718605536 ps
CPU time 3.67 seconds
Started Feb 18 01:56:42 PM PST 24
Finished Feb 18 01:56:49 PM PST 24
Peak memory 203768 kb
Host smart-24e7f05d-fc07-4aa0-a4c6-0766db1c911c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655610756 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.1655610756
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tap_fsm_rand_reset.1454488950
Short name T304
Test name
Test status
Simulation time 32693128064 ps
CPU time 26.05 seconds
Started Feb 18 01:56:47 PM PST 24
Finished Feb 18 01:57:14 PM PST 24
Peak memory 220320 kb
Host smart-5f841f19-0733-40fc-90d3-2a9577b0de9a
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454488950 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rv_dm_tap_fsm_rand_reset.1454488950
Directory /workspace/16.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.191791415
Short name T312
Test name
Test status
Simulation time 110271537 ps
CPU time 2.92 seconds
Started Feb 18 01:56:40 PM PST 24
Finished Feb 18 01:56:47 PM PST 24
Peak memory 203924 kb
Host smart-ef0d38bc-975d-47fe-b9f6-66056013999d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191791415 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.191791415
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.3827821345
Short name T267
Test name
Test status
Simulation time 1067182027 ps
CPU time 2.32 seconds
Started Feb 18 01:56:43 PM PST 24
Finished Feb 18 01:56:48 PM PST 24
Peak memory 203676 kb
Host smart-cbe00357-422d-496c-90e9-0b5fc8944a00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827821345 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.3827821345
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.244841771
Short name T280
Test name
Test status
Simulation time 452993844 ps
CPU time 1.26 seconds
Started Feb 18 01:56:44 PM PST 24
Finished Feb 18 01:56:48 PM PST 24
Peak memory 203628 kb
Host smart-3a6d8eba-2259-47b9-9325-0670f6c2a9d1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244841771 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.244841771
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.3673640000
Short name T237
Test name
Test status
Simulation time 105809723 ps
CPU time 0.79 seconds
Started Feb 18 01:56:44 PM PST 24
Finished Feb 18 01:56:47 PM PST 24
Peak memory 203368 kb
Host smart-88def126-dcac-4f7f-a88e-d588dadbda74
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673640000 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
3673640000
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2957279534
Short name T87
Test name
Test status
Simulation time 467806253 ps
CPU time 6.53 seconds
Started Feb 18 01:56:44 PM PST 24
Finished Feb 18 01:56:53 PM PST 24
Peak memory 203792 kb
Host smart-2536532e-10ae-4b17-acbc-4cb4e4f54f09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957279534 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.2957279534
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tap_fsm_rand_reset.331856817
Short name T360
Test name
Test status
Simulation time 14071647757 ps
CPU time 23.8 seconds
Started Feb 18 01:56:51 PM PST 24
Finished Feb 18 01:57:16 PM PST 24
Peak memory 220324 kb
Host smart-bf1e2976-21d8-4355-9071-571ac91a6fa5
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331856817 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.rv_dm_tap_fsm_rand_reset.331856817
Directory /workspace/17.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.29511305
Short name T323
Test name
Test status
Simulation time 201144628 ps
CPU time 4.87 seconds
Started Feb 18 01:56:43 PM PST 24
Finished Feb 18 01:56:50 PM PST 24
Peak memory 212484 kb
Host smart-6042f0b9-ed0e-428a-a51b-506427155f4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29511305 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.29511305
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.4290023685
Short name T270
Test name
Test status
Simulation time 39750990 ps
CPU time 2.1 seconds
Started Feb 18 01:56:45 PM PST 24
Finished Feb 18 01:56:49 PM PST 24
Peak memory 203648 kb
Host smart-42db2773-a775-4f7e-b97e-d6cadda18c24
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290023685 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.4290023685
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.3219623079
Short name T319
Test name
Test status
Simulation time 1567050531 ps
CPU time 5.42 seconds
Started Feb 18 01:56:43 PM PST 24
Finished Feb 18 01:56:52 PM PST 24
Peak memory 203632 kb
Host smart-175fcc54-a93c-44ff-8517-0d325c0bd733
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219623079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
3219623079
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.3252841650
Short name T255
Test name
Test status
Simulation time 98514643 ps
CPU time 0.78 seconds
Started Feb 18 01:56:45 PM PST 24
Finished Feb 18 01:56:48 PM PST 24
Peak memory 203488 kb
Host smart-54ead98e-c4a9-4b81-9fdf-1ef974d6986f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252841650 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
3252841650
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3417073286
Short name T357
Test name
Test status
Simulation time 961754040 ps
CPU time 7.24 seconds
Started Feb 18 01:56:44 PM PST 24
Finished Feb 18 01:56:54 PM PST 24
Peak memory 203744 kb
Host smart-75db8231-6e95-4335-83c8-8ead09397e3a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417073286 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.3417073286
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.1375802197
Short name T96
Test name
Test status
Simulation time 770915654 ps
CPU time 5.34 seconds
Started Feb 18 01:56:49 PM PST 24
Finished Feb 18 01:56:56 PM PST 24
Peak memory 203924 kb
Host smart-a749f96d-b9fb-48ae-8231-a566c6d48a7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375802197 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.1375802197
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2823937663
Short name T80
Test name
Test status
Simulation time 4439102907 ps
CPU time 12.59 seconds
Started Feb 18 01:56:46 PM PST 24
Finished Feb 18 01:57:00 PM PST 24
Peak memory 212068 kb
Host smart-60dbe9ca-9117-4488-b2bb-c42bc18d32dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823937663 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.2823937663
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.1710027078
Short name T361
Test name
Test status
Simulation time 81997119 ps
CPU time 2.23 seconds
Started Feb 18 01:56:46 PM PST 24
Finished Feb 18 01:56:50 PM PST 24
Peak memory 211868 kb
Host smart-b87ec415-d06c-4643-af73-e9094b8415f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710027078 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.1710027078
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.851716882
Short name T273
Test name
Test status
Simulation time 733261272 ps
CPU time 2.35 seconds
Started Feb 18 01:56:47 PM PST 24
Finished Feb 18 01:56:51 PM PST 24
Peak memory 203640 kb
Host smart-20750b44-474d-4fde-b26d-70f1bef6b667
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851716882 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.851716882
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3677581119
Short name T341
Test name
Test status
Simulation time 84006102 ps
CPU time 0.62 seconds
Started Feb 18 01:56:56 PM PST 24
Finished Feb 18 01:56:58 PM PST 24
Peak memory 203504 kb
Host smart-f88c60bc-05fa-4b63-bf91-035e0c57302c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677581119 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
3677581119
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.3178036975
Short name T117
Test name
Test status
Simulation time 190487895 ps
CPU time 6.6 seconds
Started Feb 18 01:56:47 PM PST 24
Finished Feb 18 01:56:55 PM PST 24
Peak memory 203776 kb
Host smart-3918e9e2-8b3f-4ddb-9187-75c073c7abd9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178036975 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.3178036975
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.2683319516
Short name T43
Test name
Test status
Simulation time 131680607 ps
CPU time 2.46 seconds
Started Feb 18 01:56:44 PM PST 24
Finished Feb 18 01:56:49 PM PST 24
Peak memory 203904 kb
Host smart-4ac1f771-0af8-49af-aa11-fac776a959f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683319516 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.2683319516
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.1198378000
Short name T129
Test name
Test status
Simulation time 231442004 ps
CPU time 8.44 seconds
Started Feb 18 01:56:46 PM PST 24
Finished Feb 18 01:56:56 PM PST 24
Peak memory 211880 kb
Host smart-13f425be-3fdd-49d9-a24c-e9131e134b59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198378000 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.1
198378000
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1382166981
Short name T353
Test name
Test status
Simulation time 4481314387 ps
CPU time 31.84 seconds
Started Feb 18 01:56:24 PM PST 24
Finished Feb 18 01:57:05 PM PST 24
Peak memory 203784 kb
Host smart-74f0e6a8-511c-419d-897f-bd7a061d76ef
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382166981 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.1382166981
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.3449327474
Short name T343
Test name
Test status
Simulation time 2792459810 ps
CPU time 56.42 seconds
Started Feb 18 01:56:28 PM PST 24
Finished Feb 18 01:57:34 PM PST 24
Peak memory 203764 kb
Host smart-a014128e-8e66-4723-a4b0-df90637e14ea
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449327474 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.3449327474
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3919394248
Short name T336
Test name
Test status
Simulation time 88250355 ps
CPU time 1.56 seconds
Started Feb 18 01:56:18 PM PST 24
Finished Feb 18 01:56:28 PM PST 24
Peak memory 203724 kb
Host smart-678af441-3f63-4cf5-b007-6df7f6bb1f1b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919394248 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.3919394248
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.2442933860
Short name T114
Test name
Test status
Simulation time 112870028 ps
CPU time 2.06 seconds
Started Feb 18 01:56:20 PM PST 24
Finished Feb 18 01:56:30 PM PST 24
Peak memory 203564 kb
Host smart-c816a6ae-029b-44f4-b165-5b238544f7d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442933860 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.2442933860
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2091161271
Short name T245
Test name
Test status
Simulation time 13173399308 ps
CPU time 14.33 seconds
Started Feb 18 01:56:12 PM PST 24
Finished Feb 18 01:56:33 PM PST 24
Peak memory 203724 kb
Host smart-f8f7bcba-31a4-4e3d-92f5-ef62256da499
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091161271 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.2091161271
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.2435495677
Short name T257
Test name
Test status
Simulation time 4635959087 ps
CPU time 15.08 seconds
Started Feb 18 01:56:33 PM PST 24
Finished Feb 18 01:56:55 PM PST 24
Peak memory 203684 kb
Host smart-e5ac2a81-65e2-4b86-817c-957914a2368c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435495677 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_bit_bash.2435495677
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.3007254831
Short name T101
Test name
Test status
Simulation time 1639691955 ps
CPU time 5.33 seconds
Started Feb 18 01:56:14 PM PST 24
Finished Feb 18 01:56:26 PM PST 24
Peak memory 203680 kb
Host smart-07bf1975-11a0-4d23-952d-adee6dc9f7ec
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007254831 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.3007254831
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1153420973
Short name T356
Test name
Test status
Simulation time 893445009 ps
CPU time 3.28 seconds
Started Feb 18 01:56:15 PM PST 24
Finished Feb 18 01:56:28 PM PST 24
Peak memory 203588 kb
Host smart-af95a499-36ea-4e31-aea0-a475cb7174a5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153420973 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.1
153420973
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.710553641
Short name T64
Test name
Test status
Simulation time 99453960 ps
CPU time 0.78 seconds
Started Feb 18 01:56:13 PM PST 24
Finished Feb 18 01:56:21 PM PST 24
Peak memory 203488 kb
Host smart-5bf0930d-51aa-4095-860d-4e850f4f15fc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710553641 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_aliasing.710553641
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.3546840372
Short name T282
Test name
Test status
Simulation time 393342033 ps
CPU time 1.96 seconds
Started Feb 18 01:56:20 PM PST 24
Finished Feb 18 01:56:29 PM PST 24
Peak memory 203592 kb
Host smart-688316f5-4c4f-4806-b20c-726c08a1455c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546840372 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.3546840372
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1660083886
Short name T330
Test name
Test status
Simulation time 29691991 ps
CPU time 0.71 seconds
Started Feb 18 01:56:23 PM PST 24
Finished Feb 18 01:56:32 PM PST 24
Peak memory 203452 kb
Host smart-e5593987-b33d-446e-a5d6-2aebb6740b39
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660083886 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.1660083886
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2817081140
Short name T351
Test name
Test status
Simulation time 67957665 ps
CPU time 0.64 seconds
Started Feb 18 01:56:27 PM PST 24
Finished Feb 18 01:56:38 PM PST 24
Peak memory 203456 kb
Host smart-b1adc0ad-ddff-4b85-ba4c-4d8d7922a28a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817081140 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.2
817081140
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.3504039145
Short name T290
Test name
Test status
Simulation time 24973200 ps
CPU time 0.63 seconds
Started Feb 18 01:56:22 PM PST 24
Finished Feb 18 01:56:31 PM PST 24
Peak memory 203556 kb
Host smart-3961ed53-cd03-46a6-927a-6401a2e0076c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504039145 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.3504039145
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.512976361
Short name T285
Test name
Test status
Simulation time 40470575 ps
CPU time 0.61 seconds
Started Feb 18 01:56:15 PM PST 24
Finished Feb 18 01:56:24 PM PST 24
Peak memory 203500 kb
Host smart-a585dd61-4fa0-436f-8624-729b6b95d13c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512976361 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.512976361
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.1768462867
Short name T109
Test name
Test status
Simulation time 1160140447 ps
CPU time 7.07 seconds
Started Feb 18 01:56:23 PM PST 24
Finished Feb 18 01:56:38 PM PST 24
Peak memory 203684 kb
Host smart-11ade8e5-0317-40c9-8d37-35827a3cd82f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768462867 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.1768462867
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.3009870990
Short name T265
Test name
Test status
Simulation time 510367268 ps
CPU time 3.18 seconds
Started Feb 18 01:56:20 PM PST 24
Finished Feb 18 01:56:31 PM PST 24
Peak memory 212016 kb
Host smart-6b85a2b8-b8f3-4301-b499-1fd0997b38d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009870990 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.3009870990
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.4229097535
Short name T136
Test name
Test status
Simulation time 1032003897 ps
CPU time 9.25 seconds
Started Feb 18 01:56:15 PM PST 24
Finished Feb 18 01:56:33 PM PST 24
Peak memory 212044 kb
Host smart-f3ae9e5f-e3c7-4caa-937d-c1044a85e850
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229097535 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.4229097535
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_dm_tap_fsm_rand_reset.3498435664
Short name T296
Test name
Test status
Simulation time 12988920238 ps
CPU time 11.49 seconds
Started Feb 18 01:56:45 PM PST 24
Finished Feb 18 01:56:58 PM PST 24
Peak memory 220212 kb
Host smart-580c9f14-7749-4a32-9bdc-2d8cf296307b
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498435664 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 20.rv_dm_tap_fsm_rand_reset.3498435664
Directory /workspace/20.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1654504590
Short name T317
Test name
Test status
Simulation time 10494829541 ps
CPU time 33.99 seconds
Started Feb 18 01:56:15 PM PST 24
Finished Feb 18 01:56:58 PM PST 24
Peak memory 203784 kb
Host smart-f2ad2045-4de9-475f-a5be-b494ea99dd00
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654504590 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.1654504590
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.3021331378
Short name T352
Test name
Test status
Simulation time 764614436 ps
CPU time 27.73 seconds
Started Feb 18 01:56:13 PM PST 24
Finished Feb 18 01:56:49 PM PST 24
Peak memory 203644 kb
Host smart-9632e44c-b419-4d83-bd0e-2438e220cbf4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021331378 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.3021331378
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.3221088498
Short name T326
Test name
Test status
Simulation time 237753934 ps
CPU time 1.5 seconds
Started Feb 18 01:56:20 PM PST 24
Finished Feb 18 01:56:30 PM PST 24
Peak memory 203664 kb
Host smart-9cdef420-5042-4f88-8adb-70c16fa3f295
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221088498 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.3221088498
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2060840866
Short name T310
Test name
Test status
Simulation time 32883649 ps
CPU time 1.41 seconds
Started Feb 18 01:56:22 PM PST 24
Finished Feb 18 01:56:31 PM PST 24
Peak memory 211916 kb
Host smart-efa3fe6a-5a28-4c82-8aef-5263d87223f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060840866 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.2060840866
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.2086226158
Short name T321
Test name
Test status
Simulation time 33953193332 ps
CPU time 112.41 seconds
Started Feb 18 01:56:23 PM PST 24
Finished Feb 18 01:58:24 PM PST 24
Peak memory 203692 kb
Host smart-315e5f36-bd7d-4aeb-b639-15e51ba598b8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086226158 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.2086226158
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.3502334186
Short name T98
Test name
Test status
Simulation time 876274942 ps
CPU time 1.53 seconds
Started Feb 18 01:56:19 PM PST 24
Finished Feb 18 01:56:28 PM PST 24
Peak memory 203556 kb
Host smart-e5f3a3d3-77b0-49af-909f-1478725fe016
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502334186 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.3502334186
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.191592598
Short name T359
Test name
Test status
Simulation time 803378827 ps
CPU time 1.56 seconds
Started Feb 18 01:56:20 PM PST 24
Finished Feb 18 01:56:30 PM PST 24
Peak memory 203420 kb
Host smart-6b01bf72-916f-491a-8616-fdd06fd8e5f6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191592598 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.191592598
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.858353352
Short name T292
Test name
Test status
Simulation time 186088495 ps
CPU time 0.98 seconds
Started Feb 18 01:56:19 PM PST 24
Finished Feb 18 01:56:28 PM PST 24
Peak memory 203496 kb
Host smart-23f93f90-6015-4263-bb4d-e21d5be456f2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858353352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr
_aliasing.858353352
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1075187747
Short name T269
Test name
Test status
Simulation time 4767616051 ps
CPU time 6.01 seconds
Started Feb 18 01:56:22 PM PST 24
Finished Feb 18 01:56:36 PM PST 24
Peak memory 203692 kb
Host smart-7c9ce130-e1c5-4d34-a0aa-7244c6fd715d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075187747 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.1075187747
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.2702776477
Short name T358
Test name
Test status
Simulation time 196405065 ps
CPU time 0.79 seconds
Started Feb 18 01:56:23 PM PST 24
Finished Feb 18 01:56:33 PM PST 24
Peak memory 203480 kb
Host smart-0076c7b7-2344-4b42-90f7-e2a83bd45578
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702776477 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.2702776477
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.200813668
Short name T307
Test name
Test status
Simulation time 60575429 ps
CPU time 0.64 seconds
Started Feb 18 01:56:23 PM PST 24
Finished Feb 18 01:56:31 PM PST 24
Peak memory 203488 kb
Host smart-1f7a7808-35bc-42c1-8862-33f15b6c90ce
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200813668 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.200813668
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.2309108786
Short name T338
Test name
Test status
Simulation time 49458413 ps
CPU time 0.63 seconds
Started Feb 18 01:56:14 PM PST 24
Finished Feb 18 01:56:23 PM PST 24
Peak memory 203556 kb
Host smart-02df5d3e-9436-470b-93a7-21484a9c8030
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309108786 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.2309108786
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.2254189939
Short name T295
Test name
Test status
Simulation time 16290857 ps
CPU time 0.73 seconds
Started Feb 18 01:56:20 PM PST 24
Finished Feb 18 01:56:29 PM PST 24
Peak memory 202472 kb
Host smart-bc9db8f1-cf95-405b-9c11-cffdacff7aeb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254189939 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.2254189939
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.3837862520
Short name T107
Test name
Test status
Simulation time 149167124 ps
CPU time 3.6 seconds
Started Feb 18 01:56:20 PM PST 24
Finished Feb 18 01:56:32 PM PST 24
Peak memory 202700 kb
Host smart-a0894767-9f35-42af-b67e-6777b520f24c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837862520 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.3837862520
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.2584394729
Short name T331
Test name
Test status
Simulation time 14201978596 ps
CPU time 11.66 seconds
Started Feb 18 01:56:16 PM PST 24
Finished Feb 18 01:56:36 PM PST 24
Peak memory 212176 kb
Host smart-53c5156b-e258-4ea8-b906-cfc96ba4f5d0
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584394729 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.2584394729
Directory /workspace/3.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2343552864
Short name T166
Test name
Test status
Simulation time 142086374 ps
CPU time 4.3 seconds
Started Feb 18 01:56:15 PM PST 24
Finished Feb 18 01:56:28 PM PST 24
Peak memory 212568 kb
Host smart-3f9e933e-8ad4-4c3f-9bac-609e7dd31837
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343552864 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.2343552864
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.4157112745
Short name T42
Test name
Test status
Simulation time 3446415969 ps
CPU time 16.29 seconds
Started Feb 18 01:56:14 PM PST 24
Finished Feb 18 01:56:38 PM PST 24
Peak memory 212444 kb
Host smart-c9dc3fe8-6ded-4020-803c-1fc0a9ccc31d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157112745 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.4157112745
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/32.rv_dm_tap_fsm_rand_reset.1558278742
Short name T263
Test name
Test status
Simulation time 12516092801 ps
CPU time 41.37 seconds
Started Feb 18 01:56:45 PM PST 24
Finished Feb 18 01:57:29 PM PST 24
Peak memory 212092 kb
Host smart-3fe08f5c-bc2a-4d98-81ce-34637fee75b4
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558278742 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 32.rv_dm_tap_fsm_rand_reset.1558278742
Directory /workspace/32.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/33.rv_dm_tap_fsm_rand_reset.2490697834
Short name T141
Test name
Test status
Simulation time 29808171364 ps
CPU time 23.07 seconds
Started Feb 18 01:56:51 PM PST 24
Finished Feb 18 01:57:15 PM PST 24
Peak memory 212088 kb
Host smart-e80a3486-9e3b-42e1-aa89-95bb54166511
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490697834 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 33.rv_dm_tap_fsm_rand_reset.2490697834
Directory /workspace/33.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/36.rv_dm_tap_fsm_rand_reset.1368735730
Short name T346
Test name
Test status
Simulation time 6416677215 ps
CPU time 20.16 seconds
Started Feb 18 01:56:55 PM PST 24
Finished Feb 18 01:57:17 PM PST 24
Peak memory 215740 kb
Host smart-37df6f35-8a21-4eb2-81f2-5e859b6e7e3a
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368735730 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 36.rv_dm_tap_fsm_rand_reset.1368735730
Directory /workspace/36.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/37.rv_dm_tap_fsm_rand_reset.1935796701
Short name T342
Test name
Test status
Simulation time 27528470249 ps
CPU time 25.29 seconds
Started Feb 18 01:56:57 PM PST 24
Finished Feb 18 01:57:24 PM PST 24
Peak memory 228516 kb
Host smart-83c5daed-d2e7-40d5-ae14-d23e6c4a8523
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935796701 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 37.rv_dm_tap_fsm_rand_reset.1935796701
Directory /workspace/37.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/38.rv_dm_tap_fsm_rand_reset.2419089154
Short name T322
Test name
Test status
Simulation time 9005250639 ps
CPU time 14.77 seconds
Started Feb 18 01:56:52 PM PST 24
Finished Feb 18 01:57:08 PM PST 24
Peak memory 212160 kb
Host smart-6568ce4e-7e44-406b-bfc1-a8d1f0e7edb4
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419089154 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 38.rv_dm_tap_fsm_rand_reset.2419089154
Directory /workspace/38.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1128093135
Short name T122
Test name
Test status
Simulation time 2225584433 ps
CPU time 66.84 seconds
Started Feb 18 01:56:14 PM PST 24
Finished Feb 18 01:57:28 PM PST 24
Peak memory 203784 kb
Host smart-62f48fb6-a9a2-46bc-99d5-a008ff530a25
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128093135 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.1128093135
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.4157944570
Short name T339
Test name
Test status
Simulation time 5008859225 ps
CPU time 28.33 seconds
Started Feb 18 01:56:19 PM PST 24
Finished Feb 18 01:56:55 PM PST 24
Peak memory 203768 kb
Host smart-eb8379fd-e9f9-46a1-ab0b-8159f2f73098
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157944570 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.4157944570
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.3545576694
Short name T103
Test name
Test status
Simulation time 36374573 ps
CPU time 1.49 seconds
Started Feb 18 01:56:22 PM PST 24
Finished Feb 18 01:56:31 PM PST 24
Peak memory 203776 kb
Host smart-d6d46277-6605-4efd-bb85-68912bc17ccb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545576694 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.3545576694
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.2198607764
Short name T104
Test name
Test status
Simulation time 96374392 ps
CPU time 2.29 seconds
Started Feb 18 01:56:21 PM PST 24
Finished Feb 18 01:56:31 PM PST 24
Peak memory 211832 kb
Host smart-41be50b9-30d3-4006-9af2-8a64a2419a78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198607764 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.2198607764
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.1688102962
Short name T325
Test name
Test status
Simulation time 6655743244 ps
CPU time 18.25 seconds
Started Feb 18 01:56:20 PM PST 24
Finished Feb 18 01:56:45 PM PST 24
Peak memory 203656 kb
Host smart-3f9c77ea-b183-4b1e-9402-1fab526d3489
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688102962 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.1688102962
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3167084264
Short name T243
Test name
Test status
Simulation time 15700954001 ps
CPU time 49.78 seconds
Started Feb 18 01:56:28 PM PST 24
Finished Feb 18 01:57:27 PM PST 24
Peak memory 203728 kb
Host smart-edf30f2b-07d3-4e14-8e8b-b01fc1416f22
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167084264 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_bit_bash.3167084264
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.3022013561
Short name T100
Test name
Test status
Simulation time 2572520167 ps
CPU time 2.26 seconds
Started Feb 18 01:56:21 PM PST 24
Finished Feb 18 01:56:31 PM PST 24
Peak memory 203764 kb
Host smart-75e19dd8-4419-42aa-94c5-73230286b92b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022013561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.3022013561
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3290584360
Short name T250
Test name
Test status
Simulation time 210859363 ps
CPU time 1.23 seconds
Started Feb 18 01:56:17 PM PST 24
Finished Feb 18 01:56:27 PM PST 24
Peak memory 203644 kb
Host smart-284f5237-eeb5-4def-a3c5-daf342f8e8d4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290584360 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.3
290584360
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.1943360559
Short name T75
Test name
Test status
Simulation time 128072030 ps
CPU time 0.99 seconds
Started Feb 18 01:56:23 PM PST 24
Finished Feb 18 01:56:32 PM PST 24
Peak memory 203484 kb
Host smart-c3de73d2-943f-40bb-b64e-660e969e9525
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943360559 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.1943360559
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2062003285
Short name T335
Test name
Test status
Simulation time 471086079 ps
CPU time 1.43 seconds
Started Feb 18 01:56:23 PM PST 24
Finished Feb 18 01:56:33 PM PST 24
Peak memory 203628 kb
Host smart-c9d4ce22-decc-44e1-80c5-af6dea52a5cb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062003285 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.2062003285
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2707081552
Short name T259
Test name
Test status
Simulation time 97160157 ps
CPU time 0.77 seconds
Started Feb 18 01:56:19 PM PST 24
Finished Feb 18 01:56:28 PM PST 24
Peak memory 203452 kb
Host smart-033b9b0e-8f19-4465-a80b-f63d4141ed1c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707081552 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.2707081552
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.965695587
Short name T240
Test name
Test status
Simulation time 66571973 ps
CPU time 0.7 seconds
Started Feb 18 01:56:20 PM PST 24
Finished Feb 18 01:56:29 PM PST 24
Peak memory 203436 kb
Host smart-9ed0e71d-d955-475f-aeeb-11ca1c68d9ed
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965695587 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.965695587
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.3018548535
Short name T286
Test name
Test status
Simulation time 52962810 ps
CPU time 0.63 seconds
Started Feb 18 01:56:34 PM PST 24
Finished Feb 18 01:56:41 PM PST 24
Peak memory 203548 kb
Host smart-f9e93e16-fdf2-4c36-a014-40faf83addd8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018548535 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.3018548535
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.3341159862
Short name T329
Test name
Test status
Simulation time 23498679 ps
CPU time 0.67 seconds
Started Feb 18 01:56:20 PM PST 24
Finished Feb 18 01:56:29 PM PST 24
Peak memory 203516 kb
Host smart-376519cc-c5cc-490f-adbe-24950619aa61
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341159862 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.3341159862
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3978817121
Short name T118
Test name
Test status
Simulation time 3112331004 ps
CPU time 6.71 seconds
Started Feb 18 01:56:21 PM PST 24
Finished Feb 18 01:56:35 PM PST 24
Peak memory 203844 kb
Host smart-d8a8a37f-d2bc-451e-928c-06dd8c6a2559
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978817121 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.3978817121
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.558302135
Short name T95
Test name
Test status
Simulation time 48489114753 ps
CPU time 21.77 seconds
Started Feb 18 01:56:21 PM PST 24
Finished Feb 18 01:56:50 PM PST 24
Peak memory 220316 kb
Host smart-b3f6ff9d-a418-46bb-88be-212c9649faa8
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558302135 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.558302135
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1353812349
Short name T78
Test name
Test status
Simulation time 1171286423 ps
CPU time 19.8 seconds
Started Feb 18 01:56:34 PM PST 24
Finished Feb 18 01:57:00 PM PST 24
Peak memory 214296 kb
Host smart-1ada230e-3b64-45e8-b0f8-df77457fac6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353812349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.1353812349
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.2313512011
Short name T277
Test name
Test status
Simulation time 151381923 ps
CPU time 4.38 seconds
Started Feb 18 01:56:23 PM PST 24
Finished Feb 18 01:56:37 PM PST 24
Peak memory 215284 kb
Host smart-9cbab521-4288-4967-95ec-ac48ecc035ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313512011 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.2313512011
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.2735020061
Short name T113
Test name
Test status
Simulation time 29883865 ps
CPU time 1.42 seconds
Started Feb 18 01:56:19 PM PST 24
Finished Feb 18 01:56:29 PM PST 24
Peak memory 203660 kb
Host smart-1402b9de-9d35-46b7-ac3d-01754c275092
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735020061 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.2735020061
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.271402337
Short name T261
Test name
Test status
Simulation time 343689857 ps
CPU time 2.03 seconds
Started Feb 18 01:56:24 PM PST 24
Finished Feb 18 01:56:34 PM PST 24
Peak memory 203512 kb
Host smart-ae5ebf5d-3e9f-44d8-a216-6568ef5f86ed
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271402337 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.271402337
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3212320101
Short name T248
Test name
Test status
Simulation time 69639613 ps
CPU time 0.65 seconds
Started Feb 18 01:56:35 PM PST 24
Finished Feb 18 01:56:42 PM PST 24
Peak memory 203480 kb
Host smart-2e2d899d-f685-4408-accc-5686d7d89e36
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212320101 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.3
212320101
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.3573444794
Short name T105
Test name
Test status
Simulation time 300812535 ps
CPU time 4.44 seconds
Started Feb 18 01:56:22 PM PST 24
Finished Feb 18 01:56:34 PM PST 24
Peak memory 203752 kb
Host smart-338ea334-9ecb-4335-bbfc-5973e623e8b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573444794 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.3573444794
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.873365951
Short name T45
Test name
Test status
Simulation time 171597705 ps
CPU time 2.84 seconds
Started Feb 18 01:56:17 PM PST 24
Finished Feb 18 01:56:29 PM PST 24
Peak memory 203808 kb
Host smart-56572e7d-9695-4784-92f8-fe8ea85af145
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873365951 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.873365951
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.137639460
Short name T316
Test name
Test status
Simulation time 990208429 ps
CPU time 15.7 seconds
Started Feb 18 01:56:22 PM PST 24
Finished Feb 18 01:56:45 PM PST 24
Peak memory 212036 kb
Host smart-45fd3bcd-b980-48b5-86f0-8fcd1ad0ee9c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137639460 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.137639460
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.4098715876
Short name T324
Test name
Test status
Simulation time 7312335451 ps
CPU time 20.37 seconds
Started Feb 18 01:56:22 PM PST 24
Finished Feb 18 01:56:50 PM PST 24
Peak memory 220304 kb
Host smart-54d9c738-70f6-4f15-8985-5ff3cc207ab6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098715876 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.4098715876
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.3380610974
Short name T340
Test name
Test status
Simulation time 47196048 ps
CPU time 1.32 seconds
Started Feb 18 01:56:26 PM PST 24
Finished Feb 18 01:56:36 PM PST 24
Peak memory 203700 kb
Host smart-a3fb4ac9-1256-4ac8-8a92-7116a6c087c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380610974 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.3380610974
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2889977038
Short name T306
Test name
Test status
Simulation time 539701410 ps
CPU time 2.62 seconds
Started Feb 18 01:56:24 PM PST 24
Finished Feb 18 01:56:35 PM PST 24
Peak memory 203452 kb
Host smart-f1a00472-9bae-44a4-8a6c-6c6b9006fc33
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889977038 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.2
889977038
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.3680597397
Short name T293
Test name
Test status
Simulation time 88297333 ps
CPU time 0.64 seconds
Started Feb 18 01:56:20 PM PST 24
Finished Feb 18 01:56:29 PM PST 24
Peak memory 203484 kb
Host smart-69224331-6718-442c-915a-0e4c7b73be0c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680597397 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.3
680597397
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.4156605109
Short name T106
Test name
Test status
Simulation time 566603006 ps
CPU time 6.32 seconds
Started Feb 18 01:56:21 PM PST 24
Finished Feb 18 01:56:35 PM PST 24
Peak memory 203700 kb
Host smart-66992ac9-474f-41fa-9187-cdc0aabca2c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156605109 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.4156605109
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.1839782463
Short name T298
Test name
Test status
Simulation time 94965044 ps
CPU time 5.02 seconds
Started Feb 18 01:56:26 PM PST 24
Finished Feb 18 01:56:40 PM PST 24
Peak memory 212080 kb
Host smart-8866bfdc-c270-4a24-82f9-45ba19d5b07f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839782463 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.1839782463
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2417206815
Short name T133
Test name
Test status
Simulation time 532413152 ps
CPU time 15.25 seconds
Started Feb 18 01:56:19 PM PST 24
Finished Feb 18 01:56:42 PM PST 24
Peak memory 211924 kb
Host smart-e6180fbe-e4f5-4bfb-bf33-84296922c3ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417206815 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.2417206815
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.266389763
Short name T47
Test name
Test status
Simulation time 403152668 ps
CPU time 1.5 seconds
Started Feb 18 01:56:30 PM PST 24
Finished Feb 18 01:56:40 PM PST 24
Peak memory 203720 kb
Host smart-52990b3e-5641-40a9-b375-01da5f15f386
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266389763 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.266389763
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.719786459
Short name T347
Test name
Test status
Simulation time 314990254 ps
CPU time 1.28 seconds
Started Feb 18 01:56:23 PM PST 24
Finished Feb 18 01:56:33 PM PST 24
Peak memory 203584 kb
Host smart-583b2e35-59c8-44c0-a2d7-2fa97246b6a2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719786459 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.719786459
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1080555025
Short name T299
Test name
Test status
Simulation time 116649047 ps
CPU time 0.72 seconds
Started Feb 18 01:56:21 PM PST 24
Finished Feb 18 01:56:30 PM PST 24
Peak memory 203520 kb
Host smart-7cf15477-9de8-4a8a-964f-d817ba945ec4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080555025 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.1
080555025
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3531701518
Short name T108
Test name
Test status
Simulation time 208184289 ps
CPU time 3.93 seconds
Started Feb 18 01:56:22 PM PST 24
Finished Feb 18 01:56:34 PM PST 24
Peak memory 203676 kb
Host smart-36549eb5-444b-4aa7-95f3-8e6408b0fc27
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531701518 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.3531701518
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.2476051665
Short name T82
Test name
Test status
Simulation time 38557071 ps
CPU time 1.99 seconds
Started Feb 18 01:56:24 PM PST 24
Finished Feb 18 01:56:34 PM PST 24
Peak memory 203868 kb
Host smart-a1fc590a-9c9e-44d3-a9f7-0222accd3d7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476051665 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.2476051665
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.3791156123
Short name T131
Test name
Test status
Simulation time 1661400309 ps
CPU time 10.3 seconds
Started Feb 18 01:56:20 PM PST 24
Finished Feb 18 01:56:37 PM PST 24
Peak memory 212112 kb
Host smart-9eeed9a7-822e-4ad5-8271-d3d604fdacd8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791156123 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.3791156123
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1912446992
Short name T354
Test name
Test status
Simulation time 100200572 ps
CPU time 2.21 seconds
Started Feb 18 01:56:22 PM PST 24
Finished Feb 18 01:56:33 PM PST 24
Peak memory 203668 kb
Host smart-09def2cf-854d-4da7-9350-c2efc84b515a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912446992 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.1912446992
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3334081756
Short name T291
Test name
Test status
Simulation time 170845799 ps
CPU time 1.07 seconds
Started Feb 18 01:56:22 PM PST 24
Finished Feb 18 01:56:31 PM PST 24
Peak memory 203588 kb
Host smart-f1c6195f-7c03-4634-bf96-1ebea188d284
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334081756 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.3
334081756
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2060049507
Short name T249
Test name
Test status
Simulation time 70047211 ps
CPU time 0.75 seconds
Started Feb 18 01:56:22 PM PST 24
Finished Feb 18 01:56:31 PM PST 24
Peak memory 203488 kb
Host smart-a7677b9a-fce3-4369-9f3c-d49f90744bef
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060049507 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.2
060049507
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2474975011
Short name T281
Test name
Test status
Simulation time 411129207 ps
CPU time 4.1 seconds
Started Feb 18 01:56:19 PM PST 24
Finished Feb 18 01:56:31 PM PST 24
Peak memory 203760 kb
Host smart-e731afe6-3989-4722-81b5-4ca38b8f17ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474975011 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_
csr_outstanding.2474975011
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2517867810
Short name T288
Test name
Test status
Simulation time 316669526 ps
CPU time 4.09 seconds
Started Feb 18 01:56:22 PM PST 24
Finished Feb 18 01:56:35 PM PST 24
Peak memory 212096 kb
Host smart-0d4d86f7-40b8-4e9c-88d8-e7edc30c8d65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517867810 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.2517867810
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3472780482
Short name T283
Test name
Test status
Simulation time 1816071791 ps
CPU time 9.79 seconds
Started Feb 18 01:56:22 PM PST 24
Finished Feb 18 01:56:39 PM PST 24
Peak memory 212116 kb
Host smart-91bc8ab6-f596-458e-a555-261ebd087bbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472780482 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.3472780482
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1370633921
Short name T300
Test name
Test status
Simulation time 216383170 ps
CPU time 1.48 seconds
Started Feb 18 01:56:29 PM PST 24
Finished Feb 18 01:56:40 PM PST 24
Peak memory 203692 kb
Host smart-15cb018e-fc2b-4175-822a-92af347f0670
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370633921 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.1370633921
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.38037656
Short name T253
Test name
Test status
Simulation time 350298490 ps
CPU time 1.56 seconds
Started Feb 18 01:56:29 PM PST 24
Finished Feb 18 01:56:40 PM PST 24
Peak memory 203632 kb
Host smart-416c1f99-e475-4032-80ea-a1668592bcec
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38037656 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.38037656
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1904773555
Short name T239
Test name
Test status
Simulation time 126788774 ps
CPU time 0.66 seconds
Started Feb 18 01:56:23 PM PST 24
Finished Feb 18 01:56:32 PM PST 24
Peak memory 203492 kb
Host smart-25ae8006-d5b4-487c-ad28-6eb62c6f533e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904773555 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.1
904773555
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.2698983707
Short name T102
Test name
Test status
Simulation time 472569244 ps
CPU time 3.88 seconds
Started Feb 18 01:56:26 PM PST 24
Finished Feb 18 01:56:39 PM PST 24
Peak memory 203684 kb
Host smart-ed05f61a-4742-4bc7-ada7-5d19e3098f74
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698983707 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.2698983707
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.971195593
Short name T309
Test name
Test status
Simulation time 266331592 ps
CPU time 2.22 seconds
Started Feb 18 01:56:24 PM PST 24
Finished Feb 18 01:56:35 PM PST 24
Peak memory 203868 kb
Host smart-739dc9a4-c188-4d42-a941-c759ee44530b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971195593 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.971195593
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.3390777831
Short name T130
Test name
Test status
Simulation time 5062205054 ps
CPU time 18.3 seconds
Started Feb 18 01:56:30 PM PST 24
Finished Feb 18 01:56:57 PM PST 24
Peak memory 216120 kb
Host smart-724b5df7-b9c3-416c-9c95-15f3c48d7a1b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390777831 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.3390777831
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.1319712170
Short name T165
Test name
Test status
Simulation time 24777678 ps
CPU time 0.67 seconds
Started Feb 18 02:24:48 PM PST 24
Finished Feb 18 02:24:55 PM PST 24
Peak memory 203588 kb
Host smart-f0fcd8bd-83cf-4dce-9481-13b7a545407c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319712170 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.1319712170
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.2451920484
Short name T22
Test name
Test status
Simulation time 11550692022 ps
CPU time 42.63 seconds
Started Feb 18 02:24:31 PM PST 24
Finished Feb 18 02:25:21 PM PST 24
Peak memory 204012 kb
Host smart-01433802-b9d7-4cf4-93a8-d5871042adaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451920484 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.2451920484
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.3555019710
Short name T184
Test name
Test status
Simulation time 4851761440 ps
CPU time 5.11 seconds
Started Feb 18 02:24:33 PM PST 24
Finished Feb 18 02:24:44 PM PST 24
Peak memory 204028 kb
Host smart-377e84e3-fcd3-44e0-9a05-7234d5e5ba1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555019710 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.3555019710
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.3626095205
Short name T234
Test name
Test status
Simulation time 80726109 ps
CPU time 0.66 seconds
Started Feb 18 02:24:48 PM PST 24
Finished Feb 18 02:24:54 PM PST 24
Peak memory 203588 kb
Host smart-ccbff83b-b3f3-495a-8465-8c2e2716da6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626095205 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.3626095205
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.3354708531
Short name T196
Test name
Test status
Simulation time 1830565404 ps
CPU time 4.58 seconds
Started Feb 18 02:24:29 PM PST 24
Finished Feb 18 02:24:40 PM PST 24
Peak memory 203920 kb
Host smart-c5337ee7-968d-4d56-bbe4-e7567de10fd5
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3354708531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t
l_access.3354708531
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.3421329199
Short name T16
Test name
Test status
Simulation time 258386228 ps
CPU time 0.94 seconds
Started Feb 18 02:24:49 PM PST 24
Finished Feb 18 02:24:55 PM PST 24
Peak memory 203584 kb
Host smart-d7859b10-10b8-4aad-bd7f-656878a3c5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421329199 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.3421329199
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.870669740
Short name T169
Test name
Test status
Simulation time 80961964 ps
CPU time 0.74 seconds
Started Feb 18 02:24:35 PM PST 24
Finished Feb 18 02:24:39 PM PST 24
Peak memory 203480 kb
Host smart-50dbcc58-1670-4b30-b8cc-943f2b6f7df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870669740 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.870669740
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.1752010133
Short name T179
Test name
Test status
Simulation time 237969927 ps
CPU time 0.81 seconds
Started Feb 18 02:24:46 PM PST 24
Finished Feb 18 02:24:50 PM PST 24
Peak memory 203472 kb
Host smart-b3a6726d-a8bb-4861-bab4-f993eb2148d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752010133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.1752010133
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.1866014536
Short name T17
Test name
Test status
Simulation time 365207250 ps
CPU time 1.86 seconds
Started Feb 18 02:24:52 PM PST 24
Finished Feb 18 02:25:02 PM PST 24
Peak memory 203684 kb
Host smart-6a2507e1-61f3-4b9c-968a-3c1294086ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866014536 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.1866014536
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.3713736584
Short name T23
Test name
Test status
Simulation time 23034296 ps
CPU time 0.68 seconds
Started Feb 18 02:24:46 PM PST 24
Finished Feb 18 02:24:50 PM PST 24
Peak memory 203216 kb
Host smart-3530932e-4983-4b1e-bae2-043ea8dc046c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713736584 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.3713736584
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.2927019063
Short name T124
Test name
Test status
Simulation time 313549659 ps
CPU time 0.89 seconds
Started Feb 18 02:24:32 PM PST 24
Finished Feb 18 02:24:39 PM PST 24
Peak memory 203332 kb
Host smart-d85101b1-83bf-4a70-ae53-563c5ca0ac0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927019063 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.2927019063
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.1275747207
Short name T140
Test name
Test status
Simulation time 248126319 ps
CPU time 1.17 seconds
Started Feb 18 02:24:30 PM PST 24
Finished Feb 18 02:24:39 PM PST 24
Peak memory 203376 kb
Host smart-7a75e742-d177-4868-adfe-ed27fcafaef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275747207 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.1275747207
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.516091689
Short name T19
Test name
Test status
Simulation time 1178789179 ps
CPU time 1.76 seconds
Started Feb 18 02:24:48 PM PST 24
Finished Feb 18 02:24:54 PM PST 24
Peak memory 203804 kb
Host smart-ce1f5578-9516-44c9-ab95-bac5e2bb7ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516091689 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.516091689
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.165505863
Short name T206
Test name
Test status
Simulation time 507537690 ps
CPU time 2.15 seconds
Started Feb 18 02:24:28 PM PST 24
Finished Feb 18 02:24:37 PM PST 24
Peak memory 203884 kb
Host smart-431fb80e-06fb-4ca2-b498-db8b0abbad9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165505863 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.165505863
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.1645179800
Short name T190
Test name
Test status
Simulation time 303238697 ps
CPU time 1.59 seconds
Started Feb 18 02:24:26 PM PST 24
Finished Feb 18 02:24:31 PM PST 24
Peak memory 203404 kb
Host smart-47a118d5-697f-4a1b-9370-ed811ac36811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645179800 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.1645179800
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.4272889051
Short name T26
Test name
Test status
Simulation time 2785879970 ps
CPU time 4.11 seconds
Started Feb 18 02:24:32 PM PST 24
Finished Feb 18 02:24:43 PM PST 24
Peak memory 203800 kb
Host smart-b0f29b88-b6a8-4d1d-b4a4-8b4fce0211f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272889051 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.4272889051
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.2696212070
Short name T221
Test name
Test status
Simulation time 26902496 ps
CPU time 0.64 seconds
Started Feb 18 02:25:05 PM PST 24
Finished Feb 18 02:25:07 PM PST 24
Peak memory 203624 kb
Host smart-18d71b71-d2cc-48fb-8184-be3c90a7a6e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696212070 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.2696212070
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.1168034600
Short name T125
Test name
Test status
Simulation time 3006002551 ps
CPU time 4.02 seconds
Started Feb 18 02:24:53 PM PST 24
Finished Feb 18 02:25:05 PM PST 24
Peak memory 203948 kb
Host smart-695ada39-6d0b-41c1-8f1c-2aceda875641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168034600 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.1168034600
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.2146782549
Short name T8
Test name
Test status
Simulation time 1047531100 ps
CPU time 4.21 seconds
Started Feb 18 02:24:54 PM PST 24
Finished Feb 18 02:25:05 PM PST 24
Peak memory 203856 kb
Host smart-797467fa-ba01-42a6-9b3b-1883eccb59ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146782549 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.2146782549
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.4137982481
Short name T5
Test name
Test status
Simulation time 109466609 ps
CPU time 0.93 seconds
Started Feb 18 02:24:55 PM PST 24
Finished Feb 18 02:25:02 PM PST 24
Peak memory 203500 kb
Host smart-8c5564e2-1434-44aa-8d9b-69352c977923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137982481 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.4137982481
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.107976510
Short name T29
Test name
Test status
Simulation time 264417743 ps
CPU time 0.96 seconds
Started Feb 18 02:24:53 PM PST 24
Finished Feb 18 02:25:02 PM PST 24
Peak memory 203420 kb
Host smart-51b9136a-2008-4584-b2eb-9e7d58f27d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107976510 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.107976510
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.2888330268
Short name T137
Test name
Test status
Simulation time 818295390 ps
CPU time 3.34 seconds
Started Feb 18 02:24:52 PM PST 24
Finished Feb 18 02:25:03 PM PST 24
Peak memory 203740 kb
Host smart-5e6ee1d0-41bc-4a9a-8432-da1d5b1f71b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888330268 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.2888330268
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.1671420763
Short name T138
Test name
Test status
Simulation time 36410649 ps
CPU time 0.71 seconds
Started Feb 18 02:24:59 PM PST 24
Finished Feb 18 02:25:03 PM PST 24
Peak memory 203400 kb
Host smart-e420e522-fcfc-46cc-a8c6-5292d95d4f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671420763 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.1671420763
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.3386837636
Short name T65
Test name
Test status
Simulation time 12898218177 ps
CPU time 41.69 seconds
Started Feb 18 02:24:54 PM PST 24
Finished Feb 18 02:25:43 PM PST 24
Peak memory 203208 kb
Host smart-abd7e733-b9c3-46cd-9a74-ca29fff0f496
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3386837636 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.3386837636
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.3390547858
Short name T86
Test name
Test status
Simulation time 140826318 ps
CPU time 1.04 seconds
Started Feb 18 02:24:59 PM PST 24
Finished Feb 18 02:25:04 PM PST 24
Peak memory 203576 kb
Host smart-feb32eb7-4774-4f39-b3e7-2b0f173c7c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390547858 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.3390547858
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.1475687269
Short name T187
Test name
Test status
Simulation time 50145714 ps
CPU time 0.68 seconds
Started Feb 18 02:24:51 PM PST 24
Finished Feb 18 02:25:00 PM PST 24
Peak memory 203316 kb
Host smart-d2748420-4edd-439a-bdb8-d52ab6a3527c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475687269 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.1475687269
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.4006857577
Short name T205
Test name
Test status
Simulation time 80951327 ps
CPU time 0.86 seconds
Started Feb 18 02:25:06 PM PST 24
Finished Feb 18 02:25:08 PM PST 24
Peak memory 203476 kb
Host smart-63a4fc2e-c874-4ea8-b845-934d2614bef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006857577 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.4006857577
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.3301082574
Short name T18
Test name
Test status
Simulation time 190320938 ps
CPU time 1.1 seconds
Started Feb 18 02:25:05 PM PST 24
Finished Feb 18 02:25:07 PM PST 24
Peak memory 203316 kb
Host smart-1b0bd119-95e0-4ed8-b15c-55da9bdd00e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301082574 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.3301082574
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.1822649901
Short name T30
Test name
Test status
Simulation time 30317320 ps
CPU time 0.75 seconds
Started Feb 18 02:25:04 PM PST 24
Finished Feb 18 02:25:07 PM PST 24
Peak memory 203476 kb
Host smart-18324000-ce10-4f14-bafc-65d4fd36cdb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822649901 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.1822649901
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.4044018221
Short name T139
Test name
Test status
Simulation time 27948055 ps
CPU time 0.72 seconds
Started Feb 18 02:24:52 PM PST 24
Finished Feb 18 02:25:00 PM PST 24
Peak memory 203584 kb
Host smart-d4280d4b-1e23-4e7c-ab46-a0e956475fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044018221 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.4044018221
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.146252261
Short name T7
Test name
Test status
Simulation time 856028247 ps
CPU time 2.87 seconds
Started Feb 18 02:24:53 PM PST 24
Finished Feb 18 02:25:04 PM PST 24
Peak memory 203696 kb
Host smart-fba71257-34b5-46c4-aae8-3ad6c5f2c9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146252261 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.146252261
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.1113467854
Short name T85
Test name
Test status
Simulation time 921417002 ps
CPU time 1.77 seconds
Started Feb 18 02:24:57 PM PST 24
Finished Feb 18 02:25:04 PM PST 24
Peak memory 203876 kb
Host smart-0501f75a-583a-4cc2-8eb8-ffb271fd0a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113467854 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.1113467854
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.2025083187
Short name T173
Test name
Test status
Simulation time 6972364028 ps
CPU time 10.97 seconds
Started Feb 18 02:24:46 PM PST 24
Finished Feb 18 02:25:01 PM PST 24
Peak memory 204008 kb
Host smart-edb6bcb1-5d33-4e73-acca-d80cd6382547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025083187 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.2025083187
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.3502816089
Short name T37
Test name
Test status
Simulation time 169796658 ps
CPU time 1.22 seconds
Started Feb 18 02:25:03 PM PST 24
Finished Feb 18 02:25:06 PM PST 24
Peak memory 220108 kb
Host smart-71f207e9-a8f2-49cb-bdfd-fa718febbb0d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502816089 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.3502816089
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.1700882035
Short name T220
Test name
Test status
Simulation time 197632174 ps
CPU time 1.22 seconds
Started Feb 18 02:24:49 PM PST 24
Finished Feb 18 02:24:57 PM PST 24
Peak memory 203392 kb
Host smart-d77c4913-9e6f-466e-a192-1230ac9f9c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700882035 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.1700882035
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.2186940706
Short name T209
Test name
Test status
Simulation time 1042484564 ps
CPU time 5.3 seconds
Started Feb 18 02:25:45 PM PST 24
Finished Feb 18 02:25:51 PM PST 24
Peak memory 203940 kb
Host smart-08d880f1-3702-4677-9e28-1f3c124ce5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186940706 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.2186940706
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.3410103192
Short name T193
Test name
Test status
Simulation time 2628695332 ps
CPU time 8.65 seconds
Started Feb 18 02:25:45 PM PST 24
Finished Feb 18 02:25:55 PM PST 24
Peak memory 203980 kb
Host smart-5bb3a719-92cd-4173-8a5f-112cc38976a9
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3410103192 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.3410103192
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.326499474
Short name T181
Test name
Test status
Simulation time 1940569302 ps
CPU time 8.12 seconds
Started Feb 18 02:25:36 PM PST 24
Finished Feb 18 02:25:47 PM PST 24
Peak memory 203884 kb
Host smart-a7c3b44b-065c-4897-bdad-fd1c505264c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326499474 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.326499474
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.34082820
Short name T123
Test name
Test status
Simulation time 53376288 ps
CPU time 0.65 seconds
Started Feb 18 02:25:51 PM PST 24
Finished Feb 18 02:25:53 PM PST 24
Peak memory 203604 kb
Host smart-c10cb4b6-b352-4c0d-b2b0-fb5a6709f492
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34082820 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.34082820
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.1684695528
Short name T212
Test name
Test status
Simulation time 962591318 ps
CPU time 3.24 seconds
Started Feb 18 02:25:45 PM PST 24
Finished Feb 18 02:25:49 PM PST 24
Peak memory 203920 kb
Host smart-37d9f8de-bc83-4545-a9e3-3b423f1cebd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684695528 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.1684695528
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.641309420
Short name T191
Test name
Test status
Simulation time 12714306885 ps
CPU time 14.27 seconds
Started Feb 18 02:25:45 PM PST 24
Finished Feb 18 02:26:00 PM PST 24
Peak memory 204024 kb
Host smart-9953fe85-913f-4fa2-a78c-a1a3d229268f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=641309420 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_t
l_access.641309420
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.49173558
Short name T176
Test name
Test status
Simulation time 8482243976 ps
CPU time 5.51 seconds
Started Feb 18 02:25:45 PM PST 24
Finished Feb 18 02:25:52 PM PST 24
Peak memory 203960 kb
Host smart-18be7907-5fe4-4187-90c4-8bcb93c3f983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49173558 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.49173558
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.536439275
Short name T153
Test name
Test status
Simulation time 18986275 ps
CPU time 0.68 seconds
Started Feb 18 02:25:49 PM PST 24
Finished Feb 18 02:25:50 PM PST 24
Peak memory 203600 kb
Host smart-725317ea-b42d-49c0-8666-0461020cd8ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536439275 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.536439275
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.814266521
Short name T172
Test name
Test status
Simulation time 32181679369 ps
CPU time 47.07 seconds
Started Feb 18 02:25:50 PM PST 24
Finished Feb 18 02:26:38 PM PST 24
Peak memory 204028 kb
Host smart-dba9fcea-67da-4bcc-b3b9-f6377e9abfb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814266521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.814266521
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.3755013105
Short name T188
Test name
Test status
Simulation time 1184830867 ps
CPU time 6.24 seconds
Started Feb 18 02:25:51 PM PST 24
Finished Feb 18 02:25:58 PM PST 24
Peak memory 203956 kb
Host smart-35aeb17b-93e5-4cfb-8c47-243366ed0ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755013105 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.3755013105
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.3700389833
Short name T183
Test name
Test status
Simulation time 874660747 ps
CPU time 3.4 seconds
Started Feb 18 02:25:50 PM PST 24
Finished Feb 18 02:25:54 PM PST 24
Peak memory 203860 kb
Host smart-fc3dcfe8-3067-485e-b3cc-e69d00de7af0
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3700389833 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.3700389833
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.3061137729
Short name T157
Test name
Test status
Simulation time 29802692 ps
CPU time 0.69 seconds
Started Feb 18 02:25:58 PM PST 24
Finished Feb 18 02:26:01 PM PST 24
Peak memory 203608 kb
Host smart-5d566e44-1f36-4d23-8496-567df470f7dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061137729 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.3061137729
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.4173089499
Short name T175
Test name
Test status
Simulation time 4739352197 ps
CPU time 13.9 seconds
Started Feb 18 02:26:00 PM PST 24
Finished Feb 18 02:26:16 PM PST 24
Peak memory 203936 kb
Host smart-3723f436-1cd2-4257-89ce-6ec8f2075273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173089499 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.4173089499
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.3227323284
Short name T217
Test name
Test status
Simulation time 684470583 ps
CPU time 1.7 seconds
Started Feb 18 02:25:58 PM PST 24
Finished Feb 18 02:26:02 PM PST 24
Peak memory 203916 kb
Host smart-6d41ffef-bff8-4e54-949b-e7e634b65102
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3227323284 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_
tl_access.3227323284
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.3890851804
Short name T66
Test name
Test status
Simulation time 5696704007 ps
CPU time 6.7 seconds
Started Feb 18 02:26:00 PM PST 24
Finished Feb 18 02:26:09 PM PST 24
Peak memory 204064 kb
Host smart-dce40c11-7dfb-4c17-98b2-2009e0792681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890851804 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.3890851804
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.3073012437
Short name T148
Test name
Test status
Simulation time 30804036 ps
CPU time 0.67 seconds
Started Feb 18 02:26:05 PM PST 24
Finished Feb 18 02:26:08 PM PST 24
Peak memory 203600 kb
Host smart-ec897395-7fa1-4c50-90e6-918ed821bf0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073012437 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.3073012437
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.1140384052
Short name T226
Test name
Test status
Simulation time 3354826942 ps
CPU time 7.12 seconds
Started Feb 18 02:25:59 PM PST 24
Finished Feb 18 02:26:09 PM PST 24
Peak memory 204008 kb
Host smart-4a036ab3-59e1-4725-aab3-bd4b22296dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140384052 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.1140384052
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.529969348
Short name T73
Test name
Test status
Simulation time 7099743232 ps
CPU time 6.15 seconds
Started Feb 18 02:26:01 PM PST 24
Finished Feb 18 02:26:09 PM PST 24
Peak memory 204020 kb
Host smart-9ec0c405-522d-4577-96ce-ed5a3dcb61bb
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=529969348 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_t
l_access.529969348
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.2138000668
Short name T79
Test name
Test status
Simulation time 630725258 ps
CPU time 1.33 seconds
Started Feb 18 02:25:58 PM PST 24
Finished Feb 18 02:26:01 PM PST 24
Peak memory 203876 kb
Host smart-031e1f4a-6410-4ddd-8ab5-0ee176886815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138000668 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.2138000668
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.888032279
Short name T62
Test name
Test status
Simulation time 207684731 ps
CPU time 0.63 seconds
Started Feb 18 02:26:11 PM PST 24
Finished Feb 18 02:26:13 PM PST 24
Peak memory 203580 kb
Host smart-67b34f7c-2c08-466d-b03f-bcf69a2c25eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888032279 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.888032279
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.1299273377
Short name T171
Test name
Test status
Simulation time 10870647574 ps
CPU time 11.99 seconds
Started Feb 18 02:26:17 PM PST 24
Finished Feb 18 02:26:31 PM PST 24
Peak memory 203992 kb
Host smart-535c9d73-a116-4c0f-a24f-2d281e611e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299273377 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.1299273377
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.1912512998
Short name T194
Test name
Test status
Simulation time 3138822541 ps
CPU time 11.02 seconds
Started Feb 18 02:26:14 PM PST 24
Finished Feb 18 02:26:26 PM PST 24
Peak memory 203976 kb
Host smart-eb92e05a-d4f4-4399-a35f-107c72c4b950
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1912512998 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_
tl_access.1912512998
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.2081422075
Short name T72
Test name
Test status
Simulation time 1719578332 ps
CPU time 8.07 seconds
Started Feb 18 02:26:21 PM PST 24
Finished Feb 18 02:26:31 PM PST 24
Peak memory 203836 kb
Host smart-2205e034-fa4b-423f-addc-512e295cd11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081422075 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.2081422075
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.1464946756
Short name T160
Test name
Test status
Simulation time 17236532 ps
CPU time 0.67 seconds
Started Feb 18 02:26:17 PM PST 24
Finished Feb 18 02:26:19 PM PST 24
Peak memory 203600 kb
Host smart-9f6aedbf-0fcf-4872-8440-d38454c1f278
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464946756 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.1464946756
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.1411471293
Short name T210
Test name
Test status
Simulation time 4741746516 ps
CPU time 7.14 seconds
Started Feb 18 02:26:20 PM PST 24
Finished Feb 18 02:26:30 PM PST 24
Peak memory 204036 kb
Host smart-605771db-44ad-4222-a5ff-0502ef1aaeeb
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1411471293 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_
tl_access.1411471293
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.779367268
Short name T201
Test name
Test status
Simulation time 8980852245 ps
CPU time 15.91 seconds
Started Feb 18 02:26:18 PM PST 24
Finished Feb 18 02:26:35 PM PST 24
Peak memory 204020 kb
Host smart-dd4798af-9328-4462-97c2-6df9159f3e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779367268 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.779367268
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.2062299734
Short name T144
Test name
Test status
Simulation time 48948307 ps
CPU time 0.64 seconds
Started Feb 18 02:26:16 PM PST 24
Finished Feb 18 02:26:18 PM PST 24
Peak memory 203588 kb
Host smart-a8d1179e-324e-4416-b769-260ffb0aa47d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062299734 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.2062299734
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.1579297380
Short name T170
Test name
Test status
Simulation time 46187158612 ps
CPU time 114.14 seconds
Started Feb 18 02:26:23 PM PST 24
Finished Feb 18 02:28:19 PM PST 24
Peak memory 203984 kb
Host smart-cc074a1c-e8eb-4375-b0cd-97f50809a061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579297380 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.1579297380
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.3847138090
Short name T213
Test name
Test status
Simulation time 10840971839 ps
CPU time 34.04 seconds
Started Feb 18 02:26:18 PM PST 24
Finished Feb 18 02:26:54 PM PST 24
Peak memory 204040 kb
Host smart-782e94a3-1017-49b3-b328-7ab1b86e195f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847138090 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.3847138090
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.793482897
Short name T94
Test name
Test status
Simulation time 1714842887 ps
CPU time 6.51 seconds
Started Feb 18 02:26:17 PM PST 24
Finished Feb 18 02:26:25 PM PST 24
Peak memory 203908 kb
Host smart-cc8d5532-93d2-40d5-a24a-ec242ec68cf9
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=793482897 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_t
l_access.793482897
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.1151887307
Short name T231
Test name
Test status
Simulation time 4031072175 ps
CPU time 13.65 seconds
Started Feb 18 02:26:17 PM PST 24
Finished Feb 18 02:26:32 PM PST 24
Peak memory 203980 kb
Host smart-a00c645f-d2fe-498b-b897-44c6e218f3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151887307 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.1151887307
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.3381685566
Short name T211
Test name
Test status
Simulation time 47255411 ps
CPU time 0.66 seconds
Started Feb 18 02:26:17 PM PST 24
Finished Feb 18 02:26:20 PM PST 24
Peak memory 203524 kb
Host smart-a6d895ad-58cf-4f13-b070-b271ab783227
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381685566 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.3381685566
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.3887230591
Short name T230
Test name
Test status
Simulation time 13882972437 ps
CPU time 16.38 seconds
Started Feb 18 02:26:23 PM PST 24
Finished Feb 18 02:26:41 PM PST 24
Peak memory 204064 kb
Host smart-8deea271-ae26-469a-856d-751320299e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887230591 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.3887230591
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.4078993128
Short name T207
Test name
Test status
Simulation time 1745041084 ps
CPU time 3.52 seconds
Started Feb 18 02:26:20 PM PST 24
Finished Feb 18 02:26:26 PM PST 24
Peak memory 203952 kb
Host smart-07308fb6-5fec-48a7-be3d-1fc1ca68a758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078993128 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.4078993128
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.2531305680
Short name T3
Test name
Test status
Simulation time 4035783107 ps
CPU time 6.72 seconds
Started Feb 18 02:26:20 PM PST 24
Finished Feb 18 02:26:29 PM PST 24
Peak memory 203884 kb
Host smart-8332b788-d082-4842-b505-6381f414b8a2
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2531305680 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_
tl_access.2531305680
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.693523031
Short name T233
Test name
Test status
Simulation time 4670299793 ps
CPU time 9.47 seconds
Started Feb 18 02:26:18 PM PST 24
Finished Feb 18 02:26:29 PM PST 24
Peak memory 204020 kb
Host smart-ac7ac919-f7e1-40d7-816d-ad416ef4cdb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693523031 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.693523031
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.1504993224
Short name T154
Test name
Test status
Simulation time 38001202 ps
CPU time 0.69 seconds
Started Feb 18 02:26:20 PM PST 24
Finished Feb 18 02:26:23 PM PST 24
Peak memory 203596 kb
Host smart-62bf665f-44de-4040-b145-4e16c54877ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504993224 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.1504993224
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.3664062262
Short name T229
Test name
Test status
Simulation time 2394121037 ps
CPU time 7.85 seconds
Started Feb 18 02:26:26 PM PST 24
Finished Feb 18 02:26:36 PM PST 24
Peak memory 203964 kb
Host smart-f918301b-3a17-4569-a083-2e666cd52c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664062262 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.3664062262
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.1273169507
Short name T208
Test name
Test status
Simulation time 4247186716 ps
CPU time 10.51 seconds
Started Feb 18 02:26:26 PM PST 24
Finished Feb 18 02:26:39 PM PST 24
Peak memory 204012 kb
Host smart-9932ff54-6730-4d82-864f-58ff8dacff82
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1273169507 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_
tl_access.1273169507
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.4083040835
Short name T189
Test name
Test status
Simulation time 5924113487 ps
CPU time 18.96 seconds
Started Feb 18 02:26:20 PM PST 24
Finished Feb 18 02:26:42 PM PST 24
Peak memory 204008 kb
Host smart-36952526-030b-4a31-923e-8740ca3d2366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083040835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.4083040835
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.397968999
Short name T159
Test name
Test status
Simulation time 66175239 ps
CPU time 0.67 seconds
Started Feb 18 02:25:15 PM PST 24
Finished Feb 18 02:25:17 PM PST 24
Peak memory 203512 kb
Host smart-a7f05ef1-8d0f-405f-89b8-b6d1ff74adee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397968999 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.397968999
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.3593469261
Short name T180
Test name
Test status
Simulation time 20962445337 ps
CPU time 48.77 seconds
Started Feb 18 02:25:10 PM PST 24
Finished Feb 18 02:26:00 PM PST 24
Peak memory 203944 kb
Host smart-ad35e750-918f-4bd7-b972-f725b1985db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593469261 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.3593469261
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.1801211683
Short name T185
Test name
Test status
Simulation time 1808225536 ps
CPU time 5.93 seconds
Started Feb 18 02:25:09 PM PST 24
Finished Feb 18 02:25:16 PM PST 24
Peak memory 203880 kb
Host smart-1b8e8874-a6ea-4a5b-8dd4-a42ae8dea487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801211683 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.1801211683
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.3925843912
Short name T219
Test name
Test status
Simulation time 2658342398 ps
CPU time 5.99 seconds
Started Feb 18 02:25:10 PM PST 24
Finished Feb 18 02:25:16 PM PST 24
Peak memory 204008 kb
Host smart-75e6a578-afd6-418e-92f6-74928f0ef33a
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3925843912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.3925843912
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.1990763282
Short name T10
Test name
Test status
Simulation time 103996348 ps
CPU time 0.71 seconds
Started Feb 18 02:25:11 PM PST 24
Finished Feb 18 02:25:13 PM PST 24
Peak memory 203472 kb
Host smart-e28c977a-0e4f-4b46-b90f-bc32a3c03b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990763282 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.1990763282
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.3507503469
Short name T168
Test name
Test status
Simulation time 1812717976 ps
CPU time 8.33 seconds
Started Feb 18 02:25:04 PM PST 24
Finished Feb 18 02:25:14 PM PST 24
Peak memory 203916 kb
Host smart-37df5550-bbe0-4cc9-8be5-2792b1883d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507503469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.3507503469
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.131531719
Short name T38
Test name
Test status
Simulation time 656510586 ps
CPU time 1.03 seconds
Started Feb 18 02:25:12 PM PST 24
Finished Feb 18 02:25:14 PM PST 24
Peak memory 220132 kb
Host smart-506e1db6-1936-4c09-ad45-3acf541636f6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131531719 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.131531719
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.928937984
Short name T147
Test name
Test status
Simulation time 30983404 ps
CPU time 0.68 seconds
Started Feb 18 02:26:22 PM PST 24
Finished Feb 18 02:26:25 PM PST 24
Peak memory 203588 kb
Host smart-265f7547-6d25-44c7-8e4d-0e9c7ac2bae8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928937984 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.928937984
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.1330778812
Short name T156
Test name
Test status
Simulation time 28317857 ps
CPU time 0.66 seconds
Started Feb 18 02:26:33 PM PST 24
Finished Feb 18 02:26:36 PM PST 24
Peak memory 203608 kb
Host smart-f691d432-e38c-406d-b0f7-e7f60ec29741
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330778812 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.1330778812
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.2827450126
Short name T52
Test name
Test status
Simulation time 24291547 ps
CPU time 0.71 seconds
Started Feb 18 02:26:22 PM PST 24
Finished Feb 18 02:26:25 PM PST 24
Peak memory 203596 kb
Host smart-d1c72604-a41b-43f1-8b3a-c7ade909e28f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827450126 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.2827450126
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.2192563158
Short name T150
Test name
Test status
Simulation time 114047781 ps
CPU time 0.75 seconds
Started Feb 18 02:26:25 PM PST 24
Finished Feb 18 02:26:29 PM PST 24
Peak memory 203580 kb
Host smart-0d5fadb5-5373-439b-852d-fb31184d299e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192563158 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.2192563158
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_stress_all.4271423679
Short name T20
Test name
Test status
Simulation time 1948808150 ps
CPU time 4.48 seconds
Started Feb 18 02:26:24 PM PST 24
Finished Feb 18 02:26:31 PM PST 24
Peak memory 203808 kb
Host smart-be6e672d-a1b4-4641-8394-036a3255adea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271423679 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.4271423679
Directory /workspace/24.rv_dm_stress_all/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.3140017765
Short name T186
Test name
Test status
Simulation time 24771428 ps
CPU time 0.63 seconds
Started Feb 18 02:26:31 PM PST 24
Finished Feb 18 02:26:34 PM PST 24
Peak memory 203576 kb
Host smart-cdff8ef9-1e69-425b-8a4b-cba3cfb25dbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140017765 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.3140017765
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.2110020781
Short name T177
Test name
Test status
Simulation time 53600292 ps
CPU time 0.65 seconds
Started Feb 18 02:26:34 PM PST 24
Finished Feb 18 02:26:38 PM PST 24
Peak memory 203612 kb
Host smart-36eaaf54-163d-4aaf-af63-b0924ec69d37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110020781 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.2110020781
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_stress_all.57372750
Short name T84
Test name
Test status
Simulation time 4485949420 ps
CPU time 4.38 seconds
Started Feb 18 02:26:26 PM PST 24
Finished Feb 18 02:26:33 PM PST 24
Peak memory 203924 kb
Host smart-90f18261-d6ab-4df1-905b-892f8075101b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57372750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.57372750
Directory /workspace/26.rv_dm_stress_all/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.806015147
Short name T163
Test name
Test status
Simulation time 17455719 ps
CPU time 0.7 seconds
Started Feb 18 02:26:34 PM PST 24
Finished Feb 18 02:26:38 PM PST 24
Peak memory 203628 kb
Host smart-734e5849-728e-4f9c-b791-e3c9f7fb0f6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806015147 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.806015147
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.662660720
Short name T222
Test name
Test status
Simulation time 22312308 ps
CPU time 0.62 seconds
Started Feb 18 02:26:31 PM PST 24
Finished Feb 18 02:26:33 PM PST 24
Peak memory 203580 kb
Host smart-6812dcb4-d974-48f9-8c32-54ace3e84b37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662660720 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.662660720
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_stress_all.1236476394
Short name T34
Test name
Test status
Simulation time 544609628 ps
CPU time 2.35 seconds
Started Feb 18 02:26:35 PM PST 24
Finished Feb 18 02:26:42 PM PST 24
Peak memory 203744 kb
Host smart-2d442796-636f-48a0-b409-f15a6d9d20ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236476394 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.1236476394
Directory /workspace/28.rv_dm_stress_all/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.3441908027
Short name T143
Test name
Test status
Simulation time 18425762 ps
CPU time 0.67 seconds
Started Feb 18 02:26:25 PM PST 24
Finished Feb 18 02:26:28 PM PST 24
Peak memory 203596 kb
Host smart-972a53a0-2e94-4dbd-bd8c-7363ecda2f61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441908027 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.3441908027
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.3368627368
Short name T90
Test name
Test status
Simulation time 62787109 ps
CPU time 0.74 seconds
Started Feb 18 02:25:17 PM PST 24
Finished Feb 18 02:25:19 PM PST 24
Peak memory 203540 kb
Host smart-2ad43831-7453-46cf-8360-774e77bcb326
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368627368 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.3368627368
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.113591955
Short name T126
Test name
Test status
Simulation time 945422462 ps
CPU time 3.13 seconds
Started Feb 18 02:25:20 PM PST 24
Finished Feb 18 02:25:25 PM PST 24
Peak memory 203840 kb
Host smart-b193a48b-8698-422e-bd60-780fcb3969b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113591955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.113591955
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.1362370620
Short name T198
Test name
Test status
Simulation time 3465231925 ps
CPU time 7.69 seconds
Started Feb 18 02:25:15 PM PST 24
Finished Feb 18 02:25:23 PM PST 24
Peak memory 203964 kb
Host smart-3c08beec-7d48-4602-b4b6-21d7b9801752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362370620 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.1362370620
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.4081143506
Short name T32
Test name
Test status
Simulation time 3050534248 ps
CPU time 14.39 seconds
Started Feb 18 02:25:14 PM PST 24
Finished Feb 18 02:25:29 PM PST 24
Peak memory 204032 kb
Host smart-aad08384-5454-4ddb-a015-f8d9718417b2
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4081143506 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.4081143506
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.3320162532
Short name T225
Test name
Test status
Simulation time 73724494 ps
CPU time 0.79 seconds
Started Feb 18 02:25:15 PM PST 24
Finished Feb 18 02:25:16 PM PST 24
Peak memory 203488 kb
Host smart-c654d498-5de2-471d-890e-b783495f9c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320162532 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.3320162532
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.2695273339
Short name T199
Test name
Test status
Simulation time 2313761415 ps
CPU time 4.85 seconds
Started Feb 18 02:25:16 PM PST 24
Finished Feb 18 02:25:22 PM PST 24
Peak memory 203912 kb
Host smart-a6180f7a-90a4-498f-98d0-847b0a7c1f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695273339 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.2695273339
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.3709349530
Short name T39
Test name
Test status
Simulation time 100285757 ps
CPU time 1.27 seconds
Started Feb 18 02:25:18 PM PST 24
Finished Feb 18 02:25:20 PM PST 24
Peak memory 219948 kb
Host smart-73f72f56-af73-4173-8461-3f04537330c6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709349530 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.3709349530
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all.28244351
Short name T12
Test name
Test status
Simulation time 3954147630 ps
CPU time 11.73 seconds
Started Feb 18 02:25:17 PM PST 24
Finished Feb 18 02:25:30 PM PST 24
Peak memory 203836 kb
Host smart-af4a2ea0-b1df-4409-90f2-59f5225c3e0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28244351 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.28244351
Directory /workspace/3.rv_dm_stress_all/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.1610555230
Short name T151
Test name
Test status
Simulation time 53077606 ps
CPU time 0.67 seconds
Started Feb 18 02:26:34 PM PST 24
Finished Feb 18 02:26:38 PM PST 24
Peak memory 203536 kb
Host smart-0d72e0cb-aba5-4c86-be4f-c3399850433d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610555230 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.1610555230
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.3241590357
Short name T197
Test name
Test status
Simulation time 40279298 ps
CPU time 0.67 seconds
Started Feb 18 02:26:34 PM PST 24
Finished Feb 18 02:26:38 PM PST 24
Peak memory 203536 kb
Host smart-f192d7e1-5226-44f7-956c-ec7f10a9bcd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241590357 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.3241590357
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.2164355802
Short name T2
Test name
Test status
Simulation time 48250736 ps
CPU time 0.66 seconds
Started Feb 18 02:26:31 PM PST 24
Finished Feb 18 02:26:33 PM PST 24
Peak memory 203584 kb
Host smart-e71def24-87b7-4356-83a2-e7dc381c0aa4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164355802 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.2164355802
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.402264373
Short name T158
Test name
Test status
Simulation time 66264586 ps
CPU time 0.64 seconds
Started Feb 18 02:26:39 PM PST 24
Finished Feb 18 02:26:44 PM PST 24
Peak memory 203592 kb
Host smart-1fdaceac-f223-4004-925e-fe8844d0ec9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402264373 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.402264373
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.1266623093
Short name T164
Test name
Test status
Simulation time 122480202 ps
CPU time 0.66 seconds
Started Feb 18 02:26:37 PM PST 24
Finished Feb 18 02:26:43 PM PST 24
Peak memory 203612 kb
Host smart-d236401f-ff5f-4316-97db-8ce14f3cc2e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266623093 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.1266623093
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.1438691700
Short name T146
Test name
Test status
Simulation time 30621262 ps
CPU time 0.67 seconds
Started Feb 18 02:26:40 PM PST 24
Finished Feb 18 02:26:45 PM PST 24
Peak memory 203608 kb
Host smart-bbe813e6-369e-4ee3-8f88-fd3523010520
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438691700 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.1438691700
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.1675011151
Short name T149
Test name
Test status
Simulation time 126906741 ps
CPU time 0.65 seconds
Started Feb 18 02:26:38 PM PST 24
Finished Feb 18 02:26:43 PM PST 24
Peak memory 203592 kb
Host smart-8d379482-2cb5-4188-bcda-da0a979bf26c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675011151 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.1675011151
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.1609798619
Short name T54
Test name
Test status
Simulation time 40630465 ps
CPU time 0.68 seconds
Started Feb 18 02:26:37 PM PST 24
Finished Feb 18 02:26:43 PM PST 24
Peak memory 203592 kb
Host smart-7337fe61-d022-459b-ada3-3d6870ad21b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609798619 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.1609798619
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.1776707869
Short name T92
Test name
Test status
Simulation time 26589953 ps
CPU time 0.64 seconds
Started Feb 18 02:26:52 PM PST 24
Finished Feb 18 02:26:54 PM PST 24
Peak memory 203596 kb
Host smart-af08a13f-7e8c-4a01-92d1-8d32390c8f3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776707869 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.1776707869
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.1673911881
Short name T53
Test name
Test status
Simulation time 67103420 ps
CPU time 0.65 seconds
Started Feb 18 02:26:49 PM PST 24
Finished Feb 18 02:26:52 PM PST 24
Peak memory 203580 kb
Host smart-60cfed67-e6d5-4b85-900f-fd251c21d27e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673911881 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.1673911881
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.478478338
Short name T152
Test name
Test status
Simulation time 48027082 ps
CPU time 0.67 seconds
Started Feb 18 02:25:33 PM PST 24
Finished Feb 18 02:25:37 PM PST 24
Peak memory 203528 kb
Host smart-fe0cb120-d8c3-4d9a-a14c-87028ef1aca6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478478338 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.478478338
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.856144929
Short name T228
Test name
Test status
Simulation time 46289329763 ps
CPU time 150.7 seconds
Started Feb 18 02:25:35 PM PST 24
Finished Feb 18 02:28:08 PM PST 24
Peak memory 203964 kb
Host smart-1e2223c6-52d9-413e-ad38-edb3be6dd8d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856144929 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.856144929
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.284236700
Short name T67
Test name
Test status
Simulation time 1973695941 ps
CPU time 5.23 seconds
Started Feb 18 02:25:24 PM PST 24
Finished Feb 18 02:25:32 PM PST 24
Peak memory 203904 kb
Host smart-befbaafb-1705-4756-ab3e-f16358c2018b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284236700 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.284236700
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.382126564
Short name T50
Test name
Test status
Simulation time 14308254130 ps
CPU time 50.23 seconds
Started Feb 18 02:25:18 PM PST 24
Finished Feb 18 02:26:09 PM PST 24
Peak memory 203964 kb
Host smart-b752b8c6-b9ae-4f88-9f5a-d86f7f40a69b
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=382126564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_tl
_access.382126564
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.462644884
Short name T9
Test name
Test status
Simulation time 61021011 ps
CPU time 0.66 seconds
Started Feb 18 02:25:23 PM PST 24
Finished Feb 18 02:25:26 PM PST 24
Peak memory 203212 kb
Host smart-d693a828-18a7-421e-965a-325079b2d66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462644884 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.462644884
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.2876175265
Short name T227
Test name
Test status
Simulation time 2098000325 ps
CPU time 9.87 seconds
Started Feb 18 02:25:15 PM PST 24
Finished Feb 18 02:25:26 PM PST 24
Peak memory 203924 kb
Host smart-5debdf56-0b13-4131-847d-1635c0ca1333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876175265 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.2876175265
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.1697396079
Short name T68
Test name
Test status
Simulation time 115625604 ps
CPU time 1.19 seconds
Started Feb 18 02:25:34 PM PST 24
Finished Feb 18 02:25:39 PM PST 24
Peak memory 218800 kb
Host smart-7d135d8e-5ca1-449e-a444-417f71dbfeb7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697396079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.1697396079
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.3533537798
Short name T55
Test name
Test status
Simulation time 35183508 ps
CPU time 0.74 seconds
Started Feb 18 02:26:48 PM PST 24
Finished Feb 18 02:26:51 PM PST 24
Peak memory 203608 kb
Host smart-22a87692-c2fc-43a3-92b9-16105194ec5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533537798 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.3533537798
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.2410425029
Short name T31
Test name
Test status
Simulation time 50309729 ps
CPU time 0.72 seconds
Started Feb 18 02:27:01 PM PST 24
Finished Feb 18 02:27:07 PM PST 24
Peak memory 203600 kb
Host smart-3587e502-608f-4bd4-b519-e66f9b8860e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410425029 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.2410425029
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.3376183572
Short name T162
Test name
Test status
Simulation time 23162043 ps
CPU time 0.77 seconds
Started Feb 18 02:26:59 PM PST 24
Finished Feb 18 02:27:03 PM PST 24
Peak memory 203608 kb
Host smart-574b2e7f-852d-4fce-afba-5eb514384b0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376183572 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.3376183572
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_stress_all.1712595479
Short name T25
Test name
Test status
Simulation time 2084782890 ps
CPU time 4.27 seconds
Started Feb 18 02:26:56 PM PST 24
Finished Feb 18 02:27:03 PM PST 24
Peak memory 203716 kb
Host smart-74c23c70-bae5-4ffd-a870-945aed89c266
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712595479 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.1712595479
Directory /workspace/42.rv_dm_stress_all/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.702367148
Short name T155
Test name
Test status
Simulation time 24095688 ps
CPU time 0.69 seconds
Started Feb 18 02:27:03 PM PST 24
Finished Feb 18 02:27:08 PM PST 24
Peak memory 203212 kb
Host smart-afe0997c-e462-4f87-824a-2d4d83745396
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702367148 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.702367148
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.87541431
Short name T167
Test name
Test status
Simulation time 111561602 ps
CPU time 0.68 seconds
Started Feb 18 02:26:59 PM PST 24
Finished Feb 18 02:27:02 PM PST 24
Peak memory 203604 kb
Host smart-60164a76-5e3c-4324-af4f-e9c66c15679f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87541431 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.87541431
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.1363765590
Short name T83
Test name
Test status
Simulation time 85627189 ps
CPU time 0.71 seconds
Started Feb 18 02:27:03 PM PST 24
Finished Feb 18 02:27:08 PM PST 24
Peak memory 203300 kb
Host smart-1b825707-9aa6-4245-885c-76892b58b1f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363765590 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.1363765590
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.1237640419
Short name T200
Test name
Test status
Simulation time 41485211 ps
CPU time 0.68 seconds
Started Feb 18 02:26:59 PM PST 24
Finished Feb 18 02:27:02 PM PST 24
Peak memory 203596 kb
Host smart-22432f04-467a-4de0-980d-260aa9c0a987
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237640419 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.1237640419
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.2811950935
Short name T216
Test name
Test status
Simulation time 33921862 ps
CPU time 0.67 seconds
Started Feb 18 02:26:58 PM PST 24
Finished Feb 18 02:27:01 PM PST 24
Peak memory 203580 kb
Host smart-58ce754b-0ba5-47ec-9511-6dac2d25e198
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811950935 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.2811950935
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.2652250116
Short name T142
Test name
Test status
Simulation time 28237575 ps
CPU time 0.71 seconds
Started Feb 18 02:27:22 PM PST 24
Finished Feb 18 02:27:28 PM PST 24
Peak memory 203592 kb
Host smart-d6f6bb7b-bac8-4161-aa8d-4969e4b7b2b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652250116 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.2652250116
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.964373752
Short name T91
Test name
Test status
Simulation time 53107665 ps
CPU time 0.66 seconds
Started Feb 18 02:27:12 PM PST 24
Finished Feb 18 02:27:15 PM PST 24
Peak memory 203588 kb
Host smart-9b444ac7-fe54-4190-859c-2a65d287abf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964373752 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.964373752
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.2264017199
Short name T56
Test name
Test status
Simulation time 18363934 ps
CPU time 0.66 seconds
Started Feb 18 02:25:34 PM PST 24
Finished Feb 18 02:25:38 PM PST 24
Peak memory 203592 kb
Host smart-2a7bac9d-0f75-46ec-80f7-b32d0f10b26f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264017199 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.2264017199
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.1078544792
Short name T202
Test name
Test status
Simulation time 20800174546 ps
CPU time 74.54 seconds
Started Feb 18 02:25:34 PM PST 24
Finished Feb 18 02:26:51 PM PST 24
Peak memory 204040 kb
Host smart-4fd1c835-602d-428f-b2a3-15d08a340c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078544792 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.1078544792
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.1312040417
Short name T178
Test name
Test status
Simulation time 1887149032 ps
CPU time 4.11 seconds
Started Feb 18 02:25:34 PM PST 24
Finished Feb 18 02:25:41 PM PST 24
Peak memory 203960 kb
Host smart-a1c0641c-8553-4b1c-8d34-ca983c67d7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312040417 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.1312040417
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.1774185011
Short name T204
Test name
Test status
Simulation time 3273944844 ps
CPU time 5.13 seconds
Started Feb 18 02:25:33 PM PST 24
Finished Feb 18 02:25:42 PM PST 24
Peak memory 203964 kb
Host smart-97b2f3ee-bd70-45b3-ab25-9ecf5a27bdcd
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1774185011 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t
l_access.1774185011
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.1301096087
Short name T223
Test name
Test status
Simulation time 4693106792 ps
CPU time 10.02 seconds
Started Feb 18 02:25:30 PM PST 24
Finished Feb 18 02:25:44 PM PST 24
Peak memory 204048 kb
Host smart-76262238-709a-49f2-a9be-372390b90f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301096087 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.1301096087
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.4294423839
Short name T51
Test name
Test status
Simulation time 49956092 ps
CPU time 0.68 seconds
Started Feb 18 02:25:35 PM PST 24
Finished Feb 18 02:25:39 PM PST 24
Peak memory 203612 kb
Host smart-32f5699c-a4b2-45a8-b8d6-24073c22f92e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294423839 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.4294423839
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.330216216
Short name T14
Test name
Test status
Simulation time 5581255174 ps
CPU time 9.43 seconds
Started Feb 18 02:25:35 PM PST 24
Finished Feb 18 02:25:47 PM PST 24
Peak memory 203964 kb
Host smart-c9afc031-3454-4fde-b632-c701883b4a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330216216 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.330216216
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.390280155
Short name T49
Test name
Test status
Simulation time 8682540936 ps
CPU time 13.64 seconds
Started Feb 18 02:25:35 PM PST 24
Finished Feb 18 02:25:51 PM PST 24
Peak memory 204036 kb
Host smart-80f58e19-8884-4856-8707-eca2f8f3acec
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=390280155 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_tl
_access.390280155
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.840110588
Short name T11
Test name
Test status
Simulation time 2756191846 ps
CPU time 7.06 seconds
Started Feb 18 02:25:38 PM PST 24
Finished Feb 18 02:25:48 PM PST 24
Peak memory 203360 kb
Host smart-6c920a7e-4dfa-4868-9514-8441c9b82ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840110588 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.840110588
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.547101397
Short name T36
Test name
Test status
Simulation time 31196061 ps
CPU time 0.66 seconds
Started Feb 18 02:25:36 PM PST 24
Finished Feb 18 02:25:39 PM PST 24
Peak memory 203600 kb
Host smart-9013321e-d9bc-4fc4-be2f-ce638848e959
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547101397 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.547101397
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.3729560572
Short name T215
Test name
Test status
Simulation time 2442058915 ps
CPU time 9.63 seconds
Started Feb 18 02:25:32 PM PST 24
Finished Feb 18 02:25:46 PM PST 24
Peak memory 203968 kb
Host smart-dde51d4c-c142-4a01-a135-0956e0af1719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729560572 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.3729560572
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.1594712161
Short name T195
Test name
Test status
Simulation time 16080864940 ps
CPU time 45 seconds
Started Feb 18 02:25:35 PM PST 24
Finished Feb 18 02:26:23 PM PST 24
Peak memory 204004 kb
Host smart-f65605f6-433b-498d-93d7-156af5a63f9d
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1594712161 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.1594712161
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.3721924205
Short name T214
Test name
Test status
Simulation time 1151921358 ps
CPU time 5.43 seconds
Started Feb 18 02:25:38 PM PST 24
Finished Feb 18 02:25:46 PM PST 24
Peak memory 203396 kb
Host smart-68c58a75-ddcf-4f0a-a952-3cb8309be08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721924205 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.3721924205
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.2584952634
Short name T218
Test name
Test status
Simulation time 21569448096 ps
CPU time 48.08 seconds
Started Feb 18 02:25:40 PM PST 24
Finished Feb 18 02:26:30 PM PST 24
Peak memory 204028 kb
Host smart-7c433cec-73f1-44c0-81cd-499cfe825723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584952634 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.2584952634
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.1782404672
Short name T192
Test name
Test status
Simulation time 2833794188 ps
CPU time 4.91 seconds
Started Feb 18 02:25:37 PM PST 24
Finished Feb 18 02:25:45 PM PST 24
Peak memory 203944 kb
Host smart-62ce1d7f-feb9-4178-bf8e-edf30c4870e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782404672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.1782404672
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.725057082
Short name T71
Test name
Test status
Simulation time 698285007 ps
CPU time 3.35 seconds
Started Feb 18 02:25:37 PM PST 24
Finished Feb 18 02:25:43 PM PST 24
Peak memory 203844 kb
Host smart-79c9fec9-55fd-4f91-9846-6cc48048a6d3
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=725057082 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_tl
_access.725057082
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.3881683010
Short name T232
Test name
Test status
Simulation time 1666098273 ps
CPU time 4.13 seconds
Started Feb 18 02:25:36 PM PST 24
Finished Feb 18 02:25:42 PM PST 24
Peak memory 203936 kb
Host smart-72b9b954-fd44-4fbb-8ce8-9c867e867f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881683010 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.3881683010
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.2944960468
Short name T182
Test name
Test status
Simulation time 52203431 ps
CPU time 0.62 seconds
Started Feb 18 02:25:37 PM PST 24
Finished Feb 18 02:25:41 PM PST 24
Peak memory 203540 kb
Host smart-478899bd-c98c-44ec-b9bb-3419335c933d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944960468 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.2944960468
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.1896347167
Short name T174
Test name
Test status
Simulation time 11632601770 ps
CPU time 33.34 seconds
Started Feb 18 02:25:35 PM PST 24
Finished Feb 18 02:26:11 PM PST 24
Peak memory 204044 kb
Host smart-900e286f-3b30-4cf9-ad3e-9e3a7ca0c5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896347167 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.1896347167
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.3629520933
Short name T70
Test name
Test status
Simulation time 393813826 ps
CPU time 1.2 seconds
Started Feb 18 02:25:40 PM PST 24
Finished Feb 18 02:25:44 PM PST 24
Peak memory 203900 kb
Host smart-870c2053-adb5-498f-9ad0-78da5605edfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629520933 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.3629520933
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.521100987
Short name T203
Test name
Test status
Simulation time 2250335231 ps
CPU time 4.03 seconds
Started Feb 18 02:25:41 PM PST 24
Finished Feb 18 02:25:47 PM PST 24
Peak memory 203784 kb
Host smart-9a234852-684f-45e9-86c1-c5ae4cf5ac49
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=521100987 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_tl
_access.521100987
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.754362912
Short name T224
Test name
Test status
Simulation time 430075266 ps
CPU time 2.69 seconds
Started Feb 18 02:25:40 PM PST 24
Finished Feb 18 02:25:45 PM PST 24
Peak memory 203880 kb
Host smart-5cacf929-0827-43c8-a8ab-45e57d5e8d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754362912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.754362912
Directory /workspace/9.rv_dm_sba_tl_access/latest
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