Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
87.83 92.87 79.50 89.36 76.92 83.07 97.75 95.34


Total test records in report: 377
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html
T275 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.949121403 Mar 05 01:18:57 PM PST 24 Mar 05 01:19:00 PM PST 24 544998937 ps
T276 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.3686331139 Mar 05 01:19:04 PM PST 24 Mar 05 01:19:07 PM PST 24 297448299 ps
T277 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.3937000072 Mar 05 01:18:57 PM PST 24 Mar 05 01:19:22 PM PST 24 40904764458 ps
T278 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3696876712 Mar 05 01:18:43 PM PST 24 Mar 05 01:18:49 PM PST 24 3905010706 ps
T279 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.1229558958 Mar 05 01:19:06 PM PST 24 Mar 05 01:19:07 PM PST 24 25317038 ps
T280 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.89802082 Mar 05 01:18:43 PM PST 24 Mar 05 01:18:46 PM PST 24 1085284614 ps
T281 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.2088302642 Mar 05 01:18:45 PM PST 24 Mar 05 01:18:45 PM PST 24 24300109 ps
T282 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1010191761 Mar 05 01:18:58 PM PST 24 Mar 05 01:19:00 PM PST 24 105777324 ps
T283 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1306320476 Mar 05 01:18:37 PM PST 24 Mar 05 01:19:16 PM PST 24 12772483592 ps
T284 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.4105696427 Mar 05 01:18:45 PM PST 24 Mar 05 01:19:13 PM PST 24 28856302790 ps
T285 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.283335690 Mar 05 01:18:48 PM PST 24 Mar 05 01:18:51 PM PST 24 59235881 ps
T286 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2146899518 Mar 05 01:18:49 PM PST 24 Mar 05 01:18:50 PM PST 24 753841890 ps
T287 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.2357740705 Mar 05 01:18:53 PM PST 24 Mar 05 01:18:54 PM PST 24 55570843 ps
T288 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.561990148 Mar 05 01:18:56 PM PST 24 Mar 05 01:19:00 PM PST 24 194677761 ps
T289 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3848974737 Mar 05 01:18:53 PM PST 24 Mar 05 01:18:54 PM PST 24 110171036 ps
T290 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.867697840 Mar 05 01:19:01 PM PST 24 Mar 05 01:19:06 PM PST 24 81402459 ps
T291 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.3225824542 Mar 05 01:19:04 PM PST 24 Mar 05 01:19:07 PM PST 24 854312819 ps
T292 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.85439937 Mar 05 01:18:32 PM PST 24 Mar 05 01:18:33 PM PST 24 25781269 ps
T293 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.2060092463 Mar 05 01:18:32 PM PST 24 Mar 05 01:19:48 PM PST 24 13736564663 ps
T294 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2338481555 Mar 05 01:19:03 PM PST 24 Mar 05 01:19:05 PM PST 24 82670113 ps
T295 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.215505357 Mar 05 01:18:42 PM PST 24 Mar 05 01:18:44 PM PST 24 335643506 ps
T296 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.2661411001 Mar 05 01:18:47 PM PST 24 Mar 05 01:18:48 PM PST 24 15390937 ps
T297 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.2884841083 Mar 05 01:18:41 PM PST 24 Mar 05 01:18:44 PM PST 24 995493691 ps
T298 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.3265315838 Mar 05 01:18:49 PM PST 24 Mar 05 01:18:50 PM PST 24 103682117 ps
T299 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.4055697582 Mar 05 01:18:51 PM PST 24 Mar 05 01:18:52 PM PST 24 52591392 ps
T300 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.206791076 Mar 05 01:18:58 PM PST 24 Mar 05 01:19:27 PM PST 24 28967660755 ps
T97 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.1594234803 Mar 05 01:18:58 PM PST 24 Mar 05 01:19:01 PM PST 24 522552827 ps
T301 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.795911471 Mar 05 01:18:46 PM PST 24 Mar 05 01:18:50 PM PST 24 2004597368 ps
T302 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1419895965 Mar 05 01:18:36 PM PST 24 Mar 05 01:18:40 PM PST 24 852189457 ps
T103 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.989489325 Mar 05 01:18:59 PM PST 24 Mar 05 01:19:07 PM PST 24 558696363 ps
T111 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.3437531311 Mar 05 01:18:51 PM PST 24 Mar 05 01:19:57 PM PST 24 4847143003 ps
T303 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1462789231 Mar 05 01:18:47 PM PST 24 Mar 05 01:18:53 PM PST 24 4099843569 ps
T304 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.3886139744 Mar 05 01:18:51 PM PST 24 Mar 05 01:18:55 PM PST 24 1897959382 ps
T305 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2133889872 Mar 05 01:19:00 PM PST 24 Mar 05 01:19:08 PM PST 24 7961531417 ps
T117 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3934537467 Mar 05 01:18:46 PM PST 24 Mar 05 01:18:53 PM PST 24 144928032 ps
T113 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.391530676 Mar 05 01:18:45 PM PST 24 Mar 05 01:19:39 PM PST 24 2792007412 ps
T306 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.4254489167 Mar 05 01:19:00 PM PST 24 Mar 05 01:19:08 PM PST 24 4107437970 ps
T307 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.557102099 Mar 05 01:18:56 PM PST 24 Mar 05 01:18:59 PM PST 24 109202791 ps
T112 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.4036965839 Mar 05 01:19:04 PM PST 24 Mar 05 01:19:07 PM PST 24 671437241 ps
T308 /workspace/coverage/cover_reg_top/14.rv_dm_tap_fsm_rand_reset.2909670132 Mar 05 01:19:02 PM PST 24 Mar 05 01:19:22 PM PST 24 11331573590 ps
T309 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.1824838267 Mar 05 01:18:52 PM PST 24 Mar 05 01:18:53 PM PST 24 44267441 ps
T128 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3353670154 Mar 05 01:18:37 PM PST 24 Mar 05 01:18:56 PM PST 24 2469480609 ps
T310 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2252537051 Mar 05 01:18:50 PM PST 24 Mar 05 01:18:55 PM PST 24 343742560 ps
T311 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.727565480 Mar 05 01:18:29 PM PST 24 Mar 05 01:18:30 PM PST 24 87385852 ps
T312 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2502175719 Mar 05 01:19:07 PM PST 24 Mar 05 01:19:08 PM PST 24 84871948 ps
T123 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2150178540 Mar 05 01:18:52 PM PST 24 Mar 05 01:18:56 PM PST 24 2494917985 ps
T313 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.3706903917 Mar 05 01:19:06 PM PST 24 Mar 05 01:19:09 PM PST 24 224179549 ps
T314 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.569491481 Mar 05 01:18:58 PM PST 24 Mar 05 01:18:59 PM PST 24 128212746 ps
T315 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.2281107994 Mar 05 01:18:52 PM PST 24 Mar 05 01:18:54 PM PST 24 76616259 ps
T316 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3431902259 Mar 05 01:18:58 PM PST 24 Mar 05 01:19:00 PM PST 24 136132192 ps
T317 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1605504742 Mar 05 01:18:58 PM PST 24 Mar 05 01:19:06 PM PST 24 1616487734 ps
T318 /workspace/coverage/cover_reg_top/17.rv_dm_tap_fsm_rand_reset.1070737461 Mar 05 01:19:02 PM PST 24 Mar 05 01:19:23 PM PST 24 5823556391 ps
T319 /workspace/coverage/cover_reg_top/23.rv_dm_tap_fsm_rand_reset.2679856154 Mar 05 01:19:09 PM PST 24 Mar 05 01:19:25 PM PST 24 15745293120 ps
T320 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.423412251 Mar 05 01:18:44 PM PST 24 Mar 05 01:19:20 PM PST 24 3505385802 ps
T321 /workspace/coverage/cover_reg_top/24.rv_dm_tap_fsm_rand_reset.3993015142 Mar 05 01:19:05 PM PST 24 Mar 05 01:19:22 PM PST 24 4794913673 ps
T322 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.303339026 Mar 05 01:18:51 PM PST 24 Mar 05 01:18:52 PM PST 24 28364703 ps
T323 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1443594744 Mar 05 01:18:32 PM PST 24 Mar 05 01:18:57 PM PST 24 19221082107 ps
T324 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2211139311 Mar 05 01:18:32 PM PST 24 Mar 05 01:18:51 PM PST 24 4242362061 ps
T325 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.2260612885 Mar 05 01:19:01 PM PST 24 Mar 05 01:19:05 PM PST 24 164135124 ps
T326 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.2315902260 Mar 05 01:19:04 PM PST 24 Mar 05 01:19:07 PM PST 24 326129722 ps
T327 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2991584898 Mar 05 01:19:02 PM PST 24 Mar 05 01:19:10 PM PST 24 4319978928 ps
T328 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.604062659 Mar 05 01:18:58 PM PST 24 Mar 05 01:18:59 PM PST 24 30161187 ps
T329 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.1396486351 Mar 05 01:19:04 PM PST 24 Mar 05 01:19:14 PM PST 24 553530418 ps
T330 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.1272214621 Mar 05 01:19:04 PM PST 24 Mar 05 01:19:09 PM PST 24 1169026304 ps
T331 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1119598228 Mar 05 01:18:59 PM PST 24 Mar 05 01:19:02 PM PST 24 290196330 ps
T332 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3429166242 Mar 05 01:18:44 PM PST 24 Mar 05 01:18:45 PM PST 24 15443605 ps
T59 /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.2523153864 Mar 05 01:18:51 PM PST 24 Mar 05 01:19:07 PM PST 24 27975347162 ps
T333 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1265262245 Mar 05 01:19:11 PM PST 24 Mar 05 01:19:14 PM PST 24 446928182 ps
T334 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3740308937 Mar 05 01:18:42 PM PST 24 Mar 05 01:19:25 PM PST 24 9313149696 ps
T133 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.3557546964 Mar 05 01:19:05 PM PST 24 Mar 05 01:19:23 PM PST 24 3465824788 ps
T335 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.14596116 Mar 05 01:18:51 PM PST 24 Mar 05 01:18:55 PM PST 24 5154515246 ps
T134 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.1598704780 Mar 05 01:19:08 PM PST 24 Mar 05 01:19:19 PM PST 24 1265808061 ps
T336 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.2713447820 Mar 05 01:18:50 PM PST 24 Mar 05 01:18:51 PM PST 24 25275083 ps
T337 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3835805764 Mar 05 01:19:04 PM PST 24 Mar 05 01:19:07 PM PST 24 1282945938 ps
T338 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.1193278166 Mar 05 01:19:06 PM PST 24 Mar 05 01:19:11 PM PST 24 160375000 ps
T339 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.25503109 Mar 05 01:18:51 PM PST 24 Mar 05 01:18:54 PM PST 24 863946198 ps
T340 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.952155580 Mar 05 01:18:46 PM PST 24 Mar 05 01:19:14 PM PST 24 1408203561 ps
T104 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.566273897 Mar 05 01:19:00 PM PST 24 Mar 05 01:19:04 PM PST 24 616329982 ps
T341 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.214260447 Mar 05 01:18:28 PM PST 24 Mar 05 01:18:29 PM PST 24 60727937 ps
T342 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.2504261538 Mar 05 01:18:54 PM PST 24 Mar 05 01:18:55 PM PST 24 28291834 ps
T343 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.3183096216 Mar 05 01:19:11 PM PST 24 Mar 05 01:19:12 PM PST 24 47748353 ps
T344 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2361215208 Mar 05 01:18:54 PM PST 24 Mar 05 01:18:55 PM PST 24 189895598 ps
T345 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.2939495613 Mar 05 01:18:57 PM PST 24 Mar 05 01:18:58 PM PST 24 225349227 ps
T346 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.2195007352 Mar 05 01:19:08 PM PST 24 Mar 05 01:19:09 PM PST 24 75989824 ps
T347 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.646919768 Mar 05 01:18:50 PM PST 24 Mar 05 01:18:52 PM PST 24 200391249 ps
T348 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.965159079 Mar 05 01:19:10 PM PST 24 Mar 05 01:19:15 PM PST 24 1012511527 ps
T124 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.2470863585 Mar 05 01:18:42 PM PST 24 Mar 05 01:18:45 PM PST 24 52262286 ps
T349 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3909729154 Mar 05 01:18:38 PM PST 24 Mar 05 01:18:40 PM PST 24 128931314 ps
T350 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2450407278 Mar 05 01:18:31 PM PST 24 Mar 05 01:18:33 PM PST 24 609780354 ps
T351 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2007547394 Mar 05 01:18:51 PM PST 24 Mar 05 01:18:53 PM PST 24 386808801 ps
T105 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.700019509 Mar 05 01:18:45 PM PST 24 Mar 05 01:18:49 PM PST 24 214102343 ps
T352 /workspace/coverage/cover_reg_top/28.rv_dm_tap_fsm_rand_reset.533723945 Mar 05 01:19:14 PM PST 24 Mar 05 01:19:27 PM PST 24 6301901593 ps
T98 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.4231100186 Mar 05 01:18:48 PM PST 24 Mar 05 01:18:49 PM PST 24 408850459 ps
T353 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.4054106861 Mar 05 01:19:04 PM PST 24 Mar 05 01:19:09 PM PST 24 324743420 ps
T106 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.3104419947 Mar 05 01:18:52 PM PST 24 Mar 05 01:19:00 PM PST 24 1976817043 ps
T354 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.1067244381 Mar 05 01:18:33 PM PST 24 Mar 05 01:18:34 PM PST 24 310560124 ps
T355 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2722615559 Mar 05 01:18:32 PM PST 24 Mar 05 01:18:33 PM PST 24 134642782 ps
T356 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.1970466903 Mar 05 01:18:57 PM PST 24 Mar 05 01:19:02 PM PST 24 78623592 ps
T129 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2595030675 Mar 05 01:18:57 PM PST 24 Mar 05 01:19:06 PM PST 24 393486814 ps
T357 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.967916099 Mar 05 01:18:42 PM PST 24 Mar 05 01:18:44 PM PST 24 174708571 ps
T358 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2250266787 Mar 05 01:18:41 PM PST 24 Mar 05 01:18:44 PM PST 24 875484623 ps
T99 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2663701597 Mar 05 01:18:47 PM PST 24 Mar 05 01:18:48 PM PST 24 435969929 ps
T359 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3532986082 Mar 05 01:18:54 PM PST 24 Mar 05 01:19:42 PM PST 24 13111116145 ps
T360 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.1815315471 Mar 05 01:18:55 PM PST 24 Mar 05 01:18:56 PM PST 24 39766941 ps
T361 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1372319035 Mar 05 01:18:49 PM PST 24 Mar 05 01:18:50 PM PST 24 30890319 ps
T362 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3298942953 Mar 05 01:18:59 PM PST 24 Mar 05 01:19:06 PM PST 24 277273367 ps
T363 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.204981360 Mar 05 01:18:57 PM PST 24 Mar 05 01:18:58 PM PST 24 97495797 ps
T364 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.581565041 Mar 05 01:19:04 PM PST 24 Mar 05 01:19:10 PM PST 24 1383683220 ps
T130 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2518748846 Mar 05 01:18:59 PM PST 24 Mar 05 01:19:09 PM PST 24 4795016448 ps
T365 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2214397820 Mar 05 01:19:05 PM PST 24 Mar 05 01:19:11 PM PST 24 74331594 ps
T366 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.3239910909 Mar 05 01:19:04 PM PST 24 Mar 05 01:19:11 PM PST 24 228382433 ps
T367 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2830423653 Mar 05 01:19:05 PM PST 24 Mar 05 01:19:07 PM PST 24 282826826 ps
T131 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3893871118 Mar 05 01:19:00 PM PST 24 Mar 05 01:19:09 PM PST 24 412375958 ps
T132 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.725751286 Mar 05 01:19:02 PM PST 24 Mar 05 01:19:24 PM PST 24 1342968252 ps
T125 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.1324929718 Mar 05 01:18:51 PM PST 24 Mar 05 01:19:09 PM PST 24 886314901 ps
T368 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2840698080 Mar 05 01:19:02 PM PST 24 Mar 05 01:19:06 PM PST 24 121679019 ps
T369 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.1889417663 Mar 05 01:18:52 PM PST 24 Mar 05 01:18:58 PM PST 24 596216684 ps
T370 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.3565878741 Mar 05 01:18:57 PM PST 24 Mar 05 01:18:58 PM PST 24 132692455 ps
T371 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.2167044769 Mar 05 01:18:54 PM PST 24 Mar 05 01:18:56 PM PST 24 329053427 ps
T372 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.2118821651 Mar 05 01:18:58 PM PST 24 Mar 05 01:18:59 PM PST 24 50037430 ps
T135 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2081034032 Mar 05 01:18:34 PM PST 24 Mar 05 01:18:44 PM PST 24 571179599 ps
T373 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.4015010964 Mar 05 01:19:06 PM PST 24 Mar 05 01:19:22 PM PST 24 643754555 ps
T374 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2476470984 Mar 05 01:18:52 PM PST 24 Mar 05 01:19:23 PM PST 24 5038046223 ps
T375 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2129416596 Mar 05 01:18:57 PM PST 24 Mar 05 01:19:07 PM PST 24 8092607044 ps
T127 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.904719286 Mar 05 01:18:56 PM PST 24 Mar 05 01:19:07 PM PST 24 3200984840 ps
T376 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.2811057029 Mar 05 01:18:59 PM PST 24 Mar 05 01:19:02 PM PST 24 95213889 ps
T377 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.2299172174 Mar 05 01:18:52 PM PST 24 Mar 05 01:18:54 PM PST 24 386547552 ps

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.550394560
Short name T15
Test name
Test status
Simulation time 11104611314 ps
CPU time 44.78 seconds
Started Mar 05 12:44:25 PM PST 24
Finished Mar 05 12:45:10 PM PST 24
Peak memory 204120 kb
Host smart-5a25da6d-17b5-4bce-8760-7e19ab0e3a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550394560 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.550394560
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/28.rv_dm_stress_all.1294474542
Short name T6
Test name
Test status
Simulation time 2551940267 ps
CPU time 5.25 seconds
Started Mar 05 12:44:29 PM PST 24
Finished Mar 05 12:44:34 PM PST 24
Peak memory 203992 kb
Host smart-d869d6f5-8227-4c23-9dc1-eda49e05ba7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294474542 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.1294474542
Directory /workspace/28.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.4148236110
Short name T41
Test name
Test status
Simulation time 7106810285 ps
CPU time 8.72 seconds
Started Mar 05 01:18:44 PM PST 24
Finished Mar 05 01:18:52 PM PST 24
Peak memory 216428 kb
Host smart-4c34a3a3-a641-4da8-b240-4c959562bcab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148236110 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.4148236110
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.2287508272
Short name T2
Test name
Test status
Simulation time 22678537 ps
CPU time 0.67 seconds
Started Mar 05 12:44:15 PM PST 24
Finished Mar 05 12:44:16 PM PST 24
Peak memory 203720 kb
Host smart-d73d6144-b8b9-4fbf-9be2-10183496775f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287508272 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.2287508272
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tap_fsm_rand_reset.521757328
Short name T155
Test name
Test status
Simulation time 20717506629 ps
CPU time 18.56 seconds
Started Mar 05 01:19:08 PM PST 24
Finished Mar 05 01:19:27 PM PST 24
Peak memory 219544 kb
Host smart-1cbdbcc1-d698-4f08-879c-9b85cacad043
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521757328 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.rv_dm_tap_fsm_rand_reset.521757328
Directory /workspace/15.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/40.rv_dm_stress_all.641226241
Short name T29
Test name
Test status
Simulation time 33029278065 ps
CPU time 12.43 seconds
Started Mar 05 12:44:46 PM PST 24
Finished Mar 05 12:44:58 PM PST 24
Peak memory 204208 kb
Host smart-03da3f73-1820-4883-b16d-7d6fbd282b3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641226241 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.641226241
Directory /workspace/40.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.1703536078
Short name T156
Test name
Test status
Simulation time 611879581 ps
CPU time 4.69 seconds
Started Mar 05 01:19:06 PM PST 24
Finished Mar 05 01:19:12 PM PST 24
Peak memory 212096 kb
Host smart-affa76b7-8f90-46e4-b626-2ce58055d035
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703536078 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.1703536078
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3294833724
Short name T79
Test name
Test status
Simulation time 948650090 ps
CPU time 20.05 seconds
Started Mar 05 01:18:47 PM PST 24
Finished Mar 05 01:19:08 PM PST 24
Peak memory 215084 kb
Host smart-4aaab3b8-35f1-4cfd-a46c-b13c98fb43a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294833724 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.3294833724
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.2593731486
Short name T172
Test name
Test status
Simulation time 6305486377 ps
CPU time 23.66 seconds
Started Mar 05 12:43:59 PM PST 24
Finished Mar 05 12:44:23 PM PST 24
Peak memory 204176 kb
Host smart-355d3c42-820d-4bc9-8205-a2633db758dd
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2593731486 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.2593731486
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.2035543380
Short name T55
Test name
Test status
Simulation time 8406028761 ps
CPU time 75.5 seconds
Started Mar 05 01:18:36 PM PST 24
Finished Mar 05 01:19:52 PM PST 24
Peak memory 203848 kb
Host smart-4e47a644-a198-437b-96bc-741435f9ecae
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035543380 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.2035543380
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.2856435332
Short name T84
Test name
Test status
Simulation time 43278950 ps
CPU time 0.67 seconds
Started Mar 05 12:44:04 PM PST 24
Finished Mar 05 12:44:05 PM PST 24
Peak memory 203828 kb
Host smart-daa30127-b1cb-490d-b0cf-946e6b6b2f4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856435332 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.2856435332
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.1176324467
Short name T25
Test name
Test status
Simulation time 22465471 ps
CPU time 0.77 seconds
Started Mar 05 12:44:10 PM PST 24
Finished Mar 05 12:44:11 PM PST 24
Peak memory 203820 kb
Host smart-a816fe94-244f-45ec-a5cb-9ab131a3a2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176324467 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.1176324467
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.2426181491
Short name T67
Test name
Test status
Simulation time 176574495 ps
CPU time 1.1 seconds
Started Mar 05 12:44:04 PM PST 24
Finished Mar 05 12:44:06 PM PST 24
Peak memory 219564 kb
Host smart-235a601a-4d46-442a-b701-29f378c480f5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426181491 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.2426181491
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3353670154
Short name T128
Test name
Test status
Simulation time 2469480609 ps
CPU time 18.83 seconds
Started Mar 05 01:18:37 PM PST 24
Finished Mar 05 01:18:56 PM PST 24
Peak memory 212132 kb
Host smart-0162e374-78dd-462b-a6c9-450b7d2a625f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353670154 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.3353670154
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.2951625773
Short name T9
Test name
Test status
Simulation time 598918251 ps
CPU time 0.84 seconds
Started Mar 05 12:44:06 PM PST 24
Finished Mar 05 12:44:10 PM PST 24
Peak memory 203616 kb
Host smart-d6f14d5f-c22a-4828-a67d-1300b23b0ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951625773 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.2951625773
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.1191580939
Short name T43
Test name
Test status
Simulation time 574628571 ps
CPU time 4.39 seconds
Started Mar 05 01:18:59 PM PST 24
Finished Mar 05 01:19:03 PM PST 24
Peak memory 203888 kb
Host smart-d114ee17-b967-4620-aa28-66419fa75179
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191580939 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same
_csr_outstanding.1191580939
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1193361330
Short name T75
Test name
Test status
Simulation time 86540637 ps
CPU time 0.7 seconds
Started Mar 05 01:18:45 PM PST 24
Finished Mar 05 01:18:46 PM PST 24
Peak memory 203548 kb
Host smart-c5f69c2d-ba1b-487e-b043-ac3270ba1cfc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193361330 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.1193361330
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.2523153864
Short name T59
Test name
Test status
Simulation time 27975347162 ps
CPU time 16.16 seconds
Started Mar 05 01:18:51 PM PST 24
Finished Mar 05 01:19:07 PM PST 24
Peak memory 219948 kb
Host smart-8ccb5f34-635c-4945-85b8-c4587c5497e4
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523153864 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.2523153864
Directory /workspace/8.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.3530725499
Short name T16
Test name
Test status
Simulation time 350528628 ps
CPU time 0.95 seconds
Started Mar 05 12:43:58 PM PST 24
Finished Mar 05 12:44:00 PM PST 24
Peak memory 203768 kb
Host smart-11ab7d5b-b06c-47c2-b3f8-761f55c3999e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530725499 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.3530725499
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.3755698526
Short name T122
Test name
Test status
Simulation time 71760700 ps
CPU time 4.27 seconds
Started Mar 05 01:18:57 PM PST 24
Finished Mar 05 01:19:02 PM PST 24
Peak memory 203856 kb
Host smart-51d7fcd2-4070-42cd-a04c-41374022b1b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755698526 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.3755698526
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.2260827531
Short name T39
Test name
Test status
Simulation time 4446466894 ps
CPU time 10.36 seconds
Started Mar 05 01:18:45 PM PST 24
Finished Mar 05 01:18:56 PM PST 24
Peak memory 213232 kb
Host smart-ea0fc9f6-d419-4ddf-9d82-c9abf682882a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260827531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.2260827531
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2518748846
Short name T130
Test name
Test status
Simulation time 4795016448 ps
CPU time 9.89 seconds
Started Mar 05 01:18:59 PM PST 24
Finished Mar 05 01:19:09 PM PST 24
Peak memory 213212 kb
Host smart-b9915c56-66bb-492a-be51-6e26b0e4f0de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518748846 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.2
518748846
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.725751286
Short name T132
Test name
Test status
Simulation time 1342968252 ps
CPU time 15.24 seconds
Started Mar 05 01:19:02 PM PST 24
Finished Mar 05 01:19:24 PM PST 24
Peak memory 212220 kb
Host smart-63466033-9f97-47d1-af41-7f82165d3f59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725751286 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.725751286
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.904719286
Short name T127
Test name
Test status
Simulation time 3200984840 ps
CPU time 10.12 seconds
Started Mar 05 01:18:56 PM PST 24
Finished Mar 05 01:19:07 PM PST 24
Peak memory 213068 kb
Host smart-70aa2515-9bf7-4e5f-9771-35c860238f32
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904719286 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.904719286
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2663701597
Short name T99
Test name
Test status
Simulation time 435969929 ps
CPU time 1.09 seconds
Started Mar 05 01:18:47 PM PST 24
Finished Mar 05 01:18:48 PM PST 24
Peak memory 203736 kb
Host smart-12f11ce7-89c4-4904-931e-3c94cec136a2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663701597 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.2663701597
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.1609154529
Short name T151
Test name
Test status
Simulation time 20181188 ps
CPU time 0.65 seconds
Started Mar 05 12:44:26 PM PST 24
Finished Mar 05 12:44:27 PM PST 24
Peak memory 203828 kb
Host smart-f0f94296-bd94-4b23-8d03-f19dd6422e48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609154529 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.1609154529
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.4078414281
Short name T23
Test name
Test status
Simulation time 314218971 ps
CPU time 0.8 seconds
Started Mar 05 12:44:07 PM PST 24
Finished Mar 05 12:44:08 PM PST 24
Peak memory 203592 kb
Host smart-8006bf97-e19e-4814-a3e6-5827bcde429c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078414281 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.4078414281
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3589531746
Short name T80
Test name
Test status
Simulation time 82165967 ps
CPU time 4.4 seconds
Started Mar 05 01:19:06 PM PST 24
Finished Mar 05 01:19:11 PM PST 24
Peak memory 212076 kb
Host smart-f88cb8f1-02c6-492d-8a9b-9c6a3835eb9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589531746 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.3589531746
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.4166989491
Short name T65
Test name
Test status
Simulation time 1100412344 ps
CPU time 5.17 seconds
Started Mar 05 12:44:19 PM PST 24
Finished Mar 05 12:44:24 PM PST 24
Peak memory 204088 kb
Host smart-093d150e-03fa-41cb-b533-dd72ff61525f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166989491 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.4166989491
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.2060092463
Short name T293
Test name
Test status
Simulation time 13736564663 ps
CPU time 75.19 seconds
Started Mar 05 01:18:32 PM PST 24
Finished Mar 05 01:19:48 PM PST 24
Peak memory 203892 kb
Host smart-b487f507-f826-421e-a656-b0d4ad0361c5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060092463 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.2060092463
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.423412251
Short name T320
Test name
Test status
Simulation time 3505385802 ps
CPU time 35.36 seconds
Started Mar 05 01:18:44 PM PST 24
Finished Mar 05 01:19:20 PM PST 24
Peak memory 203788 kb
Host smart-9bf23f24-4754-4e21-a688-abe767a362ef
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423412251 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.423412251
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.967916099
Short name T357
Test name
Test status
Simulation time 174708571 ps
CPU time 2.38 seconds
Started Mar 05 01:18:42 PM PST 24
Finished Mar 05 01:18:44 PM PST 24
Peak memory 203724 kb
Host smart-c81dbdb6-1325-494b-af63-ad507f21d625
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967916099 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.967916099
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3696876712
Short name T278
Test name
Test status
Simulation time 3905010706 ps
CPU time 5.56 seconds
Started Mar 05 01:18:43 PM PST 24
Finished Mar 05 01:18:49 PM PST 24
Peak memory 220324 kb
Host smart-b04de96b-d883-44c3-a8de-786800b2acac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696876712 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.3696876712
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2281484460
Short name T108
Test name
Test status
Simulation time 327096822 ps
CPU time 1.51 seconds
Started Mar 05 01:18:39 PM PST 24
Finished Mar 05 01:18:40 PM PST 24
Peak memory 203844 kb
Host smart-998f89cd-8e3b-4a0c-880a-9d301d25c572
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281484460 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.2281484460
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1306320476
Short name T283
Test name
Test status
Simulation time 12772483592 ps
CPU time 38.63 seconds
Started Mar 05 01:18:37 PM PST 24
Finished Mar 05 01:19:16 PM PST 24
Peak memory 203560 kb
Host smart-f913cf3a-b8d1-48cc-86ca-6fde862bf919
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306320476 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.1306320476
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1443594744
Short name T323
Test name
Test status
Simulation time 19221082107 ps
CPU time 24.54 seconds
Started Mar 05 01:18:32 PM PST 24
Finished Mar 05 01:18:57 PM PST 24
Peak memory 203580 kb
Host smart-c7156ff8-969b-4c7a-ad46-f499dc3a540d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443594744 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_bit_bash.1443594744
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2450407278
Short name T350
Test name
Test status
Simulation time 609780354 ps
CPU time 1.41 seconds
Started Mar 05 01:18:31 PM PST 24
Finished Mar 05 01:18:33 PM PST 24
Peak memory 203764 kb
Host smart-0e10aad4-e7a6-41b9-84de-4fa54d9509cd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450407278 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.2450407278
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.1067244381
Short name T354
Test name
Test status
Simulation time 310560124 ps
CPU time 1.32 seconds
Started Mar 05 01:18:33 PM PST 24
Finished Mar 05 01:18:34 PM PST 24
Peak memory 203676 kb
Host smart-34358220-223a-4a34-b3f8-d981956f106c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067244381 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.1
067244381
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2722615559
Short name T355
Test name
Test status
Simulation time 134642782 ps
CPU time 0.75 seconds
Started Mar 05 01:18:32 PM PST 24
Finished Mar 05 01:18:33 PM PST 24
Peak memory 203528 kb
Host smart-a331f09d-82b9-4081-8862-55400e9dd643
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722615559 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.2722615559
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1419895965
Short name T302
Test name
Test status
Simulation time 852189457 ps
CPU time 3.77 seconds
Started Mar 05 01:18:36 PM PST 24
Finished Mar 05 01:18:40 PM PST 24
Peak memory 203700 kb
Host smart-6fdef0c1-9bd3-4460-b578-1b72d0d7e07f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419895965 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.1419895965
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.214260447
Short name T341
Test name
Test status
Simulation time 60727937 ps
CPU time 0.76 seconds
Started Mar 05 01:18:28 PM PST 24
Finished Mar 05 01:18:29 PM PST 24
Peak memory 203436 kb
Host smart-edeeb9bb-b85c-45d0-ae71-fd0cae792234
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214260447 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr
_hw_reset.214260447
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.2915175397
Short name T269
Test name
Test status
Simulation time 28170251 ps
CPU time 0.69 seconds
Started Mar 05 01:18:27 PM PST 24
Finished Mar 05 01:18:28 PM PST 24
Peak memory 203392 kb
Host smart-f3f54112-1b25-4790-b4d7-760a3d742091
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915175397 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.2
915175397
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.85439937
Short name T292
Test name
Test status
Simulation time 25781269 ps
CPU time 0.64 seconds
Started Mar 05 01:18:32 PM PST 24
Finished Mar 05 01:18:33 PM PST 24
Peak memory 203404 kb
Host smart-afa696cd-c8fb-4857-adac-63629f0d38a6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85439937 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_parti
al_access.85439937
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.2661411001
Short name T296
Test name
Test status
Simulation time 15390937 ps
CPU time 0.64 seconds
Started Mar 05 01:18:47 PM PST 24
Finished Mar 05 01:18:48 PM PST 24
Peak memory 203524 kb
Host smart-cb29f459-acac-49bf-a0af-60d3834358ed
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661411001 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.2661411001
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.4100084657
Short name T115
Test name
Test status
Simulation time 532582788 ps
CPU time 6.55 seconds
Started Mar 05 01:18:37 PM PST 24
Finished Mar 05 01:18:44 PM PST 24
Peak memory 203816 kb
Host smart-43a287e2-6fc3-447d-a662-ef0a67eb7eaa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100084657 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.4100084657
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.2470863585
Short name T124
Test name
Test status
Simulation time 52262286 ps
CPU time 3.28 seconds
Started Mar 05 01:18:42 PM PST 24
Finished Mar 05 01:18:45 PM PST 24
Peak memory 212140 kb
Host smart-bfedee9e-7899-4a9a-8bc9-4321ea8f6219
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470863585 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.2470863585
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.391530676
Short name T113
Test name
Test status
Simulation time 2792007412 ps
CPU time 54.5 seconds
Started Mar 05 01:18:45 PM PST 24
Finished Mar 05 01:19:39 PM PST 24
Peak memory 203784 kb
Host smart-e39bcc58-ca2f-42d7-a589-8edd22e6d45f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391530676 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.391530676
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.4083586009
Short name T52
Test name
Test status
Simulation time 39344143 ps
CPU time 1.48 seconds
Started Mar 05 01:18:57 PM PST 24
Finished Mar 05 01:18:58 PM PST 24
Peak memory 203828 kb
Host smart-d1a6bda4-da88-401b-a4e9-ff264b480c83
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083586009 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.4083586009
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2988935195
Short name T89
Test name
Test status
Simulation time 349846043 ps
CPU time 1.95 seconds
Started Mar 05 01:18:31 PM PST 24
Finished Mar 05 01:18:33 PM PST 24
Peak memory 203536 kb
Host smart-f68931e4-3b73-4608-bb72-99554511f06d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988935195 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.2988935195
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2211139311
Short name T324
Test name
Test status
Simulation time 4242362061 ps
CPU time 19.33 seconds
Started Mar 05 01:18:32 PM PST 24
Finished Mar 05 01:18:51 PM PST 24
Peak memory 203796 kb
Host smart-d6a609fd-2e58-4e35-b1f4-8f9cbd6172fe
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211139311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.2211139311
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3740308937
Short name T334
Test name
Test status
Simulation time 9313149696 ps
CPU time 42.48 seconds
Started Mar 05 01:18:42 PM PST 24
Finished Mar 05 01:19:25 PM PST 24
Peak memory 203708 kb
Host smart-22dc8949-a5da-489c-b22b-c09902ddc3c6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740308937 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_bit_bash.3740308937
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1936764560
Short name T265
Test name
Test status
Simulation time 316476499 ps
CPU time 1.12 seconds
Started Mar 05 01:18:45 PM PST 24
Finished Mar 05 01:18:46 PM PST 24
Peak memory 203672 kb
Host smart-54a037a8-dcdd-462a-ad41-7de86655b124
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936764560 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.1
936764560
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.727565480
Short name T311
Test name
Test status
Simulation time 87385852 ps
CPU time 0.88 seconds
Started Mar 05 01:18:29 PM PST 24
Finished Mar 05 01:18:30 PM PST 24
Peak memory 203508 kb
Host smart-37070ffe-8a30-4905-b38f-45327d35d2ae
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727565480 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_aliasing.727565480
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.949121403
Short name T275
Test name
Test status
Simulation time 544998937 ps
CPU time 2.89 seconds
Started Mar 05 01:18:57 PM PST 24
Finished Mar 05 01:19:00 PM PST 24
Peak memory 203744 kb
Host smart-47b084e3-ed48-492b-b723-01f2a4f61415
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949121403 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_bit_bash.949121403
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3712948886
Short name T76
Test name
Test status
Simulation time 29699890 ps
CPU time 0.7 seconds
Started Mar 05 01:18:52 PM PST 24
Finished Mar 05 01:18:53 PM PST 24
Peak memory 203524 kb
Host smart-5358ac8c-eac9-4ce4-8133-c6badce17029
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712948886 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.3
712948886
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3429166242
Short name T332
Test name
Test status
Simulation time 15443605 ps
CPU time 0.61 seconds
Started Mar 05 01:18:44 PM PST 24
Finished Mar 05 01:18:45 PM PST 24
Peak memory 203628 kb
Host smart-03c11752-8412-40b0-bebf-ff718d14cd94
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429166242 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.3429166242
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.4198376264
Short name T244
Test name
Test status
Simulation time 33362053 ps
CPU time 0.65 seconds
Started Mar 05 01:18:42 PM PST 24
Finished Mar 05 01:18:43 PM PST 24
Peak memory 203420 kb
Host smart-b6ff93b7-b680-45e0-95fe-54783de9b45e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198376264 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.4198376264
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3934537467
Short name T117
Test name
Test status
Simulation time 144928032 ps
CPU time 6.58 seconds
Started Mar 05 01:18:46 PM PST 24
Finished Mar 05 01:18:53 PM PST 24
Peak memory 203820 kb
Host smart-db8b0d41-9e5d-44a8-8bc4-31a86212cd16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934537467 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_
csr_outstanding.3934537467
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.2884841083
Short name T297
Test name
Test status
Simulation time 995493691 ps
CPU time 2.51 seconds
Started Mar 05 01:18:41 PM PST 24
Finished Mar 05 01:18:44 PM PST 24
Peak memory 212120 kb
Host smart-d13b57e8-b599-4de9-9818-41496f4a2571
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884841083 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.2884841083
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.1272214621
Short name T330
Test name
Test status
Simulation time 1169026304 ps
CPU time 3.72 seconds
Started Mar 05 01:19:04 PM PST 24
Finished Mar 05 01:19:09 PM PST 24
Peak memory 212144 kb
Host smart-bf910e7d-9e6a-4daa-b254-98a76fa06840
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272214621 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.1272214621
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.2260612885
Short name T325
Test name
Test status
Simulation time 164135124 ps
CPU time 1.59 seconds
Started Mar 05 01:19:01 PM PST 24
Finished Mar 05 01:19:05 PM PST 24
Peak memory 203732 kb
Host smart-d43245b3-6ce5-40c4-9f5d-6ce705e82c21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260612885 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.2260612885
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3183785656
Short name T249
Test name
Test status
Simulation time 322948899 ps
CPU time 1.23 seconds
Started Mar 05 01:18:57 PM PST 24
Finished Mar 05 01:18:58 PM PST 24
Peak memory 203676 kb
Host smart-9d18f79a-4745-46f7-ab8c-c1837222b0b7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183785656 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
3183785656
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.2195007352
Short name T346
Test name
Test status
Simulation time 75989824 ps
CPU time 0.85 seconds
Started Mar 05 01:19:08 PM PST 24
Finished Mar 05 01:19:09 PM PST 24
Peak memory 203536 kb
Host smart-e3835fbc-e7f5-4576-90e9-30eff0343678
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195007352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
2195007352
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.965159079
Short name T348
Test name
Test status
Simulation time 1012511527 ps
CPU time 3.95 seconds
Started Mar 05 01:19:10 PM PST 24
Finished Mar 05 01:19:15 PM PST 24
Peak memory 203824 kb
Host smart-cf649fc1-07bd-4c2d-8dad-c061bb8abf7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965159079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same_
csr_outstanding.965159079
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.938832252
Short name T37
Test name
Test status
Simulation time 2069760473 ps
CPU time 10.88 seconds
Started Mar 05 01:19:01 PM PST 24
Finished Mar 05 01:19:13 PM PST 24
Peak memory 212540 kb
Host smart-d3e198d8-ee61-47cf-a67d-c8022607e958
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938832252 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.938832252
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1010191761
Short name T282
Test name
Test status
Simulation time 105777324 ps
CPU time 2.2 seconds
Started Mar 05 01:18:58 PM PST 24
Finished Mar 05 01:19:00 PM PST 24
Peak memory 214052 kb
Host smart-26aefdae-a42e-45b6-9726-74e6ef9662f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010191761 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.1010191761
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.204981360
Short name T363
Test name
Test status
Simulation time 97495797 ps
CPU time 1.47 seconds
Started Mar 05 01:18:57 PM PST 24
Finished Mar 05 01:18:58 PM PST 24
Peak memory 203592 kb
Host smart-c4f72dcc-a4f2-4d68-8ec0-3d2930c27e41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204981360 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.204981360
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3431902259
Short name T316
Test name
Test status
Simulation time 136132192 ps
CPU time 1.2 seconds
Started Mar 05 01:18:58 PM PST 24
Finished Mar 05 01:19:00 PM PST 24
Peak memory 203748 kb
Host smart-4722e391-4c72-449c-a3a4-8f9ccc81e136
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431902259 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
3431902259
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.122355616
Short name T274
Test name
Test status
Simulation time 56574692 ps
CPU time 0.71 seconds
Started Mar 05 01:18:58 PM PST 24
Finished Mar 05 01:18:59 PM PST 24
Peak memory 203512 kb
Host smart-b12b890d-6b0b-4e5a-a4df-20dec57d709d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122355616 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.122355616
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tap_fsm_rand_reset.3606625990
Short name T260
Test name
Test status
Simulation time 13419048210 ps
CPU time 10.69 seconds
Started Mar 05 01:19:01 PM PST 24
Finished Mar 05 01:19:14 PM PST 24
Peak memory 219448 kb
Host smart-75ceb97e-119f-4508-a428-694aba47f62e
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606625990 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rv_dm_tap_fsm_rand_reset.3606625990
Directory /workspace/11.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3298942953
Short name T362
Test name
Test status
Simulation time 277273367 ps
CPU time 7.66 seconds
Started Mar 05 01:18:59 PM PST 24
Finished Mar 05 01:19:06 PM PST 24
Peak memory 212080 kb
Host smart-c3816fa1-d54f-43ed-9d6c-fbe46c6af034
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298942953 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.3
298942953
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.766743909
Short name T93
Test name
Test status
Simulation time 4183337999 ps
CPU time 5.04 seconds
Started Mar 05 01:19:06 PM PST 24
Finished Mar 05 01:19:12 PM PST 24
Peak memory 220268 kb
Host smart-3f8e6d1d-113e-4fae-87e2-4fc17fb2c388
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766743909 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.766743909
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.2811057029
Short name T376
Test name
Test status
Simulation time 95213889 ps
CPU time 1.48 seconds
Started Mar 05 01:18:59 PM PST 24
Finished Mar 05 01:19:02 PM PST 24
Peak memory 203788 kb
Host smart-39f78a5e-ada3-4193-99b4-caa9e6b0daa1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811057029 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.2811057029
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.3225824542
Short name T291
Test name
Test status
Simulation time 854312819 ps
CPU time 1.58 seconds
Started Mar 05 01:19:04 PM PST 24
Finished Mar 05 01:19:07 PM PST 24
Peak memory 203696 kb
Host smart-5600e843-ff88-41ed-93c0-89b181fc6935
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225824542 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
3225824542
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2338481555
Short name T294
Test name
Test status
Simulation time 82670113 ps
CPU time 0.76 seconds
Started Mar 05 01:19:03 PM PST 24
Finished Mar 05 01:19:05 PM PST 24
Peak memory 203524 kb
Host smart-8ab133a7-da78-4644-ab6d-12cd01819be0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338481555 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
2338481555
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1605504742
Short name T317
Test name
Test status
Simulation time 1616487734 ps
CPU time 7.63 seconds
Started Mar 05 01:18:58 PM PST 24
Finished Mar 05 01:19:06 PM PST 24
Peak memory 203876 kb
Host smart-eafca904-527f-4fc3-bc16-eb086a036889
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605504742 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.1605504742
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.4254489167
Short name T306
Test name
Test status
Simulation time 4107437970 ps
CPU time 6.11 seconds
Started Mar 05 01:19:00 PM PST 24
Finished Mar 05 01:19:08 PM PST 24
Peak memory 212188 kb
Host smart-1bc71f0a-0fdb-4e0f-81d0-44d64b1a3ea8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254489167 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.4254489167
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.1422321585
Short name T136
Test name
Test status
Simulation time 849246620 ps
CPU time 9.58 seconds
Started Mar 05 01:18:57 PM PST 24
Finished Mar 05 01:19:07 PM PST 24
Peak memory 212144 kb
Host smart-9b4c871b-34f2-4809-b09f-cebdcbf13972
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422321585 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.1
422321585
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3758996808
Short name T83
Test name
Test status
Simulation time 1528065828 ps
CPU time 5.32 seconds
Started Mar 05 01:18:56 PM PST 24
Finished Mar 05 01:19:02 PM PST 24
Peak memory 215004 kb
Host smart-ab0297bd-809a-4a25-86ad-9f35fab4d0ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758996808 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.3758996808
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.2315902260
Short name T326
Test name
Test status
Simulation time 326129722 ps
CPU time 2.28 seconds
Started Mar 05 01:19:04 PM PST 24
Finished Mar 05 01:19:07 PM PST 24
Peak memory 211964 kb
Host smart-8f30eb7f-38b7-4059-8386-66984ac3d7fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315902260 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.2315902260
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.2939495613
Short name T345
Test name
Test status
Simulation time 225349227 ps
CPU time 1.3 seconds
Started Mar 05 01:18:57 PM PST 24
Finished Mar 05 01:18:58 PM PST 24
Peak memory 203772 kb
Host smart-680886b8-f603-4248-a6ef-0b45630734e3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939495613 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
2939495613
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3653688469
Short name T270
Test name
Test status
Simulation time 100688440 ps
CPU time 0.66 seconds
Started Mar 05 01:18:58 PM PST 24
Finished Mar 05 01:18:59 PM PST 24
Peak memory 203516 kb
Host smart-04d3d5f2-891f-40da-ab79-1cfe5a623010
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653688469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
3653688469
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.566273897
Short name T104
Test name
Test status
Simulation time 616329982 ps
CPU time 4.21 seconds
Started Mar 05 01:19:00 PM PST 24
Finished Mar 05 01:19:04 PM PST 24
Peak memory 203824 kb
Host smart-14fa71de-13d5-4a36-a51b-841b08e3709f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566273897 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same_
csr_outstanding.566273897
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.415719158
Short name T81
Test name
Test status
Simulation time 50571238 ps
CPU time 2.43 seconds
Started Mar 05 01:18:58 PM PST 24
Finished Mar 05 01:19:01 PM PST 24
Peak memory 203968 kb
Host smart-71cff4c4-c2a3-4d1d-87dd-dd967a32a585
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415719158 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.415719158
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.2664287373
Short name T250
Test name
Test status
Simulation time 2581162111 ps
CPU time 6.21 seconds
Started Mar 05 01:19:01 PM PST 24
Finished Mar 05 01:19:09 PM PST 24
Peak memory 212128 kb
Host smart-9fbcbc7d-7c33-4907-9b56-795c27d75b1e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664287373 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.2664287373
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.2932534035
Short name T110
Test name
Test status
Simulation time 412401216 ps
CPU time 2.27 seconds
Started Mar 05 01:19:08 PM PST 24
Finished Mar 05 01:19:11 PM PST 24
Peak memory 212012 kb
Host smart-eba57b96-ce3d-44a3-9e86-2cef311b4162
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932534035 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.2932534035
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1265262245
Short name T333
Test name
Test status
Simulation time 446928182 ps
CPU time 2.08 seconds
Started Mar 05 01:19:11 PM PST 24
Finished Mar 05 01:19:14 PM PST 24
Peak memory 203756 kb
Host smart-4806ff51-8151-4788-9919-9b4054c0f911
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265262245 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
1265262245
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2512765157
Short name T263
Test name
Test status
Simulation time 48419519 ps
CPU time 0.84 seconds
Started Mar 05 01:18:58 PM PST 24
Finished Mar 05 01:18:59 PM PST 24
Peak memory 203424 kb
Host smart-db2e8d54-6b11-4e1f-80be-463017d857d3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512765157 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
2512765157
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3748570749
Short name T116
Test name
Test status
Simulation time 459718580 ps
CPU time 4.23 seconds
Started Mar 05 01:19:02 PM PST 24
Finished Mar 05 01:19:08 PM PST 24
Peak memory 203856 kb
Host smart-16d85961-d7e2-4f10-891e-50d8bee63051
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748570749 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.3748570749
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tap_fsm_rand_reset.2909670132
Short name T308
Test name
Test status
Simulation time 11331573590 ps
CPU time 18.09 seconds
Started Mar 05 01:19:02 PM PST 24
Finished Mar 05 01:19:22 PM PST 24
Peak memory 215852 kb
Host smart-eb7b3aaf-a0e9-4dbb-8aac-66553a28d269
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909670132 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rv_dm_tap_fsm_rand_reset.2909670132
Directory /workspace/14.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.3239910909
Short name T366
Test name
Test status
Simulation time 228382433 ps
CPU time 6.29 seconds
Started Mar 05 01:19:04 PM PST 24
Finished Mar 05 01:19:11 PM PST 24
Peak memory 212052 kb
Host smart-10af6078-6245-43c6-97b6-979ff7cb9cf4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239910909 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.3239910909
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3893871118
Short name T131
Test name
Test status
Simulation time 412375958 ps
CPU time 8.31 seconds
Started Mar 05 01:19:00 PM PST 24
Finished Mar 05 01:19:09 PM PST 24
Peak memory 212092 kb
Host smart-574840e9-2983-44ef-8332-421eb5c68ce1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893871118 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.3
893871118
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.867697840
Short name T290
Test name
Test status
Simulation time 81402459 ps
CPU time 4.58 seconds
Started Mar 05 01:19:01 PM PST 24
Finished Mar 05 01:19:06 PM PST 24
Peak memory 212124 kb
Host smart-900e6688-d063-4d96-bc65-8d97bafa6b73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867697840 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.867697840
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2062956856
Short name T264
Test name
Test status
Simulation time 34280578 ps
CPU time 1.45 seconds
Started Mar 05 01:19:00 PM PST 24
Finished Mar 05 01:19:02 PM PST 24
Peak memory 203828 kb
Host smart-160701e7-33ca-428e-add9-8cbb13825f07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062956856 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.2062956856
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1119598228
Short name T331
Test name
Test status
Simulation time 290196330 ps
CPU time 1.54 seconds
Started Mar 05 01:18:59 PM PST 24
Finished Mar 05 01:19:02 PM PST 24
Peak memory 203764 kb
Host smart-fa026fa6-a6ec-437e-9d5f-3a859964f942
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119598228 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
1119598228
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.4057365544
Short name T77
Test name
Test status
Simulation time 32084017 ps
CPU time 0.7 seconds
Started Mar 05 01:19:02 PM PST 24
Finished Mar 05 01:19:04 PM PST 24
Peak memory 203532 kb
Host smart-388686a9-9c4f-454e-9f44-8264ba9500fa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057365544 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
4057365544
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.4054106861
Short name T353
Test name
Test status
Simulation time 324743420 ps
CPU time 4.59 seconds
Started Mar 05 01:19:04 PM PST 24
Finished Mar 05 01:19:09 PM PST 24
Peak memory 203856 kb
Host smart-6720c690-18ba-46a3-813b-26e7f87f9a92
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054106861 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.4054106861
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.4029285678
Short name T261
Test name
Test status
Simulation time 1294253736 ps
CPU time 5.8 seconds
Started Mar 05 01:18:58 PM PST 24
Finished Mar 05 01:19:04 PM PST 24
Peak memory 212076 kb
Host smart-a1a109b5-1c57-4e29-8c79-582d338a7256
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029285678 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.4029285678
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2595030675
Short name T129
Test name
Test status
Simulation time 393486814 ps
CPU time 8.17 seconds
Started Mar 05 01:18:57 PM PST 24
Finished Mar 05 01:19:06 PM PST 24
Peak memory 212060 kb
Host smart-a34d59b2-297f-43f8-906e-62e6f918f441
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595030675 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.2
595030675
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2840698080
Short name T368
Test name
Test status
Simulation time 121679019 ps
CPU time 2.22 seconds
Started Mar 05 01:19:02 PM PST 24
Finished Mar 05 01:19:06 PM PST 24
Peak memory 214792 kb
Host smart-e2de42bf-1719-4a2f-804b-579ca8174d84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840698080 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.2840698080
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.557102099
Short name T307
Test name
Test status
Simulation time 109202791 ps
CPU time 2.25 seconds
Started Mar 05 01:18:56 PM PST 24
Finished Mar 05 01:18:59 PM PST 24
Peak memory 212000 kb
Host smart-6b4d8cf0-3338-4fea-8720-197540d6d9b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557102099 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.557102099
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.3565878741
Short name T370
Test name
Test status
Simulation time 132692455 ps
CPU time 1.16 seconds
Started Mar 05 01:18:57 PM PST 24
Finished Mar 05 01:18:58 PM PST 24
Peak memory 203768 kb
Host smart-9affddd9-9e49-4303-b610-f6350a491009
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565878741 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
3565878741
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2352211289
Short name T273
Test name
Test status
Simulation time 68285280 ps
CPU time 0.81 seconds
Started Mar 05 01:19:07 PM PST 24
Finished Mar 05 01:19:09 PM PST 24
Peak memory 203340 kb
Host smart-f90a4cce-29a9-456a-9c9a-409a5bf54fa3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352211289 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
2352211289
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3727862885
Short name T102
Test name
Test status
Simulation time 756979195 ps
CPU time 6.54 seconds
Started Mar 05 01:19:01 PM PST 24
Finished Mar 05 01:19:08 PM PST 24
Peak memory 203832 kb
Host smart-e355c567-20cf-4a44-a30e-1a0a05d22aa7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727862885 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.3727862885
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.2792283620
Short name T164
Test name
Test status
Simulation time 175138783 ps
CPU time 3.92 seconds
Started Mar 05 01:18:59 PM PST 24
Finished Mar 05 01:19:03 PM PST 24
Peak memory 212140 kb
Host smart-fceb77e4-4100-4d2e-b55d-c5d8652054e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792283620 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.2792283620
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.3686331139
Short name T276
Test name
Test status
Simulation time 297448299 ps
CPU time 2.25 seconds
Started Mar 05 01:19:04 PM PST 24
Finished Mar 05 01:19:07 PM PST 24
Peak memory 212072 kb
Host smart-f9b2064e-d758-4965-94be-65728aa72224
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686331139 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.3686331139
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.4036965839
Short name T112
Test name
Test status
Simulation time 671437241 ps
CPU time 2.26 seconds
Started Mar 05 01:19:04 PM PST 24
Finished Mar 05 01:19:07 PM PST 24
Peak memory 203764 kb
Host smart-395c2fab-39a8-4947-a96b-4b02e0039214
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036965839 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.4036965839
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2263985129
Short name T258
Test name
Test status
Simulation time 226663005 ps
CPU time 1.22 seconds
Started Mar 05 01:19:00 PM PST 24
Finished Mar 05 01:19:02 PM PST 24
Peak memory 203708 kb
Host smart-957ab497-bc2b-4d2a-bb1c-23058c057d0b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263985129 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
2263985129
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.1229558958
Short name T279
Test name
Test status
Simulation time 25317038 ps
CPU time 0.67 seconds
Started Mar 05 01:19:06 PM PST 24
Finished Mar 05 01:19:07 PM PST 24
Peak memory 203364 kb
Host smart-2a910d53-7d0a-4d95-9970-c2eefe752ddd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229558958 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
1229558958
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3657046103
Short name T91
Test name
Test status
Simulation time 380385640 ps
CPU time 7 seconds
Started Mar 05 01:19:06 PM PST 24
Finished Mar 05 01:19:14 PM PST 24
Peak memory 203812 kb
Host smart-f3fa4cbd-ec62-42b0-ab9e-368707f375c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657046103 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.3657046103
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tap_fsm_rand_reset.1070737461
Short name T318
Test name
Test status
Simulation time 5823556391 ps
CPU time 19.7 seconds
Started Mar 05 01:19:02 PM PST 24
Finished Mar 05 01:19:23 PM PST 24
Peak memory 215340 kb
Host smart-428dac3a-60bd-4bc3-a294-90edd8f5fcf5
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070737461 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rv_dm_tap_fsm_rand_reset.1070737461
Directory /workspace/17.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2214397820
Short name T365
Test name
Test status
Simulation time 74331594 ps
CPU time 3.89 seconds
Started Mar 05 01:19:05 PM PST 24
Finished Mar 05 01:19:11 PM PST 24
Peak memory 204396 kb
Host smart-8146db52-f613-4d55-b544-25404da86704
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214397820 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.2214397820
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.3557546964
Short name T133
Test name
Test status
Simulation time 3465824788 ps
CPU time 17.51 seconds
Started Mar 05 01:19:05 PM PST 24
Finished Mar 05 01:19:23 PM PST 24
Peak memory 216040 kb
Host smart-b01b6c99-0046-4f17-b2bd-14b87efc96ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557546964 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.3
557546964
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.3586466191
Short name T40
Test name
Test status
Simulation time 2874542637 ps
CPU time 2.8 seconds
Started Mar 05 01:19:04 PM PST 24
Finished Mar 05 01:19:08 PM PST 24
Peak memory 212472 kb
Host smart-e8ca172c-b7ea-48c3-abde-8ad242a6a389
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586466191 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.3586466191
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.3183096216
Short name T343
Test name
Test status
Simulation time 47748353 ps
CPU time 1.39 seconds
Started Mar 05 01:19:11 PM PST 24
Finished Mar 05 01:19:12 PM PST 24
Peak memory 203712 kb
Host smart-352d834e-c9ef-4025-a645-a6f624bbc09e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183096216 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.3183096216
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2830423653
Short name T367
Test name
Test status
Simulation time 282826826 ps
CPU time 1.6 seconds
Started Mar 05 01:19:05 PM PST 24
Finished Mar 05 01:19:07 PM PST 24
Peak memory 203700 kb
Host smart-8fea612f-7316-440d-a6bc-2559d636f391
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830423653 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
2830423653
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2502175719
Short name T312
Test name
Test status
Simulation time 84871948 ps
CPU time 0.64 seconds
Started Mar 05 01:19:07 PM PST 24
Finished Mar 05 01:19:08 PM PST 24
Peak memory 203508 kb
Host smart-ae9a61e4-a17c-4441-94bc-f41b929c5629
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502175719 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
2502175719
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3156023385
Short name T92
Test name
Test status
Simulation time 162614812 ps
CPU time 3.6 seconds
Started Mar 05 01:19:07 PM PST 24
Finished Mar 05 01:19:11 PM PST 24
Peak memory 203864 kb
Host smart-2732a3eb-97e0-49c0-8dc6-a5d51c74960e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156023385 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.3156023385
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.3706903917
Short name T313
Test name
Test status
Simulation time 224179549 ps
CPU time 2.38 seconds
Started Mar 05 01:19:06 PM PST 24
Finished Mar 05 01:19:09 PM PST 24
Peak memory 212116 kb
Host smart-05da2cb0-1ca0-4671-a5f0-bf9d2ef8f086
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706903917 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.3706903917
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.4015010964
Short name T373
Test name
Test status
Simulation time 643754555 ps
CPU time 15.44 seconds
Started Mar 05 01:19:06 PM PST 24
Finished Mar 05 01:19:22 PM PST 24
Peak memory 211920 kb
Host smart-c5fc1034-c63d-441c-ab2c-d50a70ae2b5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015010964 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.4
015010964
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2133889872
Short name T305
Test name
Test status
Simulation time 7961531417 ps
CPU time 7.38 seconds
Started Mar 05 01:19:00 PM PST 24
Finished Mar 05 01:19:08 PM PST 24
Peak memory 220356 kb
Host smart-05f5cf25-685f-45a6-afd8-e11d76d04779
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133889872 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.2133889872
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3723432383
Short name T90
Test name
Test status
Simulation time 48545787 ps
CPU time 1.37 seconds
Started Mar 05 01:19:15 PM PST 24
Finished Mar 05 01:19:17 PM PST 24
Peak memory 203736 kb
Host smart-67fbe7c1-4f90-4d35-a2e6-225fe5708c66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723432383 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.3723432383
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.581565041
Short name T364
Test name
Test status
Simulation time 1383683220 ps
CPU time 4.82 seconds
Started Mar 05 01:19:04 PM PST 24
Finished Mar 05 01:19:10 PM PST 24
Peak memory 203716 kb
Host smart-c041ac6e-0217-4c96-a2f2-0e9908fda16a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581565041 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.581565041
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2385934199
Short name T259
Test name
Test status
Simulation time 54676799 ps
CPU time 0.68 seconds
Started Mar 05 01:18:59 PM PST 24
Finished Mar 05 01:19:00 PM PST 24
Peak memory 203356 kb
Host smart-5e4bb69e-69ca-4fbb-b225-da8a2b71dcd0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385934199 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
2385934199
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.2756610880
Short name T54
Test name
Test status
Simulation time 250147863 ps
CPU time 4.13 seconds
Started Mar 05 01:19:19 PM PST 24
Finished Mar 05 01:19:23 PM PST 24
Peak memory 203836 kb
Host smart-bf8b45ae-cbc3-4375-b6c5-fedbb99d6f50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756610880 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.2756610880
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.1396486351
Short name T329
Test name
Test status
Simulation time 553530418 ps
CPU time 9.73 seconds
Started Mar 05 01:19:04 PM PST 24
Finished Mar 05 01:19:14 PM PST 24
Peak memory 212200 kb
Host smart-3b718564-c132-474b-ada5-3b3701e45935
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396486351 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.1
396486351
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.3964355452
Short name T100
Test name
Test status
Simulation time 10241134697 ps
CPU time 74.15 seconds
Started Mar 05 01:18:43 PM PST 24
Finished Mar 05 01:19:57 PM PST 24
Peak memory 203720 kb
Host smart-8f72afdd-92c4-48dc-836e-12598df36d3c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964355452 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.3964355452
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.952155580
Short name T340
Test name
Test status
Simulation time 1408203561 ps
CPU time 28.11 seconds
Started Mar 05 01:18:46 PM PST 24
Finished Mar 05 01:19:14 PM PST 24
Peak memory 203824 kb
Host smart-8ff2a0d2-9102-4675-8f79-d623d1e2ff7d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952155580 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.952155580
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3909729154
Short name T349
Test name
Test status
Simulation time 128931314 ps
CPU time 1.4 seconds
Started Mar 05 01:18:38 PM PST 24
Finished Mar 05 01:18:40 PM PST 24
Peak memory 203900 kb
Host smart-00bb0f4e-c648-4fd8-8828-bcb3de59bf0e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909729154 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.3909729154
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3471313097
Short name T82
Test name
Test status
Simulation time 119122960 ps
CPU time 3.51 seconds
Started Mar 05 01:18:47 PM PST 24
Finished Mar 05 01:18:51 PM PST 24
Peak memory 216444 kb
Host smart-79f10e36-d952-49a6-9cdf-cc9fe18c06cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471313097 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.3471313097
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3842821824
Short name T109
Test name
Test status
Simulation time 70977090 ps
CPU time 2.02 seconds
Started Mar 05 01:18:41 PM PST 24
Finished Mar 05 01:18:44 PM PST 24
Peak memory 203720 kb
Host smart-133a0dd4-6b65-4cf1-a5cb-d3e14bff19a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842821824 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.3842821824
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.1793950072
Short name T254
Test name
Test status
Simulation time 10053697687 ps
CPU time 32.37 seconds
Started Mar 05 01:18:40 PM PST 24
Finished Mar 05 01:19:13 PM PST 24
Peak memory 203812 kb
Host smart-becdff47-d287-43f2-bed4-c67c7335e786
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793950072 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.1793950072
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.4105696427
Short name T284
Test name
Test status
Simulation time 28856302790 ps
CPU time 27.67 seconds
Started Mar 05 01:18:45 PM PST 24
Finished Mar 05 01:19:13 PM PST 24
Peak memory 203752 kb
Host smart-486a375e-5497-4d4f-8272-868b57c1f2b1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105696427 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_bit_bash.4105696427
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.4231100186
Short name T98
Test name
Test status
Simulation time 408850459 ps
CPU time 1.45 seconds
Started Mar 05 01:18:48 PM PST 24
Finished Mar 05 01:18:49 PM PST 24
Peak memory 203760 kb
Host smart-d59e59ed-9cfe-471f-94d8-622c9ce0818c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231100186 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.4231100186
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.215505357
Short name T295
Test name
Test status
Simulation time 335643506 ps
CPU time 1.65 seconds
Started Mar 05 01:18:42 PM PST 24
Finished Mar 05 01:18:44 PM PST 24
Peak memory 203764 kb
Host smart-7f078c19-7409-4fc4-8674-0a465a06f98b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215505357 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.215505357
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3848974737
Short name T289
Test name
Test status
Simulation time 110171036 ps
CPU time 0.8 seconds
Started Mar 05 01:18:53 PM PST 24
Finished Mar 05 01:18:54 PM PST 24
Peak memory 203424 kb
Host smart-401c2320-c432-44dd-bd97-7d1c8cd185d6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848974737 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_aliasing.3848974737
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.14596116
Short name T335
Test name
Test status
Simulation time 5154515246 ps
CPU time 4.27 seconds
Started Mar 05 01:18:51 PM PST 24
Finished Mar 05 01:18:55 PM PST 24
Peak memory 203712 kb
Host smart-d23d626b-a2a4-473d-a729-3e0a4aa0a96e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14596116 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_
bit_bash.14596116
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2361215208
Short name T344
Test name
Test status
Simulation time 189895598 ps
CPU time 0.83 seconds
Started Mar 05 01:18:54 PM PST 24
Finished Mar 05 01:18:55 PM PST 24
Peak memory 203424 kb
Host smart-35cf9f0f-edb3-4766-aae6-dd562b8e0b86
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361215208 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.2361215208
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2412688509
Short name T251
Test name
Test status
Simulation time 82765709 ps
CPU time 0.7 seconds
Started Mar 05 01:18:45 PM PST 24
Finished Mar 05 01:18:46 PM PST 24
Peak memory 203520 kb
Host smart-65f7d33b-eeff-463b-858b-a13f4d3d2dff
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412688509 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.2
412688509
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1360304561
Short name T245
Test name
Test status
Simulation time 18089143 ps
CPU time 0.62 seconds
Started Mar 05 01:18:38 PM PST 24
Finished Mar 05 01:18:38 PM PST 24
Peak memory 203632 kb
Host smart-fa6bc159-93b5-4fc6-8e9d-f7206fa6cc91
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360304561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.1360304561
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.2088302642
Short name T281
Test name
Test status
Simulation time 24300109 ps
CPU time 0.62 seconds
Started Mar 05 01:18:45 PM PST 24
Finished Mar 05 01:18:45 PM PST 24
Peak memory 203504 kb
Host smart-bd945bdf-ca61-461b-ac54-7ed9f5097095
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088302642 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.2088302642
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.79177106
Short name T87
Test name
Test status
Simulation time 552941492 ps
CPU time 7.81 seconds
Started Mar 05 01:18:46 PM PST 24
Finished Mar 05 01:18:54 PM PST 24
Peak memory 203796 kb
Host smart-41fdef90-db0f-4a9f-8bb5-dff3a15ad7ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79177106 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_cs
r_outstanding.79177106
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.4251112810
Short name T53
Test name
Test status
Simulation time 23290578868 ps
CPU time 12.91 seconds
Started Mar 05 01:18:36 PM PST 24
Finished Mar 05 01:18:49 PM PST 24
Peak memory 220344 kb
Host smart-a0b36746-e6ff-4fe4-b393-09f1a78db253
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251112810 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.4251112810
Directory /workspace/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.1889417663
Short name T369
Test name
Test status
Simulation time 596216684 ps
CPU time 5.93 seconds
Started Mar 05 01:18:52 PM PST 24
Finished Mar 05 01:18:58 PM PST 24
Peak memory 212056 kb
Host smart-1960c1fa-25f3-467c-993e-9a7f460e63bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889417663 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.1889417663
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2081034032
Short name T135
Test name
Test status
Simulation time 571179599 ps
CPU time 9.6 seconds
Started Mar 05 01:18:34 PM PST 24
Finished Mar 05 01:18:44 PM PST 24
Peak memory 211844 kb
Host smart-e6febba9-a944-4c7d-ad9e-7676cede2770
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081034032 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.2081034032
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/21.rv_dm_tap_fsm_rand_reset.3798627241
Short name T58
Test name
Test status
Simulation time 7110252795 ps
CPU time 14.39 seconds
Started Mar 05 01:18:59 PM PST 24
Finished Mar 05 01:19:14 PM PST 24
Peak memory 212188 kb
Host smart-f1358443-d07d-4d2a-9957-e730f02bc782
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798627241 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 21.rv_dm_tap_fsm_rand_reset.3798627241
Directory /workspace/21.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/23.rv_dm_tap_fsm_rand_reset.2679856154
Short name T319
Test name
Test status
Simulation time 15745293120 ps
CPU time 16.6 seconds
Started Mar 05 01:19:09 PM PST 24
Finished Mar 05 01:19:25 PM PST 24
Peak memory 219544 kb
Host smart-2d3eb4e3-4690-4875-adc0-dd37c1e425d3
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679856154 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 23.rv_dm_tap_fsm_rand_reset.2679856154
Directory /workspace/23.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/24.rv_dm_tap_fsm_rand_reset.3993015142
Short name T321
Test name
Test status
Simulation time 4794913673 ps
CPU time 16.45 seconds
Started Mar 05 01:19:05 PM PST 24
Finished Mar 05 01:19:22 PM PST 24
Peak memory 214792 kb
Host smart-9a2c3fbd-6f63-4f64-a82d-2ac946735afa
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993015142 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 24.rv_dm_tap_fsm_rand_reset.3993015142
Directory /workspace/24.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/26.rv_dm_tap_fsm_rand_reset.125669601
Short name T169
Test name
Test status
Simulation time 15693517312 ps
CPU time 11.09 seconds
Started Mar 05 01:19:07 PM PST 24
Finished Mar 05 01:19:18 PM PST 24
Peak memory 215204 kb
Host smart-2fee3305-b437-451d-adbc-e9ddd0e82c62
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125669601 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 26.rv_dm_tap_fsm_rand_reset.125669601
Directory /workspace/26.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/27.rv_dm_tap_fsm_rand_reset.1085927299
Short name T267
Test name
Test status
Simulation time 26823486839 ps
CPU time 20.92 seconds
Started Mar 05 01:19:13 PM PST 24
Finished Mar 05 01:19:35 PM PST 24
Peak memory 220344 kb
Host smart-5a7ca85e-57c5-419a-ba2d-0cab81061a72
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085927299 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 27.rv_dm_tap_fsm_rand_reset.1085927299
Directory /workspace/27.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/28.rv_dm_tap_fsm_rand_reset.533723945
Short name T352
Test name
Test status
Simulation time 6301901593 ps
CPU time 12.37 seconds
Started Mar 05 01:19:14 PM PST 24
Finished Mar 05 01:19:27 PM PST 24
Peak memory 214652 kb
Host smart-f8c24e9c-2c49-475e-b01f-4016a5c2cee0
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533723945 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 28.rv_dm_tap_fsm_rand_reset.533723945
Directory /workspace/28.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/29.rv_dm_tap_fsm_rand_reset.3456226293
Short name T168
Test name
Test status
Simulation time 17560848906 ps
CPU time 12.41 seconds
Started Mar 05 01:19:01 PM PST 24
Finished Mar 05 01:19:14 PM PST 24
Peak memory 212392 kb
Host smart-a5f85549-1973-4d7b-b946-18d37a72ca20
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456226293 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 29.rv_dm_tap_fsm_rand_reset.3456226293
Directory /workspace/29.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2840651204
Short name T101
Test name
Test status
Simulation time 6931426307 ps
CPU time 78.13 seconds
Started Mar 05 01:18:58 PM PST 24
Finished Mar 05 01:20:16 PM PST 24
Peak memory 203868 kb
Host smart-efbba301-8cc9-4121-9627-6054f2f27d24
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840651204 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.2840651204
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.3437531311
Short name T111
Test name
Test status
Simulation time 4847143003 ps
CPU time 65.75 seconds
Started Mar 05 01:18:51 PM PST 24
Finished Mar 05 01:19:57 PM PST 24
Peak memory 203796 kb
Host smart-061e057d-9896-48c0-b70a-bec6d29f1335
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437531311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.3437531311
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.2281107994
Short name T315
Test name
Test status
Simulation time 76616259 ps
CPU time 1.49 seconds
Started Mar 05 01:18:52 PM PST 24
Finished Mar 05 01:18:54 PM PST 24
Peak memory 203812 kb
Host smart-f0350613-ef60-4749-ac3b-27869d409f29
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281107994 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.2281107994
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1462789231
Short name T303
Test name
Test status
Simulation time 4099843569 ps
CPU time 5.33 seconds
Started Mar 05 01:18:47 PM PST 24
Finished Mar 05 01:18:53 PM PST 24
Peak memory 220336 kb
Host smart-77e03011-5a5f-41c4-aa99-85bbaa618884
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462789231 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.1462789231
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2936383784
Short name T252
Test name
Test status
Simulation time 64519831 ps
CPU time 1.34 seconds
Started Mar 05 01:18:50 PM PST 24
Finished Mar 05 01:18:52 PM PST 24
Peak memory 203848 kb
Host smart-6653407d-001c-4b39-be25-678fe6518c41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936383784 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.2936383784
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.206791076
Short name T300
Test name
Test status
Simulation time 28967660755 ps
CPU time 28.51 seconds
Started Mar 05 01:18:58 PM PST 24
Finished Mar 05 01:19:27 PM PST 24
Peak memory 203816 kb
Host smart-341cefd3-d138-4fba-b7ad-1cd4d82e055d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206791076 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr
_aliasing.206791076
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.3937000072
Short name T277
Test name
Test status
Simulation time 40904764458 ps
CPU time 25.77 seconds
Started Mar 05 01:18:57 PM PST 24
Finished Mar 05 01:19:22 PM PST 24
Peak memory 203756 kb
Host smart-30bacd70-e888-49ed-aa59-ab085ad0ef9f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937000072 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_bit_bash.3937000072
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2614928790
Short name T96
Test name
Test status
Simulation time 1171362072 ps
CPU time 1.54 seconds
Started Mar 05 01:18:52 PM PST 24
Finished Mar 05 01:18:53 PM PST 24
Peak memory 203756 kb
Host smart-0115dc7e-a6c2-4d7e-93fe-39bb481eeb43
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614928790 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.2614928790
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.2268065642
Short name T242
Test name
Test status
Simulation time 405983706 ps
CPU time 1.49 seconds
Started Mar 05 01:18:45 PM PST 24
Finished Mar 05 01:18:47 PM PST 24
Peak memory 203524 kb
Host smart-0bbbdfa5-8813-4a54-8517-3682d73f5a21
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268065642 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.2
268065642
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3376180618
Short name T262
Test name
Test status
Simulation time 88956188 ps
CPU time 0.72 seconds
Started Mar 05 01:18:48 PM PST 24
Finished Mar 05 01:18:49 PM PST 24
Peak memory 203532 kb
Host smart-398e024d-c2d9-416d-8cbd-92d043fad91b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376180618 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.3376180618
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.3886139744
Short name T304
Test name
Test status
Simulation time 1897959382 ps
CPU time 3.72 seconds
Started Mar 05 01:18:51 PM PST 24
Finished Mar 05 01:18:55 PM PST 24
Peak memory 203684 kb
Host smart-4bb605cb-23e9-4830-a674-e61ee104f959
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886139744 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.3886139744
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3701407942
Short name T256
Test name
Test status
Simulation time 34828928 ps
CPU time 0.7 seconds
Started Mar 05 01:18:52 PM PST 24
Finished Mar 05 01:18:53 PM PST 24
Peak memory 203516 kb
Host smart-43589c95-1d55-4bc6-bc5e-28a14f4529fe
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701407942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.3701407942
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1372319035
Short name T361
Test name
Test status
Simulation time 30890319 ps
CPU time 0.72 seconds
Started Mar 05 01:18:49 PM PST 24
Finished Mar 05 01:18:50 PM PST 24
Peak memory 203500 kb
Host smart-6a033794-6a0f-43a7-8869-c5e220d9f9db
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372319035 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.1
372319035
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.272360400
Short name T246
Test name
Test status
Simulation time 53712860 ps
CPU time 0.63 seconds
Started Mar 05 01:18:49 PM PST 24
Finished Mar 05 01:18:50 PM PST 24
Peak memory 203480 kb
Host smart-e0b4260f-8903-4b73-bb31-7b1b7897f683
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272360400 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_part
ial_access.272360400
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.2713447820
Short name T336
Test name
Test status
Simulation time 25275083 ps
CPU time 0.68 seconds
Started Mar 05 01:18:50 PM PST 24
Finished Mar 05 01:18:51 PM PST 24
Peak memory 203516 kb
Host smart-ea38ad8a-ed61-41fd-97da-ea5665624261
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713447820 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.2713447820
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.989489325
Short name T103
Test name
Test status
Simulation time 558696363 ps
CPU time 7.83 seconds
Started Mar 05 01:18:59 PM PST 24
Finished Mar 05 01:19:07 PM PST 24
Peak memory 203880 kb
Host smart-9a1b4a66-2c3c-47db-8f82-3223ffb75352
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989489325 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_c
sr_outstanding.989489325
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.1970466903
Short name T356
Test name
Test status
Simulation time 78623592 ps
CPU time 3.99 seconds
Started Mar 05 01:18:57 PM PST 24
Finished Mar 05 01:19:02 PM PST 24
Peak memory 203952 kb
Host smart-7ba7ce87-32e9-41a0-8044-4baff279732e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970466903 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.1970466903
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/31.rv_dm_tap_fsm_rand_reset.2169831797
Short name T137
Test name
Test status
Simulation time 8069632003 ps
CPU time 15.76 seconds
Started Mar 05 01:19:01 PM PST 24
Finished Mar 05 01:19:18 PM PST 24
Peak memory 212136 kb
Host smart-56a71054-1244-4689-a230-fdb06c2754ec
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169831797 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 31.rv_dm_tap_fsm_rand_reset.2169831797
Directory /workspace/31.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2476470984
Short name T374
Test name
Test status
Simulation time 5038046223 ps
CPU time 30.77 seconds
Started Mar 05 01:18:52 PM PST 24
Finished Mar 05 01:19:23 PM PST 24
Peak memory 203888 kb
Host smart-fc096ce8-eba8-44c7-b0aa-98596de4e6f2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476470984 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.2476470984
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.4266730749
Short name T257
Test name
Test status
Simulation time 737369998 ps
CPU time 26.27 seconds
Started Mar 05 01:18:58 PM PST 24
Finished Mar 05 01:19:25 PM PST 24
Peak memory 203752 kb
Host smart-3bc174af-0a9e-4b60-a4da-5db8f7ef365d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266730749 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.4266730749
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.646919768
Short name T347
Test name
Test status
Simulation time 200391249 ps
CPU time 1.56 seconds
Started Mar 05 01:18:50 PM PST 24
Finished Mar 05 01:18:52 PM PST 24
Peak memory 203768 kb
Host smart-e487ad28-88a4-4e4a-969b-8796e848af5b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646919768 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.646919768
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2991584898
Short name T327
Test name
Test status
Simulation time 4319978928 ps
CPU time 6.12 seconds
Started Mar 05 01:19:02 PM PST 24
Finished Mar 05 01:19:10 PM PST 24
Peak memory 215228 kb
Host smart-3ccd51e8-5f2e-46a2-88a5-c1e6ac921bcf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991584898 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.2991584898
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.2843626564
Short name T107
Test name
Test status
Simulation time 111421180 ps
CPU time 1.54 seconds
Started Mar 05 01:18:51 PM PST 24
Finished Mar 05 01:18:53 PM PST 24
Peak memory 211944 kb
Host smart-98c66068-fe82-4937-b1aa-0719907dcaba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843626564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.2843626564
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2129416596
Short name T375
Test name
Test status
Simulation time 8092607044 ps
CPU time 10.26 seconds
Started Mar 05 01:18:57 PM PST 24
Finished Mar 05 01:19:07 PM PST 24
Peak memory 203816 kb
Host smart-59ba313c-d9c5-4dc4-a890-553d5b318ab7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129416596 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.2129416596
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3532986082
Short name T359
Test name
Test status
Simulation time 13111116145 ps
CPU time 47.69 seconds
Started Mar 05 01:18:54 PM PST 24
Finished Mar 05 01:19:42 PM PST 24
Peak memory 203720 kb
Host smart-0b3753ed-8ec8-4dcb-8fd9-bcb8ad7cea67
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532986082 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_bit_bash.3532986082
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.1594234803
Short name T97
Test name
Test status
Simulation time 522552827 ps
CPU time 2.65 seconds
Started Mar 05 01:18:58 PM PST 24
Finished Mar 05 01:19:01 PM PST 24
Peak memory 203760 kb
Host smart-63466a2e-a62f-4759-827d-51f91812927f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594234803 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.1594234803
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.89802082
Short name T280
Test name
Test status
Simulation time 1085284614 ps
CPU time 2.46 seconds
Started Mar 05 01:18:43 PM PST 24
Finished Mar 05 01:18:46 PM PST 24
Peak memory 203696 kb
Host smart-32dbe80c-0d74-4ac4-8bf5-925d46286bb9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89802082 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.89802082
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.3265315838
Short name T298
Test name
Test status
Simulation time 103682117 ps
CPU time 0.73 seconds
Started Mar 05 01:18:49 PM PST 24
Finished Mar 05 01:18:50 PM PST 24
Peak memory 203412 kb
Host smart-082e82fe-259a-4a2d-b33e-2e70e041cac0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265315838 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.3265315838
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2250266787
Short name T358
Test name
Test status
Simulation time 875484623 ps
CPU time 2.4 seconds
Started Mar 05 01:18:41 PM PST 24
Finished Mar 05 01:18:44 PM PST 24
Peak memory 203752 kb
Host smart-75555a2b-d694-4091-8eeb-1cc808a8cdd6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250266787 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.2250266787
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.3978243253
Short name T268
Test name
Test status
Simulation time 78432316 ps
CPU time 0.76 seconds
Started Mar 05 01:19:01 PM PST 24
Finished Mar 05 01:19:03 PM PST 24
Peak memory 203504 kb
Host smart-b6732352-d6b3-41ae-ad08-2abdfaefad36
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978243253 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.3978243253
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.4055697582
Short name T299
Test name
Test status
Simulation time 52591392 ps
CPU time 0.67 seconds
Started Mar 05 01:18:51 PM PST 24
Finished Mar 05 01:18:52 PM PST 24
Peak memory 203516 kb
Host smart-84d53c07-18b3-4435-9edb-f14cb1a121ab
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055697582 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.4
055697582
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.2357740705
Short name T287
Test name
Test status
Simulation time 55570843 ps
CPU time 0.63 seconds
Started Mar 05 01:18:53 PM PST 24
Finished Mar 05 01:18:54 PM PST 24
Peak memory 203588 kb
Host smart-adfee709-0ff6-42d4-8814-deefd9bad725
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357740705 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.2357740705
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.2504261538
Short name T342
Test name
Test status
Simulation time 28291834 ps
CPU time 0.65 seconds
Started Mar 05 01:18:54 PM PST 24
Finished Mar 05 01:18:55 PM PST 24
Peak memory 203428 kb
Host smart-452bf4b3-4109-4696-a310-7618137adfd0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504261538 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.2504261538
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.700019509
Short name T105
Test name
Test status
Simulation time 214102343 ps
CPU time 4.16 seconds
Started Mar 05 01:18:45 PM PST 24
Finished Mar 05 01:18:49 PM PST 24
Peak memory 203800 kb
Host smart-894019d6-324e-4674-a731-5aa6ed4726bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700019509 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_c
sr_outstanding.700019509
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.1360520499
Short name T147
Test name
Test status
Simulation time 9476399387 ps
CPU time 12.95 seconds
Started Mar 05 01:18:59 PM PST 24
Finished Mar 05 01:19:13 PM PST 24
Peak memory 212120 kb
Host smart-e7873262-83a8-4e58-afd2-7f4633d529d2
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360520499 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.1360520499
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2150178540
Short name T123
Test name
Test status
Simulation time 2494917985 ps
CPU time 3.49 seconds
Started Mar 05 01:18:52 PM PST 24
Finished Mar 05 01:18:56 PM PST 24
Peak memory 204020 kb
Host smart-bae6da36-d591-43a8-b097-40f9d07fb09e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150178540 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.2150178540
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.25503109
Short name T339
Test name
Test status
Simulation time 863946198 ps
CPU time 2.29 seconds
Started Mar 05 01:18:51 PM PST 24
Finished Mar 05 01:18:54 PM PST 24
Peak memory 212056 kb
Host smart-4f4d5c83-1f60-4f28-8b5a-bb7776358e78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25503109 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.25503109
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.1824838267
Short name T309
Test name
Test status
Simulation time 44267441 ps
CPU time 1.44 seconds
Started Mar 05 01:18:52 PM PST 24
Finished Mar 05 01:18:53 PM PST 24
Peak memory 203780 kb
Host smart-a7dd8e0c-9438-4b10-a52e-4fdabd94f015
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824838267 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.1824838267
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.1710837109
Short name T253
Test name
Test status
Simulation time 1030204346 ps
CPU time 3.74 seconds
Started Mar 05 01:18:47 PM PST 24
Finished Mar 05 01:18:51 PM PST 24
Peak memory 203732 kb
Host smart-18b45724-8bc4-413b-b90d-83a0d992e9fe
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710837109 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.1
710837109
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.512999823
Short name T248
Test name
Test status
Simulation time 94770872 ps
CPU time 0.71 seconds
Started Mar 05 01:18:48 PM PST 24
Finished Mar 05 01:18:49 PM PST 24
Peak memory 203512 kb
Host smart-4f795a23-798d-4675-871d-730f7b763367
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512999823 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.512999823
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1194296004
Short name T88
Test name
Test status
Simulation time 394417157 ps
CPU time 6.66 seconds
Started Mar 05 01:18:49 PM PST 24
Finished Mar 05 01:18:56 PM PST 24
Peak memory 203840 kb
Host smart-ed81db16-bff7-4e8d-acfb-3f8452b21a62
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194296004 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.1194296004
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.561990148
Short name T288
Test name
Test status
Simulation time 194677761 ps
CPU time 3.39 seconds
Started Mar 05 01:18:56 PM PST 24
Finished Mar 05 01:19:00 PM PST 24
Peak memory 212020 kb
Host smart-29c378db-edf6-408e-b538-228c23c5e16e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561990148 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.561990148
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3378952818
Short name T38
Test name
Test status
Simulation time 1452736668 ps
CPU time 15.16 seconds
Started Mar 05 01:18:55 PM PST 24
Finished Mar 05 01:19:10 PM PST 24
Peak memory 211976 kb
Host smart-b78f3c9f-3b32-4ad7-8f97-7002f7c2b364
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378952818 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.3378952818
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.283335690
Short name T285
Test name
Test status
Simulation time 59235881 ps
CPU time 2.58 seconds
Started Mar 05 01:18:48 PM PST 24
Finished Mar 05 01:18:51 PM PST 24
Peak memory 214472 kb
Host smart-5eaf8a2b-0f75-4eef-8b9e-c3c42dbb0cf6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283335690 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.283335690
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.2299172174
Short name T377
Test name
Test status
Simulation time 386547552 ps
CPU time 2.28 seconds
Started Mar 05 01:18:52 PM PST 24
Finished Mar 05 01:18:54 PM PST 24
Peak memory 203828 kb
Host smart-039b05cb-95dd-4a03-b96d-a9c40098fb97
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299172174 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.2299172174
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2146899518
Short name T286
Test name
Test status
Simulation time 753841890 ps
CPU time 1.28 seconds
Started Mar 05 01:18:49 PM PST 24
Finished Mar 05 01:18:50 PM PST 24
Peak memory 203732 kb
Host smart-cb190a41-b074-47d7-afc8-613fa25c739a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146899518 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.2
146899518
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.1815315471
Short name T360
Test name
Test status
Simulation time 39766941 ps
CPU time 0.66 seconds
Started Mar 05 01:18:55 PM PST 24
Finished Mar 05 01:18:56 PM PST 24
Peak memory 203544 kb
Host smart-a8f7f2e3-2510-441c-b5e5-34b517f09758
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815315471 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.1
815315471
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.3229342936
Short name T266
Test name
Test status
Simulation time 2078372149 ps
CPU time 4.85 seconds
Started Mar 05 01:18:50 PM PST 24
Finished Mar 05 01:18:55 PM PST 24
Peak memory 203796 kb
Host smart-1fb50ccb-bd29-4d97-8b0d-21b78902ba56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229342936 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.3229342936
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.795911471
Short name T301
Test name
Test status
Simulation time 2004597368 ps
CPU time 4.18 seconds
Started Mar 05 01:18:46 PM PST 24
Finished Mar 05 01:18:50 PM PST 24
Peak memory 203820 kb
Host smart-645dd457-9864-4779-8901-d1be52fd9250
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795911471 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.795911471
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1420382204
Short name T126
Test name
Test status
Simulation time 360105871 ps
CPU time 8.5 seconds
Started Mar 05 01:18:51 PM PST 24
Finished Mar 05 01:19:00 PM PST 24
Peak memory 212028 kb
Host smart-4bfa0db8-19d1-4710-9123-21adca25d5ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420382204 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.1420382204
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2007547394
Short name T351
Test name
Test status
Simulation time 386808801 ps
CPU time 2.1 seconds
Started Mar 05 01:18:51 PM PST 24
Finished Mar 05 01:18:53 PM PST 24
Peak memory 220228 kb
Host smart-a4177cfd-1e58-4e5c-8ad2-421ad7f07673
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007547394 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.2007547394
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.2167044769
Short name T371
Test name
Test status
Simulation time 329053427 ps
CPU time 2.42 seconds
Started Mar 05 01:18:54 PM PST 24
Finished Mar 05 01:18:56 PM PST 24
Peak memory 212044 kb
Host smart-3ccca2bd-6f5d-46fb-9eea-e3f284a92593
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167044769 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.2167044769
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3304354064
Short name T255
Test name
Test status
Simulation time 1261511504 ps
CPU time 2.77 seconds
Started Mar 05 01:18:52 PM PST 24
Finished Mar 05 01:18:55 PM PST 24
Peak memory 203756 kb
Host smart-84617877-1add-4c95-9c70-c3b1f21ce9ec
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304354064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.3
304354064
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.303339026
Short name T322
Test name
Test status
Simulation time 28364703 ps
CPU time 0.72 seconds
Started Mar 05 01:18:51 PM PST 24
Finished Mar 05 01:18:52 PM PST 24
Peak memory 203540 kb
Host smart-197d2d72-f84c-4010-ad5f-d585a38e701f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303339026 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.303339026
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.4117282017
Short name T114
Test name
Test status
Simulation time 490786812 ps
CPU time 4.32 seconds
Started Mar 05 01:18:55 PM PST 24
Finished Mar 05 01:18:59 PM PST 24
Peak memory 203840 kb
Host smart-c01dcfed-fab1-492b-86b6-b87282390b2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117282017 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.4117282017
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.4256864305
Short name T271
Test name
Test status
Simulation time 169125227 ps
CPU time 4.15 seconds
Started Mar 05 01:18:49 PM PST 24
Finished Mar 05 01:18:53 PM PST 24
Peak memory 204016 kb
Host smart-991b5f28-ca76-44a0-bb5e-9b6d5cfb67a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256864305 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.4256864305
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.1324929718
Short name T125
Test name
Test status
Simulation time 886314901 ps
CPU time 17.91 seconds
Started Mar 05 01:18:51 PM PST 24
Finished Mar 05 01:19:09 PM PST 24
Peak memory 212092 kb
Host smart-a22aec91-b4d6-489a-80ce-27592de89f13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324929718 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.1324929718
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.611875716
Short name T247
Test name
Test status
Simulation time 277369067 ps
CPU time 2.08 seconds
Started Mar 05 01:19:08 PM PST 24
Finished Mar 05 01:19:11 PM PST 24
Peak memory 212092 kb
Host smart-f5d414c9-b0e7-431d-9504-0eeef0cb32c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611875716 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.611875716
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.604062659
Short name T328
Test name
Test status
Simulation time 30161187 ps
CPU time 1.49 seconds
Started Mar 05 01:18:58 PM PST 24
Finished Mar 05 01:18:59 PM PST 24
Peak memory 203680 kb
Host smart-989a858d-4b6f-43b5-adae-295ad0c522d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604062659 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.604062659
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.2224503231
Short name T243
Test name
Test status
Simulation time 776225954 ps
CPU time 2.02 seconds
Started Mar 05 01:18:52 PM PST 24
Finished Mar 05 01:18:54 PM PST 24
Peak memory 203632 kb
Host smart-41d9a1ff-917c-4bac-9424-6f47cb944884
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224503231 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.2
224503231
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.1330636499
Short name T272
Test name
Test status
Simulation time 81671121 ps
CPU time 0.7 seconds
Started Mar 05 01:18:48 PM PST 24
Finished Mar 05 01:18:49 PM PST 24
Peak memory 203300 kb
Host smart-e0a55e3a-6c46-4896-9e07-025caeed6ad2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330636499 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.1
330636499
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.3104419947
Short name T106
Test name
Test status
Simulation time 1976817043 ps
CPU time 7.33 seconds
Started Mar 05 01:18:52 PM PST 24
Finished Mar 05 01:19:00 PM PST 24
Peak memory 203860 kb
Host smart-95a4912a-024a-4408-8e78-d41efd71377b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104419947 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_
csr_outstanding.3104419947
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2252537051
Short name T310
Test name
Test status
Simulation time 343742560 ps
CPU time 5.1 seconds
Started Mar 05 01:18:50 PM PST 24
Finished Mar 05 01:18:55 PM PST 24
Peak memory 203968 kb
Host smart-f8b655a4-f0d1-4b9c-853e-1577af02671a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252537051 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.2252537051
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.4167039565
Short name T78
Test name
Test status
Simulation time 1930019830 ps
CPU time 18.22 seconds
Started Mar 05 01:19:11 PM PST 24
Finished Mar 05 01:19:29 PM PST 24
Peak memory 213992 kb
Host smart-208827f9-4177-4dc5-803c-bcda5230a95e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167039565 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.4167039565
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.117047470
Short name T42
Test name
Test status
Simulation time 2685253660 ps
CPU time 3.2 seconds
Started Mar 05 01:18:59 PM PST 24
Finished Mar 05 01:19:02 PM PST 24
Peak memory 214016 kb
Host smart-c96f21de-fd85-4239-ab84-bad83243234c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117047470 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.117047470
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.2118821651
Short name T372
Test name
Test status
Simulation time 50037430 ps
CPU time 1.57 seconds
Started Mar 05 01:18:58 PM PST 24
Finished Mar 05 01:18:59 PM PST 24
Peak memory 203672 kb
Host smart-5298d383-584d-40b6-9224-850e7c63dd2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118821651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.2118821651
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3835805764
Short name T337
Test name
Test status
Simulation time 1282945938 ps
CPU time 1.44 seconds
Started Mar 05 01:19:04 PM PST 24
Finished Mar 05 01:19:07 PM PST 24
Peak memory 203696 kb
Host smart-51db4c6e-d79a-4b63-a514-b0dd5cc90cdb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835805764 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.3
835805764
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.569491481
Short name T314
Test name
Test status
Simulation time 128212746 ps
CPU time 0.74 seconds
Started Mar 05 01:18:58 PM PST 24
Finished Mar 05 01:18:59 PM PST 24
Peak memory 203524 kb
Host smart-78165f70-1d7a-441a-9fae-7d9f38420a44
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569491481 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.569491481
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.1193278166
Short name T338
Test name
Test status
Simulation time 160375000 ps
CPU time 3.72 seconds
Started Mar 05 01:19:06 PM PST 24
Finished Mar 05 01:19:11 PM PST 24
Peak memory 203808 kb
Host smart-107a8a21-effc-4fa6-b1cc-ee24f0f1beb7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193278166 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.1193278166
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.2012072423
Short name T66
Test name
Test status
Simulation time 258323255 ps
CPU time 3.04 seconds
Started Mar 05 01:18:59 PM PST 24
Finished Mar 05 01:19:03 PM PST 24
Peak memory 212144 kb
Host smart-8ae84ec5-5c68-4c3b-b566-b7bb98ae55b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012072423 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.2012072423
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.1598704780
Short name T134
Test name
Test status
Simulation time 1265808061 ps
CPU time 9.89 seconds
Started Mar 05 01:19:08 PM PST 24
Finished Mar 05 01:19:19 PM PST 24
Peak memory 212272 kb
Host smart-c6ea3771-73d4-4a1e-b3ea-bfb0e9d9e3e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598704780 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.1598704780
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.3473050658
Short name T153
Test name
Test status
Simulation time 34106538 ps
CPU time 0.7 seconds
Started Mar 05 12:44:04 PM PST 24
Finished Mar 05 12:44:06 PM PST 24
Peak memory 203820 kb
Host smart-3b5f7cf1-565b-468d-b959-da648b4667fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473050658 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.3473050658
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.3824650061
Short name T181
Test name
Test status
Simulation time 28267371358 ps
CPU time 82.2 seconds
Started Mar 05 12:44:01 PM PST 24
Finished Mar 05 12:45:24 PM PST 24
Peak memory 204036 kb
Host smart-031ef24f-88fb-415d-91db-13f5dad65ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824650061 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.3824650061
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.3333990086
Short name T95
Test name
Test status
Simulation time 5094773242 ps
CPU time 9.41 seconds
Started Mar 05 12:44:07 PM PST 24
Finished Mar 05 12:44:16 PM PST 24
Peak memory 204168 kb
Host smart-981c759c-e029-4811-a6a9-16782af4fe13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333990086 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.3333990086
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.1670388520
Short name T120
Test name
Test status
Simulation time 637860248 ps
CPU time 2.61 seconds
Started Mar 05 12:43:54 PM PST 24
Finished Mar 05 12:43:57 PM PST 24
Peak memory 203948 kb
Host smart-990244c6-5338-46f7-bfb5-5cb3467b5da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670388520 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.1670388520
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.22201752
Short name T119
Test name
Test status
Simulation time 46660313 ps
CPU time 0.66 seconds
Started Mar 05 12:44:00 PM PST 24
Finished Mar 05 12:44:01 PM PST 24
Peak memory 203832 kb
Host smart-2ee4d8ec-fa43-4611-a463-395e2f548150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22201752 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.22201752
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.663124489
Short name T193
Test name
Test status
Simulation time 2666746512 ps
CPU time 7.58 seconds
Started Mar 05 12:44:01 PM PST 24
Finished Mar 05 12:44:09 PM PST 24
Peak memory 204188 kb
Host smart-a26f7103-a3a1-4e32-a8f1-7641891280b4
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=663124489 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_tl
_access.663124489
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.2686054329
Short name T27
Test name
Test status
Simulation time 268031299 ps
CPU time 0.91 seconds
Started Mar 05 12:44:08 PM PST 24
Finished Mar 05 12:44:09 PM PST 24
Peak memory 203948 kb
Host smart-6c77ce63-6ff2-4747-927c-dbd6fa2cd52d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686054329 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.2686054329
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.2169041988
Short name T12
Test name
Test status
Simulation time 78070942 ps
CPU time 0.73 seconds
Started Mar 05 12:44:00 PM PST 24
Finished Mar 05 12:44:02 PM PST 24
Peak memory 203588 kb
Host smart-dee59794-dc0f-492e-a93b-bb764bae89cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169041988 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.2169041988
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.1331918696
Short name T186
Test name
Test status
Simulation time 964507712 ps
CPU time 0.85 seconds
Started Mar 05 12:44:05 PM PST 24
Finished Mar 05 12:44:06 PM PST 24
Peak memory 203500 kb
Host smart-91d102a9-ba58-47f8-ab3a-f4397aa8daa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331918696 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.1331918696
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.1492304118
Short name T56
Test name
Test status
Simulation time 69908085 ps
CPU time 0.76 seconds
Started Mar 05 12:44:03 PM PST 24
Finished Mar 05 12:44:09 PM PST 24
Peak memory 203624 kb
Host smart-60f6aeb2-ef30-4eda-9c59-20310aadfdcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492304118 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.1492304118
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.3065980947
Short name T229
Test name
Test status
Simulation time 119192875 ps
CPU time 0.64 seconds
Started Mar 05 12:43:59 PM PST 24
Finished Mar 05 12:44:00 PM PST 24
Peak memory 203496 kb
Host smart-4a509613-b8cc-4e6c-9b7c-12e21abc89b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065980947 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.3065980947
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.1720733283
Short name T198
Test name
Test status
Simulation time 42803871 ps
CPU time 0.76 seconds
Started Mar 05 12:43:53 PM PST 24
Finished Mar 05 12:43:54 PM PST 24
Peak memory 203860 kb
Host smart-338fac59-2083-488a-8c23-f5dc467681b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720733283 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.1720733283
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.754361650
Short name T139
Test name
Test status
Simulation time 402215916 ps
CPU time 1.36 seconds
Started Mar 05 12:44:10 PM PST 24
Finished Mar 05 12:44:12 PM PST 24
Peak memory 203860 kb
Host smart-cf4291fd-e09e-43f0-b297-8e80d7432c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754361650 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.754361650
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.114046213
Short name T237
Test name
Test status
Simulation time 1288944510 ps
CPU time 1.41 seconds
Started Mar 05 12:43:48 PM PST 24
Finished Mar 05 12:43:50 PM PST 24
Peak memory 204000 kb
Host smart-5b9edfbe-f8b4-4f98-8e60-0d5a613e1506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114046213 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.114046213
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.1012833762
Short name T26
Test name
Test status
Simulation time 48879932 ps
CPU time 0.71 seconds
Started Mar 05 12:44:03 PM PST 24
Finished Mar 05 12:44:04 PM PST 24
Peak memory 203836 kb
Host smart-00626221-5b4c-4804-afc6-acfc52ee5dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012833762 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.1012833762
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.3939943563
Short name T183
Test name
Test status
Simulation time 3850564461 ps
CPU time 4.87 seconds
Started Mar 05 12:44:17 PM PST 24
Finished Mar 05 12:44:22 PM PST 24
Peak memory 204136 kb
Host smart-d407b469-9ce2-46d8-bfd3-573551485e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939943563 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.3939943563
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.3314616182
Short name T34
Test name
Test status
Simulation time 401097909 ps
CPU time 1.21 seconds
Started Mar 05 12:44:03 PM PST 24
Finished Mar 05 12:44:04 PM PST 24
Peak memory 219812 kb
Host smart-ef11affe-1acf-4cfe-a5f8-82633ee10b6b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314616182 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.3314616182
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.1701193729
Short name T189
Test name
Test status
Simulation time 549353668 ps
CPU time 1.74 seconds
Started Mar 05 12:44:10 PM PST 24
Finished Mar 05 12:44:12 PM PST 24
Peak memory 203792 kb
Host smart-89f8e316-178e-4a2e-8258-5cd33423dd22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701193729 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.1701193729
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.859512769
Short name T57
Test name
Test status
Simulation time 3094120643 ps
CPU time 2.62 seconds
Started Mar 05 12:44:07 PM PST 24
Finished Mar 05 12:44:10 PM PST 24
Peak memory 204008 kb
Host smart-dc3832c6-c9e6-43fa-aa91-c42ebce53e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859512769 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.859512769
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.343942798
Short name T50
Test name
Test status
Simulation time 80445417 ps
CPU time 0.64 seconds
Started Mar 05 12:44:19 PM PST 24
Finished Mar 05 12:44:20 PM PST 24
Peak memory 203720 kb
Host smart-7337fb41-3c82-459f-86b6-cf1c6327b765
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343942798 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.343942798
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.1801162821
Short name T1
Test name
Test status
Simulation time 5128447991 ps
CPU time 17.9 seconds
Started Mar 05 12:43:57 PM PST 24
Finished Mar 05 12:44:15 PM PST 24
Peak memory 204196 kb
Host smart-786bd224-ffbe-4e3e-a064-c934a915e980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801162821 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.1801162821
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.2593449911
Short name T28
Test name
Test status
Simulation time 263700890 ps
CPU time 1.5 seconds
Started Mar 05 12:44:11 PM PST 24
Finished Mar 05 12:44:12 PM PST 24
Peak memory 203796 kb
Host smart-8bee4638-bc1b-4d86-b626-3edbcbb2f434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593449911 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.2593449911
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.3751387915
Short name T10
Test name
Test status
Simulation time 167248440 ps
CPU time 0.88 seconds
Started Mar 05 12:43:58 PM PST 24
Finished Mar 05 12:43:59 PM PST 24
Peak memory 203384 kb
Host smart-8e489deb-ecea-4f4d-abb5-3dc12ba2a098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751387915 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.3751387915
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.1582244595
Short name T200
Test name
Test status
Simulation time 932501156 ps
CPU time 3.61 seconds
Started Mar 05 12:44:00 PM PST 24
Finished Mar 05 12:44:04 PM PST 24
Peak memory 204096 kb
Host smart-8bab5ec6-3c3d-4d4b-8a18-42b6b6e9897b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582244595 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.1582244595
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.2356044457
Short name T22
Test name
Test status
Simulation time 89761604 ps
CPU time 0.7 seconds
Started Mar 05 12:44:04 PM PST 24
Finished Mar 05 12:44:05 PM PST 24
Peak memory 203824 kb
Host smart-04821c9b-b78e-41e8-a052-2e52f2425a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356044457 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.2356044457
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.1974517600
Short name T7
Test name
Test status
Simulation time 372996303 ps
CPU time 1.45 seconds
Started Mar 05 12:43:59 PM PST 24
Finished Mar 05 12:44:01 PM PST 24
Peak memory 203932 kb
Host smart-abc29253-aaa9-411e-bac2-c1bef7a6e42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974517600 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.1974517600
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.3980877319
Short name T209
Test name
Test status
Simulation time 51020497 ps
CPU time 0.65 seconds
Started Mar 05 12:44:19 PM PST 24
Finished Mar 05 12:44:19 PM PST 24
Peak memory 203724 kb
Host smart-7eaa01ed-5738-4fc8-951e-d106f2f92510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980877319 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.3980877319
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.3671007414
Short name T18
Test name
Test status
Simulation time 125466860 ps
CPU time 0.79 seconds
Started Mar 05 12:44:13 PM PST 24
Finished Mar 05 12:44:14 PM PST 24
Peak memory 203756 kb
Host smart-69b8bedb-208e-4225-8dce-61df543d68e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671007414 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.3671007414
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.1097794963
Short name T216
Test name
Test status
Simulation time 402976951 ps
CPU time 1.11 seconds
Started Mar 05 12:43:57 PM PST 24
Finished Mar 05 12:43:59 PM PST 24
Peak memory 203696 kb
Host smart-64d28a99-4984-4259-babf-8863ca67a98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097794963 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.1097794963
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.1230547731
Short name T60
Test name
Test status
Simulation time 28203232 ps
CPU time 0.69 seconds
Started Mar 05 12:44:10 PM PST 24
Finished Mar 05 12:44:11 PM PST 24
Peak memory 203460 kb
Host smart-1aeafe82-7c46-4f1e-8907-6d65030149d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230547731 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.1230547731
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.1104091039
Short name T8
Test name
Test status
Simulation time 147553293 ps
CPU time 0.9 seconds
Started Mar 05 12:44:01 PM PST 24
Finished Mar 05 12:44:03 PM PST 24
Peak memory 203836 kb
Host smart-1338059d-e566-4bed-a17a-858dc333f3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104091039 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.1104091039
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.4088433016
Short name T140
Test name
Test status
Simulation time 505835679 ps
CPU time 2.09 seconds
Started Mar 05 12:44:00 PM PST 24
Finished Mar 05 12:44:02 PM PST 24
Peak memory 203928 kb
Host smart-de89ba99-ca32-421e-8261-e96d807b27a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088433016 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.4088433016
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.901138257
Short name T86
Test name
Test status
Simulation time 616596774 ps
CPU time 2.05 seconds
Started Mar 05 12:44:04 PM PST 24
Finished Mar 05 12:44:07 PM PST 24
Peak memory 204004 kb
Host smart-5811e176-b3e8-4c49-a5d1-15baed4869e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901138257 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.901138257
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.1815638060
Short name T17
Test name
Test status
Simulation time 188618415 ps
CPU time 1.22 seconds
Started Mar 05 12:44:14 PM PST 24
Finished Mar 05 12:44:15 PM PST 24
Peak memory 203812 kb
Host smart-fcea25ad-a90f-4d91-91fd-eedff40f6c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815638060 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.1815638060
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.4283626857
Short name T173
Test name
Test status
Simulation time 3118643035 ps
CPU time 10.26 seconds
Started Mar 05 12:44:07 PM PST 24
Finished Mar 05 12:44:17 PM PST 24
Peak memory 204032 kb
Host smart-3f39cadc-e685-45c1-b79a-e0285e521c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283626857 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.4283626857
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.3087573449
Short name T235
Test name
Test status
Simulation time 361039776 ps
CPU time 1.79 seconds
Started Mar 05 12:44:15 PM PST 24
Finished Mar 05 12:44:17 PM PST 24
Peak memory 203612 kb
Host smart-0e80de3e-2697-4174-bcaa-bf35ba8252bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087573449 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.3087573449
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all.2064097987
Short name T138
Test name
Test status
Simulation time 5411629420 ps
CPU time 6.04 seconds
Started Mar 05 12:44:01 PM PST 24
Finished Mar 05 12:44:07 PM PST 24
Peak memory 203928 kb
Host smart-256cd76d-5f97-49c2-957b-15e0a1004af0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064097987 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.2064097987
Directory /workspace/1.rv_dm_stress_all/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.2463822547
Short name T47
Test name
Test status
Simulation time 30210191 ps
CPU time 0.67 seconds
Started Mar 05 12:44:19 PM PST 24
Finished Mar 05 12:44:20 PM PST 24
Peak memory 203808 kb
Host smart-471fde7f-64e2-45e6-b7ca-513b7eed6add
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463822547 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.2463822547
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.744814012
Short name T241
Test name
Test status
Simulation time 503380555 ps
CPU time 3.15 seconds
Started Mar 05 12:44:31 PM PST 24
Finished Mar 05 12:44:34 PM PST 24
Peak memory 204088 kb
Host smart-4fc9313b-a1fe-46b3-863e-4778eff07f68
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=744814012 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_t
l_access.744814012
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.2132718438
Short name T230
Test name
Test status
Simulation time 4141083442 ps
CPU time 17.25 seconds
Started Mar 05 12:44:03 PM PST 24
Finished Mar 05 12:44:21 PM PST 24
Peak memory 204152 kb
Host smart-15293c96-c06a-4424-a0d9-8265fc87abe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132718438 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.2132718438
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.1138886878
Short name T150
Test name
Test status
Simulation time 35273687 ps
CPU time 0.63 seconds
Started Mar 05 12:44:23 PM PST 24
Finished Mar 05 12:44:24 PM PST 24
Peak memory 203756 kb
Host smart-d8503ba9-314b-440a-af8b-be48f5c27683
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138886878 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.1138886878
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.1880193941
Short name T20
Test name
Test status
Simulation time 6105560477 ps
CPU time 8.55 seconds
Started Mar 05 12:44:21 PM PST 24
Finished Mar 05 12:44:30 PM PST 24
Peak memory 204152 kb
Host smart-f686e133-0bd3-40f0-b1a9-173d1517d319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880193941 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.1880193941
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.1605410423
Short name T240
Test name
Test status
Simulation time 515430944 ps
CPU time 2.01 seconds
Started Mar 05 12:44:10 PM PST 24
Finished Mar 05 12:44:12 PM PST 24
Peak memory 204104 kb
Host smart-423b77a5-6c52-478c-8a81-1ad874b9dfa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605410423 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.1605410423
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.589155919
Short name T227
Test name
Test status
Simulation time 1812485883 ps
CPU time 7.24 seconds
Started Mar 05 12:44:25 PM PST 24
Finished Mar 05 12:44:32 PM PST 24
Peak memory 204132 kb
Host smart-bec828e4-d61c-4b55-a241-990683adf268
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=589155919 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_t
l_access.589155919
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.1153448372
Short name T219
Test name
Test status
Simulation time 556418365 ps
CPU time 2.45 seconds
Started Mar 05 12:44:10 PM PST 24
Finished Mar 05 12:44:12 PM PST 24
Peak memory 204300 kb
Host smart-b93d3182-424e-4ef2-970e-e8f3b4e2f011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153448372 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.1153448372
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.2438476725
Short name T30
Test name
Test status
Simulation time 41993207 ps
CPU time 0.65 seconds
Started Mar 05 12:44:10 PM PST 24
Finished Mar 05 12:44:11 PM PST 24
Peak memory 203700 kb
Host smart-cd229581-d697-47ab-97dd-806f9dd2b23a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438476725 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.2438476725
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.3347834834
Short name T187
Test name
Test status
Simulation time 23164643191 ps
CPU time 43.01 seconds
Started Mar 05 12:44:08 PM PST 24
Finished Mar 05 12:44:51 PM PST 24
Peak memory 204168 kb
Host smart-83959529-189c-4952-9ac2-d70af153dbd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347834834 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.3347834834
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.1122366993
Short name T217
Test name
Test status
Simulation time 1981262940 ps
CPU time 3.27 seconds
Started Mar 05 12:44:20 PM PST 24
Finished Mar 05 12:44:23 PM PST 24
Peak memory 204132 kb
Host smart-cb2acc4b-fb42-401f-9987-4a3b26b23e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122366993 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.1122366993
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.3424362385
Short name T185
Test name
Test status
Simulation time 2892933336 ps
CPU time 4.29 seconds
Started Mar 05 12:44:15 PM PST 24
Finished Mar 05 12:44:19 PM PST 24
Peak memory 204028 kb
Host smart-596853ae-dd57-4a64-8bcc-f647e3746975
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3424362385 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.3424362385
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.561597960
Short name T32
Test name
Test status
Simulation time 985036316 ps
CPU time 2.1 seconds
Started Mar 05 12:44:31 PM PST 24
Finished Mar 05 12:44:34 PM PST 24
Peak memory 204124 kb
Host smart-a99f7b43-f5ed-4b9a-a3b7-75ae88656bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561597960 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.561597960
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.2554402509
Short name T223
Test name
Test status
Simulation time 8441183409 ps
CPU time 20.44 seconds
Started Mar 05 12:44:20 PM PST 24
Finished Mar 05 12:44:41 PM PST 24
Peak memory 204280 kb
Host smart-ecf6932d-2d5e-4bf2-a75f-eedf5a396538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554402509 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.2554402509
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.291909900
Short name T238
Test name
Test status
Simulation time 4416092334 ps
CPU time 7.66 seconds
Started Mar 05 12:44:09 PM PST 24
Finished Mar 05 12:44:17 PM PST 24
Peak memory 204156 kb
Host smart-1ea7d74a-216f-4b06-a7bb-48f63c7d0e83
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=291909900 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_t
l_access.291909900
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.112558468
Short name T94
Test name
Test status
Simulation time 684583716 ps
CPU time 3.84 seconds
Started Mar 05 12:44:16 PM PST 24
Finished Mar 05 12:44:20 PM PST 24
Peak memory 204080 kb
Host smart-de5ec833-813a-4c65-a8aa-0595a26da879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112558468 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.112558468
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_stress_all.1636091440
Short name T24
Test name
Test status
Simulation time 1706985611 ps
CPU time 3 seconds
Started Mar 05 12:44:18 PM PST 24
Finished Mar 05 12:44:21 PM PST 24
Peak memory 203948 kb
Host smart-c150ddd2-eb0a-4bcb-890e-596f4faebbd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636091440 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.1636091440
Directory /workspace/13.rv_dm_stress_all/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.2087157615
Short name T158
Test name
Test status
Simulation time 19139726 ps
CPU time 0.65 seconds
Started Mar 05 12:44:21 PM PST 24
Finished Mar 05 12:44:22 PM PST 24
Peak memory 203748 kb
Host smart-bc79abaa-62c3-4d8a-9ca5-610b75ad15c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087157615 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.2087157615
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.3834517519
Short name T232
Test name
Test status
Simulation time 8038252982 ps
CPU time 19.18 seconds
Started Mar 05 12:44:14 PM PST 24
Finished Mar 05 12:44:34 PM PST 24
Peak memory 204152 kb
Host smart-5b9a12a2-f4b7-4bfb-aac9-80bd0e5a671c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834517519 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.3834517519
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.872963620
Short name T207
Test name
Test status
Simulation time 7760111941 ps
CPU time 14.19 seconds
Started Mar 05 12:44:50 PM PST 24
Finished Mar 05 12:45:04 PM PST 24
Peak memory 204004 kb
Host smart-0c615bd9-414e-433c-a72c-cf4e4e14e668
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=872963620 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_t
l_access.872963620
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.4204837117
Short name T205
Test name
Test status
Simulation time 448998706 ps
CPU time 1.9 seconds
Started Mar 05 12:44:23 PM PST 24
Finished Mar 05 12:44:25 PM PST 24
Peak memory 204092 kb
Host smart-d6958972-6173-4932-9803-4c77bcb66a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204837117 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.4204837117
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.2790301545
Short name T191
Test name
Test status
Simulation time 30107839 ps
CPU time 0.68 seconds
Started Mar 05 12:44:32 PM PST 24
Finished Mar 05 12:44:33 PM PST 24
Peak memory 203832 kb
Host smart-085593eb-c948-4867-8a14-5fb92e1aa294
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790301545 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.2790301545
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.1615896246
Short name T234
Test name
Test status
Simulation time 5678326151 ps
CPU time 10.82 seconds
Started Mar 05 12:44:25 PM PST 24
Finished Mar 05 12:44:36 PM PST 24
Peak memory 204148 kb
Host smart-f650927d-4bd5-4066-8e9e-9d1549b22b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615896246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.1615896246
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.1067256556
Short name T179
Test name
Test status
Simulation time 10458585685 ps
CPU time 23.55 seconds
Started Mar 05 12:44:27 PM PST 24
Finished Mar 05 12:44:51 PM PST 24
Peak memory 204152 kb
Host smart-2fe7bfd0-bcc0-4927-ae36-3afa00be32c2
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1067256556 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_
tl_access.1067256556
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.3440016774
Short name T177
Test name
Test status
Simulation time 7010589118 ps
CPU time 9.9 seconds
Started Mar 05 12:44:16 PM PST 24
Finished Mar 05 12:44:26 PM PST 24
Peak memory 204220 kb
Host smart-b7957ee8-1a5b-4248-98e9-9eff92ceda71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440016774 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.3440016774
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_stress_all.1662778551
Short name T14
Test name
Test status
Simulation time 1667818144 ps
CPU time 7.03 seconds
Started Mar 05 12:44:30 PM PST 24
Finished Mar 05 12:44:37 PM PST 24
Peak memory 203968 kb
Host smart-3d7d5aa8-0ec7-4226-8894-6a619ef70a5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662778551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.1662778551
Directory /workspace/15.rv_dm_stress_all/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.3202588919
Short name T157
Test name
Test status
Simulation time 19226383 ps
CPU time 0.63 seconds
Started Mar 05 12:44:22 PM PST 24
Finished Mar 05 12:44:23 PM PST 24
Peak memory 203748 kb
Host smart-b42dda50-7541-4aff-b05f-80624e09b5c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202588919 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.3202588919
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.2444734860
Short name T121
Test name
Test status
Simulation time 3688673841 ps
CPU time 6.7 seconds
Started Mar 05 12:44:26 PM PST 24
Finished Mar 05 12:44:33 PM PST 24
Peak memory 204044 kb
Host smart-c990617d-9f57-4b09-8b7b-2e83d5495fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444734860 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.2444734860
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.3866318968
Short name T71
Test name
Test status
Simulation time 2594662560 ps
CPU time 7.07 seconds
Started Mar 05 12:44:32 PM PST 24
Finished Mar 05 12:44:39 PM PST 24
Peak memory 204156 kb
Host smart-2a2e0434-cea2-4f32-877f-ffd919516443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866318968 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.3866318968
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.634432981
Short name T195
Test name
Test status
Simulation time 1848639781 ps
CPU time 6.95 seconds
Started Mar 05 12:44:15 PM PST 24
Finished Mar 05 12:44:22 PM PST 24
Peak memory 204048 kb
Host smart-ecae64ad-d9dc-48ba-9dcf-df726b767b2a
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=634432981 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_t
l_access.634432981
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.2748136724
Short name T73
Test name
Test status
Simulation time 1645312284 ps
CPU time 3.27 seconds
Started Mar 05 12:44:12 PM PST 24
Finished Mar 05 12:44:16 PM PST 24
Peak memory 204104 kb
Host smart-2103f186-27f1-4881-a1c7-85a056e131ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748136724 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.2748136724
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.1771872291
Short name T212
Test name
Test status
Simulation time 15257642 ps
CPU time 0.65 seconds
Started Mar 05 12:44:35 PM PST 24
Finished Mar 05 12:44:36 PM PST 24
Peak memory 203744 kb
Host smart-2c79e269-5978-4471-8141-496a66ccd09a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771872291 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.1771872291
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.645758566
Short name T215
Test name
Test status
Simulation time 3141285671 ps
CPU time 10.35 seconds
Started Mar 05 12:44:33 PM PST 24
Finished Mar 05 12:44:44 PM PST 24
Peak memory 204112 kb
Host smart-7a9439a2-6543-45bb-8377-311d55c18b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645758566 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.645758566
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.173224285
Short name T204
Test name
Test status
Simulation time 485042248 ps
CPU time 2.28 seconds
Started Mar 05 12:44:31 PM PST 24
Finished Mar 05 12:44:34 PM PST 24
Peak memory 204088 kb
Host smart-fb77901d-71a4-4c3d-9cfd-29ccdd4811c1
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=173224285 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_t
l_access.173224285
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.174025288
Short name T69
Test name
Test status
Simulation time 14943003630 ps
CPU time 27.87 seconds
Started Mar 05 12:44:40 PM PST 24
Finished Mar 05 12:45:08 PM PST 24
Peak memory 204220 kb
Host smart-e72e06e1-214d-4f9a-9d42-04fd4924ba46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174025288 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.174025288
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_stress_all.2829412242
Short name T64
Test name
Test status
Simulation time 2777071960 ps
CPU time 3 seconds
Started Mar 05 12:44:38 PM PST 24
Finished Mar 05 12:44:41 PM PST 24
Peak memory 204076 kb
Host smart-94ab5e13-059b-4fac-a694-7c24bfba55c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829412242 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.2829412242
Directory /workspace/17.rv_dm_stress_all/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.3664143939
Short name T152
Test name
Test status
Simulation time 26431361 ps
CPU time 0.7 seconds
Started Mar 05 12:44:34 PM PST 24
Finished Mar 05 12:44:34 PM PST 24
Peak memory 203828 kb
Host smart-1ead1dad-ec16-4086-bfe7-07c7ca3fc5e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664143939 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.3664143939
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.478388407
Short name T3
Test name
Test status
Simulation time 1648443175 ps
CPU time 5.61 seconds
Started Mar 05 12:44:33 PM PST 24
Finished Mar 05 12:44:39 PM PST 24
Peak memory 203980 kb
Host smart-bf909c24-5cc1-409f-bdad-8129c56d6c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478388407 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.478388407
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.3741158888
Short name T178
Test name
Test status
Simulation time 4659879789 ps
CPU time 17.78 seconds
Started Mar 05 12:44:43 PM PST 24
Finished Mar 05 12:45:01 PM PST 24
Peak memory 204144 kb
Host smart-3f718260-9859-4a05-b064-e8572708a6e3
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3741158888 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_
tl_access.3741158888
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.2630096960
Short name T203
Test name
Test status
Simulation time 2867108729 ps
CPU time 6.21 seconds
Started Mar 05 12:44:36 PM PST 24
Finished Mar 05 12:44:42 PM PST 24
Peak memory 204160 kb
Host smart-05162c24-1302-4cfa-a515-4eaae53637c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630096960 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.2630096960
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.2112844603
Short name T148
Test name
Test status
Simulation time 17127170 ps
CPU time 0.67 seconds
Started Mar 05 12:44:54 PM PST 24
Finished Mar 05 12:44:55 PM PST 24
Peak memory 203724 kb
Host smart-bad5dd66-577a-402a-ba56-b20942c6951a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112844603 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.2112844603
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.817096762
Short name T74
Test name
Test status
Simulation time 3996335346 ps
CPU time 8.43 seconds
Started Mar 05 12:44:57 PM PST 24
Finished Mar 05 12:45:05 PM PST 24
Peak memory 204152 kb
Host smart-c9f88ab0-f2fd-4416-ba6f-67486b4ca93b
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=817096762 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_t
l_access.817096762
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.497579791
Short name T190
Test name
Test status
Simulation time 4954177756 ps
CPU time 5.66 seconds
Started Mar 05 12:44:44 PM PST 24
Finished Mar 05 12:44:55 PM PST 24
Peak memory 204144 kb
Host smart-be55eae3-2ccc-41d3-ba4f-f277c0ddfcd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497579791 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.497579791
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.2814945460
Short name T51
Test name
Test status
Simulation time 58548441 ps
CPU time 0.68 seconds
Started Mar 05 12:44:00 PM PST 24
Finished Mar 05 12:44:01 PM PST 24
Peak memory 203672 kb
Host smart-e6f44ac4-7e4b-41c5-8001-0a336812de3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814945460 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.2814945460
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.3856126243
Short name T236
Test name
Test status
Simulation time 24987944908 ps
CPU time 23.71 seconds
Started Mar 05 12:44:22 PM PST 24
Finished Mar 05 12:44:46 PM PST 24
Peak memory 204040 kb
Host smart-877dcf40-9297-4fd3-ae93-9f61c58305cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856126243 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.3856126243
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.3995301309
Short name T192
Test name
Test status
Simulation time 1077419506 ps
CPU time 4.49 seconds
Started Mar 05 12:44:12 PM PST 24
Finished Mar 05 12:44:16 PM PST 24
Peak memory 204136 kb
Host smart-94541c5f-39a0-44a6-93e7-c4ba33119109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995301309 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.3995301309
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.13908133
Short name T174
Test name
Test status
Simulation time 3112073820 ps
CPU time 10.26 seconds
Started Mar 05 12:44:11 PM PST 24
Finished Mar 05 12:44:21 PM PST 24
Peak memory 204152 kb
Host smart-fd975ea1-890b-4349-aad5-3f2c66b2d39f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=13908133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_tl_
access.13908133
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.204333674
Short name T202
Test name
Test status
Simulation time 61903818 ps
CPU time 0.72 seconds
Started Mar 05 12:44:05 PM PST 24
Finished Mar 05 12:44:06 PM PST 24
Peak memory 203428 kb
Host smart-910319cd-c49b-4a8f-9666-8fb48b49e2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204333674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.204333674
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.1637663968
Short name T233
Test name
Test status
Simulation time 2630823325 ps
CPU time 3.55 seconds
Started Mar 05 12:44:10 PM PST 24
Finished Mar 05 12:44:13 PM PST 24
Peak memory 204032 kb
Host smart-836c6556-ca31-4a23-bf66-6e99c605ef35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637663968 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.1637663968
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.1966575630
Short name T35
Test name
Test status
Simulation time 320089045 ps
CPU time 1.25 seconds
Started Mar 05 12:44:24 PM PST 24
Finished Mar 05 12:44:25 PM PST 24
Peak memory 219584 kb
Host smart-a4aed023-12bf-49a6-bb0b-c43186dae329
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966575630 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.1966575630
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.1675917392
Short name T45
Test name
Test status
Simulation time 54268001 ps
CPU time 0.67 seconds
Started Mar 05 12:44:41 PM PST 24
Finished Mar 05 12:44:42 PM PST 24
Peak memory 203704 kb
Host smart-9b125606-f321-4fa9-9cd0-4b2031400947
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675917392 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.1675917392
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.115762178
Short name T182
Test name
Test status
Simulation time 26490528 ps
CPU time 0.72 seconds
Started Mar 05 12:44:33 PM PST 24
Finished Mar 05 12:44:33 PM PST 24
Peak memory 203796 kb
Host smart-62142055-b0a8-434b-a841-ecc7107b406b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115762178 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.115762178
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_stress_all.3899146668
Short name T19
Test name
Test status
Simulation time 1959092463 ps
CPU time 6.8 seconds
Started Mar 05 12:44:39 PM PST 24
Finished Mar 05 12:44:45 PM PST 24
Peak memory 203892 kb
Host smart-76152056-8ff5-4b68-88b1-18e52d88e95e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899146668 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.3899146668
Directory /workspace/21.rv_dm_stress_all/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.1107491651
Short name T49
Test name
Test status
Simulation time 20230271 ps
CPU time 0.65 seconds
Started Mar 05 12:44:36 PM PST 24
Finished Mar 05 12:44:42 PM PST 24
Peak memory 203796 kb
Host smart-1cab0a3b-cb63-480f-b3a9-7b18ba3389d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107491651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.1107491651
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.2374385390
Short name T144
Test name
Test status
Simulation time 29669939 ps
CPU time 0.66 seconds
Started Mar 05 12:44:35 PM PST 24
Finished Mar 05 12:44:36 PM PST 24
Peak memory 203848 kb
Host smart-f0fd15f5-0211-453c-8c7c-00a5bcb348d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374385390 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.2374385390
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.1240796583
Short name T48
Test name
Test status
Simulation time 27740819 ps
CPU time 0.66 seconds
Started Mar 05 12:44:37 PM PST 24
Finished Mar 05 12:44:38 PM PST 24
Peak memory 203960 kb
Host smart-c32c02c7-fc01-4e1a-9e8a-52443ce9d11c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240796583 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.1240796583
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.3447448070
Short name T188
Test name
Test status
Simulation time 17299145 ps
CPU time 0.65 seconds
Started Mar 05 12:44:47 PM PST 24
Finished Mar 05 12:44:48 PM PST 24
Peak memory 203716 kb
Host smart-32757dd7-796b-49fb-b56e-4373207496e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447448070 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.3447448070
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.504156414
Short name T199
Test name
Test status
Simulation time 78000081 ps
CPU time 0.64 seconds
Started Mar 05 12:44:26 PM PST 24
Finished Mar 05 12:44:27 PM PST 24
Peak memory 203720 kb
Host smart-33ee41ea-8458-467e-b2b5-9b95a3fb9598
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504156414 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.504156414
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.2037562793
Short name T197
Test name
Test status
Simulation time 108025375 ps
CPU time 0.64 seconds
Started Mar 05 12:44:39 PM PST 24
Finished Mar 05 12:44:39 PM PST 24
Peak memory 203828 kb
Host smart-b923b66a-f119-4f8f-bdd1-abfba58dbff5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037562793 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.2037562793
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_stress_all.1705412098
Short name T61
Test name
Test status
Simulation time 3429816715 ps
CPU time 6.35 seconds
Started Mar 05 12:44:40 PM PST 24
Finished Mar 05 12:44:46 PM PST 24
Peak memory 204032 kb
Host smart-e33f6406-bd28-4611-98b7-9fbe6afbfc21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705412098 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.1705412098
Directory /workspace/27.rv_dm_stress_all/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.158135251
Short name T222
Test name
Test status
Simulation time 20620704 ps
CPU time 0.67 seconds
Started Mar 05 12:44:39 PM PST 24
Finished Mar 05 12:44:40 PM PST 24
Peak memory 203828 kb
Host smart-8bd4b49a-1cf3-4aab-9560-7fef64a8436f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158135251 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.158135251
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.3315602276
Short name T72
Test name
Test status
Simulation time 16600303 ps
CPU time 0.64 seconds
Started Mar 05 12:44:26 PM PST 24
Finished Mar 05 12:44:32 PM PST 24
Peak memory 203832 kb
Host smart-c2f417a0-968f-4044-90fa-a317c3186f12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315602276 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.3315602276
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.4167049609
Short name T213
Test name
Test status
Simulation time 49944231793 ps
CPU time 66.98 seconds
Started Mar 05 12:44:13 PM PST 24
Finished Mar 05 12:45:20 PM PST 24
Peak memory 204196 kb
Host smart-f8e4f1b1-f522-49e9-a2fc-ca548872ead1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167049609 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.4167049609
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.1279014640
Short name T70
Test name
Test status
Simulation time 5647001540 ps
CPU time 8.41 seconds
Started Mar 05 12:44:11 PM PST 24
Finished Mar 05 12:44:19 PM PST 24
Peak memory 203988 kb
Host smart-c8f9598b-e947-4411-84f2-2e14dda1f5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279014640 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.1279014640
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.2576284851
Short name T211
Test name
Test status
Simulation time 8204086779 ps
CPU time 16.68 seconds
Started Mar 05 12:43:52 PM PST 24
Finished Mar 05 12:44:08 PM PST 24
Peak memory 204220 kb
Host smart-61832bb3-9821-4bf7-8855-cb2c487b6958
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2576284851 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.2576284851
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.501627845
Short name T11
Test name
Test status
Simulation time 74799390 ps
CPU time 0.72 seconds
Started Mar 05 12:44:19 PM PST 24
Finished Mar 05 12:44:20 PM PST 24
Peak memory 203744 kb
Host smart-4baab1a3-36a8-4dc3-a2a5-1196952caf72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501627845 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.501627845
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.2706572837
Short name T175
Test name
Test status
Simulation time 4919700620 ps
CPU time 5.18 seconds
Started Mar 05 12:44:04 PM PST 24
Finished Mar 05 12:44:10 PM PST 24
Peak memory 204144 kb
Host smart-5241d626-8362-4541-98c0-d2a61e16e8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706572837 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.2706572837
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.2087053850
Short name T68
Test name
Test status
Simulation time 227385643 ps
CPU time 1.17 seconds
Started Mar 05 12:44:24 PM PST 24
Finished Mar 05 12:44:25 PM PST 24
Peak memory 219912 kb
Host smart-ccf05c8c-effd-47e9-ad97-4dfae15de4ff
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087053850 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.2087053850
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.763191490
Short name T206
Test name
Test status
Simulation time 16193215 ps
CPU time 0.69 seconds
Started Mar 05 12:44:46 PM PST 24
Finished Mar 05 12:44:47 PM PST 24
Peak memory 203844 kb
Host smart-c4c59a79-8fa0-48f5-a1c2-aae92c72d61e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763191490 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.763191490
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.2077178088
Short name T161
Test name
Test status
Simulation time 30249352 ps
CPU time 0.65 seconds
Started Mar 05 12:44:32 PM PST 24
Finished Mar 05 12:44:33 PM PST 24
Peak memory 203848 kb
Host smart-70a45753-5947-4a6e-bfc2-bb027b7dea54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077178088 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.2077178088
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.2812859449
Short name T85
Test name
Test status
Simulation time 50131220 ps
CPU time 0.69 seconds
Started Mar 05 12:44:32 PM PST 24
Finished Mar 05 12:44:33 PM PST 24
Peak memory 203824 kb
Host smart-5ce92cd0-fe8f-43dd-bd19-9eccefa57892
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812859449 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.2812859449
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.4127757179
Short name T31
Test name
Test status
Simulation time 15068721 ps
CPU time 0.63 seconds
Started Mar 05 12:44:29 PM PST 24
Finished Mar 05 12:44:32 PM PST 24
Peak memory 203828 kb
Host smart-20df1eea-09c2-4e65-89e3-0ff79908f662
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127757179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.4127757179
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.3993402153
Short name T142
Test name
Test status
Simulation time 17925315 ps
CPU time 0.65 seconds
Started Mar 05 12:44:34 PM PST 24
Finished Mar 05 12:44:34 PM PST 24
Peak memory 203828 kb
Host smart-62f00bf1-6728-4fc0-8ba3-960ce67e1eb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993402153 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.3993402153
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.3666668337
Short name T160
Test name
Test status
Simulation time 59647986 ps
CPU time 0.65 seconds
Started Mar 05 12:44:26 PM PST 24
Finished Mar 05 12:44:27 PM PST 24
Peak memory 203832 kb
Host smart-45781320-0719-4ab7-8845-b91ac4c14ae9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666668337 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.3666668337
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_stress_all.3582378023
Short name T63
Test name
Test status
Simulation time 6936166453 ps
CPU time 11.89 seconds
Started Mar 05 12:44:38 PM PST 24
Finished Mar 05 12:44:50 PM PST 24
Peak memory 204032 kb
Host smart-dd361e5f-353c-4d99-b829-138f5899ce8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582378023 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.3582378023
Directory /workspace/35.rv_dm_stress_all/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.968507076
Short name T118
Test name
Test status
Simulation time 55436320 ps
CPU time 0.65 seconds
Started Mar 05 12:44:31 PM PST 24
Finished Mar 05 12:44:31 PM PST 24
Peak memory 203784 kb
Host smart-83828450-5299-4a96-9aad-786950aa85b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968507076 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.968507076
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.345123609
Short name T208
Test name
Test status
Simulation time 50077838 ps
CPU time 0.67 seconds
Started Mar 05 12:44:52 PM PST 24
Finished Mar 05 12:44:53 PM PST 24
Peak memory 203784 kb
Host smart-139c326e-aa76-46f1-853e-6c9e51291a04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345123609 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.345123609
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.2379765959
Short name T196
Test name
Test status
Simulation time 61018956 ps
CPU time 0.64 seconds
Started Mar 05 12:44:20 PM PST 24
Finished Mar 05 12:44:21 PM PST 24
Peak memory 203704 kb
Host smart-374ad123-9776-4716-910c-2754acaee035
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379765959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.2379765959
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_stress_all.3219446606
Short name T62
Test name
Test status
Simulation time 1753400295 ps
CPU time 4.46 seconds
Started Mar 05 12:44:25 PM PST 24
Finished Mar 05 12:44:29 PM PST 24
Peak memory 203928 kb
Host smart-20bfb137-3145-4662-a6ed-93952914fc0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219446606 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.3219446606
Directory /workspace/38.rv_dm_stress_all/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.2942583573
Short name T46
Test name
Test status
Simulation time 44392112 ps
CPU time 0.64 seconds
Started Mar 05 12:44:49 PM PST 24
Finished Mar 05 12:44:50 PM PST 24
Peak memory 203720 kb
Host smart-1362eecd-ce73-425b-8644-bc8745d6de82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942583573 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.2942583573
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.3782777492
Short name T165
Test name
Test status
Simulation time 42995806 ps
CPU time 0.67 seconds
Started Mar 05 12:44:08 PM PST 24
Finished Mar 05 12:44:09 PM PST 24
Peak memory 203828 kb
Host smart-170b15f9-5bcd-497d-9e12-00b72b76b3b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782777492 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.3782777492
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.3372314063
Short name T194
Test name
Test status
Simulation time 2299108428 ps
CPU time 5.59 seconds
Started Mar 05 12:44:31 PM PST 24
Finished Mar 05 12:44:36 PM PST 24
Peak memory 204124 kb
Host smart-5eb141b3-c57a-4d5a-a1d4-09cbf4c0e140
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3372314063 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.3372314063
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.1603604360
Short name T239
Test name
Test status
Simulation time 37637709 ps
CPU time 0.69 seconds
Started Mar 05 12:44:15 PM PST 24
Finished Mar 05 12:44:16 PM PST 24
Peak memory 203736 kb
Host smart-e29408ed-2f37-4f65-b01f-ce5a266d64d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603604360 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.1603604360
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.329071388
Short name T171
Test name
Test status
Simulation time 3985257670 ps
CPU time 7.36 seconds
Started Mar 05 12:44:13 PM PST 24
Finished Mar 05 12:44:20 PM PST 24
Peak memory 204152 kb
Host smart-ef1d96b6-f163-443d-b3d2-ff38da8172e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329071388 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.329071388
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.624550340
Short name T36
Test name
Test status
Simulation time 619969668 ps
CPU time 1.13 seconds
Started Mar 05 12:44:33 PM PST 24
Finished Mar 05 12:44:35 PM PST 24
Peak memory 219804 kb
Host smart-ab4cf5c0-e6a7-4b23-8baa-f3f283ed11e2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624550340 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.624550340
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.709418756
Short name T218
Test name
Test status
Simulation time 104506010 ps
CPU time 0.65 seconds
Started Mar 05 12:44:47 PM PST 24
Finished Mar 05 12:44:47 PM PST 24
Peak memory 203836 kb
Host smart-021bedb9-6bac-46a5-b6be-96b15c7ced37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709418756 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.709418756
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.2915193045
Short name T170
Test name
Test status
Simulation time 51171752 ps
CPU time 0.67 seconds
Started Mar 05 12:44:55 PM PST 24
Finished Mar 05 12:44:56 PM PST 24
Peak memory 203828 kb
Host smart-a5fbbff0-9cd2-461f-a725-e93ce11f7ac8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915193045 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.2915193045
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.833298109
Short name T162
Test name
Test status
Simulation time 22052744 ps
CPU time 0.68 seconds
Started Mar 05 12:44:50 PM PST 24
Finished Mar 05 12:44:55 PM PST 24
Peak memory 203828 kb
Host smart-5d7cfa4d-3e96-4bf7-9c6f-6adbd8c3c07a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833298109 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.833298109
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.1169588678
Short name T154
Test name
Test status
Simulation time 29064766 ps
CPU time 0.69 seconds
Started Mar 05 12:44:51 PM PST 24
Finished Mar 05 12:44:55 PM PST 24
Peak memory 203800 kb
Host smart-7e062c08-5b52-4db9-b337-850c3d3e1945
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169588678 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.1169588678
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_stress_all.505491830
Short name T13
Test name
Test status
Simulation time 6165845037 ps
CPU time 5.59 seconds
Started Mar 05 12:44:38 PM PST 24
Finished Mar 05 12:44:43 PM PST 24
Peak memory 204088 kb
Host smart-703a8525-38b5-47ae-a5b8-d49bd05afbc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505491830 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.505491830
Directory /workspace/43.rv_dm_stress_all/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.1583865655
Short name T145
Test name
Test status
Simulation time 19341196 ps
CPU time 0.66 seconds
Started Mar 05 12:44:37 PM PST 24
Finished Mar 05 12:44:43 PM PST 24
Peak memory 203832 kb
Host smart-f51a5170-2907-434b-b1d4-4ba3de4e8d71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583865655 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.1583865655
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.1544822026
Short name T166
Test name
Test status
Simulation time 53371269 ps
CPU time 0.66 seconds
Started Mar 05 12:44:39 PM PST 24
Finished Mar 05 12:44:40 PM PST 24
Peak memory 203836 kb
Host smart-bb4ac62b-8c69-4ddb-9877-ab896022568c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544822026 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.1544822026
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.3757091824
Short name T141
Test name
Test status
Simulation time 33001473 ps
CPU time 0.7 seconds
Started Mar 05 12:44:49 PM PST 24
Finished Mar 05 12:44:49 PM PST 24
Peak memory 203788 kb
Host smart-313e0f3f-bbbb-4493-ae53-49ffd5fc67f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757091824 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.3757091824
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.1416217967
Short name T167
Test name
Test status
Simulation time 32659207 ps
CPU time 0.62 seconds
Started Mar 05 12:44:51 PM PST 24
Finished Mar 05 12:44:51 PM PST 24
Peak memory 203828 kb
Host smart-ac0d4422-21b2-4828-84aa-047e3586b6ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416217967 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.1416217967
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.3045517185
Short name T159
Test name
Test status
Simulation time 40980215 ps
CPU time 0.63 seconds
Started Mar 05 12:44:47 PM PST 24
Finished Mar 05 12:44:48 PM PST 24
Peak memory 203820 kb
Host smart-f3475eb6-85a3-42e5-9b37-9172d85d459c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045517185 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.3045517185
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.1864089356
Short name T146
Test name
Test status
Simulation time 85092360 ps
CPU time 0.64 seconds
Started Mar 05 12:44:41 PM PST 24
Finished Mar 05 12:44:42 PM PST 24
Peak memory 202472 kb
Host smart-6190d447-3d69-4f8e-907a-95d6e398b256
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864089356 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.1864089356
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.2557585778
Short name T21
Test name
Test status
Simulation time 12938366018 ps
CPU time 21.91 seconds
Started Mar 05 12:44:20 PM PST 24
Finished Mar 05 12:44:42 PM PST 24
Peak memory 204076 kb
Host smart-cfa8634a-8205-4bed-9e7b-ed554b3c632b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557585778 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.2557585778
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.1299303247
Short name T210
Test name
Test status
Simulation time 5284830012 ps
CPU time 7.09 seconds
Started Mar 05 12:44:12 PM PST 24
Finished Mar 05 12:44:19 PM PST 24
Peak memory 204172 kb
Host smart-3f3d598c-dbdb-4427-b58d-b6c8acbebd0c
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1299303247 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t
l_access.1299303247
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.1852562823
Short name T180
Test name
Test status
Simulation time 1708791832 ps
CPU time 4.88 seconds
Started Mar 05 12:44:17 PM PST 24
Finished Mar 05 12:44:22 PM PST 24
Peak memory 204080 kb
Host smart-0497aeaf-8f4f-49a0-a106-0b2aeea76064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852562823 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.1852562823
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.1898752824
Short name T149
Test name
Test status
Simulation time 48648769 ps
CPU time 0.72 seconds
Started Mar 05 12:44:31 PM PST 24
Finished Mar 05 12:44:31 PM PST 24
Peak memory 203956 kb
Host smart-96129226-dbb5-49dc-8f0d-368f35772e07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898752824 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.1898752824
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.2108028566
Short name T220
Test name
Test status
Simulation time 1015906751 ps
CPU time 3.03 seconds
Started Mar 05 12:44:30 PM PST 24
Finished Mar 05 12:44:33 PM PST 24
Peak memory 204088 kb
Host smart-e3d85c5b-719b-4386-a52c-91701b34fabd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108028566 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.2108028566
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.1985251
Short name T225
Test name
Test status
Simulation time 3068733589 ps
CPU time 11.38 seconds
Started Mar 05 12:44:26 PM PST 24
Finished Mar 05 12:44:37 PM PST 24
Peak memory 204160 kb
Host smart-399e1d03-3d81-4526-ad6e-723a05451306
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1985251 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_tl_a
ccess.1985251
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.314053890
Short name T201
Test name
Test status
Simulation time 1852448200 ps
CPU time 5.84 seconds
Started Mar 05 12:44:04 PM PST 24
Finished Mar 05 12:44:10 PM PST 24
Peak memory 204048 kb
Host smart-ba64f4cc-61c2-44c7-9cc2-3b27958f984b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314053890 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.314053890
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.3427883750
Short name T143
Test name
Test status
Simulation time 27530467 ps
CPU time 0.64 seconds
Started Mar 05 12:44:10 PM PST 24
Finished Mar 05 12:44:10 PM PST 24
Peak memory 203840 kb
Host smart-c5f1ffd4-e6cd-4558-a2f0-2f5753135418
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427883750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.3427883750
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.1007369137
Short name T214
Test name
Test status
Simulation time 5256668040 ps
CPU time 5.19 seconds
Started Mar 05 12:44:23 PM PST 24
Finished Mar 05 12:44:28 PM PST 24
Peak memory 204156 kb
Host smart-61f30ad1-1559-4c2e-8fa4-c51dc8cf7cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007369137 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.1007369137
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.1017727317
Short name T226
Test name
Test status
Simulation time 358345821 ps
CPU time 1.57 seconds
Started Mar 05 12:44:11 PM PST 24
Finished Mar 05 12:44:13 PM PST 24
Peak memory 204132 kb
Host smart-346e10d9-2b41-4534-b648-84ed942d1299
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1017727317 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.1017727317
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.3353039205
Short name T228
Test name
Test status
Simulation time 6549373222 ps
CPU time 15.15 seconds
Started Mar 05 12:44:19 PM PST 24
Finished Mar 05 12:44:34 PM PST 24
Peak memory 204164 kb
Host smart-bf584586-e63a-44c2-919b-d60e81ff1431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353039205 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.3353039205
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.2779448176
Short name T224
Test name
Test status
Simulation time 15210738 ps
CPU time 0.64 seconds
Started Mar 05 12:44:22 PM PST 24
Finished Mar 05 12:44:23 PM PST 24
Peak memory 203720 kb
Host smart-78720761-e397-431c-99fb-4325ef1b3493
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779448176 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.2779448176
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.1754955773
Short name T44
Test name
Test status
Simulation time 9260784797 ps
CPU time 16 seconds
Started Mar 05 12:44:23 PM PST 24
Finished Mar 05 12:44:39 PM PST 24
Peak memory 204156 kb
Host smart-9cf06329-5847-4435-9dba-048976ebf614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754955773 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.1754955773
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.1567751013
Short name T33
Test name
Test status
Simulation time 4138872312 ps
CPU time 16.38 seconds
Started Mar 05 12:44:21 PM PST 24
Finished Mar 05 12:44:38 PM PST 24
Peak memory 204036 kb
Host smart-0d6faaa3-9fc8-4eed-84c2-0314281e8636
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1567751013 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t
l_access.1567751013
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.1033529721
Short name T184
Test name
Test status
Simulation time 11776939860 ps
CPU time 37.49 seconds
Started Mar 05 12:44:19 PM PST 24
Finished Mar 05 12:45:01 PM PST 24
Peak memory 204168 kb
Host smart-c14c443c-eb16-48d5-9ee4-08b0f9408484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033529721 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.1033529721
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_stress_all.2938833899
Short name T5
Test name
Test status
Simulation time 2605748704 ps
CPU time 5.28 seconds
Started Mar 05 12:44:17 PM PST 24
Finished Mar 05 12:44:22 PM PST 24
Peak memory 204052 kb
Host smart-88d489f5-7847-4101-a519-3f95afad2b34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938833899 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.2938833899
Directory /workspace/8.rv_dm_stress_all/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.986766005
Short name T163
Test name
Test status
Simulation time 41390753 ps
CPU time 0.75 seconds
Started Mar 05 12:44:26 PM PST 24
Finished Mar 05 12:44:26 PM PST 24
Peak memory 203832 kb
Host smart-272897ed-600b-408b-808f-1751eca0cd5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986766005 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.986766005
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.1138430771
Short name T221
Test name
Test status
Simulation time 8256870577 ps
CPU time 10.61 seconds
Started Mar 05 12:44:23 PM PST 24
Finished Mar 05 12:44:34 PM PST 24
Peak memory 204120 kb
Host smart-e4c9c0fb-504d-4392-8f98-b82bce345f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138430771 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.1138430771
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.309002477
Short name T231
Test name
Test status
Simulation time 3277113254 ps
CPU time 14.06 seconds
Started Mar 05 12:44:29 PM PST 24
Finished Mar 05 12:44:44 PM PST 24
Peak memory 204144 kb
Host smart-00dafc8c-fd30-417b-b242-6635c0ef61d1
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=309002477 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_tl
_access.309002477
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.1515593172
Short name T176
Test name
Test status
Simulation time 533630228 ps
CPU time 1.94 seconds
Started Mar 05 12:44:24 PM PST 24
Finished Mar 05 12:44:26 PM PST 24
Peak memory 204084 kb
Host smart-db154a98-f985-4f64-a662-680fbc4dae27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515593172 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.1515593172
Directory /workspace/9.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_stress_all.4151057177
Short name T4
Test name
Test status
Simulation time 4080025510 ps
CPU time 4.12 seconds
Started Mar 05 12:44:16 PM PST 24
Finished Mar 05 12:44:21 PM PST 24
Peak memory 203952 kb
Host smart-b36a139a-fed5-4748-a5c4-c4f020224b5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151057177 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.4151057177
Directory /workspace/9.rv_dm_stress_all/latest
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