Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
87.72 92.87 78.76 89.36 76.92 83.07 97.75 95.34


Total test records in report: 383
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T278 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.3731157605 Mar 07 01:00:03 PM PST 24 Mar 07 01:00:04 PM PST 24 50474810 ps
T121 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.3125158426 Mar 07 01:00:01 PM PST 24 Mar 07 01:00:20 PM PST 24 3071801963 ps
T95 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.1084014438 Mar 07 12:59:56 PM PST 24 Mar 07 01:00:01 PM PST 24 924431588 ps
T279 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.2024053220 Mar 07 12:59:58 PM PST 24 Mar 07 01:00:02 PM PST 24 150805878 ps
T280 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.4171119234 Mar 07 01:00:07 PM PST 24 Mar 07 01:00:08 PM PST 24 822896291 ps
T281 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.2545367288 Mar 07 12:59:46 PM PST 24 Mar 07 12:59:50 PM PST 24 252137696 ps
T282 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.1514144246 Mar 07 12:59:48 PM PST 24 Mar 07 12:59:54 PM PST 24 84712647 ps
T283 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.830921353 Mar 07 12:59:43 PM PST 24 Mar 07 01:00:51 PM PST 24 12858477759 ps
T284 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.1707290767 Mar 07 12:59:52 PM PST 24 Mar 07 12:59:53 PM PST 24 93306415 ps
T285 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1995782351 Mar 07 12:59:50 PM PST 24 Mar 07 01:02:05 PM PST 24 44184714645 ps
T286 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.4156024203 Mar 07 12:59:53 PM PST 24 Mar 07 12:59:56 PM PST 24 227140943 ps
T98 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1421360575 Mar 07 12:59:37 PM PST 24 Mar 07 01:00:08 PM PST 24 8184544711 ps
T287 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.2476580549 Mar 07 12:59:43 PM PST 24 Mar 07 12:59:48 PM PST 24 992745528 ps
T130 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2743686802 Mar 07 01:00:06 PM PST 24 Mar 07 01:00:16 PM PST 24 942616581 ps
T124 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2654676336 Mar 07 01:00:00 PM PST 24 Mar 07 01:00:09 PM PST 24 781089150 ps
T288 /workspace/coverage/cover_reg_top/32.rv_dm_tap_fsm_rand_reset.2907345074 Mar 07 01:00:00 PM PST 24 Mar 07 01:00:17 PM PST 24 7817370752 ps
T289 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.4290983696 Mar 07 12:59:58 PM PST 24 Mar 07 01:00:03 PM PST 24 409839219 ps
T290 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.1906153910 Mar 07 12:59:47 PM PST 24 Mar 07 01:00:01 PM PST 24 6349598279 ps
T291 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.3777802532 Mar 07 12:59:54 PM PST 24 Mar 07 12:59:55 PM PST 24 42583925 ps
T292 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3935581562 Mar 07 12:59:44 PM PST 24 Mar 07 12:59:45 PM PST 24 87150773 ps
T99 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.3374691724 Mar 07 12:59:42 PM PST 24 Mar 07 01:00:50 PM PST 24 19369667739 ps
T293 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.3998544764 Mar 07 01:00:04 PM PST 24 Mar 07 01:00:07 PM PST 24 169112253 ps
T294 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.54273132 Mar 07 12:59:46 PM PST 24 Mar 07 12:59:48 PM PST 24 38795513 ps
T295 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.708175565 Mar 07 12:59:44 PM PST 24 Mar 07 12:59:45 PM PST 24 196151970 ps
T296 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1464910753 Mar 07 12:59:44 PM PST 24 Mar 07 12:59:45 PM PST 24 46121822 ps
T297 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.4056046386 Mar 07 12:59:56 PM PST 24 Mar 07 01:00:00 PM PST 24 953821312 ps
T298 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.2009000267 Mar 07 12:59:45 PM PST 24 Mar 07 12:59:46 PM PST 24 173894909 ps
T299 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.2371590333 Mar 07 12:59:53 PM PST 24 Mar 07 12:59:56 PM PST 24 362936420 ps
T300 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.1004388546 Mar 07 12:59:56 PM PST 24 Mar 07 12:59:59 PM PST 24 118479046 ps
T301 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.802612477 Mar 07 12:59:48 PM PST 24 Mar 07 12:59:52 PM PST 24 1947525731 ps
T302 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.1111646786 Mar 07 12:59:50 PM PST 24 Mar 07 12:59:52 PM PST 24 115998572 ps
T303 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2433305942 Mar 07 01:00:11 PM PST 24 Mar 07 01:00:16 PM PST 24 376675869 ps
T304 /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2415792837 Mar 07 12:59:43 PM PST 24 Mar 07 12:59:59 PM PST 24 13837652237 ps
T305 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.2492921403 Mar 07 01:00:01 PM PST 24 Mar 07 01:00:04 PM PST 24 64039971 ps
T306 /workspace/coverage/cover_reg_top/36.rv_dm_tap_fsm_rand_reset.2417036369 Mar 07 01:00:05 PM PST 24 Mar 07 01:00:37 PM PST 24 15595625080 ps
T307 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.318228073 Mar 07 12:59:45 PM PST 24 Mar 07 12:59:50 PM PST 24 691842644 ps
T308 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3341538874 Mar 07 12:59:56 PM PST 24 Mar 07 01:00:02 PM PST 24 2603918574 ps
T309 /workspace/coverage/cover_reg_top/34.rv_dm_tap_fsm_rand_reset.3561863686 Mar 07 01:00:01 PM PST 24 Mar 07 01:00:32 PM PST 24 9904500252 ps
T310 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.3347602509 Mar 07 12:59:43 PM PST 24 Mar 07 12:59:45 PM PST 24 103838605 ps
T311 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2521415569 Mar 07 12:59:57 PM PST 24 Mar 07 01:00:02 PM PST 24 1313972492 ps
T312 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2640032766 Mar 07 12:59:54 PM PST 24 Mar 07 12:59:55 PM PST 24 150812893 ps
T313 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3081848768 Mar 07 12:59:46 PM PST 24 Mar 07 12:59:47 PM PST 24 22200377 ps
T111 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.2315359968 Mar 07 01:00:14 PM PST 24 Mar 07 01:00:21 PM PST 24 417785951 ps
T102 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.773910431 Mar 07 12:59:50 PM PST 24 Mar 07 12:59:52 PM PST 24 97271253 ps
T314 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3477733477 Mar 07 12:59:50 PM PST 24 Mar 07 12:59:55 PM PST 24 4001320494 ps
T315 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.3784129034 Mar 07 01:00:01 PM PST 24 Mar 07 01:00:02 PM PST 24 83660536 ps
T122 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.4252811003 Mar 07 12:59:48 PM PST 24 Mar 07 01:00:09 PM PST 24 6650666187 ps
T316 /workspace/coverage/cover_reg_top/39.rv_dm_tap_fsm_rand_reset.852696410 Mar 07 01:00:16 PM PST 24 Mar 07 01:00:45 PM PST 24 26399144862 ps
T317 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3420289854 Mar 07 12:59:58 PM PST 24 Mar 07 01:00:04 PM PST 24 875945064 ps
T318 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.3631303206 Mar 07 12:59:37 PM PST 24 Mar 07 01:00:03 PM PST 24 5728843039 ps
T319 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.4132655620 Mar 07 12:59:47 PM PST 24 Mar 07 12:59:51 PM PST 24 67998723 ps
T320 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1797003184 Mar 07 01:00:01 PM PST 24 Mar 07 01:00:02 PM PST 24 16789355 ps
T321 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.909976216 Mar 07 12:59:59 PM PST 24 Mar 07 01:00:00 PM PST 24 239869527 ps
T103 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.1742615757 Mar 07 12:59:45 PM PST 24 Mar 07 12:59:47 PM PST 24 87618429 ps
T322 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.2110504262 Mar 07 12:59:38 PM PST 24 Mar 07 12:59:40 PM PST 24 123432061 ps
T323 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.3909182566 Mar 07 12:59:48 PM PST 24 Mar 07 12:59:52 PM PST 24 77105543 ps
T324 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.317044418 Mar 07 12:59:58 PM PST 24 Mar 07 01:00:01 PM PST 24 42959018 ps
T325 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.881028260 Mar 07 12:59:52 PM PST 24 Mar 07 12:59:57 PM PST 24 1071254072 ps
T101 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.39148412 Mar 07 12:59:55 PM PST 24 Mar 07 12:59:59 PM PST 24 142779924 ps
T326 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.3938764166 Mar 07 01:00:07 PM PST 24 Mar 07 01:00:10 PM PST 24 779980535 ps
T104 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.3407023746 Mar 07 12:59:51 PM PST 24 Mar 07 01:01:05 PM PST 24 6924054285 ps
T327 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.829548815 Mar 07 01:00:03 PM PST 24 Mar 07 01:00:05 PM PST 24 534670785 ps
T328 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.1023906079 Mar 07 12:59:42 PM PST 24 Mar 07 12:59:50 PM PST 24 1111559588 ps
T329 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1633077174 Mar 07 12:59:42 PM PST 24 Mar 07 12:59:43 PM PST 24 49026566 ps
T330 /workspace/coverage/cover_reg_top/23.rv_dm_tap_fsm_rand_reset.1851437937 Mar 07 01:00:08 PM PST 24 Mar 07 01:00:20 PM PST 24 14787292657 ps
T331 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.2888385254 Mar 07 12:59:49 PM PST 24 Mar 07 12:59:50 PM PST 24 209993735 ps
T332 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.2113989758 Mar 07 01:00:00 PM PST 24 Mar 07 01:00:45 PM PST 24 12876178458 ps
T333 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.305841040 Mar 07 12:59:49 PM PST 24 Mar 07 12:59:51 PM PST 24 93791865 ps
T100 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.2039248717 Mar 07 12:59:44 PM PST 24 Mar 07 12:59:47 PM PST 24 120388097 ps
T334 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.2255459511 Mar 07 12:59:49 PM PST 24 Mar 07 12:59:50 PM PST 24 85514369 ps
T335 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.3798991658 Mar 07 12:59:58 PM PST 24 Mar 07 01:00:00 PM PST 24 216958285 ps
T128 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.4007367008 Mar 07 12:59:57 PM PST 24 Mar 07 01:00:07 PM PST 24 208939977 ps
T336 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3703599632 Mar 07 12:59:45 PM PST 24 Mar 07 12:59:47 PM PST 24 241298001 ps
T337 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.719088916 Mar 07 12:59:53 PM PST 24 Mar 07 12:59:56 PM PST 24 277324881 ps
T105 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.4120544376 Mar 07 01:00:01 PM PST 24 Mar 07 01:00:04 PM PST 24 87514998 ps
T338 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.2438376962 Mar 07 12:59:47 PM PST 24 Mar 07 01:00:04 PM PST 24 11927434963 ps
T339 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2447569847 Mar 07 12:59:54 PM PST 24 Mar 07 12:59:58 PM PST 24 1721824999 ps
T340 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.184974287 Mar 07 12:59:51 PM PST 24 Mar 07 12:59:53 PM PST 24 35490987 ps
T341 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1396222630 Mar 07 12:59:49 PM PST 24 Mar 07 12:59:50 PM PST 24 38796715 ps
T342 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.1351884329 Mar 07 01:00:01 PM PST 24 Mar 07 01:00:03 PM PST 24 101476837 ps
T343 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3466612801 Mar 07 12:59:42 PM PST 24 Mar 07 12:59:44 PM PST 24 66092886 ps
T344 /workspace/coverage/cover_reg_top/12.rv_dm_tap_fsm_rand_reset.1066487430 Mar 07 12:59:50 PM PST 24 Mar 07 01:00:03 PM PST 24 14209881795 ps
T345 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.1108919922 Mar 07 01:00:01 PM PST 24 Mar 07 01:00:03 PM PST 24 59110865 ps
T346 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3709540498 Mar 07 12:59:54 PM PST 24 Mar 07 12:59:56 PM PST 24 197159759 ps
T118 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.2218003996 Mar 07 01:00:06 PM PST 24 Mar 07 01:00:10 PM PST 24 562803419 ps
T347 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.1567933948 Mar 07 12:59:46 PM PST 24 Mar 07 12:59:47 PM PST 24 19857332 ps
T348 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3934855318 Mar 07 12:59:58 PM PST 24 Mar 07 01:00:02 PM PST 24 346908477 ps
T349 /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.2796000682 Mar 07 12:59:45 PM PST 24 Mar 07 12:59:58 PM PST 24 13882835502 ps
T350 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1331538217 Mar 07 12:59:46 PM PST 24 Mar 07 12:59:50 PM PST 24 762459161 ps
T351 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.4097706093 Mar 07 12:59:44 PM PST 24 Mar 07 12:59:45 PM PST 24 48981965 ps
T352 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.992731021 Mar 07 01:00:02 PM PST 24 Mar 07 01:00:05 PM PST 24 36765319 ps
T353 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3175508253 Mar 07 12:59:21 PM PST 24 Mar 07 12:59:23 PM PST 24 640974508 ps
T354 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.765216264 Mar 07 12:59:56 PM PST 24 Mar 07 01:00:03 PM PST 24 183917648 ps
T355 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.4107239367 Mar 07 01:00:08 PM PST 24 Mar 07 01:00:12 PM PST 24 491363331 ps
T129 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1208633817 Mar 07 01:00:07 PM PST 24 Mar 07 01:00:25 PM PST 24 967222926 ps
T96 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.4177491307 Mar 07 01:00:01 PM PST 24 Mar 07 01:00:06 PM PST 24 212945946 ps
T356 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3406194879 Mar 07 01:00:03 PM PST 24 Mar 07 01:00:12 PM PST 24 876239165 ps
T88 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2605798809 Mar 07 12:59:39 PM PST 24 Mar 07 12:59:42 PM PST 24 905584251 ps
T357 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3748686651 Mar 07 12:59:58 PM PST 24 Mar 07 01:00:02 PM PST 24 79176548 ps
T358 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2811252651 Mar 07 12:59:40 PM PST 24 Mar 07 01:00:51 PM PST 24 23514050724 ps
T359 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.4101288592 Mar 07 12:59:43 PM PST 24 Mar 07 12:59:46 PM PST 24 3394129045 ps
T360 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.599896900 Mar 07 12:59:57 PM PST 24 Mar 07 01:00:00 PM PST 24 47450786 ps
T361 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2965525424 Mar 07 12:59:44 PM PST 24 Mar 07 01:00:15 PM PST 24 4627959639 ps
T362 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.3515986804 Mar 07 01:00:11 PM PST 24 Mar 07 01:00:12 PM PST 24 172304094 ps
T363 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.1144606052 Mar 07 01:00:22 PM PST 24 Mar 07 01:00:26 PM PST 24 1680067990 ps
T127 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.3557016222 Mar 07 12:59:56 PM PST 24 Mar 07 01:00:06 PM PST 24 560921068 ps
T364 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2963079177 Mar 07 12:59:53 PM PST 24 Mar 07 12:59:56 PM PST 24 281363866 ps
T365 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2978634738 Mar 07 12:59:39 PM PST 24 Mar 07 12:59:42 PM PST 24 236379550 ps
T366 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3174966444 Mar 07 12:59:56 PM PST 24 Mar 07 12:59:58 PM PST 24 38223016 ps
T367 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.4141284334 Mar 07 12:59:41 PM PST 24 Mar 07 12:59:43 PM PST 24 228922356 ps
T368 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.234542542 Mar 07 12:59:41 PM PST 24 Mar 07 12:59:45 PM PST 24 121747333 ps
T369 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2089799604 Mar 07 01:00:00 PM PST 24 Mar 07 01:00:01 PM PST 24 44513415 ps
T370 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2546382932 Mar 07 12:59:46 PM PST 24 Mar 07 12:59:49 PM PST 24 167801372 ps
T371 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2996455289 Mar 07 12:59:52 PM PST 24 Mar 07 12:59:55 PM PST 24 1505791750 ps
T372 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.2347120627 Mar 07 01:00:05 PM PST 24 Mar 07 01:00:07 PM PST 24 297659248 ps
T373 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.3789825002 Mar 07 12:59:49 PM PST 24 Mar 07 01:00:04 PM PST 24 7793151797 ps
T89 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.3273344330 Mar 07 12:59:42 PM PST 24 Mar 07 12:59:51 PM PST 24 2604656828 ps
T125 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3640815273 Mar 07 12:59:50 PM PST 24 Mar 07 01:00:01 PM PST 24 1847428124 ps
T374 /workspace/coverage/cover_reg_top/38.rv_dm_tap_fsm_rand_reset.912082914 Mar 07 01:00:15 PM PST 24 Mar 07 01:00:27 PM PST 24 13541852373 ps
T375 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.1697761103 Mar 07 01:00:05 PM PST 24 Mar 07 01:00:06 PM PST 24 51252327 ps
T123 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.997183871 Mar 07 12:59:57 PM PST 24 Mar 07 01:00:08 PM PST 24 1931102341 ps
T376 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.4119949721 Mar 07 12:59:46 PM PST 24 Mar 07 12:59:49 PM PST 24 669138495 ps
T377 /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.3275519812 Mar 07 12:59:40 PM PST 24 Mar 07 12:59:52 PM PST 24 16756405633 ps
T378 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.322284796 Mar 07 12:59:53 PM PST 24 Mar 07 01:00:27 PM PST 24 5064749469 ps
T90 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.686337106 Mar 07 12:59:46 PM PST 24 Mar 07 12:59:47 PM PST 24 335469936 ps
T379 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.3306850479 Mar 07 12:59:51 PM PST 24 Mar 07 01:00:58 PM PST 24 12776119342 ps
T380 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.4181834302 Mar 07 12:59:59 PM PST 24 Mar 07 01:00:09 PM PST 24 3011701786 ps
T381 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.888955877 Mar 07 12:59:46 PM PST 24 Mar 07 12:59:49 PM PST 24 77045263 ps
T126 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.1359119410 Mar 07 12:59:51 PM PST 24 Mar 07 01:00:07 PM PST 24 791962496 ps
T62 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.3256918198 Mar 07 12:59:50 PM PST 24 Mar 07 12:59:55 PM PST 24 941955812 ps
T382 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.3058429331 Mar 07 12:59:38 PM PST 24 Mar 07 12:59:39 PM PST 24 18520535 ps
T119 /workspace/coverage/cover_reg_top/35.rv_dm_tap_fsm_rand_reset.2663616105 Mar 07 12:59:58 PM PST 24 Mar 07 01:00:25 PM PST 24 14263087999 ps
T383 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3331666081 Mar 07 12:59:50 PM PST 24 Mar 07 12:59:51 PM PST 24 76092727 ps

Test location /workspace/coverage/default/33.rv_dm_stress_all.3556884688
Short name T4
Test name
Test status
Simulation time 2934196826 ps
CPU time 9.5 seconds
Started Mar 07 01:01:09 PM PST 24
Finished Mar 07 01:01:19 PM PST 24
Peak memory 203668 kb
Host smart-96c6cbce-2f1b-458a-8a81-f941ff2d2f03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556884688 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.3556884688
Directory /workspace/33.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1264731449
Short name T55
Test name
Test status
Simulation time 49983732 ps
CPU time 2.78 seconds
Started Mar 07 12:59:57 PM PST 24
Finished Mar 07 01:00:01 PM PST 24
Peak memory 219396 kb
Host smart-8a8da4bb-acf5-4b49-8aa6-a678a088cdda
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264731449 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.1264731449
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.1173914497
Short name T12
Test name
Test status
Simulation time 3849332443 ps
CPU time 15.51 seconds
Started Mar 07 01:00:52 PM PST 24
Finished Mar 07 01:01:08 PM PST 24
Peak memory 203712 kb
Host smart-dbfb7579-a33c-4f58-ae7c-80fdfc84ad78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173914497 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.1173914497
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.3564845392
Short name T49
Test name
Test status
Simulation time 55252967 ps
CPU time 0.67 seconds
Started Mar 07 01:00:52 PM PST 24
Finished Mar 07 01:00:53 PM PST 24
Peak memory 203400 kb
Host smart-784cf2dc-ba89-47e6-9c59-c13546003a48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564845392 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.3564845392
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tap_fsm_rand_reset.3886340104
Short name T56
Test name
Test status
Simulation time 11820030034 ps
CPU time 19.08 seconds
Started Mar 07 12:59:55 PM PST 24
Finished Mar 07 01:00:16 PM PST 24
Peak memory 214924 kb
Host smart-f5e1e5d1-8aa9-48d8-bf08-fc267dea72e0
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886340104 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rv_dm_tap_fsm_rand_reset.3886340104
Directory /workspace/18.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.2476580549
Short name T287
Test name
Test status
Simulation time 992745528 ps
CPU time 5.25 seconds
Started Mar 07 12:59:43 PM PST 24
Finished Mar 07 12:59:48 PM PST 24
Peak memory 203868 kb
Host smart-dbdd40d6-3f26-4218-8485-6aa03923ee75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476580549 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.2476580549
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/38.rv_dm_stress_all.4206284082
Short name T14
Test name
Test status
Simulation time 1475743187 ps
CPU time 5.48 seconds
Started Mar 07 01:01:06 PM PST 24
Finished Mar 07 01:01:13 PM PST 24
Peak memory 203604 kb
Host smart-88ecbc8b-d488-4067-8ff7-2de01283ce38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206284082 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.4206284082
Directory /workspace/38.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.4137442008
Short name T75
Test name
Test status
Simulation time 1335642556 ps
CPU time 15.38 seconds
Started Mar 07 12:59:53 PM PST 24
Finished Mar 07 01:00:10 PM PST 24
Peak memory 212236 kb
Host smart-f54fd632-f473-46c1-a4c0-9fb6ac72f3d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137442008 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.4137442008
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.650467575
Short name T83
Test name
Test status
Simulation time 8866300793 ps
CPU time 76.02 seconds
Started Mar 07 12:59:58 PM PST 24
Finished Mar 07 01:01:15 PM PST 24
Peak memory 203864 kb
Host smart-3386df64-9755-40ce-bb75-cc060e478e32
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650467575 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.rv_dm_csr_aliasing.650467575
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.4039982741
Short name T45
Test name
Test status
Simulation time 531057123 ps
CPU time 3.96 seconds
Started Mar 07 01:00:03 PM PST 24
Finished Mar 07 01:00:07 PM PST 24
Peak memory 203872 kb
Host smart-ee73c807-17a1-4e2a-aaa4-6111dc0286eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039982741 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.4039982741
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.2169144182
Short name T18
Test name
Test status
Simulation time 12966232702 ps
CPU time 20.55 seconds
Started Mar 07 01:00:42 PM PST 24
Finished Mar 07 01:01:03 PM PST 24
Peak memory 203780 kb
Host smart-43ace67b-b53e-42fe-b378-d8d7afc27334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169144182 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.2169144182
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all.1645400713
Short name T5
Test name
Test status
Simulation time 6163648846 ps
CPU time 7.38 seconds
Started Mar 07 01:00:44 PM PST 24
Finished Mar 07 01:00:51 PM PST 24
Peak memory 203516 kb
Host smart-8a972d3a-4df0-42fc-ba49-305d9c8a81cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645400713 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.1645400713
Directory /workspace/0.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.344554737
Short name T91
Test name
Test status
Simulation time 388512874 ps
CPU time 2.19 seconds
Started Mar 07 12:59:51 PM PST 24
Finished Mar 07 12:59:54 PM PST 24
Peak memory 203832 kb
Host smart-c7267ab0-45e2-4f17-be1e-279508759eb0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344554737 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.344554737
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.1222784154
Short name T66
Test name
Test status
Simulation time 497163255 ps
CPU time 1.01 seconds
Started Mar 07 01:00:47 PM PST 24
Finished Mar 07 01:00:48 PM PST 24
Peak memory 219380 kb
Host smart-b76a2aa2-c16e-4464-91eb-11553697d4d6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222784154 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.1222784154
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.3385964534
Short name T26
Test name
Test status
Simulation time 22174546 ps
CPU time 0.76 seconds
Started Mar 07 01:00:54 PM PST 24
Finished Mar 07 01:00:55 PM PST 24
Peak memory 203492 kb
Host smart-f9275ac0-a14d-45bb-8f13-a5045a349e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385964534 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.3385964534
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.1991492426
Short name T6
Test name
Test status
Simulation time 258526331 ps
CPU time 1 seconds
Started Mar 07 01:00:43 PM PST 24
Finished Mar 07 01:00:44 PM PST 24
Peak memory 203356 kb
Host smart-b4037800-788f-4282-8418-923daddccada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991492426 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.1991492426
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3640815273
Short name T125
Test name
Test status
Simulation time 1847428124 ps
CPU time 10.22 seconds
Started Mar 07 12:59:50 PM PST 24
Finished Mar 07 01:00:01 PM PST 24
Peak memory 212232 kb
Host smart-efc80099-004b-4f32-9b8e-10ee3a8730fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640815273 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.3
640815273
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.3228908255
Short name T29
Test name
Test status
Simulation time 110464095 ps
CPU time 0.85 seconds
Started Mar 07 01:00:37 PM PST 24
Finished Mar 07 01:00:38 PM PST 24
Peak memory 203388 kb
Host smart-cb8c638b-30b5-4982-8c61-54a827ac748e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228908255 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.3228908255
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.75459602
Short name T120
Test name
Test status
Simulation time 8304510574 ps
CPU time 19.33 seconds
Started Mar 07 12:59:58 PM PST 24
Finished Mar 07 01:00:18 PM PST 24
Peak memory 216508 kb
Host smart-f0477697-4bf6-4ecd-acb9-fac28bc7d458
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75459602 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.75459602
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.1359119410
Short name T126
Test name
Test status
Simulation time 791962496 ps
CPU time 15.5 seconds
Started Mar 07 12:59:51 PM PST 24
Finished Mar 07 01:00:07 PM PST 24
Peak memory 212108 kb
Host smart-4a700d1a-6dfa-4f3e-b789-0e6a71967402
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359119410 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.1359119410
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.932492745
Short name T51
Test name
Test status
Simulation time 27161766 ps
CPU time 0.75 seconds
Started Mar 07 01:00:36 PM PST 24
Finished Mar 07 01:00:37 PM PST 24
Peak memory 203416 kb
Host smart-9b54b937-3964-4eca-9ff4-9a1c4f8084c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932492745 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.932492745
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3610413444
Short name T254
Test name
Test status
Simulation time 88297242 ps
CPU time 0.7 seconds
Started Mar 07 12:59:44 PM PST 24
Finished Mar 07 12:59:45 PM PST 24
Peak memory 203576 kb
Host smart-3bd9649b-cfb0-4947-9105-a13b00dc6c6d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610413444 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.3610413444
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.3256918198
Short name T62
Test name
Test status
Simulation time 941955812 ps
CPU time 4.22 seconds
Started Mar 07 12:59:50 PM PST 24
Finished Mar 07 12:59:55 PM PST 24
Peak memory 220288 kb
Host smart-5e39b52c-b0d5-4961-af22-ae61c649f0b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256918198 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.3256918198
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tap_fsm_rand_reset.981193862
Short name T61
Test name
Test status
Simulation time 7687867214 ps
CPU time 23.9 seconds
Started Mar 07 12:59:48 PM PST 24
Finished Mar 07 01:00:12 PM PST 24
Peak memory 212048 kb
Host smart-b837d123-f662-4ca7-a1ba-756d906757d7
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981193862 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.rv_dm_tap_fsm_rand_reset.981193862
Directory /workspace/15.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.2218003996
Short name T118
Test name
Test status
Simulation time 562803419 ps
CPU time 3.24 seconds
Started Mar 07 01:00:06 PM PST 24
Finished Mar 07 01:00:10 PM PST 24
Peak memory 212056 kb
Host smart-a00be881-3e40-4ca8-95ed-2a001e94d77a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218003996 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.2218003996
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2267307328
Short name T86
Test name
Test status
Simulation time 1664379755 ps
CPU time 5.95 seconds
Started Mar 07 12:59:47 PM PST 24
Finished Mar 07 12:59:53 PM PST 24
Peak memory 203804 kb
Host smart-bcd7524a-060d-4193-9aff-fb5d93562aef
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267307328 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.2267307328
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.4250851314
Short name T22
Test name
Test status
Simulation time 108722584 ps
CPU time 0.91 seconds
Started Mar 07 01:00:39 PM PST 24
Finished Mar 07 01:00:40 PM PST 24
Peak memory 203352 kb
Host smart-bc62ccdb-7858-482a-b182-6bda3c11c469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250851314 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.4250851314
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.487212174
Short name T137
Test name
Test status
Simulation time 515208183 ps
CPU time 0.92 seconds
Started Mar 07 01:00:37 PM PST 24
Finished Mar 07 01:00:48 PM PST 24
Peak memory 203196 kb
Host smart-8fdcf485-0e70-4b16-8fc1-7ce7314a0bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487212174 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.487212174
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.3342606626
Short name T57
Test name
Test status
Simulation time 3633710701 ps
CPU time 36.72 seconds
Started Mar 07 12:59:51 PM PST 24
Finished Mar 07 01:00:28 PM PST 24
Peak memory 203784 kb
Host smart-812dd956-8d28-4580-8e1c-32ae3f7ed58c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342606626 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.3342606626
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3212525673
Short name T267
Test name
Test status
Simulation time 32214944 ps
CPU time 1.46 seconds
Started Mar 07 12:59:37 PM PST 24
Finished Mar 07 12:59:39 PM PST 24
Peak memory 203808 kb
Host smart-b22f8a48-a370-46bd-bf1c-d941eaaf6e21
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212525673 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.3212525673
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3477733477
Short name T314
Test name
Test status
Simulation time 4001320494 ps
CPU time 4.21 seconds
Started Mar 07 12:59:50 PM PST 24
Finished Mar 07 12:59:55 PM PST 24
Peak memory 216528 kb
Host smart-3dac4e4a-4506-4dea-b551-c6d6fc3e3605
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477733477 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.3477733477
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.4141284334
Short name T367
Test name
Test status
Simulation time 228922356 ps
CPU time 1.48 seconds
Started Mar 07 12:59:41 PM PST 24
Finished Mar 07 12:59:43 PM PST 24
Peak memory 203792 kb
Host smart-cfad2688-2cf1-413a-878c-4f34f5df9d45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141284334 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.4141284334
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.2438376962
Short name T338
Test name
Test status
Simulation time 11927434963 ps
CPU time 16.69 seconds
Started Mar 07 12:59:47 PM PST 24
Finished Mar 07 01:00:04 PM PST 24
Peak memory 203728 kb
Host smart-03d54118-8331-430b-b82f-e24f77f0de10
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438376962 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.2438376962
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.3146059190
Short name T252
Test name
Test status
Simulation time 9662074133 ps
CPU time 21.67 seconds
Started Mar 07 12:59:45 PM PST 24
Finished Mar 07 01:00:07 PM PST 24
Peak memory 203784 kb
Host smart-3ed69699-ad8a-4693-b50a-e3b505dc1ebd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146059190 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_bit_bash.3146059190
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3175508253
Short name T353
Test name
Test status
Simulation time 640974508 ps
CPU time 2.42 seconds
Started Mar 07 12:59:21 PM PST 24
Finished Mar 07 12:59:23 PM PST 24
Peak memory 203772 kb
Host smart-a2c61602-658f-4d27-8038-338bb6c552e0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175508253 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.3
175508253
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3331666081
Short name T383
Test name
Test status
Simulation time 76092727 ps
CPU time 0.8 seconds
Started Mar 07 12:59:50 PM PST 24
Finished Mar 07 12:59:51 PM PST 24
Peak memory 203508 kb
Host smart-f0eb69d5-5e47-44ed-b7a1-075be19f6c88
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331666081 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.3331666081
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.4119949721
Short name T376
Test name
Test status
Simulation time 669138495 ps
CPU time 2.9 seconds
Started Mar 07 12:59:46 PM PST 24
Finished Mar 07 12:59:49 PM PST 24
Peak memory 203808 kb
Host smart-8b958b54-4f1b-4af3-8b91-0dfd41c0712b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119949721 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.4119949721
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.2110504262
Short name T322
Test name
Test status
Simulation time 123432061 ps
CPU time 1.03 seconds
Started Mar 07 12:59:38 PM PST 24
Finished Mar 07 12:59:40 PM PST 24
Peak memory 203512 kb
Host smart-92952cb6-019a-4be9-86cb-7b5331cd0d26
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110504262 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.2
110504262
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1633077174
Short name T329
Test name
Test status
Simulation time 49026566 ps
CPU time 0.65 seconds
Started Mar 07 12:59:42 PM PST 24
Finished Mar 07 12:59:43 PM PST 24
Peak memory 203484 kb
Host smart-0a781c1c-393e-4704-856e-7a5d686d50b6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633077174 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.1633077174
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.1567933948
Short name T347
Test name
Test status
Simulation time 19857332 ps
CPU time 0.64 seconds
Started Mar 07 12:59:46 PM PST 24
Finished Mar 07 12:59:47 PM PST 24
Peak memory 203508 kb
Host smart-cd5510d8-a870-48ff-9bff-51ecd9a074f1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567933948 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.1567933948
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.4038617023
Short name T80
Test name
Test status
Simulation time 779067665 ps
CPU time 7.14 seconds
Started Mar 07 12:59:38 PM PST 24
Finished Mar 07 12:59:45 PM PST 24
Peak memory 203872 kb
Host smart-58176566-8c66-4f5c-a925-da49296eef3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038617023 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.4038617023
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.3275519812
Short name T377
Test name
Test status
Simulation time 16756405633 ps
CPU time 11.85 seconds
Started Mar 07 12:59:40 PM PST 24
Finished Mar 07 12:59:52 PM PST 24
Peak memory 212880 kb
Host smart-f2c6d812-0b45-43c8-9f89-8190bb459aaf
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275519812 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.3275519812
Directory /workspace/0.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.234542542
Short name T368
Test name
Test status
Simulation time 121747333 ps
CPU time 3.8 seconds
Started Mar 07 12:59:41 PM PST 24
Finished Mar 07 12:59:45 PM PST 24
Peak memory 212184 kb
Host smart-5dc19d2a-3fd1-447b-afcb-1f52ed5ca639
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234542542 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.234542542
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.4124384652
Short name T39
Test name
Test status
Simulation time 515844345 ps
CPU time 9.44 seconds
Started Mar 07 12:59:45 PM PST 24
Finished Mar 07 12:59:55 PM PST 24
Peak memory 211964 kb
Host smart-00377e4f-f2ab-4607-9d4d-5ee89516694b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124384652 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.4124384652
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.830921353
Short name T283
Test name
Test status
Simulation time 12858477759 ps
CPU time 67.74 seconds
Started Mar 07 12:59:43 PM PST 24
Finished Mar 07 01:00:51 PM PST 24
Peak memory 203844 kb
Host smart-445edbb1-5e6a-4298-bd6e-224465068b58
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830921353 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.rv_dm_csr_aliasing.830921353
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.3374691724
Short name T99
Test name
Test status
Simulation time 19369667739 ps
CPU time 67.06 seconds
Started Mar 07 12:59:42 PM PST 24
Finished Mar 07 01:00:50 PM PST 24
Peak memory 203816 kb
Host smart-9dd9c60e-3dfe-414f-b7db-0401f51b0545
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374691724 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.3374691724
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2978634738
Short name T365
Test name
Test status
Simulation time 236379550 ps
CPU time 2.53 seconds
Started Mar 07 12:59:39 PM PST 24
Finished Mar 07 12:59:42 PM PST 24
Peak memory 203824 kb
Host smart-5125e575-a601-4a9e-8736-5ff47bbcd7bb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978634738 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.2978634738
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3304178389
Short name T270
Test name
Test status
Simulation time 303096067 ps
CPU time 3.31 seconds
Started Mar 07 12:59:59 PM PST 24
Finished Mar 07 01:00:03 PM PST 24
Peak memory 220340 kb
Host smart-41b40e0f-9b43-4d25-8329-78607a5aef17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304178389 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.3304178389
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.3347602509
Short name T310
Test name
Test status
Simulation time 103838605 ps
CPU time 1.47 seconds
Started Mar 07 12:59:43 PM PST 24
Finished Mar 07 12:59:45 PM PST 24
Peak memory 203888 kb
Host smart-5df761f0-860c-400b-95d5-20328bf8212b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347602509 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.3347602509
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1464016718
Short name T251
Test name
Test status
Simulation time 25294107292 ps
CPU time 48.52 seconds
Started Mar 07 12:59:44 PM PST 24
Finished Mar 07 01:00:33 PM PST 24
Peak memory 203744 kb
Host smart-5b22b38a-304f-46c2-a192-b3c04e996210
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464016718 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.1464016718
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2811252651
Short name T358
Test name
Test status
Simulation time 23514050724 ps
CPU time 70.73 seconds
Started Mar 07 12:59:40 PM PST 24
Finished Mar 07 01:00:51 PM PST 24
Peak memory 203808 kb
Host smart-3bff66f0-581b-4ecb-b4c0-b4529455e7e5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811252651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_bit_bash.2811252651
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2605798809
Short name T88
Test name
Test status
Simulation time 905584251 ps
CPU time 2.44 seconds
Started Mar 07 12:59:39 PM PST 24
Finished Mar 07 12:59:42 PM PST 24
Peak memory 203764 kb
Host smart-f683d5e4-6a5a-4baa-9a59-9b4e54fb8703
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605798809 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.2605798809
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.3508544023
Short name T253
Test name
Test status
Simulation time 328645764 ps
CPU time 1.2 seconds
Started Mar 07 12:59:41 PM PST 24
Finished Mar 07 12:59:43 PM PST 24
Peak memory 203732 kb
Host smart-cd681198-005b-4fdc-82a4-cc18bcd4a006
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508544023 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.3
508544023
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.54273132
Short name T294
Test name
Test status
Simulation time 38795513 ps
CPU time 0.74 seconds
Started Mar 07 12:59:46 PM PST 24
Finished Mar 07 12:59:48 PM PST 24
Peak memory 203520 kb
Host smart-ca2c8a25-735e-4dd6-b76a-a9aeef9ab595
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54273132 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_
aliasing.54273132
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2126732198
Short name T71
Test name
Test status
Simulation time 980780618 ps
CPU time 2.21 seconds
Started Mar 07 12:59:46 PM PST 24
Finished Mar 07 12:59:48 PM PST 24
Peak memory 203696 kb
Host smart-9e3ed9ed-aea3-4098-86b1-26b2e4717d02
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126732198 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.2126732198
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.3023639526
Short name T275
Test name
Test status
Simulation time 37749503 ps
CPU time 0.7 seconds
Started Mar 07 12:59:43 PM PST 24
Finished Mar 07 12:59:44 PM PST 24
Peak memory 203528 kb
Host smart-ae484b94-930a-4b93-bf9e-79a8a9bba83c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023639526 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.3023639526
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.1707290767
Short name T284
Test name
Test status
Simulation time 93306415 ps
CPU time 0.72 seconds
Started Mar 07 12:59:52 PM PST 24
Finished Mar 07 12:59:53 PM PST 24
Peak memory 203476 kb
Host smart-02e2e26b-dfc6-49b1-86df-d2a3170500ea
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707290767 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.1
707290767
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3081848768
Short name T313
Test name
Test status
Simulation time 22200377 ps
CPU time 0.75 seconds
Started Mar 07 12:59:46 PM PST 24
Finished Mar 07 12:59:47 PM PST 24
Peak memory 203624 kb
Host smart-8d4caa07-99ba-412e-b4bd-ad45ad90248d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081848768 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.3081848768
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.3835515942
Short name T249
Test name
Test status
Simulation time 19238842 ps
CPU time 0.65 seconds
Started Mar 07 12:59:44 PM PST 24
Finished Mar 07 12:59:44 PM PST 24
Peak memory 203536 kb
Host smart-f2b281d1-fa3b-4495-8579-991bdc78abeb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835515942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.3835515942
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.4177491307
Short name T96
Test name
Test status
Simulation time 212945946 ps
CPU time 4.1 seconds
Started Mar 07 01:00:01 PM PST 24
Finished Mar 07 01:00:06 PM PST 24
Peak memory 203844 kb
Host smart-e4848054-7611-46e5-9620-5e6c36e1bc28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177491307 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_
csr_outstanding.4177491307
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.318228073
Short name T307
Test name
Test status
Simulation time 691842644 ps
CPU time 5.64 seconds
Started Mar 07 12:59:45 PM PST 24
Finished Mar 07 12:59:50 PM PST 24
Peak memory 212100 kb
Host smart-9e4a84df-28bc-44a1-bdf7-e9e0289a501f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318228073 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.318228073
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.3214644009
Short name T268
Test name
Test status
Simulation time 515379106 ps
CPU time 9.64 seconds
Started Mar 07 12:59:43 PM PST 24
Finished Mar 07 12:59:53 PM PST 24
Peak memory 212320 kb
Host smart-6bee1e2f-2cbf-4be8-b73a-e4e12f06b5d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214644009 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.3214644009
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3729983141
Short name T44
Test name
Test status
Simulation time 1914393056 ps
CPU time 3.03 seconds
Started Mar 07 12:59:58 PM PST 24
Finished Mar 07 01:00:01 PM PST 24
Peak memory 214092 kb
Host smart-4bda9962-6b49-4ffb-8b24-8f626bfe9555
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729983141 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.3729983141
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.1439046836
Short name T92
Test name
Test status
Simulation time 165456978 ps
CPU time 2.26 seconds
Started Mar 07 12:59:53 PM PST 24
Finished Mar 07 12:59:56 PM PST 24
Peak memory 203796 kb
Host smart-92b05f0f-793b-4ed6-9e7e-0c21161067a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439046836 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.1439046836
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.826639665
Short name T258
Test name
Test status
Simulation time 527551586 ps
CPU time 0.99 seconds
Started Mar 07 01:00:02 PM PST 24
Finished Mar 07 01:00:03 PM PST 24
Peak memory 203728 kb
Host smart-50d6fb51-479b-402d-baa5-1fbcc8bdf309
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826639665 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.826639665
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.3047510865
Short name T266
Test name
Test status
Simulation time 137398891 ps
CPU time 0.7 seconds
Started Mar 07 12:59:53 PM PST 24
Finished Mar 07 12:59:54 PM PST 24
Peak memory 203608 kb
Host smart-81517c09-ff3a-48c9-a959-fe51441302c7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047510865 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
3047510865
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.719088916
Short name T337
Test name
Test status
Simulation time 277324881 ps
CPU time 3.46 seconds
Started Mar 07 12:59:53 PM PST 24
Finished Mar 07 12:59:56 PM PST 24
Peak memory 203884 kb
Host smart-41f86a52-9a3f-4529-8dfa-20962d2cd75f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719088916 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same_
csr_outstanding.719088916
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3420289854
Short name T317
Test name
Test status
Simulation time 875945064 ps
CPU time 5.14 seconds
Started Mar 07 12:59:58 PM PST 24
Finished Mar 07 01:00:04 PM PST 24
Peak memory 203808 kb
Host smart-0214f77f-1ee2-43fb-945c-3ed8cfaafff2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420289854 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.3420289854
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.3125158426
Short name T121
Test name
Test status
Simulation time 3071801963 ps
CPU time 18.6 seconds
Started Mar 07 01:00:01 PM PST 24
Finished Mar 07 01:00:20 PM PST 24
Peak memory 216024 kb
Host smart-c6788df3-f010-473c-b1ff-75d00425a5ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125158426 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.3
125158426
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.773910431
Short name T102
Test name
Test status
Simulation time 97271253 ps
CPU time 1.38 seconds
Started Mar 07 12:59:50 PM PST 24
Finished Mar 07 12:59:52 PM PST 24
Peak memory 203776 kb
Host smart-e813f8c5-b41d-4cef-b460-88a9be55d664
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773910431 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.773910431
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3709540498
Short name T346
Test name
Test status
Simulation time 197159759 ps
CPU time 1.47 seconds
Started Mar 07 12:59:54 PM PST 24
Finished Mar 07 12:59:56 PM PST 24
Peak memory 203732 kb
Host smart-811e1a37-683d-49d3-999d-afc2397fae2d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709540498 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
3709540498
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.2255459511
Short name T334
Test name
Test status
Simulation time 85514369 ps
CPU time 0.65 seconds
Started Mar 07 12:59:49 PM PST 24
Finished Mar 07 12:59:50 PM PST 24
Peak memory 203404 kb
Host smart-90b8144f-0853-4ac2-a7dc-9f8aa1fbc666
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255459511 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.
2255459511
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.1182939633
Short name T107
Test name
Test status
Simulation time 305279889 ps
CPU time 3.41 seconds
Started Mar 07 12:59:51 PM PST 24
Finished Mar 07 12:59:55 PM PST 24
Peak memory 203772 kb
Host smart-37adf606-cc87-4f6c-893d-94e506c5e4a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182939633 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same
_csr_outstanding.1182939633
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.736127396
Short name T42
Test name
Test status
Simulation time 107913392 ps
CPU time 2.42 seconds
Started Mar 07 12:59:56 PM PST 24
Finished Mar 07 01:00:01 PM PST 24
Peak memory 203820 kb
Host smart-36b459be-bc38-403f-acb1-7aa20fcad149
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736127396 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.736127396
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3406194879
Short name T356
Test name
Test status
Simulation time 876239165 ps
CPU time 9.27 seconds
Started Mar 07 01:00:03 PM PST 24
Finished Mar 07 01:00:12 PM PST 24
Peak memory 211900 kb
Host smart-49a69e8d-d6c9-487c-9389-402f0246d2b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406194879 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.3
406194879
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.4056046386
Short name T297
Test name
Test status
Simulation time 953821312 ps
CPU time 2.53 seconds
Started Mar 07 12:59:56 PM PST 24
Finished Mar 07 01:00:00 PM PST 24
Peak memory 211956 kb
Host smart-c4209bc7-1e1b-435c-b7fe-b1fc0b7e2f74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056046386 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.4056046386
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.3798991658
Short name T335
Test name
Test status
Simulation time 216958285 ps
CPU time 1.52 seconds
Started Mar 07 12:59:58 PM PST 24
Finished Mar 07 01:00:00 PM PST 24
Peak memory 203760 kb
Host smart-6074ac31-a754-49cb-815c-259e6fef0325
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798991658 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.3798991658
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.2371590333
Short name T299
Test name
Test status
Simulation time 362936420 ps
CPU time 1.57 seconds
Started Mar 07 12:59:53 PM PST 24
Finished Mar 07 12:59:56 PM PST 24
Peak memory 203716 kb
Host smart-770f8f4d-5a4f-48d6-ab20-f8db6b2ed4cd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371590333 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
2371590333
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2186141484
Short name T256
Test name
Test status
Simulation time 57296390 ps
CPU time 0.64 seconds
Started Mar 07 12:59:58 PM PST 24
Finished Mar 07 12:59:59 PM PST 24
Peak memory 203464 kb
Host smart-3aeff867-0ed6-4c74-9df1-35d2a2c52b8b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186141484 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
2186141484
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.4290983696
Short name T289
Test name
Test status
Simulation time 409839219 ps
CPU time 4.34 seconds
Started Mar 07 12:59:58 PM PST 24
Finished Mar 07 01:00:03 PM PST 24
Peak memory 203888 kb
Host smart-6c168ab7-3834-4a6a-9513-d58c568f27ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290983696 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.4290983696
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tap_fsm_rand_reset.1066487430
Short name T344
Test name
Test status
Simulation time 14209881795 ps
CPU time 13.19 seconds
Started Mar 07 12:59:50 PM PST 24
Finished Mar 07 01:00:03 PM PST 24
Peak memory 212196 kb
Host smart-1ec9dcaa-d7be-4eea-bc71-17140fdaf745
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066487430 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rv_dm_tap_fsm_rand_reset.1066487430
Directory /workspace/12.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.2492921403
Short name T305
Test name
Test status
Simulation time 64039971 ps
CPU time 2.39 seconds
Started Mar 07 01:00:01 PM PST 24
Finished Mar 07 01:00:04 PM PST 24
Peak memory 212080 kb
Host smart-ab253777-75cd-4473-9de0-2453219dbbe9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492921403 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.2492921403
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3968593297
Short name T72
Test name
Test status
Simulation time 985620655 ps
CPU time 15.57 seconds
Started Mar 07 12:59:57 PM PST 24
Finished Mar 07 01:00:14 PM PST 24
Peak memory 212056 kb
Host smart-b574216e-7758-42bd-b359-b604761dc15d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968593297 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.3
968593297
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3341538874
Short name T308
Test name
Test status
Simulation time 2603918574 ps
CPU time 4.55 seconds
Started Mar 07 12:59:56 PM PST 24
Finished Mar 07 01:00:02 PM PST 24
Peak memory 213492 kb
Host smart-8598b6cf-0420-41ef-bce2-f2c60068e46d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341538874 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.3341538874
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.4084613701
Short name T274
Test name
Test status
Simulation time 47225823 ps
CPU time 2.12 seconds
Started Mar 07 01:00:07 PM PST 24
Finished Mar 07 01:00:09 PM PST 24
Peak memory 212008 kb
Host smart-9cc05721-ff9a-44cb-bb78-db2c6e28a39b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084613701 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.4084613701
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.3437066432
Short name T276
Test name
Test status
Simulation time 642434494 ps
CPU time 2.11 seconds
Started Mar 07 01:00:02 PM PST 24
Finished Mar 07 01:00:05 PM PST 24
Peak memory 203680 kb
Host smart-9b784631-e4b2-4a1b-a600-3c7c8466c1f3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437066432 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
3437066432
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.305841040
Short name T333
Test name
Test status
Simulation time 93791865 ps
CPU time 0.72 seconds
Started Mar 07 12:59:49 PM PST 24
Finished Mar 07 12:59:51 PM PST 24
Peak memory 203500 kb
Host smart-8c58f7f0-1c81-4192-a2b7-dd0ed1717bc2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305841040 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.305841040
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.1919750153
Short name T110
Test name
Test status
Simulation time 810166266 ps
CPU time 7.44 seconds
Started Mar 07 12:59:59 PM PST 24
Finished Mar 07 01:00:07 PM PST 24
Peak memory 203892 kb
Host smart-a71aff23-6a5f-45bd-b95a-a6a984fd1005
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919750153 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.1919750153
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2963079177
Short name T364
Test name
Test status
Simulation time 281363866 ps
CPU time 3.01 seconds
Started Mar 07 12:59:53 PM PST 24
Finished Mar 07 12:59:56 PM PST 24
Peak memory 203956 kb
Host smart-b141ea58-d398-46c2-ae10-f257dc84c2bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963079177 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.2963079177
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1208633817
Short name T129
Test name
Test status
Simulation time 967222926 ps
CPU time 17.93 seconds
Started Mar 07 01:00:07 PM PST 24
Finished Mar 07 01:00:25 PM PST 24
Peak memory 212040 kb
Host smart-c359a4e6-cc11-4e59-905c-f2df38cd4620
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208633817 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.1
208633817
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.829548815
Short name T327
Test name
Test status
Simulation time 534670785 ps
CPU time 2.18 seconds
Started Mar 07 01:00:03 PM PST 24
Finished Mar 07 01:00:05 PM PST 24
Peak memory 212088 kb
Host smart-1a6860f4-ab6a-4ec4-8818-484dc6d29a90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829548815 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.829548815
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.992731021
Short name T352
Test name
Test status
Simulation time 36765319 ps
CPU time 2.08 seconds
Started Mar 07 01:00:02 PM PST 24
Finished Mar 07 01:00:05 PM PST 24
Peak memory 203800 kb
Host smart-d81bc0eb-bed0-4342-8af4-c0aa53264878
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992731021 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.992731021
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2602545895
Short name T250
Test name
Test status
Simulation time 335349562 ps
CPU time 1.05 seconds
Started Mar 07 12:59:46 PM PST 24
Finished Mar 07 12:59:47 PM PST 24
Peak memory 203640 kb
Host smart-7c4e61d8-276e-499e-b7c7-a6a5f1c5276c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602545895 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
2602545895
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.3512252148
Short name T260
Test name
Test status
Simulation time 78522859 ps
CPU time 0.83 seconds
Started Mar 07 01:00:09 PM PST 24
Finished Mar 07 01:00:10 PM PST 24
Peak memory 203484 kb
Host smart-4cb0636c-2250-4096-82e5-3a26edfffb9b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512252148 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
3512252148
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.4107239367
Short name T355
Test name
Test status
Simulation time 491363331 ps
CPU time 3.81 seconds
Started Mar 07 01:00:08 PM PST 24
Finished Mar 07 01:00:12 PM PST 24
Peak memory 203868 kb
Host smart-7c21e866-4bee-4c77-9b5c-000ca9a81678
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107239367 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.4107239367
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.997183871
Short name T123
Test name
Test status
Simulation time 1931102341 ps
CPU time 9.93 seconds
Started Mar 07 12:59:57 PM PST 24
Finished Mar 07 01:00:08 PM PST 24
Peak memory 212176 kb
Host smart-4bb8a870-d3c2-40d3-9106-5b46f0c68872
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997183871 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.997183871
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.317044418
Short name T324
Test name
Test status
Simulation time 42959018 ps
CPU time 2.37 seconds
Started Mar 07 12:59:58 PM PST 24
Finished Mar 07 01:00:01 PM PST 24
Peak memory 213768 kb
Host smart-6653c1ba-f09d-4ffc-a491-eab8b0e2b2b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317044418 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.317044418
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2449748552
Short name T265
Test name
Test status
Simulation time 70389266 ps
CPU time 1.52 seconds
Started Mar 07 01:00:10 PM PST 24
Finished Mar 07 01:00:11 PM PST 24
Peak memory 211872 kb
Host smart-c69f674d-3f46-49f4-940c-cf992ff7c304
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449748552 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.2449748552
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.744786302
Short name T257
Test name
Test status
Simulation time 379340309 ps
CPU time 1.32 seconds
Started Mar 07 12:59:57 PM PST 24
Finished Mar 07 12:59:59 PM PST 24
Peak memory 203740 kb
Host smart-b298d09c-f914-421b-93e3-abcb2335bae4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744786302 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.744786302
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.1514144246
Short name T282
Test name
Test status
Simulation time 84712647 ps
CPU time 0.64 seconds
Started Mar 07 12:59:48 PM PST 24
Finished Mar 07 12:59:54 PM PST 24
Peak memory 203412 kb
Host smart-95f09241-6091-4c4c-af1b-8e9bddb51409
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514144246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
1514144246
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.4264902881
Short name T109
Test name
Test status
Simulation time 311757217 ps
CPU time 3.44 seconds
Started Mar 07 12:59:53 PM PST 24
Finished Mar 07 12:59:57 PM PST 24
Peak memory 203868 kb
Host smart-a74b4053-d733-4bd7-ac23-2e615873b4aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264902881 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.4264902881
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.1144606052
Short name T363
Test name
Test status
Simulation time 1680067990 ps
CPU time 3.58 seconds
Started Mar 07 01:00:22 PM PST 24
Finished Mar 07 01:00:26 PM PST 24
Peak memory 220140 kb
Host smart-f4817cfd-3fb2-4b3d-8ff6-16d8fa95f2fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144606052 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.1144606052
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.3998544764
Short name T293
Test name
Test status
Simulation time 169112253 ps
CPU time 2.31 seconds
Started Mar 07 01:00:04 PM PST 24
Finished Mar 07 01:00:07 PM PST 24
Peak memory 203752 kb
Host smart-f9601899-0a81-4075-9de6-e1a549edf190
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998544764 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.3998544764
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.4171119234
Short name T280
Test name
Test status
Simulation time 822896291 ps
CPU time 1.39 seconds
Started Mar 07 01:00:07 PM PST 24
Finished Mar 07 01:00:08 PM PST 24
Peak memory 203752 kb
Host smart-ec2797b0-cee2-4b65-9b0b-ff84df731547
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171119234 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
4171119234
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.1351884329
Short name T342
Test name
Test status
Simulation time 101476837 ps
CPU time 0.79 seconds
Started Mar 07 01:00:01 PM PST 24
Finished Mar 07 01:00:03 PM PST 24
Peak memory 203584 kb
Host smart-fb9537d0-b891-420e-bee0-ff85e63f4267
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351884329 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
1351884329
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3934855318
Short name T348
Test name
Test status
Simulation time 346908477 ps
CPU time 3.54 seconds
Started Mar 07 12:59:58 PM PST 24
Finished Mar 07 01:00:02 PM PST 24
Peak memory 203876 kb
Host smart-022d34d6-d9d2-4ad3-be00-e2c0e848a073
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934855318 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.3934855318
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.2347120627
Short name T372
Test name
Test status
Simulation time 297659248 ps
CPU time 2 seconds
Started Mar 07 01:00:05 PM PST 24
Finished Mar 07 01:00:07 PM PST 24
Peak memory 203860 kb
Host smart-1fbf8f67-11b2-40ec-8448-93da0b741f49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347120627 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.2347120627
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.3513556756
Short name T76
Test name
Test status
Simulation time 45200873 ps
CPU time 2.21 seconds
Started Mar 07 01:00:10 PM PST 24
Finished Mar 07 01:00:12 PM PST 24
Peak memory 213148 kb
Host smart-30d808f9-ca17-4522-a5f4-580a6b6822e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513556756 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.3513556756
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.4120544376
Short name T105
Test name
Test status
Simulation time 87514998 ps
CPU time 2.28 seconds
Started Mar 07 01:00:01 PM PST 24
Finished Mar 07 01:00:04 PM PST 24
Peak memory 203840 kb
Host smart-125f46ae-19fb-447f-ac80-c2408273c6c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120544376 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.4120544376
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.3515986804
Short name T362
Test name
Test status
Simulation time 172304094 ps
CPU time 0.93 seconds
Started Mar 07 01:00:11 PM PST 24
Finished Mar 07 01:00:12 PM PST 24
Peak memory 203736 kb
Host smart-fb3e82d7-b33f-4f41-ad5a-df6f5ce7194d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515986804 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
3515986804
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.1697761103
Short name T375
Test name
Test status
Simulation time 51252327 ps
CPU time 0.73 seconds
Started Mar 07 01:00:05 PM PST 24
Finished Mar 07 01:00:06 PM PST 24
Peak memory 203536 kb
Host smart-e727b3ce-f339-4fc3-849c-263340a5eba3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697761103 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
1697761103
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3748686651
Short name T357
Test name
Test status
Simulation time 79176548 ps
CPU time 3.34 seconds
Started Mar 07 12:59:58 PM PST 24
Finished Mar 07 01:00:02 PM PST 24
Peak memory 203680 kb
Host smart-8c69dc1c-9a80-4beb-8d57-f8d7072c185c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748686651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.3748686651
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.1486819398
Short name T146
Test name
Test status
Simulation time 2370554633 ps
CPU time 3.65 seconds
Started Mar 07 01:00:01 PM PST 24
Finished Mar 07 01:00:05 PM PST 24
Peak memory 212188 kb
Host smart-42834131-3923-4756-9761-d401c05ef9ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486819398 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.1486819398
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.4181834302
Short name T380
Test name
Test status
Simulation time 3011701786 ps
CPU time 9.49 seconds
Started Mar 07 12:59:59 PM PST 24
Finished Mar 07 01:00:09 PM PST 24
Peak memory 213012 kb
Host smart-47dcccd5-fa1b-490d-b33f-60ce5db2b112
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181834302 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.4
181834302
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2996455289
Short name T371
Test name
Test status
Simulation time 1505791750 ps
CPU time 3.14 seconds
Started Mar 07 12:59:52 PM PST 24
Finished Mar 07 12:59:55 PM PST 24
Peak memory 212056 kb
Host smart-1e5c607b-0b98-4b4c-a42a-fbe680893a66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996455289 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.2996455289
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2079251118
Short name T97
Test name
Test status
Simulation time 133417935 ps
CPU time 2.03 seconds
Started Mar 07 12:59:59 PM PST 24
Finished Mar 07 01:00:01 PM PST 24
Peak memory 203800 kb
Host smart-ac8b3433-a6a6-4798-9f29-c1ca54d1903e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079251118 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.2079251118
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2447569847
Short name T339
Test name
Test status
Simulation time 1721824999 ps
CPU time 3.36 seconds
Started Mar 07 12:59:54 PM PST 24
Finished Mar 07 12:59:58 PM PST 24
Peak memory 203728 kb
Host smart-0738823a-37cb-45a4-80f5-cc709473a77e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447569847 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
2447569847
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.1108919922
Short name T345
Test name
Test status
Simulation time 59110865 ps
CPU time 0.7 seconds
Started Mar 07 01:00:01 PM PST 24
Finished Mar 07 01:00:03 PM PST 24
Peak memory 203504 kb
Host smart-87f11700-9506-4ecb-aee7-6636b3250f92
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108919922 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
1108919922
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.2304293249
Short name T46
Test name
Test status
Simulation time 437008836 ps
CPU time 3.76 seconds
Started Mar 07 01:00:04 PM PST 24
Finished Mar 07 01:00:08 PM PST 24
Peak memory 203832 kb
Host smart-bbe61532-27b4-422e-bd19-e4c509a31208
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304293249 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.2304293249
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2433305942
Short name T303
Test name
Test status
Simulation time 376675869 ps
CPU time 4.29 seconds
Started Mar 07 01:00:11 PM PST 24
Finished Mar 07 01:00:16 PM PST 24
Peak memory 212100 kb
Host smart-1ffe12c1-edf2-4253-9101-8332aaa645fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433305942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.2433305942
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.4007367008
Short name T128
Test name
Test status
Simulation time 208939977 ps
CPU time 8.22 seconds
Started Mar 07 12:59:57 PM PST 24
Finished Mar 07 01:00:07 PM PST 24
Peak memory 212012 kb
Host smart-0b1c5c11-526b-4442-91b5-9abcf69f251e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007367008 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.4
007367008
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2521415569
Short name T311
Test name
Test status
Simulation time 1313972492 ps
CPU time 4.82 seconds
Started Mar 07 12:59:57 PM PST 24
Finished Mar 07 01:00:02 PM PST 24
Peak memory 216848 kb
Host smart-2dbc4616-36ec-4eaf-86dc-c505aa44b553
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521415569 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.2521415569
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3174966444
Short name T366
Test name
Test status
Simulation time 38223016 ps
CPU time 1.48 seconds
Started Mar 07 12:59:56 PM PST 24
Finished Mar 07 12:59:58 PM PST 24
Peak memory 211988 kb
Host smart-d213cb38-f75a-4538-b333-2de6dab0c531
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174966444 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.3174966444
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.3938764166
Short name T326
Test name
Test status
Simulation time 779980535 ps
CPU time 3.08 seconds
Started Mar 07 01:00:07 PM PST 24
Finished Mar 07 01:00:10 PM PST 24
Peak memory 203756 kb
Host smart-b8672623-e62a-4fee-b636-e2ff09e26db4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938764166 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
3938764166
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2089799604
Short name T369
Test name
Test status
Simulation time 44513415 ps
CPU time 0.73 seconds
Started Mar 07 01:00:00 PM PST 24
Finished Mar 07 01:00:01 PM PST 24
Peak memory 203504 kb
Host smart-73e9c8b9-398f-4be0-ac77-92c56af8d085
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089799604 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
2089799604
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.2315359968
Short name T111
Test name
Test status
Simulation time 417785951 ps
CPU time 7.39 seconds
Started Mar 07 01:00:14 PM PST 24
Finished Mar 07 01:00:21 PM PST 24
Peak memory 203764 kb
Host smart-71dbad3c-a7bd-4781-b06d-46b50649e18e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315359968 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.2315359968
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2743686802
Short name T130
Test name
Test status
Simulation time 942616581 ps
CPU time 9.56 seconds
Started Mar 07 01:00:06 PM PST 24
Finished Mar 07 01:00:16 PM PST 24
Peak memory 212524 kb
Host smart-26156134-7e7e-4c03-9329-d576127685bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743686802 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.2
743686802
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1421360575
Short name T98
Test name
Test status
Simulation time 8184544711 ps
CPU time 31.48 seconds
Started Mar 07 12:59:37 PM PST 24
Finished Mar 07 01:00:08 PM PST 24
Peak memory 203848 kb
Host smart-924d5822-90d1-4718-bb9f-dfbf12981fd5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421360575 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.1421360575
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.322284796
Short name T378
Test name
Test status
Simulation time 5064749469 ps
CPU time 32.86 seconds
Started Mar 07 12:59:53 PM PST 24
Finished Mar 07 01:00:27 PM PST 24
Peak memory 203796 kb
Host smart-465da54a-7308-4780-a399-4edf995bd897
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322284796 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.322284796
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.4156024203
Short name T286
Test name
Test status
Simulation time 227140943 ps
CPU time 2.4 seconds
Started Mar 07 12:59:53 PM PST 24
Finished Mar 07 12:59:56 PM PST 24
Peak memory 203760 kb
Host smart-3e8cc242-7688-454b-adbc-742b9a39387f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156024203 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.4156024203
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.4101288592
Short name T359
Test name
Test status
Simulation time 3394129045 ps
CPU time 2.88 seconds
Started Mar 07 12:59:43 PM PST 24
Finished Mar 07 12:59:46 PM PST 24
Peak memory 212196 kb
Host smart-733ddef8-f244-4477-907d-2b230c8c7dba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101288592 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.4101288592
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.2039248717
Short name T100
Test name
Test status
Simulation time 120388097 ps
CPU time 2.39 seconds
Started Mar 07 12:59:44 PM PST 24
Finished Mar 07 12:59:47 PM PST 24
Peak memory 212004 kb
Host smart-ff092641-9f78-4abf-9e2f-cbd59df01ec5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039248717 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.2039248717
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.1906153910
Short name T290
Test name
Test status
Simulation time 6349598279 ps
CPU time 13.82 seconds
Started Mar 07 12:59:47 PM PST 24
Finished Mar 07 01:00:01 PM PST 24
Peak memory 203752 kb
Host smart-65bd205b-b666-4c48-9c3d-e2f50edb9bd2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906153910 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.1906153910
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.2113989758
Short name T332
Test name
Test status
Simulation time 12876178458 ps
CPU time 44.29 seconds
Started Mar 07 01:00:00 PM PST 24
Finished Mar 07 01:00:45 PM PST 24
Peak memory 203804 kb
Host smart-9d272d0c-2365-45fa-84bb-5f1c00aa244e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113989758 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_bit_bash.2113989758
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.393493239
Short name T87
Test name
Test status
Simulation time 1193926366 ps
CPU time 1.86 seconds
Started Mar 07 12:59:53 PM PST 24
Finished Mar 07 12:59:56 PM PST 24
Peak memory 203772 kb
Host smart-36264fbe-5329-4ee5-bf7a-ee27ec445922
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393493239 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr
_hw_reset.393493239
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.4102277426
Short name T277
Test name
Test status
Simulation time 550038738 ps
CPU time 1.76 seconds
Started Mar 07 12:59:36 PM PST 24
Finished Mar 07 12:59:38 PM PST 24
Peak memory 203640 kb
Host smart-689d42f8-b41c-464a-97b3-f4a0695314bd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102277426 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.4
102277426
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.2746736699
Short name T70
Test name
Test status
Simulation time 394771071 ps
CPU time 0.93 seconds
Started Mar 07 12:59:42 PM PST 24
Finished Mar 07 12:59:44 PM PST 24
Peak memory 203432 kb
Host smart-1c3680f4-ea7f-4c68-a6cf-b32729f68e67
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746736699 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_aliasing.2746736699
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1331538217
Short name T350
Test name
Test status
Simulation time 762459161 ps
CPU time 3.8 seconds
Started Mar 07 12:59:46 PM PST 24
Finished Mar 07 12:59:50 PM PST 24
Peak memory 203748 kb
Host smart-5973eb36-cbd1-4517-b1d7-979c034b85cf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331538217 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.1331538217
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3466612801
Short name T343
Test name
Test status
Simulation time 66092886 ps
CPU time 0.77 seconds
Started Mar 07 12:59:42 PM PST 24
Finished Mar 07 12:59:44 PM PST 24
Peak memory 203528 kb
Host smart-271f68f1-133b-4316-b1ae-a8133f2b6b4e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466612801 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.3466612801
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.1712047564
Short name T264
Test name
Test status
Simulation time 38225903 ps
CPU time 0.7 seconds
Started Mar 07 01:00:01 PM PST 24
Finished Mar 07 01:00:02 PM PST 24
Peak memory 203480 kb
Host smart-575ae755-2c88-4c51-b1a2-23b4d5061bee
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712047564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.1
712047564
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1797003184
Short name T320
Test name
Test status
Simulation time 16789355 ps
CPU time 0.69 seconds
Started Mar 07 01:00:01 PM PST 24
Finished Mar 07 01:00:02 PM PST 24
Peak memory 203456 kb
Host smart-8a8e797d-2710-484e-bcfc-89a3b51f0a0e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797003184 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.1797003184
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.3058429331
Short name T382
Test name
Test status
Simulation time 18520535 ps
CPU time 0.65 seconds
Started Mar 07 12:59:38 PM PST 24
Finished Mar 07 12:59:39 PM PST 24
Peak memory 203512 kb
Host smart-cf53cb28-777e-4156-aceb-0ae6fa3f5107
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058429331 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.3058429331
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.4285269171
Short name T81
Test name
Test status
Simulation time 143265670 ps
CPU time 6.32 seconds
Started Mar 07 12:59:46 PM PST 24
Finished Mar 07 12:59:52 PM PST 24
Peak memory 203856 kb
Host smart-cde3ff18-550d-4775-a29b-86ead473e9ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285269171 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.4285269171
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.2796000682
Short name T349
Test name
Test status
Simulation time 13882835502 ps
CPU time 12.19 seconds
Started Mar 07 12:59:45 PM PST 24
Finished Mar 07 12:59:58 PM PST 24
Peak memory 212148 kb
Host smart-68d32900-3b02-41bb-94e6-7e4e4969291d
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796000682 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.2796000682
Directory /workspace/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.4252811003
Short name T122
Test name
Test status
Simulation time 6650666187 ps
CPU time 20.64 seconds
Started Mar 07 12:59:48 PM PST 24
Finished Mar 07 01:00:09 PM PST 24
Peak memory 216232 kb
Host smart-82c9fc1a-f293-4b0f-ac95-abd3f4be13da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252811003 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.4252811003
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/21.rv_dm_tap_fsm_rand_reset.1462760561
Short name T131
Test name
Test status
Simulation time 14864641783 ps
CPU time 11.05 seconds
Started Mar 07 12:59:55 PM PST 24
Finished Mar 07 01:00:06 PM PST 24
Peak memory 220152 kb
Host smart-2635ae63-eea3-4c21-bd4b-245cad3625cc
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462760561 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 21.rv_dm_tap_fsm_rand_reset.1462760561
Directory /workspace/21.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/23.rv_dm_tap_fsm_rand_reset.1851437937
Short name T330
Test name
Test status
Simulation time 14787292657 ps
CPU time 11.11 seconds
Started Mar 07 01:00:08 PM PST 24
Finished Mar 07 01:00:20 PM PST 24
Peak memory 219972 kb
Host smart-22d9e865-a1c8-43a0-94e0-71c52cf2a93b
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851437937 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 23.rv_dm_tap_fsm_rand_reset.1851437937
Directory /workspace/23.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/26.rv_dm_tap_fsm_rand_reset.715696019
Short name T132
Test name
Test status
Simulation time 12385304863 ps
CPU time 11.69 seconds
Started Mar 07 01:00:06 PM PST 24
Finished Mar 07 01:00:18 PM PST 24
Peak memory 220284 kb
Host smart-d759e30b-5303-4cb6-9779-69f8f21a6dd6
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715696019 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 26.rv_dm_tap_fsm_rand_reset.715696019
Directory /workspace/26.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.3407023746
Short name T104
Test name
Test status
Simulation time 6924054285 ps
CPU time 74.06 seconds
Started Mar 07 12:59:51 PM PST 24
Finished Mar 07 01:01:05 PM PST 24
Peak memory 212016 kb
Host smart-874f3cdc-40e0-4752-80bb-58c85d59a0f7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407023746 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.3407023746
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.372915309
Short name T163
Test name
Test status
Simulation time 30361833350 ps
CPU time 68.51 seconds
Started Mar 07 12:59:42 PM PST 24
Finished Mar 07 01:00:51 PM PST 24
Peak memory 203788 kb
Host smart-074dd509-afe0-41eb-9b5e-23719ebfc254
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372915309 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.372915309
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.498686887
Short name T79
Test name
Test status
Simulation time 32952401 ps
CPU time 1.42 seconds
Started Mar 07 12:59:44 PM PST 24
Finished Mar 07 12:59:46 PM PST 24
Peak memory 203704 kb
Host smart-8c4a5722-0c06-47c5-b535-343d8da70f24
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498686887 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.498686887
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.1742615757
Short name T103
Test name
Test status
Simulation time 87618429 ps
CPU time 2.31 seconds
Started Mar 07 12:59:45 PM PST 24
Finished Mar 07 12:59:47 PM PST 24
Peak memory 211984 kb
Host smart-befaf71c-08a6-4668-9190-332eacbd1be8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742615757 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.1742615757
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.3789825002
Short name T373
Test name
Test status
Simulation time 7793151797 ps
CPU time 14.37 seconds
Started Mar 07 12:59:49 PM PST 24
Finished Mar 07 01:00:04 PM PST 24
Peak memory 203796 kb
Host smart-8525fa02-7de0-45c3-86e4-2c5a449617dc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789825002 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.3789825002
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1995782351
Short name T285
Test name
Test status
Simulation time 44184714645 ps
CPU time 134.39 seconds
Started Mar 07 12:59:50 PM PST 24
Finished Mar 07 01:02:05 PM PST 24
Peak memory 203772 kb
Host smart-2b54fc60-d39b-456f-9996-032d78f55779
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995782351 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_bit_bash.1995782351
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.686337106
Short name T90
Test name
Test status
Simulation time 335469936 ps
CPU time 1.53 seconds
Started Mar 07 12:59:46 PM PST 24
Finished Mar 07 12:59:47 PM PST 24
Peak memory 203732 kb
Host smart-56dfac39-7eec-4cee-a20e-f20cd44a59af
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686337106 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr
_hw_reset.686337106
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3703599632
Short name T336
Test name
Test status
Simulation time 241298001 ps
CPU time 1.36 seconds
Started Mar 07 12:59:45 PM PST 24
Finished Mar 07 12:59:47 PM PST 24
Peak memory 203688 kb
Host smart-09b4928f-9fae-4357-92a3-9d32f9bacb48
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703599632 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.3
703599632
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3935581562
Short name T292
Test name
Test status
Simulation time 87150773 ps
CPU time 0.92 seconds
Started Mar 07 12:59:44 PM PST 24
Finished Mar 07 12:59:45 PM PST 24
Peak memory 203520 kb
Host smart-a5ed1a34-3a5c-4bca-9bee-b8cd26e3006c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935581562 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.3935581562
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.796074702
Short name T263
Test name
Test status
Simulation time 4408417895 ps
CPU time 13.16 seconds
Started Mar 07 12:59:43 PM PST 24
Finished Mar 07 12:59:57 PM PST 24
Peak memory 203824 kb
Host smart-52cc3831-996d-4db7-b7c6-cbd18efa0703
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796074702 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr
_bit_bash.796074702
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.2888385254
Short name T331
Test name
Test status
Simulation time 209993735 ps
CPU time 0.66 seconds
Started Mar 07 12:59:49 PM PST 24
Finished Mar 07 12:59:50 PM PST 24
Peak memory 203564 kb
Host smart-b1465333-68aa-4574-b456-c74f92b01e3b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888385254 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.2888385254
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1396222630
Short name T341
Test name
Test status
Simulation time 38796715 ps
CPU time 0.68 seconds
Started Mar 07 12:59:49 PM PST 24
Finished Mar 07 12:59:50 PM PST 24
Peak memory 203544 kb
Host smart-c2f16915-484d-4a65-a014-d89caaa14776
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396222630 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.1
396222630
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.3777802532
Short name T291
Test name
Test status
Simulation time 42583925 ps
CPU time 0.64 seconds
Started Mar 07 12:59:54 PM PST 24
Finished Mar 07 12:59:55 PM PST 24
Peak memory 203396 kb
Host smart-98588006-dbc0-4875-995e-e8133582ad51
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777802532 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.3777802532
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1464910753
Short name T296
Test name
Test status
Simulation time 46121822 ps
CPU time 0.64 seconds
Started Mar 07 12:59:44 PM PST 24
Finished Mar 07 12:59:45 PM PST 24
Peak memory 203524 kb
Host smart-8bf14b84-5507-450a-89c0-6f77fa69bead
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464910753 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.1464910753
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.1023906079
Short name T328
Test name
Test status
Simulation time 1111559588 ps
CPU time 7.15 seconds
Started Mar 07 12:59:42 PM PST 24
Finished Mar 07 12:59:50 PM PST 24
Peak memory 203756 kb
Host smart-fe705be7-2e8e-4df4-aa87-2de0b45f4ef0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023906079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.1023906079
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.4132655620
Short name T319
Test name
Test status
Simulation time 67998723 ps
CPU time 4.09 seconds
Started Mar 07 12:59:47 PM PST 24
Finished Mar 07 12:59:51 PM PST 24
Peak memory 212120 kb
Host smart-30a83a3e-fe9e-4a03-92aa-0cee248ada8e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132655620 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.4132655620
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/32.rv_dm_tap_fsm_rand_reset.2907345074
Short name T288
Test name
Test status
Simulation time 7817370752 ps
CPU time 16.54 seconds
Started Mar 07 01:00:00 PM PST 24
Finished Mar 07 01:00:17 PM PST 24
Peak memory 212136 kb
Host smart-ecca6ed6-7fda-4300-8910-cdabc0ef3b23
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907345074 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 32.rv_dm_tap_fsm_rand_reset.2907345074
Directory /workspace/32.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/34.rv_dm_tap_fsm_rand_reset.3561863686
Short name T309
Test name
Test status
Simulation time 9904500252 ps
CPU time 30.83 seconds
Started Mar 07 01:00:01 PM PST 24
Finished Mar 07 01:00:32 PM PST 24
Peak memory 212136 kb
Host smart-6a11f5d9-86cd-4979-b77e-5892fc0339b5
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561863686 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 34.rv_dm_tap_fsm_rand_reset.3561863686
Directory /workspace/34.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/35.rv_dm_tap_fsm_rand_reset.2663616105
Short name T119
Test name
Test status
Simulation time 14263087999 ps
CPU time 26.24 seconds
Started Mar 07 12:59:58 PM PST 24
Finished Mar 07 01:00:25 PM PST 24
Peak memory 220224 kb
Host smart-97c47710-fafe-4a8e-b8d5-ab5fd95ff134
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663616105 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 35.rv_dm_tap_fsm_rand_reset.2663616105
Directory /workspace/35.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/36.rv_dm_tap_fsm_rand_reset.2417036369
Short name T306
Test name
Test status
Simulation time 15595625080 ps
CPU time 27.21 seconds
Started Mar 07 01:00:05 PM PST 24
Finished Mar 07 01:00:37 PM PST 24
Peak memory 228472 kb
Host smart-53c0ea1a-f6c0-49d9-a8d4-d20324207773
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417036369 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 36.rv_dm_tap_fsm_rand_reset.2417036369
Directory /workspace/36.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/38.rv_dm_tap_fsm_rand_reset.912082914
Short name T374
Test name
Test status
Simulation time 13541852373 ps
CPU time 11.9 seconds
Started Mar 07 01:00:15 PM PST 24
Finished Mar 07 01:00:27 PM PST 24
Peak memory 220368 kb
Host smart-cf8a8a94-f016-4cb0-8f59-19fca0ae1811
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912082914 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 38.rv_dm_tap_fsm_rand_reset.912082914
Directory /workspace/38.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/39.rv_dm_tap_fsm_rand_reset.852696410
Short name T316
Test name
Test status
Simulation time 26399144862 ps
CPU time 23.68 seconds
Started Mar 07 01:00:16 PM PST 24
Finished Mar 07 01:00:45 PM PST 24
Peak memory 212052 kb
Host smart-e41c8913-af38-4a84-8707-05c712882bf5
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852696410 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 39.rv_dm_tap_fsm_rand_reset.852696410
Directory /workspace/39.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2965525424
Short name T361
Test name
Test status
Simulation time 4627959639 ps
CPU time 31 seconds
Started Mar 07 12:59:44 PM PST 24
Finished Mar 07 01:00:15 PM PST 24
Peak memory 203872 kb
Host smart-dc3a31a5-b0ff-4737-b1db-1b62d788deba
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965525424 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.2965525424
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.3306850479
Short name T379
Test name
Test status
Simulation time 12776119342 ps
CPU time 66.97 seconds
Started Mar 07 12:59:51 PM PST 24
Finished Mar 07 01:00:58 PM PST 24
Peak memory 203792 kb
Host smart-70000cdc-709f-4224-aa05-e0b48e5bbc9e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306850479 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.3306850479
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.39148412
Short name T101
Test name
Test status
Simulation time 142779924 ps
CPU time 2.43 seconds
Started Mar 07 12:59:55 PM PST 24
Finished Mar 07 12:59:59 PM PST 24
Peak memory 211960 kb
Host smart-96d70e61-7a8b-43b7-a14a-6368c91a73fa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39148412 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.39148412
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.3286519007
Short name T58
Test name
Test status
Simulation time 3336048815 ps
CPU time 6.91 seconds
Started Mar 07 12:59:58 PM PST 24
Finished Mar 07 01:00:10 PM PST 24
Peak memory 214984 kb
Host smart-79b33fec-1569-4552-86ed-54cbfb66b0b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286519007 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.3286519007
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.2613001778
Short name T94
Test name
Test status
Simulation time 91504645 ps
CPU time 1.42 seconds
Started Mar 07 12:59:46 PM PST 24
Finished Mar 07 12:59:48 PM PST 24
Peak memory 211896 kb
Host smart-2b63ba5b-22aa-4205-acdd-d5e35a95c8c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613001778 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.2613001778
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.3631303206
Short name T318
Test name
Test status
Simulation time 5728843039 ps
CPU time 25.41 seconds
Started Mar 07 12:59:37 PM PST 24
Finished Mar 07 01:00:03 PM PST 24
Peak memory 203684 kb
Host smart-4cd9f702-c7a4-4874-bd07-65f22cfc63fa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631303206 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.3631303206
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.961044141
Short name T259
Test name
Test status
Simulation time 13831617022 ps
CPU time 25.61 seconds
Started Mar 07 12:59:53 PM PST 24
Finished Mar 07 01:00:20 PM PST 24
Peak memory 203788 kb
Host smart-c384f1ec-ecc3-48e0-a481-9a8670997d81
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961044141 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr
_bit_bash.961044141
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.3273344330
Short name T89
Test name
Test status
Simulation time 2604656828 ps
CPU time 8.19 seconds
Started Mar 07 12:59:42 PM PST 24
Finished Mar 07 12:59:51 PM PST 24
Peak memory 203812 kb
Host smart-17ba8957-ee5e-4cb2-8fef-cfc820d6a237
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273344330 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.3273344330
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.2009000267
Short name T298
Test name
Test status
Simulation time 173894909 ps
CPU time 0.83 seconds
Started Mar 07 12:59:45 PM PST 24
Finished Mar 07 12:59:46 PM PST 24
Peak memory 203668 kb
Host smart-7b7d3431-239c-44fc-914f-a0ff61355a4b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009000267 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.2
009000267
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.708175565
Short name T295
Test name
Test status
Simulation time 196151970 ps
CPU time 0.88 seconds
Started Mar 07 12:59:44 PM PST 24
Finished Mar 07 12:59:45 PM PST 24
Peak memory 203528 kb
Host smart-a72e7ffc-4fdd-4729-9104-989eca649140
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708175565 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr
_aliasing.708175565
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.3714910292
Short name T64
Test name
Test status
Simulation time 2340431647 ps
CPU time 7.49 seconds
Started Mar 07 12:59:52 PM PST 24
Finished Mar 07 12:59:59 PM PST 24
Peak memory 203812 kb
Host smart-cf546e1c-eb4e-49f7-a6a0-66462f14b61c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714910292 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.3714910292
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2640032766
Short name T312
Test name
Test status
Simulation time 150812893 ps
CPU time 0.8 seconds
Started Mar 07 12:59:54 PM PST 24
Finished Mar 07 12:59:55 PM PST 24
Peak memory 203328 kb
Host smart-16544fdc-1e94-4fb0-8315-91e04b9f59e2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640032766 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.2640032766
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.894508591
Short name T272
Test name
Test status
Simulation time 61169709 ps
CPU time 0.63 seconds
Started Mar 07 12:59:44 PM PST 24
Finished Mar 07 12:59:44 PM PST 24
Peak memory 203520 kb
Host smart-436311be-9083-40b3-9b1b-3662615c90d0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894508591 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.894508591
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.4097706093
Short name T351
Test name
Test status
Simulation time 48981965 ps
CPU time 0.6 seconds
Started Mar 07 12:59:44 PM PST 24
Finished Mar 07 12:59:45 PM PST 24
Peak memory 203592 kb
Host smart-0896c891-3983-4585-b986-7f9fc476af39
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097706093 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.4097706093
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.2795186713
Short name T269
Test name
Test status
Simulation time 163286757 ps
CPU time 0.62 seconds
Started Mar 07 12:59:42 PM PST 24
Finished Mar 07 12:59:42 PM PST 24
Peak memory 203500 kb
Host smart-f73b27d9-cc5a-423c-9869-dee46c7fd80c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795186713 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.2795186713
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.2545367288
Short name T281
Test name
Test status
Simulation time 252137696 ps
CPU time 4.1 seconds
Started Mar 07 12:59:46 PM PST 24
Finished Mar 07 12:59:50 PM PST 24
Peak memory 203876 kb
Host smart-919978ff-ba84-4c1b-a92c-01e4f07fb7de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545367288 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.2545367288
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2415792837
Short name T304
Test name
Test status
Simulation time 13837652237 ps
CPU time 15.56 seconds
Started Mar 07 12:59:43 PM PST 24
Finished Mar 07 12:59:59 PM PST 24
Peak memory 212032 kb
Host smart-ed547e4a-8662-4eec-b28b-862681d9d272
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415792837 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.2415792837
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.802612477
Short name T301
Test name
Test status
Simulation time 1947525731 ps
CPU time 3.23 seconds
Started Mar 07 12:59:48 PM PST 24
Finished Mar 07 12:59:52 PM PST 24
Peak memory 203936 kb
Host smart-317657af-f175-40d7-83f2-a31da2725f52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802612477 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.802612477
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.3817649456
Short name T271
Test name
Test status
Simulation time 903886550 ps
CPU time 9.27 seconds
Started Mar 07 12:59:48 PM PST 24
Finished Mar 07 12:59:57 PM PST 24
Peak memory 212076 kb
Host smart-9dbb3b17-6418-420e-a78f-ad0244f839b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817649456 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.3817649456
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3737349098
Short name T77
Test name
Test status
Simulation time 2004069478 ps
CPU time 5.04 seconds
Started Mar 07 12:59:53 PM PST 24
Finished Mar 07 01:00:00 PM PST 24
Peak memory 220272 kb
Host smart-c3224580-2d32-4a96-ace2-764b1ba83232
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737349098 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.3737349098
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.1033906270
Short name T93
Test name
Test status
Simulation time 27232520 ps
CPU time 1.32 seconds
Started Mar 07 01:00:00 PM PST 24
Finished Mar 07 01:00:01 PM PST 24
Peak memory 203752 kb
Host smart-80f339bf-e449-4d54-a3d0-1df7fde01afb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033906270 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.1033906270
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3830731675
Short name T255
Test name
Test status
Simulation time 1490248678 ps
CPU time 3.23 seconds
Started Mar 07 12:59:55 PM PST 24
Finished Mar 07 12:59:58 PM PST 24
Peak memory 203572 kb
Host smart-4c916281-a3bd-4976-9677-1162ffc12d69
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830731675 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.3
830731675
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.1173267534
Short name T261
Test name
Test status
Simulation time 72816011 ps
CPU time 0.63 seconds
Started Mar 07 12:59:48 PM PST 24
Finished Mar 07 12:59:49 PM PST 24
Peak memory 203492 kb
Host smart-7ff90c00-dcfe-40c2-af27-f406eecfd7c3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173267534 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.1
173267534
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.2099574292
Short name T106
Test name
Test status
Simulation time 144488272 ps
CPU time 6.25 seconds
Started Mar 07 12:59:53 PM PST 24
Finished Mar 07 12:59:59 PM PST 24
Peak memory 203896 kb
Host smart-5bc1a690-4c96-4cc8-a3e2-635a8f0d402e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099574292 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.2099574292
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.204708791
Short name T74
Test name
Test status
Simulation time 117094377 ps
CPU time 2.79 seconds
Started Mar 07 12:59:59 PM PST 24
Finished Mar 07 01:00:02 PM PST 24
Peak memory 203912 kb
Host smart-712beaca-6d2b-4f26-be83-4e0a19ee9b02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204708791 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.204708791
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2654676336
Short name T124
Test name
Test status
Simulation time 781089150 ps
CPU time 8.63 seconds
Started Mar 07 01:00:00 PM PST 24
Finished Mar 07 01:00:09 PM PST 24
Peak memory 211944 kb
Host smart-0b6625d3-e046-4957-b699-e8540f2bcd2e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654676336 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.2654676336
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.184974287
Short name T340
Test name
Test status
Simulation time 35490987 ps
CPU time 2.03 seconds
Started Mar 07 12:59:51 PM PST 24
Finished Mar 07 12:59:53 PM PST 24
Peak memory 213860 kb
Host smart-d869dff1-26ce-4397-b55c-22c50040cdbf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184974287 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.184974287
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.3936167277
Short name T47
Test name
Test status
Simulation time 104040584 ps
CPU time 2.27 seconds
Started Mar 07 12:59:55 PM PST 24
Finished Mar 07 12:59:58 PM PST 24
Peak memory 212004 kb
Host smart-69fc69ff-9f29-46f8-937e-4826de3b6e4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936167277 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.3936167277
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2807700136
Short name T248
Test name
Test status
Simulation time 356671592 ps
CPU time 1.41 seconds
Started Mar 07 12:59:52 PM PST 24
Finished Mar 07 12:59:54 PM PST 24
Peak memory 203724 kb
Host smart-29bac587-14af-4375-9ef8-ead100ce938d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807700136 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.2
807700136
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.3731157605
Short name T278
Test name
Test status
Simulation time 50474810 ps
CPU time 0.74 seconds
Started Mar 07 01:00:03 PM PST 24
Finished Mar 07 01:00:04 PM PST 24
Peak memory 203512 kb
Host smart-622cb710-be48-47d3-b184-6fb8f014d477
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731157605 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.3
731157605
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.3805425418
Short name T108
Test name
Test status
Simulation time 630218031 ps
CPU time 6.43 seconds
Started Mar 07 01:00:01 PM PST 24
Finished Mar 07 01:00:08 PM PST 24
Peak memory 203836 kb
Host smart-1b893354-7a24-444b-b13c-5247da6ae22f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805425418 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.3805425418
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.2024053220
Short name T279
Test name
Test status
Simulation time 150805878 ps
CPU time 3.69 seconds
Started Mar 07 12:59:58 PM PST 24
Finished Mar 07 01:00:02 PM PST 24
Peak memory 204004 kb
Host smart-50e12064-e384-42e9-9c48-f29bf745ea06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024053220 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.2024053220
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2546382932
Short name T370
Test name
Test status
Simulation time 167801372 ps
CPU time 2.41 seconds
Started Mar 07 12:59:46 PM PST 24
Finished Mar 07 12:59:49 PM PST 24
Peak memory 214688 kb
Host smart-c59fef46-bd6a-466e-9bcd-5b90ff3f7f45
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546382932 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.2546382932
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.599896900
Short name T360
Test name
Test status
Simulation time 47450786 ps
CPU time 1.51 seconds
Started Mar 07 12:59:57 PM PST 24
Finished Mar 07 01:00:00 PM PST 24
Peak memory 203740 kb
Host smart-c39a264d-5354-449f-8b34-de54990ed5eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599896900 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.599896900
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.909976216
Short name T321
Test name
Test status
Simulation time 239869527 ps
CPU time 0.96 seconds
Started Mar 07 12:59:59 PM PST 24
Finished Mar 07 01:00:00 PM PST 24
Peak memory 203672 kb
Host smart-8c16fb84-f830-4435-8378-93db89bbf5dc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909976216 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.909976216
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1653971065
Short name T273
Test name
Test status
Simulation time 37635674 ps
CPU time 0.74 seconds
Started Mar 07 12:59:56 PM PST 24
Finished Mar 07 12:59:59 PM PST 24
Peak memory 203492 kb
Host smart-7cef0be6-2c1d-4f2c-b5ef-1b845af92031
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653971065 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.1
653971065
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.1084014438
Short name T95
Test name
Test status
Simulation time 924431588 ps
CPU time 4.41 seconds
Started Mar 07 12:59:56 PM PST 24
Finished Mar 07 01:00:01 PM PST 24
Peak memory 203856 kb
Host smart-32b85b45-f9b4-4634-b335-ca762e633146
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084014438 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.1084014438
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.765216264
Short name T354
Test name
Test status
Simulation time 183917648 ps
CPU time 4.5 seconds
Started Mar 07 12:59:56 PM PST 24
Finished Mar 07 01:00:03 PM PST 24
Peak memory 212064 kb
Host smart-25ba5c4f-9e05-4c0d-84e7-952ee9aca15a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765216264 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.765216264
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.3557016222
Short name T127
Test name
Test status
Simulation time 560921068 ps
CPU time 8.53 seconds
Started Mar 07 12:59:56 PM PST 24
Finished Mar 07 01:00:06 PM PST 24
Peak memory 212068 kb
Host smart-a9ff37ed-2dad-4016-b4fb-80ac0da7e164
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557016222 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.3557016222
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.769478639
Short name T43
Test name
Test status
Simulation time 1862371082 ps
CPU time 2.69 seconds
Started Mar 07 12:59:55 PM PST 24
Finished Mar 07 12:59:58 PM PST 24
Peak memory 212108 kb
Host smart-168653a4-b671-431a-be6d-4fc6e5e91252
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769478639 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.769478639
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.1004388546
Short name T300
Test name
Test status
Simulation time 118479046 ps
CPU time 0.94 seconds
Started Mar 07 12:59:56 PM PST 24
Finished Mar 07 12:59:59 PM PST 24
Peak memory 203416 kb
Host smart-9331d97b-8572-4cb8-b7d2-26f77a9c3eb6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004388546 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.1
004388546
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.881028260
Short name T325
Test name
Test status
Simulation time 1071254072 ps
CPU time 3.94 seconds
Started Mar 07 12:59:52 PM PST 24
Finished Mar 07 12:59:57 PM PST 24
Peak memory 203856 kb
Host smart-4c5e1490-cb45-4df2-971a-0935febfd90d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881028260 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_c
sr_outstanding.881028260
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.1111646786
Short name T302
Test name
Test status
Simulation time 115998572 ps
CPU time 1.94 seconds
Started Mar 07 12:59:50 PM PST 24
Finished Mar 07 12:59:52 PM PST 24
Peak memory 212100 kb
Host smart-2178eaae-146c-4cb8-821b-7a2806919ab3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111646786 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.1111646786
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3009279226
Short name T41
Test name
Test status
Simulation time 1167274416 ps
CPU time 19.12 seconds
Started Mar 07 12:59:53 PM PST 24
Finished Mar 07 01:00:14 PM PST 24
Peak memory 214032 kb
Host smart-77e12d36-7729-4838-bf33-9036b84073f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009279226 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.3009279226
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.888955877
Short name T381
Test name
Test status
Simulation time 77045263 ps
CPU time 2.68 seconds
Started Mar 07 12:59:46 PM PST 24
Finished Mar 07 12:59:49 PM PST 24
Peak memory 212032 kb
Host smart-8bbdc798-a78f-44a7-b48c-b2f763217e60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888955877 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.888955877
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.4265433038
Short name T82
Test name
Test status
Simulation time 31132387 ps
CPU time 1.4 seconds
Started Mar 07 12:59:57 PM PST 24
Finished Mar 07 01:00:00 PM PST 24
Peak memory 203796 kb
Host smart-ce66b3b9-1bfa-44f1-8ea8-876212b9ef0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265433038 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.4265433038
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.2859356266
Short name T262
Test name
Test status
Simulation time 396916755 ps
CPU time 1.19 seconds
Started Mar 07 12:59:52 PM PST 24
Finished Mar 07 12:59:53 PM PST 24
Peak memory 203736 kb
Host smart-35620eee-acfd-4b41-89df-eb2840308945
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859356266 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.2
859356266
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.3784129034
Short name T315
Test name
Test status
Simulation time 83660536 ps
CPU time 0.71 seconds
Started Mar 07 01:00:01 PM PST 24
Finished Mar 07 01:00:02 PM PST 24
Peak memory 203364 kb
Host smart-5437341d-3a74-4911-b2d2-452975650116
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784129034 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.3
784129034
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.3379812962
Short name T59
Test name
Test status
Simulation time 315298273 ps
CPU time 3.36 seconds
Started Mar 07 12:59:55 PM PST 24
Finished Mar 07 01:00:00 PM PST 24
Peak memory 203836 kb
Host smart-8599c56d-0774-4cb7-a02c-6e65ebfc5044
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379812962 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.3379812962
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.3909182566
Short name T323
Test name
Test status
Simulation time 77105543 ps
CPU time 3.73 seconds
Started Mar 07 12:59:48 PM PST 24
Finished Mar 07 12:59:52 PM PST 24
Peak memory 204324 kb
Host smart-12eaa8cd-8a2d-49cf-a92d-baac113fe4b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909182566 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.3909182566
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.771411862
Short name T40
Test name
Test status
Simulation time 457990302 ps
CPU time 8.39 seconds
Started Mar 07 12:59:50 PM PST 24
Finished Mar 07 12:59:59 PM PST 24
Peak memory 212040 kb
Host smart-13ee34cc-c5ee-48d3-854a-850d8b64c96c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771411862 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.771411862
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.3070303337
Short name T175
Test name
Test status
Simulation time 1638691691 ps
CPU time 2.54 seconds
Started Mar 07 01:00:48 PM PST 24
Finished Mar 07 01:00:51 PM PST 24
Peak memory 203656 kb
Host smart-0197287e-88f4-4ad6-89c9-b3e49ed573d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070303337 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.3070303337
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.3656029514
Short name T9
Test name
Test status
Simulation time 1692950562 ps
CPU time 6.09 seconds
Started Mar 07 01:00:55 PM PST 24
Finished Mar 07 01:01:02 PM PST 24
Peak memory 203624 kb
Host smart-9f0fe6fe-ce84-4ff8-b15c-a7c5ad9d110c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656029514 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.3656029514
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.1908645832
Short name T195
Test name
Test status
Simulation time 1262011153 ps
CPU time 2.86 seconds
Started Mar 07 01:00:46 PM PST 24
Finished Mar 07 01:00:50 PM PST 24
Peak memory 203516 kb
Host smart-e1117eed-cc18-4f7b-b560-2517ddcc3c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908645832 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.1908645832
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.574474036
Short name T20
Test name
Test status
Simulation time 158462747 ps
CPU time 0.75 seconds
Started Mar 07 01:00:43 PM PST 24
Finished Mar 07 01:00:44 PM PST 24
Peak memory 203308 kb
Host smart-634fdab7-2949-4f48-b924-c570a3c8da87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574474036 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.574474036
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.1681102436
Short name T192
Test name
Test status
Simulation time 6115317806 ps
CPU time 4.09 seconds
Started Mar 07 01:00:45 PM PST 24
Finished Mar 07 01:00:49 PM PST 24
Peak memory 203720 kb
Host smart-9cd052db-89fb-476c-9810-b8eb7115cd32
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1681102436 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t
l_access.1681102436
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.2007307696
Short name T13
Test name
Test status
Simulation time 208301208 ps
CPU time 1.26 seconds
Started Mar 07 01:00:46 PM PST 24
Finished Mar 07 01:00:48 PM PST 24
Peak memory 203548 kb
Host smart-ea5962fc-357f-4522-8831-35385dfdd493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007307696 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.2007307696
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.4268033978
Short name T218
Test name
Test status
Simulation time 181990577 ps
CPU time 0.71 seconds
Started Mar 07 01:00:45 PM PST 24
Finished Mar 07 01:00:46 PM PST 24
Peak memory 203344 kb
Host smart-5093fa68-e70c-4df4-8726-c4c03da73a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268033978 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.4268033978
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.3480828273
Short name T225
Test name
Test status
Simulation time 239679480 ps
CPU time 0.81 seconds
Started Mar 07 01:00:40 PM PST 24
Finished Mar 07 01:00:41 PM PST 24
Peak memory 203308 kb
Host smart-507c998c-4e01-4cae-abea-849397ea261c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480828273 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.3480828273
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.262022562
Short name T200
Test name
Test status
Simulation time 268359480 ps
CPU time 1.4 seconds
Started Mar 07 01:00:44 PM PST 24
Finished Mar 07 01:00:46 PM PST 24
Peak memory 203236 kb
Host smart-1c36e845-0ae2-4939-a7cd-380ffe2dcd81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262022562 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.262022562
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.643496911
Short name T19
Test name
Test status
Simulation time 50153773 ps
CPU time 0.68 seconds
Started Mar 07 01:00:54 PM PST 24
Finished Mar 07 01:00:55 PM PST 24
Peak memory 203372 kb
Host smart-5efe1e63-30aa-4965-afb8-edfac7d3da52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643496911 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.643496911
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.3996879532
Short name T139
Test name
Test status
Simulation time 126756997 ps
CPU time 0.84 seconds
Started Mar 07 01:00:49 PM PST 24
Finished Mar 07 01:00:51 PM PST 24
Peak memory 203380 kb
Host smart-4bd8b405-284d-4ad5-a3ae-bfd15281a09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996879532 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.3996879532
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.2158299329
Short name T136
Test name
Test status
Simulation time 93420769 ps
CPU time 0.73 seconds
Started Mar 07 01:00:34 PM PST 24
Finished Mar 07 01:00:35 PM PST 24
Peak memory 203416 kb
Host smart-d32ef87e-f1c1-4ab4-ae93-3e7416786034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158299329 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.2158299329
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.2502823699
Short name T16
Test name
Test status
Simulation time 76610159 ps
CPU time 0.83 seconds
Started Mar 07 01:00:47 PM PST 24
Finished Mar 07 01:00:48 PM PST 24
Peak memory 203288 kb
Host smart-c6ee0b72-8ee9-497b-96ab-99c350bcdac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502823699 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.2502823699
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.2692920818
Short name T196
Test name
Test status
Simulation time 821147639 ps
CPU time 2.5 seconds
Started Mar 07 01:00:49 PM PST 24
Finished Mar 07 01:00:51 PM PST 24
Peak memory 203768 kb
Host smart-e8b6f2d0-2b7c-461f-991a-b0fee71cff7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692920818 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.2692920818
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.1285811091
Short name T68
Test name
Test status
Simulation time 645768764 ps
CPU time 2.5 seconds
Started Mar 07 01:00:56 PM PST 24
Finished Mar 07 01:01:00 PM PST 24
Peak memory 203416 kb
Host smart-50903da0-e88a-4e6f-bbae-6717405ec68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285811091 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.1285811091
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.3841529706
Short name T60
Test name
Test status
Simulation time 8584796718 ps
CPU time 2.84 seconds
Started Mar 07 01:00:45 PM PST 24
Finished Mar 07 01:00:48 PM PST 24
Peak memory 203564 kb
Host smart-da0f339b-5dba-45db-a47e-ed9645a04c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841529706 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.3841529706
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.259928042
Short name T53
Test name
Test status
Simulation time 16538793 ps
CPU time 0.63 seconds
Started Mar 07 01:00:51 PM PST 24
Finished Mar 07 01:00:51 PM PST 24
Peak memory 203412 kb
Host smart-adf41e6c-5c14-4d29-9c64-d86049a6a6de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259928042 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.259928042
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.927430235
Short name T179
Test name
Test status
Simulation time 4158775234 ps
CPU time 12.77 seconds
Started Mar 07 01:00:47 PM PST 24
Finished Mar 07 01:01:00 PM PST 24
Peak memory 203716 kb
Host smart-893bb8ff-0ce2-4fbb-a072-786aa56410b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927430235 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.927430235
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.1404419135
Short name T10
Test name
Test status
Simulation time 1781550971 ps
CPU time 3.85 seconds
Started Mar 07 01:00:37 PM PST 24
Finished Mar 07 01:00:41 PM PST 24
Peak memory 203532 kb
Host smart-6d863c8a-ee9e-4145-8f06-b8cd1b6221ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404419135 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.1404419135
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.3535978628
Short name T30
Test name
Test status
Simulation time 261082484 ps
CPU time 1.02 seconds
Started Mar 07 01:00:40 PM PST 24
Finished Mar 07 01:00:41 PM PST 24
Peak memory 203472 kb
Host smart-b5a8414e-4a7f-4dfb-848b-14f19e9e7744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535978628 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.3535978628
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.4250187873
Short name T21
Test name
Test status
Simulation time 215276626 ps
CPU time 1.23 seconds
Started Mar 07 01:00:53 PM PST 24
Finished Mar 07 01:00:54 PM PST 24
Peak memory 203232 kb
Host smart-99659cf4-41f1-4ef3-abb9-800aa01c858d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250187873 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.4250187873
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.1042588029
Short name T135
Test name
Test status
Simulation time 3312417109 ps
CPU time 2.73 seconds
Started Mar 07 01:00:49 PM PST 24
Finished Mar 07 01:00:52 PM PST 24
Peak memory 203556 kb
Host smart-0e7c186d-df23-4ca2-8865-5b427020d24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042588029 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.1042588029
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.4105036573
Short name T145
Test name
Test status
Simulation time 62802954 ps
CPU time 0.76 seconds
Started Mar 07 01:00:52 PM PST 24
Finished Mar 07 01:00:54 PM PST 24
Peak memory 203352 kb
Host smart-b89c5549-984f-4f68-be92-4838c14f9ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105036573 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.4105036573
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.2788239946
Short name T213
Test name
Test status
Simulation time 5420248019 ps
CPU time 7.14 seconds
Started Mar 07 01:00:38 PM PST 24
Finished Mar 07 01:00:45 PM PST 24
Peak memory 203780 kb
Host smart-417eb018-2da1-4cc6-ac21-65bac160004e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2788239946 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.2788239946
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.74030655
Short name T140
Test name
Test status
Simulation time 620633506 ps
CPU time 1.71 seconds
Started Mar 07 01:00:57 PM PST 24
Finished Mar 07 01:00:59 PM PST 24
Peak memory 203556 kb
Host smart-9892677a-2ebf-4ae7-b3ce-af06c12c3cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74030655 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.74030655
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.627300461
Short name T222
Test name
Test status
Simulation time 125202290 ps
CPU time 0.8 seconds
Started Mar 07 01:00:54 PM PST 24
Finished Mar 07 01:00:55 PM PST 24
Peak memory 203248 kb
Host smart-69e79368-2637-478a-864c-7c8aa39294e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627300461 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.627300461
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.3963368974
Short name T33
Test name
Test status
Simulation time 293366380 ps
CPU time 1.52 seconds
Started Mar 07 01:00:49 PM PST 24
Finished Mar 07 01:00:51 PM PST 24
Peak memory 203336 kb
Host smart-33cc03fd-7ff4-43d9-9f32-59aa62b5b131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963368974 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.3963368974
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.4028120868
Short name T188
Test name
Test status
Simulation time 82298069 ps
CPU time 0.87 seconds
Started Mar 07 01:01:04 PM PST 24
Finished Mar 07 01:01:05 PM PST 24
Peak memory 203192 kb
Host smart-cebea4c1-24bc-4a9c-8075-7fc526943a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028120868 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.4028120868
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.2917896661
Short name T211
Test name
Test status
Simulation time 131863300 ps
CPU time 0.88 seconds
Started Mar 07 01:00:48 PM PST 24
Finished Mar 07 01:00:49 PM PST 24
Peak memory 203264 kb
Host smart-5ce2e282-b12e-418e-8fde-7d01a5d52456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917896661 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.2917896661
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.1503771697
Short name T63
Test name
Test status
Simulation time 42480953 ps
CPU time 0.68 seconds
Started Mar 07 01:00:33 PM PST 24
Finished Mar 07 01:00:34 PM PST 24
Peak memory 203340 kb
Host smart-10895312-ca2a-49f7-bdf0-10367ae143bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503771697 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.1503771697
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.2529813400
Short name T73
Test name
Test status
Simulation time 61481364 ps
CPU time 0.86 seconds
Started Mar 07 01:00:47 PM PST 24
Finished Mar 07 01:00:48 PM PST 24
Peak memory 203136 kb
Host smart-096e1429-6314-4731-b969-0b1432a70464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529813400 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.2529813400
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.2675434263
Short name T144
Test name
Test status
Simulation time 172195972 ps
CPU time 1.2 seconds
Started Mar 07 01:00:53 PM PST 24
Finished Mar 07 01:00:55 PM PST 24
Peak memory 203552 kb
Host smart-aad43de0-e48e-4fbd-9cd2-b7a2bfffdbec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675434263 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.2675434263
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.2957073328
Short name T28
Test name
Test status
Simulation time 135785347 ps
CPU time 0.81 seconds
Started Mar 07 01:00:47 PM PST 24
Finished Mar 07 01:00:48 PM PST 24
Peak memory 203308 kb
Host smart-8f943ad1-b722-4996-ab28-f3760ce5ff6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957073328 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.2957073328
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.3831655280
Short name T25
Test name
Test status
Simulation time 145163720 ps
CPU time 0.72 seconds
Started Mar 07 01:00:50 PM PST 24
Finished Mar 07 01:00:51 PM PST 24
Peak memory 203428 kb
Host smart-60dce81f-cbf3-4e5e-b315-2ba7d139c4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831655280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.3831655280
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.2135885477
Short name T232
Test name
Test status
Simulation time 1298640004 ps
CPU time 4.96 seconds
Started Mar 07 01:00:40 PM PST 24
Finished Mar 07 01:00:45 PM PST 24
Peak memory 203608 kb
Host smart-38be46b0-f429-4a03-9c60-bc047feae258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135885477 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.2135885477
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.3628132787
Short name T36
Test name
Test status
Simulation time 580568036 ps
CPU time 1.18 seconds
Started Mar 07 01:00:52 PM PST 24
Finished Mar 07 01:00:53 PM PST 24
Peak memory 219652 kb
Host smart-2d52667f-1a84-4354-aa54-24243c182eca
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628132787 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.3628132787
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.2921899992
Short name T8
Test name
Test status
Simulation time 340456749 ps
CPU time 1.08 seconds
Started Mar 07 01:00:42 PM PST 24
Finished Mar 07 01:00:43 PM PST 24
Peak memory 203304 kb
Host smart-2fff5042-f568-46cb-8880-eb3e5bac8b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921899992 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.2921899992
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.29105545
Short name T156
Test name
Test status
Simulation time 20505816 ps
CPU time 0.63 seconds
Started Mar 07 01:00:37 PM PST 24
Finished Mar 07 01:00:38 PM PST 24
Peak memory 203440 kb
Host smart-cc629510-a9a0-4432-9629-46ad57d8656f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29105545 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.29105545
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.1536751386
Short name T239
Test name
Test status
Simulation time 4786581408 ps
CPU time 8.85 seconds
Started Mar 07 01:00:56 PM PST 24
Finished Mar 07 01:01:05 PM PST 24
Peak memory 203800 kb
Host smart-fb3b46e9-72c5-42d2-8492-f2bbad3328fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536751386 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.1536751386
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.556450930
Short name T84
Test name
Test status
Simulation time 1025992371 ps
CPU time 2.53 seconds
Started Mar 07 01:00:46 PM PST 24
Finished Mar 07 01:00:49 PM PST 24
Peak memory 203664 kb
Host smart-fb3b2e72-adc5-4eb4-bf27-82fa80c051b7
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=556450930 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_t
l_access.556450930
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.1231424949
Short name T190
Test name
Test status
Simulation time 2483993267 ps
CPU time 7.41 seconds
Started Mar 07 01:00:47 PM PST 24
Finished Mar 07 01:00:54 PM PST 24
Peak memory 203720 kb
Host smart-7f488df2-e220-4ae4-9191-78ab52a2bf4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231424949 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.1231424949
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.1514173094
Short name T181
Test name
Test status
Simulation time 6169106340 ps
CPU time 19.84 seconds
Started Mar 07 01:01:02 PM PST 24
Finished Mar 07 01:01:22 PM PST 24
Peak memory 203764 kb
Host smart-bfff7bb8-3d89-4001-96c7-2af4a12f8f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514173094 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.1514173094
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.2735019660
Short name T204
Test name
Test status
Simulation time 1528056796 ps
CPU time 4.92 seconds
Started Mar 07 01:01:00 PM PST 24
Finished Mar 07 01:01:05 PM PST 24
Peak memory 203584 kb
Host smart-969bb288-1a43-4375-bb66-f1777699a09d
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2735019660 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_
tl_access.2735019660
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.1307196606
Short name T227
Test name
Test status
Simulation time 7718283483 ps
CPU time 7.63 seconds
Started Mar 07 01:01:04 PM PST 24
Finished Mar 07 01:01:12 PM PST 24
Peak memory 203740 kb
Host smart-78d366fc-c274-44cd-ba60-e13fb9d86d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307196606 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.1307196606
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.3141092117
Short name T150
Test name
Test status
Simulation time 46990227 ps
CPU time 0.63 seconds
Started Mar 07 01:00:47 PM PST 24
Finished Mar 07 01:00:48 PM PST 24
Peak memory 203412 kb
Host smart-fef9965b-99e0-4347-951c-dd37ff950a05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141092117 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.3141092117
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.3902601600
Short name T235
Test name
Test status
Simulation time 21671700895 ps
CPU time 43.36 seconds
Started Mar 07 01:01:14 PM PST 24
Finished Mar 07 01:01:58 PM PST 24
Peak memory 203676 kb
Host smart-432b8ff5-b51d-4f8e-a428-e92f23f0fd05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902601600 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.3902601600
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.689536675
Short name T234
Test name
Test status
Simulation time 1139872713 ps
CPU time 4.53 seconds
Started Mar 07 01:01:02 PM PST 24
Finished Mar 07 01:01:07 PM PST 24
Peak memory 203648 kb
Host smart-b0ed5fc2-eb7a-4958-aeef-66f18f1f73a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689536675 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.689536675
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.679657313
Short name T177
Test name
Test status
Simulation time 3114653166 ps
CPU time 9.21 seconds
Started Mar 07 01:01:05 PM PST 24
Finished Mar 07 01:01:14 PM PST 24
Peak memory 203732 kb
Host smart-faa1c295-b762-4da7-bba4-6312d35a3129
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=679657313 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_t
l_access.679657313
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.1027074010
Short name T199
Test name
Test status
Simulation time 8023511178 ps
CPU time 10.97 seconds
Started Mar 07 01:01:11 PM PST 24
Finished Mar 07 01:01:22 PM PST 24
Peak memory 203696 kb
Host smart-6530f3fe-7721-4072-a9c8-87a4a201e2d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027074010 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.1027074010
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.3005667950
Short name T166
Test name
Test status
Simulation time 29730462 ps
CPU time 0.64 seconds
Started Mar 07 01:00:55 PM PST 24
Finished Mar 07 01:00:56 PM PST 24
Peak memory 203476 kb
Host smart-46135e83-7df4-41d8-9984-616fe25f9801
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005667950 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.3005667950
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.3959548331
Short name T247
Test name
Test status
Simulation time 14945881535 ps
CPU time 18.09 seconds
Started Mar 07 01:00:49 PM PST 24
Finished Mar 07 01:01:07 PM PST 24
Peak memory 203732 kb
Host smart-7514ca3f-fb88-4b3a-9580-3ea7966761b2
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3959548331 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_
tl_access.3959548331
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.2941811450
Short name T246
Test name
Test status
Simulation time 8867295857 ps
CPU time 14.11 seconds
Started Mar 07 01:00:56 PM PST 24
Finished Mar 07 01:01:10 PM PST 24
Peak memory 203668 kb
Host smart-fbcb7cea-077a-4a1a-8f75-8f0abc8eff97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941811450 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.2941811450
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.3130272515
Short name T228
Test name
Test status
Simulation time 27552618 ps
CPU time 0.71 seconds
Started Mar 07 01:01:01 PM PST 24
Finished Mar 07 01:01:02 PM PST 24
Peak memory 203356 kb
Host smart-a3742602-5bba-451b-acf6-6525c3695143
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130272515 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.3130272515
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.688339678
Short name T207
Test name
Test status
Simulation time 17277396052 ps
CPU time 33.39 seconds
Started Mar 07 01:00:53 PM PST 24
Finished Mar 07 01:01:27 PM PST 24
Peak memory 203732 kb
Host smart-a98f970a-fcd0-4653-95b3-8945ef45018c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688339678 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.688339678
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.4110389555
Short name T223
Test name
Test status
Simulation time 1381833897 ps
CPU time 3.17 seconds
Started Mar 07 01:00:53 PM PST 24
Finished Mar 07 01:00:57 PM PST 24
Peak memory 203700 kb
Host smart-b8a4cc39-6caf-4f83-88e1-cdb2b975716b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110389555 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.4110389555
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.1172642283
Short name T174
Test name
Test status
Simulation time 1907445266 ps
CPU time 5.67 seconds
Started Mar 07 01:00:57 PM PST 24
Finished Mar 07 01:01:03 PM PST 24
Peak memory 203684 kb
Host smart-fb911ab1-7381-49bd-9328-fd7285a87456
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1172642283 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.1172642283
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.1338069870
Short name T219
Test name
Test status
Simulation time 4966539367 ps
CPU time 5.08 seconds
Started Mar 07 01:00:59 PM PST 24
Finished Mar 07 01:01:05 PM PST 24
Peak memory 203704 kb
Host smart-9f5335f6-07f0-4f5a-8b18-34ce3586f588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338069870 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.1338069870
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.3083744755
Short name T31
Test name
Test status
Simulation time 17945411 ps
CPU time 0.65 seconds
Started Mar 07 01:01:08 PM PST 24
Finished Mar 07 01:01:09 PM PST 24
Peak memory 203388 kb
Host smart-6e7422ba-98fa-495d-9bba-ba7f52a13e5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083744755 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.3083744755
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.2244318116
Short name T11
Test name
Test status
Simulation time 5718501349 ps
CPU time 10.42 seconds
Started Mar 07 01:00:59 PM PST 24
Finished Mar 07 01:01:10 PM PST 24
Peak memory 203852 kb
Host smart-80267cd1-8ad8-4069-86f0-c069420da3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244318116 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.2244318116
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.64568614
Short name T189
Test name
Test status
Simulation time 2349123932 ps
CPU time 5.24 seconds
Started Mar 07 01:00:56 PM PST 24
Finished Mar 07 01:01:01 PM PST 24
Peak memory 203732 kb
Host smart-01c2c2e3-0f1d-4aaf-836a-bc3df1531a9d
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=64568614 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_tl
_access.64568614
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.1662645328
Short name T171
Test name
Test status
Simulation time 1151674296 ps
CPU time 6 seconds
Started Mar 07 01:00:47 PM PST 24
Finished Mar 07 01:00:54 PM PST 24
Peak memory 203696 kb
Host smart-74b385b8-2626-48ac-9635-8ddbdf49ce21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662645328 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.1662645328
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.4030628635
Short name T167
Test name
Test status
Simulation time 17498290 ps
CPU time 0.65 seconds
Started Mar 07 01:01:08 PM PST 24
Finished Mar 07 01:01:09 PM PST 24
Peak memory 203476 kb
Host smart-da4c5912-0439-4b49-bae3-d52e605648ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030628635 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.4030628635
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.2869502285
Short name T244
Test name
Test status
Simulation time 6206795593 ps
CPU time 9.18 seconds
Started Mar 07 01:00:53 PM PST 24
Finished Mar 07 01:01:02 PM PST 24
Peak memory 203768 kb
Host smart-d340f822-e183-46b5-9462-15c8fbc4aa8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869502285 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.2869502285
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.33386792
Short name T216
Test name
Test status
Simulation time 370797034 ps
CPU time 2.03 seconds
Started Mar 07 01:01:03 PM PST 24
Finished Mar 07 01:01:05 PM PST 24
Peak memory 203700 kb
Host smart-4f600491-a740-4564-a674-4570ebc481f0
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=33386792 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_tl
_access.33386792
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.3483341920
Short name T170
Test name
Test status
Simulation time 848785937 ps
CPU time 2.57 seconds
Started Mar 07 01:01:02 PM PST 24
Finished Mar 07 01:01:05 PM PST 24
Peak memory 203724 kb
Host smart-3655f1a8-f882-4090-95d7-6fb5214d1b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483341920 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.3483341920
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_stress_all.697800464
Short name T134
Test name
Test status
Simulation time 3459008447 ps
CPU time 11.96 seconds
Started Mar 07 01:01:07 PM PST 24
Finished Mar 07 01:01:19 PM PST 24
Peak memory 203624 kb
Host smart-2abcd38d-c2bf-4f0d-af4f-12296dae5eb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697800464 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.697800464
Directory /workspace/16.rv_dm_stress_all/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.4062595386
Short name T52
Test name
Test status
Simulation time 15721376 ps
CPU time 0.65 seconds
Started Mar 07 01:01:03 PM PST 24
Finished Mar 07 01:01:04 PM PST 24
Peak memory 203388 kb
Host smart-3b46e2c5-dab0-4e8c-896e-2bb57fc89b44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062595386 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.4062595386
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.1047557957
Short name T242
Test name
Test status
Simulation time 1306022790 ps
CPU time 3.1 seconds
Started Mar 07 01:01:04 PM PST 24
Finished Mar 07 01:01:07 PM PST 24
Peak memory 203688 kb
Host smart-ce55ca68-0491-44cf-b27b-ed375727407a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047557957 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.1047557957
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.2295981856
Short name T215
Test name
Test status
Simulation time 6119823134 ps
CPU time 12.99 seconds
Started Mar 07 01:01:28 PM PST 24
Finished Mar 07 01:01:42 PM PST 24
Peak memory 203724 kb
Host smart-c711c0a7-8b7b-4d21-984f-1baa8a8e9fc8
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2295981856 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_
tl_access.2295981856
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.2070051915
Short name T193
Test name
Test status
Simulation time 4668519810 ps
CPU time 16.72 seconds
Started Mar 07 01:01:11 PM PST 24
Finished Mar 07 01:01:28 PM PST 24
Peak memory 203724 kb
Host smart-b9f0c895-006d-4ccb-a498-d9c53ffa7069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070051915 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.2070051915
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_stress_all.1765607176
Short name T15
Test name
Test status
Simulation time 10590213098 ps
CPU time 22.14 seconds
Started Mar 07 01:01:08 PM PST 24
Finished Mar 07 01:01:30 PM PST 24
Peak memory 203556 kb
Host smart-487dcf16-b2e5-45a5-8444-23623fbcc6d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765607176 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.1765607176
Directory /workspace/17.rv_dm_stress_all/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.3054509635
Short name T160
Test name
Test status
Simulation time 54871554 ps
CPU time 0.65 seconds
Started Mar 07 01:01:11 PM PST 24
Finished Mar 07 01:01:12 PM PST 24
Peak memory 203392 kb
Host smart-0b3bb7dc-71cb-4795-ad9c-9189731298d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054509635 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.3054509635
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.901293112
Short name T17
Test name
Test status
Simulation time 7100239451 ps
CPU time 23.95 seconds
Started Mar 07 01:00:57 PM PST 24
Finished Mar 07 01:01:22 PM PST 24
Peak memory 203676 kb
Host smart-ba87ae40-e30b-4be1-9116-a3543ac21897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901293112 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.901293112
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.4077391035
Short name T238
Test name
Test status
Simulation time 3817296299 ps
CPU time 6.2 seconds
Started Mar 07 01:00:59 PM PST 24
Finished Mar 07 01:01:06 PM PST 24
Peak memory 203704 kb
Host smart-59149f87-97a9-45dc-893d-b9f15230e252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077391035 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.4077391035
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.4133001550
Short name T3
Test name
Test status
Simulation time 699957843 ps
CPU time 2.21 seconds
Started Mar 07 01:00:50 PM PST 24
Finished Mar 07 01:00:53 PM PST 24
Peak memory 203568 kb
Host smart-6be42a17-0730-4f1e-9b39-ae5f4d6fcdb8
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4133001550 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_
tl_access.4133001550
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.1484467856
Short name T178
Test name
Test status
Simulation time 3615927747 ps
CPU time 13.14 seconds
Started Mar 07 01:00:56 PM PST 24
Finished Mar 07 01:01:10 PM PST 24
Peak memory 203512 kb
Host smart-7aa09779-4a1b-45e7-a9e9-fa37301fed99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484467856 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.1484467856
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_stress_all.4121179146
Short name T32
Test name
Test status
Simulation time 1913255838 ps
CPU time 3.23 seconds
Started Mar 07 01:00:55 PM PST 24
Finished Mar 07 01:00:59 PM PST 24
Peak memory 203540 kb
Host smart-3550dc7a-628b-4e6a-b4a0-bc344da9305c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121179146 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.4121179146
Directory /workspace/18.rv_dm_stress_all/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.2700615855
Short name T54
Test name
Test status
Simulation time 36665234 ps
CPU time 0.68 seconds
Started Mar 07 01:00:53 PM PST 24
Finished Mar 07 01:00:55 PM PST 24
Peak memory 203368 kb
Host smart-c4eea7d5-14ae-42d5-81c5-bee469cf65ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700615855 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.2700615855
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.2578989868
Short name T210
Test name
Test status
Simulation time 25034619762 ps
CPU time 90.58 seconds
Started Mar 07 01:00:54 PM PST 24
Finished Mar 07 01:02:25 PM PST 24
Peak memory 203776 kb
Host smart-9d39b0f2-443f-4125-8286-4adc1517655b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578989868 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.2578989868
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.1307628440
Short name T69
Test name
Test status
Simulation time 6008905867 ps
CPU time 8.81 seconds
Started Mar 07 01:01:14 PM PST 24
Finished Mar 07 01:01:23 PM PST 24
Peak memory 203684 kb
Host smart-9e5f9801-ddb6-48af-9d35-466f2ac5f8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307628440 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.1307628440
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.1310539769
Short name T184
Test name
Test status
Simulation time 6810480624 ps
CPU time 19.79 seconds
Started Mar 07 01:00:53 PM PST 24
Finished Mar 07 01:01:13 PM PST 24
Peak memory 203732 kb
Host smart-d48782ca-8146-4032-9333-bd890f954932
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1310539769 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_
tl_access.1310539769
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.3101911047
Short name T221
Test name
Test status
Simulation time 4072007453 ps
CPU time 10.38 seconds
Started Mar 07 01:01:02 PM PST 24
Finished Mar 07 01:01:13 PM PST 24
Peak memory 203692 kb
Host smart-2cf5f4c9-12b7-4c9f-a3f2-6fd3c739170b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101911047 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.3101911047
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.1806515569
Short name T113
Test name
Test status
Simulation time 32087379 ps
CPU time 0.65 seconds
Started Mar 07 01:00:39 PM PST 24
Finished Mar 07 01:00:40 PM PST 24
Peak memory 203356 kb
Host smart-5404161d-ecc6-4253-9cd7-2e6e908273d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806515569 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.1806515569
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.190488900
Short name T1
Test name
Test status
Simulation time 13103527388 ps
CPU time 24.34 seconds
Started Mar 07 01:00:50 PM PST 24
Finished Mar 07 01:01:15 PM PST 24
Peak memory 203664 kb
Host smart-64dfc218-a907-4ca3-8ec3-6dbd04c7fb05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190488900 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.190488900
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.2048939497
Short name T245
Test name
Test status
Simulation time 7449791748 ps
CPU time 27.97 seconds
Started Mar 07 01:00:48 PM PST 24
Finished Mar 07 01:01:17 PM PST 24
Peak memory 203776 kb
Host smart-17bb7881-68b9-4ca6-93bc-7bf1d2d21133
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2048939497 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.2048939497
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.3589178849
Short name T241
Test name
Test status
Simulation time 74909290 ps
CPU time 0.71 seconds
Started Mar 07 01:00:52 PM PST 24
Finished Mar 07 01:00:53 PM PST 24
Peak memory 203180 kb
Host smart-c9d95e4f-3aab-4dfb-8fbb-6ac96f1d512d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589178849 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.3589178849
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.316214733
Short name T27
Test name
Test status
Simulation time 9422668040 ps
CPU time 30.57 seconds
Started Mar 07 01:00:53 PM PST 24
Finished Mar 07 01:01:24 PM PST 24
Peak memory 203776 kb
Host smart-dcd41b25-ec8f-4ffe-919e-d9b3a24799b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316214733 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.316214733
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.111962772
Short name T37
Test name
Test status
Simulation time 219315353 ps
CPU time 1.16 seconds
Started Mar 07 01:00:55 PM PST 24
Finished Mar 07 01:00:56 PM PST 24
Peak memory 219592 kb
Host smart-668088a2-df5b-41b1-bbbf-5a638a053d05
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111962772 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.111962772
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.2808322399
Short name T115
Test name
Test status
Simulation time 27361953 ps
CPU time 0.68 seconds
Started Mar 07 01:00:54 PM PST 24
Finished Mar 07 01:00:55 PM PST 24
Peak memory 203432 kb
Host smart-118c1738-28b1-41ee-87c1-324641eaa46f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808322399 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.2808322399
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.3090686773
Short name T197
Test name
Test status
Simulation time 19460269 ps
CPU time 0.67 seconds
Started Mar 07 01:00:55 PM PST 24
Finished Mar 07 01:01:01 PM PST 24
Peak memory 203388 kb
Host smart-901a12ae-9362-4f27-ad67-3246949bba70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090686773 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.3090686773
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_stress_all.350842559
Short name T23
Test name
Test status
Simulation time 657367001 ps
CPU time 1.61 seconds
Started Mar 07 01:01:04 PM PST 24
Finished Mar 07 01:01:05 PM PST 24
Peak memory 203516 kb
Host smart-18f627a0-ef70-4f0f-9697-bc9b48bfeef5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350842559 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.350842559
Directory /workspace/21.rv_dm_stress_all/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.959856997
Short name T162
Test name
Test status
Simulation time 26940770 ps
CPU time 0.66 seconds
Started Mar 07 01:00:58 PM PST 24
Finished Mar 07 01:00:59 PM PST 24
Peak memory 203284 kb
Host smart-40e51dc8-7671-4da7-9229-a77fb4289de7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959856997 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.959856997
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.2213320898
Short name T168
Test name
Test status
Simulation time 32924216 ps
CPU time 0.69 seconds
Started Mar 07 01:01:02 PM PST 24
Finished Mar 07 01:01:03 PM PST 24
Peak memory 203412 kb
Host smart-10f3e6ec-8bee-4557-b111-b62df29bbadd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213320898 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.2213320898
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_stress_all.183751125
Short name T141
Test name
Test status
Simulation time 6984774392 ps
CPU time 6.21 seconds
Started Mar 07 01:01:01 PM PST 24
Finished Mar 07 01:01:07 PM PST 24
Peak memory 203496 kb
Host smart-23eb0732-fedb-4c75-93c7-d714d6ed21a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183751125 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.183751125
Directory /workspace/23.rv_dm_stress_all/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.392528649
Short name T158
Test name
Test status
Simulation time 40279633 ps
CPU time 0.67 seconds
Started Mar 07 01:01:05 PM PST 24
Finished Mar 07 01:01:06 PM PST 24
Peak memory 203288 kb
Host smart-e0cbe3e8-6d92-4881-b26d-069c8b04e595
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392528649 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.392528649
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.3216488020
Short name T48
Test name
Test status
Simulation time 32127965 ps
CPU time 0.63 seconds
Started Mar 07 01:01:01 PM PST 24
Finished Mar 07 01:01:02 PM PST 24
Peak memory 203284 kb
Host smart-c9d2caab-51ca-4149-957d-263fef661966
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216488020 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.3216488020
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.474692416
Short name T201
Test name
Test status
Simulation time 32987048 ps
CPU time 0.64 seconds
Started Mar 07 01:00:58 PM PST 24
Finished Mar 07 01:01:00 PM PST 24
Peak memory 203392 kb
Host smart-cac3e954-592e-495f-a02f-066e80611fae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474692416 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.474692416
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_stress_all.3654087732
Short name T7
Test name
Test status
Simulation time 972286999 ps
CPU time 3.68 seconds
Started Mar 07 01:00:56 PM PST 24
Finished Mar 07 01:01:05 PM PST 24
Peak memory 203592 kb
Host smart-84df41f2-ee5c-45c8-8943-f85ac66ae0c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654087732 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.3654087732
Directory /workspace/26.rv_dm_stress_all/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.1208281674
Short name T187
Test name
Test status
Simulation time 32687624 ps
CPU time 0.64 seconds
Started Mar 07 01:01:01 PM PST 24
Finished Mar 07 01:01:02 PM PST 24
Peak memory 203420 kb
Host smart-36fe5c2b-5025-4606-9dff-eabc02abc928
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208281674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.1208281674
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.536660951
Short name T155
Test name
Test status
Simulation time 19071565 ps
CPU time 0.68 seconds
Started Mar 07 01:00:57 PM PST 24
Finished Mar 07 01:00:58 PM PST 24
Peak memory 203380 kb
Host smart-1e6ab80d-0810-4079-bf13-a14a5b7046ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536660951 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.536660951
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_stress_all.540006361
Short name T34
Test name
Test status
Simulation time 2227630497 ps
CPU time 7.49 seconds
Started Mar 07 01:01:15 PM PST 24
Finished Mar 07 01:01:22 PM PST 24
Peak memory 203644 kb
Host smart-f101c4f6-ee34-49d6-ae1f-220d09c15535
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540006361 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.540006361
Directory /workspace/28.rv_dm_stress_all/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.633035607
Short name T114
Test name
Test status
Simulation time 30732030 ps
CPU time 0.67 seconds
Started Mar 07 01:01:07 PM PST 24
Finished Mar 07 01:01:08 PM PST 24
Peak memory 203408 kb
Host smart-d6861858-dc40-42f5-873a-d9e8fdd6dbb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633035607 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.633035607
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.559703393
Short name T152
Test name
Test status
Simulation time 32178270 ps
CPU time 0.77 seconds
Started Mar 07 01:00:40 PM PST 24
Finished Mar 07 01:00:42 PM PST 24
Peak memory 203392 kb
Host smart-9a640482-2da1-45ed-a500-3d0e3b35a6a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559703393 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.559703393
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.3929489164
Short name T243
Test name
Test status
Simulation time 3692206028 ps
CPU time 13.95 seconds
Started Mar 07 01:00:57 PM PST 24
Finished Mar 07 01:01:12 PM PST 24
Peak memory 203768 kb
Host smart-2cc03189-a848-49c5-9785-a77a12452aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929489164 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.3929489164
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.1092206471
Short name T202
Test name
Test status
Simulation time 2733172790 ps
CPU time 6.79 seconds
Started Mar 07 01:00:54 PM PST 24
Finished Mar 07 01:01:01 PM PST 24
Peak memory 203728 kb
Host smart-e7fc22c5-7673-4261-bbf2-db6972a6ce8a
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1092206471 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.1092206471
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.2367631494
Short name T173
Test name
Test status
Simulation time 132308700 ps
CPU time 0.68 seconds
Started Mar 07 01:00:39 PM PST 24
Finished Mar 07 01:00:40 PM PST 24
Peak memory 203312 kb
Host smart-b1a98b48-ce2d-400c-ae5c-e28a5b34804d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367631494 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.2367631494
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.2665376991
Short name T191
Test name
Test status
Simulation time 5813196250 ps
CPU time 17.38 seconds
Started Mar 07 01:00:46 PM PST 24
Finished Mar 07 01:01:04 PM PST 24
Peak memory 203668 kb
Host smart-c53fd39c-87eb-42b9-93a4-5bb7aa7aa85f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665376991 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.2665376991
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.865615791
Short name T65
Test name
Test status
Simulation time 178289787 ps
CPU time 0.96 seconds
Started Mar 07 01:00:45 PM PST 24
Finished Mar 07 01:00:46 PM PST 24
Peak memory 219408 kb
Host smart-9a1626a7-37de-498e-9821-1ace3d895eac
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865615791 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.865615791
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.3269034720
Short name T35
Test name
Test status
Simulation time 17912649 ps
CPU time 0.65 seconds
Started Mar 07 01:00:50 PM PST 24
Finished Mar 07 01:00:51 PM PST 24
Peak memory 203412 kb
Host smart-1105c3ab-79d7-4561-a220-1c98985ae707
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269034720 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.3269034720
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.2972863195
Short name T157
Test name
Test status
Simulation time 21283474 ps
CPU time 0.66 seconds
Started Mar 07 01:01:27 PM PST 24
Finished Mar 07 01:01:29 PM PST 24
Peak memory 203172 kb
Host smart-114eba9f-4a60-49d5-a00f-fa170dc9cfbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972863195 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.2972863195
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.1116793973
Short name T153
Test name
Test status
Simulation time 25324274 ps
CPU time 0.65 seconds
Started Mar 07 01:01:28 PM PST 24
Finished Mar 07 01:01:29 PM PST 24
Peak memory 203352 kb
Host smart-cafe8326-7076-4f87-b4a4-c8b2a5a795fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116793973 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.1116793973
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.522890990
Short name T147
Test name
Test status
Simulation time 17667215 ps
CPU time 0.66 seconds
Started Mar 07 01:01:19 PM PST 24
Finished Mar 07 01:01:21 PM PST 24
Peak memory 203408 kb
Host smart-5c055617-09b1-4aea-bb9c-2332c5e81dcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522890990 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.522890990
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.1697771041
Short name T180
Test name
Test status
Simulation time 26834400 ps
CPU time 0.66 seconds
Started Mar 07 01:00:58 PM PST 24
Finished Mar 07 01:01:00 PM PST 24
Peak memory 203288 kb
Host smart-68d12df4-2c4e-4bb2-8dd5-5d50882402eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697771041 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.1697771041
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.941569908
Short name T2
Test name
Test status
Simulation time 106879461 ps
CPU time 0.62 seconds
Started Mar 07 01:00:59 PM PST 24
Finished Mar 07 01:01:00 PM PST 24
Peak memory 203384 kb
Host smart-444f4189-42ed-4366-ab49-5b46469a9b72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941569908 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.941569908
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_stress_all.3890898228
Short name T143
Test name
Test status
Simulation time 5403976459 ps
CPU time 3.74 seconds
Started Mar 07 01:01:12 PM PST 24
Finished Mar 07 01:01:16 PM PST 24
Peak memory 203596 kb
Host smart-0a23387a-ba30-4ad7-ae3c-d4c7fe8612db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890898228 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.3890898228
Directory /workspace/35.rv_dm_stress_all/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.1799405935
Short name T50
Test name
Test status
Simulation time 49981724 ps
CPU time 0.64 seconds
Started Mar 07 01:01:18 PM PST 24
Finished Mar 07 01:01:18 PM PST 24
Peak memory 203412 kb
Host smart-5f267274-4d35-41e7-893c-352b12cee31a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799405935 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.1799405935
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.4172095506
Short name T112
Test name
Test status
Simulation time 86504545 ps
CPU time 0.72 seconds
Started Mar 07 01:01:43 PM PST 24
Finished Mar 07 01:01:44 PM PST 24
Peak memory 203384 kb
Host smart-4305d15c-ce2b-4b95-b936-6903e80ed75d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172095506 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.4172095506
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.2629179085
Short name T161
Test name
Test status
Simulation time 53440103 ps
CPU time 0.63 seconds
Started Mar 07 01:00:58 PM PST 24
Finished Mar 07 01:01:00 PM PST 24
Peak memory 203416 kb
Host smart-2c6a4d56-6e7f-4818-888a-17d6808953de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629179085 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.2629179085
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.278516929
Short name T212
Test name
Test status
Simulation time 72869241 ps
CPU time 0.65 seconds
Started Mar 07 01:01:05 PM PST 24
Finished Mar 07 01:01:06 PM PST 24
Peak memory 203416 kb
Host smart-28bcc097-81ca-400a-a971-8287c63e562e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278516929 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.278516929
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.2750840030
Short name T209
Test name
Test status
Simulation time 78898150 ps
CPU time 0.66 seconds
Started Mar 07 01:00:43 PM PST 24
Finished Mar 07 01:00:44 PM PST 24
Peak memory 203408 kb
Host smart-aa92cc8d-c146-4f8c-9da5-b2039881a0ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750840030 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.2750840030
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.896698771
Short name T237
Test name
Test status
Simulation time 12893673298 ps
CPU time 12.41 seconds
Started Mar 07 01:01:15 PM PST 24
Finished Mar 07 01:01:28 PM PST 24
Peak memory 203752 kb
Host smart-2be585d3-3bbe-422b-ba56-95e098cce751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896698771 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.896698771
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.1039534932
Short name T229
Test name
Test status
Simulation time 7242415487 ps
CPU time 8.79 seconds
Started Mar 07 01:00:52 PM PST 24
Finished Mar 07 01:01:01 PM PST 24
Peak memory 203720 kb
Host smart-08d32533-114f-4bc2-b636-9f72b101fd5f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1039534932 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.1039534932
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.1719676607
Short name T183
Test name
Test status
Simulation time 51590275 ps
CPU time 0.74 seconds
Started Mar 07 01:00:50 PM PST 24
Finished Mar 07 01:00:51 PM PST 24
Peak memory 203340 kb
Host smart-8701fbcb-bc2e-49b6-a60c-0a3f005eb8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719676607 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.1719676607
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.1245821181
Short name T198
Test name
Test status
Simulation time 2772810815 ps
CPU time 3.21 seconds
Started Mar 07 01:00:46 PM PST 24
Finished Mar 07 01:00:50 PM PST 24
Peak memory 203716 kb
Host smart-d5a47b3f-7097-43af-9221-226845658dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245821181 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.1245821181
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.2048443530
Short name T38
Test name
Test status
Simulation time 272295150 ps
CPU time 1.06 seconds
Started Mar 07 01:00:49 PM PST 24
Finished Mar 07 01:00:51 PM PST 24
Peak memory 219652 kb
Host smart-cc91556a-96ea-4173-a62d-6624af659247
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048443530 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.2048443530
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.364007543
Short name T230
Test name
Test status
Simulation time 22458679 ps
CPU time 0.64 seconds
Started Mar 07 01:01:09 PM PST 24
Finished Mar 07 01:01:10 PM PST 24
Peak memory 203460 kb
Host smart-75a9b4fa-8757-4318-8046-b090b765646a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364007543 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.364007543
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.1710177279
Short name T231
Test name
Test status
Simulation time 43608923 ps
CPU time 0.63 seconds
Started Mar 07 01:01:16 PM PST 24
Finished Mar 07 01:01:17 PM PST 24
Peak memory 203376 kb
Host smart-b187b9d2-6bce-4b81-8e6f-5df890674a8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710177279 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.1710177279
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_stress_all.413255721
Short name T24
Test name
Test status
Simulation time 6569213630 ps
CPU time 14.61 seconds
Started Mar 07 01:01:09 PM PST 24
Finished Mar 07 01:01:24 PM PST 24
Peak memory 203636 kb
Host smart-e29f1e11-3676-4715-bea0-4b3b06b153db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413255721 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.413255721
Directory /workspace/41.rv_dm_stress_all/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.4012366102
Short name T165
Test name
Test status
Simulation time 37758999 ps
CPU time 0.63 seconds
Started Mar 07 01:01:05 PM PST 24
Finished Mar 07 01:01:05 PM PST 24
Peak memory 203396 kb
Host smart-8c14dc50-50ea-4fa9-9ed6-dc6a7737be40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012366102 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.4012366102
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.3443341054
Short name T236
Test name
Test status
Simulation time 30023325 ps
CPU time 0.64 seconds
Started Mar 07 01:01:06 PM PST 24
Finished Mar 07 01:01:06 PM PST 24
Peak memory 203460 kb
Host smart-dcaea8a7-23a6-4da5-8b3a-17ffb677bc49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443341054 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.3443341054
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_stress_all.419880575
Short name T133
Test name
Test status
Simulation time 4226914446 ps
CPU time 14.98 seconds
Started Mar 07 01:01:01 PM PST 24
Finished Mar 07 01:01:16 PM PST 24
Peak memory 203604 kb
Host smart-41704f4f-fb59-4ccf-9432-eca1c0ddeaca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419880575 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.419880575
Directory /workspace/43.rv_dm_stress_all/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.806737554
Short name T148
Test name
Test status
Simulation time 60829481 ps
CPU time 0.65 seconds
Started Mar 07 01:01:16 PM PST 24
Finished Mar 07 01:01:17 PM PST 24
Peak memory 203380 kb
Host smart-ce30b4cc-994d-4af6-87d9-02b6d1006373
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806737554 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.806737554
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.1654186730
Short name T116
Test name
Test status
Simulation time 21369381 ps
CPU time 0.64 seconds
Started Mar 07 01:01:14 PM PST 24
Finished Mar 07 01:01:15 PM PST 24
Peak memory 203460 kb
Host smart-df4b07ef-b6e6-497d-9254-610f41dd6b88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654186730 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.1654186730
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.1151979287
Short name T149
Test name
Test status
Simulation time 37778106 ps
CPU time 0.67 seconds
Started Mar 07 01:01:24 PM PST 24
Finished Mar 07 01:01:25 PM PST 24
Peak memory 203444 kb
Host smart-6f805335-16a7-4e14-9179-9f079b5b980c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151979287 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.1151979287
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_stress_all.2274226942
Short name T138
Test name
Test status
Simulation time 10226826453 ps
CPU time 7.23 seconds
Started Mar 07 01:00:58 PM PST 24
Finished Mar 07 01:01:06 PM PST 24
Peak memory 203628 kb
Host smart-c2ff51f8-4f4f-4129-b5b0-1e1cc5d86810
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274226942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.2274226942
Directory /workspace/46.rv_dm_stress_all/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.1346548923
Short name T154
Test name
Test status
Simulation time 18552182 ps
CPU time 0.66 seconds
Started Mar 07 01:01:11 PM PST 24
Finished Mar 07 01:01:12 PM PST 24
Peak memory 203432 kb
Host smart-38f2498c-dc56-4f75-aad6-d99419810473
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346548923 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.1346548923
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.27541328
Short name T164
Test name
Test status
Simulation time 26333368 ps
CPU time 0.63 seconds
Started Mar 07 01:00:56 PM PST 24
Finished Mar 07 01:00:57 PM PST 24
Peak memory 203380 kb
Host smart-5a077721-1727-4005-a7b8-8c8f2b97ee29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27541328 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.27541328
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.2276024246
Short name T182
Test name
Test status
Simulation time 28331483 ps
CPU time 0.63 seconds
Started Mar 07 01:01:02 PM PST 24
Finished Mar 07 01:01:03 PM PST 24
Peak memory 203296 kb
Host smart-17fe36ec-3ec4-4dff-bfeb-084d9f66e9d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276024246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.2276024246
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.1140097506
Short name T78
Test name
Test status
Simulation time 49802643 ps
CPU time 0.62 seconds
Started Mar 07 01:00:57 PM PST 24
Finished Mar 07 01:00:58 PM PST 24
Peak memory 203412 kb
Host smart-108b7a90-eb0c-412b-b0ae-7bfdd035801b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140097506 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.1140097506
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.516760673
Short name T233
Test name
Test status
Simulation time 2721281118 ps
CPU time 10.04 seconds
Started Mar 07 01:00:51 PM PST 24
Finished Mar 07 01:01:02 PM PST 24
Peak memory 203732 kb
Host smart-f2ca9d53-253b-43fa-a50a-0e83495ec8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516760673 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.516760673
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.881597298
Short name T176
Test name
Test status
Simulation time 5548671123 ps
CPU time 20.11 seconds
Started Mar 07 01:00:45 PM PST 24
Finished Mar 07 01:01:06 PM PST 24
Peak memory 203772 kb
Host smart-ea73f26c-07e8-4a2a-b85a-50cc9e334559
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=881597298 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_tl
_access.881597298
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.1298126880
Short name T226
Test name
Test status
Simulation time 15919605659 ps
CPU time 49.25 seconds
Started Mar 07 01:00:47 PM PST 24
Finished Mar 07 01:01:37 PM PST 24
Peak memory 203692 kb
Host smart-3e08d6b1-a8d9-472b-8d39-14ce2e21f529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298126880 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.1298126880
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.3609368911
Short name T205
Test name
Test status
Simulation time 31304375 ps
CPU time 0.68 seconds
Started Mar 07 01:00:48 PM PST 24
Finished Mar 07 01:00:54 PM PST 24
Peak memory 203384 kb
Host smart-f7e62874-2e91-4843-8b5d-3edad93c0ee1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609368911 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.3609368911
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.899690600
Short name T224
Test name
Test status
Simulation time 32073476321 ps
CPU time 40.65 seconds
Started Mar 07 01:00:54 PM PST 24
Finished Mar 07 01:01:35 PM PST 24
Peak memory 211988 kb
Host smart-583b423e-983e-4ed1-9880-947808a04bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899690600 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.899690600
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.4251857687
Short name T208
Test name
Test status
Simulation time 1733662593 ps
CPU time 3.75 seconds
Started Mar 07 01:00:53 PM PST 24
Finished Mar 07 01:00:57 PM PST 24
Peak memory 203624 kb
Host smart-12034d51-3937-4fbf-a133-a8cfc3441c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251857687 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.4251857687
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.3124438149
Short name T172
Test name
Test status
Simulation time 1308033427 ps
CPU time 3.66 seconds
Started Mar 07 01:00:57 PM PST 24
Finished Mar 07 01:01:01 PM PST 24
Peak memory 203544 kb
Host smart-cde2280c-684a-4d1a-9455-0cc79fa986e8
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3124438149 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t
l_access.3124438149
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.1816862377
Short name T220
Test name
Test status
Simulation time 3495409232 ps
CPU time 5.21 seconds
Started Mar 07 01:00:53 PM PST 24
Finished Mar 07 01:00:59 PM PST 24
Peak memory 203624 kb
Host smart-b5e24ce4-0f60-42f7-9453-3f18e43ab983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816862377 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.1816862377
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_stress_all.909036063
Short name T142
Test name
Test status
Simulation time 3999204082 ps
CPU time 4.54 seconds
Started Mar 07 01:00:50 PM PST 24
Finished Mar 07 01:00:55 PM PST 24
Peak memory 203532 kb
Host smart-7784fbe6-04e6-4c45-90eb-89a02c66aaac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909036063 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.909036063
Directory /workspace/6.rv_dm_stress_all/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.3750060466
Short name T169
Test name
Test status
Simulation time 52704841 ps
CPU time 0.68 seconds
Started Mar 07 01:00:49 PM PST 24
Finished Mar 07 01:00:51 PM PST 24
Peak memory 203332 kb
Host smart-ff3502d9-a98f-4f80-88c9-dbd9a97b8844
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750060466 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.3750060466
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.3774472676
Short name T117
Test name
Test status
Simulation time 486855242 ps
CPU time 2.59 seconds
Started Mar 07 01:00:57 PM PST 24
Finished Mar 07 01:01:01 PM PST 24
Peak memory 203776 kb
Host smart-5720ef5f-68ee-40eb-adff-1b005b8bd5ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774472676 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.3774472676
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.4116351668
Short name T185
Test name
Test status
Simulation time 6064537119 ps
CPU time 12.62 seconds
Started Mar 07 01:00:50 PM PST 24
Finished Mar 07 01:01:03 PM PST 24
Peak memory 203744 kb
Host smart-39a5ca92-3f98-4ef7-8900-70c939ba7bf1
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4116351668 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.4116351668
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.519064423
Short name T67
Test name
Test status
Simulation time 3574373323 ps
CPU time 8.76 seconds
Started Mar 07 01:00:54 PM PST 24
Finished Mar 07 01:01:03 PM PST 24
Peak memory 203700 kb
Host smart-e61f5f7d-6883-4aea-83f5-95ba67f35a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519064423 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.519064423
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.2267475727
Short name T159
Test name
Test status
Simulation time 48158233 ps
CPU time 0.66 seconds
Started Mar 07 01:00:56 PM PST 24
Finished Mar 07 01:00:57 PM PST 24
Peak memory 203388 kb
Host smart-384d6f12-78b1-44ea-a8ad-f4529a3d5671
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267475727 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.2267475727
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.939862420
Short name T214
Test name
Test status
Simulation time 34975514346 ps
CPU time 98.59 seconds
Started Mar 07 01:00:54 PM PST 24
Finished Mar 07 01:02:33 PM PST 24
Peak memory 203700 kb
Host smart-aa5f0cd1-5fd2-42e1-b334-c298b06d5a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939862420 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.939862420
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.164548628
Short name T206
Test name
Test status
Simulation time 1879688570 ps
CPU time 6 seconds
Started Mar 07 01:00:57 PM PST 24
Finished Mar 07 01:01:04 PM PST 24
Peak memory 203640 kb
Host smart-5ac84c06-0533-49e2-887e-ffd8e914fc40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164548628 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.164548628
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.3598397084
Short name T85
Test name
Test status
Simulation time 1901852835 ps
CPU time 1.85 seconds
Started Mar 07 01:00:50 PM PST 24
Finished Mar 07 01:00:52 PM PST 24
Peak memory 203720 kb
Host smart-59db0830-e998-4447-b275-188d31b410af
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3598397084 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t
l_access.3598397084
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.3362153459
Short name T217
Test name
Test status
Simulation time 4288360913 ps
CPU time 8.1 seconds
Started Mar 07 01:00:50 PM PST 24
Finished Mar 07 01:00:58 PM PST 24
Peak memory 203736 kb
Host smart-c5137e08-8531-42bb-9786-6fda9e76b2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362153459 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.3362153459
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.3168537702
Short name T151
Test name
Test status
Simulation time 42080439 ps
CPU time 0.66 seconds
Started Mar 07 01:00:52 PM PST 24
Finished Mar 07 01:00:53 PM PST 24
Peak memory 203412 kb
Host smart-446474ec-0e1b-48df-a385-0eda2ad1e3b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168537702 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.3168537702
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.1678548494
Short name T186
Test name
Test status
Simulation time 12655596278 ps
CPU time 47.83 seconds
Started Mar 07 01:01:04 PM PST 24
Finished Mar 07 01:01:52 PM PST 24
Peak memory 203740 kb
Host smart-ab906d5f-8dac-4d66-bd6b-1d2905346d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678548494 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.1678548494
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.2738432503
Short name T203
Test name
Test status
Simulation time 11972779714 ps
CPU time 24.41 seconds
Started Mar 07 01:00:54 PM PST 24
Finished Mar 07 01:01:19 PM PST 24
Peak memory 203688 kb
Host smart-ab2428f8-42c5-442e-9fa5-860583fb5bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738432503 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.2738432503
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.2531628007
Short name T194
Test name
Test status
Simulation time 4646522448 ps
CPU time 17.9 seconds
Started Mar 07 01:00:53 PM PST 24
Finished Mar 07 01:01:12 PM PST 24
Peak memory 203708 kb
Host smart-afcb4182-afdc-42d8-908c-673e5f326f33
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2531628007 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t
l_access.2531628007
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.2712714594
Short name T240
Test name
Test status
Simulation time 1753697997 ps
CPU time 8.74 seconds
Started Mar 07 01:01:02 PM PST 24
Finished Mar 07 01:01:11 PM PST 24
Peak memory 203668 kb
Host smart-932c8ae0-04fc-46f6-86e3-4f67d51e89f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712714594 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.2712714594
Directory /workspace/9.rv_dm_sba_tl_access/latest
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