Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
87.15 92.68 76.55 89.19 75.64 82.89 97.75 95.34


Total test records in report: 367
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html
T268 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.446613730 Mar 12 02:51:56 PM PDT 24 Mar 12 02:52:01 PM PDT 24 1723216719 ps
T269 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.3522491622 Mar 12 02:51:46 PM PDT 24 Mar 12 02:51:47 PM PDT 24 29017580 ps
T270 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.801218958 Mar 12 02:51:59 PM PDT 24 Mar 12 02:52:02 PM PDT 24 1135982467 ps
T103 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.2771297929 Mar 12 02:52:32 PM PDT 24 Mar 12 02:52:34 PM PDT 24 101394322 ps
T271 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3188606569 Mar 12 02:51:56 PM PDT 24 Mar 12 02:52:00 PM PDT 24 2044275783 ps
T104 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.2199355102 Mar 12 02:51:57 PM PDT 24 Mar 12 02:51:58 PM PDT 24 305749789 ps
T272 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.353081407 Mar 12 02:52:03 PM PDT 24 Mar 12 02:52:04 PM PDT 24 343480170 ps
T273 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.4216565698 Mar 12 02:52:23 PM PDT 24 Mar 12 02:52:24 PM PDT 24 74280330 ps
T274 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.880348410 Mar 12 02:51:58 PM PDT 24 Mar 12 02:51:59 PM PDT 24 19782018 ps
T275 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.3539137080 Mar 12 02:51:44 PM PDT 24 Mar 12 02:51:46 PM PDT 24 51072415 ps
T276 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1698715090 Mar 12 02:52:08 PM PDT 24 Mar 12 02:52:14 PM PDT 24 2106816585 ps
T277 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3759527350 Mar 12 02:52:17 PM PDT 24 Mar 12 02:52:25 PM PDT 24 732353618 ps
T278 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3868132247 Mar 12 02:51:46 PM PDT 24 Mar 12 02:51:52 PM PDT 24 3644932077 ps
T279 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.57494289 Mar 12 02:51:52 PM PDT 24 Mar 12 02:51:54 PM PDT 24 41724810 ps
T97 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.142623772 Mar 12 02:52:28 PM PDT 24 Mar 12 02:52:36 PM PDT 24 1030344737 ps
T280 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.3991849370 Mar 12 02:52:03 PM PDT 24 Mar 12 02:52:07 PM PDT 24 440799544 ps
T122 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.4109961698 Mar 12 02:52:08 PM PDT 24 Mar 12 02:52:25 PM PDT 24 6165016432 ps
T281 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.855234659 Mar 12 02:51:45 PM PDT 24 Mar 12 02:51:46 PM PDT 24 144279260 ps
T282 /workspace/coverage/cover_reg_top/19.rv_dm_tap_fsm_rand_reset.3040960420 Mar 12 02:52:30 PM PDT 24 Mar 12 02:52:44 PM PDT 24 15376107426 ps
T117 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.907755708 Mar 12 02:52:17 PM PDT 24 Mar 12 02:52:34 PM PDT 24 3893490839 ps
T93 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2052025563 Mar 12 02:51:52 PM PDT 24 Mar 12 02:51:55 PM PDT 24 1403964467 ps
T283 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.866399096 Mar 12 02:52:05 PM PDT 24 Mar 12 02:52:10 PM PDT 24 1524238062 ps
T284 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.3740492769 Mar 12 02:52:23 PM PDT 24 Mar 12 02:52:26 PM PDT 24 244277916 ps
T285 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.3491436354 Mar 12 02:52:15 PM PDT 24 Mar 12 02:52:18 PM PDT 24 400014363 ps
T115 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.330637878 Mar 12 02:52:10 PM PDT 24 Mar 12 02:52:17 PM PDT 24 146468697 ps
T286 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3880936619 Mar 12 02:51:55 PM PDT 24 Mar 12 02:52:40 PM PDT 24 19816719240 ps
T287 /workspace/coverage/cover_reg_top/38.rv_dm_tap_fsm_rand_reset.316722452 Mar 12 02:52:31 PM PDT 24 Mar 12 02:52:58 PM PDT 24 33801436420 ps
T94 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2514330838 Mar 12 02:51:56 PM PDT 24 Mar 12 02:51:57 PM PDT 24 584350086 ps
T288 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.4159817207 Mar 12 02:51:47 PM PDT 24 Mar 12 02:51:48 PM PDT 24 65839190 ps
T125 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.1079352281 Mar 12 02:52:23 PM PDT 24 Mar 12 02:52:33 PM PDT 24 981511477 ps
T289 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.3000757802 Mar 12 02:52:07 PM PDT 24 Mar 12 02:52:10 PM PDT 24 171401282 ps
T290 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.3393517959 Mar 12 02:51:56 PM PDT 24 Mar 12 02:52:03 PM PDT 24 418332150 ps
T291 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.4264792194 Mar 12 02:52:08 PM PDT 24 Mar 12 02:52:09 PM PDT 24 88910956 ps
T292 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2500396117 Mar 12 02:52:23 PM PDT 24 Mar 12 02:52:27 PM PDT 24 575296759 ps
T293 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2727570571 Mar 12 02:51:45 PM PDT 24 Mar 12 02:51:46 PM PDT 24 100424446 ps
T294 /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.2416762451 Mar 12 02:52:00 PM PDT 24 Mar 12 02:52:13 PM PDT 24 13187093607 ps
T295 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.134734819 Mar 12 02:52:28 PM PDT 24 Mar 12 02:52:33 PM PDT 24 394966484 ps
T296 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2016073150 Mar 12 02:51:42 PM PDT 24 Mar 12 02:51:45 PM PDT 24 1556935114 ps
T297 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.4165300862 Mar 12 02:52:03 PM PDT 24 Mar 12 02:52:07 PM PDT 24 705602763 ps
T298 /workspace/coverage/cover_reg_top/36.rv_dm_tap_fsm_rand_reset.3066133833 Mar 12 02:52:29 PM PDT 24 Mar 12 02:52:44 PM PDT 24 12872180770 ps
T299 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3722141712 Mar 12 02:52:30 PM PDT 24 Mar 12 02:52:31 PM PDT 24 92387160 ps
T105 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.2231260233 Mar 12 02:52:27 PM PDT 24 Mar 12 02:52:30 PM PDT 24 40412572 ps
T300 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.870183863 Mar 12 02:51:59 PM PDT 24 Mar 12 02:52:03 PM PDT 24 808627176 ps
T301 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.954578982 Mar 12 02:51:51 PM PDT 24 Mar 12 02:51:53 PM PDT 24 370647301 ps
T302 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2372865586 Mar 12 02:52:32 PM PDT 24 Mar 12 02:52:37 PM PDT 24 451702637 ps
T303 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.52144442 Mar 12 02:52:00 PM PDT 24 Mar 12 02:52:03 PM PDT 24 52781922 ps
T304 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3843578173 Mar 12 02:52:23 PM PDT 24 Mar 12 02:52:25 PM PDT 24 1067385852 ps
T305 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.2559966704 Mar 12 02:52:10 PM PDT 24 Mar 12 02:52:10 PM PDT 24 108144530 ps
T306 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.2023985469 Mar 12 02:52:23 PM PDT 24 Mar 12 02:52:25 PM PDT 24 57981919 ps
T307 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.3678835046 Mar 12 02:51:58 PM PDT 24 Mar 12 02:52:00 PM PDT 24 93114049 ps
T308 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.744196770 Mar 12 02:51:43 PM PDT 24 Mar 12 02:51:49 PM PDT 24 1985698776 ps
T309 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.84730303 Mar 12 02:52:31 PM PDT 24 Mar 12 02:52:33 PM PDT 24 464933179 ps
T310 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.767835587 Mar 12 02:51:38 PM PDT 24 Mar 12 02:52:24 PM PDT 24 19308639773 ps
T311 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.149510157 Mar 12 02:51:45 PM PDT 24 Mar 12 02:51:46 PM PDT 24 108103123 ps
T312 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.585407018 Mar 12 02:52:13 PM PDT 24 Mar 12 02:52:16 PM PDT 24 82890148 ps
T313 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.662407682 Mar 12 02:51:51 PM PDT 24 Mar 12 02:53:06 PM PDT 24 16906267769 ps
T314 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.439295323 Mar 12 02:51:49 PM PDT 24 Mar 12 02:51:50 PM PDT 24 37481760 ps
T121 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3340681720 Mar 12 02:52:31 PM PDT 24 Mar 12 02:52:39 PM PDT 24 220998581 ps
T315 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.228070402 Mar 12 02:51:57 PM PDT 24 Mar 12 02:53:02 PM PDT 24 20032741139 ps
T316 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2469037450 Mar 12 02:52:02 PM PDT 24 Mar 12 02:52:03 PM PDT 24 105862048 ps
T317 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1428007696 Mar 12 02:52:15 PM PDT 24 Mar 12 02:52:16 PM PDT 24 30995606 ps
T318 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.3417739553 Mar 12 02:52:23 PM PDT 24 Mar 12 02:52:25 PM PDT 24 156489920 ps
T319 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3420150301 Mar 12 02:51:51 PM PDT 24 Mar 12 02:51:52 PM PDT 24 58258834 ps
T320 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.1733416627 Mar 12 02:52:16 PM PDT 24 Mar 12 02:52:18 PM PDT 24 439797951 ps
T321 /workspace/coverage/cover_reg_top/27.rv_dm_tap_fsm_rand_reset.1504168098 Mar 12 02:52:30 PM PDT 24 Mar 12 02:52:42 PM PDT 24 12312059802 ps
T106 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.86580269 Mar 12 02:52:11 PM PDT 24 Mar 12 02:52:12 PM PDT 24 215621506 ps
T322 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.375637363 Mar 12 02:52:09 PM PDT 24 Mar 12 02:52:11 PM PDT 24 624632487 ps
T323 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.2937741405 Mar 12 02:52:01 PM PDT 24 Mar 12 02:52:16 PM PDT 24 5057466633 ps
T324 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.21820865 Mar 12 02:51:47 PM PDT 24 Mar 12 02:51:48 PM PDT 24 34458339 ps
T325 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.4291250789 Mar 12 02:52:10 PM PDT 24 Mar 12 02:52:14 PM PDT 24 246275369 ps
T326 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2459599362 Mar 12 02:52:22 PM PDT 24 Mar 12 02:52:23 PM PDT 24 185825264 ps
T327 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2271317893 Mar 12 02:52:05 PM PDT 24 Mar 12 02:52:10 PM PDT 24 2597738924 ps
T328 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.4069051959 Mar 12 02:51:46 PM PDT 24 Mar 12 02:51:47 PM PDT 24 231543760 ps
T329 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.237406733 Mar 12 02:52:30 PM PDT 24 Mar 12 02:52:32 PM PDT 24 27095656 ps
T124 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.677332732 Mar 12 02:52:22 PM PDT 24 Mar 12 02:52:32 PM PDT 24 520167514 ps
T330 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.1438214365 Mar 12 02:52:05 PM PDT 24 Mar 12 02:52:07 PM PDT 24 110547026 ps
T331 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1720917193 Mar 12 02:51:57 PM PDT 24 Mar 12 02:52:04 PM PDT 24 595609291 ps
T332 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.1191275990 Mar 12 02:51:57 PM PDT 24 Mar 12 02:52:06 PM PDT 24 2447400814 ps
T333 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2668846584 Mar 12 02:52:24 PM PDT 24 Mar 12 02:52:24 PM PDT 24 52575427 ps
T334 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.28265192 Mar 12 02:51:48 PM PDT 24 Mar 12 02:51:57 PM PDT 24 1759605587 ps
T335 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.119810918 Mar 12 02:51:49 PM PDT 24 Mar 12 02:52:33 PM PDT 24 11370131121 ps
T336 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.2902280550 Mar 12 02:52:21 PM PDT 24 Mar 12 02:52:24 PM PDT 24 84096574 ps
T337 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3969131881 Mar 12 02:51:50 PM PDT 24 Mar 12 02:51:52 PM PDT 24 75249650 ps
T338 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.3360701926 Mar 12 02:52:23 PM PDT 24 Mar 12 02:52:27 PM PDT 24 301828531 ps
T339 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.3596826148 Mar 12 02:52:03 PM PDT 24 Mar 12 02:52:06 PM PDT 24 169663897 ps
T98 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.2816685697 Mar 12 02:52:16 PM PDT 24 Mar 12 02:52:23 PM PDT 24 6292974688 ps
T340 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.2499630531 Mar 12 02:51:53 PM PDT 24 Mar 12 02:51:55 PM PDT 24 1118715323 ps
T341 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.3803468177 Mar 12 02:52:29 PM PDT 24 Mar 12 02:52:36 PM PDT 24 141926432 ps
T118 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.1033380197 Mar 12 02:51:51 PM PDT 24 Mar 12 02:52:01 PM PDT 24 1737723848 ps
T342 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.754649452 Mar 12 02:51:45 PM PDT 24 Mar 12 02:51:45 PM PDT 24 21794010 ps
T343 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.947693669 Mar 12 02:51:58 PM PDT 24 Mar 12 02:51:59 PM PDT 24 99304016 ps
T119 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.3257633372 Mar 12 02:51:58 PM PDT 24 Mar 12 02:52:13 PM PDT 24 1059219868 ps
T344 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.2888191457 Mar 12 02:52:25 PM PDT 24 Mar 12 02:52:28 PM PDT 24 420625270 ps
T345 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.403702891 Mar 12 02:51:44 PM PDT 24 Mar 12 02:52:49 PM PDT 24 4463159166 ps
T346 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3337320326 Mar 12 02:51:57 PM PDT 24 Mar 12 02:51:58 PM PDT 24 146266785 ps
T126 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.465294530 Mar 12 02:52:34 PM PDT 24 Mar 12 02:52:55 PM PDT 24 3742125053 ps
T347 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.3377743326 Mar 12 02:52:24 PM PDT 24 Mar 12 02:52:26 PM PDT 24 978361563 ps
T348 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.1765385255 Mar 12 02:52:08 PM PDT 24 Mar 12 02:52:11 PM PDT 24 416112053 ps
T349 /workspace/coverage/cover_reg_top/35.rv_dm_tap_fsm_rand_reset.927065898 Mar 12 02:52:30 PM PDT 24 Mar 12 02:52:52 PM PDT 24 6564238639 ps
T350 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.2531920813 Mar 12 02:51:44 PM PDT 24 Mar 12 02:51:45 PM PDT 24 18765387 ps
T351 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.1976397238 Mar 12 02:52:17 PM PDT 24 Mar 12 02:52:23 PM PDT 24 149344113 ps
T352 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.2189351834 Mar 12 02:52:22 PM PDT 24 Mar 12 02:52:26 PM PDT 24 226083480 ps
T353 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.4206373605 Mar 12 02:51:58 PM PDT 24 Mar 12 02:52:01 PM PDT 24 219885369 ps
T354 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.4137722996 Mar 12 02:52:00 PM PDT 24 Mar 12 02:52:01 PM PDT 24 17365247 ps
T355 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2265152405 Mar 12 02:51:59 PM PDT 24 Mar 12 02:52:25 PM PDT 24 595599457 ps
T356 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.2923764020 Mar 12 02:51:56 PM PDT 24 Mar 12 02:52:46 PM PDT 24 1455217189 ps
T357 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.4012197959 Mar 12 02:52:28 PM PDT 24 Mar 12 02:52:36 PM PDT 24 500045755 ps
T358 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.1874291522 Mar 12 02:52:22 PM PDT 24 Mar 12 02:52:25 PM PDT 24 136571390 ps
T359 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.2037057604 Mar 12 02:51:40 PM PDT 24 Mar 12 02:52:56 PM PDT 24 21596254143 ps
T360 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.415893800 Mar 12 02:51:56 PM PDT 24 Mar 12 02:51:57 PM PDT 24 57246165 ps
T361 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.1943998125 Mar 12 02:52:14 PM PDT 24 Mar 12 02:52:17 PM PDT 24 138557550 ps
T362 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.3515299750 Mar 12 02:51:57 PM PDT 24 Mar 12 02:52:00 PM PDT 24 1675170206 ps
T363 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2575821165 Mar 12 02:51:52 PM PDT 24 Mar 12 02:51:55 PM PDT 24 1849782819 ps
T364 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.619330683 Mar 12 02:52:09 PM PDT 24 Mar 12 02:52:12 PM PDT 24 876816024 ps
T365 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.2393283829 Mar 12 02:51:58 PM PDT 24 Mar 12 02:52:25 PM PDT 24 1037412884 ps
T366 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.573802636 Mar 12 02:52:32 PM PDT 24 Mar 12 02:52:43 PM PDT 24 5504241403 ps
T367 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2616849311 Mar 12 02:52:28 PM PDT 24 Mar 12 02:52:29 PM PDT 24 73035077 ps

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.2040940961
Short name T11
Test name
Test status
Simulation time 5478537963 ps
CPU time 8.05 seconds
Started Mar 12 12:30:59 PM PDT 24
Finished Mar 12 12:31:08 PM PDT 24
Peak memory 203592 kb
Host smart-8f9e6756-0f74-4dda-8619-8924d43b462e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040940961 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.2040940961
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/34.rv_dm_stress_all.4135911672
Short name T5
Test name
Test status
Simulation time 2851710520 ps
CPU time 5.26 seconds
Started Mar 12 12:30:55 PM PDT 24
Finished Mar 12 12:31:00 PM PDT 24
Peak memory 203348 kb
Host smart-a4343a28-848e-4f64-8835-5cc37a33188a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135911672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.4135911672
Directory /workspace/34.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.716017516
Short name T50
Test name
Test status
Simulation time 107792969 ps
CPU time 4.07 seconds
Started Mar 12 02:52:08 PM PDT 24
Finished Mar 12 02:52:13 PM PDT 24
Peak memory 216036 kb
Host smart-7dd0e690-2425-418b-b1a4-e917e3d8219a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716017516 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.716017516
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.4004016911
Short name T30
Test name
Test status
Simulation time 45872509 ps
CPU time 0.67 seconds
Started Mar 12 12:31:17 PM PDT 24
Finished Mar 12 12:31:18 PM PDT 24
Peak memory 203188 kb
Host smart-84673372-9828-42b9-b157-1449c1a60dfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004016911 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.4004016911
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tap_fsm_rand_reset.541216068
Short name T89
Test name
Test status
Simulation time 16795772974 ps
CPU time 33.17 seconds
Started Mar 12 02:52:23 PM PDT 24
Finished Mar 12 02:52:56 PM PDT 24
Peak memory 220092 kb
Host smart-58fb032b-ad78-4d46-a769-5d685373d492
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541216068 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.rv_dm_tap_fsm_rand_reset.541216068
Directory /workspace/13.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/11.rv_dm_stress_all.335332352
Short name T4
Test name
Test status
Simulation time 3297482891 ps
CPU time 11.58 seconds
Started Mar 12 12:30:46 PM PDT 24
Finished Mar 12 12:30:57 PM PDT 24
Peak memory 203356 kb
Host smart-7060b490-ae86-419b-9d94-b38e2065e5df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335332352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.335332352
Directory /workspace/11.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.4098748374
Short name T42
Test name
Test status
Simulation time 686154205 ps
CPU time 8.12 seconds
Started Mar 12 02:51:59 PM PDT 24
Finished Mar 12 02:52:08 PM PDT 24
Peak memory 212292 kb
Host smart-5e27bff7-1288-4d01-b152-21fa062f9b1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098748374 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.4098748374
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.1117046657
Short name T21
Test name
Test status
Simulation time 40405540921 ps
CPU time 54.31 seconds
Started Mar 12 12:30:44 PM PDT 24
Finished Mar 12 12:31:38 PM PDT 24
Peak memory 211752 kb
Host smart-5357c8a6-f814-4ee8-bc53-071ad861f357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117046657 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.1117046657
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.3679712722
Short name T43
Test name
Test status
Simulation time 3413714120 ps
CPU time 17.61 seconds
Started Mar 12 02:52:02 PM PDT 24
Finished Mar 12 02:52:20 PM PDT 24
Peak memory 214132 kb
Host smart-e7c2856d-550d-4bbb-a419-d005e96de339
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679712722 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.3679712722
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.779926306
Short name T58
Test name
Test status
Simulation time 6999692720 ps
CPU time 73.8 seconds
Started Mar 12 02:51:46 PM PDT 24
Finished Mar 12 02:53:00 PM PDT 24
Peak memory 204072 kb
Host smart-2d09fcd2-d6ae-4a3d-b0e6-4089f47b63c9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779926306 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.rv_dm_csr_aliasing.779926306
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.3070078476
Short name T29
Test name
Test status
Simulation time 51850200 ps
CPU time 0.79 seconds
Started Mar 12 12:30:34 PM PDT 24
Finished Mar 12 12:30:35 PM PDT 24
Peak memory 203228 kb
Host smart-f098c907-1b7d-4e40-9fd6-2c6deb33e3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070078476 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.3070078476
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.3597243487
Short name T40
Test name
Test status
Simulation time 287575476 ps
CPU time 1.01 seconds
Started Mar 12 12:30:45 PM PDT 24
Finished Mar 12 12:30:47 PM PDT 24
Peak memory 218292 kb
Host smart-0ff751d0-2a06-4433-9ee2-16775d639e0b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597243487 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.3597243487
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.3695702639
Short name T33
Test name
Test status
Simulation time 125107657 ps
CPU time 0.75 seconds
Started Mar 12 12:30:41 PM PDT 24
Finished Mar 12 12:30:43 PM PDT 24
Peak memory 202964 kb
Host smart-5070f18d-2fc4-4468-8d53-8bf62dc31688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695702639 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.3695702639
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.3764489540
Short name T75
Test name
Test status
Simulation time 118079777 ps
CPU time 0.71 seconds
Started Mar 12 02:52:23 PM PDT 24
Finished Mar 12 02:52:24 PM PDT 24
Peak memory 203660 kb
Host smart-39bb8da9-fa26-4b15-8b20-78ee5a8be47b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764489540 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
3764489540
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.907755708
Short name T117
Test name
Test status
Simulation time 3893490839 ps
CPU time 16.8 seconds
Started Mar 12 02:52:17 PM PDT 24
Finished Mar 12 02:52:34 PM PDT 24
Peak memory 212828 kb
Host smart-2b1c8390-4516-4966-af77-f0345fa4a7cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907755708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.907755708
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.684320569
Short name T53
Test name
Test status
Simulation time 47489311 ps
CPU time 0.69 seconds
Started Mar 12 12:31:08 PM PDT 24
Finished Mar 12 12:31:09 PM PDT 24
Peak memory 203156 kb
Host smart-e8d5a4b5-6ec5-4a96-8a0c-36da42d09982
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684320569 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.684320569
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1815448775
Short name T45
Test name
Test status
Simulation time 60257787 ps
CPU time 3.42 seconds
Started Mar 12 02:51:44 PM PDT 24
Finished Mar 12 02:51:48 PM PDT 24
Peak memory 204068 kb
Host smart-3e038390-802b-40e3-9c0e-1d9b610d1eb7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815448775 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.1815448775
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.1064856459
Short name T66
Test name
Test status
Simulation time 193957763 ps
CPU time 0.68 seconds
Started Mar 12 12:30:32 PM PDT 24
Finished Mar 12 12:30:32 PM PDT 24
Peak memory 203084 kb
Host smart-ae7e1643-34c3-40e5-9cdf-254cac4ef644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064856459 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.1064856459
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.3879272770
Short name T120
Test name
Test status
Simulation time 576545589 ps
CPU time 15.59 seconds
Started Mar 12 02:52:24 PM PDT 24
Finished Mar 12 02:52:40 PM PDT 24
Peak memory 212268 kb
Host smart-19c1afa3-1143-4094-b7a4-6f3cf89a800c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879272770 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.3
879272770
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3354744897
Short name T96
Test name
Test status
Simulation time 83672974 ps
CPU time 3.63 seconds
Started Mar 12 02:52:24 PM PDT 24
Finished Mar 12 02:52:27 PM PDT 24
Peak memory 204024 kb
Host smart-227a533b-bffd-4b68-b222-4be7d410aa61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354744897 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.3354744897
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3666372966
Short name T44
Test name
Test status
Simulation time 1369552344 ps
CPU time 10.66 seconds
Started Mar 12 02:52:21 PM PDT 24
Finished Mar 12 02:52:32 PM PDT 24
Peak memory 212240 kb
Host smart-6ddd11d4-67ba-413c-b585-989cbee0d2c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666372966 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.3
666372966
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.1079352281
Short name T125
Test name
Test status
Simulation time 981511477 ps
CPU time 10 seconds
Started Mar 12 02:52:23 PM PDT 24
Finished Mar 12 02:52:33 PM PDT 24
Peak memory 212424 kb
Host smart-082057f3-a3ba-4832-8bed-d2876bbc9eaf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079352281 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.1
079352281
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3340681720
Short name T121
Test name
Test status
Simulation time 220998581 ps
CPU time 8.19 seconds
Started Mar 12 02:52:31 PM PDT 24
Finished Mar 12 02:52:39 PM PDT 24
Peak memory 212156 kb
Host smart-5b09abb8-47da-4459-a596-1354f4cda46d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340681720 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.3
340681720
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.924447705
Short name T100
Test name
Test status
Simulation time 2049909758 ps
CPU time 31.12 seconds
Started Mar 12 02:51:37 PM PDT 24
Finished Mar 12 02:52:08 PM PDT 24
Peak memory 204012 kb
Host smart-076977d2-2151-4889-857d-833b487084c1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924447705 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.rv_dm_csr_aliasing.924447705
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2153311655
Short name T92
Test name
Test status
Simulation time 166888095 ps
CPU time 1.02 seconds
Started Mar 12 02:51:38 PM PDT 24
Finished Mar 12 02:51:39 PM PDT 24
Peak memory 203944 kb
Host smart-b14038ca-f5d4-4f08-b264-a472f86b7a9f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153311655 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.2153311655
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.3650518751
Short name T26
Test name
Test status
Simulation time 85111992 ps
CPU time 0.92 seconds
Started Mar 12 12:30:40 PM PDT 24
Finished Mar 12 12:30:41 PM PDT 24
Peak memory 202996 kb
Host smart-b1e8ad36-3c80-416c-a056-409920ed979b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650518751 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.3650518751
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.1101655246
Short name T14
Test name
Test status
Simulation time 3997205756 ps
CPU time 9.08 seconds
Started Mar 12 12:32:00 PM PDT 24
Finished Mar 12 12:32:09 PM PDT 24
Peak memory 203648 kb
Host smart-7aec1322-a36a-44aa-afd9-856226ba2df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101655246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.1101655246
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.3964329599
Short name T101
Test name
Test status
Simulation time 10105867096 ps
CPU time 34.47 seconds
Started Mar 12 02:51:44 PM PDT 24
Finished Mar 12 02:52:19 PM PDT 24
Peak memory 203892 kb
Host smart-1d754f63-739b-4699-bce7-64a61fd3887b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964329599 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.3964329599
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3450322869
Short name T83
Test name
Test status
Simulation time 121364568 ps
CPU time 1.44 seconds
Started Mar 12 02:51:46 PM PDT 24
Finished Mar 12 02:51:48 PM PDT 24
Peak memory 204028 kb
Host smart-408708a8-48ce-44db-809b-7baf05c68ed2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450322869 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.3450322869
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.613829180
Short name T262
Test name
Test status
Simulation time 719372896 ps
CPU time 2.25 seconds
Started Mar 12 02:51:47 PM PDT 24
Finished Mar 12 02:51:50 PM PDT 24
Peak memory 214044 kb
Host smart-93e85005-3086-4c98-94cb-2c3c144191d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613829180 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.613829180
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.311371206
Short name T55
Test name
Test status
Simulation time 424538298 ps
CPU time 2.15 seconds
Started Mar 12 02:51:45 PM PDT 24
Finished Mar 12 02:51:48 PM PDT 24
Peak memory 203992 kb
Host smart-95b18bf6-f90c-4ad4-8fe2-1f78cca4cf4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311371206 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.311371206
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.767835587
Short name T310
Test name
Test status
Simulation time 19308639773 ps
CPU time 45.84 seconds
Started Mar 12 02:51:38 PM PDT 24
Finished Mar 12 02:52:24 PM PDT 24
Peak memory 203832 kb
Host smart-9f7ee676-9e91-41eb-98fb-15ee0d6578c4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767835587 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr
_aliasing.767835587
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.2037057604
Short name T359
Test name
Test status
Simulation time 21596254143 ps
CPU time 75.88 seconds
Started Mar 12 02:51:40 PM PDT 24
Finished Mar 12 02:52:56 PM PDT 24
Peak memory 203844 kb
Host smart-6d203ed6-5eb9-449c-ae20-9376287e786f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037057604 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_bit_bash.2037057604
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2016073150
Short name T296
Test name
Test status
Simulation time 1556935114 ps
CPU time 2.3 seconds
Started Mar 12 02:51:42 PM PDT 24
Finished Mar 12 02:51:45 PM PDT 24
Peak memory 203816 kb
Host smart-603e104a-19c9-4fc2-bb76-e639b727c5fa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016073150 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.2
016073150
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3257368232
Short name T236
Test name
Test status
Simulation time 63069248 ps
CPU time 0.66 seconds
Started Mar 12 02:51:43 PM PDT 24
Finished Mar 12 02:51:44 PM PDT 24
Peak memory 203660 kb
Host smart-08870da9-d397-4b60-8b5d-db14cb4161d6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257368232 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.3257368232
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.2294724194
Short name T237
Test name
Test status
Simulation time 1743887267 ps
CPU time 4.14 seconds
Started Mar 12 02:51:44 PM PDT 24
Finished Mar 12 02:51:49 PM PDT 24
Peak memory 203800 kb
Host smart-042eefef-4542-46b3-98b0-58380bb97d89
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294724194 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.2294724194
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.149510157
Short name T311
Test name
Test status
Simulation time 108103123 ps
CPU time 0.7 seconds
Started Mar 12 02:51:45 PM PDT 24
Finished Mar 12 02:51:46 PM PDT 24
Peak memory 203668 kb
Host smart-c0cbda59-7b9a-46dc-b557-8e7d889bf1b9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149510157 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr
_hw_reset.149510157
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.855234659
Short name T281
Test name
Test status
Simulation time 144279260 ps
CPU time 0.82 seconds
Started Mar 12 02:51:45 PM PDT 24
Finished Mar 12 02:51:46 PM PDT 24
Peak memory 203624 kb
Host smart-ae385fe3-4e10-43bd-9e0b-6488490e4d2a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855234659 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.855234659
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.3522491622
Short name T269
Test name
Test status
Simulation time 29017580 ps
CPU time 0.63 seconds
Started Mar 12 02:51:46 PM PDT 24
Finished Mar 12 02:51:47 PM PDT 24
Peak memory 203668 kb
Host smart-3f35baac-b6c4-4c25-85b8-adadbafe45ad
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522491622 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.3522491622
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.2531920813
Short name T350
Test name
Test status
Simulation time 18765387 ps
CPU time 0.63 seconds
Started Mar 12 02:51:44 PM PDT 24
Finished Mar 12 02:51:45 PM PDT 24
Peak memory 203472 kb
Host smart-45451946-206e-428a-9ad2-76780ae7c152
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531920813 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.2531920813
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2200126014
Short name T107
Test name
Test status
Simulation time 416614215 ps
CPU time 7.25 seconds
Started Mar 12 02:51:46 PM PDT 24
Finished Mar 12 02:51:53 PM PDT 24
Peak memory 203952 kb
Host smart-f13b9940-617a-4b9d-89e7-8cea160b71d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200126014 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.2200126014
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.2058669315
Short name T69
Test name
Test status
Simulation time 200485780 ps
CPU time 5.04 seconds
Started Mar 12 02:51:38 PM PDT 24
Finished Mar 12 02:51:43 PM PDT 24
Peak memory 212280 kb
Host smart-566b27c3-37bf-47fd-be4b-91d8cc379754
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058669315 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.2058669315
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.28265192
Short name T334
Test name
Test status
Simulation time 1759605587 ps
CPU time 9.08 seconds
Started Mar 12 02:51:48 PM PDT 24
Finished Mar 12 02:51:57 PM PDT 24
Peak memory 212264 kb
Host smart-6a0eb93e-6029-4e4b-9549-6a7c2463cf13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28265192 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.28265192
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.1369267765
Short name T84
Test name
Test status
Simulation time 7561732553 ps
CPU time 37.36 seconds
Started Mar 12 02:51:48 PM PDT 24
Finished Mar 12 02:52:25 PM PDT 24
Peak memory 203884 kb
Host smart-3bd9826b-9a98-40cd-8e4a-5343b5ab6a14
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369267765 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.1369267765
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.3539137080
Short name T275
Test name
Test status
Simulation time 51072415 ps
CPU time 2.16 seconds
Started Mar 12 02:51:44 PM PDT 24
Finished Mar 12 02:51:46 PM PDT 24
Peak memory 204000 kb
Host smart-309f7024-7343-44bf-a17a-aa5a695bd8f3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539137080 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.3539137080
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3868132247
Short name T278
Test name
Test status
Simulation time 3644932077 ps
CPU time 5.7 seconds
Started Mar 12 02:51:46 PM PDT 24
Finished Mar 12 02:51:52 PM PDT 24
Peak memory 214440 kb
Host smart-2d4fed4c-51d8-4f65-a600-743ebe957351
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868132247 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.3868132247
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.3262953143
Short name T60
Test name
Test status
Simulation time 70871054 ps
CPU time 2.19 seconds
Started Mar 12 02:51:48 PM PDT 24
Finished Mar 12 02:51:50 PM PDT 24
Peak memory 212016 kb
Host smart-18e0abd2-bb74-4da9-996e-102cf16c5b54
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262953143 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.3262953143
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.119810918
Short name T335
Test name
Test status
Simulation time 11370131121 ps
CPU time 43.3 seconds
Started Mar 12 02:51:49 PM PDT 24
Finished Mar 12 02:52:33 PM PDT 24
Peak memory 203844 kb
Host smart-0c217652-ae6e-49c5-910b-46a3ae38f0a5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119810918 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr
_aliasing.119810918
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2078211523
Short name T238
Test name
Test status
Simulation time 32168997814 ps
CPU time 23.89 seconds
Started Mar 12 02:51:44 PM PDT 24
Finished Mar 12 02:52:09 PM PDT 24
Peak memory 203920 kb
Host smart-432e4515-6a2f-4108-948e-05645508758b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078211523 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_bit_bash.2078211523
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1916491993
Short name T91
Test name
Test status
Simulation time 2622139026 ps
CPU time 4.63 seconds
Started Mar 12 02:51:45 PM PDT 24
Finished Mar 12 02:51:50 PM PDT 24
Peak memory 203980 kb
Host smart-7172a6dd-106e-4af0-9d1f-b0d5b28cc513
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916491993 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.1916491993
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.4069051959
Short name T328
Test name
Test status
Simulation time 231543760 ps
CPU time 0.98 seconds
Started Mar 12 02:51:46 PM PDT 24
Finished Mar 12 02:51:47 PM PDT 24
Peak memory 203864 kb
Host smart-763ee16a-8e8a-42d5-bd68-ebf973c8429c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069051959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.4
069051959
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2843867385
Short name T235
Test name
Test status
Simulation time 48538406 ps
CPU time 0.78 seconds
Started Mar 12 02:51:46 PM PDT 24
Finished Mar 12 02:51:47 PM PDT 24
Peak memory 203464 kb
Host smart-feed3d0b-42c2-4afd-b2b5-ce17c3b3ab9f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843867385 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.2843867385
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.744196770
Short name T308
Test name
Test status
Simulation time 1985698776 ps
CPU time 6.59 seconds
Started Mar 12 02:51:43 PM PDT 24
Finished Mar 12 02:51:49 PM PDT 24
Peak memory 203748 kb
Host smart-1bc59a5e-ffb3-46ef-b4b4-5bf3f0bc809e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744196770 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_bit_bash.744196770
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.4159817207
Short name T288
Test name
Test status
Simulation time 65839190 ps
CPU time 0.72 seconds
Started Mar 12 02:51:47 PM PDT 24
Finished Mar 12 02:51:48 PM PDT 24
Peak memory 203648 kb
Host smart-5eee1892-6f4f-4067-b2d0-37e65f90e5fe
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159817207 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.4159817207
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.21820865
Short name T324
Test name
Test status
Simulation time 34458339 ps
CPU time 0.71 seconds
Started Mar 12 02:51:47 PM PDT 24
Finished Mar 12 02:51:48 PM PDT 24
Peak memory 203684 kb
Host smart-5000fb6e-7fc5-4f63-9160-c122b2c22d08
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21820865 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.21820865
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.754649452
Short name T342
Test name
Test status
Simulation time 21794010 ps
CPU time 0.67 seconds
Started Mar 12 02:51:45 PM PDT 24
Finished Mar 12 02:51:45 PM PDT 24
Peak memory 203544 kb
Host smart-b9a2e781-fbec-4e5f-9b1c-d6aeb33a5b85
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754649452 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_part
ial_access.754649452
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.439295323
Short name T314
Test name
Test status
Simulation time 37481760 ps
CPU time 0.63 seconds
Started Mar 12 02:51:49 PM PDT 24
Finished Mar 12 02:51:50 PM PDT 24
Peak memory 203608 kb
Host smart-fbc51fcc-ec7e-42c6-aa6d-a596821dd253
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439295323 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.439295323
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2337164619
Short name T114
Test name
Test status
Simulation time 163601220 ps
CPU time 3.51 seconds
Started Mar 12 02:51:45 PM PDT 24
Finished Mar 12 02:51:48 PM PDT 24
Peak memory 204092 kb
Host smart-7dd0c251-d96e-4fb6-ab84-4941ddf341c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337164619 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_
csr_outstanding.2337164619
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.2232711741
Short name T80
Test name
Test status
Simulation time 446266288 ps
CPU time 9.68 seconds
Started Mar 12 02:51:45 PM PDT 24
Finished Mar 12 02:51:55 PM PDT 24
Peak memory 212220 kb
Host smart-459dd335-c1eb-4c2b-99d9-5d4410741aeb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232711741 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.2232711741
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.619330683
Short name T364
Test name
Test status
Simulation time 876816024 ps
CPU time 2.54 seconds
Started Mar 12 02:52:09 PM PDT 24
Finished Mar 12 02:52:12 PM PDT 24
Peak memory 212296 kb
Host smart-95798f9a-3df4-46e4-a278-b5ac1e3870db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619330683 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.619330683
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.86580269
Short name T106
Test name
Test status
Simulation time 215621506 ps
CPU time 1.34 seconds
Started Mar 12 02:52:11 PM PDT 24
Finished Mar 12 02:52:12 PM PDT 24
Peak memory 204036 kb
Host smart-2e357a8f-5503-46c1-8b76-89b129f00fb0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86580269 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.86580269
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.375637363
Short name T322
Test name
Test status
Simulation time 624632487 ps
CPU time 1.69 seconds
Started Mar 12 02:52:09 PM PDT 24
Finished Mar 12 02:52:11 PM PDT 24
Peak memory 203784 kb
Host smart-a9bbf412-9542-4406-acaf-2cd81fc94379
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375637363 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.375637363
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.2559966704
Short name T305
Test name
Test status
Simulation time 108144530 ps
CPU time 0.66 seconds
Started Mar 12 02:52:10 PM PDT 24
Finished Mar 12 02:52:10 PM PDT 24
Peak memory 203672 kb
Host smart-8cb0af0a-15d0-4679-b6cd-4b94cdde1580
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559966704 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
2559966704
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.330637878
Short name T115
Test name
Test status
Simulation time 146468697 ps
CPU time 6.71 seconds
Started Mar 12 02:52:10 PM PDT 24
Finished Mar 12 02:52:17 PM PDT 24
Peak memory 204052 kb
Host smart-ffb842bd-b13e-4552-9a6d-0ec732c24170
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330637878 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same_
csr_outstanding.330637878
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tap_fsm_rand_reset.2420671590
Short name T46
Test name
Test status
Simulation time 6409238585 ps
CPU time 22.09 seconds
Started Mar 12 02:52:10 PM PDT 24
Finished Mar 12 02:52:33 PM PDT 24
Peak memory 212372 kb
Host smart-5359202b-8835-4cbc-83de-7f5ec5657973
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420671590 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rv_dm_tap_fsm_rand_reset.2420671590
Directory /workspace/10.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.4186226548
Short name T88
Test name
Test status
Simulation time 140264615 ps
CPU time 4.02 seconds
Started Mar 12 02:52:08 PM PDT 24
Finished Mar 12 02:52:12 PM PDT 24
Peak memory 212344 kb
Host smart-55a14dbd-5573-448d-95bb-56b00f1e383d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186226548 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.4186226548
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.4160638835
Short name T77
Test name
Test status
Simulation time 245900020 ps
CPU time 8.28 seconds
Started Mar 12 02:52:09 PM PDT 24
Finished Mar 12 02:52:17 PM PDT 24
Peak memory 212280 kb
Host smart-1e18059d-2bcb-4079-8cfd-2e6a0f053d7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160638835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.4
160638835
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1698715090
Short name T276
Test name
Test status
Simulation time 2106816585 ps
CPU time 5.77 seconds
Started Mar 12 02:52:08 PM PDT 24
Finished Mar 12 02:52:14 PM PDT 24
Peak memory 215336 kb
Host smart-c44fbdf9-4577-402f-86f8-55ae152dbc25
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698715090 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.1698715090
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.1016624340
Short name T56
Test name
Test status
Simulation time 225583642 ps
CPU time 1.51 seconds
Started Mar 12 02:52:12 PM PDT 24
Finished Mar 12 02:52:13 PM PDT 24
Peak memory 212176 kb
Host smart-70301915-2f4c-49a7-858c-e697450aed94
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016624340 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.1016624340
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.175168379
Short name T261
Test name
Test status
Simulation time 160967405 ps
CPU time 0.9 seconds
Started Mar 12 02:52:09 PM PDT 24
Finished Mar 12 02:52:10 PM PDT 24
Peak memory 203752 kb
Host smart-79187110-c404-4d14-927b-f6705513977d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175168379 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.175168379
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.4264792194
Short name T291
Test name
Test status
Simulation time 88910956 ps
CPU time 0.83 seconds
Started Mar 12 02:52:08 PM PDT 24
Finished Mar 12 02:52:09 PM PDT 24
Peak memory 203628 kb
Host smart-efe278dc-68d4-4e9c-9771-510d4883bbc3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264792194 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.
4264792194
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.585407018
Short name T312
Test name
Test status
Simulation time 82890148 ps
CPU time 3.62 seconds
Started Mar 12 02:52:13 PM PDT 24
Finished Mar 12 02:52:16 PM PDT 24
Peak memory 203956 kb
Host smart-c3207a38-e830-41b9-a247-dd6fffe1a2b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585407018 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same_
csr_outstanding.585407018
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.4291250789
Short name T325
Test name
Test status
Simulation time 246275369 ps
CPU time 3.82 seconds
Started Mar 12 02:52:10 PM PDT 24
Finished Mar 12 02:52:14 PM PDT 24
Peak memory 204092 kb
Host smart-c7f613c1-50cb-4a4e-b362-50466b35cb24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291250789 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.4291250789
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.4109961698
Short name T122
Test name
Test status
Simulation time 6165016432 ps
CPU time 16.36 seconds
Started Mar 12 02:52:08 PM PDT 24
Finished Mar 12 02:52:25 PM PDT 24
Peak memory 212996 kb
Host smart-b0dd1502-3684-48c2-aa36-30b217d66f39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109961698 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.4
109961698
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.3740492769
Short name T284
Test name
Test status
Simulation time 244277916 ps
CPU time 3.36 seconds
Started Mar 12 02:52:23 PM PDT 24
Finished Mar 12 02:52:26 PM PDT 24
Peak memory 215900 kb
Host smart-b3c4b1d5-8fce-4ad1-bd6c-070edff0dab1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740492769 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.3740492769
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.2991936775
Short name T99
Test name
Test status
Simulation time 661197635 ps
CPU time 2.1 seconds
Started Mar 12 02:52:15 PM PDT 24
Finished Mar 12 02:52:17 PM PDT 24
Peak memory 203928 kb
Host smart-cbc4ed7f-6d13-45a6-ba8a-e88adc39544d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991936775 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.2991936775
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1798310043
Short name T255
Test name
Test status
Simulation time 717022519 ps
CPU time 1.19 seconds
Started Mar 12 02:52:10 PM PDT 24
Finished Mar 12 02:52:11 PM PDT 24
Peak memory 203788 kb
Host smart-c2933bf1-053d-447c-a65b-cfa25571404a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798310043 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
1798310043
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2804250001
Short name T250
Test name
Test status
Simulation time 97555132 ps
CPU time 0.66 seconds
Started Mar 12 02:52:08 PM PDT 24
Finished Mar 12 02:52:09 PM PDT 24
Peak memory 203624 kb
Host smart-a8230272-525e-45f4-b6c7-32dd3d856b76
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804250001 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
2804250001
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1136610105
Short name T109
Test name
Test status
Simulation time 1123277434 ps
CPU time 8.19 seconds
Started Mar 12 02:52:15 PM PDT 24
Finished Mar 12 02:52:23 PM PDT 24
Peak memory 203972 kb
Host smart-a531e22c-b48d-4e95-b3f4-5bc5a93cb1a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136610105 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.1136610105
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.1765385255
Short name T348
Test name
Test status
Simulation time 416112053 ps
CPU time 2.63 seconds
Started Mar 12 02:52:08 PM PDT 24
Finished Mar 12 02:52:11 PM PDT 24
Peak memory 204092 kb
Host smart-a06dbb1a-7b81-4555-b25c-d7fb62f73ab4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765385255 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.1765385255
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.1943998125
Short name T361
Test name
Test status
Simulation time 138557550 ps
CPU time 2.23 seconds
Started Mar 12 02:52:14 PM PDT 24
Finished Mar 12 02:52:17 PM PDT 24
Peak memory 212304 kb
Host smart-e77879b6-3cfd-4ac7-9c88-125de91a290b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943998125 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.1943998125
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.1110132098
Short name T57
Test name
Test status
Simulation time 368689867 ps
CPU time 2.1 seconds
Started Mar 12 02:52:14 PM PDT 24
Finished Mar 12 02:52:16 PM PDT 24
Peak memory 203888 kb
Host smart-c3383b42-047c-41b5-93dc-361d5f089590
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110132098 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.1110132098
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.1733416627
Short name T320
Test name
Test status
Simulation time 439797951 ps
CPU time 1.93 seconds
Started Mar 12 02:52:16 PM PDT 24
Finished Mar 12 02:52:18 PM PDT 24
Peak memory 203832 kb
Host smart-bae0514a-8a82-43a4-8006-3b2697bf9f4d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733416627 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
1733416627
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1428007696
Short name T317
Test name
Test status
Simulation time 30995606 ps
CPU time 0.68 seconds
Started Mar 12 02:52:15 PM PDT 24
Finished Mar 12 02:52:16 PM PDT 24
Peak memory 203564 kb
Host smart-f8177d77-6275-48a4-a2d0-c8d644930750
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428007696 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
1428007696
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.3327599849
Short name T110
Test name
Test status
Simulation time 2404936780 ps
CPU time 4.1 seconds
Started Mar 12 02:52:15 PM PDT 24
Finished Mar 12 02:52:19 PM PDT 24
Peak memory 204072 kb
Host smart-e32b0677-1567-4d31-b4b4-f77a6f4fa8ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327599849 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.3327599849
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.3491436354
Short name T285
Test name
Test status
Simulation time 400014363 ps
CPU time 2.71 seconds
Started Mar 12 02:52:15 PM PDT 24
Finished Mar 12 02:52:18 PM PDT 24
Peak memory 204136 kb
Host smart-0c879875-fb1d-4d3d-ac62-b2f8ff43dad3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491436354 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.3491436354
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1170025141
Short name T123
Test name
Test status
Simulation time 2088470823 ps
CPU time 9.15 seconds
Started Mar 12 02:52:17 PM PDT 24
Finished Mar 12 02:52:27 PM PDT 24
Peak memory 212260 kb
Host smart-5d7e5de4-5528-447c-a186-ea3d2d1e706f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170025141 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.1
170025141
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.2888191457
Short name T344
Test name
Test status
Simulation time 420625270 ps
CPU time 3.21 seconds
Started Mar 12 02:52:25 PM PDT 24
Finished Mar 12 02:52:28 PM PDT 24
Peak memory 220376 kb
Host smart-60af7a0f-7253-4c9a-93a4-63b54cbca625
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888191457 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.2888191457
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.2023985469
Short name T306
Test name
Test status
Simulation time 57981919 ps
CPU time 1.58 seconds
Started Mar 12 02:52:23 PM PDT 24
Finished Mar 12 02:52:25 PM PDT 24
Peak memory 212152 kb
Host smart-2ba858e9-5c0a-4184-b902-811348ee9f5e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023985469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.2023985469
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3570195510
Short name T242
Test name
Test status
Simulation time 115490088 ps
CPU time 1.1 seconds
Started Mar 12 02:52:22 PM PDT 24
Finished Mar 12 02:52:23 PM PDT 24
Peak memory 203824 kb
Host smart-874e6b39-0654-4166-8d83-2c5d800c8901
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570195510 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
3570195510
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.4216565698
Short name T273
Test name
Test status
Simulation time 74280330 ps
CPU time 0.68 seconds
Started Mar 12 02:52:23 PM PDT 24
Finished Mar 12 02:52:24 PM PDT 24
Peak memory 203660 kb
Host smart-f8cebd7e-fc58-40e7-a246-2b6af73ab8cd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216565698 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
4216565698
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tap_fsm_rand_reset.1702427316
Short name T127
Test name
Test status
Simulation time 27354243891 ps
CPU time 14.22 seconds
Started Mar 12 02:52:23 PM PDT 24
Finished Mar 12 02:52:38 PM PDT 24
Peak memory 212352 kb
Host smart-83c7df44-bd6a-4555-bc36-25919c9f8341
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702427316 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rv_dm_tap_fsm_rand_reset.1702427316
Directory /workspace/14.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.3360701926
Short name T338
Test name
Test status
Simulation time 301828531 ps
CPU time 3.75 seconds
Started Mar 12 02:52:23 PM PDT 24
Finished Mar 12 02:52:27 PM PDT 24
Peak memory 212316 kb
Host smart-0601b1f4-2e90-4286-852a-81c3d9cbc14b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360701926 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.3360701926
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.3417739553
Short name T318
Test name
Test status
Simulation time 156489920 ps
CPU time 2.1 seconds
Started Mar 12 02:52:23 PM PDT 24
Finished Mar 12 02:52:25 PM PDT 24
Peak memory 212288 kb
Host smart-eca92ddf-1dcf-484f-83c9-db23be24084e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417739553 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.3417739553
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2459599362
Short name T326
Test name
Test status
Simulation time 185825264 ps
CPU time 1.43 seconds
Started Mar 12 02:52:22 PM PDT 24
Finished Mar 12 02:52:23 PM PDT 24
Peak memory 203996 kb
Host smart-c4d35405-199e-4b69-8af7-569c7c4072c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459599362 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.2459599362
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3843578173
Short name T304
Test name
Test status
Simulation time 1067385852 ps
CPU time 1.89 seconds
Started Mar 12 02:52:23 PM PDT 24
Finished Mar 12 02:52:25 PM PDT 24
Peak memory 203864 kb
Host smart-f00b6ab6-9c50-4e4d-b464-1bd5d3db7d34
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843578173 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
3843578173
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.665692852
Short name T232
Test name
Test status
Simulation time 23443505 ps
CPU time 0.67 seconds
Started Mar 12 02:52:23 PM PDT 24
Finished Mar 12 02:52:24 PM PDT 24
Peak memory 203664 kb
Host smart-eb9fe077-db0f-4dd3-93ef-f785b27e687d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665692852 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.665692852
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.3947400523
Short name T108
Test name
Test status
Simulation time 809837085 ps
CPU time 7.87 seconds
Started Mar 12 02:52:25 PM PDT 24
Finished Mar 12 02:52:33 PM PDT 24
Peak memory 204080 kb
Host smart-b2c6044e-09f4-48ae-aab5-acf4cf971cfb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947400523 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.3947400523
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.2189351834
Short name T352
Test name
Test status
Simulation time 226083480 ps
CPU time 3.16 seconds
Started Mar 12 02:52:22 PM PDT 24
Finished Mar 12 02:52:26 PM PDT 24
Peak memory 212316 kb
Host smart-791ea4f7-e37b-4d42-8de2-e254d4e84428
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189351834 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.2189351834
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2500396117
Short name T292
Test name
Test status
Simulation time 575296759 ps
CPU time 3.71 seconds
Started Mar 12 02:52:23 PM PDT 24
Finished Mar 12 02:52:27 PM PDT 24
Peak memory 215632 kb
Host smart-159d4675-109e-4081-b0a8-fd22e4b423ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500396117 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.2500396117
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2025167984
Short name T85
Test name
Test status
Simulation time 58583294 ps
CPU time 1.46 seconds
Started Mar 12 02:52:25 PM PDT 24
Finished Mar 12 02:52:27 PM PDT 24
Peak memory 203972 kb
Host smart-e0a598ac-a1c0-4c57-8c7b-083e57a19589
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025167984 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.2025167984
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2187150659
Short name T259
Test name
Test status
Simulation time 1427062571 ps
CPU time 1.95 seconds
Started Mar 12 02:52:25 PM PDT 24
Finished Mar 12 02:52:27 PM PDT 24
Peak memory 203804 kb
Host smart-a36069d8-702c-4cf4-9f35-83f603ef8415
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187150659 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
2187150659
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2668846584
Short name T333
Test name
Test status
Simulation time 52575427 ps
CPU time 0.71 seconds
Started Mar 12 02:52:24 PM PDT 24
Finished Mar 12 02:52:24 PM PDT 24
Peak memory 203660 kb
Host smart-1b464d84-8bc8-4932-b5a5-ea4c62119008
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668846584 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
2668846584
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1669876957
Short name T48
Test name
Test status
Simulation time 1004911728 ps
CPU time 7.35 seconds
Started Mar 12 02:52:22 PM PDT 24
Finished Mar 12 02:52:29 PM PDT 24
Peak memory 203984 kb
Host smart-eeab1d09-5ee1-4425-ab33-c454738f0e0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669876957 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.1669876957
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.2902280550
Short name T336
Test name
Test status
Simulation time 84096574 ps
CPU time 2.15 seconds
Started Mar 12 02:52:21 PM PDT 24
Finished Mar 12 02:52:24 PM PDT 24
Peak memory 204084 kb
Host smart-45f42ecd-4553-4c5d-ac77-dd06de66a9af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902280550 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.2902280550
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.4148018143
Short name T59
Test name
Test status
Simulation time 2882213845 ps
CPU time 4.88 seconds
Started Mar 12 02:52:41 PM PDT 24
Finished Mar 12 02:52:46 PM PDT 24
Peak memory 220500 kb
Host smart-684a0ee6-b19f-4666-9a31-d5d4af733385
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148018143 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.4148018143
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.2231260233
Short name T105
Test name
Test status
Simulation time 40412572 ps
CPU time 2.09 seconds
Started Mar 12 02:52:27 PM PDT 24
Finished Mar 12 02:52:30 PM PDT 24
Peak memory 212168 kb
Host smart-afb0dcbe-da7d-45d9-aa87-a1059049d855
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231260233 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.2231260233
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.3377743326
Short name T347
Test name
Test status
Simulation time 978361563 ps
CPU time 1.38 seconds
Started Mar 12 02:52:24 PM PDT 24
Finished Mar 12 02:52:26 PM PDT 24
Peak memory 203884 kb
Host smart-dda616fc-0634-4de4-b435-6a2106296e21
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377743326 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
3377743326
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.142623772
Short name T97
Test name
Test status
Simulation time 1030344737 ps
CPU time 7.77 seconds
Started Mar 12 02:52:28 PM PDT 24
Finished Mar 12 02:52:36 PM PDT 24
Peak memory 204044 kb
Host smart-76bbbdc2-48f8-4322-b677-f2f12ea973c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142623772 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same_
csr_outstanding.142623772
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.1874291522
Short name T358
Test name
Test status
Simulation time 136571390 ps
CPU time 2.95 seconds
Started Mar 12 02:52:22 PM PDT 24
Finished Mar 12 02:52:25 PM PDT 24
Peak memory 204008 kb
Host smart-f6ed9a50-3a2b-4c68-ad0f-9764e365fadc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874291522 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.1874291522
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.677332732
Short name T124
Test name
Test status
Simulation time 520167514 ps
CPU time 9.59 seconds
Started Mar 12 02:52:22 PM PDT 24
Finished Mar 12 02:52:32 PM PDT 24
Peak memory 212288 kb
Host smart-495b9b00-c081-4d85-9672-d0b17b4fa4d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677332732 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.677332732
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.573802636
Short name T366
Test name
Test status
Simulation time 5504241403 ps
CPU time 10.96 seconds
Started Mar 12 02:52:32 PM PDT 24
Finished Mar 12 02:52:43 PM PDT 24
Peak memory 216152 kb
Host smart-64c8e444-8b13-482c-a829-b847ca390271
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573802636 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.573802636
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.237406733
Short name T329
Test name
Test status
Simulation time 27095656 ps
CPU time 1.33 seconds
Started Mar 12 02:52:30 PM PDT 24
Finished Mar 12 02:52:32 PM PDT 24
Peak memory 203980 kb
Host smart-dd9cb195-3a74-437a-bd00-e3f499be0911
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237406733 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.237406733
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.3326864463
Short name T258
Test name
Test status
Simulation time 515964415 ps
CPU time 2.25 seconds
Started Mar 12 02:52:31 PM PDT 24
Finished Mar 12 02:52:34 PM PDT 24
Peak memory 203884 kb
Host smart-5fa0e0e9-7fcd-40bc-99e2-e86ef929aef6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326864463 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
3326864463
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2616849311
Short name T367
Test name
Test status
Simulation time 73035077 ps
CPU time 0.71 seconds
Started Mar 12 02:52:28 PM PDT 24
Finished Mar 12 02:52:29 PM PDT 24
Peak memory 203604 kb
Host smart-f1f2b882-418e-424f-ae36-cedc548fab5f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616849311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
2616849311
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.4012197959
Short name T357
Test name
Test status
Simulation time 500045755 ps
CPU time 7.55 seconds
Started Mar 12 02:52:28 PM PDT 24
Finished Mar 12 02:52:36 PM PDT 24
Peak memory 204076 kb
Host smart-a59fa28b-6a39-496a-8599-765a7395e141
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012197959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.4012197959
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2372865586
Short name T302
Test name
Test status
Simulation time 451702637 ps
CPU time 5.52 seconds
Started Mar 12 02:52:32 PM PDT 24
Finished Mar 12 02:52:37 PM PDT 24
Peak memory 212204 kb
Host smart-67ab843f-ee64-4f66-82cc-6cf6cff4f5e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372865586 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.2372865586
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.134734819
Short name T295
Test name
Test status
Simulation time 394966484 ps
CPU time 3.55 seconds
Started Mar 12 02:52:28 PM PDT 24
Finished Mar 12 02:52:33 PM PDT 24
Peak memory 215804 kb
Host smart-86649f70-a74c-4ba0-80a3-ef5a0bb8df78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134734819 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.134734819
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.2771297929
Short name T103
Test name
Test status
Simulation time 101394322 ps
CPU time 1.44 seconds
Started Mar 12 02:52:32 PM PDT 24
Finished Mar 12 02:52:34 PM PDT 24
Peak memory 203832 kb
Host smart-9519aa58-0743-4cda-8e4a-6ac718211b99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771297929 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.2771297929
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.84730303
Short name T309
Test name
Test status
Simulation time 464933179 ps
CPU time 1.27 seconds
Started Mar 12 02:52:31 PM PDT 24
Finished Mar 12 02:52:33 PM PDT 24
Peak memory 203836 kb
Host smart-fe998b89-f06a-47eb-a2da-a6183f0e9ac4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84730303 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.84730303
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3722141712
Short name T299
Test name
Test status
Simulation time 92387160 ps
CPU time 0.64 seconds
Started Mar 12 02:52:30 PM PDT 24
Finished Mar 12 02:52:31 PM PDT 24
Peak memory 203664 kb
Host smart-482eb5fa-91b5-4313-97d7-63ef3ea27b8c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722141712 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
3722141712
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.3803468177
Short name T341
Test name
Test status
Simulation time 141926432 ps
CPU time 6.47 seconds
Started Mar 12 02:52:29 PM PDT 24
Finished Mar 12 02:52:36 PM PDT 24
Peak memory 204040 kb
Host smart-b996ca49-b060-4f3d-96ce-9eb3ade6a204
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803468177 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.3803468177
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tap_fsm_rand_reset.3040960420
Short name T282
Test name
Test status
Simulation time 15376107426 ps
CPU time 13.62 seconds
Started Mar 12 02:52:30 PM PDT 24
Finished Mar 12 02:52:44 PM PDT 24
Peak memory 219544 kb
Host smart-b423075f-1088-4bdb-8e7d-e068fad400cb
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040960420 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rv_dm_tap_fsm_rand_reset.3040960420
Directory /workspace/19.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3159365244
Short name T251
Test name
Test status
Simulation time 120190941 ps
CPU time 3.89 seconds
Started Mar 12 02:52:33 PM PDT 24
Finished Mar 12 02:52:37 PM PDT 24
Peak memory 212356 kb
Host smart-f7df57b7-d229-4257-96c0-894c672fcf66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159365244 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.3159365244
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.465294530
Short name T126
Test name
Test status
Simulation time 3742125053 ps
CPU time 20.21 seconds
Started Mar 12 02:52:34 PM PDT 24
Finished Mar 12 02:52:55 PM PDT 24
Peak memory 216204 kb
Host smart-260775dc-16fa-4676-911e-a020c80e580c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465294530 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.465294530
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.403702891
Short name T345
Test name
Test status
Simulation time 4463159166 ps
CPU time 64.41 seconds
Started Mar 12 02:51:44 PM PDT 24
Finished Mar 12 02:52:49 PM PDT 24
Peak memory 204040 kb
Host smart-cd6fc181-a1ae-42c5-9a55-5db08ea1411f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403702891 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.rv_dm_csr_aliasing.403702891
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2588521458
Short name T245
Test name
Test status
Simulation time 2807864144 ps
CPU time 28.12 seconds
Started Mar 12 02:51:57 PM PDT 24
Finished Mar 12 02:52:25 PM PDT 24
Peak memory 204008 kb
Host smart-1b884e51-a2e1-4328-a865-70d3b9e1ae0a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588521458 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.2588521458
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3969131881
Short name T337
Test name
Test status
Simulation time 75249650 ps
CPU time 2.18 seconds
Started Mar 12 02:51:50 PM PDT 24
Finished Mar 12 02:51:52 PM PDT 24
Peak memory 203980 kb
Host smart-6f719153-bc44-4c4f-bd3f-c05dce00e62f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969131881 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.3969131881
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.2212169542
Short name T47
Test name
Test status
Simulation time 2465520001 ps
CPU time 3.39 seconds
Started Mar 12 02:51:51 PM PDT 24
Finished Mar 12 02:51:55 PM PDT 24
Peak memory 212292 kb
Host smart-e922a0ea-5434-4c46-82f9-aa4181d3a6f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212169542 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.2212169542
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1949068348
Short name T95
Test name
Test status
Simulation time 563279882 ps
CPU time 1.49 seconds
Started Mar 12 02:51:51 PM PDT 24
Finished Mar 12 02:51:53 PM PDT 24
Peak memory 212140 kb
Host smart-b933411b-487c-41df-876d-30c935cbf21a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949068348 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.1949068348
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.752660488
Short name T246
Test name
Test status
Simulation time 10879336802 ps
CPU time 21.73 seconds
Started Mar 12 02:51:49 PM PDT 24
Finished Mar 12 02:52:11 PM PDT 24
Peak memory 203860 kb
Host smart-b71f32df-1b84-46fe-9553-a256422e3ee7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752660488 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr
_aliasing.752660488
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.3030999535
Short name T230
Test name
Test status
Simulation time 21455013580 ps
CPU time 69.12 seconds
Started Mar 12 02:52:05 PM PDT 24
Finished Mar 12 02:53:14 PM PDT 24
Peak memory 203924 kb
Host smart-b7f8c758-12f7-4fb6-83e9-0a1f8cdbdecf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030999535 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_bit_bash.3030999535
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2514330838
Short name T94
Test name
Test status
Simulation time 584350086 ps
CPU time 1.04 seconds
Started Mar 12 02:51:56 PM PDT 24
Finished Mar 12 02:51:57 PM PDT 24
Peak memory 203936 kb
Host smart-be054572-fc01-4cc1-a541-74a317310bc8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514330838 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.2514330838
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.2499630531
Short name T340
Test name
Test status
Simulation time 1118715323 ps
CPU time 1.88 seconds
Started Mar 12 02:51:53 PM PDT 24
Finished Mar 12 02:51:55 PM PDT 24
Peak memory 203764 kb
Host smart-914bfe4e-850c-4f5e-b6f5-237f803c6acb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499630531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.2
499630531
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.947693669
Short name T343
Test name
Test status
Simulation time 99304016 ps
CPU time 0.79 seconds
Started Mar 12 02:51:58 PM PDT 24
Finished Mar 12 02:51:59 PM PDT 24
Peak memory 203640 kb
Host smart-24ae25fd-1eff-46dc-8017-6e187bca9d05
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947693669 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_aliasing.947693669
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.801218958
Short name T270
Test name
Test status
Simulation time 1135982467 ps
CPU time 3.14 seconds
Started Mar 12 02:51:59 PM PDT 24
Finished Mar 12 02:52:02 PM PDT 24
Peak memory 203808 kb
Host smart-81f8e522-0c9e-425f-a0c2-025768531166
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801218958 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_bit_bash.801218958
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2727570571
Short name T293
Test name
Test status
Simulation time 100424446 ps
CPU time 0.65 seconds
Started Mar 12 02:51:45 PM PDT 24
Finished Mar 12 02:51:46 PM PDT 24
Peak memory 203416 kb
Host smart-f8341d7b-2b8f-48db-9aec-4fad2ecb7c21
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727570571 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.2727570571
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.1883608085
Short name T233
Test name
Test status
Simulation time 151338619 ps
CPU time 1.02 seconds
Started Mar 12 02:51:58 PM PDT 24
Finished Mar 12 02:51:59 PM PDT 24
Peak memory 203652 kb
Host smart-1e6bfeba-3359-4d93-8243-b031517dee25
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883608085 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.1
883608085
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1720800566
Short name T231
Test name
Test status
Simulation time 36130412 ps
CPU time 0.61 seconds
Started Mar 12 02:51:56 PM PDT 24
Finished Mar 12 02:51:56 PM PDT 24
Peak memory 203620 kb
Host smart-1fad3e16-2475-449f-837a-913a7eceb33d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720800566 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.1720800566
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.2064267521
Short name T248
Test name
Test status
Simulation time 190119138 ps
CPU time 0.64 seconds
Started Mar 12 02:51:54 PM PDT 24
Finished Mar 12 02:51:55 PM PDT 24
Peak memory 203644 kb
Host smart-e31a3156-ff36-4e2d-9aef-b0f22f647ce3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064267521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.2064267521
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.656021441
Short name T112
Test name
Test status
Simulation time 836951986 ps
CPU time 4.23 seconds
Started Mar 12 02:51:51 PM PDT 24
Finished Mar 12 02:51:56 PM PDT 24
Peak memory 204072 kb
Host smart-e6878580-4832-49d1-9fa2-76d66e2f97d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656021441 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_c
sr_outstanding.656021441
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.3678835046
Short name T307
Test name
Test status
Simulation time 93114049 ps
CPU time 1.79 seconds
Started Mar 12 02:51:58 PM PDT 24
Finished Mar 12 02:52:00 PM PDT 24
Peak memory 204116 kb
Host smart-aeb18f29-9560-4c23-941e-3353eca167d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678835046 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.3678835046
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.1033380197
Short name T118
Test name
Test status
Simulation time 1737723848 ps
CPU time 9.6 seconds
Started Mar 12 02:51:51 PM PDT 24
Finished Mar 12 02:52:01 PM PDT 24
Peak memory 212276 kb
Host smart-13c7a877-b379-4cc3-bf45-c8b25d03899a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033380197 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.1033380197
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/23.rv_dm_tap_fsm_rand_reset.3874571079
Short name T257
Test name
Test status
Simulation time 11868300364 ps
CPU time 10.02 seconds
Started Mar 12 02:52:31 PM PDT 24
Finished Mar 12 02:52:41 PM PDT 24
Peak memory 220072 kb
Host smart-968af453-f8f7-4bde-916c-6dc3772ca1cd
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874571079 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 23.rv_dm_tap_fsm_rand_reset.3874571079
Directory /workspace/23.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/26.rv_dm_tap_fsm_rand_reset.3271583231
Short name T64
Test name
Test status
Simulation time 9482785393 ps
CPU time 15.07 seconds
Started Mar 12 02:52:32 PM PDT 24
Finished Mar 12 02:52:47 PM PDT 24
Peak memory 219848 kb
Host smart-488224e0-0931-46b8-bf2f-0ae1e401d9fb
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271583231 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 26.rv_dm_tap_fsm_rand_reset.3271583231
Directory /workspace/26.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/27.rv_dm_tap_fsm_rand_reset.1504168098
Short name T321
Test name
Test status
Simulation time 12312059802 ps
CPU time 11.18 seconds
Started Mar 12 02:52:30 PM PDT 24
Finished Mar 12 02:52:42 PM PDT 24
Peak memory 212312 kb
Host smart-3d67bf75-a3f9-46eb-a8a4-409ea110a274
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504168098 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 27.rv_dm_tap_fsm_rand_reset.1504168098
Directory /workspace/27.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2265152405
Short name T355
Test name
Test status
Simulation time 595599457 ps
CPU time 26.4 seconds
Started Mar 12 02:51:59 PM PDT 24
Finished Mar 12 02:52:25 PM PDT 24
Peak memory 204004 kb
Host smart-98e7d92f-250c-4ed6-8890-9c134dd47e6c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265152405 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.2265152405
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.2923764020
Short name T356
Test name
Test status
Simulation time 1455217189 ps
CPU time 50.52 seconds
Started Mar 12 02:51:56 PM PDT 24
Finished Mar 12 02:52:46 PM PDT 24
Peak memory 203936 kb
Host smart-57613f17-e076-4177-9272-72b00ec022c5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923764020 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.2923764020
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.57494289
Short name T279
Test name
Test status
Simulation time 41724810 ps
CPU time 1.57 seconds
Started Mar 12 02:51:52 PM PDT 24
Finished Mar 12 02:51:54 PM PDT 24
Peak memory 203980 kb
Host smart-c37e31c3-9f0a-4afa-86f9-7c3fe2115e14
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57494289 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.57494289
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.880593938
Short name T78
Test name
Test status
Simulation time 2511718571 ps
CPU time 4.49 seconds
Started Mar 12 02:51:53 PM PDT 24
Finished Mar 12 02:51:58 PM PDT 24
Peak memory 220464 kb
Host smart-ec113215-aeda-4477-979a-1e69f29e0e40
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880593938 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.880593938
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2575821165
Short name T363
Test name
Test status
Simulation time 1849782819 ps
CPU time 2.58 seconds
Started Mar 12 02:51:52 PM PDT 24
Finished Mar 12 02:51:55 PM PDT 24
Peak memory 203972 kb
Host smart-1d51dce1-b50e-4001-959a-455951373a2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575821165 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.2575821165
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1263385145
Short name T234
Test name
Test status
Simulation time 2666181986 ps
CPU time 11.85 seconds
Started Mar 12 02:51:51 PM PDT 24
Finished Mar 12 02:52:03 PM PDT 24
Peak memory 203716 kb
Host smart-022b6321-b197-4036-8af3-1182745fa47a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263385145 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.1263385145
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.2937741405
Short name T323
Test name
Test status
Simulation time 5057466633 ps
CPU time 13.97 seconds
Started Mar 12 02:52:01 PM PDT 24
Finished Mar 12 02:52:16 PM PDT 24
Peak memory 203940 kb
Host smart-a26f39db-971b-4a28-ac4e-f6f48ef12d0d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937741405 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_bit_bash.2937741405
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2052025563
Short name T93
Test name
Test status
Simulation time 1403964467 ps
CPU time 2.37 seconds
Started Mar 12 02:51:52 PM PDT 24
Finished Mar 12 02:51:55 PM PDT 24
Peak memory 203976 kb
Host smart-2da3afda-9add-4a5c-9f5f-e316277a057c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052025563 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.2052025563
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.2903433285
Short name T229
Test name
Test status
Simulation time 611517135 ps
CPU time 2.61 seconds
Started Mar 12 02:51:51 PM PDT 24
Finished Mar 12 02:51:54 PM PDT 24
Peak memory 203832 kb
Host smart-fed6aa23-2f97-4915-a0c7-969a022d7a87
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903433285 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.2
903433285
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3420150301
Short name T319
Test name
Test status
Simulation time 58258834 ps
CPU time 0.67 seconds
Started Mar 12 02:51:51 PM PDT 24
Finished Mar 12 02:51:52 PM PDT 24
Peak memory 203596 kb
Host smart-186a1497-4382-4697-a92b-a3d52d249eee
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420150301 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.3420150301
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.3863451499
Short name T253
Test name
Test status
Simulation time 1741588974 ps
CPU time 7.05 seconds
Started Mar 12 02:51:54 PM PDT 24
Finished Mar 12 02:52:01 PM PDT 24
Peak memory 203864 kb
Host smart-149d4e3e-c55b-4bf0-8bb9-3cdc58b1954e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863451499 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.3863451499
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3337320326
Short name T346
Test name
Test status
Simulation time 146266785 ps
CPU time 1.06 seconds
Started Mar 12 02:51:57 PM PDT 24
Finished Mar 12 02:51:58 PM PDT 24
Peak memory 203648 kb
Host smart-57828139-09cd-4126-a4b0-5f502af07a05
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337320326 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.3337320326
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.4188304988
Short name T239
Test name
Test status
Simulation time 112693168 ps
CPU time 0.72 seconds
Started Mar 12 02:52:05 PM PDT 24
Finished Mar 12 02:52:06 PM PDT 24
Peak memory 203632 kb
Host smart-6fa32efe-e227-4933-8e95-4df4cb4444a1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188304988 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.4
188304988
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.2359223485
Short name T263
Test name
Test status
Simulation time 39174911 ps
CPU time 0.61 seconds
Started Mar 12 02:51:54 PM PDT 24
Finished Mar 12 02:51:54 PM PDT 24
Peak memory 203664 kb
Host smart-bee711cd-5793-4379-8da8-3c8d0d44596b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359223485 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.2359223485
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.4137722996
Short name T354
Test name
Test status
Simulation time 17365247 ps
CPU time 0.65 seconds
Started Mar 12 02:52:00 PM PDT 24
Finished Mar 12 02:52:01 PM PDT 24
Peak memory 203632 kb
Host smart-6b270066-424e-4ae2-90f6-121bc9d04604
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137722996 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.4137722996
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.1852123634
Short name T113
Test name
Test status
Simulation time 506655272 ps
CPU time 4.07 seconds
Started Mar 12 02:51:51 PM PDT 24
Finished Mar 12 02:51:55 PM PDT 24
Peak memory 204080 kb
Host smart-fa1adb3f-67f7-4d45-9675-3c8602ae16bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852123634 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.1852123634
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.1438214365
Short name T330
Test name
Test status
Simulation time 110547026 ps
CPU time 2.13 seconds
Started Mar 12 02:52:05 PM PDT 24
Finished Mar 12 02:52:07 PM PDT 24
Peak memory 212652 kb
Host smart-38439fe0-8754-4553-a189-a5ac7aa58482
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438214365 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.1438214365
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.1370970518
Short name T79
Test name
Test status
Simulation time 240343075 ps
CPU time 7.82 seconds
Started Mar 12 02:52:05 PM PDT 24
Finished Mar 12 02:52:13 PM PDT 24
Peak memory 212200 kb
Host smart-dfa8e339-38f6-4b37-bb28-e0c8245ec475
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370970518 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.1370970518
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/35.rv_dm_tap_fsm_rand_reset.927065898
Short name T349
Test name
Test status
Simulation time 6564238639 ps
CPU time 20.92 seconds
Started Mar 12 02:52:30 PM PDT 24
Finished Mar 12 02:52:52 PM PDT 24
Peak memory 220484 kb
Host smart-6d24f22f-434b-4f78-be00-f0efe6a9cde6
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927065898 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 35.rv_dm_tap_fsm_rand_reset.927065898
Directory /workspace/35.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/36.rv_dm_tap_fsm_rand_reset.3066133833
Short name T298
Test name
Test status
Simulation time 12872180770 ps
CPU time 14.49 seconds
Started Mar 12 02:52:29 PM PDT 24
Finished Mar 12 02:52:44 PM PDT 24
Peak memory 212328 kb
Host smart-4ad0eb5d-bfc9-426a-b7c4-ef066604fa94
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066133833 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 36.rv_dm_tap_fsm_rand_reset.3066133833
Directory /workspace/36.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/38.rv_dm_tap_fsm_rand_reset.316722452
Short name T287
Test name
Test status
Simulation time 33801436420 ps
CPU time 27.18 seconds
Started Mar 12 02:52:31 PM PDT 24
Finished Mar 12 02:52:58 PM PDT 24
Peak memory 219852 kb
Host smart-95da7fa3-ff01-486b-ad3a-ae1e25f7ae69
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316722452 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 38.rv_dm_tap_fsm_rand_reset.316722452
Directory /workspace/38.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.662407682
Short name T313
Test name
Test status
Simulation time 16906267769 ps
CPU time 75.03 seconds
Started Mar 12 02:51:51 PM PDT 24
Finished Mar 12 02:53:06 PM PDT 24
Peak memory 203968 kb
Host smart-90af05d5-b333-4481-8497-667ab9b32bda
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662407682 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.rv_dm_csr_aliasing.662407682
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.2393283829
Short name T365
Test name
Test status
Simulation time 1037412884 ps
CPU time 27.02 seconds
Started Mar 12 02:51:58 PM PDT 24
Finished Mar 12 02:52:25 PM PDT 24
Peak memory 203948 kb
Host smart-8a8cfae4-a91b-415b-98ac-3264ac4dac6f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393283829 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.2393283829
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.3000757802
Short name T289
Test name
Test status
Simulation time 171401282 ps
CPU time 2.44 seconds
Started Mar 12 02:52:07 PM PDT 24
Finished Mar 12 02:52:10 PM PDT 24
Peak memory 203944 kb
Host smart-c90e4fb8-626b-4a2c-9d06-ad3b5dd178fb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000757802 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.3000757802
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.3515299750
Short name T362
Test name
Test status
Simulation time 1675170206 ps
CPU time 2.85 seconds
Started Mar 12 02:51:57 PM PDT 24
Finished Mar 12 02:52:00 PM PDT 24
Peak memory 215140 kb
Host smart-d82e206d-5a62-481c-a4e3-d2b4ddc7c9ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515299750 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.3515299750
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.3170499312
Short name T254
Test name
Test status
Simulation time 39802992 ps
CPU time 2.11 seconds
Started Mar 12 02:51:59 PM PDT 24
Finished Mar 12 02:52:01 PM PDT 24
Peak memory 212192 kb
Host smart-3debbdb6-8b5b-4ad1-879e-cdd1fb2c69a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170499312 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.3170499312
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.228070402
Short name T315
Test name
Test status
Simulation time 20032741139 ps
CPU time 65.18 seconds
Started Mar 12 02:51:57 PM PDT 24
Finished Mar 12 02:53:02 PM PDT 24
Peak memory 203920 kb
Host smart-df342a33-8aa1-4075-87f9-c03929115ea3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228070402 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr
_aliasing.228070402
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3880936619
Short name T286
Test name
Test status
Simulation time 19816719240 ps
CPU time 44.7 seconds
Started Mar 12 02:51:55 PM PDT 24
Finished Mar 12 02:52:40 PM PDT 24
Peak memory 203928 kb
Host smart-dff4176d-cdd7-441e-aa5f-8ece8f937deb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880936619 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_bit_bash.3880936619
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.1111465180
Short name T90
Test name
Test status
Simulation time 247204015 ps
CPU time 1.09 seconds
Started Mar 12 02:51:59 PM PDT 24
Finished Mar 12 02:52:00 PM PDT 24
Peak memory 203948 kb
Host smart-52219433-d33f-4f73-8f32-6200e68e4d73
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111465180 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.1111465180
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.2729673821
Short name T240
Test name
Test status
Simulation time 494846343 ps
CPU time 1.09 seconds
Started Mar 12 02:51:52 PM PDT 24
Finished Mar 12 02:51:53 PM PDT 24
Peak memory 203820 kb
Host smart-cb95f952-19bb-44ff-aa85-ba3642cef8df
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729673821 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.2
729673821
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.954578982
Short name T301
Test name
Test status
Simulation time 370647301 ps
CPU time 1.69 seconds
Started Mar 12 02:51:51 PM PDT 24
Finished Mar 12 02:51:53 PM PDT 24
Peak memory 203628 kb
Host smart-04c63638-0b1d-4214-b097-d3c211393f4c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954578982 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr
_aliasing.954578982
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2271317893
Short name T327
Test name
Test status
Simulation time 2597738924 ps
CPU time 4.34 seconds
Started Mar 12 02:52:05 PM PDT 24
Finished Mar 12 02:52:10 PM PDT 24
Peak memory 203920 kb
Host smart-299745a1-f274-46f2-bc34-d53e058453f0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271317893 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.2271317893
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.3200076
Short name T249
Test name
Test status
Simulation time 87421807 ps
CPU time 0.87 seconds
Started Mar 12 02:51:50 PM PDT 24
Finished Mar 12 02:51:51 PM PDT 24
Peak memory 203692 kb
Host smart-7fe319d8-4bf3-4763-bd48-2dd8f9b5af49
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200076 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_h
w_reset.3200076
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.4123809108
Short name T68
Test name
Test status
Simulation time 46922721 ps
CPU time 0.65 seconds
Started Mar 12 02:51:51 PM PDT 24
Finished Mar 12 02:51:52 PM PDT 24
Peak memory 203604 kb
Host smart-f6aca3f5-bc3d-411a-b5c3-a104d358fde1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123809108 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.4
123809108
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1432087057
Short name T243
Test name
Test status
Simulation time 24250753 ps
CPU time 0.65 seconds
Started Mar 12 02:52:08 PM PDT 24
Finished Mar 12 02:52:08 PM PDT 24
Peak memory 203636 kb
Host smart-fb00bb8c-79ac-42fb-b3e5-046a87bf6ac9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432087057 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.1432087057
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.880348410
Short name T274
Test name
Test status
Simulation time 19782018 ps
CPU time 0.66 seconds
Started Mar 12 02:51:58 PM PDT 24
Finished Mar 12 02:51:59 PM PDT 24
Peak memory 203600 kb
Host smart-b89354f9-652c-4a39-b691-b9a2831bc863
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880348410 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.880348410
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.870183863
Short name T300
Test name
Test status
Simulation time 808627176 ps
CPU time 4.33 seconds
Started Mar 12 02:51:59 PM PDT 24
Finished Mar 12 02:52:03 PM PDT 24
Peak memory 204020 kb
Host smart-b65d467f-afa2-4d89-9807-b8b35060fafc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870183863 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_c
sr_outstanding.870183863
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.52144442
Short name T303
Test name
Test status
Simulation time 52781922 ps
CPU time 2.35 seconds
Started Mar 12 02:52:00 PM PDT 24
Finished Mar 12 02:52:03 PM PDT 24
Peak memory 212308 kb
Host smart-2687eb74-0e84-4c00-8786-c5db69556e57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52144442 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.52144442
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3188606569
Short name T271
Test name
Test status
Simulation time 2044275783 ps
CPU time 4.3 seconds
Started Mar 12 02:51:56 PM PDT 24
Finished Mar 12 02:52:00 PM PDT 24
Peak memory 220460 kb
Host smart-f5974b52-3316-45d3-aaa9-9bbde3887d3f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188606569 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.3188606569
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.1130349953
Short name T102
Test name
Test status
Simulation time 202967217 ps
CPU time 2.05 seconds
Started Mar 12 02:51:58 PM PDT 24
Finished Mar 12 02:52:00 PM PDT 24
Peak memory 203776 kb
Host smart-81a216a9-b80b-451d-9293-9c7a522a69d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130349953 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.1130349953
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.1469586225
Short name T264
Test name
Test status
Simulation time 662110373 ps
CPU time 1.11 seconds
Started Mar 12 02:51:56 PM PDT 24
Finished Mar 12 02:51:58 PM PDT 24
Peak memory 203824 kb
Host smart-2ccbf10e-1ae3-426e-968f-ded9b7eb0a0d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469586225 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.1
469586225
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.1820877046
Short name T76
Test name
Test status
Simulation time 137962257 ps
CPU time 1.01 seconds
Started Mar 12 02:51:59 PM PDT 24
Finished Mar 12 02:52:00 PM PDT 24
Peak memory 203648 kb
Host smart-57ffe411-2ea8-4a8b-8b41-ac8204d2d6e3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820877046 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.1
820877046
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1720917193
Short name T331
Test name
Test status
Simulation time 595609291 ps
CPU time 7.37 seconds
Started Mar 12 02:51:57 PM PDT 24
Finished Mar 12 02:52:04 PM PDT 24
Peak memory 204032 kb
Host smart-e4f9c434-cd58-4356-886e-279bd88384f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720917193 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.1720917193
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.2416762451
Short name T294
Test name
Test status
Simulation time 13187093607 ps
CPU time 12.73 seconds
Started Mar 12 02:52:00 PM PDT 24
Finished Mar 12 02:52:13 PM PDT 24
Peak memory 212380 kb
Host smart-085d99f3-c3ec-4549-8dda-e8f0045b5569
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416762451 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.2416762451
Directory /workspace/5.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.80482074
Short name T260
Test name
Test status
Simulation time 687997618 ps
CPU time 5.92 seconds
Started Mar 12 02:51:57 PM PDT 24
Finished Mar 12 02:52:03 PM PDT 24
Peak memory 212340 kb
Host smart-2d1f2e14-01e2-4d24-9f97-e8f977f9bf52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80482074 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.80482074
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.1191275990
Short name T332
Test name
Test status
Simulation time 2447400814 ps
CPU time 9.28 seconds
Started Mar 12 02:51:57 PM PDT 24
Finished Mar 12 02:52:06 PM PDT 24
Peak memory 212228 kb
Host smart-c8f1656f-dc71-4917-b437-300a9c22ed01
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191275990 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.1191275990
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.446613730
Short name T268
Test name
Test status
Simulation time 1723216719 ps
CPU time 4.51 seconds
Started Mar 12 02:51:56 PM PDT 24
Finished Mar 12 02:52:01 PM PDT 24
Peak memory 213716 kb
Host smart-c1cf4249-eef8-4027-90de-a69272ba9dc9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446613730 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.446613730
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.2199355102
Short name T104
Test name
Test status
Simulation time 305749789 ps
CPU time 1.54 seconds
Started Mar 12 02:51:57 PM PDT 24
Finished Mar 12 02:51:58 PM PDT 24
Peak memory 203992 kb
Host smart-b9ef56a5-57d3-4c12-82a4-d4ddb2e761fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199355102 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.2199355102
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.885555619
Short name T256
Test name
Test status
Simulation time 319986054 ps
CPU time 1.09 seconds
Started Mar 12 02:51:57 PM PDT 24
Finished Mar 12 02:51:59 PM PDT 24
Peak memory 203796 kb
Host smart-e071478a-52d3-4abe-8677-98e4d35a3f2b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885555619 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.885555619
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2469037450
Short name T316
Test name
Test status
Simulation time 105862048 ps
CPU time 0.68 seconds
Started Mar 12 02:52:02 PM PDT 24
Finished Mar 12 02:52:03 PM PDT 24
Peak memory 203624 kb
Host smart-533c37d7-ed17-4286-a966-4058a2ef0362
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469037450 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.2
469037450
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.3393517959
Short name T290
Test name
Test status
Simulation time 418332150 ps
CPU time 7.2 seconds
Started Mar 12 02:51:56 PM PDT 24
Finished Mar 12 02:52:03 PM PDT 24
Peak memory 204056 kb
Host smart-573a9987-1ac3-45d4-a689-fc13de577783
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393517959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.3393517959
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.4206373605
Short name T353
Test name
Test status
Simulation time 219885369 ps
CPU time 2.61 seconds
Started Mar 12 02:51:58 PM PDT 24
Finished Mar 12 02:52:01 PM PDT 24
Peak memory 204008 kb
Host smart-5f371425-9fad-4892-94b1-ad239e86363f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206373605 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.4206373605
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.3257633372
Short name T119
Test name
Test status
Simulation time 1059219868 ps
CPU time 14.73 seconds
Started Mar 12 02:51:58 PM PDT 24
Finished Mar 12 02:52:13 PM PDT 24
Peak memory 212448 kb
Host smart-c44be866-c3f1-49c4-b2c5-9f6259006eff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257633372 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.3257633372
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.866399096
Short name T283
Test name
Test status
Simulation time 1524238062 ps
CPU time 5.66 seconds
Started Mar 12 02:52:05 PM PDT 24
Finished Mar 12 02:52:10 PM PDT 24
Peak memory 216464 kb
Host smart-69844566-88eb-49ac-9005-fa306688353f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866399096 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.866399096
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.2635861445
Short name T49
Test name
Test status
Simulation time 90464337 ps
CPU time 2.16 seconds
Started Mar 12 02:52:03 PM PDT 24
Finished Mar 12 02:52:05 PM PDT 24
Peak memory 212392 kb
Host smart-b816686d-41d7-449e-baf7-26ae2e206a91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635861445 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.2635861445
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3488882718
Short name T241
Test name
Test status
Simulation time 190571651 ps
CPU time 0.95 seconds
Started Mar 12 02:51:57 PM PDT 24
Finished Mar 12 02:51:58 PM PDT 24
Peak memory 203868 kb
Host smart-228db33f-5a3e-49ad-99bc-7f34ce3bd57d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488882718 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.3
488882718
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.415893800
Short name T360
Test name
Test status
Simulation time 57246165 ps
CPU time 0.78 seconds
Started Mar 12 02:51:56 PM PDT 24
Finished Mar 12 02:51:57 PM PDT 24
Peak memory 203676 kb
Host smart-84771f89-1343-4c54-95f1-566d1ea213bd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415893800 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.415893800
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.2816685697
Short name T98
Test name
Test status
Simulation time 6292974688 ps
CPU time 7.06 seconds
Started Mar 12 02:52:16 PM PDT 24
Finished Mar 12 02:52:23 PM PDT 24
Peak memory 204068 kb
Host smart-96589140-e922-4b35-9556-52b00dc73351
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816685697 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.2816685697
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.4165300862
Short name T297
Test name
Test status
Simulation time 705602763 ps
CPU time 4.17 seconds
Started Mar 12 02:52:03 PM PDT 24
Finished Mar 12 02:52:07 PM PDT 24
Peak memory 212348 kb
Host smart-0dfca731-2c8c-44ff-99af-f2b0477d0a6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165300862 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.4165300862
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2372626810
Short name T267
Test name
Test status
Simulation time 1878390176 ps
CPU time 10.05 seconds
Started Mar 12 02:52:04 PM PDT 24
Finished Mar 12 02:52:14 PM PDT 24
Peak memory 212544 kb
Host smart-05dfe829-f6c6-4445-8690-5a9d85c61852
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372626810 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.2372626810
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.430028623
Short name T265
Test name
Test status
Simulation time 933688484 ps
CPU time 3.58 seconds
Started Mar 12 02:52:17 PM PDT 24
Finished Mar 12 02:52:21 PM PDT 24
Peak memory 219720 kb
Host smart-baea72c9-6368-4c9f-b716-1a9867bcf5bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430028623 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.430028623
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.3596826148
Short name T339
Test name
Test status
Simulation time 169663897 ps
CPU time 2.22 seconds
Started Mar 12 02:52:03 PM PDT 24
Finished Mar 12 02:52:06 PM PDT 24
Peak memory 202484 kb
Host smart-39d6757c-2799-4c01-a84b-52e50dd2d8bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596826148 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.3596826148
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.4046037162
Short name T266
Test name
Test status
Simulation time 1466901445 ps
CPU time 4.97 seconds
Started Mar 12 02:52:02 PM PDT 24
Finished Mar 12 02:52:07 PM PDT 24
Peak memory 203824 kb
Host smart-01930dad-91c4-43d4-ba35-7dfd85cb62ab
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046037162 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.4
046037162
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.533442748
Short name T247
Test name
Test status
Simulation time 40511492 ps
CPU time 0.66 seconds
Started Mar 12 02:52:17 PM PDT 24
Finished Mar 12 02:52:18 PM PDT 24
Peak memory 203460 kb
Host smart-1bba3fe7-92a0-44fd-8209-7a6d78f7df72
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533442748 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.533442748
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.1563672691
Short name T111
Test name
Test status
Simulation time 504662815 ps
CPU time 7.41 seconds
Started Mar 12 02:52:16 PM PDT 24
Finished Mar 12 02:52:24 PM PDT 24
Peak memory 203952 kb
Host smart-f6a3e927-2532-4fd7-ba52-336b3ecde687
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563672691 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_
csr_outstanding.1563672691
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.3991849370
Short name T280
Test name
Test status
Simulation time 440799544 ps
CPU time 3.36 seconds
Started Mar 12 02:52:03 PM PDT 24
Finished Mar 12 02:52:07 PM PDT 24
Peak memory 204140 kb
Host smart-d95a3dad-a0bd-4d28-a713-4d600496d043
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991849370 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.3991849370
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3759527350
Short name T277
Test name
Test status
Simulation time 732353618 ps
CPU time 7.59 seconds
Started Mar 12 02:52:17 PM PDT 24
Finished Mar 12 02:52:25 PM PDT 24
Peak memory 211816 kb
Host smart-764cfb5a-c858-49c2-afce-18d8765fa6ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759527350 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.3759527350
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.3853526810
Short name T252
Test name
Test status
Simulation time 173449576 ps
CPU time 1.55 seconds
Started Mar 12 02:52:03 PM PDT 24
Finished Mar 12 02:52:05 PM PDT 24
Peak memory 203968 kb
Host smart-fb2d3b3e-f159-4673-8f78-aeee98769cf0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853526810 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.3853526810
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.353081407
Short name T272
Test name
Test status
Simulation time 343480170 ps
CPU time 1.05 seconds
Started Mar 12 02:52:03 PM PDT 24
Finished Mar 12 02:52:04 PM PDT 24
Peak memory 202240 kb
Host smart-d9eaff29-083e-4de6-a604-93821a7ee120
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353081407 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.353081407
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.3520080077
Short name T244
Test name
Test status
Simulation time 85226576 ps
CPU time 0.8 seconds
Started Mar 12 02:52:03 PM PDT 24
Finished Mar 12 02:52:03 PM PDT 24
Peak memory 203200 kb
Host smart-5dd3f642-b34f-4c85-9661-5f7d41c056dc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520080077 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.3
520080077
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.1976397238
Short name T351
Test name
Test status
Simulation time 149344113 ps
CPU time 6.16 seconds
Started Mar 12 02:52:17 PM PDT 24
Finished Mar 12 02:52:23 PM PDT 24
Peak memory 203704 kb
Host smart-ab6c05eb-fa99-4d67-9422-ea5d8f6f6d4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976397238 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.1976397238
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.89391756
Short name T156
Test name
Test status
Simulation time 230984412 ps
CPU time 4.01 seconds
Started Mar 12 02:52:04 PM PDT 24
Finished Mar 12 02:52:08 PM PDT 24
Peak memory 212236 kb
Host smart-71d9d613-f52e-4a65-a8c7-5af0d7c074dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89391756 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.89391756
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.145108657
Short name T38
Test name
Test status
Simulation time 19229135 ps
CPU time 0.66 seconds
Started Mar 12 12:30:33 PM PDT 24
Finished Mar 12 12:30:34 PM PDT 24
Peak memory 203184 kb
Host smart-36b86eb1-667d-4027-bcfb-37bfe75962e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145108657 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.145108657
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.1279085854
Short name T211
Test name
Test status
Simulation time 5634916304 ps
CPU time 8.53 seconds
Started Mar 12 12:30:41 PM PDT 24
Finished Mar 12 12:30:50 PM PDT 24
Peak memory 203532 kb
Host smart-90a6851e-5d61-47a7-a49e-ac71bd4c44c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279085854 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.1279085854
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.4015942086
Short name T12
Test name
Test status
Simulation time 3582990831 ps
CPU time 3.59 seconds
Started Mar 12 12:30:29 PM PDT 24
Finished Mar 12 12:30:33 PM PDT 24
Peak memory 203456 kb
Host smart-1fe28bad-ed14-4aff-8155-35ac847a69bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015942086 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.4015942086
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.1673489430
Short name T24
Test name
Test status
Simulation time 2044325158 ps
CPU time 1.98 seconds
Started Mar 12 12:30:38 PM PDT 24
Finished Mar 12 12:30:40 PM PDT 24
Peak memory 203428 kb
Host smart-cd491f30-18d7-43c6-a206-9541d8fb2972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673489430 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.1673489430
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.2766283122
Short name T16
Test name
Test status
Simulation time 69471920 ps
CPU time 0.7 seconds
Started Mar 12 12:30:40 PM PDT 24
Finished Mar 12 12:30:42 PM PDT 24
Peak memory 203208 kb
Host smart-8ab15543-40cb-459f-864a-c7c5c6a0bcf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766283122 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.2766283122
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.3438050618
Short name T228
Test name
Test status
Simulation time 2255983668 ps
CPU time 4.89 seconds
Started Mar 12 12:30:40 PM PDT 24
Finished Mar 12 12:30:46 PM PDT 24
Peak memory 203512 kb
Host smart-ab57f04e-6007-4ee9-85c7-7db4e2ec5683
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3438050618 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t
l_access.3438050618
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.3968524624
Short name T31
Test name
Test status
Simulation time 362765011 ps
CPU time 1.73 seconds
Started Mar 12 12:30:25 PM PDT 24
Finished Mar 12 12:30:27 PM PDT 24
Peak memory 203352 kb
Host smart-0adb23cb-1fb0-4d04-aba2-3a6dc1c63f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968524624 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.3968524624
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.3346665016
Short name T180
Test name
Test status
Simulation time 63938514 ps
CPU time 0.73 seconds
Started Mar 12 12:30:30 PM PDT 24
Finished Mar 12 12:30:31 PM PDT 24
Peak memory 203116 kb
Host smart-7a72baf8-0b28-4bed-a667-0b7f0ef13600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346665016 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.3346665016
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.3538114318
Short name T203
Test name
Test status
Simulation time 232667447 ps
CPU time 1.01 seconds
Started Mar 12 12:30:42 PM PDT 24
Finished Mar 12 12:30:44 PM PDT 24
Peak memory 203112 kb
Host smart-a4906816-88f5-4ef5-8263-071278394c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538114318 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.3538114318
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.2730863595
Short name T209
Test name
Test status
Simulation time 177184748 ps
CPU time 0.82 seconds
Started Mar 12 12:30:39 PM PDT 24
Finished Mar 12 12:30:40 PM PDT 24
Peak memory 203076 kb
Host smart-3dce5731-7ad6-4a3e-8a00-bf971c10b860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730863595 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.2730863595
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.2844739574
Short name T67
Test name
Test status
Simulation time 44238626 ps
CPU time 0.71 seconds
Started Mar 12 12:30:34 PM PDT 24
Finished Mar 12 12:30:35 PM PDT 24
Peak memory 202788 kb
Host smart-d2b2e517-fd1d-44a1-ba95-c55ab09d3e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844739574 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.2844739574
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.713131133
Short name T8
Test name
Test status
Simulation time 56867589 ps
CPU time 0.74 seconds
Started Mar 12 12:30:23 PM PDT 24
Finished Mar 12 12:30:23 PM PDT 24
Peak memory 203196 kb
Host smart-224b1db8-85b0-43a7-b543-cac3ce86c2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713131133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.713131133
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.153539348
Short name T116
Test name
Test status
Simulation time 176881646 ps
CPU time 1.2 seconds
Started Mar 12 12:30:25 PM PDT 24
Finished Mar 12 12:30:27 PM PDT 24
Peak memory 203380 kb
Host smart-527d2d9d-b02e-4ee8-af03-ed43ae9e6742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153539348 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.153539348
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.1851923571
Short name T81
Test name
Test status
Simulation time 354543162 ps
CPU time 1.12 seconds
Started Mar 12 12:30:29 PM PDT 24
Finished Mar 12 12:30:30 PM PDT 24
Peak memory 203828 kb
Host smart-48d8ae90-dcd3-426c-bd6b-41d06c7f25bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851923571 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.1851923571
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.2682089594
Short name T13
Test name
Test status
Simulation time 439084904 ps
CPU time 2.5 seconds
Started Mar 12 12:30:56 PM PDT 24
Finished Mar 12 12:30:59 PM PDT 24
Peak memory 203544 kb
Host smart-89829fdf-4cca-4dde-9b59-bc563a8709a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682089594 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.2682089594
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.72374919
Short name T73
Test name
Test status
Simulation time 979630261 ps
CPU time 1.22 seconds
Started Mar 12 12:30:44 PM PDT 24
Finished Mar 12 12:30:46 PM PDT 24
Peak memory 219524 kb
Host smart-a0e5819e-f30b-4681-8ae1-a16cca04a0ee
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72374919 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.72374919
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.2230900388
Short name T189
Test name
Test status
Simulation time 1015291800 ps
CPU time 1.04 seconds
Started Mar 12 12:30:31 PM PDT 24
Finished Mar 12 12:30:32 PM PDT 24
Peak memory 203092 kb
Host smart-abca9d13-f62a-47f6-93e8-f97ee3663e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230900388 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.2230900388
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.1828679166
Short name T25
Test name
Test status
Simulation time 1178174033 ps
CPU time 2.51 seconds
Started Mar 12 12:32:01 PM PDT 24
Finished Mar 12 12:32:03 PM PDT 24
Peak memory 203344 kb
Host smart-1b24dff2-cf54-4025-9c99-915b97e67d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828679166 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.1828679166
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.1568080445
Short name T135
Test name
Test status
Simulation time 50635861 ps
CPU time 0.67 seconds
Started Mar 12 12:30:35 PM PDT 24
Finished Mar 12 12:30:36 PM PDT 24
Peak memory 203208 kb
Host smart-c69f2dea-8637-48d7-9517-9313cb62bfef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568080445 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.1568080445
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.178736429
Short name T61
Test name
Test status
Simulation time 1078401576 ps
CPU time 5.54 seconds
Started Mar 12 12:30:45 PM PDT 24
Finished Mar 12 12:30:51 PM PDT 24
Peak memory 203620 kb
Host smart-9089b541-9115-47b3-b8d9-be1fc5964b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178736429 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.178736429
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.305810193
Short name T128
Test name
Test status
Simulation time 1136635864 ps
CPU time 4.44 seconds
Started Mar 12 12:30:34 PM PDT 24
Finished Mar 12 12:30:38 PM PDT 24
Peak memory 202620 kb
Host smart-3e74bd8c-a659-42a0-b994-8e7f16ff8125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305810193 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.305810193
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.2370570679
Short name T32
Test name
Test status
Simulation time 38490444 ps
CPU time 0.69 seconds
Started Mar 12 12:30:38 PM PDT 24
Finished Mar 12 12:30:39 PM PDT 24
Peak memory 203188 kb
Host smart-c6f0cee2-80c3-4152-8a7f-71e0e156a342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370570679 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.2370570679
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.936204423
Short name T27
Test name
Test status
Simulation time 230183906 ps
CPU time 1.32 seconds
Started Mar 12 12:30:34 PM PDT 24
Finished Mar 12 12:30:36 PM PDT 24
Peak memory 203112 kb
Host smart-6bd23f8d-3951-4bc7-9d9b-c601ad6a7385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936204423 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.936204423
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.946622637
Short name T23
Test name
Test status
Simulation time 1386443022 ps
CPU time 2.91 seconds
Started Mar 12 12:30:41 PM PDT 24
Finished Mar 12 12:30:45 PM PDT 24
Peak memory 203364 kb
Host smart-7e834bcb-71da-456b-936a-1b1ae2f0f3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946622637 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.946622637
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.1166434692
Short name T129
Test name
Test status
Simulation time 78381928 ps
CPU time 0.69 seconds
Started Mar 12 12:30:43 PM PDT 24
Finished Mar 12 12:30:44 PM PDT 24
Peak memory 203228 kb
Host smart-8b80c877-8762-4613-b09d-c71ef6c10db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166434692 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.1166434692
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.2420844187
Short name T160
Test name
Test status
Simulation time 1585282592 ps
CPU time 5.1 seconds
Started Mar 12 12:30:34 PM PDT 24
Finished Mar 12 12:30:39 PM PDT 24
Peak memory 203084 kb
Host smart-6c1f155e-4813-42f6-887d-f410931451ae
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2420844187 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.2420844187
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.1950390180
Short name T6
Test name
Test status
Simulation time 65251804 ps
CPU time 0.7 seconds
Started Mar 12 12:30:34 PM PDT 24
Finished Mar 12 12:30:34 PM PDT 24
Peak memory 203064 kb
Host smart-43e10f37-5962-491e-8aa8-a89d617ee320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950390180 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.1950390180
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.294312469
Short name T175
Test name
Test status
Simulation time 25561047 ps
CPU time 0.67 seconds
Started Mar 12 12:30:25 PM PDT 24
Finished Mar 12 12:30:26 PM PDT 24
Peak memory 203056 kb
Host smart-98855eb8-7a37-4776-9012-fab4edd6f830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294312469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.294312469
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.1770888348
Short name T205
Test name
Test status
Simulation time 399176130 ps
CPU time 1.7 seconds
Started Mar 12 12:30:40 PM PDT 24
Finished Mar 12 12:30:42 PM PDT 24
Peak memory 203088 kb
Host smart-ec754cb2-b495-4c15-8fbb-3fa4de22b3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770888348 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.1770888348
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.565475353
Short name T19
Test name
Test status
Simulation time 219816610 ps
CPU time 0.81 seconds
Started Mar 12 12:32:00 PM PDT 24
Finished Mar 12 12:32:01 PM PDT 24
Peak memory 203200 kb
Host smart-88842d8d-ad42-43d2-ad8a-308d0f25600c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565475353 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.565475353
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.3670793378
Short name T63
Test name
Test status
Simulation time 836838764 ps
CPU time 1.55 seconds
Started Mar 12 12:30:35 PM PDT 24
Finished Mar 12 12:30:36 PM PDT 24
Peak memory 203220 kb
Host smart-16f7956c-dcd4-4438-9663-a3cf3cc0ebe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670793378 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.3670793378
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.481953750
Short name T22
Test name
Test status
Simulation time 106936771 ps
CPU time 0.67 seconds
Started Mar 12 12:30:40 PM PDT 24
Finished Mar 12 12:30:41 PM PDT 24
Peak memory 203112 kb
Host smart-ab755e0e-80ca-42c7-a745-088efdcfdbba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481953750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.481953750
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.1887012892
Short name T7
Test name
Test status
Simulation time 77956107 ps
CPU time 0.77 seconds
Started Mar 12 12:30:41 PM PDT 24
Finished Mar 12 12:30:42 PM PDT 24
Peak memory 203200 kb
Host smart-e95d62e1-9476-43ac-983a-14ce7e1b141f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887012892 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.1887012892
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.926245626
Short name T130
Test name
Test status
Simulation time 314579564 ps
CPU time 0.7 seconds
Started Mar 12 12:30:28 PM PDT 24
Finished Mar 12 12:30:30 PM PDT 24
Peak memory 203220 kb
Host smart-3dc89a9d-d9d2-46c1-801c-2b2368247344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926245626 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.926245626
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.257317423
Short name T17
Test name
Test status
Simulation time 1908432913 ps
CPU time 2.71 seconds
Started Mar 12 12:30:34 PM PDT 24
Finished Mar 12 12:30:37 PM PDT 24
Peak memory 202796 kb
Host smart-822d8a92-c2f1-42f1-a3ea-c282a7db75e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257317423 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.257317423
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.1826919257
Short name T28
Test name
Test status
Simulation time 136384730 ps
CPU time 0.74 seconds
Started Mar 12 12:30:40 PM PDT 24
Finished Mar 12 12:30:41 PM PDT 24
Peak memory 203176 kb
Host smart-2a3ecd17-f31c-4889-9931-931fdb85cfba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826919257 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.1826919257
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.2512341356
Short name T177
Test name
Test status
Simulation time 12564606450 ps
CPU time 12.75 seconds
Started Mar 12 12:30:36 PM PDT 24
Finished Mar 12 12:30:49 PM PDT 24
Peak memory 203556 kb
Host smart-a5a9427c-e0ea-4f23-ab29-8359dec91a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512341356 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.2512341356
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.241883376
Short name T41
Test name
Test status
Simulation time 113045766 ps
CPU time 1.12 seconds
Started Mar 12 12:31:40 PM PDT 24
Finished Mar 12 12:31:41 PM PDT 24
Peak memory 218728 kb
Host smart-cfcdd163-87a0-41ee-86cc-7e9dd98890d7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241883376 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.241883376
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.2874534904
Short name T65
Test name
Test status
Simulation time 331977546 ps
CPU time 0.89 seconds
Started Mar 12 12:30:44 PM PDT 24
Finished Mar 12 12:30:45 PM PDT 24
Peak memory 203132 kb
Host smart-b305aeb2-c399-4948-8d53-daf86f590f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874534904 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.2874534904
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.2291166637
Short name T151
Test name
Test status
Simulation time 24678751 ps
CPU time 0.68 seconds
Started Mar 12 12:30:44 PM PDT 24
Finished Mar 12 12:30:45 PM PDT 24
Peak memory 203152 kb
Host smart-c8ce34a5-60f6-443c-b7ac-cccf668cc264
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291166637 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.2291166637
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.2222856337
Short name T197
Test name
Test status
Simulation time 13975602193 ps
CPU time 33.91 seconds
Started Mar 12 12:30:45 PM PDT 24
Finished Mar 12 12:31:19 PM PDT 24
Peak memory 203596 kb
Host smart-ba8d04e8-723c-48c8-b3bf-2bc808c5a674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222856337 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.2222856337
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.1973989828
Short name T214
Test name
Test status
Simulation time 760495446 ps
CPU time 2.73 seconds
Started Mar 12 12:31:01 PM PDT 24
Finished Mar 12 12:31:04 PM PDT 24
Peak memory 203440 kb
Host smart-2e8de69f-c325-4f0a-b1df-49c054bbd00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973989828 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.1973989828
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.1845538418
Short name T213
Test name
Test status
Simulation time 5192793415 ps
CPU time 19.91 seconds
Started Mar 12 12:30:45 PM PDT 24
Finished Mar 12 12:31:05 PM PDT 24
Peak memory 203532 kb
Host smart-115bc827-d413-44bf-9f9c-91d261ace660
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1845538418 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.1845538418
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.592280048
Short name T173
Test name
Test status
Simulation time 521615607 ps
CPU time 1.56 seconds
Started Mar 12 12:31:21 PM PDT 24
Finished Mar 12 12:31:23 PM PDT 24
Peak memory 203496 kb
Host smart-d509e85c-e1f1-46ad-ae3a-305c073e5133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592280048 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.592280048
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.1621076761
Short name T142
Test name
Test status
Simulation time 41391780 ps
CPU time 0.64 seconds
Started Mar 12 12:30:42 PM PDT 24
Finished Mar 12 12:30:43 PM PDT 24
Peak memory 203204 kb
Host smart-1335d3c3-5b6e-4488-8890-e0c4eb549373
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621076761 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.1621076761
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.2568236948
Short name T181
Test name
Test status
Simulation time 5657128945 ps
CPU time 20.38 seconds
Started Mar 12 12:30:36 PM PDT 24
Finished Mar 12 12:30:56 PM PDT 24
Peak memory 203532 kb
Host smart-74b81829-f9c9-4be4-896a-8f7728b0c3d4
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2568236948 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_
tl_access.2568236948
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.3481537222
Short name T39
Test name
Test status
Simulation time 925236730 ps
CPU time 1.78 seconds
Started Mar 12 12:30:36 PM PDT 24
Finished Mar 12 12:30:44 PM PDT 24
Peak memory 203504 kb
Host smart-b83fce37-8928-4e2e-a963-0f9e639e24d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481537222 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.3481537222
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.1197297750
Short name T144
Test name
Test status
Simulation time 40011469 ps
CPU time 0.67 seconds
Started Mar 12 12:30:43 PM PDT 24
Finished Mar 12 12:30:44 PM PDT 24
Peak memory 203192 kb
Host smart-6f546149-d7be-4961-bfc4-baa8e9bd77e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197297750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.1197297750
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.2855465245
Short name T194
Test name
Test status
Simulation time 7423813075 ps
CPU time 27.61 seconds
Started Mar 12 12:30:45 PM PDT 24
Finished Mar 12 12:31:13 PM PDT 24
Peak memory 203520 kb
Host smart-bd3dcdab-9cee-4376-ba6a-a7b0e0475bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855465245 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.2855465245
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.1211477917
Short name T190
Test name
Test status
Simulation time 2746998853 ps
CPU time 10.02 seconds
Started Mar 12 12:30:45 PM PDT 24
Finished Mar 12 12:30:55 PM PDT 24
Peak memory 203588 kb
Host smart-8b074496-f543-4d43-8a03-aeada8a641e3
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1211477917 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.1211477917
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.805784388
Short name T170
Test name
Test status
Simulation time 2411121599 ps
CPU time 5.04 seconds
Started Mar 12 12:30:55 PM PDT 24
Finished Mar 12 12:31:00 PM PDT 24
Peak memory 203588 kb
Host smart-2687d5ea-d6dc-404a-b322-f05e421562fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805784388 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.805784388
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.3891553420
Short name T150
Test name
Test status
Simulation time 128891884 ps
CPU time 0.65 seconds
Started Mar 12 12:30:50 PM PDT 24
Finished Mar 12 12:30:51 PM PDT 24
Peak memory 203172 kb
Host smart-1ae4a499-9e64-4707-96a6-ba7841ee4ec7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891553420 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.3891553420
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.942729416
Short name T62
Test name
Test status
Simulation time 3635158346 ps
CPU time 4.44 seconds
Started Mar 12 12:31:07 PM PDT 24
Finished Mar 12 12:31:12 PM PDT 24
Peak memory 203632 kb
Host smart-9b2a5c66-3a64-4a27-adb8-c1b6052f39c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942729416 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.942729416
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.2046488589
Short name T171
Test name
Test status
Simulation time 1694809782 ps
CPU time 8.31 seconds
Started Mar 12 12:30:46 PM PDT 24
Finished Mar 12 12:30:54 PM PDT 24
Peak memory 203520 kb
Host smart-56b17a38-d725-4703-a5b1-7a7811e8be3c
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2046488589 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_
tl_access.2046488589
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.659034527
Short name T202
Test name
Test status
Simulation time 2405713857 ps
CPU time 7.43 seconds
Started Mar 12 12:30:45 PM PDT 24
Finished Mar 12 12:30:53 PM PDT 24
Peak memory 203544 kb
Host smart-2007abd9-0a63-4a49-a9a9-56db8c066633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659034527 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.659034527
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.2740492848
Short name T72
Test name
Test status
Simulation time 121489697 ps
CPU time 0.66 seconds
Started Mar 12 12:30:48 PM PDT 24
Finished Mar 12 12:30:49 PM PDT 24
Peak memory 203212 kb
Host smart-4ec821e5-d8df-4148-ad50-d07e8a85e899
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740492848 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.2740492848
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.1571759432
Short name T200
Test name
Test status
Simulation time 1411820280 ps
CPU time 5.79 seconds
Started Mar 12 12:31:02 PM PDT 24
Finished Mar 12 12:31:08 PM PDT 24
Peak memory 203496 kb
Host smart-81fb6b02-a70d-428f-80fa-cc28bc11e432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571759432 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.1571759432
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.1444342329
Short name T161
Test name
Test status
Simulation time 3337915599 ps
CPU time 6.43 seconds
Started Mar 12 12:30:57 PM PDT 24
Finished Mar 12 12:31:04 PM PDT 24
Peak memory 203524 kb
Host smart-8c371c94-410e-4ed2-8e3d-eb1728a1d641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444342329 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.1444342329
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.1947344137
Short name T159
Test name
Test status
Simulation time 1475397271 ps
CPU time 4.83 seconds
Started Mar 12 12:32:00 PM PDT 24
Finished Mar 12 12:32:05 PM PDT 24
Peak memory 203564 kb
Host smart-18c27253-b991-4767-92f1-d78391bed82b
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1947344137 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.1947344137
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.2970116648
Short name T10
Test name
Test status
Simulation time 9613287713 ps
CPU time 20.08 seconds
Started Mar 12 12:30:46 PM PDT 24
Finished Mar 12 12:31:07 PM PDT 24
Peak memory 203592 kb
Host smart-92c0ccd3-47c9-4a39-b6e1-ce42f7ef0859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970116648 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.2970116648
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.4280228436
Short name T145
Test name
Test status
Simulation time 23228358 ps
CPU time 0.67 seconds
Started Mar 12 12:30:49 PM PDT 24
Finished Mar 12 12:30:49 PM PDT 24
Peak memory 203228 kb
Host smart-a05bab75-22df-4513-a5fa-0148f38a3b29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280228436 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.4280228436
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.29882523
Short name T192
Test name
Test status
Simulation time 5624824201 ps
CPU time 12.51 seconds
Started Mar 12 12:30:40 PM PDT 24
Finished Mar 12 12:30:52 PM PDT 24
Peak memory 204020 kb
Host smart-e7ba12b5-cfda-491f-b91b-e9d8a4a56094
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=29882523 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_tl
_access.29882523
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.2542791098
Short name T204
Test name
Test status
Simulation time 2124878722 ps
CPU time 4.6 seconds
Started Mar 12 12:30:44 PM PDT 24
Finished Mar 12 12:30:49 PM PDT 24
Peak memory 203464 kb
Host smart-2b184c12-4eec-474c-a7f2-4f91cdd248e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542791098 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.2542791098
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.4073270617
Short name T138
Test name
Test status
Simulation time 32530442 ps
CPU time 0.7 seconds
Started Mar 12 12:30:59 PM PDT 24
Finished Mar 12 12:31:00 PM PDT 24
Peak memory 203160 kb
Host smart-d7c0d9bf-c143-4085-a98f-d1c8409df37b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073270617 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.4073270617
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.1836613392
Short name T217
Test name
Test status
Simulation time 1706003150 ps
CPU time 4.77 seconds
Started Mar 12 12:30:44 PM PDT 24
Finished Mar 12 12:30:49 PM PDT 24
Peak memory 203504 kb
Host smart-239ed411-c083-404f-bd89-46b796829939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836613392 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.1836613392
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.1289338348
Short name T206
Test name
Test status
Simulation time 6240437113 ps
CPU time 12.95 seconds
Started Mar 12 12:30:48 PM PDT 24
Finished Mar 12 12:31:01 PM PDT 24
Peak memory 203632 kb
Host smart-eae81827-ff0a-46f0-a97a-4f2581add54e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1289338348 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_
tl_access.1289338348
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.3210815606
Short name T178
Test name
Test status
Simulation time 2476124661 ps
CPU time 10.58 seconds
Started Mar 12 12:30:51 PM PDT 24
Finished Mar 12 12:31:02 PM PDT 24
Peak memory 203544 kb
Host smart-90e9f83a-fd0a-45ef-aa1c-6bc72f4a5216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210815606 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.3210815606
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.1589113492
Short name T153
Test name
Test status
Simulation time 17683679 ps
CPU time 0.69 seconds
Started Mar 12 12:31:03 PM PDT 24
Finished Mar 12 12:31:03 PM PDT 24
Peak memory 203216 kb
Host smart-204197dc-d6a9-459b-bbb2-1615b7eec265
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589113492 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.1589113492
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.1879642765
Short name T185
Test name
Test status
Simulation time 21595320533 ps
CPU time 37.65 seconds
Started Mar 12 12:30:46 PM PDT 24
Finished Mar 12 12:31:23 PM PDT 24
Peak memory 203516 kb
Host smart-4b4696b0-36c9-46a4-9a5f-33c7c72de504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879642765 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.1879642765
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.1967536460
Short name T166
Test name
Test status
Simulation time 794449488 ps
CPU time 2.3 seconds
Started Mar 12 12:30:45 PM PDT 24
Finished Mar 12 12:30:48 PM PDT 24
Peak memory 203616 kb
Host smart-efd38b58-d053-4a00-8c27-759d706313ee
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1967536460 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_
tl_access.1967536460
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.901090510
Short name T86
Test name
Test status
Simulation time 956564087 ps
CPU time 4.11 seconds
Started Mar 12 12:30:50 PM PDT 24
Finished Mar 12 12:30:55 PM PDT 24
Peak memory 203576 kb
Host smart-40fb8b41-c94f-44e1-9224-f87239f9fecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901090510 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.901090510
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.686217332
Short name T132
Test name
Test status
Simulation time 26270341 ps
CPU time 0.67 seconds
Started Mar 12 12:30:55 PM PDT 24
Finished Mar 12 12:30:56 PM PDT 24
Peak memory 203244 kb
Host smart-193f482e-d7a4-4753-b783-bae8a5705533
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686217332 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.686217332
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.3528167498
Short name T187
Test name
Test status
Simulation time 4802789446 ps
CPU time 5.7 seconds
Started Mar 12 12:31:04 PM PDT 24
Finished Mar 12 12:31:09 PM PDT 24
Peak memory 203544 kb
Host smart-63994e03-5e5c-4169-a83d-5d746dca34db
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3528167498 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_
tl_access.3528167498
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.649159938
Short name T226
Test name
Test status
Simulation time 3493002043 ps
CPU time 6.26 seconds
Started Mar 12 12:30:51 PM PDT 24
Finished Mar 12 12:30:57 PM PDT 24
Peak memory 203544 kb
Host smart-e864a180-e12d-4e99-a310-e80850a31115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649159938 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.649159938
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.490437679
Short name T54
Test name
Test status
Simulation time 28131102 ps
CPU time 0.72 seconds
Started Mar 12 12:31:06 PM PDT 24
Finished Mar 12 12:31:07 PM PDT 24
Peak memory 203232 kb
Host smart-7aef8fdb-cdfc-4570-b689-37d38c93c175
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490437679 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.490437679
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.2430269899
Short name T183
Test name
Test status
Simulation time 4756775588 ps
CPU time 16.8 seconds
Started Mar 12 12:31:00 PM PDT 24
Finished Mar 12 12:31:17 PM PDT 24
Peak memory 203600 kb
Host smart-4f4bbc92-76ad-45ee-895f-7d660c0c11df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430269899 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.2430269899
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.1799553747
Short name T208
Test name
Test status
Simulation time 3220971306 ps
CPU time 7.49 seconds
Started Mar 12 12:31:02 PM PDT 24
Finished Mar 12 12:31:10 PM PDT 24
Peak memory 203532 kb
Host smart-aaa452c3-d711-4f37-8334-d7d1746e58c2
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1799553747 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_
tl_access.1799553747
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.2113342640
Short name T168
Test name
Test status
Simulation time 4797004657 ps
CPU time 7.62 seconds
Started Mar 12 12:30:43 PM PDT 24
Finished Mar 12 12:30:51 PM PDT 24
Peak memory 203648 kb
Host smart-f55fbfd8-0eac-4dab-b488-f79592ac83d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113342640 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.2113342640
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.3994970334
Short name T139
Test name
Test status
Simulation time 43350502 ps
CPU time 0.64 seconds
Started Mar 12 12:30:33 PM PDT 24
Finished Mar 12 12:30:34 PM PDT 24
Peak memory 203200 kb
Host smart-f85c9c74-7df8-42cc-b651-a3e0cddadc49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994970334 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.3994970334
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.668914484
Short name T20
Test name
Test status
Simulation time 8010960390 ps
CPU time 8.94 seconds
Started Mar 12 12:30:37 PM PDT 24
Finished Mar 12 12:30:46 PM PDT 24
Peak memory 203536 kb
Host smart-8274c4f7-cc98-4639-a349-1fdf0b5b74a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668914484 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.668914484
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.1056616732
Short name T224
Test name
Test status
Simulation time 4597619465 ps
CPU time 9.89 seconds
Started Mar 12 12:31:59 PM PDT 24
Finished Mar 12 12:32:09 PM PDT 24
Peak memory 203592 kb
Host smart-57c08dba-3345-4142-bec7-572dff16261f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1056616732 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.1056616732
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.3545471907
Short name T165
Test name
Test status
Simulation time 56376045 ps
CPU time 0.71 seconds
Started Mar 12 12:30:36 PM PDT 24
Finished Mar 12 12:30:37 PM PDT 24
Peak memory 203148 kb
Host smart-3e36cd35-f0fc-4252-8989-c039203ac94b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545471907 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.3545471907
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.3225361858
Short name T188
Test name
Test status
Simulation time 924533412 ps
CPU time 3.56 seconds
Started Mar 12 12:30:36 PM PDT 24
Finished Mar 12 12:30:40 PM PDT 24
Peak memory 203484 kb
Host smart-dae38e8a-51d0-4284-a378-7de180f64a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225361858 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.3225361858
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.1801232231
Short name T74
Test name
Test status
Simulation time 123784359 ps
CPU time 1.18 seconds
Started Mar 12 12:31:59 PM PDT 24
Finished Mar 12 12:32:00 PM PDT 24
Peak memory 219288 kb
Host smart-504c0454-118c-4f01-ad57-dfd14fbae517
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801232231 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.1801232231
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.273523996
Short name T148
Test name
Test status
Simulation time 24825120 ps
CPU time 0.69 seconds
Started Mar 12 12:30:49 PM PDT 24
Finished Mar 12 12:30:50 PM PDT 24
Peak memory 203332 kb
Host smart-d00e7f59-d389-4663-b9ae-13bea7ccbbd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273523996 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.273523996
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.3654845674
Short name T1
Test name
Test status
Simulation time 42836188 ps
CPU time 0.63 seconds
Started Mar 12 12:30:49 PM PDT 24
Finished Mar 12 12:30:50 PM PDT 24
Peak memory 203204 kb
Host smart-19349ffc-c40c-4f15-a82e-914d9b0977e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654845674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.3654845674
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.2911233328
Short name T176
Test name
Test status
Simulation time 29763055 ps
CPU time 0.69 seconds
Started Mar 12 12:31:08 PM PDT 24
Finished Mar 12 12:31:09 PM PDT 24
Peak memory 203236 kb
Host smart-89827b18-9e5f-4ede-a060-69f496be6b4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911233328 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.2911233328
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.3226090026
Short name T157
Test name
Test status
Simulation time 69093807 ps
CPU time 0.65 seconds
Started Mar 12 12:30:53 PM PDT 24
Finished Mar 12 12:30:54 PM PDT 24
Peak memory 203168 kb
Host smart-50a47e12-7974-4126-bef9-f3e7b88850c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226090026 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.3226090026
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.3571452459
Short name T216
Test name
Test status
Simulation time 34034314 ps
CPU time 0.65 seconds
Started Mar 12 12:31:06 PM PDT 24
Finished Mar 12 12:31:07 PM PDT 24
Peak memory 203060 kb
Host smart-2cebbfd9-1b45-41be-b7c3-8f027f68b7aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571452459 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.3571452459
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.1494208834
Short name T179
Test name
Test status
Simulation time 21354683 ps
CPU time 0.66 seconds
Started Mar 12 12:30:47 PM PDT 24
Finished Mar 12 12:30:48 PM PDT 24
Peak memory 203148 kb
Host smart-7ede5f38-4803-4a8a-83f7-765caa301811
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494208834 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.1494208834
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.1784444602
Short name T149
Test name
Test status
Simulation time 29499572 ps
CPU time 0.68 seconds
Started Mar 12 12:30:46 PM PDT 24
Finished Mar 12 12:30:46 PM PDT 24
Peak memory 203240 kb
Host smart-22e944d8-e548-4786-ad07-5de8f965bd88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784444602 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.1784444602
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.3393225036
Short name T140
Test name
Test status
Simulation time 28829405 ps
CPU time 0.62 seconds
Started Mar 12 12:30:51 PM PDT 24
Finished Mar 12 12:30:52 PM PDT 24
Peak memory 203228 kb
Host smart-2d47c6ad-4b7e-40e3-bdd2-53d346fb3bb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393225036 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.3393225036
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.1602986475
Short name T2
Test name
Test status
Simulation time 28756588 ps
CPU time 0.68 seconds
Started Mar 12 12:31:04 PM PDT 24
Finished Mar 12 12:31:05 PM PDT 24
Peak memory 203200 kb
Host smart-32e1d80a-425f-4b13-8f39-32cef68c52b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602986475 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.1602986475
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.43242688
Short name T87
Test name
Test status
Simulation time 40992764 ps
CPU time 0.62 seconds
Started Mar 12 12:30:36 PM PDT 24
Finished Mar 12 12:30:37 PM PDT 24
Peak memory 203220 kb
Host smart-e78ef2a0-8b99-493f-b88e-7e89b8c7274b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43242688 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.43242688
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.2022376906
Short name T227
Test name
Test status
Simulation time 3618593303 ps
CPU time 10.56 seconds
Started Mar 12 12:30:36 PM PDT 24
Finished Mar 12 12:30:47 PM PDT 24
Peak memory 203520 kb
Host smart-b29e74d5-f6a9-47bb-a45c-8acf1415b7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022376906 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.2022376906
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.693956012
Short name T172
Test name
Test status
Simulation time 14630683721 ps
CPU time 16.43 seconds
Started Mar 12 12:30:51 PM PDT 24
Finished Mar 12 12:31:08 PM PDT 24
Peak memory 203584 kb
Host smart-5fa26feb-df96-4f2b-880c-f07656d481a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693956012 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.693956012
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.1351550717
Short name T169
Test name
Test status
Simulation time 1883253654 ps
CPU time 4.56 seconds
Started Mar 12 12:30:35 PM PDT 24
Finished Mar 12 12:30:40 PM PDT 24
Peak memory 203512 kb
Host smart-034eea6c-75e7-423f-884a-a6463f0dfe65
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1351550717 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.1351550717
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.2309210940
Short name T9
Test name
Test status
Simulation time 47065706 ps
CPU time 0.77 seconds
Started Mar 12 12:30:41 PM PDT 24
Finished Mar 12 12:30:42 PM PDT 24
Peak memory 202956 kb
Host smart-c3cda1fb-4322-41b3-ad88-cae4c3988069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309210940 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.2309210940
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.2264439855
Short name T193
Test name
Test status
Simulation time 11657103396 ps
CPU time 10.85 seconds
Started Mar 12 12:31:40 PM PDT 24
Finished Mar 12 12:31:51 PM PDT 24
Peak memory 202812 kb
Host smart-b450a03c-24d9-4615-a3be-83def37a6479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264439855 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.2264439855
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.3231186752
Short name T37
Test name
Test status
Simulation time 205359191 ps
CPU time 1.46 seconds
Started Mar 12 12:30:41 PM PDT 24
Finished Mar 12 12:30:43 PM PDT 24
Peak memory 219420 kb
Host smart-ceeff36f-b2a7-423d-a555-96e8fb518656
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231186752 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.3231186752
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.3420777385
Short name T131
Test name
Test status
Simulation time 93952699 ps
CPU time 0.66 seconds
Started Mar 12 12:31:12 PM PDT 24
Finished Mar 12 12:31:13 PM PDT 24
Peak memory 203236 kb
Host smart-2b564135-4e9d-4d03-89e7-fdfce8f05795
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420777385 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.3420777385
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.1185287709
Short name T191
Test name
Test status
Simulation time 29895150 ps
CPU time 0.66 seconds
Started Mar 12 12:31:09 PM PDT 24
Finished Mar 12 12:31:10 PM PDT 24
Peak memory 203156 kb
Host smart-ba176142-c8de-4e4b-840b-757733527986
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185287709 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.1185287709
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.2445097459
Short name T195
Test name
Test status
Simulation time 31870952 ps
CPU time 0.65 seconds
Started Mar 12 12:31:06 PM PDT 24
Finished Mar 12 12:31:07 PM PDT 24
Peak memory 203232 kb
Host smart-3630e901-4ffd-4670-ba3b-24d2912fb34c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445097459 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.2445097459
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.3111802200
Short name T174
Test name
Test status
Simulation time 24869698 ps
CPU time 0.71 seconds
Started Mar 12 12:31:00 PM PDT 24
Finished Mar 12 12:31:01 PM PDT 24
Peak memory 203216 kb
Host smart-78e2aee0-cc64-4055-806b-cabf13bd025f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111802200 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.3111802200
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_stress_all.3832493932
Short name T35
Test name
Test status
Simulation time 2948654568 ps
CPU time 9.99 seconds
Started Mar 12 12:30:54 PM PDT 24
Finished Mar 12 12:31:10 PM PDT 24
Peak memory 203452 kb
Host smart-769bfcbd-e376-4d46-9149-c91cc419d9b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832493932 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.3832493932
Directory /workspace/33.rv_dm_stress_all/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.282399522
Short name T207
Test name
Test status
Simulation time 50613122 ps
CPU time 0.69 seconds
Started Mar 12 12:30:51 PM PDT 24
Finished Mar 12 12:30:52 PM PDT 24
Peak memory 203184 kb
Host smart-bf58b6a5-42d6-4979-a42c-c574d804bee2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282399522 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.282399522
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.3570892462
Short name T36
Test name
Test status
Simulation time 65973743 ps
CPU time 0.66 seconds
Started Mar 12 12:30:52 PM PDT 24
Finished Mar 12 12:30:53 PM PDT 24
Peak memory 203172 kb
Host smart-f9b501aa-4af4-4b3c-b61f-8a3872540384
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570892462 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.3570892462
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.2236148318
Short name T51
Test name
Test status
Simulation time 50995088 ps
CPU time 0.63 seconds
Started Mar 12 12:30:56 PM PDT 24
Finished Mar 12 12:30:57 PM PDT 24
Peak memory 203168 kb
Host smart-9f0325c8-4080-425b-ab0b-50f7cf72da79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236148318 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.2236148318
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.787697902
Short name T143
Test name
Test status
Simulation time 45403057 ps
CPU time 0.68 seconds
Started Mar 12 12:31:05 PM PDT 24
Finished Mar 12 12:31:06 PM PDT 24
Peak memory 203228 kb
Host smart-48bf872c-7d3c-4fc9-80a6-90f57447ef46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787697902 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.787697902
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_stress_all.1513983960
Short name T34
Test name
Test status
Simulation time 3034391526 ps
CPU time 10.1 seconds
Started Mar 12 12:31:11 PM PDT 24
Finished Mar 12 12:31:21 PM PDT 24
Peak memory 203448 kb
Host smart-c37fe036-c118-4527-802d-e39bd196e8c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513983960 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.1513983960
Directory /workspace/38.rv_dm_stress_all/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.1087004809
Short name T3
Test name
Test status
Simulation time 53111774 ps
CPU time 0.69 seconds
Started Mar 12 12:31:09 PM PDT 24
Finished Mar 12 12:31:10 PM PDT 24
Peak memory 203228 kb
Host smart-c5cd62a4-a3d9-4ec1-955b-138ff8f014b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087004809 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.1087004809
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.1734674068
Short name T155
Test name
Test status
Simulation time 16620334 ps
CPU time 0.66 seconds
Started Mar 12 12:30:31 PM PDT 24
Finished Mar 12 12:30:32 PM PDT 24
Peak memory 203196 kb
Host smart-ffcfb40a-ba9b-495e-b996-b1f30426a26f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734674068 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.1734674068
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.4137464071
Short name T222
Test name
Test status
Simulation time 29662725349 ps
CPU time 97.32 seconds
Started Mar 12 12:30:39 PM PDT 24
Finished Mar 12 12:32:17 PM PDT 24
Peak memory 203596 kb
Host smart-4d946b80-f0a2-46eb-8fcc-059e63e37a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137464071 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.4137464071
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.331718869
Short name T201
Test name
Test status
Simulation time 1648210832 ps
CPU time 4.3 seconds
Started Mar 12 12:30:41 PM PDT 24
Finished Mar 12 12:30:45 PM PDT 24
Peak memory 203548 kb
Host smart-e504b97d-eaba-489f-b6ef-354063b6acae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331718869 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.331718869
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.2339414329
Short name T219
Test name
Test status
Simulation time 668523029 ps
CPU time 1.8 seconds
Started Mar 12 12:30:41 PM PDT 24
Finished Mar 12 12:30:44 PM PDT 24
Peak memory 203340 kb
Host smart-74c2d3cc-694c-494c-8c20-a584e6236a95
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2339414329 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.2339414329
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.2830019596
Short name T164
Test name
Test status
Simulation time 5578351507 ps
CPU time 9.21 seconds
Started Mar 12 12:30:41 PM PDT 24
Finished Mar 12 12:30:51 PM PDT 24
Peak memory 203396 kb
Host smart-0322bdb1-016b-4809-91d6-a6135e4e07eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830019596 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.2830019596
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.1942566149
Short name T152
Test name
Test status
Simulation time 47521241 ps
CPU time 0.67 seconds
Started Mar 12 12:31:09 PM PDT 24
Finished Mar 12 12:31:10 PM PDT 24
Peak memory 203244 kb
Host smart-3bfca156-9c04-45d0-b0a9-64546e3b7cdb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942566149 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.1942566149
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/40.rv_dm_stress_all.3941525887
Short name T82
Test name
Test status
Simulation time 5865156525 ps
CPU time 9.71 seconds
Started Mar 12 12:30:53 PM PDT 24
Finished Mar 12 12:31:03 PM PDT 24
Peak memory 203400 kb
Host smart-bdaf2f66-5935-464e-b34f-ee4660a08cbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941525887 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.3941525887
Directory /workspace/40.rv_dm_stress_all/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.632992754
Short name T137
Test name
Test status
Simulation time 31643466 ps
CPU time 0.72 seconds
Started Mar 12 12:31:02 PM PDT 24
Finished Mar 12 12:31:03 PM PDT 24
Peak memory 203200 kb
Host smart-396196e5-559f-4ebb-91d4-800432b627cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632992754 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.632992754
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.2392749795
Short name T52
Test name
Test status
Simulation time 24120749 ps
CPU time 0.63 seconds
Started Mar 12 12:31:05 PM PDT 24
Finished Mar 12 12:31:06 PM PDT 24
Peak memory 203212 kb
Host smart-e052b59d-8150-4fb6-b60d-7c8a4a708a2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392749795 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.2392749795
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.1243902679
Short name T134
Test name
Test status
Simulation time 53325516 ps
CPU time 0.67 seconds
Started Mar 12 12:30:52 PM PDT 24
Finished Mar 12 12:30:53 PM PDT 24
Peak memory 203168 kb
Host smart-d7ca2b6f-873b-4eec-8742-06de6e92937c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243902679 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.1243902679
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.25842759
Short name T215
Test name
Test status
Simulation time 25419300 ps
CPU time 0.66 seconds
Started Mar 12 12:31:00 PM PDT 24
Finished Mar 12 12:31:02 PM PDT 24
Peak memory 203224 kb
Host smart-793855b2-ccb6-4a23-910e-0babec747791
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25842759 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.25842759
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.351804522
Short name T218
Test name
Test status
Simulation time 39712359 ps
CPU time 0.67 seconds
Started Mar 12 12:31:12 PM PDT 24
Finished Mar 12 12:31:13 PM PDT 24
Peak memory 203236 kb
Host smart-f9baa529-ebf9-4db2-a25d-6d3b2dee45ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351804522 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.351804522
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_stress_all.1641434745
Short name T18
Test name
Test status
Simulation time 3672433973 ps
CPU time 11.78 seconds
Started Mar 12 12:31:07 PM PDT 24
Finished Mar 12 12:31:19 PM PDT 24
Peak memory 203500 kb
Host smart-8bd18579-db1c-4ea4-9ca3-3e9a268a6861
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641434745 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.1641434745
Directory /workspace/45.rv_dm_stress_all/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.1529431884
Short name T220
Test name
Test status
Simulation time 47768435 ps
CPU time 0.65 seconds
Started Mar 12 12:31:11 PM PDT 24
Finished Mar 12 12:31:12 PM PDT 24
Peak memory 203228 kb
Host smart-53430989-3ae7-4370-8649-cf596dcc805f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529431884 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.1529431884
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.3395875011
Short name T212
Test name
Test status
Simulation time 21989543 ps
CPU time 0.67 seconds
Started Mar 12 12:31:12 PM PDT 24
Finished Mar 12 12:31:13 PM PDT 24
Peak memory 203128 kb
Host smart-8266978b-050c-479d-9ef9-687df3b5de87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395875011 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.3395875011
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.1214139921
Short name T141
Test name
Test status
Simulation time 103396029 ps
CPU time 0.64 seconds
Started Mar 12 12:31:11 PM PDT 24
Finished Mar 12 12:31:12 PM PDT 24
Peak memory 203248 kb
Host smart-4a127226-a2c5-4219-93b7-76e79f07c00c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214139921 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.1214139921
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.4282150471
Short name T136
Test name
Test status
Simulation time 15601358 ps
CPU time 0.64 seconds
Started Mar 12 12:31:00 PM PDT 24
Finished Mar 12 12:31:01 PM PDT 24
Peak memory 203192 kb
Host smart-f92f92c8-7c34-43a8-9145-5a8ea2304734
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282150471 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.4282150471
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.2449575708
Short name T133
Test name
Test status
Simulation time 30147413 ps
CPU time 0.67 seconds
Started Mar 12 12:30:44 PM PDT 24
Finished Mar 12 12:30:44 PM PDT 24
Peak memory 203256 kb
Host smart-2989e17f-f9f7-453e-88b3-816fd7d9ab27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449575708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.2449575708
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.3898114458
Short name T210
Test name
Test status
Simulation time 5224663495 ps
CPU time 17.15 seconds
Started Mar 12 12:30:44 PM PDT 24
Finished Mar 12 12:31:01 PM PDT 24
Peak memory 203632 kb
Host smart-d255bf07-2560-44eb-8bf5-318620ade0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898114458 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.3898114458
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.2375990479
Short name T223
Test name
Test status
Simulation time 8050640753 ps
CPU time 11.48 seconds
Started Mar 12 12:30:44 PM PDT 24
Finished Mar 12 12:30:55 PM PDT 24
Peak memory 203588 kb
Host smart-ce3d9b8f-b123-4ef5-a674-0109b9924c4f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2375990479 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t
l_access.2375990479
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.3916658310
Short name T162
Test name
Test status
Simulation time 4641776947 ps
CPU time 14.46 seconds
Started Mar 12 12:30:21 PM PDT 24
Finished Mar 12 12:30:35 PM PDT 24
Peak memory 203580 kb
Host smart-8d80b8cd-8ac2-4c24-8cd6-17065d31e444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916658310 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.3916658310
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.3600762348
Short name T147
Test name
Test status
Simulation time 53138268 ps
CPU time 0.65 seconds
Started Mar 12 12:30:48 PM PDT 24
Finished Mar 12 12:30:49 PM PDT 24
Peak memory 203236 kb
Host smart-3e2ca959-0909-488e-bf60-3cb26bba3fff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600762348 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.3600762348
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.998923341
Short name T182
Test name
Test status
Simulation time 1410609972 ps
CPU time 6.29 seconds
Started Mar 12 12:30:44 PM PDT 24
Finished Mar 12 12:30:50 PM PDT 24
Peak memory 203520 kb
Host smart-da068102-3ddf-429e-a25c-16c3a8856d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998923341 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.998923341
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.3980612110
Short name T198
Test name
Test status
Simulation time 6782624216 ps
CPU time 22.42 seconds
Started Mar 12 12:30:57 PM PDT 24
Finished Mar 12 12:31:19 PM PDT 24
Peak memory 203552 kb
Host smart-1843d81a-1811-46fc-ad06-3bcdb096380c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980612110 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.3980612110
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.1689270697
Short name T154
Test name
Test status
Simulation time 27445517 ps
CPU time 0.66 seconds
Started Mar 12 12:30:59 PM PDT 24
Finished Mar 12 12:31:00 PM PDT 24
Peak memory 203196 kb
Host smart-7080f9c6-2bf3-42f6-97e6-3fd6fef7d285
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689270697 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.1689270697
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.2085186221
Short name T225
Test name
Test status
Simulation time 2206141359 ps
CPU time 3.1 seconds
Started Mar 12 12:30:44 PM PDT 24
Finished Mar 12 12:30:48 PM PDT 24
Peak memory 203508 kb
Host smart-c9138c01-0e2d-4c19-a6e9-62dc061393e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085186221 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.2085186221
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.4194320744
Short name T186
Test name
Test status
Simulation time 6999261127 ps
CPU time 10.15 seconds
Started Mar 12 12:30:38 PM PDT 24
Finished Mar 12 12:30:48 PM PDT 24
Peak memory 203572 kb
Host smart-c6f9822e-2474-406c-bb07-c4a69ed5fe00
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4194320744 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.4194320744
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.534332508
Short name T158
Test name
Test status
Simulation time 14060658652 ps
CPU time 13.42 seconds
Started Mar 12 12:30:42 PM PDT 24
Finished Mar 12 12:30:56 PM PDT 24
Peak memory 203536 kb
Host smart-64bf70fc-7ddb-48ab-929b-4f8ffcd9a6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534332508 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.534332508
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.1397467505
Short name T199
Test name
Test status
Simulation time 43957157 ps
CPU time 0.66 seconds
Started Mar 12 12:30:43 PM PDT 24
Finished Mar 12 12:30:43 PM PDT 24
Peak memory 203164 kb
Host smart-925e9798-cd70-4866-89c5-f778269fdcc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397467505 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.1397467505
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.4120279837
Short name T15
Test name
Test status
Simulation time 6779220058 ps
CPU time 13.34 seconds
Started Mar 12 12:30:55 PM PDT 24
Finished Mar 12 12:31:09 PM PDT 24
Peak memory 203592 kb
Host smart-b50ae8fb-8f98-4c53-b9a2-1b9755ebd27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120279837 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.4120279837
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.2240100087
Short name T184
Test name
Test status
Simulation time 5549383623 ps
CPU time 12.19 seconds
Started Mar 12 12:30:57 PM PDT 24
Finished Mar 12 12:31:09 PM PDT 24
Peak memory 203560 kb
Host smart-c2af42f4-0597-4429-ac9b-dd27b02aca2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240100087 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.2240100087
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.2606024751
Short name T70
Test name
Test status
Simulation time 4670191416 ps
CPU time 15.95 seconds
Started Mar 12 12:31:57 PM PDT 24
Finished Mar 12 12:32:13 PM PDT 24
Peak memory 203592 kb
Host smart-b6eaf25e-a8a2-4b1d-8884-eb19c4408846
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2606024751 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t
l_access.2606024751
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.161403136
Short name T163
Test name
Test status
Simulation time 5813919723 ps
CPU time 17.81 seconds
Started Mar 12 12:30:49 PM PDT 24
Finished Mar 12 12:31:07 PM PDT 24
Peak memory 203608 kb
Host smart-f5e35aac-554f-4496-915a-b86f03c27b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161403136 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.161403136
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.1347633735
Short name T146
Test name
Test status
Simulation time 116377227 ps
CPU time 0.66 seconds
Started Mar 12 12:30:40 PM PDT 24
Finished Mar 12 12:30:41 PM PDT 24
Peak memory 203208 kb
Host smart-259f3f42-4239-4d2f-9dca-3aab20a029fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347633735 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.1347633735
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.2302731133
Short name T167
Test name
Test status
Simulation time 11569150903 ps
CPU time 19.45 seconds
Started Mar 12 12:30:39 PM PDT 24
Finished Mar 12 12:30:59 PM PDT 24
Peak memory 203528 kb
Host smart-73183cb6-4631-4070-9d4e-33a2378b0418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302731133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.2302731133
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.1420624505
Short name T196
Test name
Test status
Simulation time 2079721985 ps
CPU time 7.74 seconds
Started Mar 12 12:30:49 PM PDT 24
Finished Mar 12 12:30:57 PM PDT 24
Peak memory 203500 kb
Host smart-387f0427-9d7a-42f4-8e6e-f83a25e8e76e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420624505 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.1420624505
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.2208726000
Short name T221
Test name
Test status
Simulation time 10857097846 ps
CPU time 17.64 seconds
Started Mar 12 12:30:45 PM PDT 24
Finished Mar 12 12:31:02 PM PDT 24
Peak memory 203604 kb
Host smart-5841ac45-e868-41c8-aea9-e28c58993605
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2208726000 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t
l_access.2208726000
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.149756958
Short name T71
Test name
Test status
Simulation time 2128894247 ps
CPU time 5.39 seconds
Started Mar 12 12:31:02 PM PDT 24
Finished Mar 12 12:31:07 PM PDT 24
Peak memory 203504 kb
Host smart-5426a5bb-a8b4-4f9c-8961-e4bd343b80e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149756958 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.149756958
Directory /workspace/9.rv_dm_sba_tl_access/latest
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