Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
80.36 94.82 81.77 89.99 78.21 84.55 98.52 34.67


Total test records in report: 382
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html
T274 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1000355548 Mar 14 12:30:09 PM PDT 24 Mar 14 12:30:11 PM PDT 24 744692486 ps
T123 /workspace/coverage/cover_reg_top/25.rv_dm_tap_fsm_rand_reset.3382892899 Mar 14 12:30:26 PM PDT 24 Mar 14 12:31:03 PM PDT 24 11150157473 ps
T275 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.1654745669 Mar 14 12:30:36 PM PDT 24 Mar 14 12:30:38 PM PDT 24 56979268 ps
T276 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.2886253407 Mar 14 12:30:24 PM PDT 24 Mar 14 12:30:29 PM PDT 24 944018380 ps
T130 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2226762128 Mar 14 12:30:08 PM PDT 24 Mar 14 12:30:24 PM PDT 24 651641874 ps
T277 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.1409028224 Mar 14 12:29:58 PM PDT 24 Mar 14 12:30:00 PM PDT 24 53897243 ps
T278 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3760011932 Mar 14 12:30:35 PM PDT 24 Mar 14 12:30:35 PM PDT 24 72986485 ps
T279 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.1107571734 Mar 14 12:30:21 PM PDT 24 Mar 14 12:30:23 PM PDT 24 358093152 ps
T280 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2810906338 Mar 14 12:30:02 PM PDT 24 Mar 14 12:30:03 PM PDT 24 318815166 ps
T281 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.4272042757 Mar 14 12:30:24 PM PDT 24 Mar 14 12:30:28 PM PDT 24 132647448 ps
T282 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1523295217 Mar 14 12:30:24 PM PDT 24 Mar 14 12:30:28 PM PDT 24 117870076 ps
T97 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.1557896955 Mar 14 12:30:07 PM PDT 24 Mar 14 12:30:09 PM PDT 24 753888447 ps
T105 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.2617608247 Mar 14 12:30:22 PM PDT 24 Mar 14 12:30:29 PM PDT 24 296495692 ps
T126 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.1898668653 Mar 14 12:30:21 PM PDT 24 Mar 14 12:30:30 PM PDT 24 621741086 ps
T283 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3419094758 Mar 14 12:30:04 PM PDT 24 Mar 14 12:30:43 PM PDT 24 22638076041 ps
T43 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.1238897551 Mar 14 12:30:25 PM PDT 24 Mar 14 12:30:29 PM PDT 24 4902346959 ps
T131 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1078299175 Mar 14 12:30:38 PM PDT 24 Mar 14 12:30:55 PM PDT 24 590068514 ps
T284 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.3593238781 Mar 14 12:30:23 PM PDT 24 Mar 14 12:30:27 PM PDT 24 1079360683 ps
T285 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.849529467 Mar 14 12:30:14 PM PDT 24 Mar 14 12:30:18 PM PDT 24 304126012 ps
T108 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2453288893 Mar 14 12:30:25 PM PDT 24 Mar 14 12:30:27 PM PDT 24 60508198 ps
T286 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.3303661553 Mar 14 12:30:05 PM PDT 24 Mar 14 12:30:31 PM PDT 24 8932648944 ps
T287 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2429468712 Mar 14 12:30:14 PM PDT 24 Mar 14 12:30:16 PM PDT 24 77027412 ps
T288 /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.4000611129 Mar 14 12:29:50 PM PDT 24 Mar 14 12:30:03 PM PDT 24 3801253685 ps
T289 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1987919631 Mar 14 12:30:28 PM PDT 24 Mar 14 12:30:32 PM PDT 24 1887995486 ps
T290 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.3676621839 Mar 14 12:30:30 PM PDT 24 Mar 14 12:30:34 PM PDT 24 1508992374 ps
T291 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.208256034 Mar 14 12:30:26 PM PDT 24 Mar 14 12:30:30 PM PDT 24 819912086 ps
T109 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.1996146876 Mar 14 12:30:27 PM PDT 24 Mar 14 12:31:20 PM PDT 24 2806650550 ps
T292 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.323553400 Mar 14 12:30:21 PM PDT 24 Mar 14 12:30:27 PM PDT 24 253936043 ps
T293 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1646597533 Mar 14 12:30:08 PM PDT 24 Mar 14 12:30:09 PM PDT 24 195017267 ps
T110 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.2488839680 Mar 14 12:30:30 PM PDT 24 Mar 14 12:30:32 PM PDT 24 44964491 ps
T294 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.3300049265 Mar 14 12:30:10 PM PDT 24 Mar 14 12:30:11 PM PDT 24 108019595 ps
T295 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2195450011 Mar 14 12:30:02 PM PDT 24 Mar 14 12:30:18 PM PDT 24 12757950681 ps
T128 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.1215950185 Mar 14 12:30:31 PM PDT 24 Mar 14 12:30:40 PM PDT 24 536653015 ps
T135 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.1164129980 Mar 14 12:30:23 PM PDT 24 Mar 14 12:30:37 PM PDT 24 461297972 ps
T296 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.1841044857 Mar 14 12:30:07 PM PDT 24 Mar 14 12:30:17 PM PDT 24 549342629 ps
T297 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.785795967 Mar 14 12:30:24 PM PDT 24 Mar 14 12:30:25 PM PDT 24 169844210 ps
T298 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.3841491548 Mar 14 12:30:28 PM PDT 24 Mar 14 12:30:31 PM PDT 24 79663353 ps
T299 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.1464147018 Mar 14 12:30:24 PM PDT 24 Mar 14 12:30:26 PM PDT 24 78374058 ps
T300 /workspace/coverage/cover_reg_top/32.rv_dm_tap_fsm_rand_reset.2467347217 Mar 14 12:30:49 PM PDT 24 Mar 14 12:31:20 PM PDT 24 17964817873 ps
T132 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.1997229185 Mar 14 12:30:29 PM PDT 24 Mar 14 12:30:43 PM PDT 24 939928949 ps
T301 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.81609109 Mar 14 12:30:29 PM PDT 24 Mar 14 12:30:30 PM PDT 24 72649792 ps
T129 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2668272712 Mar 14 12:30:31 PM PDT 24 Mar 14 12:30:46 PM PDT 24 727416047 ps
T133 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2111378802 Mar 14 12:30:20 PM PDT 24 Mar 14 12:30:35 PM PDT 24 713070604 ps
T302 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.2901273041 Mar 14 12:30:24 PM PDT 24 Mar 14 12:30:25 PM PDT 24 55940376 ps
T303 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.147788497 Mar 14 12:30:22 PM PDT 24 Mar 14 12:30:24 PM PDT 24 297355478 ps
T304 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.918385743 Mar 14 12:30:21 PM PDT 24 Mar 14 12:30:23 PM PDT 24 388425991 ps
T305 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.2517265996 Mar 14 12:30:15 PM PDT 24 Mar 14 12:31:17 PM PDT 24 17366493036 ps
T306 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2742467320 Mar 14 12:30:12 PM PDT 24 Mar 14 12:30:13 PM PDT 24 22789780 ps
T307 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1242415937 Mar 14 12:30:28 PM PDT 24 Mar 14 12:30:30 PM PDT 24 59774776 ps
T308 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.3007103505 Mar 14 12:30:20 PM PDT 24 Mar 14 12:31:18 PM PDT 24 35048286973 ps
T309 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.780119129 Mar 14 12:30:37 PM PDT 24 Mar 14 12:30:39 PM PDT 24 54384196 ps
T106 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.456443774 Mar 14 12:30:28 PM PDT 24 Mar 14 12:30:35 PM PDT 24 238966918 ps
T310 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.1809890675 Mar 14 12:30:41 PM PDT 24 Mar 14 12:30:42 PM PDT 24 55226806 ps
T311 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3458302373 Mar 14 12:30:20 PM PDT 24 Mar 14 12:30:31 PM PDT 24 11781459845 ps
T312 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2025375757 Mar 14 12:30:23 PM PDT 24 Mar 14 12:30:24 PM PDT 24 295214216 ps
T313 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.1877299902 Mar 14 12:30:36 PM PDT 24 Mar 14 12:30:41 PM PDT 24 546189595 ps
T314 /workspace/coverage/cover_reg_top/21.rv_dm_tap_fsm_rand_reset.698715813 Mar 14 12:30:18 PM PDT 24 Mar 14 12:30:37 PM PDT 24 20426480337 ps
T315 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.2662966663 Mar 14 12:30:22 PM PDT 24 Mar 14 12:30:24 PM PDT 24 1328044550 ps
T316 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3314966366 Mar 14 12:30:37 PM PDT 24 Mar 14 12:30:40 PM PDT 24 165253421 ps
T317 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.4092452106 Mar 14 12:30:27 PM PDT 24 Mar 14 12:30:39 PM PDT 24 81993118 ps
T318 /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.616606782 Mar 14 12:30:25 PM PDT 24 Mar 14 12:30:44 PM PDT 24 9951649424 ps
T319 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.2432473610 Mar 14 12:30:48 PM PDT 24 Mar 14 12:30:56 PM PDT 24 7394002116 ps
T320 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1311242432 Mar 14 12:31:01 PM PDT 24 Mar 14 12:31:06 PM PDT 24 934148545 ps
T321 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.1511565486 Mar 14 12:30:27 PM PDT 24 Mar 14 12:30:32 PM PDT 24 1512340329 ps
T322 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.1194758331 Mar 14 12:30:06 PM PDT 24 Mar 14 12:30:07 PM PDT 24 72304316 ps
T323 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3655096046 Mar 14 12:30:26 PM PDT 24 Mar 14 12:30:27 PM PDT 24 78707774 ps
T324 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.3449384500 Mar 14 12:30:03 PM PDT 24 Mar 14 12:30:04 PM PDT 24 59531216 ps
T325 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3796844440 Mar 14 12:30:23 PM PDT 24 Mar 14 12:30:25 PM PDT 24 502923388 ps
T326 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.4059987422 Mar 14 12:30:08 PM PDT 24 Mar 14 12:30:43 PM PDT 24 8611343849 ps
T327 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.113757779 Mar 14 12:30:26 PM PDT 24 Mar 14 12:30:29 PM PDT 24 569536987 ps
T328 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2822677474 Mar 14 12:30:46 PM PDT 24 Mar 14 12:31:19 PM PDT 24 9322246078 ps
T329 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2570352281 Mar 14 12:30:11 PM PDT 24 Mar 14 12:30:13 PM PDT 24 180945552 ps
T330 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3917848127 Mar 14 12:30:07 PM PDT 24 Mar 14 12:30:15 PM PDT 24 700016278 ps
T331 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.2468381860 Mar 14 12:30:10 PM PDT 24 Mar 14 12:30:18 PM PDT 24 1131626240 ps
T332 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.519113379 Mar 14 12:30:10 PM PDT 24 Mar 14 12:30:11 PM PDT 24 77220488 ps
T333 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.3939066313 Mar 14 12:30:22 PM PDT 24 Mar 14 12:30:26 PM PDT 24 850330496 ps
T136 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3676717672 Mar 14 12:30:28 PM PDT 24 Mar 14 12:30:38 PM PDT 24 962787028 ps
T334 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1500820202 Mar 14 12:30:19 PM PDT 24 Mar 14 12:30:20 PM PDT 24 286949692 ps
T335 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.3960761344 Mar 14 12:30:23 PM PDT 24 Mar 14 12:30:24 PM PDT 24 317515944 ps
T336 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.72502806 Mar 14 12:30:24 PM PDT 24 Mar 14 12:30:25 PM PDT 24 89973239 ps
T337 /workspace/coverage/cover_reg_top/38.rv_dm_tap_fsm_rand_reset.1027213900 Mar 14 12:30:45 PM PDT 24 Mar 14 12:30:58 PM PDT 24 16231924681 ps
T338 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.4052427825 Mar 14 12:30:04 PM PDT 24 Mar 14 12:30:59 PM PDT 24 1436139193 ps
T339 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.4059464228 Mar 14 12:30:28 PM PDT 24 Mar 14 12:30:34 PM PDT 24 866432862 ps
T340 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3407722516 Mar 14 12:30:24 PM PDT 24 Mar 14 12:30:27 PM PDT 24 1058773218 ps
T134 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.379299014 Mar 14 12:30:29 PM PDT 24 Mar 14 12:30:49 PM PDT 24 5093669039 ps
T341 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.1409693394 Mar 14 12:30:16 PM PDT 24 Mar 14 12:30:20 PM PDT 24 74175817 ps
T342 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.1636092565 Mar 14 12:30:05 PM PDT 24 Mar 14 12:30:06 PM PDT 24 585157118 ps
T111 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.2878901113 Mar 14 12:30:22 PM PDT 24 Mar 14 12:31:32 PM PDT 24 7947503162 ps
T343 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.1643923753 Mar 14 12:30:29 PM PDT 24 Mar 14 12:30:30 PM PDT 24 33007323 ps
T113 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.165067449 Mar 14 12:30:22 PM PDT 24 Mar 14 12:30:24 PM PDT 24 55476234 ps
T98 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.244625030 Mar 14 12:30:06 PM PDT 24 Mar 14 12:30:08 PM PDT 24 247882637 ps
T344 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2835312518 Mar 14 12:30:28 PM PDT 24 Mar 14 12:30:32 PM PDT 24 1392573234 ps
T345 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.552802191 Mar 14 12:30:10 PM PDT 24 Mar 14 12:30:10 PM PDT 24 52218070 ps
T346 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.1880954882 Mar 14 12:30:27 PM PDT 24 Mar 14 12:30:31 PM PDT 24 201049263 ps
T347 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.3103096959 Mar 14 12:30:08 PM PDT 24 Mar 14 12:30:09 PM PDT 24 601169960 ps
T348 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.2357100457 Mar 14 12:30:09 PM PDT 24 Mar 14 12:31:20 PM PDT 24 20081879183 ps
T349 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3866361201 Mar 14 12:30:22 PM PDT 24 Mar 14 12:30:23 PM PDT 24 47177535 ps
T350 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.4073980096 Mar 14 12:30:24 PM PDT 24 Mar 14 12:30:28 PM PDT 24 266548096 ps
T351 /workspace/coverage/cover_reg_top/30.rv_dm_tap_fsm_rand_reset.2306029439 Mar 14 12:30:29 PM PDT 24 Mar 14 12:30:42 PM PDT 24 6595613084 ps
T352 /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.3337542778 Mar 14 12:30:17 PM PDT 24 Mar 14 12:30:29 PM PDT 24 15689762057 ps
T112 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.285965727 Mar 14 12:30:14 PM PDT 24 Mar 14 12:30:16 PM PDT 24 902595052 ps
T353 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.1601971570 Mar 14 12:30:10 PM PDT 24 Mar 14 12:30:14 PM PDT 24 383804982 ps
T354 /workspace/coverage/cover_reg_top/22.rv_dm_tap_fsm_rand_reset.3772724498 Mar 14 12:30:29 PM PDT 24 Mar 14 12:30:56 PM PDT 24 16117064215 ps
T355 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2842572617 Mar 14 12:30:24 PM PDT 24 Mar 14 12:30:28 PM PDT 24 4261975745 ps
T356 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.3414117430 Mar 14 12:30:19 PM PDT 24 Mar 14 12:30:21 PM PDT 24 191849105 ps
T357 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.1783403934 Mar 14 12:30:21 PM PDT 24 Mar 14 12:30:24 PM PDT 24 805178442 ps
T127 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2273728222 Mar 14 12:30:08 PM PDT 24 Mar 14 12:30:24 PM PDT 24 761375593 ps
T358 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2794439338 Mar 14 12:30:07 PM PDT 24 Mar 14 12:30:14 PM PDT 24 2219816455 ps
T359 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.2074150594 Mar 14 12:30:19 PM PDT 24 Mar 14 12:30:27 PM PDT 24 1159831845 ps
T360 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2408978382 Mar 14 12:30:29 PM PDT 24 Mar 14 12:30:38 PM PDT 24 4213741117 ps
T361 /workspace/coverage/cover_reg_top/29.rv_dm_tap_fsm_rand_reset.852120498 Mar 14 12:30:28 PM PDT 24 Mar 14 12:30:41 PM PDT 24 14126431022 ps
T362 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3751572391 Mar 14 12:29:54 PM PDT 24 Mar 14 12:29:55 PM PDT 24 26799381 ps
T363 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.146344691 Mar 14 12:30:22 PM PDT 24 Mar 14 12:30:28 PM PDT 24 1313411748 ps
T364 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.1443675984 Mar 14 12:30:12 PM PDT 24 Mar 14 12:30:45 PM PDT 24 1482289439 ps
T365 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1058560250 Mar 14 12:30:34 PM PDT 24 Mar 14 12:30:34 PM PDT 24 46524408 ps
T366 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.2994650121 Mar 14 12:30:22 PM PDT 24 Mar 14 12:30:23 PM PDT 24 41626889 ps
T367 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2326959594 Mar 14 12:30:21 PM PDT 24 Mar 14 12:30:28 PM PDT 24 130025572 ps
T368 /workspace/coverage/cover_reg_top/37.rv_dm_tap_fsm_rand_reset.2830404715 Mar 14 12:30:29 PM PDT 24 Mar 14 12:30:47 PM PDT 24 34723904383 ps
T369 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.2778277183 Mar 14 12:30:21 PM PDT 24 Mar 14 12:30:22 PM PDT 24 19777620 ps
T370 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2680208701 Mar 14 12:30:23 PM PDT 24 Mar 14 12:30:55 PM PDT 24 2328571788 ps
T371 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.2050421262 Mar 14 12:30:28 PM PDT 24 Mar 14 12:30:30 PM PDT 24 28367611 ps
T372 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.4145102644 Mar 14 12:30:31 PM PDT 24 Mar 14 12:30:34 PM PDT 24 164746944 ps
T373 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.3036200151 Mar 14 12:30:38 PM PDT 24 Mar 14 12:30:41 PM PDT 24 208072201 ps
T374 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1273387953 Mar 14 12:29:58 PM PDT 24 Mar 14 12:30:01 PM PDT 24 491040654 ps
T375 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3505343035 Mar 14 12:30:32 PM PDT 24 Mar 14 12:30:36 PM PDT 24 244866812 ps
T376 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2779149666 Mar 14 12:30:27 PM PDT 24 Mar 14 12:30:29 PM PDT 24 185686022 ps
T377 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.1445645500 Mar 14 12:30:09 PM PDT 24 Mar 14 12:30:10 PM PDT 24 23200995 ps
T378 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3428583363 Mar 14 12:30:28 PM PDT 24 Mar 14 12:30:36 PM PDT 24 776451870 ps
T379 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.3440904754 Mar 14 12:30:42 PM PDT 24 Mar 14 12:30:43 PM PDT 24 37529227 ps
T380 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.3555423905 Mar 14 12:30:31 PM PDT 24 Mar 14 12:30:40 PM PDT 24 419885252 ps
T381 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1374188012 Mar 14 12:30:22 PM PDT 24 Mar 14 12:30:55 PM PDT 24 1210826436 ps
T382 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.3086418118 Mar 14 12:30:27 PM PDT 24 Mar 14 12:30:29 PM PDT 24 45748036 ps

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.4030219231
Short name T13
Test name
Test status
Simulation time 6969370353 ps
CPU time 22.58 seconds
Started Mar 14 01:15:35 PM PDT 24
Finished Mar 14 01:15:58 PM PDT 24
Peak memory 212864 kb
Host smart-3d2f6f19-2a86-4620-814f-4e578ac54f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030219231 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.4030219231
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/38.rv_dm_stress_all.3532472551
Short name T15
Test name
Test status
Simulation time 1508983575 ps
CPU time 5.31 seconds
Started Mar 14 01:16:14 PM PDT 24
Finished Mar 14 01:16:20 PM PDT 24
Peak memory 204364 kb
Host smart-43d7e498-fdca-4164-bf0b-85f2dc5802e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532472551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.3532472551
Directory /workspace/38.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3513392681
Short name T48
Test name
Test status
Simulation time 2088872263 ps
CPU time 4.74 seconds
Started Mar 14 12:30:09 PM PDT 24
Finished Mar 14 12:30:14 PM PDT 24
Peak memory 217688 kb
Host smart-7c064a1b-c520-4103-900b-5bacd87767fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513392681 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.3513392681
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.3347586343
Short name T14
Test name
Test status
Simulation time 26355162339 ps
CPU time 95.23 seconds
Started Mar 14 01:16:00 PM PDT 24
Finished Mar 14 01:17:36 PM PDT 24
Peak memory 212888 kb
Host smart-67e23a19-5077-4aec-a5a3-c87d0c7a227e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347586343 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.3347586343
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.1946279184
Short name T26
Test name
Test status
Simulation time 65108869 ps
CPU time 0.73 seconds
Started Mar 14 01:16:39 PM PDT 24
Finished Mar 14 01:16:42 PM PDT 24
Peak memory 204276 kb
Host smart-423fd621-5e6e-4231-a3d7-86062cad53a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946279184 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.1946279184
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_stress_all.3784333812
Short name T41
Test name
Test status
Simulation time 4147519658 ps
CPU time 8.45 seconds
Started Mar 14 01:16:12 PM PDT 24
Finished Mar 14 01:16:21 PM PDT 24
Peak memory 212716 kb
Host smart-fcbaad01-ea53-4a93-b3db-5082f599ef53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784333812 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.3784333812
Directory /workspace/27.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/25.rv_dm_tap_fsm_rand_reset.3382892899
Short name T123
Test name
Test status
Simulation time 11150157473 ps
CPU time 35.88 seconds
Started Mar 14 12:30:26 PM PDT 24
Finished Mar 14 12:31:03 PM PDT 24
Peak memory 221408 kb
Host smart-28291973-3d5d-4117-8127-3ad01087a534
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382892899 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 25.rv_dm_tap_fsm_rand_reset.3382892899
Directory /workspace/25.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2730819505
Short name T119
Test name
Test status
Simulation time 360917214 ps
CPU time 8.22 seconds
Started Mar 14 12:30:25 PM PDT 24
Finished Mar 14 12:30:34 PM PDT 24
Peak memory 221312 kb
Host smart-76d93d61-9300-40f1-ada5-e5d6b8babcca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730819505 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.2
730819505
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3361321684
Short name T101
Test name
Test status
Simulation time 570921373 ps
CPU time 27.2 seconds
Started Mar 14 12:29:52 PM PDT 24
Finished Mar 14 12:30:19 PM PDT 24
Peak memory 214336 kb
Host smart-6be2473c-2972-44a0-b455-2dc1bfe2665b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361321684 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.3361321684
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/default/14.rv_dm_stress_all.1203885776
Short name T16
Test name
Test status
Simulation time 18339501629 ps
CPU time 6.52 seconds
Started Mar 14 01:15:50 PM PDT 24
Finished Mar 14 01:15:57 PM PDT 24
Peak memory 204300 kb
Host smart-299e5490-9324-4acf-b652-45250a335b3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203885776 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.1203885776
Directory /workspace/14.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.1037966924
Short name T37
Test name
Test status
Simulation time 1709094804 ps
CPU time 3.65 seconds
Started Mar 14 01:15:36 PM PDT 24
Finished Mar 14 01:15:40 PM PDT 24
Peak memory 204316 kb
Host smart-37aebdb5-d3e0-4c3f-bb0b-762726b56f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037966924 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.1037966924
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.4143805895
Short name T79
Test name
Test status
Simulation time 341082334 ps
CPU time 2.95 seconds
Started Mar 14 12:30:19 PM PDT 24
Finished Mar 14 12:30:22 PM PDT 24
Peak memory 213292 kb
Host smart-af01f213-3a9b-444e-b10a-2c4d36cdacda
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143805895 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.4143805895
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.3284121829
Short name T38
Test name
Test status
Simulation time 170622201 ps
CPU time 1.45 seconds
Started Mar 14 01:15:34 PM PDT 24
Finished Mar 14 01:15:36 PM PDT 24
Peak memory 228316 kb
Host smart-da097bbe-da39-443a-bde9-778238abbfba
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284121829 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.3284121829
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.1502261681
Short name T30
Test name
Test status
Simulation time 19741118 ps
CPU time 0.8 seconds
Started Mar 14 01:15:33 PM PDT 24
Finished Mar 14 01:15:34 PM PDT 24
Peak memory 212512 kb
Host smart-016f8ea4-a557-4aec-a121-6917613df2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502261681 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.1502261681
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.1114996560
Short name T34
Test name
Test status
Simulation time 395640295 ps
CPU time 1.35 seconds
Started Mar 14 01:15:34 PM PDT 24
Finished Mar 14 01:15:36 PM PDT 24
Peak memory 204232 kb
Host smart-6dd60989-8d6b-4e3f-9619-bd564b50f6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114996560 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.1114996560
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.958185623
Short name T92
Test name
Test status
Simulation time 318588669 ps
CPU time 4.53 seconds
Started Mar 14 12:30:03 PM PDT 24
Finished Mar 14 12:30:07 PM PDT 24
Peak memory 204988 kb
Host smart-388a13d3-8d2f-47ac-8eb3-03c75e7c6fbf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958185623 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_c
sr_outstanding.958185623
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2111378802
Short name T133
Test name
Test status
Simulation time 713070604 ps
CPU time 15.13 seconds
Started Mar 14 12:30:20 PM PDT 24
Finished Mar 14 12:30:35 PM PDT 24
Peak memory 213344 kb
Host smart-6dbd49e7-b911-4e8f-a5be-308d9d4a91df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111378802 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.2
111378802
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.2372687270
Short name T31
Test name
Test status
Simulation time 63803297 ps
CPU time 0.95 seconds
Started Mar 14 01:15:36 PM PDT 24
Finished Mar 14 01:15:37 PM PDT 24
Peak memory 204172 kb
Host smart-11f05527-080a-4feb-a9bb-1221698c02ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372687270 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.2372687270
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.37867565
Short name T36
Test name
Test status
Simulation time 30211829 ps
CPU time 0.77 seconds
Started Mar 14 01:15:42 PM PDT 24
Finished Mar 14 01:15:43 PM PDT 24
Peak memory 204176 kb
Host smart-cb51a08c-5ad6-4878-8762-d71a570c811a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37867565 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.37867565
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.1174481783
Short name T65
Test name
Test status
Simulation time 134344719 ps
CPU time 1.07 seconds
Started Mar 14 12:30:24 PM PDT 24
Finished Mar 14 12:30:25 PM PDT 24
Peak memory 204520 kb
Host smart-94d3d3a6-497e-41d6-92a5-6795f204f41e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174481783 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.1174481783
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/default/34.rv_dm_stress_all.2506732142
Short name T32
Test name
Test status
Simulation time 7874582828 ps
CPU time 8.08 seconds
Started Mar 14 01:16:19 PM PDT 24
Finished Mar 14 01:16:28 PM PDT 24
Peak memory 204468 kb
Host smart-8df9ace2-5999-4abd-b792-213d42dea8c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506732142 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.2506732142
Directory /workspace/34.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.526590690
Short name T67
Test name
Test status
Simulation time 752874282 ps
CPU time 7.89 seconds
Started Mar 14 12:30:21 PM PDT 24
Finished Mar 14 12:30:29 PM PDT 24
Peak memory 213252 kb
Host smart-2327fd57-4f3a-4839-a728-63721322d1b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526590690 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.526590690
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.244625030
Short name T98
Test name
Test status
Simulation time 247882637 ps
CPU time 1.06 seconds
Started Mar 14 12:30:06 PM PDT 24
Finished Mar 14 12:30:08 PM PDT 24
Peak memory 205008 kb
Host smart-1ef20d09-ef13-4b8e-bb9a-f11c583741c7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244625030 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr
_hw_reset.244625030
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.2219906008
Short name T27
Test name
Test status
Simulation time 697760752 ps
CPU time 1.18 seconds
Started Mar 14 01:15:39 PM PDT 24
Finished Mar 14 01:15:40 PM PDT 24
Peak memory 204116 kb
Host smart-42493a63-087c-471f-a426-0ddd5c54722b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219906008 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.2219906008
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2801989705
Short name T102
Test name
Test status
Simulation time 268218808 ps
CPU time 2.27 seconds
Started Mar 14 12:30:12 PM PDT 24
Finished Mar 14 12:30:14 PM PDT 24
Peak memory 213180 kb
Host smart-1e423ce6-7176-4573-9d1e-52c41788e1fd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801989705 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.2801989705
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.1164129980
Short name T135
Test name
Test status
Simulation time 461297972 ps
CPU time 8.02 seconds
Started Mar 14 12:30:23 PM PDT 24
Finished Mar 14 12:30:37 PM PDT 24
Peak memory 213244 kb
Host smart-cd8235ab-accf-436e-b0f7-86acf7fdcc2c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164129980 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.1164129980
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.1898668653
Short name T126
Test name
Test status
Simulation time 621741086 ps
CPU time 8.08 seconds
Started Mar 14 12:30:21 PM PDT 24
Finished Mar 14 12:30:30 PM PDT 24
Peak memory 213204 kb
Host smart-5830c898-a96f-4669-8135-16f3929b2611
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898668653 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.1
898668653
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.3775838830
Short name T146
Test name
Test status
Simulation time 47901702 ps
CPU time 0.73 seconds
Started Mar 14 01:16:02 PM PDT 24
Finished Mar 14 01:16:04 PM PDT 24
Peak memory 204256 kb
Host smart-fbbf48c4-93a2-49f3-ae07-1e9a1b0414b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775838830 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.3775838830
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3867422797
Short name T49
Test name
Test status
Simulation time 3281126515 ps
CPU time 7.54 seconds
Started Mar 14 12:30:13 PM PDT 24
Finished Mar 14 12:30:21 PM PDT 24
Peak memory 218840 kb
Host smart-b2e189fd-57c5-4ae1-b964-4033234fd968
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867422797 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.3867422797
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3583747346
Short name T90
Test name
Test status
Simulation time 16908678461 ps
CPU time 73.83 seconds
Started Mar 14 12:30:10 PM PDT 24
Finished Mar 14 12:31:24 PM PDT 24
Peak memory 213304 kb
Host smart-739a2668-5bb5-4825-93eb-3dbd9642d66a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583747346 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.3583747346
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.4052427825
Short name T338
Test name
Test status
Simulation time 1436139193 ps
CPU time 54.49 seconds
Started Mar 14 12:30:04 PM PDT 24
Finished Mar 14 12:30:59 PM PDT 24
Peak memory 204936 kb
Host smart-9d89c1de-44f1-4f98-8747-3b565a3f63c7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052427825 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.4052427825
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.1409028224
Short name T277
Test name
Test status
Simulation time 53897243 ps
CPU time 1.56 seconds
Started Mar 14 12:29:58 PM PDT 24
Finished Mar 14 12:30:00 PM PDT 24
Peak memory 213212 kb
Host smart-73360887-dce8-432e-9ad3-8bdad6bbc394
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409028224 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.1409028224
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.968219991
Short name T263
Test name
Test status
Simulation time 51058696 ps
CPU time 1.45 seconds
Started Mar 14 12:30:13 PM PDT 24
Finished Mar 14 12:30:14 PM PDT 24
Peak memory 217628 kb
Host smart-2bd96196-39b8-4698-b301-d8e04ef15e5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968219991 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.968219991
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3419094758
Short name T283
Test name
Test status
Simulation time 22638076041 ps
CPU time 38.87 seconds
Started Mar 14 12:30:04 PM PDT 24
Finished Mar 14 12:30:43 PM PDT 24
Peak memory 204912 kb
Host smart-8b025ca7-09e9-4538-9970-b47aeccdf3ba
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419094758 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.3419094758
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.3007103505
Short name T308
Test name
Test status
Simulation time 35048286973 ps
CPU time 57.61 seconds
Started Mar 14 12:30:20 PM PDT 24
Finished Mar 14 12:31:18 PM PDT 24
Peak memory 204804 kb
Host smart-72f97be7-4738-4e6e-9134-947805da4d3d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007103505 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_bit_bash.3007103505
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3318712997
Short name T241
Test name
Test status
Simulation time 1298125155 ps
CPU time 2.94 seconds
Started Mar 14 12:30:00 PM PDT 24
Finished Mar 14 12:30:03 PM PDT 24
Peak memory 204732 kb
Host smart-2b5c35a4-a726-42f3-a970-0b30b3627f63
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318712997 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.3
318712997
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1273387953
Short name T374
Test name
Test status
Simulation time 491040654 ps
CPU time 2.69 seconds
Started Mar 14 12:29:58 PM PDT 24
Finished Mar 14 12:30:01 PM PDT 24
Peak memory 204756 kb
Host smart-125c4af4-cb78-4e3e-9951-4975b6822656
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273387953 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.1273387953
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2326959594
Short name T367
Test name
Test status
Simulation time 130025572 ps
CPU time 0.84 seconds
Started Mar 14 12:30:21 PM PDT 24
Finished Mar 14 12:30:28 PM PDT 24
Peak memory 204580 kb
Host smart-94223633-cdf5-4484-810f-d71e398a3c68
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326959594 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.2326959594
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.2994650121
Short name T366
Test name
Test status
Simulation time 41626889 ps
CPU time 0.74 seconds
Started Mar 14 12:30:22 PM PDT 24
Finished Mar 14 12:30:23 PM PDT 24
Peak memory 204696 kb
Host smart-f99c637d-fa85-45e6-80d1-3c50bf8c5af7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994650121 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.2
994650121
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.2702823851
Short name T261
Test name
Test status
Simulation time 50129103 ps
CPU time 0.75 seconds
Started Mar 14 12:30:09 PM PDT 24
Finished Mar 14 12:30:09 PM PDT 24
Peak memory 204576 kb
Host smart-fef3c016-2090-40d8-9962-090fc7024ccd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702823851 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.2702823851
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.2502480303
Short name T264
Test name
Test status
Simulation time 27205269 ps
CPU time 0.66 seconds
Started Mar 14 12:30:17 PM PDT 24
Finished Mar 14 12:30:18 PM PDT 24
Peak memory 204968 kb
Host smart-d57af019-f96c-4a1a-bae5-1960e1706d1d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502480303 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.2502480303
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.4000611129
Short name T288
Test name
Test status
Simulation time 3801253685 ps
CPU time 13.22 seconds
Started Mar 14 12:29:50 PM PDT 24
Finished Mar 14 12:30:03 PM PDT 24
Peak memory 221084 kb
Host smart-5c184cf2-e309-4b0f-bd91-6bc5a7341882
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000611129 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.4000611129
Directory /workspace/0.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.1107571734
Short name T279
Test name
Test status
Simulation time 358093152 ps
CPU time 1.75 seconds
Started Mar 14 12:30:21 PM PDT 24
Finished Mar 14 12:30:23 PM PDT 24
Peak memory 213104 kb
Host smart-3616a36c-b2f6-4a19-b101-107ca3dcc990
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107571734 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.1107571734
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3917848127
Short name T330
Test name
Test status
Simulation time 700016278 ps
CPU time 7.63 seconds
Started Mar 14 12:30:07 PM PDT 24
Finished Mar 14 12:30:15 PM PDT 24
Peak memory 213252 kb
Host smart-14bce35f-374b-4148-80cc-95ab821d0a3e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917848127 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.3917848127
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.1443675984
Short name T364
Test name
Test status
Simulation time 1482289439 ps
CPU time 28.44 seconds
Started Mar 14 12:30:12 PM PDT 24
Finished Mar 14 12:30:45 PM PDT 24
Peak memory 205032 kb
Host smart-3a5721bb-d36b-4ad0-b7ab-8235f9c3d307
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443675984 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.1443675984
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.859086841
Short name T273
Test name
Test status
Simulation time 150080709 ps
CPU time 1.96 seconds
Started Mar 14 12:30:22 PM PDT 24
Finished Mar 14 12:30:24 PM PDT 24
Peak memory 216508 kb
Host smart-ba741cd1-c3bd-4c57-beaa-bf340360dc04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859086841 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.859086841
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.1464147018
Short name T299
Test name
Test status
Simulation time 78374058 ps
CPU time 2.04 seconds
Started Mar 14 12:30:24 PM PDT 24
Finished Mar 14 12:30:26 PM PDT 24
Peak memory 221352 kb
Host smart-ca797748-d25f-46df-bd4a-b7e2b998a0f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464147018 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.1464147018
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.4059987422
Short name T326
Test name
Test status
Simulation time 8611343849 ps
CPU time 34.47 seconds
Started Mar 14 12:30:08 PM PDT 24
Finished Mar 14 12:30:43 PM PDT 24
Peak memory 204908 kb
Host smart-827a97b8-02c6-4a49-b15c-0c896d24f9c1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059987422 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.4059987422
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.3593238781
Short name T284
Test name
Test status
Simulation time 1079360683 ps
CPU time 4.05 seconds
Started Mar 14 12:30:23 PM PDT 24
Finished Mar 14 12:30:27 PM PDT 24
Peak memory 204864 kb
Host smart-c955d0e4-5535-4e83-a9e2-34abb38da646
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593238781 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.3
593238781
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2810906338
Short name T280
Test name
Test status
Simulation time 318815166 ps
CPU time 0.98 seconds
Started Mar 14 12:30:02 PM PDT 24
Finished Mar 14 12:30:03 PM PDT 24
Peak memory 204584 kb
Host smart-7e69b9f1-dbc5-41cd-a5b2-5e202e1449a8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810906338 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.2810906338
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.3103096959
Short name T347
Test name
Test status
Simulation time 601169960 ps
CPU time 1.48 seconds
Started Mar 14 12:30:08 PM PDT 24
Finished Mar 14 12:30:09 PM PDT 24
Peak memory 204748 kb
Host smart-4e6bc595-1050-4114-a136-d5aa7edd5e21
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103096959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.3103096959
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.3827107629
Short name T249
Test name
Test status
Simulation time 79587828 ps
CPU time 0.82 seconds
Started Mar 14 12:29:51 PM PDT 24
Finished Mar 14 12:29:52 PM PDT 24
Peak memory 204640 kb
Host smart-2fb8cd90-993f-4790-94d7-f5dbabedc1b0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827107629 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.3827107629
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3751572391
Short name T362
Test name
Test status
Simulation time 26799381 ps
CPU time 0.72 seconds
Started Mar 14 12:29:54 PM PDT 24
Finished Mar 14 12:29:55 PM PDT 24
Peak memory 204696 kb
Host smart-3cbb52b2-f765-40bc-8fb7-3c617a0a34f8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751572391 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.3
751572391
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2742467320
Short name T306
Test name
Test status
Simulation time 22789780 ps
CPU time 0.63 seconds
Started Mar 14 12:30:12 PM PDT 24
Finished Mar 14 12:30:13 PM PDT 24
Peak memory 204628 kb
Host smart-02484bd9-3b89-4f53-ab67-fe40c9f4424a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742467320 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.2742467320
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.2778277183
Short name T369
Test name
Test status
Simulation time 19777620 ps
CPU time 0.66 seconds
Started Mar 14 12:30:21 PM PDT 24
Finished Mar 14 12:30:22 PM PDT 24
Peak memory 204564 kb
Host smart-aa96393b-2f70-4b73-9789-95f70f2420d9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778277183 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.2778277183
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3428583363
Short name T378
Test name
Test status
Simulation time 776451870 ps
CPU time 6.84 seconds
Started Mar 14 12:30:28 PM PDT 24
Finished Mar 14 12:30:36 PM PDT 24
Peak memory 204944 kb
Host smart-6594d206-f3e6-4fae-8a8d-9bda42180bdf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428583363 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_
csr_outstanding.3428583363
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.616606782
Short name T318
Test name
Test status
Simulation time 9951649424 ps
CPU time 19.2 seconds
Started Mar 14 12:30:25 PM PDT 24
Finished Mar 14 12:30:44 PM PDT 24
Peak memory 215544 kb
Host smart-90d5fd86-a854-4b9c-861a-7bc4e214a7b7
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616606782 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.616606782
Directory /workspace/1.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.323553400
Short name T292
Test name
Test status
Simulation time 253936043 ps
CPU time 5.26 seconds
Started Mar 14 12:30:21 PM PDT 24
Finished Mar 14 12:30:27 PM PDT 24
Peak memory 213220 kb
Host smart-ed28f9fa-b7e5-4ef2-a5b1-c17d7f11066a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323553400 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.323553400
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.3278459573
Short name T86
Test name
Test status
Simulation time 90557929 ps
CPU time 2.32 seconds
Started Mar 14 12:30:38 PM PDT 24
Finished Mar 14 12:30:41 PM PDT 24
Peak memory 213176 kb
Host smart-232fb230-ab89-4e39-a99b-8c701ef24edd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278459573 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.3278459573
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2835312518
Short name T344
Test name
Test status
Simulation time 1392573234 ps
CPU time 3 seconds
Started Mar 14 12:30:28 PM PDT 24
Finished Mar 14 12:30:32 PM PDT 24
Peak memory 204728 kb
Host smart-a6e09e30-52ab-40a1-a263-c48105117b5b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835312518 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
2835312518
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.3739815241
Short name T45
Test name
Test status
Simulation time 101082532 ps
CPU time 0.69 seconds
Started Mar 14 12:30:26 PM PDT 24
Finished Mar 14 12:30:27 PM PDT 24
Peak memory 204564 kb
Host smart-c55c9fae-b67a-4bce-be6a-9c92e5f09c2b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739815241 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
3739815241
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.2617608247
Short name T105
Test name
Test status
Simulation time 296495692 ps
CPU time 6.47 seconds
Started Mar 14 12:30:22 PM PDT 24
Finished Mar 14 12:30:29 PM PDT 24
Peak memory 204936 kb
Host smart-89069a1a-3bd6-404c-a7bc-2dac8bf3ef78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617608247 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.2617608247
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.4059464228
Short name T339
Test name
Test status
Simulation time 866432862 ps
CPU time 5.64 seconds
Started Mar 14 12:30:28 PM PDT 24
Finished Mar 14 12:30:34 PM PDT 24
Peak memory 213256 kb
Host smart-fc74ebee-b97a-482e-aecc-fbdee89ba2e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059464228 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.4059464228
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.2432473610
Short name T319
Test name
Test status
Simulation time 7394002116 ps
CPU time 7.65 seconds
Started Mar 14 12:30:48 PM PDT 24
Finished Mar 14 12:30:56 PM PDT 24
Peak memory 218504 kb
Host smart-f14d3641-c5c1-4d76-9948-2f9cbdc774c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432473610 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.2432473610
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.3440904754
Short name T379
Test name
Test status
Simulation time 37529227 ps
CPU time 1.47 seconds
Started Mar 14 12:30:42 PM PDT 24
Finished Mar 14 12:30:43 PM PDT 24
Peak memory 218248 kb
Host smart-0d39a7ba-33af-41b5-928e-32952ebb6b6a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440904754 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.3440904754
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.113757779
Short name T327
Test name
Test status
Simulation time 569536987 ps
CPU time 2.32 seconds
Started Mar 14 12:30:26 PM PDT 24
Finished Mar 14 12:30:29 PM PDT 24
Peak memory 204788 kb
Host smart-36fee7b5-1664-4853-a799-d095ea1a8fbf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113757779 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.113757779
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3655096046
Short name T323
Test name
Test status
Simulation time 78707774 ps
CPU time 0.88 seconds
Started Mar 14 12:30:26 PM PDT 24
Finished Mar 14 12:30:27 PM PDT 24
Peak memory 204584 kb
Host smart-5fd690c8-c78c-4d7b-9711-c970c2a13e34
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655096046 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.
3655096046
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.1877299902
Short name T313
Test name
Test status
Simulation time 546189595 ps
CPU time 4.2 seconds
Started Mar 14 12:30:36 PM PDT 24
Finished Mar 14 12:30:41 PM PDT 24
Peak memory 205008 kb
Host smart-b70a9e7c-255e-4ad8-94e5-2bb46b9ff095
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877299902 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same
_csr_outstanding.1877299902
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1640570118
Short name T75
Test name
Test status
Simulation time 146184023 ps
CPU time 2.09 seconds
Started Mar 14 12:30:30 PM PDT 24
Finished Mar 14 12:30:32 PM PDT 24
Peak memory 213272 kb
Host smart-d620de19-9345-4282-bd02-f805c6eb98b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640570118 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.1640570118
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3676717672
Short name T136
Test name
Test status
Simulation time 962787028 ps
CPU time 9.05 seconds
Started Mar 14 12:30:28 PM PDT 24
Finished Mar 14 12:30:38 PM PDT 24
Peak memory 221324 kb
Host smart-72bc62b7-a45e-4068-be10-aa4bfa4d90bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676717672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.3
676717672
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1311242432
Short name T320
Test name
Test status
Simulation time 934148545 ps
CPU time 4.98 seconds
Started Mar 14 12:31:01 PM PDT 24
Finished Mar 14 12:31:06 PM PDT 24
Peak memory 218432 kb
Host smart-82724d3f-f315-4dc4-b468-c12af46b7273
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311242432 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.1311242432
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.808793286
Short name T107
Test name
Test status
Simulation time 112679220 ps
CPU time 1.46 seconds
Started Mar 14 12:30:57 PM PDT 24
Finished Mar 14 12:31:04 PM PDT 24
Peak memory 213112 kb
Host smart-6b5957f1-b40f-4bcf-803f-7bfa63de51be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808793286 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.808793286
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1709156838
Short name T242
Test name
Test status
Simulation time 1511794670 ps
CPU time 3.18 seconds
Started Mar 14 12:30:37 PM PDT 24
Finished Mar 14 12:30:40 PM PDT 24
Peak memory 204760 kb
Host smart-bc54abc4-166d-40ce-9852-9fddd526f13a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709156838 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
1709156838
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.263388646
Short name T262
Test name
Test status
Simulation time 63104547 ps
CPU time 0.7 seconds
Started Mar 14 12:30:33 PM PDT 24
Finished Mar 14 12:30:34 PM PDT 24
Peak memory 204616 kb
Host smart-494a83c2-1460-4b34-aee7-c4cd5107c1dd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263388646 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.263388646
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.2453669250
Short name T114
Test name
Test status
Simulation time 879266722 ps
CPU time 3.39 seconds
Started Mar 14 12:30:26 PM PDT 24
Finished Mar 14 12:30:30 PM PDT 24
Peak memory 205052 kb
Host smart-d3de21ef-63a6-49fc-8596-0c0496a472d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453669250 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.2453669250
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.3036200151
Short name T373
Test name
Test status
Simulation time 208072201 ps
CPU time 2.52 seconds
Started Mar 14 12:30:38 PM PDT 24
Finished Mar 14 12:30:41 PM PDT 24
Peak memory 213256 kb
Host smart-31142481-0cf4-4085-a006-520d96fd8946
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036200151 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.3036200151
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.1238897551
Short name T43
Test name
Test status
Simulation time 4902346959 ps
CPU time 3.88 seconds
Started Mar 14 12:30:25 PM PDT 24
Finished Mar 14 12:30:29 PM PDT 24
Peak memory 217912 kb
Host smart-c95428a7-c645-4389-96f7-261b6064a682
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238897551 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.1238897551
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.2080433511
Short name T84
Test name
Test status
Simulation time 338707303 ps
CPU time 2.08 seconds
Started Mar 14 12:30:37 PM PDT 24
Finished Mar 14 12:30:39 PM PDT 24
Peak memory 221296 kb
Host smart-f3bddffe-e86f-4bee-8456-1d3bccd78d0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080433511 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.2080433511
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.2977373483
Short name T259
Test name
Test status
Simulation time 640296674 ps
CPU time 1.88 seconds
Started Mar 14 12:30:25 PM PDT 24
Finished Mar 14 12:30:28 PM PDT 24
Peak memory 204792 kb
Host smart-11911669-72e8-45e8-9846-d5c8190bd9c3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977373483 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
2977373483
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1242415937
Short name T307
Test name
Test status
Simulation time 59774776 ps
CPU time 0.68 seconds
Started Mar 14 12:30:28 PM PDT 24
Finished Mar 14 12:30:30 PM PDT 24
Peak memory 204544 kb
Host smart-6ee5d919-aa77-4d51-8a79-13ba5664b752
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242415937 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
1242415937
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.3418911958
Short name T99
Test name
Test status
Simulation time 530741861 ps
CPU time 4.05 seconds
Started Mar 14 12:30:37 PM PDT 24
Finished Mar 14 12:30:41 PM PDT 24
Peak memory 204952 kb
Host smart-5bff11b4-119b-4b23-8e8d-c2c0f998b233
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418911958 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.3418911958
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.1409693394
Short name T341
Test name
Test status
Simulation time 74175817 ps
CPU time 3.54 seconds
Started Mar 14 12:30:16 PM PDT 24
Finished Mar 14 12:30:20 PM PDT 24
Peak memory 213240 kb
Host smart-f0ab3fb2-6d79-49b9-88f6-bd7382605be6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409693394 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.1409693394
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.562017076
Short name T47
Test name
Test status
Simulation time 40374988 ps
CPU time 2.35 seconds
Started Mar 14 12:30:29 PM PDT 24
Finished Mar 14 12:30:31 PM PDT 24
Peak memory 218172 kb
Host smart-764464db-d427-40bb-ab00-ae1f0867e32f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562017076 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.562017076
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.4145102644
Short name T372
Test name
Test status
Simulation time 164746944 ps
CPU time 2.27 seconds
Started Mar 14 12:30:31 PM PDT 24
Finished Mar 14 12:30:34 PM PDT 24
Peak memory 213168 kb
Host smart-93809c6c-cdbb-4417-995d-676b3db5f037
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145102644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.4145102644
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1363704858
Short name T267
Test name
Test status
Simulation time 329584313 ps
CPU time 1.72 seconds
Started Mar 14 12:30:21 PM PDT 24
Finished Mar 14 12:30:23 PM PDT 24
Peak memory 204720 kb
Host smart-5529b077-1931-4cfe-99f5-ef193e71033d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363704858 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
1363704858
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.1643923753
Short name T343
Test name
Test status
Simulation time 33007323 ps
CPU time 0.72 seconds
Started Mar 14 12:30:29 PM PDT 24
Finished Mar 14 12:30:30 PM PDT 24
Peak memory 204624 kb
Host smart-12cf8710-f4b6-4fbb-be3a-a0d58fb8b82c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643923753 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
1643923753
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3505343035
Short name T375
Test name
Test status
Simulation time 244866812 ps
CPU time 4.03 seconds
Started Mar 14 12:30:32 PM PDT 24
Finished Mar 14 12:30:36 PM PDT 24
Peak memory 205000 kb
Host smart-b04de20c-cf92-4a47-9b28-cc5d443ab504
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505343035 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.3505343035
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.2439893290
Short name T254
Test name
Test status
Simulation time 157286680 ps
CPU time 2.43 seconds
Started Mar 14 12:30:26 PM PDT 24
Finished Mar 14 12:30:29 PM PDT 24
Peak memory 213628 kb
Host smart-f0980156-87cd-4f4f-bd48-ef63c962aed0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439893290 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.2439893290
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1078299175
Short name T131
Test name
Test status
Simulation time 590068514 ps
CPU time 15.48 seconds
Started Mar 14 12:30:38 PM PDT 24
Finished Mar 14 12:30:55 PM PDT 24
Peak memory 213200 kb
Host smart-9077f80c-7c0e-4367-a0b0-0aa61a0a5a72
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078299175 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.1
078299175
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1987919631
Short name T289
Test name
Test status
Simulation time 1887995486 ps
CPU time 3.69 seconds
Started Mar 14 12:30:28 PM PDT 24
Finished Mar 14 12:30:32 PM PDT 24
Peak memory 218276 kb
Host smart-028cf39d-7833-4ecb-afcc-f231f540005b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987919631 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.1987919631
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.780119129
Short name T309
Test name
Test status
Simulation time 54384196 ps
CPU time 1.52 seconds
Started Mar 14 12:30:37 PM PDT 24
Finished Mar 14 12:30:39 PM PDT 24
Peak memory 213084 kb
Host smart-f04edcf5-2537-4f98-acf7-75ac554b6955
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780119129 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.780119129
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1593848721
Short name T246
Test name
Test status
Simulation time 190848448 ps
CPU time 1 seconds
Started Mar 14 12:30:28 PM PDT 24
Finished Mar 14 12:30:30 PM PDT 24
Peak memory 204716 kb
Host smart-7a658d48-d1d2-4f09-9654-6b41a5da6c6e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593848721 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
1593848721
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.81609109
Short name T301
Test name
Test status
Simulation time 72649792 ps
CPU time 0.68 seconds
Started Mar 14 12:30:29 PM PDT 24
Finished Mar 14 12:30:30 PM PDT 24
Peak memory 204560 kb
Host smart-7fe49f44-2530-4164-86d9-5602a2ff7149
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81609109 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.81609109
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.2468381860
Short name T331
Test name
Test status
Simulation time 1131626240 ps
CPU time 7.4 seconds
Started Mar 14 12:30:10 PM PDT 24
Finished Mar 14 12:30:18 PM PDT 24
Peak memory 204936 kb
Host smart-2a8185d8-d51c-403f-bf56-416e737aa6ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468381860 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.2468381860
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.4272042757
Short name T281
Test name
Test status
Simulation time 132647448 ps
CPU time 4.21 seconds
Started Mar 14 12:30:24 PM PDT 24
Finished Mar 14 12:30:28 PM PDT 24
Peak memory 213208 kb
Host smart-8ef39cde-140a-4576-a4a5-e58e831e4f5f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272042757 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.4272042757
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2668272712
Short name T129
Test name
Test status
Simulation time 727416047 ps
CPU time 14.2 seconds
Started Mar 14 12:30:31 PM PDT 24
Finished Mar 14 12:30:46 PM PDT 24
Peak memory 213128 kb
Host smart-94294e13-82b6-4126-848f-139a8e84dcd0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668272712 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.2
668272712
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.3676621839
Short name T290
Test name
Test status
Simulation time 1508992374 ps
CPU time 3.48 seconds
Started Mar 14 12:30:30 PM PDT 24
Finished Mar 14 12:30:34 PM PDT 24
Peak memory 217064 kb
Host smart-14905dc0-778a-42b3-883e-8caf694cc5a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676621839 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.3676621839
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.93121780
Short name T89
Test name
Test status
Simulation time 95468080 ps
CPU time 1.47 seconds
Started Mar 14 12:30:34 PM PDT 24
Finished Mar 14 12:30:36 PM PDT 24
Peak memory 213156 kb
Host smart-346a9c2d-d7fb-43f6-9e9f-6eaa42d27bf6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93121780 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.93121780
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.4107491201
Short name T247
Test name
Test status
Simulation time 507338615 ps
CPU time 1.68 seconds
Started Mar 14 12:30:23 PM PDT 24
Finished Mar 14 12:30:25 PM PDT 24
Peak memory 204848 kb
Host smart-e2f8e391-ecba-469c-bc4f-5fcdf750d07c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107491201 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
4107491201
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2011232957
Short name T252
Test name
Test status
Simulation time 38046205 ps
CPU time 0.69 seconds
Started Mar 14 12:30:26 PM PDT 24
Finished Mar 14 12:30:28 PM PDT 24
Peak memory 204596 kb
Host smart-2da914cb-16cc-4a0a-9a1e-311725ef4dfb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011232957 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
2011232957
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.2037492186
Short name T51
Test name
Test status
Simulation time 402487681 ps
CPU time 3.83 seconds
Started Mar 14 12:30:25 PM PDT 24
Finished Mar 14 12:30:29 PM PDT 24
Peak memory 204980 kb
Host smart-069fe44d-ff07-4c46-adc4-a5d886b7a152
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037492186 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.2037492186
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tap_fsm_rand_reset.1478766670
Short name T137
Test name
Test status
Simulation time 5685669302 ps
CPU time 19.87 seconds
Started Mar 14 12:30:42 PM PDT 24
Finished Mar 14 12:31:02 PM PDT 24
Peak memory 219612 kb
Host smart-458b978b-b567-4309-801d-506765e5b9ee
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478766670 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rv_dm_tap_fsm_rand_reset.1478766670
Directory /workspace/16.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.4205801982
Short name T68
Test name
Test status
Simulation time 299445861 ps
CPU time 3.81 seconds
Started Mar 14 12:30:35 PM PDT 24
Finished Mar 14 12:30:39 PM PDT 24
Peak memory 213148 kb
Host smart-de96eeb4-7c6a-4950-b4b7-6f26775a88e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205801982 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.4205801982
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.379299014
Short name T134
Test name
Test status
Simulation time 5093669039 ps
CPU time 18.81 seconds
Started Mar 14 12:30:29 PM PDT 24
Finished Mar 14 12:30:49 PM PDT 24
Peak memory 213292 kb
Host smart-191e4d8a-75e3-42a1-9fc4-40b736d424f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379299014 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.379299014
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2069638280
Short name T76
Test name
Test status
Simulation time 3981454867 ps
CPU time 5.1 seconds
Started Mar 14 12:30:27 PM PDT 24
Finished Mar 14 12:30:33 PM PDT 24
Peak memory 219896 kb
Host smart-015e0777-1c05-458d-87e7-ee7e17c65f55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069638280 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.2069638280
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.2488839680
Short name T110
Test name
Test status
Simulation time 44964491 ps
CPU time 2.04 seconds
Started Mar 14 12:30:30 PM PDT 24
Finished Mar 14 12:30:32 PM PDT 24
Peak memory 218988 kb
Host smart-bd7a624d-815a-4d30-90c7-bdb00f8ea500
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488839680 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.2488839680
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.1511565486
Short name T321
Test name
Test status
Simulation time 1512340329 ps
CPU time 3.09 seconds
Started Mar 14 12:30:27 PM PDT 24
Finished Mar 14 12:30:32 PM PDT 24
Peak memory 204728 kb
Host smart-ff5b75b5-8990-41eb-bdf4-8279ac959cf6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511565486 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
1511565486
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.1343884087
Short name T271
Test name
Test status
Simulation time 79801558 ps
CPU time 0.66 seconds
Started Mar 14 12:30:27 PM PDT 24
Finished Mar 14 12:30:28 PM PDT 24
Peak memory 204620 kb
Host smart-e783ca54-6010-4e3d-a8c7-045f0950a24a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343884087 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
1343884087
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.1443676379
Short name T103
Test name
Test status
Simulation time 90449023 ps
CPU time 3.35 seconds
Started Mar 14 12:30:27 PM PDT 24
Finished Mar 14 12:30:32 PM PDT 24
Peak memory 205032 kb
Host smart-7a17b826-a2e1-43fa-880f-dae7c5151f28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443676379 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.1443676379
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.208256034
Short name T291
Test name
Test status
Simulation time 819912086 ps
CPU time 3.55 seconds
Started Mar 14 12:30:26 PM PDT 24
Finished Mar 14 12:30:30 PM PDT 24
Peak memory 213264 kb
Host smart-8d862cae-d09f-4cbc-b736-857ed97e0881
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208256034 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.208256034
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.1997229185
Short name T132
Test name
Test status
Simulation time 939928949 ps
CPU time 13.88 seconds
Started Mar 14 12:30:29 PM PDT 24
Finished Mar 14 12:30:43 PM PDT 24
Peak memory 212924 kb
Host smart-f466f0b5-d2af-4441-afb8-1751cece36f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997229185 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.1
997229185
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2408978382
Short name T360
Test name
Test status
Simulation time 4213741117 ps
CPU time 8.63 seconds
Started Mar 14 12:30:29 PM PDT 24
Finished Mar 14 12:30:38 PM PDT 24
Peak memory 215868 kb
Host smart-97190984-9559-464f-a6c2-85ffcdfc1c35
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408978382 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.2408978382
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2453288893
Short name T108
Test name
Test status
Simulation time 60508198 ps
CPU time 1.55 seconds
Started Mar 14 12:30:25 PM PDT 24
Finished Mar 14 12:30:27 PM PDT 24
Peak memory 213128 kb
Host smart-25e6eaa3-aa97-4e22-9ab4-a91b29dc8814
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453288893 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.2453288893
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2025375757
Short name T312
Test name
Test status
Simulation time 295214216 ps
CPU time 1.24 seconds
Started Mar 14 12:30:23 PM PDT 24
Finished Mar 14 12:30:24 PM PDT 24
Peak memory 204800 kb
Host smart-fc07bbd8-b433-49c3-a08d-8d2b66acc527
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025375757 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
2025375757
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.1530338457
Short name T257
Test name
Test status
Simulation time 64194282 ps
CPU time 0.69 seconds
Started Mar 14 12:30:11 PM PDT 24
Finished Mar 14 12:30:12 PM PDT 24
Peak memory 204592 kb
Host smart-dc28be3d-bce2-4909-a5d7-23c2da14dd6d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530338457 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
1530338457
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3314966366
Short name T316
Test name
Test status
Simulation time 165253421 ps
CPU time 3.6 seconds
Started Mar 14 12:30:37 PM PDT 24
Finished Mar 14 12:30:40 PM PDT 24
Peak memory 204952 kb
Host smart-9e4fe5b1-30ba-4353-8a7d-9fb0fb6b6724
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314966366 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.3314966366
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.1654745669
Short name T275
Test name
Test status
Simulation time 56979268 ps
CPU time 1.73 seconds
Started Mar 14 12:30:36 PM PDT 24
Finished Mar 14 12:30:38 PM PDT 24
Peak memory 213252 kb
Host smart-9b6eeebf-a2bd-4019-a316-9e76eb1a9192
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654745669 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.1654745669
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.1215950185
Short name T128
Test name
Test status
Simulation time 536653015 ps
CPU time 8.12 seconds
Started Mar 14 12:30:31 PM PDT 24
Finished Mar 14 12:30:40 PM PDT 24
Peak memory 213160 kb
Host smart-1612de66-d401-4108-be23-84b9cfe542f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215950185 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.1
215950185
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.707156760
Short name T78
Test name
Test status
Simulation time 6598498003 ps
CPU time 8.18 seconds
Started Mar 14 12:30:30 PM PDT 24
Finished Mar 14 12:30:38 PM PDT 24
Peak memory 218060 kb
Host smart-b93d51da-98fa-4a55-a9ee-52684739ea60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707156760 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.707156760
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.1809890675
Short name T310
Test name
Test status
Simulation time 55226806 ps
CPU time 1.49 seconds
Started Mar 14 12:30:41 PM PDT 24
Finished Mar 14 12:30:42 PM PDT 24
Peak memory 218492 kb
Host smart-2d035c87-5bc6-4b7e-8cbf-b0351817a554
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809890675 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.1809890675
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.147788497
Short name T303
Test name
Test status
Simulation time 297355478 ps
CPU time 1.82 seconds
Started Mar 14 12:30:22 PM PDT 24
Finished Mar 14 12:30:24 PM PDT 24
Peak memory 204864 kb
Host smart-06ab0aca-97aa-43e5-8d15-7b21556a83e4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147788497 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.147788497
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3760011932
Short name T278
Test name
Test status
Simulation time 72986485 ps
CPU time 0.74 seconds
Started Mar 14 12:30:35 PM PDT 24
Finished Mar 14 12:30:35 PM PDT 24
Peak memory 204556 kb
Host smart-1bc3925b-01ca-4bcd-94e9-55d6b58990dc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760011932 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
3760011932
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1998455789
Short name T104
Test name
Test status
Simulation time 297387806 ps
CPU time 6.43 seconds
Started Mar 14 12:30:27 PM PDT 24
Finished Mar 14 12:30:34 PM PDT 24
Peak memory 204984 kb
Host smart-0497a591-c15e-422b-bfa0-d4140070e5cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998455789 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.1998455789
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.2730859941
Short name T272
Test name
Test status
Simulation time 274298592 ps
CPU time 4.98 seconds
Started Mar 14 12:30:36 PM PDT 24
Finished Mar 14 12:30:41 PM PDT 24
Peak memory 213156 kb
Host smart-0c7fb718-5661-47eb-96fc-12449f8b9b34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730859941 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.2730859941
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.3555423905
Short name T380
Test name
Test status
Simulation time 419885252 ps
CPU time 8.92 seconds
Started Mar 14 12:30:31 PM PDT 24
Finished Mar 14 12:30:40 PM PDT 24
Peak memory 213076 kb
Host smart-bb6f3f04-f949-410d-a05e-eb9899c4fccf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555423905 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.3
555423905
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2680208701
Short name T370
Test name
Test status
Simulation time 2328571788 ps
CPU time 31.97 seconds
Started Mar 14 12:30:23 PM PDT 24
Finished Mar 14 12:30:55 PM PDT 24
Peak memory 205116 kb
Host smart-e48451b4-1561-490b-a128-0b566aa09447
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680208701 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.2680208701
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.1996146876
Short name T109
Test name
Test status
Simulation time 2806650550 ps
CPU time 52.71 seconds
Started Mar 14 12:30:27 PM PDT 24
Finished Mar 14 12:31:20 PM PDT 24
Peak memory 205048 kb
Host smart-8e7e6567-7484-40de-b4c0-c5f8af0da63e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996146876 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.1996146876
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.165067449
Short name T113
Test name
Test status
Simulation time 55476234 ps
CPU time 1.45 seconds
Started Mar 14 12:30:22 PM PDT 24
Finished Mar 14 12:30:24 PM PDT 24
Peak memory 213152 kb
Host smart-e9c0e7d9-c347-4ff9-b759-7c39ce6e1b28
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165067449 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.165067449
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3572924247
Short name T255
Test name
Test status
Simulation time 1978083916 ps
CPU time 4.04 seconds
Started Mar 14 12:30:24 PM PDT 24
Finished Mar 14 12:30:28 PM PDT 24
Peak memory 218736 kb
Host smart-1e4222d1-e03b-4b80-9d19-fee49eae1efe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572924247 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.3572924247
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.2050421262
Short name T371
Test name
Test status
Simulation time 28367611 ps
CPU time 1.46 seconds
Started Mar 14 12:30:28 PM PDT 24
Finished Mar 14 12:30:30 PM PDT 24
Peak memory 213196 kb
Host smart-8bb89068-6916-47bb-b932-0f2959c98588
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050421262 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.2050421262
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.3303661553
Short name T286
Test name
Test status
Simulation time 8932648944 ps
CPU time 26.02 seconds
Started Mar 14 12:30:05 PM PDT 24
Finished Mar 14 12:30:31 PM PDT 24
Peak memory 204924 kb
Host smart-c42ccd5d-fc21-426a-a01d-e1e86222155e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303661553 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.3303661553
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.2517265996
Short name T305
Test name
Test status
Simulation time 17366493036 ps
CPU time 62.3 seconds
Started Mar 14 12:30:15 PM PDT 24
Finished Mar 14 12:31:17 PM PDT 24
Peak memory 204868 kb
Host smart-8374cf90-dc12-4c08-b821-9a49bb67940a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517265996 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_bit_bash.2517265996
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.1557896955
Short name T97
Test name
Test status
Simulation time 753888447 ps
CPU time 1.42 seconds
Started Mar 14 12:30:07 PM PDT 24
Finished Mar 14 12:30:09 PM PDT 24
Peak memory 204952 kb
Host smart-6adb32fd-97d2-4ec6-bf4d-3158f18544c6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557896955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.1557896955
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1592751912
Short name T253
Test name
Test status
Simulation time 222199867 ps
CPU time 1.58 seconds
Started Mar 14 12:30:28 PM PDT 24
Finished Mar 14 12:30:30 PM PDT 24
Peak memory 204704 kb
Host smart-2d10f736-e628-4bd8-8cff-e83407cee22a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592751912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.1
592751912
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.785795967
Short name T297
Test name
Test status
Simulation time 169844210 ps
CPU time 0.88 seconds
Started Mar 14 12:30:24 PM PDT 24
Finished Mar 14 12:30:25 PM PDT 24
Peak memory 204708 kb
Host smart-ddb47669-1809-4168-a037-b9a1e1701019
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785795967 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_aliasing.785795967
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.918385743
Short name T304
Test name
Test status
Simulation time 388425991 ps
CPU time 2.19 seconds
Started Mar 14 12:30:21 PM PDT 24
Finished Mar 14 12:30:23 PM PDT 24
Peak memory 204756 kb
Host smart-a0d9354c-1401-450c-9af4-095f3aaa902c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918385743 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_bit_bash.918385743
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1058560250
Short name T365
Test name
Test status
Simulation time 46524408 ps
CPU time 0.73 seconds
Started Mar 14 12:30:34 PM PDT 24
Finished Mar 14 12:30:34 PM PDT 24
Peak memory 204708 kb
Host smart-972b27e4-6a7f-4c34-897f-f867f97ec010
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058560250 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.1058560250
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.552802191
Short name T345
Test name
Test status
Simulation time 52218070 ps
CPU time 0.81 seconds
Started Mar 14 12:30:10 PM PDT 24
Finished Mar 14 12:30:10 PM PDT 24
Peak memory 204552 kb
Host smart-c9126bad-c849-4667-85eb-2b0f87676494
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552802191 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.552802191
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1343094268
Short name T251
Test name
Test status
Simulation time 112820983 ps
CPU time 0.67 seconds
Started Mar 14 12:30:11 PM PDT 24
Finished Mar 14 12:30:12 PM PDT 24
Peak memory 204584 kb
Host smart-4a3b241f-23f0-458e-946b-bcd4d4c9aae5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343094268 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.1343094268
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.624728653
Short name T258
Test name
Test status
Simulation time 54014307 ps
CPU time 0.65 seconds
Started Mar 14 12:30:22 PM PDT 24
Finished Mar 14 12:30:23 PM PDT 24
Peak memory 204600 kb
Host smart-8a0678d3-41be-4c7b-867e-77023a9838be
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624728653 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.624728653
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.1601971570
Short name T353
Test name
Test status
Simulation time 383804982 ps
CPU time 3.41 seconds
Started Mar 14 12:30:10 PM PDT 24
Finished Mar 14 12:30:14 PM PDT 24
Peak memory 204984 kb
Host smart-02a51e91-89e3-4ba1-8c35-4ce72481b17b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601971570 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.1601971570
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.849529467
Short name T285
Test name
Test status
Simulation time 304126012 ps
CPU time 3.69 seconds
Started Mar 14 12:30:14 PM PDT 24
Finished Mar 14 12:30:18 PM PDT 24
Peak memory 213168 kb
Host smart-1355ce33-c7c5-4c02-939a-790357304353
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849529467 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.849529467
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.1293413608
Short name T124
Test name
Test status
Simulation time 5748412673 ps
CPU time 18.53 seconds
Started Mar 14 12:30:23 PM PDT 24
Finished Mar 14 12:30:42 PM PDT 24
Peak memory 220428 kb
Host smart-10fc7f59-aae5-4b23-8c57-04db9cce9158
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293413608 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.1293413608
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/21.rv_dm_tap_fsm_rand_reset.698715813
Short name T314
Test name
Test status
Simulation time 20426480337 ps
CPU time 19.12 seconds
Started Mar 14 12:30:18 PM PDT 24
Finished Mar 14 12:30:37 PM PDT 24
Peak memory 229676 kb
Host smart-2227959e-7b1f-498d-b9cc-f4d01c451550
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698715813 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 21.rv_dm_tap_fsm_rand_reset.698715813
Directory /workspace/21.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/22.rv_dm_tap_fsm_rand_reset.3772724498
Short name T354
Test name
Test status
Simulation time 16117064215 ps
CPU time 26.86 seconds
Started Mar 14 12:30:29 PM PDT 24
Finished Mar 14 12:30:56 PM PDT 24
Peak memory 213360 kb
Host smart-8d09ceb6-9ef2-46eb-bcd1-036510aaf70d
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772724498 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 22.rv_dm_tap_fsm_rand_reset.3772724498
Directory /workspace/22.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/27.rv_dm_tap_fsm_rand_reset.2884625663
Short name T63
Test name
Test status
Simulation time 10210482204 ps
CPU time 14.47 seconds
Started Mar 14 12:30:32 PM PDT 24
Finished Mar 14 12:30:47 PM PDT 24
Peak memory 214168 kb
Host smart-714ce806-af68-441c-90f2-ce0438055bc9
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884625663 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 27.rv_dm_tap_fsm_rand_reset.2884625663
Directory /workspace/27.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/29.rv_dm_tap_fsm_rand_reset.852120498
Short name T361
Test name
Test status
Simulation time 14126431022 ps
CPU time 12.12 seconds
Started Mar 14 12:30:28 PM PDT 24
Finished Mar 14 12:30:41 PM PDT 24
Peak memory 213900 kb
Host smart-a94285f8-b2b3-4387-bf8d-6e80f3112ecb
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852120498 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 29.rv_dm_tap_fsm_rand_reset.852120498
Directory /workspace/29.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1374188012
Short name T381
Test name
Test status
Simulation time 1210826436 ps
CPU time 26.42 seconds
Started Mar 14 12:30:22 PM PDT 24
Finished Mar 14 12:30:55 PM PDT 24
Peak memory 204980 kb
Host smart-e1f264cd-001d-4536-b57a-73db89f2905e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374188012 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.1374188012
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.135022157
Short name T85
Test name
Test status
Simulation time 3180415906 ps
CPU time 34.85 seconds
Started Mar 14 12:30:16 PM PDT 24
Finished Mar 14 12:30:51 PM PDT 24
Peak memory 213348 kb
Host smart-239d31bf-1e46-4a04-aced-9049e414dd25
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135022157 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.135022157
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.3300049265
Short name T294
Test name
Test status
Simulation time 108019595 ps
CPU time 1.43 seconds
Started Mar 14 12:30:10 PM PDT 24
Finished Mar 14 12:30:11 PM PDT 24
Peak memory 213240 kb
Host smart-1ac3d58a-8abc-4d50-950e-3c9de950fba8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300049265 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.3300049265
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1523295217
Short name T282
Test name
Test status
Simulation time 117870076 ps
CPU time 3.48 seconds
Started Mar 14 12:30:24 PM PDT 24
Finished Mar 14 12:30:28 PM PDT 24
Peak memory 218760 kb
Host smart-99be726e-904e-4f67-9129-6b939c400708
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523295217 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.1523295217
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2779149666
Short name T376
Test name
Test status
Simulation time 185686022 ps
CPU time 1.57 seconds
Started Mar 14 12:30:27 PM PDT 24
Finished Mar 14 12:30:29 PM PDT 24
Peak memory 213004 kb
Host smart-6bc95ed4-7d6a-4cd2-a541-a7d97524e318
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779149666 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.2779149666
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.2247152260
Short name T270
Test name
Test status
Simulation time 15292439985 ps
CPU time 46.7 seconds
Started Mar 14 12:30:07 PM PDT 24
Finished Mar 14 12:30:54 PM PDT 24
Peak memory 204896 kb
Host smart-cc4357c6-256a-416f-9b0e-c3659323bb4a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247152260 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.2247152260
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.2357100457
Short name T348
Test name
Test status
Simulation time 20081879183 ps
CPU time 70.91 seconds
Started Mar 14 12:30:09 PM PDT 24
Finished Mar 14 12:31:20 PM PDT 24
Peak memory 204920 kb
Host smart-cfb82e79-9b70-4d39-840f-0228b4cc5cf9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357100457 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_bit_bash.2357100457
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2794439338
Short name T358
Test name
Test status
Simulation time 2219816455 ps
CPU time 7.11 seconds
Started Mar 14 12:30:07 PM PDT 24
Finished Mar 14 12:30:14 PM PDT 24
Peak memory 205044 kb
Host smart-8d701f94-7f36-498f-8071-7753b5740ecd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794439338 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.2794439338
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1000355548
Short name T274
Test name
Test status
Simulation time 744692486 ps
CPU time 2.04 seconds
Started Mar 14 12:30:09 PM PDT 24
Finished Mar 14 12:30:11 PM PDT 24
Peak memory 204864 kb
Host smart-3c8168aa-1cd4-4b65-b7b1-a789426605de
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000355548 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.1
000355548
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3866361201
Short name T349
Test name
Test status
Simulation time 47177535 ps
CPU time 0.74 seconds
Started Mar 14 12:30:22 PM PDT 24
Finished Mar 14 12:30:23 PM PDT 24
Peak memory 204620 kb
Host smart-51bf5a4e-0b1c-4428-b851-a97f391ba448
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866361201 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.3866361201
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2936874843
Short name T260
Test name
Test status
Simulation time 861574299 ps
CPU time 2.21 seconds
Started Mar 14 12:30:08 PM PDT 24
Finished Mar 14 12:30:11 PM PDT 24
Peak memory 204884 kb
Host smart-6980527d-f2c8-4c02-8490-93d37bf1978c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936874843 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.2936874843
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3228587727
Short name T245
Test name
Test status
Simulation time 383827984 ps
CPU time 0.72 seconds
Started Mar 14 12:30:23 PM PDT 24
Finished Mar 14 12:30:24 PM PDT 24
Peak memory 204612 kb
Host smart-da48ff5a-d19e-4c1e-891f-656c72608159
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228587727 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.3228587727
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.3971046497
Short name T268
Test name
Test status
Simulation time 70398581 ps
CPU time 0.79 seconds
Started Mar 14 12:30:24 PM PDT 24
Finished Mar 14 12:30:25 PM PDT 24
Peak memory 204608 kb
Host smart-3de7a8dc-f7df-4983-84ac-0f962d035d1f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971046497 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.3
971046497
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.1445645500
Short name T377
Test name
Test status
Simulation time 23200995 ps
CPU time 0.66 seconds
Started Mar 14 12:30:09 PM PDT 24
Finished Mar 14 12:30:10 PM PDT 24
Peak memory 204632 kb
Host smart-9c76fbcd-3c33-4d2f-947e-b337b537192f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445645500 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.1445645500
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.3392848604
Short name T248
Test name
Test status
Simulation time 16052241 ps
CPU time 0.65 seconds
Started Mar 14 12:30:23 PM PDT 24
Finished Mar 14 12:30:24 PM PDT 24
Peak memory 204612 kb
Host smart-fb149481-7981-40e4-a9e9-ccdd76506bc2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392848604 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.3392848604
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.456443774
Short name T106
Test name
Test status
Simulation time 238966918 ps
CPU time 6.02 seconds
Started Mar 14 12:30:28 PM PDT 24
Finished Mar 14 12:30:35 PM PDT 24
Peak memory 204940 kb
Host smart-ccea46ce-a439-43f5-9b7c-2dbcf42713b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456443774 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_c
sr_outstanding.456443774
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.4073980096
Short name T350
Test name
Test status
Simulation time 266548096 ps
CPU time 4.27 seconds
Started Mar 14 12:30:24 PM PDT 24
Finished Mar 14 12:30:28 PM PDT 24
Peak memory 213180 kb
Host smart-e3b1f9ca-8b02-4220-84aa-151da477e80a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073980096 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.4073980096
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.1152255439
Short name T77
Test name
Test status
Simulation time 249106275 ps
CPU time 7.95 seconds
Started Mar 14 12:30:07 PM PDT 24
Finished Mar 14 12:30:15 PM PDT 24
Peak memory 213144 kb
Host smart-bfaa8223-95c9-432c-b53c-fccda1d34f1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152255439 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.1152255439
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_dm_tap_fsm_rand_reset.2306029439
Short name T351
Test name
Test status
Simulation time 6595613084 ps
CPU time 13.27 seconds
Started Mar 14 12:30:29 PM PDT 24
Finished Mar 14 12:30:42 PM PDT 24
Peak memory 221104 kb
Host smart-570e1821-7336-4703-85ad-6bb6fcc1ad5d
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306029439 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 30.rv_dm_tap_fsm_rand_reset.2306029439
Directory /workspace/30.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/32.rv_dm_tap_fsm_rand_reset.2467347217
Short name T300
Test name
Test status
Simulation time 17964817873 ps
CPU time 30.72 seconds
Started Mar 14 12:30:49 PM PDT 24
Finished Mar 14 12:31:20 PM PDT 24
Peak memory 229688 kb
Host smart-dcb12ce0-a5a3-490e-ad46-d74458ed1357
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467347217 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 32.rv_dm_tap_fsm_rand_reset.2467347217
Directory /workspace/32.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/33.rv_dm_tap_fsm_rand_reset.3341139291
Short name T62
Test name
Test status
Simulation time 14008659631 ps
CPU time 13.31 seconds
Started Mar 14 12:30:36 PM PDT 24
Finished Mar 14 12:30:50 PM PDT 24
Peak memory 221428 kb
Host smart-161e22ea-f2f1-42a5-a91a-00e412e1f1f4
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341139291 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 33.rv_dm_tap_fsm_rand_reset.3341139291
Directory /workspace/33.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/37.rv_dm_tap_fsm_rand_reset.2830404715
Short name T368
Test name
Test status
Simulation time 34723904383 ps
CPU time 16.8 seconds
Started Mar 14 12:30:29 PM PDT 24
Finished Mar 14 12:30:47 PM PDT 24
Peak memory 229672 kb
Host smart-72607856-7e1a-4c00-88ba-947808673f60
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830404715 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 37.rv_dm_tap_fsm_rand_reset.2830404715
Directory /workspace/37.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/38.rv_dm_tap_fsm_rand_reset.1027213900
Short name T337
Test name
Test status
Simulation time 16231924681 ps
CPU time 12.93 seconds
Started Mar 14 12:30:45 PM PDT 24
Finished Mar 14 12:30:58 PM PDT 24
Peak memory 221124 kb
Host smart-dbf471ad-21f9-4c61-96cc-e75a36180904
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027213900 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 38.rv_dm_tap_fsm_rand_reset.1027213900
Directory /workspace/38.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2822677474
Short name T328
Test name
Test status
Simulation time 9322246078 ps
CPU time 32.94 seconds
Started Mar 14 12:30:46 PM PDT 24
Finished Mar 14 12:31:19 PM PDT 24
Peak memory 205104 kb
Host smart-5563df22-b644-4240-ac15-34af425d5582
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822677474 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.2822677474
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.2878901113
Short name T111
Test name
Test status
Simulation time 7947503162 ps
CPU time 69.6 seconds
Started Mar 14 12:30:22 PM PDT 24
Finished Mar 14 12:31:32 PM PDT 24
Peak memory 205192 kb
Host smart-1ccdeea8-4111-4c44-8532-3f3168af062e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878901113 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.2878901113
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.3414117430
Short name T356
Test name
Test status
Simulation time 191849105 ps
CPU time 1.57 seconds
Started Mar 14 12:30:19 PM PDT 24
Finished Mar 14 12:30:21 PM PDT 24
Peak memory 213128 kb
Host smart-db06e992-39b0-493f-a632-a7525c8b8f3a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414117430 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.3414117430
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2842572617
Short name T355
Test name
Test status
Simulation time 4261975745 ps
CPU time 3.59 seconds
Started Mar 14 12:30:24 PM PDT 24
Finished Mar 14 12:30:28 PM PDT 24
Peak memory 216096 kb
Host smart-d7d004a2-91e2-4cad-8a19-38fdd41378e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842572617 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.2842572617
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.27858956
Short name T256
Test name
Test status
Simulation time 84479485 ps
CPU time 1.51 seconds
Started Mar 14 12:30:24 PM PDT 24
Finished Mar 14 12:30:26 PM PDT 24
Peak memory 213176 kb
Host smart-4c11d2cc-b3ad-449a-acd8-a4a8eb12655a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27858956 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.27858956
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2195450011
Short name T295
Test name
Test status
Simulation time 12757950681 ps
CPU time 14.83 seconds
Started Mar 14 12:30:02 PM PDT 24
Finished Mar 14 12:30:18 PM PDT 24
Peak memory 204900 kb
Host smart-4122e636-17ee-43cb-a192-c585c600c35d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195450011 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.2195450011
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3458302373
Short name T311
Test name
Test status
Simulation time 11781459845 ps
CPU time 11.58 seconds
Started Mar 14 12:30:20 PM PDT 24
Finished Mar 14 12:30:31 PM PDT 24
Peak memory 204964 kb
Host smart-10a42952-b1cb-4b24-9e9a-a2807ddd5387
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458302373 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_bit_bash.3458302373
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.3812585565
Short name T96
Test name
Test status
Simulation time 989960801 ps
CPU time 2.32 seconds
Started Mar 14 12:30:25 PM PDT 24
Finished Mar 14 12:30:27 PM PDT 24
Peak memory 204976 kb
Host smart-b86e0962-daa1-4340-b2de-81f7a70acd4e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812585565 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.3812585565
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.1636092565
Short name T342
Test name
Test status
Simulation time 585157118 ps
CPU time 1.25 seconds
Started Mar 14 12:30:05 PM PDT 24
Finished Mar 14 12:30:06 PM PDT 24
Peak memory 204756 kb
Host smart-03622106-0796-43b1-aee2-7fd9c1b607e2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636092565 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.1
636092565
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.906220420
Short name T66
Test name
Test status
Simulation time 111279626 ps
CPU time 0.99 seconds
Started Mar 14 12:30:24 PM PDT 24
Finished Mar 14 12:30:25 PM PDT 24
Peak memory 204620 kb
Host smart-9f4d111b-a7f8-4504-860b-ca126b206623
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906220420 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr
_aliasing.906220420
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.4167658382
Short name T266
Test name
Test status
Simulation time 3076809223 ps
CPU time 2.98 seconds
Started Mar 14 12:30:22 PM PDT 24
Finished Mar 14 12:30:25 PM PDT 24
Peak memory 204980 kb
Host smart-6d39b606-0c53-4648-90ca-866b398c8ba3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167658382 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.4167658382
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.1904903297
Short name T42
Test name
Test status
Simulation time 340231319 ps
CPU time 0.69 seconds
Started Mar 14 12:30:21 PM PDT 24
Finished Mar 14 12:30:22 PM PDT 24
Peak memory 204556 kb
Host smart-e0f4c2a4-70a0-404e-b83d-4bde2565e3d7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904903297 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.1904903297
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.4092452106
Short name T317
Test name
Test status
Simulation time 81993118 ps
CPU time 0.9 seconds
Started Mar 14 12:30:27 PM PDT 24
Finished Mar 14 12:30:39 PM PDT 24
Peak memory 204576 kb
Host smart-3858deb5-c345-447c-a628-f9fdf0536ac0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092452106 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.4
092452106
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.3449384500
Short name T324
Test name
Test status
Simulation time 59531216 ps
CPU time 0.7 seconds
Started Mar 14 12:30:03 PM PDT 24
Finished Mar 14 12:30:04 PM PDT 24
Peak memory 204580 kb
Host smart-1e11ab37-47ef-4653-96bc-a3ab909100f0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449384500 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.3449384500
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.79948432
Short name T244
Test name
Test status
Simulation time 15084635 ps
CPU time 0.68 seconds
Started Mar 14 12:30:24 PM PDT 24
Finished Mar 14 12:30:25 PM PDT 24
Peak memory 204592 kb
Host smart-c1b7f65b-c18f-414a-97fa-fa3a0908585d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79948432 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.79948432
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.119548552
Short name T115
Test name
Test status
Simulation time 1049454481 ps
CPU time 3.89 seconds
Started Mar 14 12:30:07 PM PDT 24
Finished Mar 14 12:30:11 PM PDT 24
Peak memory 205040 kb
Host smart-3d253452-4ce7-40df-84cd-631baf1492dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119548552 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_c
sr_outstanding.119548552
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2617819228
Short name T269
Test name
Test status
Simulation time 391090873 ps
CPU time 2.86 seconds
Started Mar 14 12:30:25 PM PDT 24
Finished Mar 14 12:30:29 PM PDT 24
Peak memory 213260 kb
Host smart-35f8e5f7-fc31-418f-b18c-845edff884fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617819228 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.2617819228
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.2074150594
Short name T359
Test name
Test status
Simulation time 1159831845 ps
CPU time 7.93 seconds
Started Mar 14 12:30:19 PM PDT 24
Finished Mar 14 12:30:27 PM PDT 24
Peak memory 221268 kb
Host smart-8235bb01-36cc-4c11-9d05-5d9a607f3cbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074150594 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.2074150594
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.1783403934
Short name T357
Test name
Test status
Simulation time 805178442 ps
CPU time 3.05 seconds
Started Mar 14 12:30:21 PM PDT 24
Finished Mar 14 12:30:24 PM PDT 24
Peak memory 214492 kb
Host smart-e91dd00f-541a-40be-8ece-a8379694e4f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783403934 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.1783403934
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.3064329030
Short name T250
Test name
Test status
Simulation time 872919537 ps
CPU time 2.37 seconds
Started Mar 14 12:30:20 PM PDT 24
Finished Mar 14 12:30:22 PM PDT 24
Peak memory 213292 kb
Host smart-e03d61f4-e592-4f04-b647-f9cb19897f51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064329030 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.3064329030
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3796844440
Short name T325
Test name
Test status
Simulation time 502923388 ps
CPU time 2.21 seconds
Started Mar 14 12:30:23 PM PDT 24
Finished Mar 14 12:30:25 PM PDT 24
Peak memory 204804 kb
Host smart-716df84d-5336-42bf-9df0-113dd8d44600
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796844440 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.3
796844440
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.1194758331
Short name T322
Test name
Test status
Simulation time 72304316 ps
CPU time 0.7 seconds
Started Mar 14 12:30:06 PM PDT 24
Finished Mar 14 12:30:07 PM PDT 24
Peak memory 204608 kb
Host smart-3febc4c6-3886-4bdf-9eb3-445357172290
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194758331 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.1
194758331
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.3939066313
Short name T333
Test name
Test status
Simulation time 850330496 ps
CPU time 4.24 seconds
Started Mar 14 12:30:22 PM PDT 24
Finished Mar 14 12:30:26 PM PDT 24
Peak memory 205032 kb
Host smart-327dc7df-21a6-41ef-b754-71e90e2d101d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939066313 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.3939066313
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.3337542778
Short name T352
Test name
Test status
Simulation time 15689762057 ps
CPU time 11.9 seconds
Started Mar 14 12:30:17 PM PDT 24
Finished Mar 14 12:30:29 PM PDT 24
Peak memory 213740 kb
Host smart-37c0d945-9a76-48c6-b5c8-060dad8b0265
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337542778 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.3337542778
Directory /workspace/5.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.2913588910
Short name T50
Test name
Test status
Simulation time 161086426 ps
CPU time 3.79 seconds
Started Mar 14 12:30:19 PM PDT 24
Finished Mar 14 12:30:23 PM PDT 24
Peak memory 213192 kb
Host smart-89cd3a9e-8729-44ea-a817-568bb81a6e51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913588910 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.2913588910
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.1841044857
Short name T296
Test name
Test status
Simulation time 549342629 ps
CPU time 9.78 seconds
Started Mar 14 12:30:07 PM PDT 24
Finished Mar 14 12:30:17 PM PDT 24
Peak memory 213164 kb
Host smart-0ed932a7-4878-459b-bee8-53fa0260a11a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841044857 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.1841044857
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2429468712
Short name T287
Test name
Test status
Simulation time 77027412 ps
CPU time 2.23 seconds
Started Mar 14 12:30:14 PM PDT 24
Finished Mar 14 12:30:16 PM PDT 24
Peak memory 217664 kb
Host smart-ec0b4968-bdf9-420e-b788-a4991cef37e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429468712 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.2429468712
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.2118918656
Short name T88
Test name
Test status
Simulation time 513642405 ps
CPU time 2.29 seconds
Started Mar 14 12:30:13 PM PDT 24
Finished Mar 14 12:30:15 PM PDT 24
Peak memory 221480 kb
Host smart-c5c7b5f3-ccc2-451c-8394-f69873be2ad8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118918656 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.2118918656
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.3960761344
Short name T335
Test name
Test status
Simulation time 317515944 ps
CPU time 1.23 seconds
Started Mar 14 12:30:23 PM PDT 24
Finished Mar 14 12:30:24 PM PDT 24
Peak memory 204716 kb
Host smart-03bb4c50-8fe8-43da-a19d-3ed1b1372235
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960761344 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.3
960761344
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.3086418118
Short name T382
Test name
Test status
Simulation time 45748036 ps
CPU time 0.7 seconds
Started Mar 14 12:30:27 PM PDT 24
Finished Mar 14 12:30:29 PM PDT 24
Peak memory 204572 kb
Host smart-21e25384-c1b8-4d86-8c67-7bdf81a5f57b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086418118 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.3
086418118
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.1880954882
Short name T346
Test name
Test status
Simulation time 201049263 ps
CPU time 3.87 seconds
Started Mar 14 12:30:27 PM PDT 24
Finished Mar 14 12:30:31 PM PDT 24
Peak memory 204968 kb
Host smart-416a697e-76cb-4311-a0f0-d151874fdbc0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880954882 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.1880954882
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3407722516
Short name T340
Test name
Test status
Simulation time 1058773218 ps
CPU time 2.83 seconds
Started Mar 14 12:30:24 PM PDT 24
Finished Mar 14 12:30:27 PM PDT 24
Peak memory 218444 kb
Host smart-c4e976e7-09c7-4523-aa19-7a10792faf1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407722516 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.3407722516
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.285965727
Short name T112
Test name
Test status
Simulation time 902595052 ps
CPU time 2.53 seconds
Started Mar 14 12:30:14 PM PDT 24
Finished Mar 14 12:30:16 PM PDT 24
Peak memory 213228 kb
Host smart-473e751f-1eb6-49e9-911b-e3acad2d62c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285965727 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.285965727
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3390436538
Short name T243
Test name
Test status
Simulation time 507991996 ps
CPU time 0.95 seconds
Started Mar 14 12:30:23 PM PDT 24
Finished Mar 14 12:30:24 PM PDT 24
Peak memory 204744 kb
Host smart-129b2b38-7378-4e95-8919-ff8cfdad7e5e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390436538 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.3
390436538
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.2901273041
Short name T302
Test name
Test status
Simulation time 55940376 ps
CPU time 0.68 seconds
Started Mar 14 12:30:24 PM PDT 24
Finished Mar 14 12:30:25 PM PDT 24
Peak memory 204576 kb
Host smart-bcdc5bcf-fca0-4f96-86b5-90dbc2363b2e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901273041 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.2
901273041
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.146344691
Short name T363
Test name
Test status
Simulation time 1313411748 ps
CPU time 6.35 seconds
Started Mar 14 12:30:22 PM PDT 24
Finished Mar 14 12:30:28 PM PDT 24
Peak memory 204956 kb
Host smart-69ce256c-cd4c-4d8f-ba22-b962431f85d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146344691 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_c
sr_outstanding.146344691
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.2694120667
Short name T95
Test name
Test status
Simulation time 66799867 ps
CPU time 3.64 seconds
Started Mar 14 12:30:10 PM PDT 24
Finished Mar 14 12:30:14 PM PDT 24
Peak memory 213224 kb
Host smart-203d2cc4-0c92-452d-bfb1-44009772dccf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694120667 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.2694120667
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2273728222
Short name T127
Test name
Test status
Simulation time 761375593 ps
CPU time 15.7 seconds
Started Mar 14 12:30:08 PM PDT 24
Finished Mar 14 12:30:24 PM PDT 24
Peak memory 213304 kb
Host smart-4d1cabc1-d014-4d29-bf9d-d1c0abdee1d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273728222 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.2273728222
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.551927505
Short name T265
Test name
Test status
Simulation time 87464845 ps
CPU time 2.17 seconds
Started Mar 14 12:30:27 PM PDT 24
Finished Mar 14 12:30:29 PM PDT 24
Peak memory 213228 kb
Host smart-85b21216-0842-4021-82a0-13ca43ed5c2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551927505 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.551927505
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.3889338566
Short name T100
Test name
Test status
Simulation time 190157027 ps
CPU time 1.45 seconds
Started Mar 14 12:30:22 PM PDT 24
Finished Mar 14 12:30:29 PM PDT 24
Peak memory 213172 kb
Host smart-66edd04a-31f2-407e-9d9c-370006bebf6f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889338566 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.3889338566
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1646597533
Short name T293
Test name
Test status
Simulation time 195017267 ps
CPU time 1.12 seconds
Started Mar 14 12:30:08 PM PDT 24
Finished Mar 14 12:30:09 PM PDT 24
Peak memory 204772 kb
Host smart-b5654d72-1d52-459d-8f6d-aae7f45628c8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646597533 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.1
646597533
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.72502806
Short name T336
Test name
Test status
Simulation time 89973239 ps
CPU time 0.76 seconds
Started Mar 14 12:30:24 PM PDT 24
Finished Mar 14 12:30:25 PM PDT 24
Peak memory 204624 kb
Host smart-b7746808-4f57-4033-b608-6508448930e4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72502806 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.72502806
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.271179823
Short name T91
Test name
Test status
Simulation time 375151445 ps
CPU time 3.43 seconds
Started Mar 14 12:30:18 PM PDT 24
Finished Mar 14 12:30:21 PM PDT 24
Peak memory 204940 kb
Host smart-3111002f-21d6-4885-a109-d01a1f308ee0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271179823 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_c
sr_outstanding.271179823
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2570352281
Short name T329
Test name
Test status
Simulation time 180945552 ps
CPU time 1.95 seconds
Started Mar 14 12:30:11 PM PDT 24
Finished Mar 14 12:30:13 PM PDT 24
Peak memory 213136 kb
Host smart-6d1352c4-fa4b-4d97-8fbc-c40369a28dc6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570352281 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.2570352281
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.1645092858
Short name T125
Test name
Test status
Simulation time 406818282 ps
CPU time 8.1 seconds
Started Mar 14 12:30:17 PM PDT 24
Finished Mar 14 12:30:25 PM PDT 24
Peak memory 213532 kb
Host smart-7ac2e84c-11bd-4b9c-bd48-74cfcb191aef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645092858 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.1645092858
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.2886253407
Short name T276
Test name
Test status
Simulation time 944018380 ps
CPU time 4.16 seconds
Started Mar 14 12:30:24 PM PDT 24
Finished Mar 14 12:30:29 PM PDT 24
Peak memory 217920 kb
Host smart-a3ef4ec4-61e5-41c3-8417-abc54f6c15f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886253407 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.2886253407
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1500820202
Short name T334
Test name
Test status
Simulation time 286949692 ps
CPU time 1.37 seconds
Started Mar 14 12:30:19 PM PDT 24
Finished Mar 14 12:30:20 PM PDT 24
Peak memory 213100 kb
Host smart-f09d9939-a4f0-4066-b8af-520683f37cdf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500820202 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.1500820202
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.2662966663
Short name T315
Test name
Test status
Simulation time 1328044550 ps
CPU time 1.75 seconds
Started Mar 14 12:30:22 PM PDT 24
Finished Mar 14 12:30:24 PM PDT 24
Peak memory 204688 kb
Host smart-987179e4-ff0d-49b9-837b-9cdc3e932852
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662966663 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.2
662966663
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.519113379
Short name T332
Test name
Test status
Simulation time 77220488 ps
CPU time 0.93 seconds
Started Mar 14 12:30:10 PM PDT 24
Finished Mar 14 12:30:11 PM PDT 24
Peak memory 204580 kb
Host smart-3bfde278-7c39-4393-a7a2-0a6f5ba8110e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519113379 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.519113379
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.102497979
Short name T87
Test name
Test status
Simulation time 830625075 ps
CPU time 7.46 seconds
Started Mar 14 12:30:21 PM PDT 24
Finished Mar 14 12:30:29 PM PDT 24
Peak memory 205044 kb
Host smart-a9e8231e-3623-40a9-bee4-a90068ab1771
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102497979 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_c
sr_outstanding.102497979
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.3841491548
Short name T298
Test name
Test status
Simulation time 79663353 ps
CPU time 2.49 seconds
Started Mar 14 12:30:28 PM PDT 24
Finished Mar 14 12:30:31 PM PDT 24
Peak memory 213232 kb
Host smart-2b266b50-d52f-4722-a81d-cba171c4048c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841491548 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.3841491548
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2226762128
Short name T130
Test name
Test status
Simulation time 651641874 ps
CPU time 15.14 seconds
Started Mar 14 12:30:08 PM PDT 24
Finished Mar 14 12:30:24 PM PDT 24
Peak memory 213236 kb
Host smart-94cb8e77-011f-40c7-b1b3-0b94a7186346
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226762128 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.2226762128
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.3246570635
Short name T149
Test name
Test status
Simulation time 21708595 ps
CPU time 0.74 seconds
Started Mar 14 01:15:33 PM PDT 24
Finished Mar 14 01:15:34 PM PDT 24
Peak memory 204312 kb
Host smart-512c6eae-3106-4198-bb31-f4de18b21b02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246570635 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.3246570635
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.3954555999
Short name T229
Test name
Test status
Simulation time 4317197341 ps
CPU time 9.04 seconds
Started Mar 14 01:15:33 PM PDT 24
Finished Mar 14 01:15:43 PM PDT 24
Peak memory 204704 kb
Host smart-48e5845e-4d71-4a6f-b79a-11765f08c047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954555999 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.3954555999
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.3645297235
Short name T118
Test name
Test status
Simulation time 2780546970 ps
CPU time 10.86 seconds
Started Mar 14 01:15:38 PM PDT 24
Finished Mar 14 01:15:49 PM PDT 24
Peak memory 204680 kb
Host smart-b7076b7c-0e8f-4b1a-a912-a4771db86ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645297235 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.3645297235
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.1894698489
Short name T139
Test name
Test status
Simulation time 2154464660 ps
CPU time 2.9 seconds
Started Mar 14 01:15:33 PM PDT 24
Finished Mar 14 01:15:36 PM PDT 24
Peak memory 204428 kb
Host smart-6265a26a-f876-49d7-92b1-7d7eb56f7751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894698489 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.1894698489
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.116711863
Short name T142
Test name
Test status
Simulation time 40148848 ps
CPU time 0.76 seconds
Started Mar 14 01:15:33 PM PDT 24
Finished Mar 14 01:15:34 PM PDT 24
Peak memory 204232 kb
Host smart-44de0a88-fa6e-473d-a68a-646c31d431e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116711863 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.116711863
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.2897829890
Short name T179
Test name
Test status
Simulation time 2326067276 ps
CPU time 8.37 seconds
Started Mar 14 01:15:35 PM PDT 24
Finished Mar 14 01:15:43 PM PDT 24
Peak memory 204668 kb
Host smart-bb54d5fa-ec06-4f72-be2a-552d23657f74
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2897829890 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t
l_access.2897829890
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.1740271579
Short name T140
Test name
Test status
Simulation time 719105417 ps
CPU time 1.55 seconds
Started Mar 14 01:15:39 PM PDT 24
Finished Mar 14 01:15:40 PM PDT 24
Peak memory 204364 kb
Host smart-ede66e90-beed-4efe-b0ab-4613d78e92ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740271579 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.1740271579
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.2682568590
Short name T180
Test name
Test status
Simulation time 195281330 ps
CPU time 0.97 seconds
Started Mar 14 01:15:35 PM PDT 24
Finished Mar 14 01:15:36 PM PDT 24
Peak memory 204116 kb
Host smart-4ceec2dd-46c5-496a-b30f-69a3b57e599e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682568590 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.2682568590
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.39523546
Short name T18
Test name
Test status
Simulation time 135603455 ps
CPU time 0.89 seconds
Started Mar 14 01:15:35 PM PDT 24
Finished Mar 14 01:15:36 PM PDT 24
Peak memory 204140 kb
Host smart-df9f00b3-7298-4e41-b7e9-d68f1ae0d207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39523546 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.39523546
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.2675902849
Short name T192
Test name
Test status
Simulation time 178996575 ps
CPU time 0.81 seconds
Started Mar 14 01:15:33 PM PDT 24
Finished Mar 14 01:15:34 PM PDT 24
Peak memory 204148 kb
Host smart-38f4d303-6289-45ef-ac9d-1530cb8dbcf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675902849 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.2675902849
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.553238490
Short name T2
Test name
Test status
Simulation time 357149316 ps
CPU time 1.23 seconds
Started Mar 14 01:15:36 PM PDT 24
Finished Mar 14 01:15:37 PM PDT 24
Peak memory 204076 kb
Host smart-6b89e184-d74e-4be4-82b7-0f0820842c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553238490 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.553238490
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.1076950649
Short name T44
Test name
Test status
Simulation time 73273053 ps
CPU time 0.74 seconds
Started Mar 14 01:15:31 PM PDT 24
Finished Mar 14 01:15:32 PM PDT 24
Peak memory 204144 kb
Host smart-098f9afe-ab89-4eb2-8dbd-59c4ded9cf2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076950649 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.1076950649
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.1930340030
Short name T71
Test name
Test status
Simulation time 201182399 ps
CPU time 0.83 seconds
Started Mar 14 01:15:35 PM PDT 24
Finished Mar 14 01:15:36 PM PDT 24
Peak memory 204228 kb
Host smart-27383e6b-f7b3-4b8b-8d0e-7ad4aa9d2f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930340030 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.1930340030
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.1094678813
Short name T72
Test name
Test status
Simulation time 2001058489 ps
CPU time 1.17 seconds
Started Mar 14 01:15:33 PM PDT 24
Finished Mar 14 01:15:34 PM PDT 24
Peak memory 204352 kb
Host smart-fae988b2-bd5b-43c7-bb45-dedc1a272349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094678813 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.1094678813
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.2054678642
Short name T200
Test name
Test status
Simulation time 597625684 ps
CPU time 1.31 seconds
Started Mar 14 01:15:35 PM PDT 24
Finished Mar 14 01:15:36 PM PDT 24
Peak memory 204404 kb
Host smart-e756f2d1-7221-4c57-b272-756115c5741e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054678642 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.2054678642
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.2593126090
Short name T216
Test name
Test status
Simulation time 1826738551 ps
CPU time 7.55 seconds
Started Mar 14 01:15:39 PM PDT 24
Finished Mar 14 01:15:46 PM PDT 24
Peak memory 204636 kb
Host smart-d71b2cda-a883-4304-ae23-95152e0d7a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593126090 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.2593126090
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.3115364500
Short name T221
Test name
Test status
Simulation time 522607265 ps
CPU time 1.51 seconds
Started Mar 14 01:15:33 PM PDT 24
Finished Mar 14 01:15:34 PM PDT 24
Peak memory 204308 kb
Host smart-78087187-d73d-4dbd-8130-02e66e982466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115364500 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.3115364500
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.3607197524
Short name T170
Test name
Test status
Simulation time 31534437 ps
CPU time 0.71 seconds
Started Mar 14 01:15:44 PM PDT 24
Finished Mar 14 01:15:45 PM PDT 24
Peak memory 204288 kb
Host smart-8be99216-98ba-495c-aef7-5c52bbb6ff63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607197524 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.3607197524
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.1684175045
Short name T232
Test name
Test status
Simulation time 21422495483 ps
CPU time 41.42 seconds
Started Mar 14 01:15:37 PM PDT 24
Finished Mar 14 01:16:19 PM PDT 24
Peak memory 212892 kb
Host smart-d9707be3-b26e-4741-8cb8-67a44a1a1c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684175045 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.1684175045
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.2862480579
Short name T183
Test name
Test status
Simulation time 3320092323 ps
CPU time 5.24 seconds
Started Mar 14 01:15:39 PM PDT 24
Finished Mar 14 01:15:44 PM PDT 24
Peak memory 213960 kb
Host smart-15b233ed-c66f-440c-8277-83573fbd5715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862480579 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.2862480579
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.1222445377
Short name T144
Test name
Test status
Simulation time 2819437795 ps
CPU time 8.96 seconds
Started Mar 14 01:15:36 PM PDT 24
Finished Mar 14 01:15:45 PM PDT 24
Peak memory 204504 kb
Host smart-9e725ea4-2bc4-44a8-97ed-cd50fd260baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222445377 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.1222445377
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.3083775784
Short name T33
Test name
Test status
Simulation time 741401360 ps
CPU time 1.37 seconds
Started Mar 14 01:15:35 PM PDT 24
Finished Mar 14 01:15:36 PM PDT 24
Peak memory 204116 kb
Host smart-ec8040a4-620e-47c7-b732-ae792bf95566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083775784 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.3083775784
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.2859940796
Short name T28
Test name
Test status
Simulation time 161614389 ps
CPU time 1.19 seconds
Started Mar 14 01:15:37 PM PDT 24
Finished Mar 14 01:15:38 PM PDT 24
Peak memory 204148 kb
Host smart-0f2c1782-3a31-40b5-9d03-4af1c1b7daf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859940796 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.2859940796
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.2172969233
Short name T4
Test name
Test status
Simulation time 1659646138 ps
CPU time 2.79 seconds
Started Mar 14 01:15:39 PM PDT 24
Finished Mar 14 01:15:42 PM PDT 24
Peak memory 204396 kb
Host smart-629061b3-09e6-4700-8447-ff8fdbb0053c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172969233 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.2172969233
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.2621221167
Short name T24
Test name
Test status
Simulation time 265261752 ps
CPU time 0.73 seconds
Started Mar 14 01:15:42 PM PDT 24
Finished Mar 14 01:15:43 PM PDT 24
Peak memory 204228 kb
Host smart-3e7b4ffe-49ef-48ae-a5f0-681932137367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621221167 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.2621221167
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.4128807271
Short name T238
Test name
Test status
Simulation time 656547677 ps
CPU time 2.06 seconds
Started Mar 14 01:15:37 PM PDT 24
Finished Mar 14 01:15:39 PM PDT 24
Peak memory 204604 kb
Host smart-59b5324d-6de4-4da2-ab96-f379a28167be
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4128807271 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.4128807271
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.583738985
Short name T83
Test name
Test status
Simulation time 1162163401 ps
CPU time 1.4 seconds
Started Mar 14 01:15:37 PM PDT 24
Finished Mar 14 01:15:38 PM PDT 24
Peak memory 204432 kb
Host smart-dac468f4-576c-45bd-a8c4-b658e08eddbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583738985 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.583738985
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.1603337999
Short name T225
Test name
Test status
Simulation time 110717130 ps
CPU time 0.68 seconds
Started Mar 14 01:15:44 PM PDT 24
Finished Mar 14 01:15:45 PM PDT 24
Peak memory 204144 kb
Host smart-a9687664-52fe-4935-b66c-31aecd377e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603337999 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.1603337999
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.2202923382
Short name T195
Test name
Test status
Simulation time 91087285 ps
CPU time 0.77 seconds
Started Mar 14 01:15:40 PM PDT 24
Finished Mar 14 01:15:41 PM PDT 24
Peak memory 204136 kb
Host smart-0ff75e86-8aa5-4021-8b8c-fbcacd3b5642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202923382 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.2202923382
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.1596939815
Short name T17
Test name
Test status
Simulation time 747899230 ps
CPU time 1.33 seconds
Started Mar 14 01:15:40 PM PDT 24
Finished Mar 14 01:15:41 PM PDT 24
Peak memory 204352 kb
Host smart-614d9b88-d9e2-4700-bf90-15fd99d962cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596939815 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.1596939815
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.1388924407
Short name T22
Test name
Test status
Simulation time 46351213 ps
CPU time 0.82 seconds
Started Mar 14 01:15:35 PM PDT 24
Finished Mar 14 01:15:36 PM PDT 24
Peak memory 204148 kb
Host smart-a22a1dcf-a436-4641-85d9-435b1b55194f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388924407 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.1388924407
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.3873934780
Short name T7
Test name
Test status
Simulation time 174445480 ps
CPU time 0.86 seconds
Started Mar 14 01:15:35 PM PDT 24
Finished Mar 14 01:15:36 PM PDT 24
Peak memory 204116 kb
Host smart-b0aca07c-c1dc-4b7b-8b56-9788f59e36c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873934780 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.3873934780
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.1529224568
Short name T141
Test name
Test status
Simulation time 153279206 ps
CPU time 1.17 seconds
Started Mar 14 01:15:42 PM PDT 24
Finished Mar 14 01:15:44 PM PDT 24
Peak memory 204224 kb
Host smart-1dabf0ff-bcac-459f-ab64-4de4f242b8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529224568 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.1529224568
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.93202832
Short name T81
Test name
Test status
Simulation time 77969146 ps
CPU time 0.93 seconds
Started Mar 14 01:15:42 PM PDT 24
Finished Mar 14 01:15:43 PM PDT 24
Peak memory 204212 kb
Host smart-327f2c43-caf1-40c1-a3ca-6f8d57c67420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93202832 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.93202832
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.1090262292
Short name T12
Test name
Test status
Simulation time 186530542 ps
CPU time 1.08 seconds
Started Mar 14 01:15:41 PM PDT 24
Finished Mar 14 01:15:42 PM PDT 24
Peak memory 204176 kb
Host smart-2e153e0a-b92f-4d89-919e-ecd34967f451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090262292 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.1090262292
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.1651642979
Short name T35
Test name
Test status
Simulation time 69319626 ps
CPU time 0.82 seconds
Started Mar 14 01:15:45 PM PDT 24
Finished Mar 14 01:15:46 PM PDT 24
Peak memory 204228 kb
Host smart-1ab350c0-a937-4a64-8748-0242337c3bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651642979 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.1651642979
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.1602837505
Short name T29
Test name
Test status
Simulation time 22546197 ps
CPU time 0.8 seconds
Started Mar 14 01:15:42 PM PDT 24
Finished Mar 14 01:15:43 PM PDT 24
Peak memory 212500 kb
Host smart-31efe0a3-b890-4442-b79d-0e0c7bc77029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602837505 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.1602837505
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.171873403
Short name T215
Test name
Test status
Simulation time 4023488725 ps
CPU time 3.72 seconds
Started Mar 14 01:15:33 PM PDT 24
Finished Mar 14 01:15:37 PM PDT 24
Peak memory 204680 kb
Host smart-09e44d68-c084-4743-a474-f87f42e3f424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171873403 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.171873403
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.1509620078
Short name T39
Test name
Test status
Simulation time 114184674 ps
CPU time 1.07 seconds
Started Mar 14 01:15:43 PM PDT 24
Finished Mar 14 01:15:44 PM PDT 24
Peak memory 227632 kb
Host smart-c539a261-b5e8-4557-9267-884c9dfc41fe
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509620078 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.1509620078
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.1450029163
Short name T189
Test name
Test status
Simulation time 480025879 ps
CPU time 2 seconds
Started Mar 14 01:15:34 PM PDT 24
Finished Mar 14 01:15:36 PM PDT 24
Peak memory 204312 kb
Host smart-fb9a7e5c-0273-4cb7-9acb-fe30bada9648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450029163 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.1450029163
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.1328824484
Short name T164
Test name
Test status
Simulation time 22118712 ps
CPU time 0.74 seconds
Started Mar 14 01:15:53 PM PDT 24
Finished Mar 14 01:15:54 PM PDT 24
Peak memory 204224 kb
Host smart-cacc522f-4ee8-4e39-98ec-fc40e59d0424
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328824484 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.1328824484
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.643697589
Short name T193
Test name
Test status
Simulation time 15740359169 ps
CPU time 62.33 seconds
Started Mar 14 01:15:53 PM PDT 24
Finished Mar 14 01:16:55 PM PDT 24
Peak memory 212720 kb
Host smart-93ea7bea-7d3a-445b-bdfd-13d0398cc2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643697589 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.643697589
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.2357542416
Short name T223
Test name
Test status
Simulation time 6257253839 ps
CPU time 10 seconds
Started Mar 14 01:15:50 PM PDT 24
Finished Mar 14 01:16:00 PM PDT 24
Peak memory 214716 kb
Host smart-928e5b9d-35c8-4090-b410-9330ff6efc48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357542416 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.2357542416
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.3989563086
Short name T9
Test name
Test status
Simulation time 4392820121 ps
CPU time 14.72 seconds
Started Mar 14 01:15:51 PM PDT 24
Finished Mar 14 01:16:06 PM PDT 24
Peak memory 204760 kb
Host smart-96611f23-ff60-4187-96bc-2f28caaa95e8
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3989563086 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.3989563086
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.378876006
Short name T228
Test name
Test status
Simulation time 1907198465 ps
CPU time 7.6 seconds
Started Mar 14 01:15:51 PM PDT 24
Finished Mar 14 01:15:59 PM PDT 24
Peak memory 204656 kb
Host smart-fbd14360-4351-43b2-a585-8c87e2f64048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378876006 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.378876006
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.3745377410
Short name T73
Test name
Test status
Simulation time 78569532 ps
CPU time 0.74 seconds
Started Mar 14 01:15:54 PM PDT 24
Finished Mar 14 01:15:54 PM PDT 24
Peak memory 204228 kb
Host smart-0c417d6c-eeab-4b5a-900d-ad3f2fe4f6e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745377410 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.3745377410
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.2740298394
Short name T94
Test name
Test status
Simulation time 2878521381 ps
CPU time 2.94 seconds
Started Mar 14 01:15:53 PM PDT 24
Finished Mar 14 01:15:56 PM PDT 24
Peak memory 204632 kb
Host smart-0ac402c1-43bc-4f1b-b1a6-5aed837b7cfa
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2740298394 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_
tl_access.2740298394
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.4240375056
Short name T145
Test name
Test status
Simulation time 38227097 ps
CPU time 0.75 seconds
Started Mar 14 01:16:03 PM PDT 24
Finished Mar 14 01:16:05 PM PDT 24
Peak memory 204292 kb
Host smart-b510613b-df41-4dd5-ab46-a5f9b24f18fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240375056 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.4240375056
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.4056860034
Short name T11
Test name
Test status
Simulation time 2647978184 ps
CPU time 10.16 seconds
Started Mar 14 01:15:53 PM PDT 24
Finished Mar 14 01:16:03 PM PDT 24
Peak memory 214016 kb
Host smart-f380a865-829c-424f-94fd-0a1b568212b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056860034 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.4056860034
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.2776585578
Short name T194
Test name
Test status
Simulation time 1932982540 ps
CPU time 8.8 seconds
Started Mar 14 01:15:53 PM PDT 24
Finished Mar 14 01:16:02 PM PDT 24
Peak memory 204584 kb
Host smart-8ed9b97d-23f5-49c4-b220-5d11f2114849
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2776585578 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.2776585578
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.1355586118
Short name T74
Test name
Test status
Simulation time 3222218201 ps
CPU time 3.01 seconds
Started Mar 14 01:15:55 PM PDT 24
Finished Mar 14 01:15:58 PM PDT 24
Peak memory 204704 kb
Host smart-e6400df7-b9c4-445e-a6d5-3f3ed1de1ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355586118 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.1355586118
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.2101803877
Short name T166
Test name
Test status
Simulation time 56751696 ps
CPU time 0.7 seconds
Started Mar 14 01:15:54 PM PDT 24
Finished Mar 14 01:15:55 PM PDT 24
Peak memory 204292 kb
Host smart-fb490093-d1ae-4f18-8889-169b185a2a24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101803877 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.2101803877
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.1321209520
Short name T190
Test name
Test status
Simulation time 11579723962 ps
CPU time 13.35 seconds
Started Mar 14 01:15:53 PM PDT 24
Finished Mar 14 01:16:06 PM PDT 24
Peak memory 212828 kb
Host smart-28858f81-1cc0-4f13-8273-6dd1bb71d8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321209520 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.1321209520
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.2800366964
Short name T217
Test name
Test status
Simulation time 811144618 ps
CPU time 2.55 seconds
Started Mar 14 01:16:03 PM PDT 24
Finished Mar 14 01:16:07 PM PDT 24
Peak memory 204592 kb
Host smart-e6b637dc-4442-4b14-ac2e-15da33191e55
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2800366964 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_
tl_access.2800366964
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.2108595975
Short name T220
Test name
Test status
Simulation time 5403629636 ps
CPU time 12.06 seconds
Started Mar 14 01:16:03 PM PDT 24
Finished Mar 14 01:16:17 PM PDT 24
Peak memory 204632 kb
Host smart-96592c75-fb92-4c4f-a2a8-275bf2f20ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108595975 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.2108595975
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_stress_all.2238085840
Short name T23
Test name
Test status
Simulation time 5271425512 ps
CPU time 6.19 seconds
Started Mar 14 01:15:53 PM PDT 24
Finished Mar 14 01:15:59 PM PDT 24
Peak memory 204424 kb
Host smart-9e2d707b-de1e-4ea2-9954-c6e359cd1329
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238085840 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.2238085840
Directory /workspace/13.rv_dm_stress_all/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.2681263292
Short name T155
Test name
Test status
Simulation time 22306775 ps
CPU time 0.69 seconds
Started Mar 14 01:15:47 PM PDT 24
Finished Mar 14 01:15:48 PM PDT 24
Peak memory 204296 kb
Host smart-2e75acbd-5271-4be9-9894-469f5ead630c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681263292 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.2681263292
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.680232950
Short name T204
Test name
Test status
Simulation time 1552886373 ps
CPU time 2.52 seconds
Started Mar 14 01:15:49 PM PDT 24
Finished Mar 14 01:15:51 PM PDT 24
Peak memory 204596 kb
Host smart-0f0b0157-e995-41a2-b8d7-ac8bc63861a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680232950 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.680232950
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.2730213679
Short name T212
Test name
Test status
Simulation time 2832008595 ps
CPU time 4.77 seconds
Started Mar 14 01:15:51 PM PDT 24
Finished Mar 14 01:15:56 PM PDT 24
Peak memory 204676 kb
Host smart-d9e9ad0c-ada3-439e-9fbf-64135493b44a
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2730213679 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.2730213679
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.1437665022
Short name T209
Test name
Test status
Simulation time 7402505893 ps
CPU time 8.98 seconds
Started Mar 14 01:15:55 PM PDT 24
Finished Mar 14 01:16:04 PM PDT 24
Peak memory 204784 kb
Host smart-9bc2e555-68e5-495d-a405-acec7ad627df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437665022 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.1437665022
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.2818919196
Short name T21
Test name
Test status
Simulation time 15930319093 ps
CPU time 35.56 seconds
Started Mar 14 01:16:22 PM PDT 24
Finished Mar 14 01:16:57 PM PDT 24
Peak memory 212880 kb
Host smart-3d2c40ec-f83b-48d2-9a32-ddec51144369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818919196 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.2818919196
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.29595453
Short name T202
Test name
Test status
Simulation time 2994218636 ps
CPU time 11.41 seconds
Started Mar 14 01:16:01 PM PDT 24
Finished Mar 14 01:16:13 PM PDT 24
Peak memory 204692 kb
Host smart-a154b770-1bb7-4e1a-b2a8-4ad07f5aa075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29595453 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.29595453
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.714258052
Short name T239
Test name
Test status
Simulation time 6050771425 ps
CPU time 6.25 seconds
Started Mar 14 01:15:59 PM PDT 24
Finished Mar 14 01:16:06 PM PDT 24
Peak memory 213888 kb
Host smart-51684fa9-2e82-445f-a846-9c086ebbaa3b
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=714258052 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_t
l_access.714258052
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.342873728
Short name T201
Test name
Test status
Simulation time 850115126 ps
CPU time 2.54 seconds
Started Mar 14 01:15:51 PM PDT 24
Finished Mar 14 01:15:53 PM PDT 24
Peak memory 204640 kb
Host smart-bfe88e26-2590-4f89-8873-d09a0b5a66b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342873728 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.342873728
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_stress_all.2633098861
Short name T138
Test name
Test status
Simulation time 7402097714 ps
CPU time 7.3 seconds
Started Mar 14 01:16:08 PM PDT 24
Finished Mar 14 01:16:15 PM PDT 24
Peak memory 204392 kb
Host smart-6a2cf428-51e2-495c-a09c-d50ec812e11f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633098861 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.2633098861
Directory /workspace/15.rv_dm_stress_all/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.382596944
Short name T171
Test name
Test status
Simulation time 33749264 ps
CPU time 0.7 seconds
Started Mar 14 01:16:06 PM PDT 24
Finished Mar 14 01:16:07 PM PDT 24
Peak memory 204288 kb
Host smart-8b16c08f-7a94-4e6d-8d27-9739a0e1bed5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382596944 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.382596944
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.2223202511
Short name T219
Test name
Test status
Simulation time 2363484831 ps
CPU time 6.39 seconds
Started Mar 14 01:16:02 PM PDT 24
Finished Mar 14 01:16:10 PM PDT 24
Peak memory 204644 kb
Host smart-f1df7b1e-5533-4084-a2ad-acb45e937cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223202511 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.2223202511
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.1939743025
Short name T211
Test name
Test status
Simulation time 6981938390 ps
CPU time 12.2 seconds
Started Mar 14 01:15:57 PM PDT 24
Finished Mar 14 01:16:10 PM PDT 24
Peak memory 204672 kb
Host smart-e0ca9374-7035-46db-a9e0-4822807db654
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1939743025 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_
tl_access.1939743025
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.1868171144
Short name T231
Test name
Test status
Simulation time 10028039283 ps
CPU time 20.04 seconds
Started Mar 14 01:16:01 PM PDT 24
Finished Mar 14 01:16:22 PM PDT 24
Peak memory 213900 kb
Host smart-8fd8f672-b8ba-46ea-a885-64c1a24d8ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868171144 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.1868171144
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.754990451
Short name T175
Test name
Test status
Simulation time 53233189 ps
CPU time 0.69 seconds
Started Mar 14 01:16:01 PM PDT 24
Finished Mar 14 01:16:03 PM PDT 24
Peak memory 204288 kb
Host smart-991c819e-cb8b-493b-b631-c47a6a696aad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754990451 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.754990451
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.4239277150
Short name T191
Test name
Test status
Simulation time 14551831344 ps
CPU time 14.09 seconds
Started Mar 14 01:16:00 PM PDT 24
Finished Mar 14 01:16:14 PM PDT 24
Peak memory 212908 kb
Host smart-337d31fe-cd5e-4608-9428-9b0481654695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239277150 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.4239277150
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.150306531
Short name T3
Test name
Test status
Simulation time 9570545443 ps
CPU time 17.06 seconds
Started Mar 14 01:16:16 PM PDT 24
Finished Mar 14 01:16:34 PM PDT 24
Peak memory 212872 kb
Host smart-a365e120-8d36-4c84-b135-210fbe50363d
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=150306531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_t
l_access.150306531
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.4199378752
Short name T59
Test name
Test status
Simulation time 734281692 ps
CPU time 2.67 seconds
Started Mar 14 01:16:03 PM PDT 24
Finished Mar 14 01:16:07 PM PDT 24
Peak memory 204620 kb
Host smart-f25d0ad4-acbd-4293-83e7-91bbff0b6142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199378752 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.4199378752
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.3216883940
Short name T169
Test name
Test status
Simulation time 40157162 ps
CPU time 0.67 seconds
Started Mar 14 01:16:06 PM PDT 24
Finished Mar 14 01:16:07 PM PDT 24
Peak memory 204256 kb
Host smart-bd60f04f-a49b-4ec9-a8f0-992193ac045b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216883940 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.3216883940
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.2481789746
Short name T227
Test name
Test status
Simulation time 3895314911 ps
CPU time 5.8 seconds
Started Mar 14 01:16:01 PM PDT 24
Finished Mar 14 01:16:07 PM PDT 24
Peak memory 204720 kb
Host smart-f6c5f2b7-72d1-48cc-adc7-d0956b064ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481789746 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.2481789746
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.1407605102
Short name T186
Test name
Test status
Simulation time 1885355991 ps
CPU time 7.49 seconds
Started Mar 14 01:15:59 PM PDT 24
Finished Mar 14 01:16:07 PM PDT 24
Peak memory 204660 kb
Host smart-49e7512e-d540-4730-8555-0cd22a8ebdb6
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1407605102 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_
tl_access.1407605102
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.3989143957
Short name T187
Test name
Test status
Simulation time 3680410009 ps
CPU time 7.02 seconds
Started Mar 14 01:16:22 PM PDT 24
Finished Mar 14 01:16:29 PM PDT 24
Peak memory 204800 kb
Host smart-ed414252-a0d7-4182-a27e-a0fb023df683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989143957 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.3989143957
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.1001268545
Short name T152
Test name
Test status
Simulation time 15830774 ps
CPU time 0.72 seconds
Started Mar 14 01:16:14 PM PDT 24
Finished Mar 14 01:16:15 PM PDT 24
Peak memory 204280 kb
Host smart-e9395443-9d3c-4107-9724-fe40ec7c7460
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001268545 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.1001268545
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.229294100
Short name T93
Test name
Test status
Simulation time 1819481417 ps
CPU time 5.98 seconds
Started Mar 14 01:16:13 PM PDT 24
Finished Mar 14 01:16:19 PM PDT 24
Peak memory 204648 kb
Host smart-e9ce3220-5845-4b20-a4b9-3c3c664c1bca
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=229294100 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_t
l_access.229294100
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.2573249484
Short name T237
Test name
Test status
Simulation time 1248819568 ps
CPU time 7.52 seconds
Started Mar 14 01:15:59 PM PDT 24
Finished Mar 14 01:16:06 PM PDT 24
Peak memory 204632 kb
Host smart-41b25b28-0267-42ee-8d28-ccdf5579db36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573249484 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.2573249484
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.3371325507
Short name T236
Test name
Test status
Simulation time 50243726 ps
CPU time 0.72 seconds
Started Mar 14 01:15:43 PM PDT 24
Finished Mar 14 01:15:44 PM PDT 24
Peak memory 204304 kb
Host smart-d36a2f7c-2146-4bf1-8a51-46abed08ffc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371325507 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.3371325507
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.799792662
Short name T198
Test name
Test status
Simulation time 11371851133 ps
CPU time 22.33 seconds
Started Mar 14 01:15:46 PM PDT 24
Finished Mar 14 01:16:08 PM PDT 24
Peak memory 204676 kb
Host smart-9b3ea4e5-4725-4842-a681-ed7242e30b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799792662 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.799792662
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.3238344459
Short name T188
Test name
Test status
Simulation time 1604374870 ps
CPU time 7.35 seconds
Started Mar 14 01:15:46 PM PDT 24
Finished Mar 14 01:15:53 PM PDT 24
Peak memory 204620 kb
Host smart-d5c341d9-481b-48e0-912c-2b0172e910a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238344459 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.3238344459
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.918972213
Short name T213
Test name
Test status
Simulation time 2182699561 ps
CPU time 10.88 seconds
Started Mar 14 01:15:44 PM PDT 24
Finished Mar 14 01:15:55 PM PDT 24
Peak memory 204760 kb
Host smart-67d65476-fc4e-492a-80e9-e47d207b987f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=918972213 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_tl
_access.918972213
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.3519882642
Short name T181
Test name
Test status
Simulation time 93250991 ps
CPU time 0.93 seconds
Started Mar 14 01:15:45 PM PDT 24
Finished Mar 14 01:15:46 PM PDT 24
Peak memory 204140 kb
Host smart-03fd1442-c8ef-4cea-b539-2a0d4c20c31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519882642 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.3519882642
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.3890106832
Short name T205
Test name
Test status
Simulation time 6488228805 ps
CPU time 22.35 seconds
Started Mar 14 01:15:44 PM PDT 24
Finished Mar 14 01:16:06 PM PDT 24
Peak memory 213860 kb
Host smart-735bb3bd-d681-41ac-aa3a-e6c0e23df5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890106832 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.3890106832
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.1120663605
Short name T55
Test name
Test status
Simulation time 283872938 ps
CPU time 1.16 seconds
Started Mar 14 01:15:41 PM PDT 24
Finished Mar 14 01:15:42 PM PDT 24
Peak memory 228232 kb
Host smart-98b650bf-d976-43fc-ad4c-a4f8148edaf6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120663605 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.1120663605
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all.2555163660
Short name T5
Test name
Test status
Simulation time 6096821853 ps
CPU time 11.12 seconds
Started Mar 14 01:15:28 PM PDT 24
Finished Mar 14 01:15:39 PM PDT 24
Peak memory 212664 kb
Host smart-6285821b-a6ee-4a90-a549-49a90d05e0cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555163660 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.2555163660
Directory /workspace/2.rv_dm_stress_all/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.3900962727
Short name T56
Test name
Test status
Simulation time 19146796 ps
CPU time 0.72 seconds
Started Mar 14 01:16:00 PM PDT 24
Finished Mar 14 01:16:00 PM PDT 24
Peak memory 204276 kb
Host smart-0e1d80cb-90fe-4f10-b15c-bb0e339a114d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900962727 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.3900962727
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.3375117556
Short name T233
Test name
Test status
Simulation time 48241181 ps
CPU time 0.69 seconds
Started Mar 14 01:16:13 PM PDT 24
Finished Mar 14 01:16:14 PM PDT 24
Peak memory 204288 kb
Host smart-b01158cb-501d-4bc0-9f1e-0998ba16ec7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375117556 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.3375117556
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_stress_all.788832583
Short name T143
Test name
Test status
Simulation time 2373938258 ps
CPU time 7.3 seconds
Started Mar 14 01:16:01 PM PDT 24
Finished Mar 14 01:16:09 PM PDT 24
Peak memory 204476 kb
Host smart-0d870f32-fbd7-40f1-ac1b-06a5610e7bd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788832583 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.788832583
Directory /workspace/21.rv_dm_stress_all/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.857090361
Short name T158
Test name
Test status
Simulation time 53529638 ps
CPU time 0.67 seconds
Started Mar 14 01:16:02 PM PDT 24
Finished Mar 14 01:16:03 PM PDT 24
Peak memory 204296 kb
Host smart-5cf39640-8bee-4488-82f0-0f1d50a4c1c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857090361 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.857090361
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.2271676157
Short name T160
Test name
Test status
Simulation time 43919078 ps
CPU time 0.73 seconds
Started Mar 14 01:16:01 PM PDT 24
Finished Mar 14 01:16:04 PM PDT 24
Peak memory 204180 kb
Host smart-61778078-dcea-48cd-8c77-7b873fa90c1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271676157 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.2271676157
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_stress_all.2633211140
Short name T80
Test name
Test status
Simulation time 1477680546 ps
CPU time 4.39 seconds
Started Mar 14 01:16:13 PM PDT 24
Finished Mar 14 01:16:18 PM PDT 24
Peak memory 204408 kb
Host smart-30ebabbd-a2d7-4e17-bf66-858cd446a26d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633211140 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.2633211140
Directory /workspace/23.rv_dm_stress_all/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.4217592415
Short name T154
Test name
Test status
Simulation time 44096800 ps
CPU time 0.73 seconds
Started Mar 14 01:16:14 PM PDT 24
Finished Mar 14 01:16:14 PM PDT 24
Peak memory 204296 kb
Host smart-534fdc30-ad95-4635-96b0-d99b533792d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217592415 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.4217592415
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.3992947871
Short name T172
Test name
Test status
Simulation time 43605444 ps
CPU time 0.73 seconds
Started Mar 14 01:16:17 PM PDT 24
Finished Mar 14 01:16:19 PM PDT 24
Peak memory 204252 kb
Host smart-97f7a554-29ec-455a-b408-ddedb9cb2558
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992947871 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.3992947871
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.2330126126
Short name T60
Test name
Test status
Simulation time 45937540 ps
CPU time 0.7 seconds
Started Mar 14 01:16:14 PM PDT 24
Finished Mar 14 01:16:15 PM PDT 24
Peak memory 204280 kb
Host smart-9558f275-db97-4916-9c55-a81985ca71e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330126126 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.2330126126
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.3444292162
Short name T57
Test name
Test status
Simulation time 17919152 ps
CPU time 0.74 seconds
Started Mar 14 01:16:14 PM PDT 24
Finished Mar 14 01:16:15 PM PDT 24
Peak memory 204276 kb
Host smart-90269ecb-e123-4559-a34e-820c3956c271
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444292162 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.3444292162
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.2536393195
Short name T168
Test name
Test status
Simulation time 28616685 ps
CPU time 0.8 seconds
Started Mar 14 01:16:16 PM PDT 24
Finished Mar 14 01:16:17 PM PDT 24
Peak memory 204260 kb
Host smart-f7610c36-1d2a-4121-a50f-c84b3938f15c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536393195 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.2536393195
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.3341822605
Short name T148
Test name
Test status
Simulation time 60469959 ps
CPU time 0.78 seconds
Started Mar 14 01:16:16 PM PDT 24
Finished Mar 14 01:16:17 PM PDT 24
Peak memory 204292 kb
Host smart-539798af-adb0-4aa9-bb54-0815eb9ae4ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341822605 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.3341822605
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_stress_all.4049826137
Short name T82
Test name
Test status
Simulation time 1384022525 ps
CPU time 5.18 seconds
Started Mar 14 01:16:15 PM PDT 24
Finished Mar 14 01:16:21 PM PDT 24
Peak memory 204372 kb
Host smart-6edc7e4a-2fb0-4066-a765-e1158df31921
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049826137 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.4049826137
Directory /workspace/29.rv_dm_stress_all/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.103366491
Short name T174
Test name
Test status
Simulation time 27109050 ps
CPU time 0.69 seconds
Started Mar 14 01:15:46 PM PDT 24
Finished Mar 14 01:15:47 PM PDT 24
Peak memory 204292 kb
Host smart-4bb4e090-ba26-4ac3-9bef-f52c7131a99a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103366491 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.103366491
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.3911109763
Short name T121
Test name
Test status
Simulation time 12393117066 ps
CPU time 29.56 seconds
Started Mar 14 01:15:36 PM PDT 24
Finished Mar 14 01:16:05 PM PDT 24
Peak memory 212840 kb
Host smart-429fef3b-70b2-4c2d-8f19-c0663498ab48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911109763 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.3911109763
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.2176987861
Short name T224
Test name
Test status
Simulation time 1735334537 ps
CPU time 7.06 seconds
Started Mar 14 01:15:37 PM PDT 24
Finished Mar 14 01:15:44 PM PDT 24
Peak memory 204656 kb
Host smart-6ebc27c0-088a-492f-a9b7-b73341ac9ce7
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2176987861 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.2176987861
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.2824430477
Short name T8
Test name
Test status
Simulation time 275368668 ps
CPU time 0.77 seconds
Started Mar 14 01:15:35 PM PDT 24
Finished Mar 14 01:15:36 PM PDT 24
Peak memory 204128 kb
Host smart-7095743d-30a8-4cd8-a88b-7f253651076a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824430477 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.2824430477
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.4250881244
Short name T206
Test name
Test status
Simulation time 337779696 ps
CPU time 1.74 seconds
Started Mar 14 01:15:34 PM PDT 24
Finished Mar 14 01:15:36 PM PDT 24
Peak memory 204616 kb
Host smart-5f63e8d3-50e8-4a2c-a6c6-2e607b19731c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250881244 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.4250881244
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.384565640
Short name T54
Test name
Test status
Simulation time 176862917 ps
CPU time 1.43 seconds
Started Mar 14 01:15:46 PM PDT 24
Finished Mar 14 01:15:48 PM PDT 24
Peak memory 228464 kb
Host smart-bdc5557c-287a-4b97-bb5d-509410bfef26
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384565640 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.384565640
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.2410069018
Short name T165
Test name
Test status
Simulation time 20687173 ps
CPU time 0.67 seconds
Started Mar 14 01:16:18 PM PDT 24
Finished Mar 14 01:16:19 PM PDT 24
Peak memory 204268 kb
Host smart-a42bf0c6-6397-4960-bbd2-7d69d4b17807
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410069018 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.2410069018
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.3078698056
Short name T163
Test name
Test status
Simulation time 23274774 ps
CPU time 0.76 seconds
Started Mar 14 01:16:13 PM PDT 24
Finished Mar 14 01:16:14 PM PDT 24
Peak memory 204292 kb
Host smart-ed7bc338-6f27-49a6-b10d-910c74a763c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078698056 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.3078698056
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_stress_all.1798429114
Short name T64
Test name
Test status
Simulation time 792538020 ps
CPU time 3.36 seconds
Started Mar 14 01:16:14 PM PDT 24
Finished Mar 14 01:16:18 PM PDT 24
Peak memory 204384 kb
Host smart-00f6dad5-93d5-4b88-bf1a-65aaae9f00d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798429114 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.1798429114
Directory /workspace/31.rv_dm_stress_all/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.3154901666
Short name T70
Test name
Test status
Simulation time 65610440 ps
CPU time 0.71 seconds
Started Mar 14 01:16:16 PM PDT 24
Finished Mar 14 01:16:17 PM PDT 24
Peak memory 204300 kb
Host smart-371ec097-6882-437c-b575-9ed14e00ddee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154901666 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.3154901666
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.419021261
Short name T122
Test name
Test status
Simulation time 25344727 ps
CPU time 0.71 seconds
Started Mar 14 01:16:12 PM PDT 24
Finished Mar 14 01:16:13 PM PDT 24
Peak memory 204296 kb
Host smart-98c36852-2ca7-4e2d-a760-bc29302557b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419021261 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.419021261
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.3080307579
Short name T176
Test name
Test status
Simulation time 36899885 ps
CPU time 0.67 seconds
Started Mar 14 01:16:14 PM PDT 24
Finished Mar 14 01:16:15 PM PDT 24
Peak memory 204284 kb
Host smart-5e32990c-bc38-400b-98f4-1d2ab754c7ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080307579 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.3080307579
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.2994277292
Short name T162
Test name
Test status
Simulation time 48864989 ps
CPU time 0.73 seconds
Started Mar 14 01:16:15 PM PDT 24
Finished Mar 14 01:16:17 PM PDT 24
Peak memory 204244 kb
Host smart-40b0092f-3416-41d8-a5e4-c3e772e50fc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994277292 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.2994277292
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.1275407
Short name T1
Test name
Test status
Simulation time 21704724 ps
CPU time 0.71 seconds
Started Mar 14 01:16:15 PM PDT 24
Finished Mar 14 01:16:16 PM PDT 24
Peak memory 204284 kb
Host smart-ad1dda58-f764-4a07-a5e0-c46f98411fe8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275407 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.1275407
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_stress_all.3161872577
Short name T6
Test name
Test status
Simulation time 6501228301 ps
CPU time 20.43 seconds
Started Mar 14 01:16:18 PM PDT 24
Finished Mar 14 01:16:39 PM PDT 24
Peak memory 204476 kb
Host smart-158a34e9-7d7c-42be-9d9e-0016e71cde4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161872577 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.3161872577
Directory /workspace/36.rv_dm_stress_all/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.801810966
Short name T173
Test name
Test status
Simulation time 31161913 ps
CPU time 0.77 seconds
Started Mar 14 01:16:14 PM PDT 24
Finished Mar 14 01:16:15 PM PDT 24
Peak memory 204180 kb
Host smart-8bbaad1e-0366-4a6c-b7c7-afb4d560237f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801810966 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.801810966
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.2635927615
Short name T58
Test name
Test status
Simulation time 49570745 ps
CPU time 0.76 seconds
Started Mar 14 01:16:15 PM PDT 24
Finished Mar 14 01:16:17 PM PDT 24
Peak memory 204288 kb
Host smart-51d4db72-ca26-4b1a-b597-ddadb345a298
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635927615 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.2635927615
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.2217838157
Short name T116
Test name
Test status
Simulation time 22383282 ps
CPU time 0.72 seconds
Started Mar 14 01:16:40 PM PDT 24
Finished Mar 14 01:16:42 PM PDT 24
Peak memory 204284 kb
Host smart-f80c245e-0cd3-4f96-b9c3-03eb9e555f04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217838157 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.2217838157
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_stress_all.949619874
Short name T10
Test name
Test status
Simulation time 13634346157 ps
CPU time 7.76 seconds
Started Mar 14 01:16:13 PM PDT 24
Finished Mar 14 01:16:21 PM PDT 24
Peak memory 204440 kb
Host smart-e0a10577-bddf-4eae-8444-df34529b66f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949619874 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.949619874
Directory /workspace/39.rv_dm_stress_all/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.3398777688
Short name T117
Test name
Test status
Simulation time 56178698 ps
CPU time 0.71 seconds
Started Mar 14 01:15:52 PM PDT 24
Finished Mar 14 01:15:53 PM PDT 24
Peak memory 204268 kb
Host smart-d9f23cc6-37ef-4d9d-81ce-a0e19260db1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398777688 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.3398777688
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.2142008668
Short name T120
Test name
Test status
Simulation time 31342542983 ps
CPU time 29.43 seconds
Started Mar 14 01:15:45 PM PDT 24
Finished Mar 14 01:16:15 PM PDT 24
Peak memory 212904 kb
Host smart-9c697a79-470f-49d2-8b3c-c7d4e579d1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142008668 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.2142008668
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.4212274695
Short name T235
Test name
Test status
Simulation time 1828730519 ps
CPU time 6.2 seconds
Started Mar 14 01:15:46 PM PDT 24
Finished Mar 14 01:15:52 PM PDT 24
Peak memory 204620 kb
Host smart-21a7413a-1c43-456a-afab-c05ae3ead21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212274695 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.4212274695
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.2028422428
Short name T184
Test name
Test status
Simulation time 13213368025 ps
CPU time 23.4 seconds
Started Mar 14 01:15:46 PM PDT 24
Finished Mar 14 01:16:10 PM PDT 24
Peak memory 212948 kb
Host smart-803baefc-45c9-4f0c-9541-425be350fda9
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2028422428 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.2028422428
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.711165467
Short name T19
Test name
Test status
Simulation time 118146054 ps
CPU time 0.78 seconds
Started Mar 14 01:15:47 PM PDT 24
Finished Mar 14 01:15:48 PM PDT 24
Peak memory 204120 kb
Host smart-a28614ea-d1fe-458d-b679-f9a5b580f056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711165467 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.711165467
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.3525512894
Short name T197
Test name
Test status
Simulation time 6772936946 ps
CPU time 13.37 seconds
Started Mar 14 01:15:51 PM PDT 24
Finished Mar 14 01:16:05 PM PDT 24
Peak memory 204644 kb
Host smart-95b64e1f-66e2-44fa-8113-35f6c8f0e200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525512894 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.3525512894
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.22468841
Short name T40
Test name
Test status
Simulation time 173143909 ps
CPU time 1 seconds
Started Mar 14 01:15:48 PM PDT 24
Finished Mar 14 01:15:50 PM PDT 24
Peak memory 228772 kb
Host smart-f2375392-de29-448c-a161-67cc96ae8e9d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22468841 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.22468841
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.2609655695
Short name T161
Test name
Test status
Simulation time 23741397 ps
CPU time 0.75 seconds
Started Mar 14 01:16:37 PM PDT 24
Finished Mar 14 01:16:39 PM PDT 24
Peak memory 204256 kb
Host smart-d3eddf96-98d0-49bc-b82c-055c304f0b47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609655695 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.2609655695
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.1572696508
Short name T150
Test name
Test status
Simulation time 40986614 ps
CPU time 0.71 seconds
Started Mar 14 01:16:41 PM PDT 24
Finished Mar 14 01:16:42 PM PDT 24
Peak memory 204256 kb
Host smart-38c87810-90c8-4c55-a3ae-ff4a5c704b22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572696508 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.1572696508
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.1469305732
Short name T25
Test name
Test status
Simulation time 67612330 ps
CPU time 0.74 seconds
Started Mar 14 01:16:40 PM PDT 24
Finished Mar 14 01:16:42 PM PDT 24
Peak memory 204260 kb
Host smart-b808ab37-d1f2-4388-ad99-61a449d624f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469305732 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.1469305732
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.1712118682
Short name T226
Test name
Test status
Simulation time 37768668 ps
CPU time 0.7 seconds
Started Mar 14 01:16:39 PM PDT 24
Finished Mar 14 01:16:42 PM PDT 24
Peak memory 204248 kb
Host smart-4439eafb-9c68-4f49-a8f8-89dfc5bb06ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712118682 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.1712118682
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.4244683571
Short name T53
Test name
Test status
Simulation time 18881387 ps
CPU time 0.72 seconds
Started Mar 14 01:16:47 PM PDT 24
Finished Mar 14 01:16:48 PM PDT 24
Peak memory 204212 kb
Host smart-4c0529e6-a57e-4924-9279-05a27c039879
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244683571 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.4244683571
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.3576277887
Short name T167
Test name
Test status
Simulation time 105975115 ps
CPU time 0.76 seconds
Started Mar 14 01:16:42 PM PDT 24
Finished Mar 14 01:16:44 PM PDT 24
Peak memory 204260 kb
Host smart-4e90fa20-b736-4e30-aaf6-083c85cb2038
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576277887 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.3576277887
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.182881547
Short name T156
Test name
Test status
Simulation time 41854348 ps
CPU time 0.71 seconds
Started Mar 14 01:16:43 PM PDT 24
Finished Mar 14 01:16:45 PM PDT 24
Peak memory 204284 kb
Host smart-33454310-a83c-4bce-b4a3-5a285d25d6c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182881547 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.182881547
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.3837756320
Short name T157
Test name
Test status
Simulation time 51522790 ps
CPU time 0.69 seconds
Started Mar 14 01:16:39 PM PDT 24
Finished Mar 14 01:16:42 PM PDT 24
Peak memory 204296 kb
Host smart-9f2584fd-dac5-465f-9099-7d945a016386
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837756320 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.3837756320
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.3918445805
Short name T199
Test name
Test status
Simulation time 47883928 ps
CPU time 0.73 seconds
Started Mar 14 01:16:43 PM PDT 24
Finished Mar 14 01:16:45 PM PDT 24
Peak memory 204292 kb
Host smart-da758047-6c10-47f8-bfc0-2471c6194cc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918445805 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.3918445805
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.3738498538
Short name T151
Test name
Test status
Simulation time 28932072 ps
CPU time 0.76 seconds
Started Mar 14 01:15:52 PM PDT 24
Finished Mar 14 01:15:52 PM PDT 24
Peak memory 204280 kb
Host smart-c3712201-76d0-4324-845d-9cbc6389d279
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738498538 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.3738498538
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.2293935221
Short name T203
Test name
Test status
Simulation time 5446176318 ps
CPU time 13.28 seconds
Started Mar 14 01:15:53 PM PDT 24
Finished Mar 14 01:16:07 PM PDT 24
Peak memory 204584 kb
Host smart-0ca2e0f8-a8e3-4e26-8940-cc584ce067f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293935221 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.2293935221
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.2499277093
Short name T69
Test name
Test status
Simulation time 11142774413 ps
CPU time 19.32 seconds
Started Mar 14 01:15:53 PM PDT 24
Finished Mar 14 01:16:13 PM PDT 24
Peak memory 214880 kb
Host smart-9ce34e00-3809-42b0-8521-15a7db0c08ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499277093 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.2499277093
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.2545831861
Short name T185
Test name
Test status
Simulation time 13255749335 ps
CPU time 16.27 seconds
Started Mar 14 01:15:52 PM PDT 24
Finished Mar 14 01:16:08 PM PDT 24
Peak memory 212888 kb
Host smart-9c601504-5ae2-4862-b988-3b12532bbdfc
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2545831861 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t
l_access.2545831861
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.3470004897
Short name T182
Test name
Test status
Simulation time 839361244 ps
CPU time 3.52 seconds
Started Mar 14 01:15:46 PM PDT 24
Finished Mar 14 01:15:50 PM PDT 24
Peak memory 204620 kb
Host smart-b9395372-3751-4247-9ad7-42e432b429c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470004897 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.3470004897
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.3958299973
Short name T147
Test name
Test status
Simulation time 15003677 ps
CPU time 0.73 seconds
Started Mar 14 01:15:53 PM PDT 24
Finished Mar 14 01:15:54 PM PDT 24
Peak memory 204256 kb
Host smart-a912e914-1729-4d0b-bc59-922f54f77539
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958299973 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.3958299973
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.3052020725
Short name T20
Test name
Test status
Simulation time 26535267446 ps
CPU time 79.62 seconds
Started Mar 14 01:15:51 PM PDT 24
Finished Mar 14 01:17:11 PM PDT 24
Peak memory 212848 kb
Host smart-03dd35cc-6781-40b5-aaa5-a0f86c13e66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052020725 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.3052020725
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.2467757032
Short name T218
Test name
Test status
Simulation time 5802288187 ps
CPU time 23.87 seconds
Started Mar 14 01:15:51 PM PDT 24
Finished Mar 14 01:16:15 PM PDT 24
Peak memory 214844 kb
Host smart-f72b2551-47c8-4191-a02a-18a1e297cc65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467757032 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.2467757032
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.1139026826
Short name T61
Test name
Test status
Simulation time 4204943172 ps
CPU time 16.21 seconds
Started Mar 14 01:15:51 PM PDT 24
Finished Mar 14 01:16:07 PM PDT 24
Peak memory 204788 kb
Host smart-b1ab4c4e-e4fd-4cc4-9374-b77fccf2ecdc
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1139026826 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t
l_access.1139026826
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.3875960539
Short name T178
Test name
Test status
Simulation time 5323485186 ps
CPU time 8.5 seconds
Started Mar 14 01:15:51 PM PDT 24
Finished Mar 14 01:16:00 PM PDT 24
Peak memory 204644 kb
Host smart-e2bf329e-f12c-415f-85c3-782716f3bf8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875960539 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.3875960539
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.3231380975
Short name T153
Test name
Test status
Simulation time 22106184 ps
CPU time 0.72 seconds
Started Mar 14 01:15:46 PM PDT 24
Finished Mar 14 01:15:47 PM PDT 24
Peak memory 204508 kb
Host smart-7a2cd82a-6835-461b-99a7-d9f4e639777f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231380975 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.3231380975
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.3893855950
Short name T196
Test name
Test status
Simulation time 18395907795 ps
CPU time 34.81 seconds
Started Mar 14 01:15:52 PM PDT 24
Finished Mar 14 01:16:27 PM PDT 24
Peak memory 212880 kb
Host smart-af015319-3296-47ad-be84-3edfc3ffeab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893855950 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.3893855950
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.1804982737
Short name T240
Test name
Test status
Simulation time 2726533616 ps
CPU time 7.18 seconds
Started Mar 14 01:15:51 PM PDT 24
Finished Mar 14 01:15:59 PM PDT 24
Peak memory 214436 kb
Host smart-d193f9fc-395f-40dc-a7e4-21397bd8bfe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804982737 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.1804982737
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.1650180804
Short name T210
Test name
Test status
Simulation time 1336611774 ps
CPU time 2.62 seconds
Started Mar 14 01:15:54 PM PDT 24
Finished Mar 14 01:15:56 PM PDT 24
Peak memory 204620 kb
Host smart-41c38bf1-81d7-45b1-ba35-71015fbb5da5
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1650180804 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.1650180804
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.1095479024
Short name T208
Test name
Test status
Simulation time 3409407035 ps
CPU time 3.44 seconds
Started Mar 14 01:15:53 PM PDT 24
Finished Mar 14 01:15:56 PM PDT 24
Peak memory 204600 kb
Host smart-0c4f78af-607b-48c6-8997-c40337b86d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095479024 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.1095479024
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_stress_all.1149593132
Short name T46
Test name
Test status
Simulation time 7884807745 ps
CPU time 7.41 seconds
Started Mar 14 01:15:54 PM PDT 24
Finished Mar 14 01:16:01 PM PDT 24
Peak memory 204464 kb
Host smart-d0b9140e-addb-46fe-9880-749a3dc0b63e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149593132 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.1149593132
Directory /workspace/7.rv_dm_stress_all/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.2751741606
Short name T207
Test name
Test status
Simulation time 22345522 ps
CPU time 0.71 seconds
Started Mar 14 01:15:51 PM PDT 24
Finished Mar 14 01:15:52 PM PDT 24
Peak memory 204256 kb
Host smart-65a87aaf-21af-4d5c-ba2d-0dfa67495d3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751741606 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.2751741606
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.1414124506
Short name T234
Test name
Test status
Simulation time 998384544 ps
CPU time 5.09 seconds
Started Mar 14 01:15:51 PM PDT 24
Finished Mar 14 01:15:56 PM PDT 24
Peak memory 204636 kb
Host smart-8622e680-f279-4b74-ab14-1e7074c2682d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414124506 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.1414124506
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.969331798
Short name T222
Test name
Test status
Simulation time 2658566795 ps
CPU time 8.65 seconds
Started Mar 14 01:15:51 PM PDT 24
Finished Mar 14 01:16:00 PM PDT 24
Peak memory 204736 kb
Host smart-9c6f4179-8f5f-467c-ad29-91a58365d9ac
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=969331798 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_tl
_access.969331798
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.2958557419
Short name T159
Test name
Test status
Simulation time 81753103 ps
CPU time 0.73 seconds
Started Mar 14 01:15:48 PM PDT 24
Finished Mar 14 01:15:49 PM PDT 24
Peak memory 204504 kb
Host smart-ce1c6319-c783-4183-b06d-c41902801508
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958557419 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.2958557419
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.1533887228
Short name T214
Test name
Test status
Simulation time 8093594147 ps
CPU time 23.76 seconds
Started Mar 14 01:15:51 PM PDT 24
Finished Mar 14 01:16:15 PM PDT 24
Peak memory 215080 kb
Host smart-af71a635-1315-4c1e-b0c7-32e227f24174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533887228 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.1533887228
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.2875911795
Short name T52
Test name
Test status
Simulation time 3186452851 ps
CPU time 6.08 seconds
Started Mar 14 01:15:48 PM PDT 24
Finished Mar 14 01:15:54 PM PDT 24
Peak memory 212804 kb
Host smart-0ce7f616-328a-44be-b4e1-16eb343f4780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875911795 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.2875911795
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.601312532
Short name T177
Test name
Test status
Simulation time 1498203803 ps
CPU time 3.37 seconds
Started Mar 14 01:15:51 PM PDT 24
Finished Mar 14 01:15:55 PM PDT 24
Peak memory 204624 kb
Host smart-cb56f722-3595-481a-a28d-a5d74b75e589
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=601312532 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_tl
_access.601312532
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.258560534
Short name T230
Test name
Test status
Simulation time 2423476250 ps
CPU time 7.05 seconds
Started Mar 14 01:15:50 PM PDT 24
Finished Mar 14 01:15:57 PM PDT 24
Peak memory 204696 kb
Host smart-dc06c85b-87dd-4239-9272-b001bc102c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258560534 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.258560534
Directory /workspace/9.rv_dm_sba_tl_access/latest
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