Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
80.42 94.49 80.32 87.69 76.92 83.83 98.52 41.19


Total test records in report: 376
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html
T106 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2165460585 Mar 17 12:58:45 PM PDT 24 Mar 17 12:58:52 PM PDT 24 578459247 ps
T270 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.3591698730 Mar 17 12:58:26 PM PDT 24 Mar 17 12:58:28 PM PDT 24 366505416 ps
T271 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1778554139 Mar 17 12:59:01 PM PDT 24 Mar 17 12:59:05 PM PDT 24 210040535 ps
T272 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.1483950948 Mar 17 12:58:24 PM PDT 24 Mar 17 12:59:00 PM PDT 24 7334252839 ps
T273 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.3998719122 Mar 17 12:58:31 PM PDT 24 Mar 17 12:58:58 PM PDT 24 2820759396 ps
T274 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.1696976684 Mar 17 12:58:59 PM PDT 24 Mar 17 12:59:00 PM PDT 24 48998748 ps
T97 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.1625208851 Mar 17 12:58:38 PM PDT 24 Mar 17 12:58:41 PM PDT 24 535059097 ps
T275 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.584859788 Mar 17 12:58:32 PM PDT 24 Mar 17 12:58:32 PM PDT 24 18956466 ps
T110 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1489885439 Mar 17 12:58:38 PM PDT 24 Mar 17 12:58:41 PM PDT 24 380393385 ps
T276 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.4144932635 Mar 17 12:58:31 PM PDT 24 Mar 17 12:58:35 PM PDT 24 283220148 ps
T277 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2362991017 Mar 17 12:58:25 PM PDT 24 Mar 17 12:58:31 PM PDT 24 4237499972 ps
T107 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.3477180487 Mar 17 12:58:24 PM PDT 24 Mar 17 12:59:28 PM PDT 24 1139356727 ps
T278 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2053399409 Mar 17 12:58:38 PM PDT 24 Mar 17 12:58:39 PM PDT 24 53754139 ps
T279 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2978600018 Mar 17 12:58:45 PM PDT 24 Mar 17 12:58:50 PM PDT 24 1090830491 ps
T280 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.585788328 Mar 17 12:58:44 PM PDT 24 Mar 17 12:58:45 PM PDT 24 54367549 ps
T281 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.4196038638 Mar 17 12:58:32 PM PDT 24 Mar 17 12:58:33 PM PDT 24 114893949 ps
T282 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.1995795382 Mar 17 12:58:44 PM PDT 24 Mar 17 12:58:46 PM PDT 24 336330423 ps
T111 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3284647258 Mar 17 12:58:26 PM PDT 24 Mar 17 12:58:29 PM PDT 24 111413110 ps
T283 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3328394047 Mar 17 12:58:31 PM PDT 24 Mar 17 12:58:36 PM PDT 24 148535635 ps
T284 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2562277092 Mar 17 12:58:31 PM PDT 24 Mar 17 12:58:35 PM PDT 24 656646529 ps
T285 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3913666953 Mar 17 12:58:50 PM PDT 24 Mar 17 12:58:53 PM PDT 24 50903441 ps
T126 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.593854454 Mar 17 12:58:26 PM PDT 24 Mar 17 12:58:45 PM PDT 24 1432038551 ps
T286 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3019448482 Mar 17 12:58:24 PM PDT 24 Mar 17 12:58:29 PM PDT 24 3779552453 ps
T287 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.4269688602 Mar 17 12:58:38 PM PDT 24 Mar 17 12:58:41 PM PDT 24 242986730 ps
T288 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2349231195 Mar 17 12:58:26 PM PDT 24 Mar 17 12:58:27 PM PDT 24 149802933 ps
T289 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.865460642 Mar 17 12:58:37 PM PDT 24 Mar 17 12:58:58 PM PDT 24 7211575728 ps
T134 /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.2454119689 Mar 17 12:58:26 PM PDT 24 Mar 17 12:58:48 PM PDT 24 20343252989 ps
T128 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.1867070808 Mar 17 12:58:37 PM PDT 24 Mar 17 12:58:57 PM PDT 24 1367196828 ps
T131 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.2090679998 Mar 17 12:58:55 PM PDT 24 Mar 17 12:59:03 PM PDT 24 252135951 ps
T290 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.2258722029 Mar 17 12:58:34 PM PDT 24 Mar 17 12:58:35 PM PDT 24 74241033 ps
T127 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1159914002 Mar 17 12:58:39 PM PDT 24 Mar 17 12:58:48 PM PDT 24 672164563 ps
T291 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.3448289021 Mar 17 12:58:48 PM PDT 24 Mar 17 12:58:49 PM PDT 24 69504255 ps
T292 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.164273931 Mar 17 12:58:47 PM PDT 24 Mar 17 12:58:48 PM PDT 24 65155098 ps
T293 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2862339231 Mar 17 12:58:57 PM PDT 24 Mar 17 12:59:01 PM PDT 24 1849254277 ps
T294 /workspace/coverage/cover_reg_top/21.rv_dm_tap_fsm_rand_reset.1368185908 Mar 17 12:59:02 PM PDT 24 Mar 17 12:59:23 PM PDT 24 5976501001 ps
T295 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.80980365 Mar 17 12:58:18 PM PDT 24 Mar 17 12:58:19 PM PDT 24 55683767 ps
T296 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.2154157254 Mar 17 12:58:31 PM PDT 24 Mar 17 12:58:47 PM PDT 24 407040623 ps
T108 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2916424714 Mar 17 12:58:25 PM PDT 24 Mar 17 12:59:40 PM PDT 24 6840082426 ps
T297 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.28835488 Mar 17 12:58:47 PM PDT 24 Mar 17 12:58:54 PM PDT 24 1571269415 ps
T112 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.971261519 Mar 17 12:58:52 PM PDT 24 Mar 17 12:58:55 PM PDT 24 584514842 ps
T298 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.1101682787 Mar 17 12:58:36 PM PDT 24 Mar 17 12:58:38 PM PDT 24 276384522 ps
T299 /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.2006238794 Mar 17 12:58:37 PM PDT 24 Mar 17 12:59:06 PM PDT 24 7989822043 ps
T300 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.2003124043 Mar 17 12:58:30 PM PDT 24 Mar 17 12:58:31 PM PDT 24 22436518 ps
T301 /workspace/coverage/cover_reg_top/11.rv_dm_tap_fsm_rand_reset.1174089176 Mar 17 12:58:47 PM PDT 24 Mar 17 12:59:13 PM PDT 24 14627308214 ps
T302 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.4231415834 Mar 17 12:58:26 PM PDT 24 Mar 17 12:59:01 PM PDT 24 2448219595 ps
T303 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.3142265059 Mar 17 12:58:38 PM PDT 24 Mar 17 12:58:40 PM PDT 24 57507912 ps
T304 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.1006168194 Mar 17 12:58:55 PM PDT 24 Mar 17 12:59:05 PM PDT 24 739488654 ps
T305 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1080269325 Mar 17 12:58:46 PM PDT 24 Mar 17 12:58:51 PM PDT 24 1284958062 ps
T306 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.1110156804 Mar 17 12:58:48 PM PDT 24 Mar 17 12:58:51 PM PDT 24 135011313 ps
T98 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.3126633102 Mar 17 12:58:17 PM PDT 24 Mar 17 12:58:23 PM PDT 24 2326253453 ps
T307 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3128804995 Mar 17 12:58:49 PM PDT 24 Mar 17 12:58:58 PM PDT 24 384375797 ps
T308 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.3213198604 Mar 17 12:58:31 PM PDT 24 Mar 17 12:58:36 PM PDT 24 3423164038 ps
T309 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1983923396 Mar 17 12:58:53 PM PDT 24 Mar 17 12:58:54 PM PDT 24 49031773 ps
T310 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.820690445 Mar 17 12:58:59 PM PDT 24 Mar 17 12:59:01 PM PDT 24 37798261 ps
T311 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3645741814 Mar 17 12:58:53 PM PDT 24 Mar 17 12:58:58 PM PDT 24 5142731070 ps
T312 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2717394815 Mar 17 12:58:43 PM PDT 24 Mar 17 12:58:52 PM PDT 24 443389625 ps
T313 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.1271445366 Mar 17 12:58:54 PM PDT 24 Mar 17 12:58:56 PM PDT 24 146547372 ps
T314 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.1290466794 Mar 17 12:58:28 PM PDT 24 Mar 17 12:58:30 PM PDT 24 109853499 ps
T315 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.3779477255 Mar 17 12:58:34 PM PDT 24 Mar 17 12:58:39 PM PDT 24 2575607194 ps
T109 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3591824603 Mar 17 12:58:44 PM PDT 24 Mar 17 12:58:51 PM PDT 24 134261810 ps
T316 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2662727623 Mar 17 12:58:56 PM PDT 24 Mar 17 12:58:56 PM PDT 24 262949158 ps
T113 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.163398120 Mar 17 12:58:48 PM PDT 24 Mar 17 12:58:49 PM PDT 24 39388510 ps
T317 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.3442118084 Mar 17 12:58:38 PM PDT 24 Mar 17 12:58:40 PM PDT 24 68223484 ps
T318 /workspace/coverage/cover_reg_top/24.rv_dm_tap_fsm_rand_reset.927523636 Mar 17 12:59:06 PM PDT 24 Mar 17 12:59:31 PM PDT 24 30044684426 ps
T319 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.1857232479 Mar 17 12:58:46 PM PDT 24 Mar 17 12:58:48 PM PDT 24 722456123 ps
T114 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.1382660624 Mar 17 12:58:49 PM PDT 24 Mar 17 12:58:50 PM PDT 24 50103516 ps
T320 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.738543801 Mar 17 12:58:37 PM PDT 24 Mar 17 12:58:41 PM PDT 24 2437456409 ps
T321 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1972998046 Mar 17 12:58:43 PM PDT 24 Mar 17 12:58:44 PM PDT 24 32952611 ps
T322 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.2198966018 Mar 17 12:58:36 PM PDT 24 Mar 17 12:58:40 PM PDT 24 1341178152 ps
T323 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2007359466 Mar 17 12:58:31 PM PDT 24 Mar 17 12:58:32 PM PDT 24 55810525 ps
T324 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.4099853205 Mar 17 12:58:24 PM PDT 24 Mar 17 12:58:26 PM PDT 24 45473462 ps
T325 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3448008095 Mar 17 12:58:50 PM PDT 24 Mar 17 12:58:53 PM PDT 24 1269010600 ps
T129 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.4116501881 Mar 17 12:58:49 PM PDT 24 Mar 17 12:59:10 PM PDT 24 4262295218 ps
T326 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.1767955901 Mar 17 12:58:27 PM PDT 24 Mar 17 12:58:30 PM PDT 24 52711686 ps
T327 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.822249725 Mar 17 12:58:32 PM PDT 24 Mar 17 12:58:34 PM PDT 24 60514073 ps
T328 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.924860956 Mar 17 12:58:24 PM PDT 24 Mar 17 12:58:26 PM PDT 24 189959841 ps
T329 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.3437039094 Mar 17 12:58:29 PM PDT 24 Mar 17 12:58:42 PM PDT 24 10283192130 ps
T330 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.2552125651 Mar 17 12:58:28 PM PDT 24 Mar 17 12:58:42 PM PDT 24 6292800472 ps
T331 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2414705797 Mar 17 12:58:46 PM PDT 24 Mar 17 12:59:03 PM PDT 24 655039401 ps
T332 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2941950098 Mar 17 12:58:24 PM PDT 24 Mar 17 12:58:27 PM PDT 24 296465082 ps
T333 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3730657510 Mar 17 12:58:41 PM PDT 24 Mar 17 12:58:49 PM PDT 24 1595372577 ps
T334 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3381432093 Mar 17 12:58:47 PM PDT 24 Mar 17 12:58:48 PM PDT 24 395877175 ps
T335 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2614866443 Mar 17 12:58:31 PM PDT 24 Mar 17 12:58:51 PM PDT 24 6754810202 ps
T336 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2967006292 Mar 17 12:58:24 PM PDT 24 Mar 17 12:58:26 PM PDT 24 489376246 ps
T337 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1511192957 Mar 17 12:58:28 PM PDT 24 Mar 17 12:58:29 PM PDT 24 14324435 ps
T338 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.3713794972 Mar 17 12:58:25 PM PDT 24 Mar 17 12:58:31 PM PDT 24 498780373 ps
T339 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.1948905136 Mar 17 12:58:48 PM PDT 24 Mar 17 12:58:52 PM PDT 24 1485272690 ps
T115 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.651925493 Mar 17 12:58:43 PM PDT 24 Mar 17 12:58:44 PM PDT 24 27244096 ps
T340 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.71692664 Mar 17 12:58:26 PM PDT 24 Mar 17 12:59:00 PM PDT 24 10260659579 ps
T341 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1765305064 Mar 17 12:59:01 PM PDT 24 Mar 17 12:59:04 PM PDT 24 342278176 ps
T342 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.3815368175 Mar 17 12:58:24 PM PDT 24 Mar 17 12:58:30 PM PDT 24 1593095341 ps
T343 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.3277412650 Mar 17 12:58:49 PM PDT 24 Mar 17 12:58:58 PM PDT 24 3005201775 ps
T344 /workspace/coverage/cover_reg_top/10.rv_dm_tap_fsm_rand_reset.940157460 Mar 17 12:58:46 PM PDT 24 Mar 17 12:59:06 PM PDT 24 5553969243 ps
T99 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.203129274 Mar 17 12:58:25 PM PDT 24 Mar 17 12:58:28 PM PDT 24 880562369 ps
T345 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.3988702074 Mar 17 12:58:49 PM PDT 24 Mar 17 12:58:55 PM PDT 24 1432161393 ps
T346 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.309227527 Mar 17 12:58:31 PM PDT 24 Mar 17 12:58:32 PM PDT 24 53484029 ps
T347 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.3059422866 Mar 17 12:58:49 PM PDT 24 Mar 17 12:58:53 PM PDT 24 247671782 ps
T348 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.4205766104 Mar 17 12:58:22 PM PDT 24 Mar 17 12:58:50 PM PDT 24 1183082107 ps
T349 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3884665885 Mar 17 12:58:39 PM PDT 24 Mar 17 12:58:44 PM PDT 24 1425171086 ps
T350 /workspace/coverage/cover_reg_top/31.rv_dm_tap_fsm_rand_reset.2575170453 Mar 17 12:59:09 PM PDT 24 Mar 17 12:59:28 PM PDT 24 5467890250 ps
T351 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.3469154968 Mar 17 12:58:49 PM PDT 24 Mar 17 12:58:51 PM PDT 24 358176935 ps
T352 /workspace/coverage/cover_reg_top/35.rv_dm_tap_fsm_rand_reset.3193718107 Mar 17 12:59:09 PM PDT 24 Mar 17 12:59:35 PM PDT 24 23818808605 ps
T353 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.968464638 Mar 17 12:58:24 PM PDT 24 Mar 17 12:58:25 PM PDT 24 291212871 ps
T354 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.673919496 Mar 17 12:58:55 PM PDT 24 Mar 17 12:58:57 PM PDT 24 394860543 ps
T355 /workspace/coverage/cover_reg_top/28.rv_dm_tap_fsm_rand_reset.1212413829 Mar 17 12:59:00 PM PDT 24 Mar 17 12:59:23 PM PDT 24 28285027358 ps
T356 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.1249136918 Mar 17 12:58:25 PM PDT 24 Mar 17 12:58:33 PM PDT 24 992046861 ps
T357 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.2615398692 Mar 17 12:58:37 PM PDT 24 Mar 17 12:58:38 PM PDT 24 31990421 ps
T358 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3573290880 Mar 17 12:58:50 PM PDT 24 Mar 17 12:58:52 PM PDT 24 482783283 ps
T359 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.164054939 Mar 17 12:58:37 PM PDT 24 Mar 17 12:58:40 PM PDT 24 295945426 ps
T360 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2916235561 Mar 17 12:58:57 PM PDT 24 Mar 17 12:59:00 PM PDT 24 859553119 ps
T361 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1548287594 Mar 17 12:59:06 PM PDT 24 Mar 17 12:59:09 PM PDT 24 2203200441 ps
T362 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.754566248 Mar 17 12:58:37 PM PDT 24 Mar 17 12:58:41 PM PDT 24 1060893361 ps
T363 /workspace/coverage/cover_reg_top/29.rv_dm_tap_fsm_rand_reset.2798475639 Mar 17 12:58:56 PM PDT 24 Mar 17 12:59:06 PM PDT 24 11010906710 ps
T364 /workspace/coverage/cover_reg_top/19.rv_dm_tap_fsm_rand_reset.4252518066 Mar 17 12:59:06 PM PDT 24 Mar 17 12:59:19 PM PDT 24 13043239731 ps
T365 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.1017416626 Mar 17 12:58:59 PM PDT 24 Mar 17 12:59:02 PM PDT 24 305458775 ps
T366 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.3339777454 Mar 17 12:58:36 PM PDT 24 Mar 17 12:58:40 PM PDT 24 119959372 ps
T367 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.67597400 Mar 17 12:58:49 PM PDT 24 Mar 17 12:58:52 PM PDT 24 196136448 ps
T368 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.3404491045 Mar 17 12:58:30 PM PDT 24 Mar 17 12:58:31 PM PDT 24 25535449 ps
T369 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3942280847 Mar 17 12:58:28 PM PDT 24 Mar 17 01:00:11 PM PDT 24 49354822453 ps
T370 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1306988795 Mar 17 12:58:42 PM PDT 24 Mar 17 12:58:45 PM PDT 24 710561084 ps
T371 /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.889748058 Mar 17 12:58:32 PM PDT 24 Mar 17 12:58:56 PM PDT 24 12518174500 ps
T372 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.1742329004 Mar 17 12:58:31 PM PDT 24 Mar 17 12:58:40 PM PDT 24 469550625 ps
T373 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.675322928 Mar 17 12:58:32 PM PDT 24 Mar 17 12:58:35 PM PDT 24 107431891 ps
T374 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1534473427 Mar 17 12:58:52 PM PDT 24 Mar 17 12:58:55 PM PDT 24 652744085 ps
T375 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.2124583647 Mar 17 12:58:37 PM PDT 24 Mar 17 12:58:38 PM PDT 24 55424573 ps
T376 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.2977990497 Mar 17 12:58:24 PM PDT 24 Mar 17 12:58:26 PM PDT 24 928261265 ps

Test location /workspace/coverage/default/14.rv_dm_stress_all.3216848443
Short name T2
Test name
Test status
Simulation time 2928731743 ps
CPU time 6.41 seconds
Started Mar 17 02:14:07 PM PDT 24
Finished Mar 17 02:14:13 PM PDT 24
Peak memory 205112 kb
Host smart-6dd9ad40-ec92-4574-8a89-1f774844f2a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216848443 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.3216848443
Directory /workspace/14.rv_dm_stress_all/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.877502562
Short name T30
Test name
Test status
Simulation time 3093465619 ps
CPU time 6.7 seconds
Started Mar 17 02:14:02 PM PDT 24
Finished Mar 17 02:14:09 PM PDT 24
Peak memory 213404 kb
Host smart-d3b30fc5-8d13-4ff8-9d85-abac3f44be31
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=877502562 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_t
l_access.877502562
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.326787015
Short name T27
Test name
Test status
Simulation time 17896768 ps
CPU time 0.74 seconds
Started Mar 17 02:14:31 PM PDT 24
Finished Mar 17 02:14:33 PM PDT 24
Peak memory 204896 kb
Host smart-fc40621a-78c7-49da-bd14-4f8230fbeb0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326787015 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.326787015
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.1787394509
Short name T32
Test name
Test status
Simulation time 2950789841 ps
CPU time 4.96 seconds
Started Mar 17 12:59:01 PM PDT 24
Finished Mar 17 12:59:06 PM PDT 24
Peak memory 218332 kb
Host smart-a8d02e0e-6d75-4a24-9e58-b6962f2523bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787394509 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.1787394509
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/49.rv_dm_stress_all.456629059
Short name T4
Test name
Test status
Simulation time 3642344984 ps
CPU time 7.27 seconds
Started Mar 17 02:14:40 PM PDT 24
Finished Mar 17 02:14:47 PM PDT 24
Peak memory 205164 kb
Host smart-c1ac5af9-feea-40c6-b014-f3768aa1f5fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456629059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.456629059
Directory /workspace/49.rv_dm_stress_all/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.3527830702
Short name T21
Test name
Test status
Simulation time 30469189804 ps
CPU time 52.26 seconds
Started Mar 17 02:13:41 PM PDT 24
Finished Mar 17 02:14:34 PM PDT 24
Peak memory 217536 kb
Host smart-957d20ae-8b62-4c2c-8227-37e0086293dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527830702 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.3527830702
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/22.rv_dm_tap_fsm_rand_reset.3398443430
Short name T64
Test name
Test status
Simulation time 24140317590 ps
CPU time 17.4 seconds
Started Mar 17 12:59:02 PM PDT 24
Finished Mar 17 12:59:20 PM PDT 24
Peak memory 221068 kb
Host smart-ee4ccdca-737d-429e-8219-25eb3b066f88
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398443430 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 22.rv_dm_tap_fsm_rand_reset.3398443430
Directory /workspace/22.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.2018788993
Short name T121
Test name
Test status
Simulation time 1046798942 ps
CPU time 19.04 seconds
Started Mar 17 12:58:53 PM PDT 24
Finished Mar 17 12:59:12 PM PDT 24
Peak memory 221036 kb
Host smart-a86fdabb-0b83-4519-98c2-b116766e735a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018788993 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.2
018788993
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2975368946
Short name T93
Test name
Test status
Simulation time 1134802653 ps
CPU time 66.35 seconds
Started Mar 17 12:58:30 PM PDT 24
Finished Mar 17 12:59:37 PM PDT 24
Peak memory 204600 kb
Host smart-6874dde1-0a2b-4a4b-99c5-e936ad13358f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975368946 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.2975368946
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.1235694839
Short name T25
Test name
Test status
Simulation time 343431100 ps
CPU time 1.42 seconds
Started Mar 17 02:13:45 PM PDT 24
Finished Mar 17 02:13:47 PM PDT 24
Peak memory 229096 kb
Host smart-1f177842-2c80-44bf-a11c-6e12597fb856
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235694839 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.1235694839
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.3846551851
Short name T54
Test name
Test status
Simulation time 21795109 ps
CPU time 0.81 seconds
Started Mar 17 02:13:40 PM PDT 24
Finished Mar 17 02:13:41 PM PDT 24
Peak memory 213100 kb
Host smart-d3bbb9b1-d55c-4d84-9893-f793303e584f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846551851 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.3846551851
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.2202788885
Short name T257
Test name
Test status
Simulation time 116735256 ps
CPU time 2.88 seconds
Started Mar 17 12:58:36 PM PDT 24
Finished Mar 17 12:58:40 PM PDT 24
Peak memory 212772 kb
Host smart-713e488c-7e12-4a53-a822-3535fd6e06c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202788885 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.2202788885
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.769457804
Short name T58
Test name
Test status
Simulation time 121048518 ps
CPU time 1.07 seconds
Started Mar 17 02:13:41 PM PDT 24
Finished Mar 17 02:13:42 PM PDT 24
Peak memory 204860 kb
Host smart-e8247b58-e3b5-4010-b0e3-4fe5cfbd4144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769457804 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.769457804
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.3528284721
Short name T5
Test name
Test status
Simulation time 2575548732 ps
CPU time 4.93 seconds
Started Mar 17 02:13:46 PM PDT 24
Finished Mar 17 02:13:52 PM PDT 24
Peak memory 205156 kb
Host smart-0cbdc18e-ce05-4936-98ae-4753bc8b1a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528284721 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.3528284721
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.3364290450
Short name T65
Test name
Test status
Simulation time 201366907 ps
CPU time 0.68 seconds
Started Mar 17 02:14:28 PM PDT 24
Finished Mar 17 02:14:29 PM PDT 24
Peak memory 204904 kb
Host smart-774b15c5-f6d3-4f94-8d05-3b21fdf65770
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364290450 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.3364290450
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.300856726
Short name T36
Test name
Test status
Simulation time 2277088267 ps
CPU time 4.61 seconds
Started Mar 17 12:58:50 PM PDT 24
Finished Mar 17 12:58:55 PM PDT 24
Peak memory 204772 kb
Host smart-8ae32987-dc09-4304-9461-66e120317b27
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300856726 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same_
csr_outstanding.300856726
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.297774600
Short name T57
Test name
Test status
Simulation time 191849374 ps
CPU time 1.12 seconds
Started Mar 17 02:13:33 PM PDT 24
Finished Mar 17 02:13:34 PM PDT 24
Peak memory 204804 kb
Host smart-bf83a990-5777-40a2-ab79-572e3fc6025b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297774600 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.297774600
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.978002321
Short name T59
Test name
Test status
Simulation time 38994419 ps
CPU time 0.74 seconds
Started Mar 17 02:13:33 PM PDT 24
Finished Mar 17 02:13:34 PM PDT 24
Peak memory 204828 kb
Host smart-1567fea6-2fd3-48ea-9468-42413a41de9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978002321 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.978002321
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.593854454
Short name T126
Test name
Test status
Simulation time 1432038551 ps
CPU time 18.37 seconds
Started Mar 17 12:58:26 PM PDT 24
Finished Mar 17 12:58:45 PM PDT 24
Peak memory 220052 kb
Host smart-8727bf6b-3bfc-4f1e-a1a2-e0d6d65686bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593854454 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.593854454
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.3766520639
Short name T41
Test name
Test status
Simulation time 7416010375 ps
CPU time 10.41 seconds
Started Mar 17 02:13:46 PM PDT 24
Finished Mar 17 02:13:56 PM PDT 24
Peak memory 213340 kb
Host smart-30f5e5e3-2822-4dae-a487-66f2f9cdb449
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3766520639 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.3766520639
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_stress_all.3247557466
Short name T8
Test name
Test status
Simulation time 1685747971 ps
CPU time 7.24 seconds
Started Mar 17 02:13:59 PM PDT 24
Finished Mar 17 02:14:06 PM PDT 24
Peak memory 205012 kb
Host smart-e2212a6f-0aab-4777-8573-604e82da757d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247557466 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.3247557466
Directory /workspace/12.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2530264465
Short name T237
Test name
Test status
Simulation time 201416497 ps
CPU time 0.82 seconds
Started Mar 17 12:58:25 PM PDT 24
Finished Mar 17 12:58:26 PM PDT 24
Peak memory 204368 kb
Host smart-ded684a0-b82d-49cb-9ad8-d8ca53cfa337
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530264465 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.2530264465
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.3126633102
Short name T98
Test name
Test status
Simulation time 2326253453 ps
CPU time 5.17 seconds
Started Mar 17 12:58:17 PM PDT 24
Finished Mar 17 12:58:23 PM PDT 24
Peak memory 204684 kb
Host smart-d7137ed3-f5bc-4fa8-889e-d813a84a144f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126633102 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.3126633102
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.4116501881
Short name T129
Test name
Test status
Simulation time 4262295218 ps
CPU time 20.61 seconds
Started Mar 17 12:58:49 PM PDT 24
Finished Mar 17 12:59:10 PM PDT 24
Peak memory 220980 kb
Host smart-b18f7244-b13a-4a88-995a-cdf2bcace12e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116501881 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.4
116501881
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.3796482999
Short name T125
Test name
Test status
Simulation time 3605737796 ps
CPU time 18.6 seconds
Started Mar 17 12:58:38 PM PDT 24
Finished Mar 17 12:58:57 PM PDT 24
Peak memory 212912 kb
Host smart-3396a3a6-9f2d-44b2-a503-e4a528d77b46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796482999 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.3796482999
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.62529225
Short name T66
Test name
Test status
Simulation time 357343735 ps
CPU time 1.01 seconds
Started Mar 17 12:58:26 PM PDT 24
Finished Mar 17 12:58:27 PM PDT 24
Peak memory 204588 kb
Host smart-3e80918e-b71f-40ba-880f-58a77408f1d7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62529225 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_
hw_reset.62529225
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.37199007
Short name T46
Test name
Test status
Simulation time 747950351 ps
CPU time 1.1 seconds
Started Mar 17 02:13:27 PM PDT 24
Finished Mar 17 02:13:28 PM PDT 24
Peak memory 204712 kb
Host smart-6acbe074-6337-464a-8ff9-d56fc548e07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37199007 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.37199007
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.2472156345
Short name T94
Test name
Test status
Simulation time 84417863 ps
CPU time 2.22 seconds
Started Mar 17 12:58:26 PM PDT 24
Finished Mar 17 12:58:29 PM PDT 24
Peak memory 212696 kb
Host smart-62492af6-90fa-4947-b719-1ff7c4a014da
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472156345 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.2472156345
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1361960679
Short name T88
Test name
Test status
Simulation time 769162532 ps
CPU time 2.23 seconds
Started Mar 17 12:58:26 PM PDT 24
Finished Mar 17 12:58:29 PM PDT 24
Peak memory 212880 kb
Host smart-4a256bde-7743-4749-a20d-a7d5986b7c8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361960679 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.1361960679
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.259003039
Short name T42
Test name
Test status
Simulation time 181229466 ps
CPU time 0.73 seconds
Started Mar 17 02:14:04 PM PDT 24
Finished Mar 17 02:14:05 PM PDT 24
Peak memory 204888 kb
Host smart-860e2423-7ca1-47c5-90b7-1974b17a8501
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259003039 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.259003039
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.2125914432
Short name T92
Test name
Test status
Simulation time 36520300084 ps
CPU time 81.19 seconds
Started Mar 17 12:58:27 PM PDT 24
Finished Mar 17 12:59:49 PM PDT 24
Peak memory 212860 kb
Host smart-d999441b-436b-4f15-a266-6c27ddc56f11
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125914432 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.2125914432
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.1483950948
Short name T272
Test name
Test status
Simulation time 7334252839 ps
CPU time 36.39 seconds
Started Mar 17 12:58:24 PM PDT 24
Finished Mar 17 12:59:00 PM PDT 24
Peak memory 204636 kb
Host smart-bb8ea292-6cf8-41e5-8abd-a69fe2c2e1a0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483950948 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.1483950948
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.2198966018
Short name T322
Test name
Test status
Simulation time 1341178152 ps
CPU time 3.15 seconds
Started Mar 17 12:58:36 PM PDT 24
Finished Mar 17 12:58:40 PM PDT 24
Peak memory 216588 kb
Host smart-bfb61035-3ab9-4d84-9624-1cf6b1a42243
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198966018 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.2198966018
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.1290466794
Short name T314
Test name
Test status
Simulation time 109853499 ps
CPU time 2.31 seconds
Started Mar 17 12:58:28 PM PDT 24
Finished Mar 17 12:58:30 PM PDT 24
Peak memory 212848 kb
Host smart-bf10f171-1898-480b-a16f-e7b8554b379e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290466794 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.1290466794
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1880474690
Short name T260
Test name
Test status
Simulation time 15779013831 ps
CPU time 16.44 seconds
Started Mar 17 12:58:22 PM PDT 24
Finished Mar 17 12:58:39 PM PDT 24
Peak memory 204608 kb
Host smart-aee2ed9b-9d42-4454-ae5d-c5e06c160098
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880474690 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.1880474690
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.4134058173
Short name T244
Test name
Test status
Simulation time 9118015122 ps
CPU time 8.99 seconds
Started Mar 17 12:58:23 PM PDT 24
Finished Mar 17 12:58:32 PM PDT 24
Peak memory 204608 kb
Host smart-4a56f585-7c75-4e6f-b5c6-4cee74395dfa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134058173 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_bit_bash.4134058173
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.1031514852
Short name T240
Test name
Test status
Simulation time 228180606 ps
CPU time 1.09 seconds
Started Mar 17 12:58:27 PM PDT 24
Finished Mar 17 12:58:28 PM PDT 24
Peak memory 204656 kb
Host smart-e8b8d057-2162-4052-8297-19e2cf127640
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031514852 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.1
031514852
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1710335578
Short name T263
Test name
Test status
Simulation time 809289701 ps
CPU time 3.95 seconds
Started Mar 17 12:58:19 PM PDT 24
Finished Mar 17 12:58:23 PM PDT 24
Peak memory 204492 kb
Host smart-62cad4f7-6003-4db1-9774-6ce75f8ae448
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710335578 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.1710335578
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.80980365
Short name T295
Test name
Test status
Simulation time 55683767 ps
CPU time 0.74 seconds
Started Mar 17 12:58:18 PM PDT 24
Finished Mar 17 12:58:19 PM PDT 24
Peak memory 204380 kb
Host smart-11d87bce-a0ea-453e-991d-32d2337d0811
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80980365 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_
hw_reset.80980365
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.2158814493
Short name T268
Test name
Test status
Simulation time 38062302 ps
CPU time 0.74 seconds
Started Mar 17 12:58:22 PM PDT 24
Finished Mar 17 12:58:23 PM PDT 24
Peak memory 204404 kb
Host smart-e983c5fe-7d7d-4efa-bf38-286967bcd53c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158814493 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.2
158814493
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1511192957
Short name T337
Test name
Test status
Simulation time 14324435 ps
CPU time 0.68 seconds
Started Mar 17 12:58:28 PM PDT 24
Finished Mar 17 12:58:29 PM PDT 24
Peak memory 204292 kb
Host smart-b0b0888b-20b1-42cb-9a98-016018cc78b0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511192957 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.1511192957
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.3404491045
Short name T368
Test name
Test status
Simulation time 25535449 ps
CPU time 0.66 seconds
Started Mar 17 12:58:30 PM PDT 24
Finished Mar 17 12:58:31 PM PDT 24
Peak memory 204420 kb
Host smart-f3327fa4-50db-45a2-9199-86ec20ebaec2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404491045 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.3404491045
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2684598105
Short name T91
Test name
Test status
Simulation time 417040416 ps
CPU time 3.99 seconds
Started Mar 17 12:58:28 PM PDT 24
Finished Mar 17 12:58:32 PM PDT 24
Peak memory 204624 kb
Host smart-563ac4cf-03c4-4073-a390-9166337fa38a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684598105 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.2684598105
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.3713794972
Short name T338
Test name
Test status
Simulation time 498780373 ps
CPU time 5.53 seconds
Started Mar 17 12:58:25 PM PDT 24
Finished Mar 17 12:58:31 PM PDT 24
Peak memory 212868 kb
Host smart-a16dfa29-2a9c-4360-9ac8-94306b655978
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713794972 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.3713794972
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.2154157254
Short name T296
Test name
Test status
Simulation time 407040623 ps
CPU time 16.35 seconds
Started Mar 17 12:58:31 PM PDT 24
Finished Mar 17 12:58:47 PM PDT 24
Peak memory 212828 kb
Host smart-d4fa3631-31b2-4fd0-ab21-f81f25672102
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154157254 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.2154157254
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.4205766104
Short name T348
Test name
Test status
Simulation time 1183082107 ps
CPU time 26.99 seconds
Started Mar 17 12:58:22 PM PDT 24
Finished Mar 17 12:58:50 PM PDT 24
Peak memory 204816 kb
Host smart-77fd2415-319f-4f2a-bb6e-4530b0630611
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205766104 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.4205766104
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.4231415834
Short name T302
Test name
Test status
Simulation time 2448219595 ps
CPU time 34.22 seconds
Started Mar 17 12:58:26 PM PDT 24
Finished Mar 17 12:59:01 PM PDT 24
Peak memory 204712 kb
Host smart-971dbf06-61cb-4807-9bac-22d3059142ee
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231415834 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.4231415834
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2941950098
Short name T332
Test name
Test status
Simulation time 296465082 ps
CPU time 2.22 seconds
Started Mar 17 12:58:24 PM PDT 24
Finished Mar 17 12:58:27 PM PDT 24
Peak memory 212876 kb
Host smart-28f4fb65-0320-4322-9730-cb0a79631d9d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941950098 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.2941950098
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3019448482
Short name T286
Test name
Test status
Simulation time 3779552453 ps
CPU time 5.02 seconds
Started Mar 17 12:58:24 PM PDT 24
Finished Mar 17 12:58:29 PM PDT 24
Peak memory 215560 kb
Host smart-404f56e8-3c35-4d4b-9b76-457d1362e2d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019448482 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.3019448482
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.924860956
Short name T328
Test name
Test status
Simulation time 189959841 ps
CPU time 1.51 seconds
Started Mar 17 12:58:24 PM PDT 24
Finished Mar 17 12:58:26 PM PDT 24
Peak memory 217792 kb
Host smart-0854e435-4a35-4ec9-8580-9616d70bafe1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924860956 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.924860956
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.3817381727
Short name T258
Test name
Test status
Simulation time 12130151057 ps
CPU time 27.09 seconds
Started Mar 17 12:58:25 PM PDT 24
Finished Mar 17 12:58:53 PM PDT 24
Peak memory 204648 kb
Host smart-23937a4d-401a-48a0-92d0-f07b27bc1f42
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817381727 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.3817381727
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3942280847
Short name T369
Test name
Test status
Simulation time 49354822453 ps
CPU time 102.63 seconds
Started Mar 17 12:58:28 PM PDT 24
Finished Mar 17 01:00:11 PM PDT 24
Peak memory 204580 kb
Host smart-28aca9c5-b528-484e-9194-f36216f83dd9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942280847 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_bit_bash.3942280847
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.203129274
Short name T99
Test name
Test status
Simulation time 880562369 ps
CPU time 3.57 seconds
Started Mar 17 12:58:25 PM PDT 24
Finished Mar 17 12:58:28 PM PDT 24
Peak memory 204604 kb
Host smart-6865a140-7a81-4ca4-9e58-eb3104faf225
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203129274 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr
_hw_reset.203129274
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2967006292
Short name T336
Test name
Test status
Simulation time 489376246 ps
CPU time 1.48 seconds
Started Mar 17 12:58:24 PM PDT 24
Finished Mar 17 12:58:26 PM PDT 24
Peak memory 204468 kb
Host smart-4b6df203-4e82-496a-883d-2a760f6b00e2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967006292 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.2
967006292
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.968464638
Short name T353
Test name
Test status
Simulation time 291212871 ps
CPU time 0.74 seconds
Started Mar 17 12:58:24 PM PDT 24
Finished Mar 17 12:58:25 PM PDT 24
Peak memory 204264 kb
Host smart-e8ceaae4-3562-430e-a8b6-6767733302a1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968464638 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_aliasing.968464638
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.3591698730
Short name T270
Test name
Test status
Simulation time 366505416 ps
CPU time 1.78 seconds
Started Mar 17 12:58:26 PM PDT 24
Finished Mar 17 12:58:28 PM PDT 24
Peak memory 204632 kb
Host smart-6efebfb7-5005-4825-9ea1-59e1df642d65
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591698730 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.3591698730
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.4099853205
Short name T324
Test name
Test status
Simulation time 45473462 ps
CPU time 0.78 seconds
Started Mar 17 12:58:24 PM PDT 24
Finished Mar 17 12:58:26 PM PDT 24
Peak memory 204372 kb
Host smart-87142bfd-358e-4475-81c0-a35cf922318b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099853205 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.4099853205
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.630854814
Short name T239
Test name
Test status
Simulation time 104207487 ps
CPU time 0.85 seconds
Started Mar 17 12:58:24 PM PDT 24
Finished Mar 17 12:58:25 PM PDT 24
Peak memory 204348 kb
Host smart-6254e749-2220-4d5e-9cc7-3b09922e6be7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630854814 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.630854814
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.416851547
Short name T262
Test name
Test status
Simulation time 13526766 ps
CPU time 0.67 seconds
Started Mar 17 12:58:27 PM PDT 24
Finished Mar 17 12:58:27 PM PDT 24
Peak memory 204344 kb
Host smart-79c3a481-8e0e-429c-a2bc-36b614bd5d85
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416851547 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_part
ial_access.416851547
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.584859788
Short name T275
Test name
Test status
Simulation time 18956466 ps
CPU time 0.68 seconds
Started Mar 17 12:58:32 PM PDT 24
Finished Mar 17 12:58:32 PM PDT 24
Peak memory 204392 kb
Host smart-a5020d1d-af73-4da2-b807-00ebf12bff2f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584859788 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.584859788
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3900852016
Short name T37
Test name
Test status
Simulation time 553796815 ps
CPU time 6.71 seconds
Started Mar 17 12:58:22 PM PDT 24
Finished Mar 17 12:58:29 PM PDT 24
Peak memory 204552 kb
Host smart-99e4d326-343a-4f26-994f-46547ce8427e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900852016 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_
csr_outstanding.3900852016
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.3815368175
Short name T342
Test name
Test status
Simulation time 1593095341 ps
CPU time 5.27 seconds
Started Mar 17 12:58:24 PM PDT 24
Finished Mar 17 12:58:30 PM PDT 24
Peak memory 212920 kb
Host smart-37ba82d4-5c06-4310-bee5-3db78539766a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815368175 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.3815368175
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.2123407156
Short name T31
Test name
Test status
Simulation time 996965987 ps
CPU time 9.68 seconds
Started Mar 17 12:58:26 PM PDT 24
Finished Mar 17 12:58:36 PM PDT 24
Peak memory 220984 kb
Host smart-39f16c88-f898-47b2-a684-c2cf0fd4c709
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123407156 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.2123407156
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3785805337
Short name T80
Test name
Test status
Simulation time 4459743180 ps
CPU time 4.47 seconds
Started Mar 17 12:58:42 PM PDT 24
Finished Mar 17 12:58:47 PM PDT 24
Peak memory 219812 kb
Host smart-d854290a-93d3-4b35-96fc-0d0640a0aa51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785805337 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.3785805337
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.1110156804
Short name T306
Test name
Test status
Simulation time 135011313 ps
CPU time 2.15 seconds
Started Mar 17 12:58:48 PM PDT 24
Finished Mar 17 12:58:51 PM PDT 24
Peak memory 217260 kb
Host smart-ab8747f4-de36-40a6-9159-ebfd0b2bf18a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110156804 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.1110156804
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3573290880
Short name T358
Test name
Test status
Simulation time 482783283 ps
CPU time 1.75 seconds
Started Mar 17 12:58:50 PM PDT 24
Finished Mar 17 12:58:52 PM PDT 24
Peak memory 204572 kb
Host smart-633f76ce-8ae8-42a5-8af3-b8db94a74bcd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573290880 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
3573290880
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1972998046
Short name T321
Test name
Test status
Simulation time 32952611 ps
CPU time 0.77 seconds
Started Mar 17 12:58:43 PM PDT 24
Finished Mar 17 12:58:44 PM PDT 24
Peak memory 204376 kb
Host smart-e6d8e048-f0b1-4e68-b8f2-bbc7251c28e1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972998046 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
1972998046
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3730657510
Short name T333
Test name
Test status
Simulation time 1595372577 ps
CPU time 7.9 seconds
Started Mar 17 12:58:41 PM PDT 24
Finished Mar 17 12:58:49 PM PDT 24
Peak memory 204600 kb
Host smart-23f48ce3-65e2-43c7-8b6d-9456f68c64d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730657510 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.3730657510
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tap_fsm_rand_reset.940157460
Short name T344
Test name
Test status
Simulation time 5553969243 ps
CPU time 19.81 seconds
Started Mar 17 12:58:46 PM PDT 24
Finished Mar 17 12:59:06 PM PDT 24
Peak memory 218364 kb
Host smart-ec3d0a1a-c1a6-47c7-960d-b28c1ca3277b
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940157460 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.rv_dm_tap_fsm_rand_reset.940157460
Directory /workspace/10.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.494950447
Short name T249
Test name
Test status
Simulation time 62790304 ps
CPU time 2.35 seconds
Started Mar 17 12:58:52 PM PDT 24
Finished Mar 17 12:58:55 PM PDT 24
Peak memory 212744 kb
Host smart-8c158136-872c-47a4-aad8-9a102b4977ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494950447 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.494950447
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2414705797
Short name T331
Test name
Test status
Simulation time 655039401 ps
CPU time 17.29 seconds
Started Mar 17 12:58:46 PM PDT 24
Finished Mar 17 12:59:03 PM PDT 24
Peak memory 221076 kb
Host smart-4a17bde0-c517-4231-bd49-0ef44db657f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414705797 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.2
414705797
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3448008095
Short name T325
Test name
Test status
Simulation time 1269010600 ps
CPU time 3.02 seconds
Started Mar 17 12:58:50 PM PDT 24
Finished Mar 17 12:58:53 PM PDT 24
Peak memory 214412 kb
Host smart-5722c11f-a2dd-44ec-9f5f-8c266862bbd5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448008095 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.3448008095
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.651925493
Short name T115
Test name
Test status
Simulation time 27244096 ps
CPU time 1.48 seconds
Started Mar 17 12:58:43 PM PDT 24
Finished Mar 17 12:58:44 PM PDT 24
Peak memory 218308 kb
Host smart-1115658a-d00e-49b1-ac79-6aceb72670d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651925493 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.651925493
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.1857232479
Short name T319
Test name
Test status
Simulation time 722456123 ps
CPU time 1.58 seconds
Started Mar 17 12:58:46 PM PDT 24
Finished Mar 17 12:58:48 PM PDT 24
Peak memory 204436 kb
Host smart-b4a10b3a-9566-4652-b35f-99459a1b80e5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857232479 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
1857232479
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.585788328
Short name T280
Test name
Test status
Simulation time 54367549 ps
CPU time 0.73 seconds
Started Mar 17 12:58:44 PM PDT 24
Finished Mar 17 12:58:45 PM PDT 24
Peak memory 204292 kb
Host smart-5faa88f4-54b0-48bc-ab95-0615ff229ca5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585788328 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.585788328
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tap_fsm_rand_reset.1174089176
Short name T301
Test name
Test status
Simulation time 14627308214 ps
CPU time 26.51 seconds
Started Mar 17 12:58:47 PM PDT 24
Finished Mar 17 12:59:13 PM PDT 24
Peak memory 221120 kb
Host smart-5a45bba1-e58c-4cbf-9ed9-e65dab752b02
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174089176 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rv_dm_tap_fsm_rand_reset.1174089176
Directory /workspace/11.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.67597400
Short name T367
Test name
Test status
Simulation time 196136448 ps
CPU time 2.84 seconds
Started Mar 17 12:58:49 PM PDT 24
Finished Mar 17 12:58:52 PM PDT 24
Peak memory 212800 kb
Host smart-6523bded-9fd5-4c48-b4a4-03d2185a4c88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67597400 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.67597400
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.2090679998
Short name T131
Test name
Test status
Simulation time 252135951 ps
CPU time 8.41 seconds
Started Mar 17 12:58:55 PM PDT 24
Finished Mar 17 12:59:03 PM PDT 24
Peak memory 212788 kb
Host smart-a4350312-9df4-4122-b3ac-f8e37f5cc9ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090679998 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.2
090679998
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.3277412650
Short name T343
Test name
Test status
Simulation time 3005201775 ps
CPU time 8.31 seconds
Started Mar 17 12:58:49 PM PDT 24
Finished Mar 17 12:58:58 PM PDT 24
Peak memory 220504 kb
Host smart-04a36153-4526-4d4c-abbb-65f8b16acbc9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277412650 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.3277412650
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.142093490
Short name T100
Test name
Test status
Simulation time 257959202 ps
CPU time 1.53 seconds
Started Mar 17 12:58:50 PM PDT 24
Finished Mar 17 12:58:51 PM PDT 24
Peak memory 212816 kb
Host smart-cc77b5f9-23cf-4de7-bc15-cd2c4fdc6d9e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142093490 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.142093490
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1534473427
Short name T374
Test name
Test status
Simulation time 652744085 ps
CPU time 2.72 seconds
Started Mar 17 12:58:52 PM PDT 24
Finished Mar 17 12:58:55 PM PDT 24
Peak memory 204492 kb
Host smart-1bfe92fb-49f5-4473-8e88-ae1b41264cf5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534473427 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
1534473427
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.745747865
Short name T235
Test name
Test status
Simulation time 50924735 ps
CPU time 0.65 seconds
Started Mar 17 12:58:58 PM PDT 24
Finished Mar 17 12:58:58 PM PDT 24
Peak memory 204288 kb
Host smart-dfb93dcf-2071-4e3c-8a05-d57642aa488a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745747865 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.745747865
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.201163109
Short name T116
Test name
Test status
Simulation time 364746726 ps
CPU time 4.2 seconds
Started Mar 17 12:58:47 PM PDT 24
Finished Mar 17 12:58:52 PM PDT 24
Peak memory 204620 kb
Host smart-3419270b-942c-4ff8-923f-ac457b1731da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201163109 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same_
csr_outstanding.201163109
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.1497982096
Short name T242
Test name
Test status
Simulation time 204151072 ps
CPU time 2.75 seconds
Started Mar 17 12:58:50 PM PDT 24
Finished Mar 17 12:58:52 PM PDT 24
Peak memory 212756 kb
Host smart-009304e2-bcac-4e7a-9be5-652cb7b6af94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497982096 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.1497982096
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3128804995
Short name T307
Test name
Test status
Simulation time 384375797 ps
CPU time 8.16 seconds
Started Mar 17 12:58:49 PM PDT 24
Finished Mar 17 12:58:58 PM PDT 24
Peak memory 220848 kb
Host smart-a9f769bb-19bc-4ad5-a21b-7c64a369c6fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128804995 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.3
128804995
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.2895840646
Short name T243
Test name
Test status
Simulation time 4690689988 ps
CPU time 6.35 seconds
Started Mar 17 12:58:45 PM PDT 24
Finished Mar 17 12:58:52 PM PDT 24
Peak memory 218296 kb
Host smart-1849bfa9-fa56-4d09-afa3-23a373fae5b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895840646 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.2895840646
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.163398120
Short name T113
Test name
Test status
Simulation time 39388510 ps
CPU time 1.44 seconds
Started Mar 17 12:58:48 PM PDT 24
Finished Mar 17 12:58:49 PM PDT 24
Peak memory 212728 kb
Host smart-b6cde1b5-4d54-4165-b0a9-98d88dd47b2d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163398120 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.163398120
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.1995795382
Short name T282
Test name
Test status
Simulation time 336330423 ps
CPU time 1.35 seconds
Started Mar 17 12:58:44 PM PDT 24
Finished Mar 17 12:58:46 PM PDT 24
Peak memory 204580 kb
Host smart-187bf5c5-fc95-4dbe-bfff-f9910d66ce32
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995795382 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
1995795382
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.4192975458
Short name T69
Test name
Test status
Simulation time 129782497 ps
CPU time 0.8 seconds
Started Mar 17 12:58:50 PM PDT 24
Finished Mar 17 12:58:51 PM PDT 24
Peak memory 204308 kb
Host smart-40b5f577-039c-44df-9bf5-01d291df4513
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192975458 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
4192975458
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2978600018
Short name T279
Test name
Test status
Simulation time 1090830491 ps
CPU time 4.55 seconds
Started Mar 17 12:58:45 PM PDT 24
Finished Mar 17 12:58:50 PM PDT 24
Peak memory 204604 kb
Host smart-a37fdd6b-79ae-4c80-aece-85960e91ebe4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978600018 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.2978600018
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.1948905136
Short name T339
Test name
Test status
Simulation time 1485272690 ps
CPU time 4.01 seconds
Started Mar 17 12:58:48 PM PDT 24
Finished Mar 17 12:58:52 PM PDT 24
Peak memory 212860 kb
Host smart-c644bce0-f9f0-4d20-91d6-c4769247d3aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948905136 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.1948905136
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3645741814
Short name T311
Test name
Test status
Simulation time 5142731070 ps
CPU time 4.86 seconds
Started Mar 17 12:58:53 PM PDT 24
Finished Mar 17 12:58:58 PM PDT 24
Peak memory 217464 kb
Host smart-ae0d13af-b3ef-41e7-a412-c6bfa18d061a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645741814 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.3645741814
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.1382660624
Short name T114
Test name
Test status
Simulation time 50103516 ps
CPU time 1.57 seconds
Started Mar 17 12:58:49 PM PDT 24
Finished Mar 17 12:58:50 PM PDT 24
Peak memory 218148 kb
Host smart-bb6efbf7-a69d-4e21-9c86-66ef84fd15f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382660624 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.1382660624
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1306988795
Short name T370
Test name
Test status
Simulation time 710561084 ps
CPU time 2.92 seconds
Started Mar 17 12:58:42 PM PDT 24
Finished Mar 17 12:58:45 PM PDT 24
Peak memory 204548 kb
Host smart-834081d4-4c3c-40e6-be1e-d9a23ea9d663
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306988795 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
1306988795
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.3448289021
Short name T291
Test name
Test status
Simulation time 69504255 ps
CPU time 0.73 seconds
Started Mar 17 12:58:48 PM PDT 24
Finished Mar 17 12:58:49 PM PDT 24
Peak memory 204396 kb
Host smart-5474b7d0-98da-4943-8d27-34e9464d0157
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448289021 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
3448289021
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3591824603
Short name T109
Test name
Test status
Simulation time 134261810 ps
CPU time 6.3 seconds
Started Mar 17 12:58:44 PM PDT 24
Finished Mar 17 12:58:51 PM PDT 24
Peak memory 204580 kb
Host smart-85445029-c20e-4dc5-82dd-9dfefda1e532
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591824603 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.3591824603
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.3988702074
Short name T345
Test name
Test status
Simulation time 1432161393 ps
CPU time 5.49 seconds
Started Mar 17 12:58:49 PM PDT 24
Finished Mar 17 12:58:55 PM PDT 24
Peak memory 212884 kb
Host smart-7efa9d27-80b3-4e12-ad74-b83a20e1b99c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988702074 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.3988702074
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.3469154968
Short name T351
Test name
Test status
Simulation time 358176935 ps
CPU time 2.16 seconds
Started Mar 17 12:58:49 PM PDT 24
Finished Mar 17 12:58:51 PM PDT 24
Peak memory 214448 kb
Host smart-d1118562-2eb1-4bd4-8522-15bc50da60fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469154968 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.3469154968
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.3079296924
Short name T102
Test name
Test status
Simulation time 89720975 ps
CPU time 1.56 seconds
Started Mar 17 12:58:48 PM PDT 24
Finished Mar 17 12:58:50 PM PDT 24
Peak memory 212868 kb
Host smart-7398fc06-68f0-4491-839a-07324689e01b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079296924 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.3079296924
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1080269325
Short name T305
Test name
Test status
Simulation time 1284958062 ps
CPU time 4.1 seconds
Started Mar 17 12:58:46 PM PDT 24
Finished Mar 17 12:58:51 PM PDT 24
Peak memory 204568 kb
Host smart-4bcfd786-bb92-40bf-8a86-17ffe9d6f987
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080269325 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
1080269325
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.4006668485
Short name T245
Test name
Test status
Simulation time 80174292 ps
CPU time 0.88 seconds
Started Mar 17 12:58:52 PM PDT 24
Finished Mar 17 12:58:53 PM PDT 24
Peak memory 204288 kb
Host smart-9aa1f60f-1b55-40f0-a60e-3b2db70375cf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006668485 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
4006668485
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.2004733830
Short name T104
Test name
Test status
Simulation time 429991007 ps
CPU time 3.61 seconds
Started Mar 17 12:58:49 PM PDT 24
Finished Mar 17 12:58:53 PM PDT 24
Peak memory 204564 kb
Host smart-a15564da-ee8f-441d-96c8-92843b9ed929
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004733830 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.2004733830
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tap_fsm_rand_reset.1392895076
Short name T63
Test name
Test status
Simulation time 7187321218 ps
CPU time 22.79 seconds
Started Mar 17 12:58:43 PM PDT 24
Finished Mar 17 12:59:06 PM PDT 24
Peak memory 214568 kb
Host smart-90560bd0-b727-4e4a-8697-7936d2ba4758
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392895076 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rv_dm_tap_fsm_rand_reset.1392895076
Directory /workspace/15.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.1698426578
Short name T34
Test name
Test status
Simulation time 950277591 ps
CPU time 2.73 seconds
Started Mar 17 12:58:48 PM PDT 24
Finished Mar 17 12:58:51 PM PDT 24
Peak memory 212836 kb
Host smart-3a9f7d93-4ded-41a4-b852-0341ec7c33db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698426578 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.1698426578
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3248591320
Short name T130
Test name
Test status
Simulation time 334309206 ps
CPU time 8.2 seconds
Started Mar 17 12:58:50 PM PDT 24
Finished Mar 17 12:58:58 PM PDT 24
Peak memory 212912 kb
Host smart-41b6991d-cbfe-4ec4-88eb-ea0ff23a314c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248591320 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.3
248591320
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2862339231
Short name T293
Test name
Test status
Simulation time 1849254277 ps
CPU time 3.81 seconds
Started Mar 17 12:58:57 PM PDT 24
Finished Mar 17 12:59:01 PM PDT 24
Peak memory 217244 kb
Host smart-5c02f9bc-3e2a-42b7-b79b-cc5b5ae4773c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862339231 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.2862339231
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.971261519
Short name T112
Test name
Test status
Simulation time 584514842 ps
CPU time 2.42 seconds
Started Mar 17 12:58:52 PM PDT 24
Finished Mar 17 12:58:55 PM PDT 24
Peak memory 212784 kb
Host smart-80187798-1499-4435-b46c-116856ae66f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971261519 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.971261519
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.706848215
Short name T252
Test name
Test status
Simulation time 636586313 ps
CPU time 1.5 seconds
Started Mar 17 12:58:52 PM PDT 24
Finished Mar 17 12:58:54 PM PDT 24
Peak memory 204616 kb
Host smart-0e171eb0-9f69-447d-a4eb-689395bf8700
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706848215 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.706848215
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3264107207
Short name T248
Test name
Test status
Simulation time 176978595 ps
CPU time 0.72 seconds
Started Mar 17 12:58:49 PM PDT 24
Finished Mar 17 12:58:50 PM PDT 24
Peak memory 204284 kb
Host smart-a77c01f3-50b9-48cf-b3fd-b19f05bdcdfb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264107207 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
3264107207
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3544377654
Short name T90
Test name
Test status
Simulation time 153706635 ps
CPU time 3.42 seconds
Started Mar 17 12:59:01 PM PDT 24
Finished Mar 17 12:59:04 PM PDT 24
Peak memory 204504 kb
Host smart-46ef9fa5-92e8-45b2-b2df-7cf21726a924
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544377654 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.3544377654
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3913666953
Short name T285
Test name
Test status
Simulation time 50903441 ps
CPU time 2.67 seconds
Started Mar 17 12:58:50 PM PDT 24
Finished Mar 17 12:58:53 PM PDT 24
Peak memory 212824 kb
Host smart-87f65e44-dff5-4760-8997-010d31f91f06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913666953 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.3913666953
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.1006168194
Short name T304
Test name
Test status
Simulation time 739488654 ps
CPU time 10.22 seconds
Started Mar 17 12:58:55 PM PDT 24
Finished Mar 17 12:59:05 PM PDT 24
Peak memory 212808 kb
Host smart-730654d3-b7ff-47ec-b781-fe5445100b81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006168194 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.1
006168194
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.1271445366
Short name T313
Test name
Test status
Simulation time 146547372 ps
CPU time 1.41 seconds
Started Mar 17 12:58:54 PM PDT 24
Finished Mar 17 12:58:56 PM PDT 24
Peak memory 212832 kb
Host smart-35cf0ecd-7647-41bc-aaf3-b14d9bd1939f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271445366 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.1271445366
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2006560632
Short name T246
Test name
Test status
Simulation time 861442278 ps
CPU time 2.25 seconds
Started Mar 17 12:59:00 PM PDT 24
Finished Mar 17 12:59:02 PM PDT 24
Peak memory 204596 kb
Host smart-121b5db6-47a9-47a9-a339-1f5391a4a7a1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006560632 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
2006560632
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2935735430
Short name T251
Test name
Test status
Simulation time 49932509 ps
CPU time 0.77 seconds
Started Mar 17 12:59:01 PM PDT 24
Finished Mar 17 12:59:02 PM PDT 24
Peak memory 204348 kb
Host smart-58f7b383-a7a4-408a-838a-7a6884bb6341
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935735430 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
2935735430
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2916235561
Short name T360
Test name
Test status
Simulation time 859553119 ps
CPU time 3.64 seconds
Started Mar 17 12:58:57 PM PDT 24
Finished Mar 17 12:59:00 PM PDT 24
Peak memory 204556 kb
Host smart-5765de1d-4977-4903-b1f2-2492b69b6e28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916235561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.2916235561
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.3059422866
Short name T347
Test name
Test status
Simulation time 247671782 ps
CPU time 4.64 seconds
Started Mar 17 12:58:49 PM PDT 24
Finished Mar 17 12:58:53 PM PDT 24
Peak memory 212912 kb
Host smart-e2935437-272b-445f-9081-2fa7e5c3803e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059422866 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.3059422866
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.673382139
Short name T82
Test name
Test status
Simulation time 1667553984 ps
CPU time 18.83 seconds
Started Mar 17 12:58:58 PM PDT 24
Finished Mar 17 12:59:17 PM PDT 24
Peak memory 212820 kb
Host smart-2326acac-932c-43ba-8495-5de97a6cf65f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673382139 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.673382139
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1765305064
Short name T341
Test name
Test status
Simulation time 342278176 ps
CPU time 2.44 seconds
Started Mar 17 12:59:01 PM PDT 24
Finished Mar 17 12:59:04 PM PDT 24
Peak memory 215536 kb
Host smart-6d0a11fe-3b66-4346-9bf8-ad2bedf8e476
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765305064 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.1765305064
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.820690445
Short name T310
Test name
Test status
Simulation time 37798261 ps
CPU time 2.35 seconds
Started Mar 17 12:58:59 PM PDT 24
Finished Mar 17 12:59:01 PM PDT 24
Peak memory 212924 kb
Host smart-107c56de-a627-4e03-b2e5-5ebe35f8b332
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820690445 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.820690445
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1099614005
Short name T236
Test name
Test status
Simulation time 1699309362 ps
CPU time 2.1 seconds
Started Mar 17 12:58:59 PM PDT 24
Finished Mar 17 12:59:01 PM PDT 24
Peak memory 204484 kb
Host smart-d48aea67-e8cd-4660-87f1-e1437e2f3d2b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099614005 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
1099614005
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2662727623
Short name T316
Test name
Test status
Simulation time 262949158 ps
CPU time 0.68 seconds
Started Mar 17 12:58:56 PM PDT 24
Finished Mar 17 12:58:56 PM PDT 24
Peak memory 204272 kb
Host smart-487dba0a-412c-4176-9f21-b1e3a71d2efa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662727623 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
2662727623
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1778554139
Short name T271
Test name
Test status
Simulation time 210040535 ps
CPU time 4.1 seconds
Started Mar 17 12:59:01 PM PDT 24
Finished Mar 17 12:59:05 PM PDT 24
Peak memory 204668 kb
Host smart-e1200253-a27f-48b3-b218-14b629d6457b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778554139 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.1778554139
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2102246875
Short name T84
Test name
Test status
Simulation time 243788436 ps
CPU time 5.24 seconds
Started Mar 17 12:58:49 PM PDT 24
Finished Mar 17 12:58:55 PM PDT 24
Peak memory 212828 kb
Host smart-5dbd7758-a474-4098-9745-30ecce520892
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102246875 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.2102246875
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3957895112
Short name T124
Test name
Test status
Simulation time 1484720991 ps
CPU time 15.89 seconds
Started Mar 17 12:58:57 PM PDT 24
Finished Mar 17 12:59:13 PM PDT 24
Peak memory 212828 kb
Host smart-0db16602-9343-48d3-917f-2917a3752e9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957895112 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.3
957895112
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1548287594
Short name T361
Test name
Test status
Simulation time 2203200441 ps
CPU time 2.78 seconds
Started Mar 17 12:59:06 PM PDT 24
Finished Mar 17 12:59:09 PM PDT 24
Peak memory 214068 kb
Host smart-b6f13f57-cc20-4d75-b051-6c07fb076701
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548287594 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.1548287594
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.1017416626
Short name T365
Test name
Test status
Simulation time 305458775 ps
CPU time 2.4 seconds
Started Mar 17 12:58:59 PM PDT 24
Finished Mar 17 12:59:02 PM PDT 24
Peak memory 212876 kb
Host smart-5f88002d-4ca4-4cf5-9656-41fdb60c3b24
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017416626 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.1017416626
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.673919496
Short name T354
Test name
Test status
Simulation time 394860543 ps
CPU time 1.18 seconds
Started Mar 17 12:58:55 PM PDT 24
Finished Mar 17 12:58:57 PM PDT 24
Peak memory 204584 kb
Host smart-f7632932-347d-489d-86a7-f4a2408a32be
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673919496 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.673919496
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.1696976684
Short name T274
Test name
Test status
Simulation time 48998748 ps
CPU time 0.7 seconds
Started Mar 17 12:58:59 PM PDT 24
Finished Mar 17 12:59:00 PM PDT 24
Peak memory 204408 kb
Host smart-01850b0f-a6de-40f5-9b18-728b7a7a01ba
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696976684 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
1696976684
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.3936763347
Short name T118
Test name
Test status
Simulation time 4644512176 ps
CPU time 8.38 seconds
Started Mar 17 12:59:01 PM PDT 24
Finished Mar 17 12:59:10 PM PDT 24
Peak memory 204592 kb
Host smart-da3e024a-2aa8-48bf-aa47-4b881b88159f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936763347 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.3936763347
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tap_fsm_rand_reset.4252518066
Short name T364
Test name
Test status
Simulation time 13043239731 ps
CPU time 13.28 seconds
Started Mar 17 12:59:06 PM PDT 24
Finished Mar 17 12:59:19 PM PDT 24
Peak memory 214204 kb
Host smart-2b6a24fb-9d63-4eb7-84ed-206e969a9603
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252518066 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rv_dm_tap_fsm_rand_reset.4252518066
Directory /workspace/19.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.931037514
Short name T85
Test name
Test status
Simulation time 605805879 ps
CPU time 4.68 seconds
Started Mar 17 12:59:01 PM PDT 24
Finished Mar 17 12:59:05 PM PDT 24
Peak memory 212932 kb
Host smart-dffb84c9-e7ae-48b7-89eb-738fcc9bd662
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931037514 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.931037514
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.3983555155
Short name T33
Test name
Test status
Simulation time 522547245 ps
CPU time 8.37 seconds
Started Mar 17 12:58:56 PM PDT 24
Finished Mar 17 12:59:05 PM PDT 24
Peak memory 220928 kb
Host smart-bc00b2be-2a44-4ff2-8bbc-223d7e2070ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983555155 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.3
983555155
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.3477180487
Short name T107
Test name
Test status
Simulation time 1139356727 ps
CPU time 64.34 seconds
Started Mar 17 12:58:24 PM PDT 24
Finished Mar 17 12:59:28 PM PDT 24
Peak memory 216308 kb
Host smart-c42732d2-d7c8-42dc-a099-c5cd1e4167eb
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477180487 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.3477180487
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.71692664
Short name T340
Test name
Test status
Simulation time 10260659579 ps
CPU time 33.37 seconds
Started Mar 17 12:58:26 PM PDT 24
Finished Mar 17 12:59:00 PM PDT 24
Peak memory 212920 kb
Host smart-22cb1797-1da3-48ae-8757-c664854d6ec7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71692664 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.71692664
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3284647258
Short name T111
Test name
Test status
Simulation time 111413110 ps
CPU time 2.49 seconds
Started Mar 17 12:58:26 PM PDT 24
Finished Mar 17 12:58:29 PM PDT 24
Peak memory 212832 kb
Host smart-1dfbaa77-2565-4318-b515-1eb0a6a88d67
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284647258 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.3284647258
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3328394047
Short name T283
Test name
Test status
Simulation time 148535635 ps
CPU time 4.08 seconds
Started Mar 17 12:58:31 PM PDT 24
Finished Mar 17 12:58:36 PM PDT 24
Peak memory 219152 kb
Host smart-c07c6e86-adc8-46fe-a922-1378ae759d39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328394047 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.3328394047
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2614866443
Short name T335
Test name
Test status
Simulation time 6754810202 ps
CPU time 19.84 seconds
Started Mar 17 12:58:31 PM PDT 24
Finished Mar 17 12:58:51 PM PDT 24
Peak memory 204744 kb
Host smart-26a6fc2c-f983-4e9d-ad4a-b92fdcf8fc80
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614866443 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.2614866443
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.4154783901
Short name T234
Test name
Test status
Simulation time 39279305022 ps
CPU time 81.4 seconds
Started Mar 17 12:58:31 PM PDT 24
Finished Mar 17 12:59:52 PM PDT 24
Peak memory 204608 kb
Host smart-3621139d-4e5a-4ea6-80de-b0afcd5cd6a5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154783901 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_bit_bash.4154783901
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1553691997
Short name T247
Test name
Test status
Simulation time 165530835 ps
CPU time 0.92 seconds
Started Mar 17 12:58:24 PM PDT 24
Finished Mar 17 12:58:25 PM PDT 24
Peak memory 204488 kb
Host smart-37f3bfd3-9610-46fd-bdb3-c2f1eff80e93
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553691997 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.1
553691997
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.969624970
Short name T67
Test name
Test status
Simulation time 220188941 ps
CPU time 1.02 seconds
Started Mar 17 12:58:23 PM PDT 24
Finished Mar 17 12:58:25 PM PDT 24
Peak memory 204432 kb
Host smart-957ed12b-2e95-4a5f-b110-a2f44d5fcbf7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969624970 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_aliasing.969624970
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.2977990497
Short name T376
Test name
Test status
Simulation time 928261265 ps
CPU time 1.96 seconds
Started Mar 17 12:58:24 PM PDT 24
Finished Mar 17 12:58:26 PM PDT 24
Peak memory 204536 kb
Host smart-3f6e2707-67c6-4f0f-9b99-1a19564020d9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977990497 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.2977990497
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2349231195
Short name T288
Test name
Test status
Simulation time 149802933 ps
CPU time 0.78 seconds
Started Mar 17 12:58:26 PM PDT 24
Finished Mar 17 12:58:27 PM PDT 24
Peak memory 204384 kb
Host smart-9504523f-7dcb-40ba-bfcc-57a4f6aa87fb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349231195 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.2349231195
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2588258068
Short name T241
Test name
Test status
Simulation time 36870210 ps
CPU time 0.73 seconds
Started Mar 17 12:58:24 PM PDT 24
Finished Mar 17 12:58:25 PM PDT 24
Peak memory 204268 kb
Host smart-4a1276ca-21c7-49d3-9ddb-bec35128ee18
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588258068 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.2
588258068
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.3471953306
Short name T250
Test name
Test status
Simulation time 25378857 ps
CPU time 0.7 seconds
Started Mar 17 12:58:24 PM PDT 24
Finished Mar 17 12:58:25 PM PDT 24
Peak memory 204280 kb
Host smart-4e55239f-3e61-417b-9f3a-ab580db2926f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471953306 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.3471953306
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.2211517570
Short name T267
Test name
Test status
Simulation time 41863153 ps
CPU time 0.67 seconds
Started Mar 17 12:58:29 PM PDT 24
Finished Mar 17 12:58:29 PM PDT 24
Peak memory 204364 kb
Host smart-b1727e77-6f44-4fca-b943-e1fff6b56fa9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211517570 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.2211517570
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.1249136918
Short name T356
Test name
Test status
Simulation time 992046861 ps
CPU time 8.03 seconds
Started Mar 17 12:58:25 PM PDT 24
Finished Mar 17 12:58:33 PM PDT 24
Peak memory 204676 kb
Host smart-2987712c-5f82-4e19-a8f0-767945d0284d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249136918 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.1249136918
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.2454119689
Short name T134
Test name
Test status
Simulation time 20343252989 ps
CPU time 22.15 seconds
Started Mar 17 12:58:26 PM PDT 24
Finished Mar 17 12:58:48 PM PDT 24
Peak memory 221164 kb
Host smart-222b4e80-3e65-430c-bfb6-3f036743e9e1
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454119689 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.2454119689
Directory /workspace/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.1767955901
Short name T326
Test name
Test status
Simulation time 52711686 ps
CPU time 3.51 seconds
Started Mar 17 12:58:27 PM PDT 24
Finished Mar 17 12:58:30 PM PDT 24
Peak memory 212808 kb
Host smart-1800c5da-66c3-433d-8110-16aca5118c7f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767955901 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.1767955901
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/21.rv_dm_tap_fsm_rand_reset.1368185908
Short name T294
Test name
Test status
Simulation time 5976501001 ps
CPU time 21.35 seconds
Started Mar 17 12:59:02 PM PDT 24
Finished Mar 17 12:59:23 PM PDT 24
Peak memory 220468 kb
Host smart-489fef08-11b9-431d-a314-e7f6a9a5756a
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368185908 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 21.rv_dm_tap_fsm_rand_reset.1368185908
Directory /workspace/21.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/24.rv_dm_tap_fsm_rand_reset.927523636
Short name T318
Test name
Test status
Simulation time 30044684426 ps
CPU time 25.24 seconds
Started Mar 17 12:59:06 PM PDT 24
Finished Mar 17 12:59:31 PM PDT 24
Peak memory 221096 kb
Host smart-fc879ca3-5cbb-4804-a9fd-6b19df0dcf0c
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927523636 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 24.rv_dm_tap_fsm_rand_reset.927523636
Directory /workspace/24.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/28.rv_dm_tap_fsm_rand_reset.1212413829
Short name T355
Test name
Test status
Simulation time 28285027358 ps
CPU time 22.55 seconds
Started Mar 17 12:59:00 PM PDT 24
Finished Mar 17 12:59:23 PM PDT 24
Peak memory 221192 kb
Host smart-ad87060f-6445-4086-abd7-eea6b7bf588b
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212413829 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 28.rv_dm_tap_fsm_rand_reset.1212413829
Directory /workspace/28.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/29.rv_dm_tap_fsm_rand_reset.2798475639
Short name T363
Test name
Test status
Simulation time 11010906710 ps
CPU time 10.27 seconds
Started Mar 17 12:58:56 PM PDT 24
Finished Mar 17 12:59:06 PM PDT 24
Peak memory 220976 kb
Host smart-8c918af8-6b3e-4af5-af96-ed868684264c
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798475639 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 29.rv_dm_tap_fsm_rand_reset.2798475639
Directory /workspace/29.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2916424714
Short name T108
Test name
Test status
Simulation time 6840082426 ps
CPU time 74.93 seconds
Started Mar 17 12:58:25 PM PDT 24
Finished Mar 17 12:59:40 PM PDT 24
Peak memory 212960 kb
Host smart-c26a7e4f-8516-4d2d-877e-513fe5f4c903
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916424714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.2916424714
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.3399888237
Short name T101
Test name
Test status
Simulation time 6161985965 ps
CPU time 34.13 seconds
Started Mar 17 12:58:30 PM PDT 24
Finished Mar 17 12:59:04 PM PDT 24
Peak memory 204876 kb
Host smart-261d720a-f2b9-4425-8f4b-79fee5255a1b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399888237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.3399888237
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.4269688602
Short name T287
Test name
Test status
Simulation time 242986730 ps
CPU time 2.17 seconds
Started Mar 17 12:58:38 PM PDT 24
Finished Mar 17 12:58:41 PM PDT 24
Peak memory 212916 kb
Host smart-9dd1a3fc-ae59-4b49-bc3b-299116c61317
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269688602 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.4269688602
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.3779477255
Short name T315
Test name
Test status
Simulation time 2575607194 ps
CPU time 4.87 seconds
Started Mar 17 12:58:34 PM PDT 24
Finished Mar 17 12:58:39 PM PDT 24
Peak memory 219396 kb
Host smart-2490a240-a6f0-4193-b990-40ce1d6f456f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779477255 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.3779477255
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.1802021444
Short name T105
Test name
Test status
Simulation time 577876902 ps
CPU time 2.41 seconds
Started Mar 17 12:58:36 PM PDT 24
Finished Mar 17 12:58:38 PM PDT 24
Peak memory 212884 kb
Host smart-4fb1eba3-46c8-4735-838c-4809300cb81a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802021444 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.1802021444
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.3437039094
Short name T329
Test name
Test status
Simulation time 10283192130 ps
CPU time 12.68 seconds
Started Mar 17 12:58:29 PM PDT 24
Finished Mar 17 12:58:42 PM PDT 24
Peak memory 204632 kb
Host smart-755d3df8-c563-4247-830a-54e5ce76d405
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437039094 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.3437039094
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.2552125651
Short name T330
Test name
Test status
Simulation time 6292800472 ps
CPU time 13.26 seconds
Started Mar 17 12:58:28 PM PDT 24
Finished Mar 17 12:58:42 PM PDT 24
Peak memory 204612 kb
Host smart-aefdc0d3-0313-41b5-a02f-bf2fc800c92f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552125651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_bit_bash.2552125651
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.3937657543
Short name T96
Test name
Test status
Simulation time 1730836714 ps
CPU time 5.86 seconds
Started Mar 17 12:58:26 PM PDT 24
Finished Mar 17 12:58:32 PM PDT 24
Peak memory 204428 kb
Host smart-c4e5ac9f-3413-4559-803e-5f9e75ab1478
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937657543 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.3937657543
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1997778647
Short name T253
Test name
Test status
Simulation time 352260290 ps
CPU time 0.93 seconds
Started Mar 17 12:58:26 PM PDT 24
Finished Mar 17 12:58:27 PM PDT 24
Peak memory 204564 kb
Host smart-c4a0eee2-4353-4e47-9b2b-d17084b96037
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997778647 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.1
997778647
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.4196038638
Short name T281
Test name
Test status
Simulation time 114893949 ps
CPU time 1 seconds
Started Mar 17 12:58:32 PM PDT 24
Finished Mar 17 12:58:33 PM PDT 24
Peak memory 204400 kb
Host smart-9c07908f-ea20-470c-ad01-8309ee8e5b35
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196038638 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.4196038638
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2362991017
Short name T277
Test name
Test status
Simulation time 4237499972 ps
CPU time 5.59 seconds
Started Mar 17 12:58:25 PM PDT 24
Finished Mar 17 12:58:31 PM PDT 24
Peak memory 204696 kb
Host smart-81d8cc61-b6fc-44b1-83db-162a10feb421
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362991017 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.2362991017
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.216720978
Short name T259
Test name
Test status
Simulation time 66347800 ps
CPU time 0.7 seconds
Started Mar 17 12:58:28 PM PDT 24
Finished Mar 17 12:58:29 PM PDT 24
Peak memory 204308 kb
Host smart-4c9a301c-5a1a-466a-a2c7-d839e210fd16
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216720978 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr
_hw_reset.216720978
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.309227527
Short name T346
Test name
Test status
Simulation time 53484029 ps
CPU time 0.74 seconds
Started Mar 17 12:58:31 PM PDT 24
Finished Mar 17 12:58:32 PM PDT 24
Peak memory 204400 kb
Host smart-7e745865-e012-4551-b57f-1c61a1c81f6f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309227527 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.309227527
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.2003124043
Short name T300
Test name
Test status
Simulation time 22436518 ps
CPU time 0.67 seconds
Started Mar 17 12:58:30 PM PDT 24
Finished Mar 17 12:58:31 PM PDT 24
Peak memory 204316 kb
Host smart-553a1849-9a63-41c0-87b3-c2e128263988
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003124043 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.2003124043
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.4242127648
Short name T255
Test name
Test status
Simulation time 54974815 ps
CPU time 0.65 seconds
Started Mar 17 12:58:30 PM PDT 24
Finished Mar 17 12:58:31 PM PDT 24
Peak memory 204416 kb
Host smart-99fd7aa6-86a6-492b-935d-306825697c00
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242127648 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.4242127648
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.3481280033
Short name T95
Test name
Test status
Simulation time 500174798 ps
CPU time 4.12 seconds
Started Mar 17 12:58:30 PM PDT 24
Finished Mar 17 12:58:34 PM PDT 24
Peak memory 204692 kb
Host smart-2b484629-0640-422b-bdfb-01ee96ada0c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481280033 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.3481280033
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.4200871368
Short name T264
Test name
Test status
Simulation time 131551332 ps
CPU time 3.5 seconds
Started Mar 17 12:58:34 PM PDT 24
Finished Mar 17 12:58:38 PM PDT 24
Peak memory 212828 kb
Host smart-a5bf2691-30b3-4d11-a4b4-f43dd6b8311e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200871368 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.4200871368
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.1964927663
Short name T132
Test name
Test status
Simulation time 425375234 ps
CPU time 15.56 seconds
Started Mar 17 12:58:37 PM PDT 24
Finished Mar 17 12:58:52 PM PDT 24
Peak memory 212904 kb
Host smart-fdaf65b8-db07-46a7-bca1-dec4a033c8fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964927663 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.1964927663
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/31.rv_dm_tap_fsm_rand_reset.2575170453
Short name T350
Test name
Test status
Simulation time 5467890250 ps
CPU time 18.6 seconds
Started Mar 17 12:59:09 PM PDT 24
Finished Mar 17 12:59:28 PM PDT 24
Peak memory 212948 kb
Host smart-529afa1d-b714-4ae6-9eb1-d43d2e191b07
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575170453 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 31.rv_dm_tap_fsm_rand_reset.2575170453
Directory /workspace/31.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/34.rv_dm_tap_fsm_rand_reset.2346090326
Short name T133
Test name
Test status
Simulation time 13902583550 ps
CPU time 15.67 seconds
Started Mar 17 12:59:00 PM PDT 24
Finished Mar 17 12:59:16 PM PDT 24
Peak memory 214064 kb
Host smart-d182cedb-068c-457f-8559-ef6cedfbf679
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346090326 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 34.rv_dm_tap_fsm_rand_reset.2346090326
Directory /workspace/34.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/35.rv_dm_tap_fsm_rand_reset.3193718107
Short name T352
Test name
Test status
Simulation time 23818808605 ps
CPU time 26.58 seconds
Started Mar 17 12:59:09 PM PDT 24
Finished Mar 17 12:59:35 PM PDT 24
Peak memory 221124 kb
Host smart-a5c15c78-6584-46a4-8ac9-d8d7013bf5b3
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193718107 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 35.rv_dm_tap_fsm_rand_reset.3193718107
Directory /workspace/35.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.3998719122
Short name T273
Test name
Test status
Simulation time 2820759396 ps
CPU time 26.77 seconds
Started Mar 17 12:58:31 PM PDT 24
Finished Mar 17 12:58:58 PM PDT 24
Peak memory 204656 kb
Host smart-32e74252-6479-4ed3-9a13-1b1b3160bdfd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998719122 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.3998719122
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.822249725
Short name T327
Test name
Test status
Simulation time 60514073 ps
CPU time 1.55 seconds
Started Mar 17 12:58:32 PM PDT 24
Finished Mar 17 12:58:34 PM PDT 24
Peak memory 212848 kb
Host smart-d97a138a-452b-44ad-aa5e-1d8ac22bb346
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822249725 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.822249725
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.3213198604
Short name T308
Test name
Test status
Simulation time 3423164038 ps
CPU time 5.4 seconds
Started Mar 17 12:58:31 PM PDT 24
Finished Mar 17 12:58:36 PM PDT 24
Peak memory 215760 kb
Host smart-6e8b5595-8882-4d8c-9825-d50613e6ee28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213198604 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.3213198604
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.2124583647
Short name T375
Test name
Test status
Simulation time 55424573 ps
CPU time 1.59 seconds
Started Mar 17 12:58:37 PM PDT 24
Finished Mar 17 12:58:38 PM PDT 24
Peak memory 212696 kb
Host smart-cd107a04-5007-4295-9c8e-869414846970
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124583647 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.2124583647
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.865460642
Short name T289
Test name
Test status
Simulation time 7211575728 ps
CPU time 21.47 seconds
Started Mar 17 12:58:37 PM PDT 24
Finished Mar 17 12:58:58 PM PDT 24
Peak memory 204556 kb
Host smart-10a906bc-643b-4d9d-beca-055161d475e4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865460642 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr
_aliasing.865460642
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.352388086
Short name T256
Test name
Test status
Simulation time 12360851242 ps
CPU time 51.39 seconds
Started Mar 17 12:58:37 PM PDT 24
Finished Mar 17 12:59:29 PM PDT 24
Peak memory 204724 kb
Host smart-76ab05a6-a8a8-4d03-9741-81c746040189
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352388086 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr
_bit_bash.352388086
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.1625208851
Short name T97
Test name
Test status
Simulation time 535059097 ps
CPU time 2.56 seconds
Started Mar 17 12:58:38 PM PDT 24
Finished Mar 17 12:58:41 PM PDT 24
Peak memory 204668 kb
Host smart-f0118a4f-7259-4eae-8bc6-9b9b33e5f46b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625208851 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.1625208851
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.767973232
Short name T233
Test name
Test status
Simulation time 361916961 ps
CPU time 1.88 seconds
Started Mar 17 12:58:37 PM PDT 24
Finished Mar 17 12:58:39 PM PDT 24
Peak memory 204484 kb
Host smart-960945a0-6767-480f-adc7-236324314630
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767973232 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.767973232
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.1101682787
Short name T298
Test name
Test status
Simulation time 276384522 ps
CPU time 1.49 seconds
Started Mar 17 12:58:36 PM PDT 24
Finished Mar 17 12:58:38 PM PDT 24
Peak memory 204396 kb
Host smart-8832ea2d-81fd-452b-85a7-1b845a81e35c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101682787 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.1101682787
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2562277092
Short name T284
Test name
Test status
Simulation time 656646529 ps
CPU time 3.09 seconds
Started Mar 17 12:58:31 PM PDT 24
Finished Mar 17 12:58:35 PM PDT 24
Peak memory 204492 kb
Host smart-fb2cf5fa-f821-4d6f-8386-ce9f2934bf99
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562277092 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.2562277092
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2007359466
Short name T323
Test name
Test status
Simulation time 55810525 ps
CPU time 0.83 seconds
Started Mar 17 12:58:31 PM PDT 24
Finished Mar 17 12:58:32 PM PDT 24
Peak memory 204368 kb
Host smart-3d9abe3b-3cf4-4c57-9297-3e44bea61fea
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007359466 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.2007359466
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.3527035731
Short name T68
Test name
Test status
Simulation time 54463264 ps
CPU time 0.74 seconds
Started Mar 17 12:58:34 PM PDT 24
Finished Mar 17 12:58:35 PM PDT 24
Peak memory 204380 kb
Host smart-2d5b7674-37d6-4a80-9b2d-93a603acaa08
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527035731 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.3
527035731
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.78058209
Short name T261
Test name
Test status
Simulation time 24524378 ps
CPU time 0.66 seconds
Started Mar 17 12:58:34 PM PDT 24
Finished Mar 17 12:58:35 PM PDT 24
Peak memory 204320 kb
Host smart-96e8bd33-8106-43fd-a360-67ab93de2d37
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78058209 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_parti
al_access.78058209
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.2612882895
Short name T254
Test name
Test status
Simulation time 28064034 ps
CPU time 0.73 seconds
Started Mar 17 12:58:35 PM PDT 24
Finished Mar 17 12:58:36 PM PDT 24
Peak memory 204352 kb
Host smart-dd296967-6b7a-4942-8801-87aceec65897
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612882895 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.2612882895
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.4144932635
Short name T276
Test name
Test status
Simulation time 283220148 ps
CPU time 4.34 seconds
Started Mar 17 12:58:31 PM PDT 24
Finished Mar 17 12:58:35 PM PDT 24
Peak memory 204612 kb
Host smart-09ba33ae-e578-47eb-b110-1238089f513c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144932635 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.4144932635
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.675322928
Short name T373
Test name
Test status
Simulation time 107431891 ps
CPU time 2.43 seconds
Started Mar 17 12:58:32 PM PDT 24
Finished Mar 17 12:58:35 PM PDT 24
Peak memory 212748 kb
Host smart-a7fa79ed-977f-488a-b3ea-96f1e2413437
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675322928 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.675322928
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.4210399343
Short name T123
Test name
Test status
Simulation time 930557641 ps
CPU time 18.32 seconds
Started Mar 17 12:58:37 PM PDT 24
Finished Mar 17 12:58:56 PM PDT 24
Peak memory 221040 kb
Host smart-ee12b14c-fd0d-4b84-811f-623c3fc30099
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210399343 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.4210399343
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.2826079297
Short name T83
Test name
Test status
Simulation time 3107735357 ps
CPU time 8.02 seconds
Started Mar 17 12:58:38 PM PDT 24
Finished Mar 17 12:58:46 PM PDT 24
Peak memory 218652 kb
Host smart-343bcc77-70e4-407c-a709-da30909f3f50
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826079297 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.2826079297
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.1489245798
Short name T89
Test name
Test status
Simulation time 242718151 ps
CPU time 1.54 seconds
Started Mar 17 12:58:37 PM PDT 24
Finished Mar 17 12:58:39 PM PDT 24
Peak memory 212856 kb
Host smart-9a50a2cf-3b01-4608-9f0b-6cf60cff2409
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489245798 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.1489245798
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3645203820
Short name T265
Test name
Test status
Simulation time 186068516 ps
CPU time 1.14 seconds
Started Mar 17 12:58:32 PM PDT 24
Finished Mar 17 12:58:33 PM PDT 24
Peak memory 204436 kb
Host smart-dc937868-3d36-4eed-99c1-87c2a22dfc3d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645203820 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.3
645203820
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.2258722029
Short name T290
Test name
Test status
Simulation time 74241033 ps
CPU time 0.83 seconds
Started Mar 17 12:58:34 PM PDT 24
Finished Mar 17 12:58:35 PM PDT 24
Peak memory 204380 kb
Host smart-e8369832-0a21-4b1e-8bd2-84879b57ff1a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258722029 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.2
258722029
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.2138677366
Short name T103
Test name
Test status
Simulation time 314798465 ps
CPU time 6.46 seconds
Started Mar 17 12:58:39 PM PDT 24
Finished Mar 17 12:58:45 PM PDT 24
Peak memory 204624 kb
Host smart-d340dbc5-3071-4a0b-a9a3-580d69c0bcdb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138677366 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.2138677366
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.889748058
Short name T371
Test name
Test status
Simulation time 12518174500 ps
CPU time 23.84 seconds
Started Mar 17 12:58:32 PM PDT 24
Finished Mar 17 12:58:56 PM PDT 24
Peak memory 229196 kb
Host smart-e47d5f06-ab84-4c98-a15c-474a2e0f9b2c
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889748058 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.889748058
Directory /workspace/5.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.3339777454
Short name T366
Test name
Test status
Simulation time 119959372 ps
CPU time 2.93 seconds
Started Mar 17 12:58:36 PM PDT 24
Finished Mar 17 12:58:40 PM PDT 24
Peak memory 212844 kb
Host smart-69d4a8b8-e2d8-49ab-b405-a8ef32d4f769
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339777454 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.3339777454
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.1742329004
Short name T372
Test name
Test status
Simulation time 469550625 ps
CPU time 8.46 seconds
Started Mar 17 12:58:31 PM PDT 24
Finished Mar 17 12:58:40 PM PDT 24
Peak memory 212848 kb
Host smart-c87f4cf6-1fdc-4084-aa19-99e9a5368dd1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742329004 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.1742329004
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.738543801
Short name T320
Test name
Test status
Simulation time 2437456409 ps
CPU time 3.85 seconds
Started Mar 17 12:58:37 PM PDT 24
Finished Mar 17 12:58:41 PM PDT 24
Peak memory 216088 kb
Host smart-180c47d8-4b08-4646-ba24-42b26d0824c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738543801 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.738543801
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1489885439
Short name T110
Test name
Test status
Simulation time 380393385 ps
CPU time 2.46 seconds
Started Mar 17 12:58:38 PM PDT 24
Finished Mar 17 12:58:41 PM PDT 24
Peak memory 218228 kb
Host smart-a6d95662-3933-4e19-9140-ca10ba530e59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489885439 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.1489885439
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2710948329
Short name T266
Test name
Test status
Simulation time 199684029 ps
CPU time 0.93 seconds
Started Mar 17 12:58:37 PM PDT 24
Finished Mar 17 12:58:38 PM PDT 24
Peak memory 204536 kb
Host smart-4d34080f-95c5-4d1a-8f3d-06134c9024d4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710948329 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.2
710948329
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2053399409
Short name T278
Test name
Test status
Simulation time 53754139 ps
CPU time 0.82 seconds
Started Mar 17 12:58:38 PM PDT 24
Finished Mar 17 12:58:39 PM PDT 24
Peak memory 204528 kb
Host smart-06152fd5-b4ef-4427-8b37-93c824a45e17
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053399409 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.2
053399409
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.1643962181
Short name T117
Test name
Test status
Simulation time 3080959838 ps
CPU time 7.46 seconds
Started Mar 17 12:58:37 PM PDT 24
Finished Mar 17 12:58:45 PM PDT 24
Peak memory 204700 kb
Host smart-ee8b4b92-976a-4161-9e63-9e0e544f5b1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643962181 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.1643962181
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1159914002
Short name T127
Test name
Test status
Simulation time 672164563 ps
CPU time 8.36 seconds
Started Mar 17 12:58:39 PM PDT 24
Finished Mar 17 12:58:48 PM PDT 24
Peak memory 220968 kb
Host smart-a08e6f67-df61-4f94-b796-327447df18f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159914002 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.1159914002
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3474987659
Short name T269
Test name
Test status
Simulation time 35342675 ps
CPU time 2.68 seconds
Started Mar 17 12:58:45 PM PDT 24
Finished Mar 17 12:58:48 PM PDT 24
Peak memory 217512 kb
Host smart-a6da9854-b195-45a9-bdba-430389991b8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474987659 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.3474987659
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.3142265059
Short name T303
Test name
Test status
Simulation time 57507912 ps
CPU time 1.52 seconds
Started Mar 17 12:58:38 PM PDT 24
Finished Mar 17 12:58:40 PM PDT 24
Peak memory 212872 kb
Host smart-3a42c409-dbd3-45ec-aa3c-5af424e147c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142265059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.3142265059
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3772972437
Short name T231
Test name
Test status
Simulation time 180867706 ps
CPU time 1.32 seconds
Started Mar 17 12:58:36 PM PDT 24
Finished Mar 17 12:58:38 PM PDT 24
Peak memory 204456 kb
Host smart-80fe8525-d109-4c5b-9413-2bf08ff20b37
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772972437 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.3
772972437
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.164273931
Short name T292
Test name
Test status
Simulation time 65155098 ps
CPU time 0.77 seconds
Started Mar 17 12:58:47 PM PDT 24
Finished Mar 17 12:58:48 PM PDT 24
Peak memory 204300 kb
Host smart-f0898a78-3ad9-4a5d-879e-5ff1c7a00e0f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164273931 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.164273931
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3884665885
Short name T349
Test name
Test status
Simulation time 1425171086 ps
CPU time 4.27 seconds
Started Mar 17 12:58:39 PM PDT 24
Finished Mar 17 12:58:44 PM PDT 24
Peak memory 204656 kb
Host smart-ebe4bfa4-ae81-4cb6-adb6-f3994eb01629
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884665885 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.3884665885
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.2006238794
Short name T299
Test name
Test status
Simulation time 7989822043 ps
CPU time 29.43 seconds
Started Mar 17 12:58:37 PM PDT 24
Finished Mar 17 12:59:06 PM PDT 24
Peak memory 220328 kb
Host smart-a70cc9f6-94d4-4bb3-b9e2-a01333f78653
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006238794 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.2006238794
Directory /workspace/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.2616577167
Short name T35
Test name
Test status
Simulation time 61472964 ps
CPU time 4.33 seconds
Started Mar 17 12:58:39 PM PDT 24
Finished Mar 17 12:58:43 PM PDT 24
Peak memory 212780 kb
Host smart-aaaff5a0-c668-497e-b9d6-10555849e5d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616577167 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.2616577167
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.754566248
Short name T362
Test name
Test status
Simulation time 1060893361 ps
CPU time 3.91 seconds
Started Mar 17 12:58:37 PM PDT 24
Finished Mar 17 12:58:41 PM PDT 24
Peak memory 218332 kb
Host smart-9e3695f4-9f57-41f9-a489-b1c096a151a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754566248 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.754566248
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.3442118084
Short name T317
Test name
Test status
Simulation time 68223484 ps
CPU time 1.55 seconds
Started Mar 17 12:58:38 PM PDT 24
Finished Mar 17 12:58:40 PM PDT 24
Peak memory 212892 kb
Host smart-d4f0f0b2-e0ae-491c-9ee5-0753f15b884b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442118084 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.3442118084
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3381432093
Short name T334
Test name
Test status
Simulation time 395877175 ps
CPU time 1.28 seconds
Started Mar 17 12:58:47 PM PDT 24
Finished Mar 17 12:58:48 PM PDT 24
Peak memory 204512 kb
Host smart-641833a2-d181-468c-b2af-29badc7d3e10
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381432093 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.3
381432093
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.187002847
Short name T238
Test name
Test status
Simulation time 232985490 ps
CPU time 0.82 seconds
Started Mar 17 12:58:37 PM PDT 24
Finished Mar 17 12:58:39 PM PDT 24
Peak memory 204304 kb
Host smart-f9a64879-1fff-4134-bf9f-bc75ed83665e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187002847 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.187002847
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2165460585
Short name T106
Test name
Test status
Simulation time 578459247 ps
CPU time 6.66 seconds
Started Mar 17 12:58:45 PM PDT 24
Finished Mar 17 12:58:52 PM PDT 24
Peak memory 204680 kb
Host smart-18e7b3d1-47e7-4d01-9697-25e5b66d2e67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165460585 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_
csr_outstanding.2165460585
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.482350671
Short name T158
Test name
Test status
Simulation time 84768826 ps
CPU time 2.65 seconds
Started Mar 17 12:58:38 PM PDT 24
Finished Mar 17 12:58:41 PM PDT 24
Peak memory 220924 kb
Host smart-7a652b3d-c496-4a08-be33-6cebc8df58db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482350671 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.482350671
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.1867070808
Short name T128
Test name
Test status
Simulation time 1367196828 ps
CPU time 19.46 seconds
Started Mar 17 12:58:37 PM PDT 24
Finished Mar 17 12:58:57 PM PDT 24
Peak memory 212864 kb
Host smart-6cb21f2e-ec93-415a-8ea5-3a7721423963
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867070808 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.1867070808
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.2213043182
Short name T81
Test name
Test status
Simulation time 357664704 ps
CPU time 2.43 seconds
Started Mar 17 12:58:45 PM PDT 24
Finished Mar 17 12:58:48 PM PDT 24
Peak memory 217104 kb
Host smart-b9da928b-65e0-4af7-bbb1-dd7139fe9804
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213043182 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.2213043182
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1983923396
Short name T309
Test name
Test status
Simulation time 49031773 ps
CPU time 1.55 seconds
Started Mar 17 12:58:53 PM PDT 24
Finished Mar 17 12:58:54 PM PDT 24
Peak memory 218220 kb
Host smart-04246948-ca01-4580-b109-22ad2e4ac1e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983923396 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.1983923396
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.2485058538
Short name T232
Test name
Test status
Simulation time 1294115560 ps
CPU time 4.71 seconds
Started Mar 17 12:58:37 PM PDT 24
Finished Mar 17 12:58:42 PM PDT 24
Peak memory 204540 kb
Host smart-f488ecee-a48b-4223-9fb9-bedd2100a5b0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485058538 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.2
485058538
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.2615398692
Short name T357
Test name
Test status
Simulation time 31990421 ps
CPU time 0.77 seconds
Started Mar 17 12:58:37 PM PDT 24
Finished Mar 17 12:58:38 PM PDT 24
Peak memory 204248 kb
Host smart-615f04dd-d430-41e6-9f0c-4afc99cb20a2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615398692 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.2
615398692
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.28835488
Short name T297
Test name
Test status
Simulation time 1571269415 ps
CPU time 7.41 seconds
Started Mar 17 12:58:47 PM PDT 24
Finished Mar 17 12:58:54 PM PDT 24
Peak memory 204688 kb
Host smart-d0a94462-a31a-4a03-aa01-ff2cc1e0bc76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28835488 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_cs
r_outstanding.28835488
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.164054939
Short name T359
Test name
Test status
Simulation time 295945426 ps
CPU time 2.39 seconds
Started Mar 17 12:58:37 PM PDT 24
Finished Mar 17 12:58:40 PM PDT 24
Peak memory 212848 kb
Host smart-d99b8b8a-f1bb-4472-b260-5d5c36766b6a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164054939 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.164054939
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2717394815
Short name T312
Test name
Test status
Simulation time 443389625 ps
CPU time 8.85 seconds
Started Mar 17 12:58:43 PM PDT 24
Finished Mar 17 12:58:52 PM PDT 24
Peak memory 220996 kb
Host smart-bc652b7d-9cd4-468f-9a08-53eb00967c5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717394815 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.2717394815
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.764191148
Short name T145
Test name
Test status
Simulation time 44464226 ps
CPU time 0.7 seconds
Started Mar 17 02:13:35 PM PDT 24
Finished Mar 17 02:13:36 PM PDT 24
Peak memory 204876 kb
Host smart-9d7065ae-4808-4438-ba64-c7f2fb66b241
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764191148 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.764191148
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.3651008341
Short name T20
Test name
Test status
Simulation time 10049809207 ps
CPU time 31.59 seconds
Started Mar 17 02:13:29 PM PDT 24
Finished Mar 17 02:14:01 PM PDT 24
Peak memory 205292 kb
Host smart-f72bb465-8edf-4ebf-800b-59142c193e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651008341 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.3651008341
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.3001657773
Short name T217
Test name
Test status
Simulation time 4231389190 ps
CPU time 8.69 seconds
Started Mar 17 02:13:29 PM PDT 24
Finished Mar 17 02:13:37 PM PDT 24
Peak memory 215240 kb
Host smart-11dc8b1f-1cbe-43bf-b329-a69939cd916e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001657773 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.3001657773
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.2013957378
Short name T6
Test name
Test status
Simulation time 649232217 ps
CPU time 1.25 seconds
Started Mar 17 02:13:28 PM PDT 24
Finished Mar 17 02:13:30 PM PDT 24
Peak memory 204776 kb
Host smart-685cc0c0-2f9a-4aaf-abf3-1ac1652d8047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013957378 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.2013957378
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.249631666
Short name T22
Test name
Test status
Simulation time 2319897046 ps
CPU time 4.8 seconds
Started Mar 17 02:13:28 PM PDT 24
Finished Mar 17 02:13:33 PM PDT 24
Peak memory 204984 kb
Host smart-3324816e-d1c5-4ccd-ab08-d6b16cd6d199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249631666 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.249631666
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.2454124573
Short name T182
Test name
Test status
Simulation time 54169081 ps
CPU time 0.87 seconds
Started Mar 17 02:13:30 PM PDT 24
Finished Mar 17 02:13:31 PM PDT 24
Peak memory 204832 kb
Host smart-a5171523-2ea6-48e1-9a92-7ec7ffcdcbd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454124573 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.2454124573
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.1723007497
Short name T202
Test name
Test status
Simulation time 2566631938 ps
CPU time 11.89 seconds
Started Mar 17 02:13:27 PM PDT 24
Finished Mar 17 02:13:39 PM PDT 24
Peak memory 205100 kb
Host smart-68ac1c04-c5f1-48f1-ba07-6c14b659e093
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1723007497 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t
l_access.1723007497
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.4119996774
Short name T86
Test name
Test status
Simulation time 269531801 ps
CPU time 1 seconds
Started Mar 17 02:13:35 PM PDT 24
Finished Mar 17 02:13:37 PM PDT 24
Peak memory 204864 kb
Host smart-00be319a-853d-43e5-9db3-dc69a31804db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119996774 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.4119996774
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.2926983831
Short name T204
Test name
Test status
Simulation time 59655608 ps
CPU time 0.78 seconds
Started Mar 17 02:13:27 PM PDT 24
Finished Mar 17 02:13:28 PM PDT 24
Peak memory 204724 kb
Host smart-4dcb0fc6-490f-4674-b8dd-1edc7606d25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926983831 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.2926983831
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.4168810942
Short name T16
Test name
Test status
Simulation time 122849559 ps
CPU time 0.85 seconds
Started Mar 17 02:13:34 PM PDT 24
Finished Mar 17 02:13:36 PM PDT 24
Peak memory 204744 kb
Host smart-9aa6a1b5-978b-4aaf-aa69-9288c3b2744a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168810942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.4168810942
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.271882231
Short name T7
Test name
Test status
Simulation time 151100436 ps
CPU time 0.76 seconds
Started Mar 17 02:13:37 PM PDT 24
Finished Mar 17 02:13:38 PM PDT 24
Peak memory 204636 kb
Host smart-d85ac411-d7d2-467f-95d8-f7f63e83bfd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271882231 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.271882231
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.4259611309
Short name T205
Test name
Test status
Simulation time 60239947 ps
CPU time 0.68 seconds
Started Mar 17 02:13:32 PM PDT 24
Finished Mar 17 02:13:33 PM PDT 24
Peak memory 204712 kb
Host smart-821280e2-555c-485a-83c6-11687cac3384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259611309 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.4259611309
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.626073686
Short name T45
Test name
Test status
Simulation time 26098481 ps
CPU time 0.79 seconds
Started Mar 17 02:13:28 PM PDT 24
Finished Mar 17 02:13:29 PM PDT 24
Peak memory 204844 kb
Host smart-e784e2f1-7a67-4590-bd59-ea5b13c79963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626073686 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.626073686
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.1035209153
Short name T76
Test name
Test status
Simulation time 129411436 ps
CPU time 1.12 seconds
Started Mar 17 02:13:27 PM PDT 24
Finished Mar 17 02:13:28 PM PDT 24
Peak memory 204832 kb
Host smart-f6ea51a7-9024-41de-9cdc-99416e081022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035209153 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.1035209153
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.1855854194
Short name T135
Test name
Test status
Simulation time 719543658 ps
CPU time 1.39 seconds
Started Mar 17 02:13:33 PM PDT 24
Finished Mar 17 02:13:35 PM PDT 24
Peak memory 204940 kb
Host smart-22543799-8c1e-4d9d-ad74-dc0795199dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855854194 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.1855854194
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.1093818195
Short name T55
Test name
Test status
Simulation time 53754205 ps
CPU time 0.79 seconds
Started Mar 17 02:13:34 PM PDT 24
Finished Mar 17 02:13:35 PM PDT 24
Peak memory 213052 kb
Host smart-fcc27a13-5193-4494-9c62-f8b2a0485aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093818195 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.1093818195
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.2427554202
Short name T166
Test name
Test status
Simulation time 883789806 ps
CPU time 3.71 seconds
Started Mar 17 02:13:27 PM PDT 24
Finished Mar 17 02:13:31 PM PDT 24
Peak memory 205104 kb
Host smart-28cc4283-9aed-44a1-b07e-c8ac16ca6275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427554202 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.2427554202
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.264341690
Short name T23
Test name
Test status
Simulation time 139488141 ps
CPU time 1.02 seconds
Started Mar 17 02:13:37 PM PDT 24
Finished Mar 17 02:13:38 PM PDT 24
Peak memory 228464 kb
Host smart-3a561c13-a3e6-4625-9c78-dd3a2620cc1a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264341690 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.264341690
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.1866775525
Short name T18
Test name
Test status
Simulation time 308877676 ps
CPU time 1.66 seconds
Started Mar 17 02:13:27 PM PDT 24
Finished Mar 17 02:13:29 PM PDT 24
Peak memory 204884 kb
Host smart-33817784-d3c5-47ae-98e1-9d63b75871ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866775525 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.1866775525
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.1219465816
Short name T62
Test name
Test status
Simulation time 2643830393 ps
CPU time 3.28 seconds
Started Mar 17 02:13:27 PM PDT 24
Finished Mar 17 02:13:31 PM PDT 24
Peak memory 204968 kb
Host smart-fb313f05-bbcd-41e0-be33-b7e779d877b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219465816 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.1219465816
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.3514182402
Short name T212
Test name
Test status
Simulation time 66093325 ps
CPU time 0.74 seconds
Started Mar 17 02:13:40 PM PDT 24
Finished Mar 17 02:13:40 PM PDT 24
Peak memory 204808 kb
Host smart-7cc0db6b-6cd6-4457-b2e6-cdbbc1824fdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514182402 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.3514182402
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.2815091354
Short name T222
Test name
Test status
Simulation time 7438781908 ps
CPU time 8.69 seconds
Started Mar 17 02:13:36 PM PDT 24
Finished Mar 17 02:13:46 PM PDT 24
Peak memory 205240 kb
Host smart-a805f046-362d-4fdf-b053-1296666c5a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815091354 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.2815091354
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.1503274733
Short name T198
Test name
Test status
Simulation time 1659336438 ps
CPU time 8.25 seconds
Started Mar 17 02:13:37 PM PDT 24
Finished Mar 17 02:13:45 PM PDT 24
Peak memory 205104 kb
Host smart-0086c1bd-ea9c-423e-99e8-be4cca92358a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503274733 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.1503274733
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.3390501978
Short name T120
Test name
Test status
Simulation time 1763509923 ps
CPU time 4.22 seconds
Started Mar 17 02:13:36 PM PDT 24
Finished Mar 17 02:13:41 PM PDT 24
Peak memory 205096 kb
Host smart-cab1071d-d450-4bb9-bc1a-5abb49b21e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390501978 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.3390501978
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.2260827785
Short name T53
Test name
Test status
Simulation time 105085980 ps
CPU time 0.81 seconds
Started Mar 17 02:13:39 PM PDT 24
Finished Mar 17 02:13:41 PM PDT 24
Peak memory 204692 kb
Host smart-b1aed96e-340e-4c5d-9fef-83d69f566118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260827785 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.2260827785
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.3723879574
Short name T3
Test name
Test status
Simulation time 66246082 ps
CPU time 0.72 seconds
Started Mar 17 02:13:40 PM PDT 24
Finished Mar 17 02:13:41 PM PDT 24
Peak memory 204692 kb
Host smart-93139c49-86b4-4161-a82d-40ae492bbc51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723879574 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.3723879574
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.1800431920
Short name T165
Test name
Test status
Simulation time 3406340843 ps
CPU time 4.81 seconds
Started Mar 17 02:13:35 PM PDT 24
Finished Mar 17 02:13:40 PM PDT 24
Peak memory 205332 kb
Host smart-ff2fd76e-d8a3-46b3-b299-fdc7dd7b222e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1800431920 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.1800431920
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.2965373272
Short name T197
Test name
Test status
Simulation time 360297689 ps
CPU time 1.42 seconds
Started Mar 17 02:13:40 PM PDT 24
Finished Mar 17 02:13:41 PM PDT 24
Peak memory 205092 kb
Host smart-3858881c-0064-49d5-9b47-9a5918e986a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965373272 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.2965373272
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.2991014660
Short name T203
Test name
Test status
Simulation time 37012545 ps
CPU time 0.69 seconds
Started Mar 17 02:13:38 PM PDT 24
Finished Mar 17 02:13:39 PM PDT 24
Peak memory 204620 kb
Host smart-7d353578-ab73-40c4-91cb-171a3a3b1655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991014660 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.2991014660
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.1845933630
Short name T179
Test name
Test status
Simulation time 279185694 ps
CPU time 0.83 seconds
Started Mar 17 02:13:40 PM PDT 24
Finished Mar 17 02:13:41 PM PDT 24
Peak memory 204652 kb
Host smart-496a4e1d-5d81-4415-91c4-8125a147bb73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845933630 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.1845933630
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.2145218230
Short name T61
Test name
Test status
Simulation time 212018964 ps
CPU time 0.89 seconds
Started Mar 17 02:13:39 PM PDT 24
Finished Mar 17 02:13:41 PM PDT 24
Peak memory 204748 kb
Host smart-2d025ce6-b2d2-4e07-8937-e5b2090579fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145218230 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.2145218230
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.3409942965
Short name T210
Test name
Test status
Simulation time 24203824 ps
CPU time 0.72 seconds
Started Mar 17 02:13:46 PM PDT 24
Finished Mar 17 02:13:48 PM PDT 24
Peak memory 204704 kb
Host smart-8447b380-4a36-43cb-8b94-20ce59da0b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409942965 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.3409942965
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.1600591802
Short name T136
Test name
Test status
Simulation time 117408181 ps
CPU time 0.87 seconds
Started Mar 17 02:13:38 PM PDT 24
Finished Mar 17 02:13:39 PM PDT 24
Peak memory 204816 kb
Host smart-8395bbb2-dcf5-4574-a777-dcd398d29b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600591802 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.1600591802
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.1605669467
Short name T14
Test name
Test status
Simulation time 395343674 ps
CPU time 0.95 seconds
Started Mar 17 02:13:40 PM PDT 24
Finished Mar 17 02:13:41 PM PDT 24
Peak memory 204860 kb
Host smart-d508de29-8306-4c42-8ff8-ebf6c558a0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605669467 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.1605669467
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.3803771724
Short name T87
Test name
Test status
Simulation time 721531216 ps
CPU time 1.36 seconds
Started Mar 17 02:13:40 PM PDT 24
Finished Mar 17 02:13:42 PM PDT 24
Peak memory 204852 kb
Host smart-e8fc8021-a46c-4ea2-b688-304507fd7a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803771724 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.3803771724
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.1737692417
Short name T56
Test name
Test status
Simulation time 179331375 ps
CPU time 0.9 seconds
Started Mar 17 02:13:43 PM PDT 24
Finished Mar 17 02:13:44 PM PDT 24
Peak memory 204860 kb
Host smart-ee5ec5b4-91f6-45e9-8056-e1591540d827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737692417 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.1737692417
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.1114320595
Short name T60
Test name
Test status
Simulation time 84137787 ps
CPU time 0.93 seconds
Started Mar 17 02:13:46 PM PDT 24
Finished Mar 17 02:13:48 PM PDT 24
Peak memory 204844 kb
Host smart-85167ed8-b839-4de1-b0cc-6c05db6feb1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114320595 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.1114320595
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.3279145749
Short name T200
Test name
Test status
Simulation time 14044987054 ps
CPU time 14.89 seconds
Started Mar 17 02:13:35 PM PDT 24
Finished Mar 17 02:13:50 PM PDT 24
Peak memory 205140 kb
Host smart-b30645ac-db20-4910-a004-f1a37291fb33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279145749 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.3279145749
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.76982348
Short name T44
Test name
Test status
Simulation time 186054339 ps
CPU time 1.22 seconds
Started Mar 17 02:13:40 PM PDT 24
Finished Mar 17 02:13:41 PM PDT 24
Peak memory 229012 kb
Host smart-89386ac8-a16a-4da7-a6e0-156165e6498c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76982348 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.76982348
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.2454541404
Short name T177
Test name
Test status
Simulation time 630423381 ps
CPU time 1.26 seconds
Started Mar 17 02:13:33 PM PDT 24
Finished Mar 17 02:13:35 PM PDT 24
Peak memory 204932 kb
Host smart-1c1aa920-6653-4436-843f-90cc47e7b70e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454541404 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.2454541404
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all.1242328696
Short name T9
Test name
Test status
Simulation time 2229391924 ps
CPU time 5.49 seconds
Started Mar 17 02:13:40 PM PDT 24
Finished Mar 17 02:13:46 PM PDT 24
Peak memory 204964 kb
Host smart-53260aba-f55d-4d08-9047-0140c8c71d21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242328696 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.1242328696
Directory /workspace/1.rv_dm_stress_all/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.1088682846
Short name T71
Test name
Test status
Simulation time 20039481 ps
CPU time 0.7 seconds
Started Mar 17 02:14:00 PM PDT 24
Finished Mar 17 02:14:01 PM PDT 24
Peak memory 204852 kb
Host smart-e6faebf9-e438-48fc-ad00-b398c62f9d2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088682846 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.1088682846
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.2928262812
Short name T220
Test name
Test status
Simulation time 448764289 ps
CPU time 2 seconds
Started Mar 17 02:14:01 PM PDT 24
Finished Mar 17 02:14:03 PM PDT 24
Peak memory 205220 kb
Host smart-a53ae122-4bfd-4ea8-a38d-3cbb0e2d084b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928262812 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.2928262812
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.3287266969
Short name T175
Test name
Test status
Simulation time 1135927468 ps
CPU time 1.82 seconds
Started Mar 17 02:13:59 PM PDT 24
Finished Mar 17 02:14:01 PM PDT 24
Peak memory 205096 kb
Host smart-cfa6eaf2-d177-43e4-8f30-b9ab3c866ff9
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3287266969 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.3287266969
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.242945659
Short name T190
Test name
Test status
Simulation time 2664872710 ps
CPU time 8.48 seconds
Started Mar 17 02:14:00 PM PDT 24
Finished Mar 17 02:14:09 PM PDT 24
Peak memory 205140 kb
Host smart-44b8c583-5cb6-443c-897d-9dc7712ea697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242945659 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.242945659
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.1917351873
Short name T216
Test name
Test status
Simulation time 32737427 ps
CPU time 0.7 seconds
Started Mar 17 02:13:59 PM PDT 24
Finished Mar 17 02:14:00 PM PDT 24
Peak memory 204776 kb
Host smart-8df029ae-d85f-4455-a2ca-94da5114912c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917351873 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.1917351873
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.1686743384
Short name T12
Test name
Test status
Simulation time 2337520361 ps
CPU time 3.25 seconds
Started Mar 17 02:14:01 PM PDT 24
Finished Mar 17 02:14:04 PM PDT 24
Peak memory 205264 kb
Host smart-96659919-9d94-44d1-9aa2-29cb88792bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686743384 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.1686743384
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.4010464061
Short name T188
Test name
Test status
Simulation time 16707161145 ps
CPU time 25.64 seconds
Started Mar 17 02:13:58 PM PDT 24
Finished Mar 17 02:14:24 PM PDT 24
Peak memory 213448 kb
Host smart-a4953129-5302-4a75-8e26-d0734999e614
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4010464061 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_
tl_access.4010464061
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.3221315078
Short name T78
Test name
Test status
Simulation time 2636802307 ps
CPU time 12.15 seconds
Started Mar 17 02:14:01 PM PDT 24
Finished Mar 17 02:14:13 PM PDT 24
Peak memory 205240 kb
Host smart-f95a5481-e487-440e-aa76-0809badbcad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221315078 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.3221315078
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.3900622420
Short name T122
Test name
Test status
Simulation time 52815963 ps
CPU time 0.69 seconds
Started Mar 17 02:13:59 PM PDT 24
Finished Mar 17 02:14:00 PM PDT 24
Peak memory 204872 kb
Host smart-43b1e527-4524-46a9-b03a-8c160d60200c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900622420 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.3900622420
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.868096375
Short name T221
Test name
Test status
Simulation time 3618238232 ps
CPU time 11.49 seconds
Started Mar 17 02:13:59 PM PDT 24
Finished Mar 17 02:14:11 PM PDT 24
Peak memory 205232 kb
Host smart-89e18a25-af27-45d0-a30c-e0bd6a8672bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868096375 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.868096375
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.2701804941
Short name T187
Test name
Test status
Simulation time 11869535744 ps
CPU time 10.15 seconds
Started Mar 17 02:14:04 PM PDT 24
Finished Mar 17 02:14:15 PM PDT 24
Peak memory 205280 kb
Host smart-d7b4685f-a4e3-43bb-9b33-ce1af91c7694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701804941 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.2701804941
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.1423710629
Short name T227
Test name
Test status
Simulation time 5651951596 ps
CPU time 7.14 seconds
Started Mar 17 02:14:00 PM PDT 24
Finished Mar 17 02:14:07 PM PDT 24
Peak memory 205240 kb
Host smart-97b0a2d1-0e9a-48e2-b8da-f398bd716737
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1423710629 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.1423710629
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.2474730538
Short name T191
Test name
Test status
Simulation time 4163209526 ps
CPU time 6.77 seconds
Started Mar 17 02:13:59 PM PDT 24
Finished Mar 17 02:14:06 PM PDT 24
Peak memory 205276 kb
Host smart-9c92affc-2fa3-4b99-9d3d-10d7d631d0b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474730538 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.2474730538
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.4220387227
Short name T139
Test name
Test status
Simulation time 42248281 ps
CPU time 0.69 seconds
Started Mar 17 02:14:05 PM PDT 24
Finished Mar 17 02:14:06 PM PDT 24
Peak memory 204808 kb
Host smart-bd96d0e9-28ee-4f60-899f-a6d8d33e33c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220387227 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.4220387227
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.85025852
Short name T181
Test name
Test status
Simulation time 14770536547 ps
CPU time 30.21 seconds
Started Mar 17 02:14:14 PM PDT 24
Finished Mar 17 02:14:44 PM PDT 24
Peak memory 213404 kb
Host smart-814e2b06-e66d-49f0-a39d-80c0c4675241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85025852 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.85025852
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.3331306540
Short name T173
Test name
Test status
Simulation time 4087061836 ps
CPU time 16.63 seconds
Started Mar 17 02:14:04 PM PDT 24
Finished Mar 17 02:14:20 PM PDT 24
Peak memory 213340 kb
Host smart-1baff508-3c69-4c8a-a40f-96b93389d24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331306540 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.3331306540
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.1459538684
Short name T163
Test name
Test status
Simulation time 3890234477 ps
CPU time 2.5 seconds
Started Mar 17 02:14:14 PM PDT 24
Finished Mar 17 02:14:16 PM PDT 24
Peak memory 205108 kb
Host smart-c00107c1-3830-49f5-a129-84835ae1691f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1459538684 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_
tl_access.1459538684
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.3849736204
Short name T171
Test name
Test status
Simulation time 3341012458 ps
CPU time 13.41 seconds
Started Mar 17 02:13:58 PM PDT 24
Finished Mar 17 02:14:12 PM PDT 24
Peak memory 205320 kb
Host smart-1e134d67-5684-4d39-a558-84464d96deac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849736204 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.3849736204
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_stress_all.1561198335
Short name T15
Test name
Test status
Simulation time 843923935 ps
CPU time 3.37 seconds
Started Mar 17 02:14:04 PM PDT 24
Finished Mar 17 02:14:07 PM PDT 24
Peak memory 205048 kb
Host smart-ff9aad15-c638-4e82-b8bb-675d3d9d7cf5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561198335 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.1561198335
Directory /workspace/13.rv_dm_stress_all/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.902309965
Short name T155
Test name
Test status
Simulation time 27199873 ps
CPU time 0.76 seconds
Started Mar 17 02:14:07 PM PDT 24
Finished Mar 17 02:14:08 PM PDT 24
Peak memory 204892 kb
Host smart-24c98606-eade-420e-9f35-0640ffc4059c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902309965 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.902309965
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.3640447515
Short name T215
Test name
Test status
Simulation time 714336458 ps
CPU time 3.97 seconds
Started Mar 17 02:14:04 PM PDT 24
Finished Mar 17 02:14:08 PM PDT 24
Peak memory 205160 kb
Host smart-0c7fd160-2709-4a29-9bea-efe9ed7cdffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640447515 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.3640447515
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.4158427249
Short name T211
Test name
Test status
Simulation time 8467754079 ps
CPU time 10.69 seconds
Started Mar 17 02:14:03 PM PDT 24
Finished Mar 17 02:14:14 PM PDT 24
Peak memory 205300 kb
Host smart-9dcb6bdb-929a-4527-9cb2-17fbebef5255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158427249 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.4158427249
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.1034085868
Short name T186
Test name
Test status
Simulation time 1227505342 ps
CPU time 6.95 seconds
Started Mar 17 02:14:09 PM PDT 24
Finished Mar 17 02:14:16 PM PDT 24
Peak memory 205132 kb
Host smart-5ed9d7e0-a87e-4fbc-9001-263508c08306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034085868 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.1034085868
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.198235886
Short name T10
Test name
Test status
Simulation time 1419239321 ps
CPU time 6.62 seconds
Started Mar 17 02:14:04 PM PDT 24
Finished Mar 17 02:14:10 PM PDT 24
Peak memory 205164 kb
Host smart-8f2d316a-0e2e-427f-b90d-27885f80931a
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=198235886 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_t
l_access.198235886
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.1121983315
Short name T225
Test name
Test status
Simulation time 1598617533 ps
CPU time 3.62 seconds
Started Mar 17 02:14:04 PM PDT 24
Finished Mar 17 02:14:07 PM PDT 24
Peak memory 205164 kb
Host smart-5e27b3e8-5cb7-498f-a290-d690cabadbea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121983315 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.1121983315
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.2014150184
Short name T140
Test name
Test status
Simulation time 22987078 ps
CPU time 0.74 seconds
Started Mar 17 02:14:07 PM PDT 24
Finished Mar 17 02:14:08 PM PDT 24
Peak memory 204808 kb
Host smart-27040b1a-e504-47ac-83fa-9b8cc31bd820
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014150184 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.2014150184
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.1598885417
Short name T47
Test name
Test status
Simulation time 1485154971 ps
CPU time 2.84 seconds
Started Mar 17 02:14:14 PM PDT 24
Finished Mar 17 02:14:17 PM PDT 24
Peak memory 205084 kb
Host smart-19408d93-6418-40ee-985a-c4c3989df6ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598885417 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.1598885417
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.957207418
Short name T77
Test name
Test status
Simulation time 9274364123 ps
CPU time 30.58 seconds
Started Mar 17 02:14:04 PM PDT 24
Finished Mar 17 02:14:35 PM PDT 24
Peak memory 214428 kb
Host smart-001a9f44-e525-4666-899b-554d2668ad8c
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=957207418 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_t
l_access.957207418
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.3011973727
Short name T176
Test name
Test status
Simulation time 995708137 ps
CPU time 4.86 seconds
Started Mar 17 02:14:03 PM PDT 24
Finished Mar 17 02:14:08 PM PDT 24
Peak memory 205176 kb
Host smart-29acfbf2-b3f2-45a7-8c10-4572e135ab48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011973727 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.3011973727
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.718745761
Short name T150
Test name
Test status
Simulation time 58890090 ps
CPU time 0.78 seconds
Started Mar 17 02:14:11 PM PDT 24
Finished Mar 17 02:14:11 PM PDT 24
Peak memory 204848 kb
Host smart-aebdb30b-94d6-4b0f-a3de-3605734f437a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718745761 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.718745761
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.2879424282
Short name T189
Test name
Test status
Simulation time 19167506765 ps
CPU time 58.71 seconds
Started Mar 17 02:14:09 PM PDT 24
Finished Mar 17 02:15:08 PM PDT 24
Peak memory 213392 kb
Host smart-37a171d4-f02d-41e9-82b9-78b91bb6c908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879424282 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.2879424282
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.4094235682
Short name T209
Test name
Test status
Simulation time 4782821772 ps
CPU time 10.74 seconds
Started Mar 17 02:14:08 PM PDT 24
Finished Mar 17 02:14:19 PM PDT 24
Peak memory 215408 kb
Host smart-2b6cb604-5e12-4917-957e-038ddd0ae76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094235682 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.4094235682
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.722145903
Short name T218
Test name
Test status
Simulation time 1762185708 ps
CPU time 9.89 seconds
Started Mar 17 02:14:13 PM PDT 24
Finished Mar 17 02:14:22 PM PDT 24
Peak memory 213324 kb
Host smart-2d2b472a-4ac0-4743-b917-d6922ec3ad9f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=722145903 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_t
l_access.722145903
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.1095223391
Short name T79
Test name
Test status
Simulation time 4195782788 ps
CPU time 5.24 seconds
Started Mar 17 02:14:08 PM PDT 24
Finished Mar 17 02:14:13 PM PDT 24
Peak memory 205228 kb
Host smart-1b822eab-50b3-4acd-b0f4-d2a1b5274928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095223391 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.1095223391
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.3540391238
Short name T156
Test name
Test status
Simulation time 29204688 ps
CPU time 0.71 seconds
Started Mar 17 02:14:09 PM PDT 24
Finished Mar 17 02:14:10 PM PDT 24
Peak memory 204840 kb
Host smart-93f8cd79-78bd-40af-adaf-528986394611
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540391238 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.3540391238
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.1946061914
Short name T193
Test name
Test status
Simulation time 23426300729 ps
CPU time 41.75 seconds
Started Mar 17 02:14:10 PM PDT 24
Finished Mar 17 02:14:52 PM PDT 24
Peak memory 213444 kb
Host smart-4038d098-2642-4aed-a746-e70c5a3640d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946061914 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.1946061914
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.1005478074
Short name T214
Test name
Test status
Simulation time 2099900187 ps
CPU time 7.53 seconds
Started Mar 17 02:14:10 PM PDT 24
Finished Mar 17 02:14:18 PM PDT 24
Peak memory 205160 kb
Host smart-f9d340a6-0017-4b1c-bece-f011a756d17c
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1005478074 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_
tl_access.1005478074
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.2543574775
Short name T213
Test name
Test status
Simulation time 1441469916 ps
CPU time 4.09 seconds
Started Mar 17 02:14:10 PM PDT 24
Finished Mar 17 02:14:14 PM PDT 24
Peak memory 205088 kb
Host smart-b76045b6-ea0b-4e69-a2b6-1dd87f2e0791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543574775 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.2543574775
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.309894151
Short name T153
Test name
Test status
Simulation time 31755110 ps
CPU time 0.73 seconds
Started Mar 17 02:14:22 PM PDT 24
Finished Mar 17 02:14:23 PM PDT 24
Peak memory 204912 kb
Host smart-1d172553-6f13-48fb-99cc-6b0e3a1176bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309894151 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.309894151
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.2959060349
Short name T19
Test name
Test status
Simulation time 6353000242 ps
CPU time 17.37 seconds
Started Mar 17 02:14:21 PM PDT 24
Finished Mar 17 02:14:39 PM PDT 24
Peak memory 213444 kb
Host smart-068c09ae-55ad-43ad-b0f8-0c15f5864d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959060349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.2959060349
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.3688015184
Short name T178
Test name
Test status
Simulation time 4331357035 ps
CPU time 9.95 seconds
Started Mar 17 02:14:19 PM PDT 24
Finished Mar 17 02:14:29 PM PDT 24
Peak memory 205144 kb
Host smart-f125b41b-c83b-49d8-a374-dc83545cbd25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688015184 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.3688015184
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.4041189941
Short name T208
Test name
Test status
Simulation time 729761372 ps
CPU time 2.5 seconds
Started Mar 17 02:14:11 PM PDT 24
Finished Mar 17 02:14:13 PM PDT 24
Peak memory 205152 kb
Host smart-b8b8ea54-cbba-4c35-95f1-cd6581bfa879
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4041189941 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_
tl_access.4041189941
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.834583465
Short name T167
Test name
Test status
Simulation time 6343147113 ps
CPU time 7.3 seconds
Started Mar 17 02:14:13 PM PDT 24
Finished Mar 17 02:14:20 PM PDT 24
Peak memory 205212 kb
Host smart-39a6b37e-7a6b-4400-9b64-28f9a5250c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834583465 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.834583465
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.3976178944
Short name T70
Test name
Test status
Simulation time 18085334 ps
CPU time 0.77 seconds
Started Mar 17 02:13:39 PM PDT 24
Finished Mar 17 02:13:40 PM PDT 24
Peak memory 204912 kb
Host smart-b9145b16-2338-4c41-92e0-45a89ba9a907
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976178944 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.3976178944
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.3583317220
Short name T1
Test name
Test status
Simulation time 8893791494 ps
CPU time 12.65 seconds
Started Mar 17 02:13:39 PM PDT 24
Finished Mar 17 02:13:53 PM PDT 24
Peak memory 205200 kb
Host smart-9d18f9ab-d295-4d16-83d7-65782c105511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583317220 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.3583317220
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.3369557450
Short name T168
Test name
Test status
Simulation time 5211252316 ps
CPU time 9.5 seconds
Started Mar 17 02:13:40 PM PDT 24
Finished Mar 17 02:13:50 PM PDT 24
Peak memory 205204 kb
Host smart-cd5d26fd-ab32-4d26-81c1-e76eb6bbcd75
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3369557450 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.3369557450
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.3999397727
Short name T228
Test name
Test status
Simulation time 51851296 ps
CPU time 0.83 seconds
Started Mar 17 02:13:46 PM PDT 24
Finished Mar 17 02:13:48 PM PDT 24
Peak memory 204672 kb
Host smart-cb0cc6f1-f289-4add-91db-aa7f090015f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999397727 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.3999397727
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.3659183313
Short name T11
Test name
Test status
Simulation time 2623296588 ps
CPU time 9.19 seconds
Started Mar 17 02:13:41 PM PDT 24
Finished Mar 17 02:13:51 PM PDT 24
Peak memory 205088 kb
Host smart-c81052ae-aaa4-4ab2-9203-ee2979f4caae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659183313 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.3659183313
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.467072156
Short name T24
Test name
Test status
Simulation time 279956390 ps
CPU time 1.24 seconds
Started Mar 17 02:13:41 PM PDT 24
Finished Mar 17 02:13:43 PM PDT 24
Peak memory 229112 kb
Host smart-ed0f438e-3ae5-43a6-8fb4-73be68c37b77
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467072156 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.467072156
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.1446506554
Short name T73
Test name
Test status
Simulation time 17251154 ps
CPU time 0.7 seconds
Started Mar 17 02:14:15 PM PDT 24
Finished Mar 17 02:14:16 PM PDT 24
Peak memory 204832 kb
Host smart-295a2999-371a-4c3e-a8ed-b1b557c91b36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446506554 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.1446506554
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.3461914426
Short name T162
Test name
Test status
Simulation time 44560553 ps
CPU time 0.7 seconds
Started Mar 17 02:14:15 PM PDT 24
Finished Mar 17 02:14:16 PM PDT 24
Peak memory 204880 kb
Host smart-72d88fb3-8839-4c8b-acfd-8b08b2bc7dff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461914426 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.3461914426
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.1229331335
Short name T207
Test name
Test status
Simulation time 74678849 ps
CPU time 0.72 seconds
Started Mar 17 02:14:19 PM PDT 24
Finished Mar 17 02:14:19 PM PDT 24
Peak memory 204876 kb
Host smart-428067fb-95ab-466d-9b73-5eb3c9609245
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229331335 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.1229331335
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_stress_all.1511734870
Short name T137
Test name
Test status
Simulation time 3372513999 ps
CPU time 6.8 seconds
Started Mar 17 02:14:17 PM PDT 24
Finished Mar 17 02:14:24 PM PDT 24
Peak memory 205132 kb
Host smart-c784f7bc-07a9-411b-b2c6-a042ab64d908
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511734870 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.1511734870
Directory /workspace/22.rv_dm_stress_all/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.2518488772
Short name T230
Test name
Test status
Simulation time 85318911 ps
CPU time 0.72 seconds
Started Mar 17 02:14:16 PM PDT 24
Finished Mar 17 02:14:17 PM PDT 24
Peak memory 204788 kb
Host smart-79b431b7-65ce-4758-9a57-0c0b14a55d58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518488772 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.2518488772
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.2796670564
Short name T160
Test name
Test status
Simulation time 24744489 ps
CPU time 0.7 seconds
Started Mar 17 02:14:17 PM PDT 24
Finished Mar 17 02:14:18 PM PDT 24
Peak memory 204812 kb
Host smart-548433c4-4cc3-4068-b66e-988eb7cf42bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796670564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.2796670564
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.2415050002
Short name T159
Test name
Test status
Simulation time 19607623 ps
CPU time 0.72 seconds
Started Mar 17 02:14:18 PM PDT 24
Finished Mar 17 02:14:19 PM PDT 24
Peak memory 204808 kb
Host smart-557140e2-dce9-4573-b2c5-e46beb3097a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415050002 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.2415050002
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.2140798412
Short name T147
Test name
Test status
Simulation time 51619458 ps
CPU time 0.71 seconds
Started Mar 17 02:14:17 PM PDT 24
Finished Mar 17 02:14:18 PM PDT 24
Peak memory 204876 kb
Host smart-f455f78f-6a67-42d6-bce6-56bdd3e81fa6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140798412 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.2140798412
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.1247281321
Short name T72
Test name
Test status
Simulation time 63041897 ps
CPU time 0.72 seconds
Started Mar 17 02:14:20 PM PDT 24
Finished Mar 17 02:14:21 PM PDT 24
Peak memory 204848 kb
Host smart-9e726fc2-4eb1-4781-84d2-0b3ff4e68541
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247281321 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.1247281321
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.2038351787
Short name T157
Test name
Test status
Simulation time 27478902 ps
CPU time 0.74 seconds
Started Mar 17 02:14:20 PM PDT 24
Finished Mar 17 02:14:21 PM PDT 24
Peak memory 204884 kb
Host smart-b985ade1-82ee-457b-94e7-ed93d9fa97f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038351787 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.2038351787
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.3428257484
Short name T51
Test name
Test status
Simulation time 15877274 ps
CPU time 0.73 seconds
Started Mar 17 02:14:21 PM PDT 24
Finished Mar 17 02:14:21 PM PDT 24
Peak memory 204880 kb
Host smart-36c2277c-9b2d-49b6-8af9-50dd26aa039b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428257484 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.3428257484
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.3640547108
Short name T74
Test name
Test status
Simulation time 61374812 ps
CPU time 0.71 seconds
Started Mar 17 02:13:45 PM PDT 24
Finished Mar 17 02:13:46 PM PDT 24
Peak memory 204864 kb
Host smart-8cb38412-a98f-4067-b18a-117b83ab37b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640547108 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.3640547108
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.3293506474
Short name T13
Test name
Test status
Simulation time 274489282 ps
CPU time 1.27 seconds
Started Mar 17 02:13:45 PM PDT 24
Finished Mar 17 02:13:46 PM PDT 24
Peak memory 205172 kb
Host smart-62dd39c0-d84a-4510-9d3b-0fa17a59eb17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293506474 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.3293506474
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.246108003
Short name T223
Test name
Test status
Simulation time 3392309194 ps
CPU time 4.28 seconds
Started Mar 17 02:13:47 PM PDT 24
Finished Mar 17 02:13:52 PM PDT 24
Peak memory 205236 kb
Host smart-4c7a3035-6306-48de-830a-13f125ee0bd5
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=246108003 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_tl
_access.246108003
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.2696766812
Short name T194
Test name
Test status
Simulation time 149975976 ps
CPU time 1.12 seconds
Started Mar 17 02:13:47 PM PDT 24
Finished Mar 17 02:13:48 PM PDT 24
Peak memory 204720 kb
Host smart-cb6e472c-a614-4b01-addb-d2a78cfff127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696766812 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.2696766812
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.1151633578
Short name T201
Test name
Test status
Simulation time 15586374502 ps
CPU time 35.24 seconds
Started Mar 17 02:13:45 PM PDT 24
Finished Mar 17 02:14:20 PM PDT 24
Peak memory 213492 kb
Host smart-70704a85-4c1d-458e-82ef-e62661c756e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151633578 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.1151633578
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.4113410598
Short name T143
Test name
Test status
Simulation time 48911103 ps
CPU time 0.73 seconds
Started Mar 17 02:14:20 PM PDT 24
Finished Mar 17 02:14:21 PM PDT 24
Peak memory 204808 kb
Host smart-d7918185-8460-403f-8294-c0c53dcec19b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113410598 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.4113410598
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.3157906958
Short name T38
Test name
Test status
Simulation time 66318929 ps
CPU time 0.74 seconds
Started Mar 17 02:14:22 PM PDT 24
Finished Mar 17 02:14:23 PM PDT 24
Peak memory 204888 kb
Host smart-8d71ecd4-55f4-48c7-b768-12e05a933732
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157906958 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.3157906958
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.3628371592
Short name T152
Test name
Test status
Simulation time 90502793 ps
CPU time 0.73 seconds
Started Mar 17 02:14:21 PM PDT 24
Finished Mar 17 02:14:22 PM PDT 24
Peak memory 204784 kb
Host smart-aef4ee4e-82c4-4e60-9a98-777ede11a2e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628371592 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.3628371592
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.3358925301
Short name T151
Test name
Test status
Simulation time 46451648 ps
CPU time 0.67 seconds
Started Mar 17 02:14:28 PM PDT 24
Finished Mar 17 02:14:29 PM PDT 24
Peak memory 204904 kb
Host smart-ee2c8675-a8d8-4785-b0d0-3964cbe44e22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358925301 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.3358925301
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.242201222
Short name T39
Test name
Test status
Simulation time 44472094 ps
CPU time 0.68 seconds
Started Mar 17 02:14:28 PM PDT 24
Finished Mar 17 02:14:29 PM PDT 24
Peak memory 204856 kb
Host smart-9d442c0e-3b2a-4b8d-935c-6df150ba00dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242201222 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.242201222
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.3155848921
Short name T26
Test name
Test status
Simulation time 35566102 ps
CPU time 0.7 seconds
Started Mar 17 02:14:33 PM PDT 24
Finished Mar 17 02:14:34 PM PDT 24
Peak memory 204888 kb
Host smart-9a592484-38b0-470d-a626-02304ea428b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155848921 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.3155848921
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_stress_all.1719370616
Short name T17
Test name
Test status
Simulation time 13014808799 ps
CPU time 22.1 seconds
Started Mar 17 02:14:27 PM PDT 24
Finished Mar 17 02:14:49 PM PDT 24
Peak memory 213296 kb
Host smart-4e04890b-8a25-49eb-b7bd-b73f8b36b813
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719370616 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.1719370616
Directory /workspace/35.rv_dm_stress_all/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.1777442641
Short name T28
Test name
Test status
Simulation time 19789301 ps
CPU time 0.71 seconds
Started Mar 17 02:14:26 PM PDT 24
Finished Mar 17 02:14:27 PM PDT 24
Peak memory 204888 kb
Host smart-7d80cb11-c224-40d4-be62-ba8f56b99c92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777442641 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.1777442641
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.2551588079
Short name T40
Test name
Test status
Simulation time 39716329 ps
CPU time 0.75 seconds
Started Mar 17 02:14:32 PM PDT 24
Finished Mar 17 02:14:34 PM PDT 24
Peak memory 204848 kb
Host smart-074d975b-f31a-417d-896b-bfa70ea4a8c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551588079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.2551588079
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.1306307502
Short name T224
Test name
Test status
Simulation time 45825720 ps
CPU time 0.73 seconds
Started Mar 17 02:13:51 PM PDT 24
Finished Mar 17 02:13:51 PM PDT 24
Peak memory 204896 kb
Host smart-3e147063-c6c3-49f7-9da6-aa3eda3744fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306307502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.1306307502
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.3075654268
Short name T48
Test name
Test status
Simulation time 101816729 ps
CPU time 0.73 seconds
Started Mar 17 02:13:47 PM PDT 24
Finished Mar 17 02:13:48 PM PDT 24
Peak memory 204688 kb
Host smart-c964317d-b95a-4c26-9cc7-dd82e0e3c220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075654268 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.3075654268
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.3868865731
Short name T229
Test name
Test status
Simulation time 8654721174 ps
CPU time 32.49 seconds
Started Mar 17 02:13:44 PM PDT 24
Finished Mar 17 02:14:17 PM PDT 24
Peak memory 205188 kb
Host smart-ca4fa666-43ef-419c-9293-66c13ece69ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868865731 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.3868865731
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.3495379662
Short name T43
Test name
Test status
Simulation time 78821453 ps
CPU time 1.13 seconds
Started Mar 17 02:13:56 PM PDT 24
Finished Mar 17 02:13:57 PM PDT 24
Peak memory 229372 kb
Host smart-7f54e341-5519-44ef-a707-aa5b81e9b928
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495379662 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.3495379662
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.3433140451
Short name T119
Test name
Test status
Simulation time 205192566 ps
CPU time 0.71 seconds
Started Mar 17 02:14:33 PM PDT 24
Finished Mar 17 02:14:35 PM PDT 24
Peak memory 204880 kb
Host smart-15dfd025-1f5f-4f62-afe2-a92e82797a15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433140451 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.3433140451
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.659739312
Short name T164
Test name
Test status
Simulation time 46658617 ps
CPU time 0.72 seconds
Started Mar 17 02:14:33 PM PDT 24
Finished Mar 17 02:14:35 PM PDT 24
Peak memory 204784 kb
Host smart-483c729f-06e5-4f64-b6d2-8e10ac7e5337
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659739312 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.659739312
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_stress_all.603523548
Short name T138
Test name
Test status
Simulation time 3621167215 ps
CPU time 13.52 seconds
Started Mar 17 02:14:32 PM PDT 24
Finished Mar 17 02:14:46 PM PDT 24
Peak memory 205212 kb
Host smart-8621af2b-8383-48ae-b513-d2eb1d137e8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603523548 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.603523548
Directory /workspace/41.rv_dm_stress_all/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.3662122986
Short name T149
Test name
Test status
Simulation time 109993049 ps
CPU time 0.73 seconds
Started Mar 17 02:14:31 PM PDT 24
Finished Mar 17 02:14:32 PM PDT 24
Peak memory 204876 kb
Host smart-ac10f002-380b-4eec-8d19-d5ad87220658
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662122986 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.3662122986
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.1639034101
Short name T50
Test name
Test status
Simulation time 66680848 ps
CPU time 0.71 seconds
Started Mar 17 02:14:45 PM PDT 24
Finished Mar 17 02:14:47 PM PDT 24
Peak memory 204800 kb
Host smart-bf0ce4a5-e4f1-4512-b59a-6c39a1d05707
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639034101 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.1639034101
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_stress_all.2677584804
Short name T29
Test name
Test status
Simulation time 761131311 ps
CPU time 3.7 seconds
Started Mar 17 02:14:33 PM PDT 24
Finished Mar 17 02:14:38 PM PDT 24
Peak memory 205004 kb
Host smart-e137f9c9-9fb3-467b-bab3-b6073ad91fe4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677584804 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.2677584804
Directory /workspace/43.rv_dm_stress_all/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.2826557048
Short name T49
Test name
Test status
Simulation time 24091107 ps
CPU time 0.75 seconds
Started Mar 17 02:14:38 PM PDT 24
Finished Mar 17 02:14:39 PM PDT 24
Peak memory 204800 kb
Host smart-871f3d28-4206-4641-99eb-4b9056e151b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826557048 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.2826557048
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.711619798
Short name T75
Test name
Test status
Simulation time 70044307 ps
CPU time 0.73 seconds
Started Mar 17 02:14:42 PM PDT 24
Finished Mar 17 02:14:43 PM PDT 24
Peak memory 204836 kb
Host smart-b5f5ee7b-2129-44aa-8951-b707ef316a1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711619798 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.711619798
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.3749408476
Short name T52
Test name
Test status
Simulation time 19233287 ps
CPU time 0.73 seconds
Started Mar 17 02:14:39 PM PDT 24
Finished Mar 17 02:14:39 PM PDT 24
Peak memory 204824 kb
Host smart-bb2b42f5-e198-4ecc-b2d2-1392e25f8ac5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749408476 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.3749408476
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.4225698974
Short name T141
Test name
Test status
Simulation time 26184115 ps
CPU time 0.78 seconds
Started Mar 17 02:14:45 PM PDT 24
Finished Mar 17 02:14:46 PM PDT 24
Peak memory 204800 kb
Host smart-66a7b53e-8ea7-44d6-b5db-19d210b8ab32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225698974 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.4225698974
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.2159351604
Short name T154
Test name
Test status
Simulation time 20405225 ps
CPU time 0.72 seconds
Started Mar 17 02:14:43 PM PDT 24
Finished Mar 17 02:14:44 PM PDT 24
Peak memory 204812 kb
Host smart-3ea22e74-e002-4eeb-b09f-a7dfce6334fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159351604 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.2159351604
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.2989133693
Short name T170
Test name
Test status
Simulation time 48680341 ps
CPU time 0.76 seconds
Started Mar 17 02:14:38 PM PDT 24
Finished Mar 17 02:14:39 PM PDT 24
Peak memory 204776 kb
Host smart-6c6cec78-520d-4ca8-b3b3-29403bf42784
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989133693 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.2989133693
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.1391315541
Short name T144
Test name
Test status
Simulation time 40445143 ps
CPU time 0.67 seconds
Started Mar 17 02:13:51 PM PDT 24
Finished Mar 17 02:13:52 PM PDT 24
Peak memory 204840 kb
Host smart-1105adb1-1c3c-4d48-8ad7-b22e1b798134
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391315541 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.1391315541
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.3141470353
Short name T184
Test name
Test status
Simulation time 1487473520 ps
CPU time 4.34 seconds
Started Mar 17 02:13:54 PM PDT 24
Finished Mar 17 02:13:58 PM PDT 24
Peak memory 205200 kb
Host smart-87ce63e3-b3de-44c8-aa0d-766c3b4c6a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141470353 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.3141470353
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.2507527982
Short name T174
Test name
Test status
Simulation time 361456819 ps
CPU time 1.26 seconds
Started Mar 17 02:14:00 PM PDT 24
Finished Mar 17 02:14:01 PM PDT 24
Peak memory 205176 kb
Host smart-c76fec8f-1d93-428f-98d3-030ba602fd50
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2507527982 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t
l_access.2507527982
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.4123499529
Short name T206
Test name
Test status
Simulation time 3969525695 ps
CPU time 14.94 seconds
Started Mar 17 02:13:53 PM PDT 24
Finished Mar 17 02:14:08 PM PDT 24
Peak memory 205300 kb
Host smart-d96333a1-ccf0-4895-8ae1-3df1dbe7c503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123499529 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.4123499529
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.2610999244
Short name T146
Test name
Test status
Simulation time 51540292 ps
CPU time 0.72 seconds
Started Mar 17 02:13:52 PM PDT 24
Finished Mar 17 02:13:54 PM PDT 24
Peak memory 204844 kb
Host smart-60a42d9e-5ca4-48d8-8c7c-7abb980cfc15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610999244 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.2610999244
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.247133479
Short name T180
Test name
Test status
Simulation time 2633211717 ps
CPU time 13.43 seconds
Started Mar 17 02:13:59 PM PDT 24
Finished Mar 17 02:14:13 PM PDT 24
Peak memory 205416 kb
Host smart-e70ea49f-903b-4651-bd90-c4badff8e7dc
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=247133479 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_tl
_access.247133479
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.2648427840
Short name T192
Test name
Test status
Simulation time 6176674638 ps
CPU time 21.8 seconds
Started Mar 17 02:13:58 PM PDT 24
Finished Mar 17 02:14:20 PM PDT 24
Peak memory 204940 kb
Host smart-fcc1b080-0504-405a-aff0-aed2d41fd0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648427840 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.2648427840
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.3376159766
Short name T161
Test name
Test status
Simulation time 78517453 ps
CPU time 0.73 seconds
Started Mar 17 02:13:55 PM PDT 24
Finished Mar 17 02:13:56 PM PDT 24
Peak memory 204836 kb
Host smart-197de86d-e0ce-4dc0-80df-ccb363142df2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376159766 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.3376159766
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.122878197
Short name T172
Test name
Test status
Simulation time 7230176769 ps
CPU time 9.31 seconds
Started Mar 17 02:13:53 PM PDT 24
Finished Mar 17 02:14:03 PM PDT 24
Peak memory 213548 kb
Host smart-2fc69870-9d43-40b9-b5e4-804f0c8ceadc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122878197 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.122878197
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.1375408649
Short name T199
Test name
Test status
Simulation time 656541409 ps
CPU time 2.89 seconds
Started Mar 17 02:13:51 PM PDT 24
Finished Mar 17 02:13:54 PM PDT 24
Peak memory 205108 kb
Host smart-db39ff95-435b-4945-87d6-1ca18b44fa88
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1375408649 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.1375408649
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.826801517
Short name T195
Test name
Test status
Simulation time 15087260225 ps
CPU time 46.16 seconds
Started Mar 17 02:13:51 PM PDT 24
Finished Mar 17 02:14:38 PM PDT 24
Peak memory 213424 kb
Host smart-74e2690f-87ef-4339-93ee-e12014620fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826801517 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.826801517
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.3914067420
Short name T142
Test name
Test status
Simulation time 21656807 ps
CPU time 0.73 seconds
Started Mar 17 02:13:52 PM PDT 24
Finished Mar 17 02:13:53 PM PDT 24
Peak memory 204904 kb
Host smart-27d5b8bb-e074-4fe7-a251-d3ecd4813eec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914067420 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.3914067420
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.259361960
Short name T226
Test name
Test status
Simulation time 9564156170 ps
CPU time 15.03 seconds
Started Mar 17 02:13:52 PM PDT 24
Finished Mar 17 02:14:07 PM PDT 24
Peak memory 205292 kb
Host smart-a62c4b75-6c61-4853-9168-c6c945c6d8ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259361960 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.259361960
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.2990581821
Short name T169
Test name
Test status
Simulation time 3295778191 ps
CPU time 7.71 seconds
Started Mar 17 02:13:54 PM PDT 24
Finished Mar 17 02:14:02 PM PDT 24
Peak memory 213440 kb
Host smart-0d623e31-0ae7-4712-bfd3-9ac0ecfc3c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990581821 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.2990581821
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.3672324822
Short name T219
Test name
Test status
Simulation time 2474620136 ps
CPU time 12.71 seconds
Started Mar 17 02:13:52 PM PDT 24
Finished Mar 17 02:14:06 PM PDT 24
Peak memory 205172 kb
Host smart-7f1b5ade-1442-4c5e-9fa4-c2c337484274
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3672324822 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t
l_access.3672324822
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.3625416257
Short name T196
Test name
Test status
Simulation time 1115915943 ps
CPU time 2.98 seconds
Started Mar 17 02:13:57 PM PDT 24
Finished Mar 17 02:14:00 PM PDT 24
Peak memory 205172 kb
Host smart-46b0d429-8297-488d-8aac-409cfffbfcfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625416257 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.3625416257
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.632761868
Short name T148
Test name
Test status
Simulation time 91788247 ps
CPU time 0.71 seconds
Started Mar 17 02:13:59 PM PDT 24
Finished Mar 17 02:13:59 PM PDT 24
Peak memory 204808 kb
Host smart-92941232-d600-4f7b-9761-655ff5107bbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632761868 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.632761868
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.1948147204
Short name T183
Test name
Test status
Simulation time 8536560613 ps
CPU time 31.83 seconds
Started Mar 17 02:13:52 PM PDT 24
Finished Mar 17 02:14:24 PM PDT 24
Peak memory 213456 kb
Host smart-dd5002ea-49c4-4d1d-9f3c-ea0a59e3fbd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948147204 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.1948147204
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.1839283610
Short name T185
Test name
Test status
Simulation time 11957147760 ps
CPU time 12.99 seconds
Started Mar 17 02:14:00 PM PDT 24
Finished Mar 17 02:14:13 PM PDT 24
Peak memory 214764 kb
Host smart-91e12463-6710-4606-aedb-4032a90561b7
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1839283610 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t
l_access.1839283610
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest
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