Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
80.45 94.44 80.05 87.69 78.21 83.66 97.89 41.19


Total test records in report: 376
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html
T273 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.3439432220 Mar 19 02:55:47 PM PDT 24 Mar 19 02:55:52 PM PDT 24 223426648 ps
T106 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.4197998123 Mar 19 02:55:31 PM PDT 24 Mar 19 02:55:33 PM PDT 24 547403644 ps
T111 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.338472563 Mar 19 02:55:01 PM PDT 24 Mar 19 02:55:06 PM PDT 24 3237265011 ps
T274 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2189687149 Mar 19 02:54:55 PM PDT 24 Mar 19 02:54:57 PM PDT 24 289225373 ps
T275 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.1655943375 Mar 19 02:54:58 PM PDT 24 Mar 19 02:55:04 PM PDT 24 642576241 ps
T276 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.2193588324 Mar 19 02:55:33 PM PDT 24 Mar 19 02:55:38 PM PDT 24 1313827475 ps
T277 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.886567741 Mar 19 02:55:33 PM PDT 24 Mar 19 02:55:35 PM PDT 24 192445232 ps
T107 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.2584905848 Mar 19 02:55:24 PM PDT 24 Mar 19 02:55:27 PM PDT 24 372833401 ps
T123 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.552768 Mar 19 02:55:38 PM PDT 24 Mar 19 02:55:49 PM PDT 24 561622224 ps
T278 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2075840012 Mar 19 02:55:13 PM PDT 24 Mar 19 02:55:22 PM PDT 24 854037598 ps
T133 /workspace/coverage/cover_reg_top/35.rv_dm_tap_fsm_rand_reset.2409379036 Mar 19 02:55:42 PM PDT 24 Mar 19 02:55:59 PM PDT 24 4869471114 ps
T279 /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.1427219253 Mar 19 02:55:16 PM PDT 24 Mar 19 02:55:29 PM PDT 24 7323290980 ps
T280 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.419265379 Mar 19 02:55:01 PM PDT 24 Mar 19 02:55:02 PM PDT 24 793013752 ps
T119 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.1140872867 Mar 19 02:55:31 PM PDT 24 Mar 19 02:55:35 PM PDT 24 500254072 ps
T108 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.89417532 Mar 19 02:55:03 PM PDT 24 Mar 19 02:55:39 PM PDT 24 28650070566 ps
T281 /workspace/coverage/cover_reg_top/30.rv_dm_tap_fsm_rand_reset.1726062190 Mar 19 02:55:39 PM PDT 24 Mar 19 02:55:50 PM PDT 24 11659354632 ps
T93 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2354461847 Mar 19 02:54:54 PM PDT 24 Mar 19 02:54:59 PM PDT 24 1277588995 ps
T128 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.1094725970 Mar 19 02:55:05 PM PDT 24 Mar 19 02:55:15 PM PDT 24 2263279484 ps
T282 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3119811406 Mar 19 02:55:34 PM PDT 24 Mar 19 02:55:36 PM PDT 24 1082646828 ps
T99 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.871801535 Mar 19 02:55:38 PM PDT 24 Mar 19 02:55:42 PM PDT 24 871813745 ps
T283 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.2905093051 Mar 19 02:55:32 PM PDT 24 Mar 19 02:55:35 PM PDT 24 373728428 ps
T284 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.4191129116 Mar 19 02:55:12 PM PDT 24 Mar 19 02:55:14 PM PDT 24 152738087 ps
T285 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.770571801 Mar 19 02:54:52 PM PDT 24 Mar 19 02:55:16 PM PDT 24 9731694972 ps
T286 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.1342850750 Mar 19 02:55:06 PM PDT 24 Mar 19 02:55:29 PM PDT 24 6797504666 ps
T287 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1947573860 Mar 19 02:55:09 PM PDT 24 Mar 19 02:55:19 PM PDT 24 578289915 ps
T288 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.3680492157 Mar 19 02:54:58 PM PDT 24 Mar 19 02:56:28 PM PDT 24 43013717693 ps
T289 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.1806734889 Mar 19 02:55:18 PM PDT 24 Mar 19 02:55:22 PM PDT 24 2279870411 ps
T290 /workspace/coverage/cover_reg_top/26.rv_dm_tap_fsm_rand_reset.596937642 Mar 19 02:55:41 PM PDT 24 Mar 19 02:56:02 PM PDT 24 5499462867 ps
T291 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2893076922 Mar 19 02:55:17 PM PDT 24 Mar 19 02:55:18 PM PDT 24 45755256 ps
T109 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1110742264 Mar 19 02:55:21 PM PDT 24 Mar 19 02:55:23 PM PDT 24 57740712 ps
T292 /workspace/coverage/cover_reg_top/14.rv_dm_tap_fsm_rand_reset.2983751347 Mar 19 02:55:29 PM PDT 24 Mar 19 02:55:43 PM PDT 24 16139404353 ps
T293 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2224406914 Mar 19 02:55:10 PM PDT 24 Mar 19 02:55:11 PM PDT 24 102642390 ps
T294 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2425901780 Mar 19 02:55:04 PM PDT 24 Mar 19 02:55:40 PM PDT 24 5110335101 ps
T100 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.29917808 Mar 19 02:55:38 PM PDT 24 Mar 19 02:55:40 PM PDT 24 75877375 ps
T295 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.3461284254 Mar 19 02:54:53 PM PDT 24 Mar 19 02:54:53 PM PDT 24 139835425 ps
T296 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.547281396 Mar 19 02:55:05 PM PDT 24 Mar 19 02:55:06 PM PDT 24 86238298 ps
T297 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.516349237 Mar 19 02:55:39 PM PDT 24 Mar 19 02:55:42 PM PDT 24 59550629 ps
T298 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3090915405 Mar 19 02:55:08 PM PDT 24 Mar 19 02:55:09 PM PDT 24 334556635 ps
T299 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1106420868 Mar 19 02:54:58 PM PDT 24 Mar 19 02:55:01 PM PDT 24 2603918670 ps
T130 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.1551206089 Mar 19 02:55:16 PM PDT 24 Mar 19 02:55:37 PM PDT 24 9340847609 ps
T300 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2379415542 Mar 19 02:55:08 PM PDT 24 Mar 19 02:55:12 PM PDT 24 170134637 ps
T301 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.2591397997 Mar 19 02:55:08 PM PDT 24 Mar 19 02:55:11 PM PDT 24 83227190 ps
T302 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3617918288 Mar 19 02:54:50 PM PDT 24 Mar 19 02:54:51 PM PDT 24 67682963 ps
T303 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.905613692 Mar 19 02:55:25 PM PDT 24 Mar 19 02:55:30 PM PDT 24 278120790 ps
T304 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3517613831 Mar 19 02:55:24 PM PDT 24 Mar 19 02:55:28 PM PDT 24 888851474 ps
T305 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2709943700 Mar 19 02:55:41 PM PDT 24 Mar 19 02:55:43 PM PDT 24 33109297 ps
T306 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.2839078926 Mar 19 02:55:03 PM PDT 24 Mar 19 02:55:05 PM PDT 24 88711942 ps
T307 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.2513583967 Mar 19 02:54:52 PM PDT 24 Mar 19 02:56:10 PM PDT 24 17381951088 ps
T308 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.1423509982 Mar 19 02:55:11 PM PDT 24 Mar 19 02:55:21 PM PDT 24 3977832237 ps
T309 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.2793197187 Mar 19 02:55:40 PM PDT 24 Mar 19 02:55:42 PM PDT 24 45537950 ps
T310 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.1256639253 Mar 19 02:54:51 PM PDT 24 Mar 19 02:54:52 PM PDT 24 43726865 ps
T311 /workspace/coverage/cover_reg_top/33.rv_dm_tap_fsm_rand_reset.3740648955 Mar 19 02:55:37 PM PDT 24 Mar 19 02:55:50 PM PDT 24 6628336786 ps
T312 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.2157144673 Mar 19 02:55:10 PM PDT 24 Mar 19 02:55:14 PM PDT 24 662143951 ps
T110 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1201843344 Mar 19 02:55:12 PM PDT 24 Mar 19 02:55:14 PM PDT 24 220453013 ps
T313 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.1170760024 Mar 19 02:55:30 PM PDT 24 Mar 19 02:55:37 PM PDT 24 1212242651 ps
T314 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.3399223015 Mar 19 02:55:18 PM PDT 24 Mar 19 02:55:22 PM PDT 24 214582928 ps
T101 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.306929989 Mar 19 02:55:05 PM PDT 24 Mar 19 02:55:06 PM PDT 24 153588998 ps
T315 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.4084931613 Mar 19 02:54:55 PM PDT 24 Mar 19 02:54:56 PM PDT 24 26551404 ps
T316 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.3257453367 Mar 19 02:55:24 PM PDT 24 Mar 19 02:55:27 PM PDT 24 37376562 ps
T127 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1043383342 Mar 19 02:55:24 PM PDT 24 Mar 19 02:55:41 PM PDT 24 1299073425 ps
T317 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.1942997764 Mar 19 02:54:49 PM PDT 24 Mar 19 02:55:26 PM PDT 24 6929588012 ps
T122 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3676132048 Mar 19 02:55:25 PM PDT 24 Mar 19 02:55:45 PM PDT 24 3099534734 ps
T318 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2682873211 Mar 19 02:55:19 PM PDT 24 Mar 19 02:55:27 PM PDT 24 546862073 ps
T319 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.609304175 Mar 19 02:55:04 PM PDT 24 Mar 19 02:56:20 PM PDT 24 37526630675 ps
T320 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1326984248 Mar 19 02:54:51 PM PDT 24 Mar 19 02:54:55 PM PDT 24 642883993 ps
T321 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1014954454 Mar 19 02:55:09 PM PDT 24 Mar 19 02:55:10 PM PDT 24 362028155 ps
T322 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2674397019 Mar 19 02:55:04 PM PDT 24 Mar 19 02:55:21 PM PDT 24 5478428893 ps
T323 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1400417546 Mar 19 02:55:36 PM PDT 24 Mar 19 02:55:44 PM PDT 24 2869015970 ps
T324 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.2901356775 Mar 19 02:54:58 PM PDT 24 Mar 19 02:55:19 PM PDT 24 15347621689 ps
T325 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.4195134201 Mar 19 02:54:59 PM PDT 24 Mar 19 02:55:34 PM PDT 24 4402340561 ps
T326 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.3019938104 Mar 19 02:55:06 PM PDT 24 Mar 19 02:55:07 PM PDT 24 116609287 ps
T327 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.2664093751 Mar 19 02:55:04 PM PDT 24 Mar 19 02:55:05 PM PDT 24 53126073 ps
T328 /workspace/coverage/cover_reg_top/27.rv_dm_tap_fsm_rand_reset.2754721089 Mar 19 02:55:44 PM PDT 24 Mar 19 02:56:03 PM PDT 24 4406743036 ps
T329 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.1122024859 Mar 19 02:54:55 PM PDT 24 Mar 19 02:55:00 PM PDT 24 379408428 ps
T330 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.1261693364 Mar 19 02:54:59 PM PDT 24 Mar 19 02:55:01 PM PDT 24 97754974 ps
T331 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.3209268954 Mar 19 02:54:58 PM PDT 24 Mar 19 02:55:01 PM PDT 24 132331797 ps
T332 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.1015979956 Mar 19 02:55:18 PM PDT 24 Mar 19 02:55:20 PM PDT 24 310770881 ps
T126 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.1509340419 Mar 19 02:55:40 PM PDT 24 Mar 19 02:55:56 PM PDT 24 446550854 ps
T333 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.1081223179 Mar 19 02:54:58 PM PDT 24 Mar 19 02:54:58 PM PDT 24 18414314 ps
T102 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1264143201 Mar 19 02:55:29 PM PDT 24 Mar 19 02:55:37 PM PDT 24 544081981 ps
T334 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.2596835387 Mar 19 02:55:19 PM PDT 24 Mar 19 02:55:35 PM PDT 24 3806310057 ps
T335 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3700471871 Mar 19 02:55:25 PM PDT 24 Mar 19 02:55:26 PM PDT 24 73739261 ps
T336 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2687690220 Mar 19 02:55:34 PM PDT 24 Mar 19 02:55:35 PM PDT 24 45935504 ps
T124 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3366574805 Mar 19 02:55:41 PM PDT 24 Mar 19 02:56:02 PM PDT 24 8510923954 ps
T337 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.2041042282 Mar 19 02:54:52 PM PDT 24 Mar 19 02:55:24 PM PDT 24 8089607969 ps
T338 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.988217262 Mar 19 02:55:22 PM PDT 24 Mar 19 02:55:26 PM PDT 24 724179619 ps
T339 /workspace/coverage/cover_reg_top/15.rv_dm_tap_fsm_rand_reset.294149510 Mar 19 02:55:34 PM PDT 24 Mar 19 02:55:56 PM PDT 24 30659484782 ps
T340 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.3458068610 Mar 19 02:55:31 PM PDT 24 Mar 19 02:55:33 PM PDT 24 284451234 ps
T341 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.797996247 Mar 19 02:55:12 PM PDT 24 Mar 19 02:55:14 PM PDT 24 127957379 ps
T342 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.3344397086 Mar 19 02:55:05 PM PDT 24 Mar 19 02:55:09 PM PDT 24 2232735411 ps
T343 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1334044923 Mar 19 02:55:02 PM PDT 24 Mar 19 02:55:04 PM PDT 24 88177948 ps
T344 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.1295353468 Mar 19 02:54:58 PM PDT 24 Mar 19 02:55:00 PM PDT 24 94263361 ps
T345 /workspace/coverage/cover_reg_top/32.rv_dm_tap_fsm_rand_reset.120566779 Mar 19 02:55:45 PM PDT 24 Mar 19 02:56:22 PM PDT 24 10907177831 ps
T346 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.2241304656 Mar 19 02:55:28 PM PDT 24 Mar 19 02:55:31 PM PDT 24 90735044 ps
T347 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.4185362773 Mar 19 02:55:42 PM PDT 24 Mar 19 02:55:44 PM PDT 24 409485149 ps
T348 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.1596672380 Mar 19 02:54:51 PM PDT 24 Mar 19 02:54:53 PM PDT 24 179873986 ps
T349 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1197967257 Mar 19 02:55:03 PM PDT 24 Mar 19 02:55:04 PM PDT 24 182964319 ps
T350 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.1891095090 Mar 19 02:55:17 PM PDT 24 Mar 19 02:55:34 PM PDT 24 632125433 ps
T351 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.584642614 Mar 19 02:55:28 PM PDT 24 Mar 19 02:55:47 PM PDT 24 1983660950 ps
T103 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.336662460 Mar 19 02:55:19 PM PDT 24 Mar 19 02:55:21 PM PDT 24 269571321 ps
T352 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2655624127 Mar 19 02:55:04 PM PDT 24 Mar 19 02:55:05 PM PDT 24 81878902 ps
T353 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.1850306981 Mar 19 02:55:05 PM PDT 24 Mar 19 02:55:12 PM PDT 24 3075996667 ps
T354 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1616236539 Mar 19 02:55:09 PM PDT 24 Mar 19 02:55:17 PM PDT 24 508906963 ps
T355 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1617489276 Mar 19 02:55:18 PM PDT 24 Mar 19 02:55:19 PM PDT 24 187172390 ps
T356 /workspace/coverage/cover_reg_top/17.rv_dm_tap_fsm_rand_reset.3467597702 Mar 19 02:55:31 PM PDT 24 Mar 19 02:55:44 PM PDT 24 13182355694 ps
T357 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2412384053 Mar 19 02:55:33 PM PDT 24 Mar 19 02:55:35 PM PDT 24 349670170 ps
T358 /workspace/coverage/cover_reg_top/13.rv_dm_tap_fsm_rand_reset.3984002579 Mar 19 02:55:31 PM PDT 24 Mar 19 02:55:59 PM PDT 24 8910212863 ps
T129 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.1926030239 Mar 19 02:55:02 PM PDT 24 Mar 19 02:55:17 PM PDT 24 437405570 ps
T359 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2804022978 Mar 19 02:55:05 PM PDT 24 Mar 19 02:55:21 PM PDT 24 3165604882 ps
T360 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.343664238 Mar 19 02:55:22 PM PDT 24 Mar 19 02:55:25 PM PDT 24 111266729 ps
T361 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.405551708 Mar 19 02:55:01 PM PDT 24 Mar 19 02:55:01 PM PDT 24 26628954 ps
T362 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.791877107 Mar 19 02:55:15 PM PDT 24 Mar 19 02:55:20 PM PDT 24 517133294 ps
T363 /workspace/coverage/cover_reg_top/11.rv_dm_tap_fsm_rand_reset.1093415304 Mar 19 02:55:25 PM PDT 24 Mar 19 02:55:42 PM PDT 24 9464965559 ps
T364 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1595920909 Mar 19 02:55:18 PM PDT 24 Mar 19 02:55:19 PM PDT 24 73868482 ps
T365 /workspace/coverage/cover_reg_top/31.rv_dm_tap_fsm_rand_reset.1737254167 Mar 19 02:55:38 PM PDT 24 Mar 19 02:55:50 PM PDT 24 5460342521 ps
T366 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.985789998 Mar 19 02:55:35 PM PDT 24 Mar 19 02:55:36 PM PDT 24 47747379 ps
T367 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1620914064 Mar 19 02:55:33 PM PDT 24 Mar 19 02:55:35 PM PDT 24 783298847 ps
T368 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.4289967796 Mar 19 02:55:24 PM PDT 24 Mar 19 02:55:29 PM PDT 24 75129576 ps
T369 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.1967615660 Mar 19 02:54:51 PM PDT 24 Mar 19 02:54:53 PM PDT 24 80974833 ps
T370 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.1852433913 Mar 19 02:55:07 PM PDT 24 Mar 19 02:55:08 PM PDT 24 63360963 ps
T371 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1126966417 Mar 19 02:55:29 PM PDT 24 Mar 19 02:55:46 PM PDT 24 735943229 ps
T372 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.88647970 Mar 19 02:55:09 PM PDT 24 Mar 19 02:55:11 PM PDT 24 407741047 ps
T373 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.3930632036 Mar 19 02:55:07 PM PDT 24 Mar 19 02:55:11 PM PDT 24 108194095 ps
T374 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.1832060140 Mar 19 02:55:25 PM PDT 24 Mar 19 02:55:26 PM PDT 24 108684097 ps
T375 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.3770076539 Mar 19 02:54:51 PM PDT 24 Mar 19 02:54:55 PM PDT 24 1038132614 ps
T376 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.551994433 Mar 19 02:55:25 PM PDT 24 Mar 19 02:55:27 PM PDT 24 241998407 ps

Test location /workspace/coverage/default/45.rv_dm_stress_all.1182147709
Short name T1
Test name
Test status
Simulation time 1335482940 ps
CPU time 5.2 seconds
Started Mar 19 02:44:10 PM PDT 24
Finished Mar 19 02:44:15 PM PDT 24
Peak memory 205000 kb
Host smart-bcd5557f-7b74-4fd6-a1dd-874cb5a1b6f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182147709 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.1182147709
Directory /workspace/45.rv_dm_stress_all/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.1428741572
Short name T90
Test name
Test status
Simulation time 10956696532 ps
CPU time 15.8 seconds
Started Mar 19 02:43:55 PM PDT 24
Finished Mar 19 02:44:11 PM PDT 24
Peak memory 215600 kb
Host smart-fe76d867-0e20-4de4-83d9-91be0b88d437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428741572 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.1428741572
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.3250871341
Short name T36
Test name
Test status
Simulation time 3822475786 ps
CPU time 6.84 seconds
Started Mar 19 02:55:39 PM PDT 24
Finished Mar 19 02:55:46 PM PDT 24
Peak memory 218692 kb
Host smart-fd8447ef-eb72-4f01-af92-143aecebf3c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250871341 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.3250871341
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.103890226
Short name T66
Test name
Test status
Simulation time 1479973757 ps
CPU time 3.71 seconds
Started Mar 19 02:43:21 PM PDT 24
Finished Mar 19 02:43:25 PM PDT 24
Peak memory 204996 kb
Host smart-a8d5b14c-8b41-4036-842d-2847660aedb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103890226 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.103890226
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.1181322590
Short name T31
Test name
Test status
Simulation time 38543454 ps
CPU time 0.73 seconds
Started Mar 19 02:44:10 PM PDT 24
Finished Mar 19 02:44:11 PM PDT 24
Peak memory 204784 kb
Host smart-cafbb70b-33af-4887-93a0-f32501ac95f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181322590 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.1181322590
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.1394542449
Short name T61
Test name
Test status
Simulation time 470491514 ps
CPU time 1.26 seconds
Started Mar 19 02:43:23 PM PDT 24
Finished Mar 19 02:43:25 PM PDT 24
Peak memory 205004 kb
Host smart-a5b99455-d07d-4521-b0ec-3794a5e704c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394542449 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.1394542449
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.966514895
Short name T75
Test name
Test status
Simulation time 487609576 ps
CPU time 5.59 seconds
Started Mar 19 02:55:29 PM PDT 24
Finished Mar 19 02:55:36 PM PDT 24
Peak memory 212984 kb
Host smart-6bb9f138-adef-471d-a821-cc56617da333
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966514895 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.966514895
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/30.rv_dm_stress_all.3976079430
Short name T9
Test name
Test status
Simulation time 3938215113 ps
CPU time 7.48 seconds
Started Mar 19 02:44:05 PM PDT 24
Finished Mar 19 02:44:13 PM PDT 24
Peak memory 205132 kb
Host smart-38049dc0-305e-4ce7-9f88-89dd3ef396c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976079430 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.3976079430
Directory /workspace/30.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.3200180561
Short name T10
Test name
Test status
Simulation time 3433420388 ps
CPU time 13.25 seconds
Started Mar 19 02:43:17 PM PDT 24
Finished Mar 19 02:43:30 PM PDT 24
Peak memory 214476 kb
Host smart-1faabf2e-e3de-4865-8c63-ae3968cb1106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200180561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.3200180561
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.2689956637
Short name T121
Test name
Test status
Simulation time 1949304889 ps
CPU time 19.37 seconds
Started Mar 19 02:55:23 PM PDT 24
Finished Mar 19 02:55:43 PM PDT 24
Peak memory 217600 kb
Host smart-ffa6672a-8b7a-4656-8c45-8dc8fffb04a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689956637 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.2
689956637
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.3337655247
Short name T17
Test name
Test status
Simulation time 581532866 ps
CPU time 2.66 seconds
Started Mar 19 02:43:30 PM PDT 24
Finished Mar 19 02:43:33 PM PDT 24
Peak memory 205036 kb
Host smart-ca53b4a8-7cd5-4111-ad14-bd5061275b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337655247 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.3337655247
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.2284634073
Short name T41
Test name
Test status
Simulation time 1664827463 ps
CPU time 8.12 seconds
Started Mar 19 02:55:23 PM PDT 24
Finished Mar 19 02:55:33 PM PDT 24
Peak memory 204712 kb
Host smart-fa12ff02-6ee3-489c-9e45-b0d17688c5db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284634073 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.2284634073
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.575330772
Short name T178
Test name
Test status
Simulation time 1891006667 ps
CPU time 10.84 seconds
Started Mar 19 02:43:32 PM PDT 24
Finished Mar 19 02:43:43 PM PDT 24
Peak memory 205324 kb
Host smart-16e5eea5-6101-4b32-9578-56778a2e8f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575330772 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.575330772
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.3038156553
Short name T63
Test name
Test status
Simulation time 77754950 ps
CPU time 0.87 seconds
Started Mar 19 02:43:30 PM PDT 24
Finished Mar 19 02:43:31 PM PDT 24
Peak memory 204856 kb
Host smart-f2c5f636-9ffb-439a-80eb-b7b14aca0869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038156553 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.3038156553
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.3434846292
Short name T27
Test name
Test status
Simulation time 97722521 ps
CPU time 1.14 seconds
Started Mar 19 02:43:32 PM PDT 24
Finished Mar 19 02:43:33 PM PDT 24
Peak memory 228160 kb
Host smart-e6e3c3d7-48b0-48f7-868b-bf6bd0447538
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434846292 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.3434846292
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/23.rv_dm_tap_fsm_rand_reset.2661456535
Short name T132
Test name
Test status
Simulation time 16670981338 ps
CPU time 27.19 seconds
Started Mar 19 02:55:44 PM PDT 24
Finished Mar 19 02:56:13 PM PDT 24
Peak memory 221232 kb
Host smart-c2c96c60-d8ff-4c56-9320-27d55b5f2992
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661456535 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 23.rv_dm_tap_fsm_rand_reset.2661456535
Directory /workspace/23.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.750698158
Short name T97
Test name
Test status
Simulation time 100909236 ps
CPU time 2.38 seconds
Started Mar 19 02:54:59 PM PDT 24
Finished Mar 19 02:55:02 PM PDT 24
Peak memory 218540 kb
Host smart-06cd59f5-a311-4ee5-827e-037884e55cf7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750698158 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.750698158
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.3836153590
Short name T6
Test name
Test status
Simulation time 214242205 ps
CPU time 1.13 seconds
Started Mar 19 02:43:23 PM PDT 24
Finished Mar 19 02:43:24 PM PDT 24
Peak memory 205128 kb
Host smart-8b1451b8-f9dc-47cb-a869-dd97c0b5be3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836153590 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.3836153590
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.3196552197
Short name T60
Test name
Test status
Simulation time 50457223 ps
CPU time 0.8 seconds
Started Mar 19 02:43:22 PM PDT 24
Finished Mar 19 02:43:23 PM PDT 24
Peak memory 213096 kb
Host smart-18683840-f36a-4e72-bac8-178b96292f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196552197 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.3196552197
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3560740828
Short name T244
Test name
Test status
Simulation time 89429742 ps
CPU time 0.93 seconds
Started Mar 19 02:54:59 PM PDT 24
Finished Mar 19 02:55:00 PM PDT 24
Peak memory 204488 kb
Host smart-ddb65f36-c6da-441d-b951-34772af61b7c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560740828 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.3560740828
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.4250064018
Short name T182
Test name
Test status
Simulation time 2089081410 ps
CPU time 11.46 seconds
Started Mar 19 02:43:43 PM PDT 24
Finished Mar 19 02:43:56 PM PDT 24
Peak memory 213436 kb
Host smart-9908e988-94d5-40b0-b06e-0c8ed0567c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250064018 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.4250064018
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.2414807103
Short name T120
Test name
Test status
Simulation time 3665630064 ps
CPU time 20.53 seconds
Started Mar 19 02:55:32 PM PDT 24
Finished Mar 19 02:55:53 PM PDT 24
Peak memory 213080 kb
Host smart-4d502738-949d-4d52-9ea2-90bf90eaef65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414807103 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.2
414807103
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.954231914
Short name T64
Test name
Test status
Simulation time 69169910 ps
CPU time 0.83 seconds
Started Mar 19 02:43:18 PM PDT 24
Finished Mar 19 02:43:19 PM PDT 24
Peak memory 204860 kb
Host smart-58a148dc-0044-4f0d-9987-65c2ca76c2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954231914 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.954231914
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.77977679
Short name T77
Test name
Test status
Simulation time 226087368 ps
CPU time 2.73 seconds
Started Mar 19 02:55:43 PM PDT 24
Finished Mar 19 02:55:47 PM PDT 24
Peak memory 212920 kb
Host smart-192b6951-96f6-47ee-a703-7c2925318019
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77977679 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.77977679
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.792015248
Short name T92
Test name
Test status
Simulation time 719711595 ps
CPU time 2.21 seconds
Started Mar 19 02:54:52 PM PDT 24
Finished Mar 19 02:54:54 PM PDT 24
Peak memory 204748 kb
Host smart-277ca5f9-caeb-4ba2-b14e-316210ee0176
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792015248 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr
_hw_reset.792015248
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.1509340419
Short name T126
Test name
Test status
Simulation time 446550854 ps
CPU time 15.7 seconds
Started Mar 19 02:55:40 PM PDT 24
Finished Mar 19 02:55:56 PM PDT 24
Peak memory 212972 kb
Host smart-a0c50939-6471-4160-bb32-9699f402cfa4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509340419 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.1
509340419
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.1256639253
Short name T310
Test name
Test status
Simulation time 43726865 ps
CPU time 0.76 seconds
Started Mar 19 02:54:51 PM PDT 24
Finished Mar 19 02:54:52 PM PDT 24
Peak memory 204520 kb
Host smart-ee2894dc-c409-4add-ac96-e0d5ec8e9964
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256639253 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.1256639253
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.1936726875
Short name T24
Test name
Test status
Simulation time 85503222 ps
CPU time 0.9 seconds
Started Mar 19 02:43:21 PM PDT 24
Finished Mar 19 02:43:22 PM PDT 24
Peak memory 204672 kb
Host smart-ad70fb1d-554c-4218-bab8-5fb23504eeb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936726875 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.1936726875
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/24.rv_dm_stress_all.3654596676
Short name T4
Test name
Test status
Simulation time 2540512139 ps
CPU time 9.01 seconds
Started Mar 19 02:44:04 PM PDT 24
Finished Mar 19 02:44:13 PM PDT 24
Peak memory 205076 kb
Host smart-5cd5d3ad-ce52-46ae-a99e-8d1502bb27c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654596676 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.3654596676
Directory /workspace/24.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.55438196
Short name T87
Test name
Test status
Simulation time 638278208 ps
CPU time 3.55 seconds
Started Mar 19 02:54:52 PM PDT 24
Finished Mar 19 02:54:56 PM PDT 24
Peak memory 204760 kb
Host smart-5769374e-e0b5-4096-8cb2-385e8d58908b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55438196 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_cs
r_outstanding.55438196
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.1926030239
Short name T129
Test name
Test status
Simulation time 437405570 ps
CPU time 15.74 seconds
Started Mar 19 02:55:02 PM PDT 24
Finished Mar 19 02:55:17 PM PDT 24
Peak memory 221124 kb
Host smart-9de67e05-76c8-4a89-b528-602ec1e1be80
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926030239 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.1926030239
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.2336118219
Short name T166
Test name
Test status
Simulation time 20336564 ps
CPU time 0.74 seconds
Started Mar 19 02:43:29 PM PDT 24
Finished Mar 19 02:43:31 PM PDT 24
Peak memory 204880 kb
Host smart-bdc6963a-7f41-4e45-b23b-0bbde30e9a20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336118219 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.2336118219
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3715927616
Short name T104
Test name
Test status
Simulation time 760385999 ps
CPU time 26.82 seconds
Started Mar 19 02:54:51 PM PDT 24
Finished Mar 19 02:55:18 PM PDT 24
Peak memory 213032 kb
Host smart-da2875e9-cbb9-4bf5-b005-045d2f6e0f12
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715927616 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.3715927616
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.1942997764
Short name T317
Test name
Test status
Simulation time 6929588012 ps
CPU time 37.15 seconds
Started Mar 19 02:54:49 PM PDT 24
Finished Mar 19 02:55:26 PM PDT 24
Peak memory 204848 kb
Host smart-d890fe9d-f764-4081-8d7d-8a07e9be336f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942997764 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.1942997764
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.1967615660
Short name T369
Test name
Test status
Simulation time 80974833 ps
CPU time 1.61 seconds
Started Mar 19 02:54:51 PM PDT 24
Finished Mar 19 02:54:53 PM PDT 24
Peak memory 212992 kb
Host smart-5961fd70-f6c1-4b9f-b4d8-f3b197a110d7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967615660 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.1967615660
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1326984248
Short name T320
Test name
Test status
Simulation time 642883993 ps
CPU time 4.34 seconds
Started Mar 19 02:54:51 PM PDT 24
Finished Mar 19 02:54:55 PM PDT 24
Peak memory 215428 kb
Host smart-a15bf93a-a08b-4944-baaf-f206df270b9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326984248 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.1326984248
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.1596672380
Short name T348
Test name
Test status
Simulation time 179873986 ps
CPU time 2.3 seconds
Started Mar 19 02:54:51 PM PDT 24
Finished Mar 19 02:54:53 PM PDT 24
Peak memory 212900 kb
Host smart-745964da-9497-4025-ba0e-9b927906a425
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596672380 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.1596672380
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.770571801
Short name T285
Test name
Test status
Simulation time 9731694972 ps
CPU time 23.97 seconds
Started Mar 19 02:54:52 PM PDT 24
Finished Mar 19 02:55:16 PM PDT 24
Peak memory 204752 kb
Host smart-a2970aa7-df24-4de2-ab07-454851e0cef9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770571801 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr
_aliasing.770571801
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.2041042282
Short name T337
Test name
Test status
Simulation time 8089607969 ps
CPU time 31.71 seconds
Started Mar 19 02:54:52 PM PDT 24
Finished Mar 19 02:55:24 PM PDT 24
Peak memory 204756 kb
Host smart-819aa520-de08-4be8-bfd4-2d1341736d2c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041042282 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_bit_bash.2041042282
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.916350723
Short name T242
Test name
Test status
Simulation time 215597021 ps
CPU time 0.96 seconds
Started Mar 19 02:54:52 PM PDT 24
Finished Mar 19 02:54:53 PM PDT 24
Peak memory 204700 kb
Host smart-eb5c2256-13c7-4ab8-9b72-0c6e7f8f749c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916350723 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.916350723
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2328294468
Short name T270
Test name
Test status
Simulation time 129802853 ps
CPU time 1.06 seconds
Started Mar 19 02:54:50 PM PDT 24
Finished Mar 19 02:54:52 PM PDT 24
Peak memory 204500 kb
Host smart-ffaf3420-2aa0-4289-8062-414f4e372d6f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328294468 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.2328294468
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.4135974162
Short name T73
Test name
Test status
Simulation time 2457386521 ps
CPU time 2.93 seconds
Started Mar 19 02:54:51 PM PDT 24
Finished Mar 19 02:54:54 PM PDT 24
Peak memory 204768 kb
Host smart-2aa2137b-c8cc-4b85-9d1c-99d7dc3407a8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135974162 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.4135974162
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3986138016
Short name T253
Test name
Test status
Simulation time 67142153 ps
CPU time 0.67 seconds
Started Mar 19 02:54:51 PM PDT 24
Finished Mar 19 02:54:52 PM PDT 24
Peak memory 204496 kb
Host smart-6d460c12-da51-4b91-a9b7-297c024e8e59
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986138016 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.3
986138016
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.2811808965
Short name T239
Test name
Test status
Simulation time 22511940 ps
CPU time 0.74 seconds
Started Mar 19 02:54:50 PM PDT 24
Finished Mar 19 02:54:50 PM PDT 24
Peak memory 204492 kb
Host smart-59a0af54-4043-4d9e-97b3-36a1363c9c1e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811808965 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.2811808965
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.2313115190
Short name T231
Test name
Test status
Simulation time 26558583 ps
CPU time 0.67 seconds
Started Mar 19 02:54:51 PM PDT 24
Finished Mar 19 02:54:51 PM PDT 24
Peak memory 204504 kb
Host smart-6bc9b387-51d5-414b-981f-2bd6d2bb5878
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313115190 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.2313115190
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.1122024859
Short name T329
Test name
Test status
Simulation time 379408428 ps
CPU time 5.25 seconds
Started Mar 19 02:54:55 PM PDT 24
Finished Mar 19 02:55:00 PM PDT 24
Peak memory 212948 kb
Host smart-c2217765-652b-4e3a-91f4-8869d7222226
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122024859 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.1122024859
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.1835412202
Short name T262
Test name
Test status
Simulation time 291520359 ps
CPU time 8.43 seconds
Started Mar 19 02:54:53 PM PDT 24
Finished Mar 19 02:55:01 PM PDT 24
Peak memory 212812 kb
Host smart-eec60280-7ca9-478f-976a-3ba59d9b035f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835412202 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.1835412202
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.2513583967
Short name T307
Test name
Test status
Simulation time 17381951088 ps
CPU time 78.13 seconds
Started Mar 19 02:54:52 PM PDT 24
Finished Mar 19 02:56:10 PM PDT 24
Peak memory 217848 kb
Host smart-0c8f082e-73a0-40f2-b9cb-20713f8f3d11
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513583967 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.2513583967
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.3680492157
Short name T288
Test name
Test status
Simulation time 43013717693 ps
CPU time 90.21 seconds
Started Mar 19 02:54:58 PM PDT 24
Finished Mar 19 02:56:28 PM PDT 24
Peak memory 204836 kb
Host smart-ec04a93f-ba28-49d2-8c31-0b3778605c92
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680492157 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.3680492157
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.1261693364
Short name T330
Test name
Test status
Simulation time 97754974 ps
CPU time 1.48 seconds
Started Mar 19 02:54:59 PM PDT 24
Finished Mar 19 02:55:01 PM PDT 24
Peak memory 213008 kb
Host smart-2b6fa0e9-79aa-4055-98b6-8d6e73075792
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261693364 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.1261693364
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.1295353468
Short name T344
Test name
Test status
Simulation time 94263361 ps
CPU time 2.42 seconds
Started Mar 19 02:54:58 PM PDT 24
Finished Mar 19 02:55:00 PM PDT 24
Peak memory 213016 kb
Host smart-e82bd3bf-69b2-4d8c-8d72-a6dd4d1f15a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295353468 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.1295353468
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.3462408026
Short name T230
Test name
Test status
Simulation time 27564375416 ps
CPU time 27.27 seconds
Started Mar 19 02:54:57 PM PDT 24
Finished Mar 19 02:55:24 PM PDT 24
Peak memory 204812 kb
Host smart-29a51b4b-c6b7-4711-bdf5-a03e2f2f5cd1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462408026 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.3462408026
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2246859799
Short name T240
Test name
Test status
Simulation time 20702867365 ps
CPU time 21.85 seconds
Started Mar 19 02:54:55 PM PDT 24
Finished Mar 19 02:55:17 PM PDT 24
Peak memory 204816 kb
Host smart-20c80d4d-8c36-40d4-a6d8-f944844da282
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246859799 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_bit_bash.2246859799
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2354461847
Short name T93
Test name
Test status
Simulation time 1277588995 ps
CPU time 5.25 seconds
Started Mar 19 02:54:54 PM PDT 24
Finished Mar 19 02:54:59 PM PDT 24
Peak memory 204780 kb
Host smart-6457a5f3-28a7-4f4e-9290-e8a6cebd6554
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354461847 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.2354461847
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2189687149
Short name T274
Test name
Test status
Simulation time 289225373 ps
CPU time 1.62 seconds
Started Mar 19 02:54:55 PM PDT 24
Finished Mar 19 02:54:57 PM PDT 24
Peak memory 204684 kb
Host smart-af640c0f-527b-4086-a0ee-a4e542c39b3e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189687149 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.2
189687149
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3617918288
Short name T302
Test name
Test status
Simulation time 67682963 ps
CPU time 0.83 seconds
Started Mar 19 02:54:50 PM PDT 24
Finished Mar 19 02:54:51 PM PDT 24
Peak memory 204420 kb
Host smart-6ff077b3-e5a4-464e-9454-9cf32916c28a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617918288 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.3617918288
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.3770076539
Short name T375
Test name
Test status
Simulation time 1038132614 ps
CPU time 3.66 seconds
Started Mar 19 02:54:51 PM PDT 24
Finished Mar 19 02:54:55 PM PDT 24
Peak memory 204676 kb
Host smart-df8176d6-a2f6-4887-a310-29ad0c90fb81
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770076539 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.3770076539
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.3461284254
Short name T295
Test name
Test status
Simulation time 139835425 ps
CPU time 0.7 seconds
Started Mar 19 02:54:53 PM PDT 24
Finished Mar 19 02:54:53 PM PDT 24
Peak memory 204504 kb
Host smart-2d1a670d-0303-4d5f-a14e-844d57a3fa20
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461284254 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.3461284254
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.4084931613
Short name T315
Test name
Test status
Simulation time 26551404 ps
CPU time 0.69 seconds
Started Mar 19 02:54:55 PM PDT 24
Finished Mar 19 02:54:56 PM PDT 24
Peak memory 204484 kb
Host smart-5e6abffb-6908-4e64-bbba-1cdb3c6b4449
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084931613 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.4
084931613
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2518805773
Short name T248
Test name
Test status
Simulation time 15632439 ps
CPU time 0.71 seconds
Started Mar 19 02:55:08 PM PDT 24
Finished Mar 19 02:55:10 PM PDT 24
Peak memory 204484 kb
Host smart-78581e92-015d-48c9-b6f9-42ed19abd308
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518805773 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.2518805773
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.1081223179
Short name T333
Test name
Test status
Simulation time 18414314 ps
CPU time 0.65 seconds
Started Mar 19 02:54:58 PM PDT 24
Finished Mar 19 02:54:58 PM PDT 24
Peak memory 204496 kb
Host smart-3a0802ea-ee75-42c7-9b4e-1a05b3f95123
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081223179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.1081223179
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.338472563
Short name T111
Test name
Test status
Simulation time 3237265011 ps
CPU time 4.93 seconds
Started Mar 19 02:55:01 PM PDT 24
Finished Mar 19 02:55:06 PM PDT 24
Peak memory 204724 kb
Host smart-19fa2f99-8ad2-4b36-9037-7557c7179d12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338472563 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_c
sr_outstanding.338472563
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.3209268954
Short name T331
Test name
Test status
Simulation time 132331797 ps
CPU time 3.27 seconds
Started Mar 19 02:54:58 PM PDT 24
Finished Mar 19 02:55:01 PM PDT 24
Peak memory 213008 kb
Host smart-eed67f8a-821c-40f2-b6f4-1ab04a8b34a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209268954 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.3209268954
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.2892041369
Short name T81
Test name
Test status
Simulation time 428273605 ps
CPU time 8.85 seconds
Started Mar 19 02:54:58 PM PDT 24
Finished Mar 19 02:55:07 PM PDT 24
Peak memory 212940 kb
Host smart-d85719a8-b2a2-4799-a96d-23ce38dccee1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892041369 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.2892041369
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3517613831
Short name T304
Test name
Test status
Simulation time 888851474 ps
CPU time 3.77 seconds
Started Mar 19 02:55:24 PM PDT 24
Finished Mar 19 02:55:28 PM PDT 24
Peak memory 217524 kb
Host smart-2dd5c0d0-2162-4236-bc22-c0f76c7994c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517613831 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.3517613831
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.2184454117
Short name T260
Test name
Test status
Simulation time 94255761 ps
CPU time 1.41 seconds
Started Mar 19 02:55:30 PM PDT 24
Finished Mar 19 02:55:32 PM PDT 24
Peak memory 213032 kb
Host smart-f589b980-655f-4381-ba7a-0cf77b30bf25
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184454117 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.2184454117
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3156814346
Short name T233
Test name
Test status
Simulation time 335437876 ps
CPU time 1.07 seconds
Started Mar 19 02:55:26 PM PDT 24
Finished Mar 19 02:55:27 PM PDT 24
Peak memory 204608 kb
Host smart-4be564a9-0bab-4a47-b14b-4c34d21a59ca
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156814346 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
3156814346
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.4223344241
Short name T243
Test name
Test status
Simulation time 33085689 ps
CPU time 0.77 seconds
Started Mar 19 02:55:24 PM PDT 24
Finished Mar 19 02:55:25 PM PDT 24
Peak memory 204464 kb
Host smart-e18fe87d-8f10-464f-b088-a788489e6ac7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223344241 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
4223344241
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.343664238
Short name T360
Test name
Test status
Simulation time 111266729 ps
CPU time 2.43 seconds
Started Mar 19 02:55:22 PM PDT 24
Finished Mar 19 02:55:25 PM PDT 24
Peak memory 212932 kb
Host smart-83e24083-b974-4d5c-be6d-43b7f76f7caf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343664238 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.343664238
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1043383342
Short name T127
Test name
Test status
Simulation time 1299073425 ps
CPU time 16.94 seconds
Started Mar 19 02:55:24 PM PDT 24
Finished Mar 19 02:55:41 PM PDT 24
Peak memory 213036 kb
Host smart-cac58283-1e48-4b0f-a57f-7a255923b58b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043383342 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.1
043383342
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.2241304656
Short name T346
Test name
Test status
Simulation time 90735044 ps
CPU time 2.36 seconds
Started Mar 19 02:55:28 PM PDT 24
Finished Mar 19 02:55:31 PM PDT 24
Peak memory 217392 kb
Host smart-d674b329-8f2e-4984-a60f-9dc19660a506
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241304656 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.2241304656
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.1859220818
Short name T84
Test name
Test status
Simulation time 96703291 ps
CPU time 2.32 seconds
Started Mar 19 02:55:24 PM PDT 24
Finished Mar 19 02:55:27 PM PDT 24
Peak memory 218140 kb
Host smart-295be9f5-f777-44cd-8973-30d0634919f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859220818 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.1859220818
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3495006853
Short name T257
Test name
Test status
Simulation time 169216857 ps
CPU time 1.06 seconds
Started Mar 19 02:55:27 PM PDT 24
Finished Mar 19 02:55:28 PM PDT 24
Peak memory 204700 kb
Host smart-928f5042-8006-43f2-87fc-1c9170433d50
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495006853 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
3495006853
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.1832060140
Short name T374
Test name
Test status
Simulation time 108684097 ps
CPU time 0.9 seconds
Started Mar 19 02:55:25 PM PDT 24
Finished Mar 19 02:55:26 PM PDT 24
Peak memory 204472 kb
Host smart-6d7a9d91-15ef-42e7-9d0f-610313d44988
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832060140 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.
1832060140
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.905613692
Short name T303
Test name
Test status
Simulation time 278120790 ps
CPU time 4.43 seconds
Started Mar 19 02:55:25 PM PDT 24
Finished Mar 19 02:55:30 PM PDT 24
Peak memory 204820 kb
Host smart-e045cd8c-70f5-44b0-8b9f-8297cf82aa1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905613692 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same_
csr_outstanding.905613692
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tap_fsm_rand_reset.1093415304
Short name T363
Test name
Test status
Simulation time 9464965559 ps
CPU time 16.61 seconds
Started Mar 19 02:55:25 PM PDT 24
Finished Mar 19 02:55:42 PM PDT 24
Peak memory 221240 kb
Host smart-792712fd-cd31-4823-b5aa-748e43658156
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093415304 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rv_dm_tap_fsm_rand_reset.1093415304
Directory /workspace/11.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.3257453367
Short name T316
Test name
Test status
Simulation time 37376562 ps
CPU time 1.89 seconds
Started Mar 19 02:55:24 PM PDT 24
Finished Mar 19 02:55:27 PM PDT 24
Peak memory 212988 kb
Host smart-e89c5d60-cd07-4c10-95ec-d9c1605bc3b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257453367 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.3257453367
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.305197391
Short name T265
Test name
Test status
Simulation time 3124311390 ps
CPU time 5.4 seconds
Started Mar 19 02:55:24 PM PDT 24
Finished Mar 19 02:55:30 PM PDT 24
Peak memory 219516 kb
Host smart-4b7c1add-a0d8-4d44-9828-9c57cb545079
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305197391 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.305197391
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.2584905848
Short name T107
Test name
Test status
Simulation time 372833401 ps
CPU time 2.23 seconds
Started Mar 19 02:55:24 PM PDT 24
Finished Mar 19 02:55:27 PM PDT 24
Peak memory 219000 kb
Host smart-94adc6ca-a6c5-49d6-b10b-436ab540fe13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584905848 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.2584905848
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.551994433
Short name T376
Test name
Test status
Simulation time 241998407 ps
CPU time 1.42 seconds
Started Mar 19 02:55:25 PM PDT 24
Finished Mar 19 02:55:27 PM PDT 24
Peak memory 204736 kb
Host smart-6a1c7e98-b4a4-40c3-8467-9fdbfd2f2a38
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551994433 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.551994433
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3700471871
Short name T335
Test name
Test status
Simulation time 73739261 ps
CPU time 0.77 seconds
Started Mar 19 02:55:25 PM PDT 24
Finished Mar 19 02:55:26 PM PDT 24
Peak memory 204492 kb
Host smart-3013883a-6def-4da9-a81b-c729d3462c31
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700471871 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
3700471871
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3060619253
Short name T82
Test name
Test status
Simulation time 626949044 ps
CPU time 4.47 seconds
Started Mar 19 02:55:26 PM PDT 24
Finished Mar 19 02:55:31 PM PDT 24
Peak memory 204664 kb
Host smart-a33cc768-f668-4986-8e31-729ca704bc8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060619253 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.3060619253
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tap_fsm_rand_reset.3375681793
Short name T72
Test name
Test status
Simulation time 24037788104 ps
CPU time 23.3 seconds
Started Mar 19 02:55:28 PM PDT 24
Finished Mar 19 02:55:52 PM PDT 24
Peak memory 221200 kb
Host smart-bb7875f3-8a1d-45e9-812b-72fb4ac12b45
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375681793 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rv_dm_tap_fsm_rand_reset.3375681793
Directory /workspace/12.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.4289967796
Short name T368
Test name
Test status
Simulation time 75129576 ps
CPU time 4.47 seconds
Started Mar 19 02:55:24 PM PDT 24
Finished Mar 19 02:55:29 PM PDT 24
Peak memory 212968 kb
Host smart-26479fc1-ff04-49b2-8565-9eba7b8d17df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289967796 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.4289967796
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3676132048
Short name T122
Test name
Test status
Simulation time 3099534734 ps
CPU time 19.05 seconds
Started Mar 19 02:55:25 PM PDT 24
Finished Mar 19 02:55:45 PM PDT 24
Peak memory 213020 kb
Host smart-23037859-c81f-46cb-9188-2ab5c255d81c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676132048 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.3
676132048
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.673657651
Short name T258
Test name
Test status
Simulation time 84612506 ps
CPU time 2.38 seconds
Started Mar 19 02:55:34 PM PDT 24
Finished Mar 19 02:55:36 PM PDT 24
Peak memory 217600 kb
Host smart-7ac3aca7-fe86-4185-a5da-f0bdcfdfefdd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673657651 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.673657651
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.1608598346
Short name T131
Test name
Test status
Simulation time 57883528 ps
CPU time 1.65 seconds
Started Mar 19 02:55:34 PM PDT 24
Finished Mar 19 02:55:36 PM PDT 24
Peak memory 218308 kb
Host smart-820590c6-664b-4019-9601-bb722e6a0022
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608598346 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.1608598346
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.886567741
Short name T277
Test name
Test status
Simulation time 192445232 ps
CPU time 1.37 seconds
Started Mar 19 02:55:33 PM PDT 24
Finished Mar 19 02:55:35 PM PDT 24
Peak memory 204688 kb
Host smart-070418d8-00c2-4a9e-a3a9-f07991f82578
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886567741 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.886567741
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2037259517
Short name T74
Test name
Test status
Simulation time 109104598 ps
CPU time 0.81 seconds
Started Mar 19 02:55:22 PM PDT 24
Finished Mar 19 02:55:23 PM PDT 24
Peak memory 204488 kb
Host smart-67566bcc-50b4-4c6e-b398-bdfae7f98484
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037259517 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
2037259517
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.1336004040
Short name T88
Test name
Test status
Simulation time 1375869968 ps
CPU time 8.03 seconds
Started Mar 19 02:55:31 PM PDT 24
Finished Mar 19 02:55:40 PM PDT 24
Peak memory 204748 kb
Host smart-6405680e-e265-4d53-ac10-019214af8552
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336004040 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.1336004040
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tap_fsm_rand_reset.3984002579
Short name T358
Test name
Test status
Simulation time 8910212863 ps
CPU time 26.65 seconds
Started Mar 19 02:55:31 PM PDT 24
Finished Mar 19 02:55:59 PM PDT 24
Peak memory 218572 kb
Host smart-d3dc901d-a2ea-431f-8908-85377dbed606
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984002579 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rv_dm_tap_fsm_rand_reset.3984002579
Directory /workspace/13.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.1140872867
Short name T119
Test name
Test status
Simulation time 500254072 ps
CPU time 3.4 seconds
Started Mar 19 02:55:31 PM PDT 24
Finished Mar 19 02:55:35 PM PDT 24
Peak memory 212952 kb
Host smart-e39918b7-d1c3-46ed-b764-d0b1d7d11ddc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140872867 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.1140872867
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1126966417
Short name T371
Test name
Test status
Simulation time 735943229 ps
CPU time 16.3 seconds
Started Mar 19 02:55:29 PM PDT 24
Finished Mar 19 02:55:46 PM PDT 24
Peak memory 212952 kb
Host smart-21a02011-2483-4211-9970-5aa844a3e47c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126966417 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.1
126966417
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.2905093051
Short name T283
Test name
Test status
Simulation time 373728428 ps
CPU time 2.28 seconds
Started Mar 19 02:55:32 PM PDT 24
Finished Mar 19 02:55:35 PM PDT 24
Peak memory 215028 kb
Host smart-35a2fb30-3a88-4926-9468-f970f732d98c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905093051 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.2905093051
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.4197998123
Short name T106
Test name
Test status
Simulation time 547403644 ps
CPU time 1.53 seconds
Started Mar 19 02:55:31 PM PDT 24
Finished Mar 19 02:55:33 PM PDT 24
Peak memory 212952 kb
Host smart-3d4494e2-9649-4a6a-8502-e397a7fce4e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197998123 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.4197998123
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3119811406
Short name T282
Test name
Test status
Simulation time 1082646828 ps
CPU time 2.56 seconds
Started Mar 19 02:55:34 PM PDT 24
Finished Mar 19 02:55:36 PM PDT 24
Peak memory 204772 kb
Host smart-d3329149-c91d-479a-babd-70968511e2ea
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119811406 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
3119811406
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.985789998
Short name T366
Test name
Test status
Simulation time 47747379 ps
CPU time 0.73 seconds
Started Mar 19 02:55:35 PM PDT 24
Finished Mar 19 02:55:36 PM PDT 24
Peak memory 204388 kb
Host smart-1aa9225c-587b-4332-ad8d-73cd6e95f0e6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985789998 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.985789998
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1264143201
Short name T102
Test name
Test status
Simulation time 544081981 ps
CPU time 6.3 seconds
Started Mar 19 02:55:29 PM PDT 24
Finished Mar 19 02:55:37 PM PDT 24
Peak memory 204772 kb
Host smart-5fe1fa86-8109-4de8-a256-ff3b64cb70e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264143201 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.1264143201
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tap_fsm_rand_reset.2983751347
Short name T292
Test name
Test status
Simulation time 16139404353 ps
CPU time 13.01 seconds
Started Mar 19 02:55:29 PM PDT 24
Finished Mar 19 02:55:43 PM PDT 24
Peak memory 214468 kb
Host smart-b55a9e9d-d354-4423-93f8-2d14962f024c
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983751347 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rv_dm_tap_fsm_rand_reset.2983751347
Directory /workspace/14.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.1006344298
Short name T79
Test name
Test status
Simulation time 118073200 ps
CPU time 3.11 seconds
Started Mar 19 02:55:33 PM PDT 24
Finished Mar 19 02:55:36 PM PDT 24
Peak memory 212964 kb
Host smart-c0eb0091-c127-4846-b6bd-8201a2829885
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006344298 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.1006344298
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.4127079108
Short name T37
Test name
Test status
Simulation time 3027047954 ps
CPU time 4.74 seconds
Started Mar 19 02:55:32 PM PDT 24
Finished Mar 19 02:55:37 PM PDT 24
Peak memory 218560 kb
Host smart-7833bff2-a3c3-4484-bd4c-77d8ef37235b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127079108 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.4127079108
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2687690220
Short name T336
Test name
Test status
Simulation time 45935504 ps
CPU time 1.48 seconds
Started Mar 19 02:55:34 PM PDT 24
Finished Mar 19 02:55:35 PM PDT 24
Peak memory 218164 kb
Host smart-28970fae-152e-49c4-b32c-325c713fd773
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687690220 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.2687690220
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1620914064
Short name T367
Test name
Test status
Simulation time 783298847 ps
CPU time 1.43 seconds
Started Mar 19 02:55:33 PM PDT 24
Finished Mar 19 02:55:35 PM PDT 24
Peak memory 204680 kb
Host smart-66352587-688f-4e0c-a4c3-9de03910360a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620914064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
1620914064
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.2220845698
Short name T70
Test name
Test status
Simulation time 83689439 ps
CPU time 0.73 seconds
Started Mar 19 02:55:34 PM PDT 24
Finished Mar 19 02:55:35 PM PDT 24
Peak memory 204396 kb
Host smart-76882d4f-51ae-4d96-b2c4-d8705f1babb1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220845698 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
2220845698
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.2193588324
Short name T276
Test name
Test status
Simulation time 1313827475 ps
CPU time 4.23 seconds
Started Mar 19 02:55:33 PM PDT 24
Finished Mar 19 02:55:38 PM PDT 24
Peak memory 204672 kb
Host smart-e3399566-1ddd-43c0-bc93-de75a20409ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193588324 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.2193588324
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tap_fsm_rand_reset.294149510
Short name T339
Test name
Test status
Simulation time 30659484782 ps
CPU time 21.72 seconds
Started Mar 19 02:55:34 PM PDT 24
Finished Mar 19 02:55:56 PM PDT 24
Peak memory 214812 kb
Host smart-b8e20b6e-af87-4654-b7bd-5988e39c4d08
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294149510 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.rv_dm_tap_fsm_rand_reset.294149510
Directory /workspace/15.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.1170760024
Short name T313
Test name
Test status
Simulation time 1212242651 ps
CPU time 5.62 seconds
Started Mar 19 02:55:30 PM PDT 24
Finished Mar 19 02:55:37 PM PDT 24
Peak memory 213048 kb
Host smart-054256a5-bb60-4339-96fe-9950ed4e473c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170760024 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.1170760024
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.1226836926
Short name T117
Test name
Test status
Simulation time 286693264 ps
CPU time 8.28 seconds
Started Mar 19 02:55:30 PM PDT 24
Finished Mar 19 02:55:39 PM PDT 24
Peak memory 212884 kb
Host smart-ce2141a2-2897-4964-976b-e8f63e253fa0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226836926 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.1
226836926
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.3842672303
Short name T114
Test name
Test status
Simulation time 4657825805 ps
CPU time 6.11 seconds
Started Mar 19 02:55:30 PM PDT 24
Finished Mar 19 02:55:38 PM PDT 24
Peak memory 216364 kb
Host smart-ed7207e2-3849-44dd-8af0-c9bfd2c4bedb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842672303 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.3842672303
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.4293141087
Short name T95
Test name
Test status
Simulation time 160732475 ps
CPU time 2.3 seconds
Started Mar 19 02:55:31 PM PDT 24
Finished Mar 19 02:55:34 PM PDT 24
Peak memory 218660 kb
Host smart-5df8d427-e64c-4d6e-ba00-b954249daf67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293141087 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.4293141087
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.3458068610
Short name T340
Test name
Test status
Simulation time 284451234 ps
CPU time 1.31 seconds
Started Mar 19 02:55:31 PM PDT 24
Finished Mar 19 02:55:33 PM PDT 24
Peak memory 204704 kb
Host smart-2397d647-80e5-4db2-a3eb-4271c65f8d69
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458068610 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
3458068610
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.1347437455
Short name T267
Test name
Test status
Simulation time 34231734 ps
CPU time 0.73 seconds
Started Mar 19 02:55:32 PM PDT 24
Finished Mar 19 02:55:33 PM PDT 24
Peak memory 204492 kb
Host smart-6e3c390a-ba82-4245-b0a8-0f6d8f1e3ad6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347437455 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
1347437455
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3558206779
Short name T98
Test name
Test status
Simulation time 3350534011 ps
CPU time 4.43 seconds
Started Mar 19 02:55:33 PM PDT 24
Finished Mar 19 02:55:38 PM PDT 24
Peak memory 204852 kb
Host smart-bbd9333f-8507-4ca4-ac64-feb7e1963bfc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558206779 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.3558206779
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.584642614
Short name T351
Test name
Test status
Simulation time 1983660950 ps
CPU time 18.21 seconds
Started Mar 19 02:55:28 PM PDT 24
Finished Mar 19 02:55:47 PM PDT 24
Peak memory 213000 kb
Host smart-3c0f6228-f0d9-4541-91e4-8cd5bd409151
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584642614 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.584642614
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.516349237
Short name T297
Test name
Test status
Simulation time 59550629 ps
CPU time 2.24 seconds
Started Mar 19 02:55:39 PM PDT 24
Finished Mar 19 02:55:42 PM PDT 24
Peak memory 217156 kb
Host smart-e25fbeaf-eca7-4882-868d-d0b97c8742ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516349237 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.516349237
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.29917808
Short name T100
Test name
Test status
Simulation time 75877375 ps
CPU time 2.18 seconds
Started Mar 19 02:55:38 PM PDT 24
Finished Mar 19 02:55:40 PM PDT 24
Peak memory 218536 kb
Host smart-7cb44dc8-e82b-41cd-9c9a-e85233447a6a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29917808 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.29917808
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2412384053
Short name T357
Test name
Test status
Simulation time 349670170 ps
CPU time 1.75 seconds
Started Mar 19 02:55:33 PM PDT 24
Finished Mar 19 02:55:35 PM PDT 24
Peak memory 204676 kb
Host smart-8bdbb9a3-da9c-4634-8906-0f3fa1d79ef9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412384053 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
2412384053
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2306087481
Short name T247
Test name
Test status
Simulation time 54528182 ps
CPU time 0.7 seconds
Started Mar 19 02:55:30 PM PDT 24
Finished Mar 19 02:55:31 PM PDT 24
Peak memory 204480 kb
Host smart-e4dbd23c-a45d-4274-bad5-905e27c65e78
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306087481 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
2306087481
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.137699930
Short name T94
Test name
Test status
Simulation time 838169428 ps
CPU time 8.26 seconds
Started Mar 19 02:55:40 PM PDT 24
Finished Mar 19 02:55:49 PM PDT 24
Peak memory 204804 kb
Host smart-03601958-e834-4793-8fb0-9468f37b97fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137699930 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same_
csr_outstanding.137699930
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tap_fsm_rand_reset.3467597702
Short name T356
Test name
Test status
Simulation time 13182355694 ps
CPU time 12.78 seconds
Started Mar 19 02:55:31 PM PDT 24
Finished Mar 19 02:55:44 PM PDT 24
Peak memory 221076 kb
Host smart-25fcd6d8-1c67-408f-9c67-f1702a3da838
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467597702 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rv_dm_tap_fsm_rand_reset.3467597702
Directory /workspace/17.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.3772515306
Short name T251
Test name
Test status
Simulation time 466406094 ps
CPU time 5.88 seconds
Started Mar 19 02:55:40 PM PDT 24
Finished Mar 19 02:55:47 PM PDT 24
Peak memory 213012 kb
Host smart-a3d92c4e-6d9b-46d0-840a-4e7ef5f639d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772515306 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.3772515306
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.552768
Short name T123
Test name
Test status
Simulation time 561622224 ps
CPU time 10.46 seconds
Started Mar 19 02:55:38 PM PDT 24
Finished Mar 19 02:55:49 PM PDT 24
Peak memory 221008 kb
Host smart-991e1e09-663e-4ae4-b89b-cd4f14ab6c55
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552768 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.552768
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.1959294465
Short name T43
Test name
Test status
Simulation time 177771108 ps
CPU time 1.54 seconds
Started Mar 19 02:55:37 PM PDT 24
Finished Mar 19 02:55:39 PM PDT 24
Peak memory 212928 kb
Host smart-c20a84fb-38f9-46e8-b8c9-906de1cf8f8e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959294465 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.1959294465
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2884870102
Short name T264
Test name
Test status
Simulation time 850212498 ps
CPU time 1.24 seconds
Started Mar 19 02:55:37 PM PDT 24
Finished Mar 19 02:55:39 PM PDT 24
Peak memory 204632 kb
Host smart-86435ffe-86d9-4abe-a560-3171d1fecd20
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884870102 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
2884870102
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.1031015220
Short name T266
Test name
Test status
Simulation time 87299420 ps
CPU time 0.71 seconds
Started Mar 19 02:55:38 PM PDT 24
Finished Mar 19 02:55:39 PM PDT 24
Peak memory 204504 kb
Host smart-9be8ee03-3f68-425a-983c-9f4d81a24f7e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031015220 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
1031015220
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.871801535
Short name T99
Test name
Test status
Simulation time 871813745 ps
CPU time 4.12 seconds
Started Mar 19 02:55:38 PM PDT 24
Finished Mar 19 02:55:42 PM PDT 24
Peak memory 204628 kb
Host smart-da7152df-152e-4ad7-991b-99b0b260050f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871801535 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same_
csr_outstanding.871801535
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.3439432220
Short name T273
Test name
Test status
Simulation time 223426648 ps
CPU time 3.02 seconds
Started Mar 19 02:55:47 PM PDT 24
Finished Mar 19 02:55:52 PM PDT 24
Peak memory 213004 kb
Host smart-2b947781-d3b7-4129-86bf-cc75eed4c961
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439432220 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.3439432220
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3366574805
Short name T124
Test name
Test status
Simulation time 8510923954 ps
CPU time 20.6 seconds
Started Mar 19 02:55:41 PM PDT 24
Finished Mar 19 02:56:02 PM PDT 24
Peak memory 213056 kb
Host smart-47aac22b-c347-426c-8f4e-b31702895a7e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366574805 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.3
366574805
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1400417546
Short name T323
Test name
Test status
Simulation time 2869015970 ps
CPU time 7.67 seconds
Started Mar 19 02:55:36 PM PDT 24
Finished Mar 19 02:55:44 PM PDT 24
Peak memory 221240 kb
Host smart-23209238-4bfa-467c-9209-1fb55125f8ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400417546 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.1400417546
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.2793197187
Short name T309
Test name
Test status
Simulation time 45537950 ps
CPU time 1.48 seconds
Started Mar 19 02:55:40 PM PDT 24
Finished Mar 19 02:55:42 PM PDT 24
Peak memory 212996 kb
Host smart-b662d416-b777-4d60-8ee1-94897393f9a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793197187 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.2793197187
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.4185362773
Short name T347
Test name
Test status
Simulation time 409485149 ps
CPU time 2.3 seconds
Started Mar 19 02:55:42 PM PDT 24
Finished Mar 19 02:55:44 PM PDT 24
Peak memory 204688 kb
Host smart-0540c8e5-ded8-4b11-ba66-524b9955a643
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185362773 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
4185362773
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2709943700
Short name T305
Test name
Test status
Simulation time 33109297 ps
CPU time 0.74 seconds
Started Mar 19 02:55:41 PM PDT 24
Finished Mar 19 02:55:43 PM PDT 24
Peak memory 204496 kb
Host smart-6ff7f2c3-aea2-4cbc-844b-acfbc7e46b1a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709943700 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
2709943700
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.562858294
Short name T85
Test name
Test status
Simulation time 4558476439 ps
CPU time 5.01 seconds
Started Mar 19 02:55:44 PM PDT 24
Finished Mar 19 02:55:50 PM PDT 24
Peak memory 204800 kb
Host smart-f2bb59cb-f79c-47f4-956a-415982bd4871
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562858294 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same_
csr_outstanding.562858294
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.4195134201
Short name T325
Test name
Test status
Simulation time 4402340561 ps
CPU time 34.84 seconds
Started Mar 19 02:54:59 PM PDT 24
Finished Mar 19 02:55:34 PM PDT 24
Peak memory 213032 kb
Host smart-a8204947-bd6a-4bc1-a156-e6b794934ae5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195134201 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.4195134201
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2425901780
Short name T294
Test name
Test status
Simulation time 5110335101 ps
CPU time 35.35 seconds
Started Mar 19 02:55:04 PM PDT 24
Finished Mar 19 02:55:40 PM PDT 24
Peak memory 204840 kb
Host smart-694e1ae2-c58c-4cf9-a86a-814638ee3e9e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425901780 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.2425901780
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.547281396
Short name T296
Test name
Test status
Simulation time 86238298 ps
CPU time 1.55 seconds
Started Mar 19 02:55:05 PM PDT 24
Finished Mar 19 02:55:06 PM PDT 24
Peak memory 212960 kb
Host smart-bd63a415-7047-44b9-92f8-65c69b7d5f0b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547281396 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.547281396
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.1850445269
Short name T80
Test name
Test status
Simulation time 5303461278 ps
CPU time 5.43 seconds
Started Mar 19 02:55:06 PM PDT 24
Finished Mar 19 02:55:11 PM PDT 24
Peak memory 216876 kb
Host smart-2240d94a-65e7-417c-a152-fec41fb91650
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850445269 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.1850445269
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1014954454
Short name T321
Test name
Test status
Simulation time 362028155 ps
CPU time 1.5 seconds
Started Mar 19 02:55:09 PM PDT 24
Finished Mar 19 02:55:10 PM PDT 24
Peak memory 221116 kb
Host smart-1fff3b91-a02b-4c0d-957a-5330cd4daab9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014954454 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.1014954454
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.3376923137
Short name T268
Test name
Test status
Simulation time 17727231834 ps
CPU time 35.45 seconds
Started Mar 19 02:55:09 PM PDT 24
Finished Mar 19 02:55:44 PM PDT 24
Peak memory 204756 kb
Host smart-accce5da-1b41-454f-b68b-0388308d00b1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376923137 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.3376923137
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.2901356775
Short name T324
Test name
Test status
Simulation time 15347621689 ps
CPU time 21.06 seconds
Started Mar 19 02:54:58 PM PDT 24
Finished Mar 19 02:55:19 PM PDT 24
Peak memory 204756 kb
Host smart-138d22f5-007c-4ace-ad34-56a1182995cf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901356775 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_bit_bash.2901356775
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.419265379
Short name T280
Test name
Test status
Simulation time 793013752 ps
CPU time 1.67 seconds
Started Mar 19 02:55:01 PM PDT 24
Finished Mar 19 02:55:02 PM PDT 24
Peak memory 204664 kb
Host smart-ce564c08-5246-4d8b-8a03-e4c05f7afb60
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419265379 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr
_hw_reset.419265379
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.3616032881
Short name T236
Test name
Test status
Simulation time 202293111 ps
CPU time 1.4 seconds
Started Mar 19 02:55:08 PM PDT 24
Finished Mar 19 02:55:10 PM PDT 24
Peak memory 204672 kb
Host smart-23477b52-9bed-46c3-85df-71f8d64892ad
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616032881 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.3
616032881
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.4000746109
Short name T272
Test name
Test status
Simulation time 68857137 ps
CPU time 0.74 seconds
Started Mar 19 02:54:58 PM PDT 24
Finished Mar 19 02:54:58 PM PDT 24
Peak memory 204472 kb
Host smart-42e131f8-4d38-4eba-b53d-37d175583c0e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000746109 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_aliasing.4000746109
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1106420868
Short name T299
Test name
Test status
Simulation time 2603918670 ps
CPU time 3.2 seconds
Started Mar 19 02:54:58 PM PDT 24
Finished Mar 19 02:55:01 PM PDT 24
Peak memory 204776 kb
Host smart-64c43b9b-cac9-4b6b-bdbd-37d993f0d81e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106420868 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.1106420868
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2569483779
Short name T256
Test name
Test status
Simulation time 47246811 ps
CPU time 0.77 seconds
Started Mar 19 02:54:58 PM PDT 24
Finished Mar 19 02:54:59 PM PDT 24
Peak memory 204504 kb
Host smart-2ec8ee49-cb7b-4a0c-880a-77bacbfaaee1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569483779 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.2
569483779
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.405551708
Short name T361
Test name
Test status
Simulation time 26628954 ps
CPU time 0.7 seconds
Started Mar 19 02:55:01 PM PDT 24
Finished Mar 19 02:55:01 PM PDT 24
Peak memory 204488 kb
Host smart-0d33e476-5fb6-4eb3-98f5-18ecb5d3a217
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405551708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_part
ial_access.405551708
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.3442517095
Short name T263
Test name
Test status
Simulation time 22895015 ps
CPU time 0.67 seconds
Started Mar 19 02:54:57 PM PDT 24
Finished Mar 19 02:54:58 PM PDT 24
Peak memory 204448 kb
Host smart-02b63a1b-8a4d-4848-aab6-4775a574bbf3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442517095 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.3442517095
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.2591397997
Short name T301
Test name
Test status
Simulation time 83227190 ps
CPU time 3.65 seconds
Started Mar 19 02:55:08 PM PDT 24
Finished Mar 19 02:55:11 PM PDT 24
Peak memory 204744 kb
Host smart-313b4c83-899c-41b1-a545-7b23b5dcb628
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591397997 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.2591397997
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.1655943375
Short name T275
Test name
Test status
Simulation time 642576241 ps
CPU time 5.29 seconds
Started Mar 19 02:54:58 PM PDT 24
Finished Mar 19 02:55:04 PM PDT 24
Peak memory 212944 kb
Host smart-86c59b37-4b1c-439e-8537-b8bb46f08c38
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655943375 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.1655943375
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/26.rv_dm_tap_fsm_rand_reset.596937642
Short name T290
Test name
Test status
Simulation time 5499462867 ps
CPU time 20.44 seconds
Started Mar 19 02:55:41 PM PDT 24
Finished Mar 19 02:56:02 PM PDT 24
Peak memory 218028 kb
Host smart-946a7396-c9c5-4ae2-a99c-8ab50ae91822
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596937642 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 26.rv_dm_tap_fsm_rand_reset.596937642
Directory /workspace/26.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/27.rv_dm_tap_fsm_rand_reset.2754721089
Short name T328
Test name
Test status
Simulation time 4406743036 ps
CPU time 17.2 seconds
Started Mar 19 02:55:44 PM PDT 24
Finished Mar 19 02:56:03 PM PDT 24
Peak memory 220284 kb
Host smart-a632e78e-0854-48cc-ad80-dc4186d7f81c
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754721089 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 27.rv_dm_tap_fsm_rand_reset.2754721089
Directory /workspace/27.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.89417532
Short name T108
Test name
Test status
Simulation time 28650070566 ps
CPU time 35.12 seconds
Started Mar 19 02:55:03 PM PDT 24
Finished Mar 19 02:55:39 PM PDT 24
Peak memory 213088 kb
Host smart-ea7dd3be-b996-425a-b543-7a6369a653b8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89417532 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UV
M_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 3.rv_dm_csr_aliasing.89417532
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.609304175
Short name T319
Test name
Test status
Simulation time 37526630675 ps
CPU time 75.39 seconds
Started Mar 19 02:55:04 PM PDT 24
Finished Mar 19 02:56:20 PM PDT 24
Peak memory 213064 kb
Host smart-13c18615-7d67-4101-916d-9b715f27253d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609304175 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.609304175
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1334044923
Short name T343
Test name
Test status
Simulation time 88177948 ps
CPU time 1.67 seconds
Started Mar 19 02:55:02 PM PDT 24
Finished Mar 19 02:55:04 PM PDT 24
Peak memory 212936 kb
Host smart-8fb42445-c797-470e-a518-3ffbae49f766
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334044923 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.1334044923
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.3344397086
Short name T342
Test name
Test status
Simulation time 2232735411 ps
CPU time 4.34 seconds
Started Mar 19 02:55:05 PM PDT 24
Finished Mar 19 02:55:09 PM PDT 24
Peak memory 214824 kb
Host smart-1a3f5a65-db81-458f-8537-4f75a3f8ba2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344397086 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.3344397086
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.306929989
Short name T101
Test name
Test status
Simulation time 153588998 ps
CPU time 1.45 seconds
Started Mar 19 02:55:05 PM PDT 24
Finished Mar 19 02:55:06 PM PDT 24
Peak memory 218468 kb
Host smart-053f45b8-fe1a-4040-b8e9-18fc92989640
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306929989 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.306929989
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.2596835387
Short name T334
Test name
Test status
Simulation time 3806310057 ps
CPU time 16.21 seconds
Started Mar 19 02:55:19 PM PDT 24
Finished Mar 19 02:55:35 PM PDT 24
Peak memory 204668 kb
Host smart-7b9cb367-84d9-49bd-97ed-e6e4a2f1e386
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596835387 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.2596835387
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1678482571
Short name T238
Test name
Test status
Simulation time 14842623185 ps
CPU time 66.35 seconds
Started Mar 19 02:55:08 PM PDT 24
Finished Mar 19 02:56:14 PM PDT 24
Peak memory 204772 kb
Host smart-9b4b261c-e85c-4921-9814-b92433da92bd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678482571 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_bit_bash.1678482571
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.1015979956
Short name T332
Test name
Test status
Simulation time 310770881 ps
CPU time 1.84 seconds
Started Mar 19 02:55:18 PM PDT 24
Finished Mar 19 02:55:20 PM PDT 24
Peak memory 204520 kb
Host smart-424525fb-c531-4019-bdfc-07b5c05480ec
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015979956 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.1015979956
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3090915405
Short name T298
Test name
Test status
Simulation time 334556635 ps
CPU time 1.83 seconds
Started Mar 19 02:55:08 PM PDT 24
Finished Mar 19 02:55:09 PM PDT 24
Peak memory 204688 kb
Host smart-42595d65-7cdd-4d65-9017-c7b03bab3c2a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090915405 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.3
090915405
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1617489276
Short name T355
Test name
Test status
Simulation time 187172390 ps
CPU time 0.93 seconds
Started Mar 19 02:55:18 PM PDT 24
Finished Mar 19 02:55:19 PM PDT 24
Peak memory 204296 kb
Host smart-77616528-3b4a-4e85-9ffb-451913edfd0b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617489276 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.1617489276
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2674397019
Short name T322
Test name
Test status
Simulation time 5478428893 ps
CPU time 16.91 seconds
Started Mar 19 02:55:04 PM PDT 24
Finished Mar 19 02:55:21 PM PDT 24
Peak memory 204752 kb
Host smart-ef20a501-83ff-4643-81b6-3f234c33f955
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674397019 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.2674397019
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1197967257
Short name T349
Test name
Test status
Simulation time 182964319 ps
CPU time 0.95 seconds
Started Mar 19 02:55:03 PM PDT 24
Finished Mar 19 02:55:04 PM PDT 24
Peak memory 204496 kb
Host smart-d0c38869-20b7-45e2-9561-0388a66a82ef
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197967257 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.1197967257
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.580747351
Short name T259
Test name
Test status
Simulation time 51404593 ps
CPU time 0.69 seconds
Started Mar 19 02:55:06 PM PDT 24
Finished Mar 19 02:55:07 PM PDT 24
Peak memory 204472 kb
Host smart-8f4f1781-bf12-4c1a-af4a-c32b7aa61bbb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580747351 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.580747351
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.3553134560
Short name T235
Test name
Test status
Simulation time 18048147 ps
CPU time 0.67 seconds
Started Mar 19 02:55:06 PM PDT 24
Finished Mar 19 02:55:07 PM PDT 24
Peak memory 204480 kb
Host smart-5db16648-baf0-4d06-9b5b-adb23a7a9df2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553134560 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.3553134560
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1595920909
Short name T364
Test name
Test status
Simulation time 73868482 ps
CPU time 0.67 seconds
Started Mar 19 02:55:18 PM PDT 24
Finished Mar 19 02:55:19 PM PDT 24
Peak memory 204404 kb
Host smart-31792b20-ec32-40b4-ad4d-76142e62c3b2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595920909 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.1595920909
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.4288391827
Short name T42
Test name
Test status
Simulation time 478079311 ps
CPU time 6.66 seconds
Started Mar 19 02:55:05 PM PDT 24
Finished Mar 19 02:55:12 PM PDT 24
Peak memory 204744 kb
Host smart-a4fe9ee2-5999-405d-8765-58fb9dcb23f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288391827 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.4288391827
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.3828391918
Short name T38
Test name
Test status
Simulation time 22211774625 ps
CPU time 9.67 seconds
Started Mar 19 02:55:03 PM PDT 24
Finished Mar 19 02:55:13 PM PDT 24
Peak memory 218680 kb
Host smart-6a2c55f3-d13f-451b-83d6-088719bfd655
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828391918 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.3828391918
Directory /workspace/3.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2379415542
Short name T300
Test name
Test status
Simulation time 170134637 ps
CPU time 2.76 seconds
Started Mar 19 02:55:08 PM PDT 24
Finished Mar 19 02:55:12 PM PDT 24
Peak memory 215088 kb
Host smart-6ab7cea3-bc9a-49c3-82e8-b2b89d009234
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379415542 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.2379415542
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2804022978
Short name T359
Test name
Test status
Simulation time 3165604882 ps
CPU time 15.75 seconds
Started Mar 19 02:55:05 PM PDT 24
Finished Mar 19 02:55:21 PM PDT 24
Peak memory 213076 kb
Host smart-dbfe7e5f-4909-4a7f-afc1-9d4ac2e8a0f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804022978 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.2804022978
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_dm_tap_fsm_rand_reset.1726062190
Short name T281
Test name
Test status
Simulation time 11659354632 ps
CPU time 10.61 seconds
Started Mar 19 02:55:39 PM PDT 24
Finished Mar 19 02:55:50 PM PDT 24
Peak memory 215120 kb
Host smart-b4738a52-c546-4262-a07c-c10ceafce7e7
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726062190 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 30.rv_dm_tap_fsm_rand_reset.1726062190
Directory /workspace/30.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/31.rv_dm_tap_fsm_rand_reset.1737254167
Short name T365
Test name
Test status
Simulation time 5460342521 ps
CPU time 11.47 seconds
Started Mar 19 02:55:38 PM PDT 24
Finished Mar 19 02:55:50 PM PDT 24
Peak memory 221212 kb
Host smart-08c5ab61-70d2-4150-9f38-3ca2dd162ed8
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737254167 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 31.rv_dm_tap_fsm_rand_reset.1737254167
Directory /workspace/31.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/32.rv_dm_tap_fsm_rand_reset.120566779
Short name T345
Test name
Test status
Simulation time 10907177831 ps
CPU time 35.29 seconds
Started Mar 19 02:55:45 PM PDT 24
Finished Mar 19 02:56:22 PM PDT 24
Peak memory 221208 kb
Host smart-0cbab1be-57de-4354-b328-a2c32929f7e3
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120566779 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 32.rv_dm_tap_fsm_rand_reset.120566779
Directory /workspace/32.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/33.rv_dm_tap_fsm_rand_reset.3740648955
Short name T311
Test name
Test status
Simulation time 6628336786 ps
CPU time 12.99 seconds
Started Mar 19 02:55:37 PM PDT 24
Finished Mar 19 02:55:50 PM PDT 24
Peak memory 221084 kb
Host smart-159ad302-1a6f-42d5-b139-67117573cd42
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740648955 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 33.rv_dm_tap_fsm_rand_reset.3740648955
Directory /workspace/33.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/35.rv_dm_tap_fsm_rand_reset.2409379036
Short name T133
Test name
Test status
Simulation time 4869471114 ps
CPU time 16.19 seconds
Started Mar 19 02:55:42 PM PDT 24
Finished Mar 19 02:55:59 PM PDT 24
Peak memory 217268 kb
Host smart-bbe3ac03-36d9-4842-ae8a-b3551687ae73
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409379036 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 35.rv_dm_tap_fsm_rand_reset.2409379036
Directory /workspace/35.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.3519655837
Short name T105
Test name
Test status
Simulation time 550078345 ps
CPU time 27.41 seconds
Started Mar 19 02:55:04 PM PDT 24
Finished Mar 19 02:55:32 PM PDT 24
Peak memory 204756 kb
Host smart-6a5317f7-142b-4d30-be87-22f003e1fa39
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519655837 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.3519655837
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.1982226555
Short name T96
Test name
Test status
Simulation time 19495403054 ps
CPU time 67.12 seconds
Started Mar 19 02:55:03 PM PDT 24
Finished Mar 19 02:56:10 PM PDT 24
Peak memory 213052 kb
Host smart-6688888a-1186-4d5f-a457-d4b173b6450f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982226555 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.1982226555
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.336662460
Short name T103
Test name
Test status
Simulation time 269571321 ps
CPU time 2.19 seconds
Started Mar 19 02:55:19 PM PDT 24
Finished Mar 19 02:55:21 PM PDT 24
Peak memory 212912 kb
Host smart-df9e400d-5b92-4786-ac7a-601c29a95732
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336662460 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.336662460
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.1850306981
Short name T353
Test name
Test status
Simulation time 3075996667 ps
CPU time 6.83 seconds
Started Mar 19 02:55:05 PM PDT 24
Finished Mar 19 02:55:12 PM PDT 24
Peak memory 221128 kb
Host smart-a2497b85-d8be-4e64-9f5c-c73feca9f39b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850306981 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.1850306981
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.1852433913
Short name T370
Test name
Test status
Simulation time 63360963 ps
CPU time 1.59 seconds
Started Mar 19 02:55:07 PM PDT 24
Finished Mar 19 02:55:08 PM PDT 24
Peak memory 212884 kb
Host smart-c63f8a1b-ce06-4e0c-bb59-cb77a480c170
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852433913 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.1852433913
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.1342850750
Short name T286
Test name
Test status
Simulation time 6797504666 ps
CPU time 22.56 seconds
Started Mar 19 02:55:06 PM PDT 24
Finished Mar 19 02:55:29 PM PDT 24
Peak memory 204796 kb
Host smart-4b18a22e-f78d-4dc8-b1fe-5e27b5a862f0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342850750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.1342850750
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.2696565532
Short name T232
Test name
Test status
Simulation time 12605864194 ps
CPU time 51.25 seconds
Started Mar 19 02:55:04 PM PDT 24
Finished Mar 19 02:55:55 PM PDT 24
Peak memory 204732 kb
Host smart-5d0e31d6-8ad9-42a9-b4fa-3dbe455759c1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696565532 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_bit_bash.2696565532
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2356723529
Short name T234
Test name
Test status
Simulation time 846958833 ps
CPU time 1.49 seconds
Started Mar 19 02:55:04 PM PDT 24
Finished Mar 19 02:55:05 PM PDT 24
Peak memory 204728 kb
Host smart-e997655c-2b1c-4885-a30e-ebf0b1370ca5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356723529 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.2356723529
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.2803109090
Short name T255
Test name
Test status
Simulation time 243540593 ps
CPU time 1.35 seconds
Started Mar 19 02:55:08 PM PDT 24
Finished Mar 19 02:55:10 PM PDT 24
Peak memory 204688 kb
Host smart-faafef33-e0d9-4195-bea4-055dbb6e5588
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803109090 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.2
803109090
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.580067525
Short name T261
Test name
Test status
Simulation time 187360836 ps
CPU time 0.83 seconds
Started Mar 19 02:55:03 PM PDT 24
Finished Mar 19 02:55:04 PM PDT 24
Peak memory 204484 kb
Host smart-7814c5c6-1d6e-4985-9635-cabc02690a60
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580067525 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr
_aliasing.580067525
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.1806734889
Short name T289
Test name
Test status
Simulation time 2279870411 ps
CPU time 3.07 seconds
Started Mar 19 02:55:18 PM PDT 24
Finished Mar 19 02:55:22 PM PDT 24
Peak memory 204736 kb
Host smart-9e9c7f6d-2d08-4dfe-8afa-fa6c647ed150
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806734889 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.1806734889
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2655624127
Short name T352
Test name
Test status
Simulation time 81878902 ps
CPU time 1 seconds
Started Mar 19 02:55:04 PM PDT 24
Finished Mar 19 02:55:05 PM PDT 24
Peak memory 204480 kb
Host smart-0786b955-3182-4357-a40d-d23fb7703ac7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655624127 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.2655624127
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.3019938104
Short name T326
Test name
Test status
Simulation time 116609287 ps
CPU time 0.72 seconds
Started Mar 19 02:55:06 PM PDT 24
Finished Mar 19 02:55:07 PM PDT 24
Peak memory 204336 kb
Host smart-de950a83-59d9-4434-8680-8eb19c15a467
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019938104 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.3
019938104
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.3771488380
Short name T271
Test name
Test status
Simulation time 42723347 ps
CPU time 0.68 seconds
Started Mar 19 02:55:06 PM PDT 24
Finished Mar 19 02:55:07 PM PDT 24
Peak memory 204352 kb
Host smart-706523a3-e358-4df9-8f62-0f3ac4656362
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771488380 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.3771488380
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.2664093751
Short name T327
Test name
Test status
Simulation time 53126073 ps
CPU time 0.7 seconds
Started Mar 19 02:55:04 PM PDT 24
Finished Mar 19 02:55:05 PM PDT 24
Peak memory 204492 kb
Host smart-b069710c-d658-4a88-83ab-a4f4a5dcff06
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664093751 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.2664093751
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1616236539
Short name T354
Test name
Test status
Simulation time 508906963 ps
CPU time 7.89 seconds
Started Mar 19 02:55:09 PM PDT 24
Finished Mar 19 02:55:17 PM PDT 24
Peak memory 204728 kb
Host smart-9210d433-7d8d-4bea-9293-b26c5627acf2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616236539 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.1616236539
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.3930632036
Short name T373
Test name
Test status
Simulation time 108194095 ps
CPU time 3.25 seconds
Started Mar 19 02:55:07 PM PDT 24
Finished Mar 19 02:55:11 PM PDT 24
Peak memory 213012 kb
Host smart-0fe9f2bd-86b1-4eaf-9f89-954e7dfa1678
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930632036 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.3930632036
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.2218086553
Short name T116
Test name
Test status
Simulation time 864336807 ps
CPU time 9.8 seconds
Started Mar 19 02:55:05 PM PDT 24
Finished Mar 19 02:55:15 PM PDT 24
Peak memory 212980 kb
Host smart-c3bcd08c-d750-41ca-8210-99d90bcf1270
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218086553 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.2218086553
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.2157144673
Short name T312
Test name
Test status
Simulation time 662143951 ps
CPU time 3.71 seconds
Started Mar 19 02:55:10 PM PDT 24
Finished Mar 19 02:55:14 PM PDT 24
Peak memory 221200 kb
Host smart-7ed554a4-61de-47e3-ad2a-827bae556a94
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157144673 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.2157144673
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.2839078926
Short name T306
Test name
Test status
Simulation time 88711942 ps
CPU time 2.23 seconds
Started Mar 19 02:55:03 PM PDT 24
Finished Mar 19 02:55:05 PM PDT 24
Peak memory 212884 kb
Host smart-b423b780-6627-4188-8183-712074cfbe2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839078926 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.2839078926
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.88647970
Short name T372
Test name
Test status
Simulation time 407741047 ps
CPU time 1.59 seconds
Started Mar 19 02:55:09 PM PDT 24
Finished Mar 19 02:55:11 PM PDT 24
Peak memory 204676 kb
Host smart-f084b9a6-1c85-4f27-b804-6c7fd45609fc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88647970 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.88647970
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3684854149
Short name T237
Test name
Test status
Simulation time 78714857 ps
CPU time 0.73 seconds
Started Mar 19 02:55:04 PM PDT 24
Finished Mar 19 02:55:05 PM PDT 24
Peak memory 204456 kb
Host smart-12d673b2-1b08-44d8-b48a-e97c3dbdbaaf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684854149 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.3
684854149
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1071383085
Short name T83
Test name
Test status
Simulation time 100125081 ps
CPU time 3.62 seconds
Started Mar 19 02:55:19 PM PDT 24
Finished Mar 19 02:55:22 PM PDT 24
Peak memory 204640 kb
Host smart-70d2e252-e022-4b1a-983d-4f0edb70be1d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071383085 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.1071383085
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.225422295
Short name T78
Test name
Test status
Simulation time 36524266 ps
CPU time 1.8 seconds
Started Mar 19 02:55:07 PM PDT 24
Finished Mar 19 02:55:09 PM PDT 24
Peak memory 212936 kb
Host smart-51139a67-0c6e-448d-a40d-77b9e909edbf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225422295 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.225422295
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.1094725970
Short name T128
Test name
Test status
Simulation time 2263279484 ps
CPU time 9.6 seconds
Started Mar 19 02:55:05 PM PDT 24
Finished Mar 19 02:55:15 PM PDT 24
Peak memory 213104 kb
Host smart-617a5f76-c8fb-4661-9d57-b1317a81751d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094725970 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.1094725970
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.1423509982
Short name T308
Test name
Test status
Simulation time 3977832237 ps
CPU time 10.05 seconds
Started Mar 19 02:55:11 PM PDT 24
Finished Mar 19 02:55:21 PM PDT 24
Peak memory 218260 kb
Host smart-316b12cb-6500-43da-8ed8-31a2f8a536e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423509982 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.1423509982
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1201843344
Short name T110
Test name
Test status
Simulation time 220453013 ps
CPU time 1.63 seconds
Started Mar 19 02:55:12 PM PDT 24
Finished Mar 19 02:55:14 PM PDT 24
Peak memory 212932 kb
Host smart-1ce1bfe2-a383-4dd2-b665-cffb15566faf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201843344 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.1201843344
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.797996247
Short name T341
Test name
Test status
Simulation time 127957379 ps
CPU time 1.23 seconds
Started Mar 19 02:55:12 PM PDT 24
Finished Mar 19 02:55:14 PM PDT 24
Peak memory 204660 kb
Host smart-984a6061-33c2-4f5d-8c47-535f24ac40e8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797996247 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.797996247
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2224406914
Short name T293
Test name
Test status
Simulation time 102642390 ps
CPU time 0.77 seconds
Started Mar 19 02:55:10 PM PDT 24
Finished Mar 19 02:55:11 PM PDT 24
Peak memory 204464 kb
Host smart-781394bb-2ce1-4afc-8d0e-9e0e5825472f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224406914 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.2
224406914
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2075840012
Short name T278
Test name
Test status
Simulation time 854037598 ps
CPU time 8.01 seconds
Started Mar 19 02:55:13 PM PDT 24
Finished Mar 19 02:55:22 PM PDT 24
Peak memory 204800 kb
Host smart-1ae15d96-de1d-4548-b8cd-fa210337de9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075840012 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.2075840012
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.555869489
Short name T269
Test name
Test status
Simulation time 248594267 ps
CPU time 3.15 seconds
Started Mar 19 02:55:10 PM PDT 24
Finished Mar 19 02:55:13 PM PDT 24
Peak memory 212940 kb
Host smart-1e984c44-8b66-44b2-8e7c-a4cd9e5c3929
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555869489 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.555869489
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1947573860
Short name T287
Test name
Test status
Simulation time 578289915 ps
CPU time 10.17 seconds
Started Mar 19 02:55:09 PM PDT 24
Finished Mar 19 02:55:19 PM PDT 24
Peak memory 221092 kb
Host smart-c9aa0ab4-ad47-443f-8060-9349ef06c653
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947573860 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.1947573860
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.1452472933
Short name T245
Test name
Test status
Simulation time 2555190413 ps
CPU time 4.54 seconds
Started Mar 19 02:55:21 PM PDT 24
Finished Mar 19 02:55:26 PM PDT 24
Peak memory 221060 kb
Host smart-c300d7c8-9e69-4878-93a2-e5dc803663cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452472933 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.1452472933
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.3347887780
Short name T250
Test name
Test status
Simulation time 289581823 ps
CPU time 2.51 seconds
Started Mar 19 02:55:17 PM PDT 24
Finished Mar 19 02:55:20 PM PDT 24
Peak memory 212972 kb
Host smart-cf5b6745-92b7-4e60-8b9b-99f8625bd07f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347887780 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.3347887780
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.4191129116
Short name T284
Test name
Test status
Simulation time 152738087 ps
CPU time 1.31 seconds
Started Mar 19 02:55:12 PM PDT 24
Finished Mar 19 02:55:14 PM PDT 24
Peak memory 204688 kb
Host smart-414ffca1-e02e-4164-a21f-c4c35d4fbf1c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191129116 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.4
191129116
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.80511879
Short name T249
Test name
Test status
Simulation time 121595852 ps
CPU time 1 seconds
Started Mar 19 02:55:09 PM PDT 24
Finished Mar 19 02:55:11 PM PDT 24
Peak memory 204500 kb
Host smart-c1c5b467-4c9e-4651-8a62-56e8af7b234b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80511879 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.80511879
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.791877107
Short name T362
Test name
Test status
Simulation time 517133294 ps
CPU time 4.08 seconds
Started Mar 19 02:55:15 PM PDT 24
Finished Mar 19 02:55:20 PM PDT 24
Peak memory 204800 kb
Host smart-b8891150-4678-4662-b202-d76f585460ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791877107 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_c
sr_outstanding.791877107
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.541033503
Short name T39
Test name
Test status
Simulation time 244031452 ps
CPU time 3.85 seconds
Started Mar 19 02:55:13 PM PDT 24
Finished Mar 19 02:55:17 PM PDT 24
Peak memory 213000 kb
Host smart-328d005c-a110-41c5-b4c7-158648b37547
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541033503 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.541033503
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.784576577
Short name T125
Test name
Test status
Simulation time 2127203741 ps
CPU time 19.99 seconds
Started Mar 19 02:55:23 PM PDT 24
Finished Mar 19 02:55:43 PM PDT 24
Peak memory 212988 kb
Host smart-52675cd0-ab2e-417e-b8f4-113d26d4de40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784576577 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.784576577
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.3399223015
Short name T314
Test name
Test status
Simulation time 214582928 ps
CPU time 3.84 seconds
Started Mar 19 02:55:18 PM PDT 24
Finished Mar 19 02:55:22 PM PDT 24
Peak memory 218684 kb
Host smart-7e5055e1-f4dd-44fe-8314-ed372fd63b02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399223015 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.3399223015
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1110742264
Short name T109
Test name
Test status
Simulation time 57740712 ps
CPU time 1.54 seconds
Started Mar 19 02:55:21 PM PDT 24
Finished Mar 19 02:55:23 PM PDT 24
Peak memory 212928 kb
Host smart-ea23d0e1-631a-45e9-aafe-ea0e705acb73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110742264 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.1110742264
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3134589114
Short name T241
Test name
Test status
Simulation time 316135929 ps
CPU time 1.03 seconds
Started Mar 19 02:55:23 PM PDT 24
Finished Mar 19 02:55:24 PM PDT 24
Peak memory 204724 kb
Host smart-34c1cd08-b409-4ddf-ab51-38f8ac34a0e1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134589114 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.3
134589114
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2893076922
Short name T291
Test name
Test status
Simulation time 45755256 ps
CPU time 0.8 seconds
Started Mar 19 02:55:17 PM PDT 24
Finished Mar 19 02:55:18 PM PDT 24
Peak memory 204500 kb
Host smart-a9f10896-54d5-402b-83ed-7355e47c283e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893076922 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.2
893076922
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2682873211
Short name T318
Test name
Test status
Simulation time 546862073 ps
CPU time 7.97 seconds
Started Mar 19 02:55:19 PM PDT 24
Finished Mar 19 02:55:27 PM PDT 24
Peak memory 204740 kb
Host smart-7bc606f5-56fb-4543-a5de-1641d5d0fb00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682873211 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_
csr_outstanding.2682873211
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2456161007
Short name T91
Test name
Test status
Simulation time 159727043 ps
CPU time 2.61 seconds
Started Mar 19 02:55:17 PM PDT 24
Finished Mar 19 02:55:20 PM PDT 24
Peak memory 212996 kb
Host smart-5328c953-cf28-46f6-919c-53fa7e6cf605
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456161007 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.2456161007
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.1891095090
Short name T350
Test name
Test status
Simulation time 632125433 ps
CPU time 17.03 seconds
Started Mar 19 02:55:17 PM PDT 24
Finished Mar 19 02:55:34 PM PDT 24
Peak memory 212964 kb
Host smart-4a8ef182-b681-473c-8002-8c818c238e7e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891095090 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.1891095090
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.1717051645
Short name T246
Test name
Test status
Simulation time 2777120773 ps
CPU time 8.46 seconds
Started Mar 19 02:55:24 PM PDT 24
Finished Mar 19 02:55:33 PM PDT 24
Peak memory 221264 kb
Host smart-3fd59ea1-4b42-4f5b-a452-f02ddb9212fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717051645 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.1717051645
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1684813316
Short name T86
Test name
Test status
Simulation time 134847735 ps
CPU time 2.27 seconds
Started Mar 19 02:55:17 PM PDT 24
Finished Mar 19 02:55:19 PM PDT 24
Peak memory 212960 kb
Host smart-092ce816-88d0-4da9-aa8f-8c0f41f32077
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684813316 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.1684813316
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.2327380850
Short name T254
Test name
Test status
Simulation time 403927819 ps
CPU time 1.11 seconds
Started Mar 19 02:55:18 PM PDT 24
Finished Mar 19 02:55:20 PM PDT 24
Peak memory 204696 kb
Host smart-9ae032e7-2a2e-409b-817b-f6c4128b95a8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327380850 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.2
327380850
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.3098324786
Short name T252
Test name
Test status
Simulation time 78375082 ps
CPU time 0.72 seconds
Started Mar 19 02:55:18 PM PDT 24
Finished Mar 19 02:55:19 PM PDT 24
Peak memory 204476 kb
Host smart-281530bf-eab9-46c8-bef4-409767cac518
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098324786 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.3
098324786
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.988217262
Short name T338
Test name
Test status
Simulation time 724179619 ps
CPU time 4.13 seconds
Started Mar 19 02:55:22 PM PDT 24
Finished Mar 19 02:55:26 PM PDT 24
Peak memory 204748 kb
Host smart-b88a2c6f-a2a7-493b-9765-471755b4b519
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988217262 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_c
sr_outstanding.988217262
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.1427219253
Short name T279
Test name
Test status
Simulation time 7323290980 ps
CPU time 12.24 seconds
Started Mar 19 02:55:16 PM PDT 24
Finished Mar 19 02:55:29 PM PDT 24
Peak memory 221228 kb
Host smart-9e67d9b0-49d5-474f-82b7-438859247c71
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427219253 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.1427219253
Directory /workspace/9.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.4045915837
Short name T40
Test name
Test status
Simulation time 1023865682 ps
CPU time 6.74 seconds
Started Mar 19 02:55:18 PM PDT 24
Finished Mar 19 02:55:25 PM PDT 24
Peak memory 212972 kb
Host smart-bd5eb5cb-7859-47f9-8675-a09691fb75f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045915837 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.4045915837
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.1551206089
Short name T130
Test name
Test status
Simulation time 9340847609 ps
CPU time 19.82 seconds
Started Mar 19 02:55:16 PM PDT 24
Finished Mar 19 02:55:37 PM PDT 24
Peak memory 213084 kb
Host smart-b95cbcac-45d2-4ab2-924f-cc98461a209d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551206089 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.1551206089
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.2213965182
Short name T212
Test name
Test status
Simulation time 52961791 ps
CPU time 0.71 seconds
Started Mar 19 02:43:20 PM PDT 24
Finished Mar 19 02:43:21 PM PDT 24
Peak memory 204896 kb
Host smart-2942a62b-aa60-4549-8e05-8776beee31c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213965182 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.2213965182
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.3580217083
Short name T176
Test name
Test status
Simulation time 20506314030 ps
CPU time 59.33 seconds
Started Mar 19 02:43:20 PM PDT 24
Finished Mar 19 02:44:20 PM PDT 24
Peak memory 213392 kb
Host smart-b05f0564-2012-4f6d-9403-1d43b865b35e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580217083 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.3580217083
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.4007966448
Short name T8
Test name
Test status
Simulation time 4085800004 ps
CPU time 7.71 seconds
Started Mar 19 02:43:24 PM PDT 24
Finished Mar 19 02:43:32 PM PDT 24
Peak memory 205144 kb
Host smart-22ed6df6-125b-4fc6-a9d6-3d396422f5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007966448 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.4007966448
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.4004537753
Short name T13
Test name
Test status
Simulation time 164302470 ps
CPU time 1.22 seconds
Started Mar 19 02:43:21 PM PDT 24
Finished Mar 19 02:43:22 PM PDT 24
Peak memory 204880 kb
Host smart-3789f843-1e8b-4542-9e82-3897d38f34de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004537753 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.4004537753
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.3428847118
Short name T23
Test name
Test status
Simulation time 1146849618 ps
CPU time 4.23 seconds
Started Mar 19 02:43:20 PM PDT 24
Finished Mar 19 02:43:24 PM PDT 24
Peak memory 205112 kb
Host smart-f2dd5e73-4986-4b75-af5f-e52faff4cc8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428847118 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.3428847118
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.3809022573
Short name T112
Test name
Test status
Simulation time 117713060 ps
CPU time 0.73 seconds
Started Mar 19 02:43:23 PM PDT 24
Finished Mar 19 02:43:24 PM PDT 24
Peak memory 204760 kb
Host smart-159cd5f0-4c5e-443b-9a1e-5f00f2d49419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809022573 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.3809022573
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.950420130
Short name T46
Test name
Test status
Simulation time 4042460034 ps
CPU time 7.08 seconds
Started Mar 19 02:43:20 PM PDT 24
Finished Mar 19 02:43:28 PM PDT 24
Peak memory 205268 kb
Host smart-828a2f02-cf4f-4e7e-9caa-317f1dd50a5e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=950420130 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_tl
_access.950420130
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.885084026
Short name T227
Test name
Test status
Simulation time 67927550 ps
CPU time 0.76 seconds
Started Mar 19 02:43:19 PM PDT 24
Finished Mar 19 02:43:20 PM PDT 24
Peak memory 204652 kb
Host smart-d2d026ff-d583-4727-8a0f-aac1559cda0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885084026 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.885084026
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.1531229260
Short name T216
Test name
Test status
Simulation time 125697072 ps
CPU time 1.17 seconds
Started Mar 19 02:43:18 PM PDT 24
Finished Mar 19 02:43:19 PM PDT 24
Peak memory 204716 kb
Host smart-9418a791-6e4d-4c69-a891-164bb481e1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531229260 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.1531229260
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.741722849
Short name T217
Test name
Test status
Simulation time 222189956 ps
CPU time 0.88 seconds
Started Mar 19 02:43:22 PM PDT 24
Finished Mar 19 02:43:23 PM PDT 24
Peak memory 204704 kb
Host smart-45b29808-63ff-4abd-a216-4e24bf012188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741722849 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.741722849
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.662211430
Short name T16
Test name
Test status
Simulation time 34840032 ps
CPU time 0.78 seconds
Started Mar 19 02:43:20 PM PDT 24
Finished Mar 19 02:43:21 PM PDT 24
Peak memory 204724 kb
Host smart-f1309ee6-29e5-45cc-acd8-91a61ca826e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662211430 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.662211430
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.3605624314
Short name T69
Test name
Test status
Simulation time 129115047 ps
CPU time 0.74 seconds
Started Mar 19 02:43:23 PM PDT 24
Finished Mar 19 02:43:24 PM PDT 24
Peak memory 204724 kb
Host smart-5f24ace0-adb4-40d1-aaef-37232ac5b6c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605624314 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.3605624314
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.829385493
Short name T76
Test name
Test status
Simulation time 46657401 ps
CPU time 0.83 seconds
Started Mar 19 02:43:22 PM PDT 24
Finished Mar 19 02:43:23 PM PDT 24
Peak memory 204848 kb
Host smart-87a81dbd-317e-4e18-a7f8-546cd5c266e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829385493 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.829385493
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.665804206
Short name T7
Test name
Test status
Simulation time 343050452 ps
CPU time 1.09 seconds
Started Mar 19 02:43:22 PM PDT 24
Finished Mar 19 02:43:23 PM PDT 24
Peak memory 204864 kb
Host smart-87f5bf6a-fbab-488b-9897-b14398f6494a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665804206 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.665804206
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.309894791
Short name T18
Test name
Test status
Simulation time 360165207 ps
CPU time 1.1 seconds
Started Mar 19 02:43:19 PM PDT 24
Finished Mar 19 02:43:20 PM PDT 24
Peak memory 204840 kb
Host smart-bb6c6e55-978a-451e-84c0-7b2a7101da80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309894791 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.309894791
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.1831875655
Short name T187
Test name
Test status
Simulation time 9071313764 ps
CPU time 16.67 seconds
Started Mar 19 02:43:19 PM PDT 24
Finished Mar 19 02:43:36 PM PDT 24
Peak memory 213520 kb
Host smart-35bb0cec-ad80-4a57-aded-13758bf24a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831875655 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.1831875655
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.336575989
Short name T26
Test name
Test status
Simulation time 306848249 ps
CPU time 1.28 seconds
Started Mar 19 02:43:25 PM PDT 24
Finished Mar 19 02:43:26 PM PDT 24
Peak memory 228928 kb
Host smart-d0df3d65-9d95-4e6a-9235-08033478405c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336575989 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.336575989
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.3200813144
Short name T206
Test name
Test status
Simulation time 659227947 ps
CPU time 1.11 seconds
Started Mar 19 02:43:24 PM PDT 24
Finished Mar 19 02:43:25 PM PDT 24
Peak memory 204624 kb
Host smart-69e6be34-a267-44b1-a457-70432e6e259f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200813144 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.3200813144
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.1936690895
Short name T228
Test name
Test status
Simulation time 464864974 ps
CPU time 1.88 seconds
Started Mar 19 02:43:23 PM PDT 24
Finished Mar 19 02:43:25 PM PDT 24
Peak memory 205156 kb
Host smart-c27bb907-b04f-4f82-bf77-f1183b990807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936690895 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.1936690895
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.2729001615
Short name T214
Test name
Test status
Simulation time 4731054552 ps
CPU time 4.76 seconds
Started Mar 19 02:43:21 PM PDT 24
Finished Mar 19 02:43:25 PM PDT 24
Peak memory 205156 kb
Host smart-edb34f5f-e568-4882-9211-7ef9c1c5fe3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729001615 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.2729001615
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.2551094129
Short name T57
Test name
Test status
Simulation time 151569724 ps
CPU time 1.1 seconds
Started Mar 19 02:43:30 PM PDT 24
Finished Mar 19 02:43:32 PM PDT 24
Peak memory 204612 kb
Host smart-ab5e37ec-367c-4dad-90c6-480845997416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551094129 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.2551094129
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.1491898421
Short name T229
Test name
Test status
Simulation time 1852002850 ps
CPU time 3.55 seconds
Started Mar 19 02:43:23 PM PDT 24
Finished Mar 19 02:43:27 PM PDT 24
Peak memory 204956 kb
Host smart-55ed48ac-119a-4600-9b83-52c71900ed71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491898421 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.1491898421
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.2829852372
Short name T25
Test name
Test status
Simulation time 43273910 ps
CPU time 0.84 seconds
Started Mar 19 02:43:29 PM PDT 24
Finished Mar 19 02:43:31 PM PDT 24
Peak memory 204836 kb
Host smart-3c4b4a5d-bce4-4371-91f4-ad8bc450d2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829852372 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.2829852372
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.4049405001
Short name T11
Test name
Test status
Simulation time 486044304 ps
CPU time 1.9 seconds
Started Mar 19 02:43:21 PM PDT 24
Finished Mar 19 02:43:23 PM PDT 24
Peak memory 205176 kb
Host smart-647d486b-57e9-4c57-a088-da918c1a8ee3
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4049405001 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.4049405001
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.1431146381
Short name T62
Test name
Test status
Simulation time 43644512 ps
CPU time 0.84 seconds
Started Mar 19 02:43:29 PM PDT 24
Finished Mar 19 02:43:29 PM PDT 24
Peak memory 204884 kb
Host smart-d474408d-d939-4978-bcb0-45828657e2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431146381 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.1431146381
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.2398778350
Short name T211
Test name
Test status
Simulation time 53808740 ps
CPU time 0.84 seconds
Started Mar 19 02:43:31 PM PDT 24
Finished Mar 19 02:43:32 PM PDT 24
Peak memory 204720 kb
Host smart-ce039ed2-3eae-4681-9073-d95b069fa729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398778350 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.2398778350
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.1857490554
Short name T202
Test name
Test status
Simulation time 245637582 ps
CPU time 0.98 seconds
Started Mar 19 02:43:31 PM PDT 24
Finished Mar 19 02:43:32 PM PDT 24
Peak memory 204516 kb
Host smart-3830c9e8-5abd-489f-a9ae-82ae433c79f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857490554 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.1857490554
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.1892982559
Short name T68
Test name
Test status
Simulation time 416441943 ps
CPU time 1.2 seconds
Started Mar 19 02:43:31 PM PDT 24
Finished Mar 19 02:43:33 PM PDT 24
Peak memory 204912 kb
Host smart-0182696e-0fa8-4d99-913e-a5466fabe711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892982559 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.1892982559
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.43195567
Short name T58
Test name
Test status
Simulation time 29904923 ps
CPU time 0.73 seconds
Started Mar 19 02:43:30 PM PDT 24
Finished Mar 19 02:43:31 PM PDT 24
Peak memory 204680 kb
Host smart-77faa178-5532-4fb6-a258-038c1b99e58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43195567 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.43195567
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.3990546678
Short name T113
Test name
Test status
Simulation time 131052248 ps
CPU time 0.86 seconds
Started Mar 19 02:43:29 PM PDT 24
Finished Mar 19 02:43:31 PM PDT 24
Peak memory 204844 kb
Host smart-5b02146e-94c1-46da-914f-ac1da7c0439c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990546678 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.3990546678
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.3632604720
Short name T2
Test name
Test status
Simulation time 235229129 ps
CPU time 1.34 seconds
Started Mar 19 02:43:29 PM PDT 24
Finished Mar 19 02:43:30 PM PDT 24
Peak memory 204864 kb
Host smart-edd78c90-d141-45ba-98c3-8aa43173471c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632604720 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.3632604720
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.3278746563
Short name T5
Test name
Test status
Simulation time 98337698 ps
CPU time 0.75 seconds
Started Mar 19 02:43:29 PM PDT 24
Finished Mar 19 02:43:30 PM PDT 24
Peak memory 204836 kb
Host smart-71dbe83b-7b52-4030-86e5-90f90a50c5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278746563 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.3278746563
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.3414228784
Short name T65
Test name
Test status
Simulation time 44742055 ps
CPU time 0.78 seconds
Started Mar 19 02:43:29 PM PDT 24
Finished Mar 19 02:43:29 PM PDT 24
Peak memory 204852 kb
Host smart-db98816e-d7cc-48b0-86fe-71ed9b3028f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414228784 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.3414228784
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.2643949722
Short name T59
Test name
Test status
Simulation time 28605051 ps
CPU time 0.83 seconds
Started Mar 19 02:43:31 PM PDT 24
Finished Mar 19 02:43:32 PM PDT 24
Peak memory 212928 kb
Host smart-f5df27da-5256-4ae8-b8e1-e398a1b9d81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643949722 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.2643949722
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.3695897543
Short name T225
Test name
Test status
Simulation time 2206214377 ps
CPU time 7.2 seconds
Started Mar 19 02:43:24 PM PDT 24
Finished Mar 19 02:43:31 PM PDT 24
Peak memory 205204 kb
Host smart-198ac867-ffbd-41db-90a1-e38815afe95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695897543 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.3695897543
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.2318714731
Short name T51
Test name
Test status
Simulation time 164463391 ps
CPU time 1.33 seconds
Started Mar 19 02:43:31 PM PDT 24
Finished Mar 19 02:43:33 PM PDT 24
Peak memory 228848 kb
Host smart-6c2337e7-9cf2-4adb-b0f6-8af24329d427
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318714731 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.2318714731
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.4140430570
Short name T172
Test name
Test status
Simulation time 196931737 ps
CPU time 1.04 seconds
Started Mar 19 02:43:20 PM PDT 24
Finished Mar 19 02:43:21 PM PDT 24
Peak memory 204752 kb
Host smart-c7ef6585-fe17-473c-9c5a-d071bfec7931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140430570 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.4140430570
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.2120477150
Short name T34
Test name
Test status
Simulation time 32637000 ps
CPU time 0.75 seconds
Started Mar 19 02:43:42 PM PDT 24
Finished Mar 19 02:43:45 PM PDT 24
Peak memory 204892 kb
Host smart-b7770cc1-24eb-454b-889c-f3ef4e3e99c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120477150 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.2120477150
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.1506236422
Short name T19
Test name
Test status
Simulation time 543144259 ps
CPU time 1.46 seconds
Started Mar 19 02:43:43 PM PDT 24
Finished Mar 19 02:43:46 PM PDT 24
Peak memory 205156 kb
Host smart-04ac935a-f704-480c-a35f-614f5623819a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506236422 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.1506236422
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.3657545160
Short name T184
Test name
Test status
Simulation time 3241712237 ps
CPU time 10.92 seconds
Started Mar 19 02:43:43 PM PDT 24
Finished Mar 19 02:43:56 PM PDT 24
Peak memory 205236 kb
Host smart-2b9a86e9-2262-4435-a7bd-9a0637a25ef4
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3657545160 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.3657545160
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.719454090
Short name T196
Test name
Test status
Simulation time 12121369607 ps
CPU time 35.88 seconds
Started Mar 19 02:43:42 PM PDT 24
Finished Mar 19 02:44:19 PM PDT 24
Peak memory 205260 kb
Host smart-564ff621-6950-4a27-80c6-9b8078b999d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719454090 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.719454090
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.2459160396
Short name T209
Test name
Test status
Simulation time 33307126 ps
CPU time 0.81 seconds
Started Mar 19 02:43:46 PM PDT 24
Finished Mar 19 02:43:48 PM PDT 24
Peak memory 204852 kb
Host smart-8e30d1a6-6f37-43b1-94a6-15bb17ce49f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459160396 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.2459160396
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.1808323824
Short name T14
Test name
Test status
Simulation time 16220875917 ps
CPU time 47.37 seconds
Started Mar 19 02:43:45 PM PDT 24
Finished Mar 19 02:44:33 PM PDT 24
Peak memory 213480 kb
Host smart-03c9202c-a739-4dab-b0b6-8fd020942749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808323824 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.1808323824
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.4226664416
Short name T165
Test name
Test status
Simulation time 9443632185 ps
CPU time 32.83 seconds
Started Mar 19 02:43:43 PM PDT 24
Finished Mar 19 02:44:18 PM PDT 24
Peak memory 213500 kb
Host smart-72fa3eeb-f027-4cec-bc99-859b5d9a511f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4226664416 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_
tl_access.4226664416
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.1399290733
Short name T12
Test name
Test status
Simulation time 631752919 ps
CPU time 2.19 seconds
Started Mar 19 02:43:43 PM PDT 24
Finished Mar 19 02:43:47 PM PDT 24
Peak memory 205176 kb
Host smart-066c8ea1-6280-4abe-83da-b044c43d2fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399290733 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.1399290733
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_stress_all.3964639220
Short name T22
Test name
Test status
Simulation time 14680929852 ps
CPU time 6.15 seconds
Started Mar 19 02:43:44 PM PDT 24
Finished Mar 19 02:43:51 PM PDT 24
Peak memory 205060 kb
Host smart-0eb56ff9-c10b-46f3-8ad9-0c3fdea779a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964639220 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.3964639220
Directory /workspace/11.rv_dm_stress_all/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.1354342062
Short name T148
Test name
Test status
Simulation time 33337525 ps
CPU time 0.71 seconds
Started Mar 19 02:43:44 PM PDT 24
Finished Mar 19 02:43:46 PM PDT 24
Peak memory 204784 kb
Host smart-32a88905-2357-43c0-8d54-d7802649780f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354342062 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.1354342062
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.314387568
Short name T115
Test name
Test status
Simulation time 13365585182 ps
CPU time 28.85 seconds
Started Mar 19 02:43:41 PM PDT 24
Finished Mar 19 02:44:11 PM PDT 24
Peak memory 215388 kb
Host smart-eac93aa6-d460-4efa-b827-9901e4f2e1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314387568 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.314387568
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.2270574120
Short name T169
Test name
Test status
Simulation time 11323636664 ps
CPU time 37.92 seconds
Started Mar 19 02:43:41 PM PDT 24
Finished Mar 19 02:44:21 PM PDT 24
Peak memory 213464 kb
Host smart-0bc5a5d1-a412-480e-a158-6ee62485521b
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2270574120 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.2270574120
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.4023306714
Short name T201
Test name
Test status
Simulation time 2759209976 ps
CPU time 10.52 seconds
Started Mar 19 02:43:47 PM PDT 24
Finished Mar 19 02:43:57 PM PDT 24
Peak memory 205300 kb
Host smart-b5f6657b-1cf7-43d6-ab68-46c7bfa0bfaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023306714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.4023306714
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.1651384958
Short name T29
Test name
Test status
Simulation time 42817997 ps
CPU time 0.75 seconds
Started Mar 19 02:43:45 PM PDT 24
Finished Mar 19 02:43:47 PM PDT 24
Peak memory 204284 kb
Host smart-0e5f5344-3d94-4f78-9062-0a0ebb61cea1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651384958 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.1651384958
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.1886957349
Short name T190
Test name
Test status
Simulation time 45761709727 ps
CPU time 150.29 seconds
Started Mar 19 02:43:45 PM PDT 24
Finished Mar 19 02:46:16 PM PDT 24
Peak memory 212876 kb
Host smart-66cfbb57-d4d9-4ba3-a77d-1360ce2bc9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886957349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.1886957349
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.1570628529
Short name T193
Test name
Test status
Simulation time 5935624479 ps
CPU time 21.84 seconds
Started Mar 19 02:43:47 PM PDT 24
Finished Mar 19 02:44:09 PM PDT 24
Peak memory 213372 kb
Host smart-73b1af62-263f-409f-81d3-0a82723fa257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570628529 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.1570628529
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.2464478862
Short name T221
Test name
Test status
Simulation time 2906011857 ps
CPU time 4.15 seconds
Started Mar 19 02:43:46 PM PDT 24
Finished Mar 19 02:43:51 PM PDT 24
Peak memory 205212 kb
Host smart-3450df7c-f54e-4a63-898c-827f3cc0807f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2464478862 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_
tl_access.2464478862
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.3016761885
Short name T183
Test name
Test status
Simulation time 3731376027 ps
CPU time 8.2 seconds
Started Mar 19 02:43:47 PM PDT 24
Finished Mar 19 02:43:56 PM PDT 24
Peak memory 205256 kb
Host smart-081092b4-0491-46ac-9fd0-d41b003cdde3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016761885 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.3016761885
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_stress_all.2166888520
Short name T32
Test name
Test status
Simulation time 2135286981 ps
CPU time 3.04 seconds
Started Mar 19 02:43:46 PM PDT 24
Finished Mar 19 02:43:50 PM PDT 24
Peak memory 205048 kb
Host smart-77bc7daf-74ed-40e3-adc8-5d5d9bccfcd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166888520 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.2166888520
Directory /workspace/13.rv_dm_stress_all/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.283655517
Short name T138
Test name
Test status
Simulation time 16875533 ps
CPU time 0.74 seconds
Started Mar 19 02:43:53 PM PDT 24
Finished Mar 19 02:43:54 PM PDT 24
Peak memory 204904 kb
Host smart-9f440b84-dca5-4057-bc08-d8e5502ba019
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283655517 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.283655517
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.2428278893
Short name T170
Test name
Test status
Simulation time 5567997972 ps
CPU time 18.65 seconds
Started Mar 19 02:43:54 PM PDT 24
Finished Mar 19 02:44:12 PM PDT 24
Peak memory 205260 kb
Host smart-fd5a357c-b0cf-460f-982e-879ebb58cd29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428278893 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.2428278893
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.4168629802
Short name T198
Test name
Test status
Simulation time 961289188 ps
CPU time 4.81 seconds
Started Mar 19 02:43:56 PM PDT 24
Finished Mar 19 02:44:01 PM PDT 24
Peak memory 205172 kb
Host smart-1acd237e-1227-440b-88ad-1cb96bd39f02
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4168629802 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.4168629802
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.8087373
Short name T205
Test name
Test status
Simulation time 2238098684 ps
CPU time 9.1 seconds
Started Mar 19 02:43:48 PM PDT 24
Finished Mar 19 02:43:57 PM PDT 24
Peak memory 205228 kb
Host smart-4500dd5e-6a60-4213-a5be-87cc2204df34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8087373 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.8087373
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.3135037453
Short name T177
Test name
Test status
Simulation time 26985616 ps
CPU time 0.77 seconds
Started Mar 19 02:43:53 PM PDT 24
Finished Mar 19 02:43:54 PM PDT 24
Peak memory 204896 kb
Host smart-382563a5-823f-47e6-80b4-0aeeb4c15d9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135037453 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.3135037453
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.1982505609
Short name T168
Test name
Test status
Simulation time 1406610353 ps
CPU time 6.25 seconds
Started Mar 19 02:43:52 PM PDT 24
Finished Mar 19 02:43:59 PM PDT 24
Peak memory 205188 kb
Host smart-127a854d-2ab5-4c22-bb9d-7413f3c3245a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982505609 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.1982505609
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.2397300725
Short name T218
Test name
Test status
Simulation time 3788241081 ps
CPU time 15.21 seconds
Started Mar 19 02:44:00 PM PDT 24
Finished Mar 19 02:44:15 PM PDT 24
Peak memory 205216 kb
Host smart-ead9a942-f92c-4489-82fb-dad21b6b226e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2397300725 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_
tl_access.2397300725
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.2533572780
Short name T200
Test name
Test status
Simulation time 4180507198 ps
CPU time 9.66 seconds
Started Mar 19 02:43:56 PM PDT 24
Finished Mar 19 02:44:06 PM PDT 24
Peak memory 205272 kb
Host smart-2cf8dd92-3bf6-4098-a032-adbe20601419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533572780 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.2533572780
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.1284249615
Short name T30
Test name
Test status
Simulation time 50418040 ps
CPU time 0.7 seconds
Started Mar 19 02:43:54 PM PDT 24
Finished Mar 19 02:43:55 PM PDT 24
Peak memory 204820 kb
Host smart-b640a795-3a13-49da-9945-362d905d128b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284249615 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.1284249615
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.362507617
Short name T215
Test name
Test status
Simulation time 24599732631 ps
CPU time 91.43 seconds
Started Mar 19 02:43:57 PM PDT 24
Finished Mar 19 02:45:28 PM PDT 24
Peak memory 213444 kb
Host smart-5dcf3e3f-0aab-4efe-90a0-52152abf8fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362507617 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.362507617
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.924079331
Short name T175
Test name
Test status
Simulation time 1586064978 ps
CPU time 3.68 seconds
Started Mar 19 02:43:57 PM PDT 24
Finished Mar 19 02:44:00 PM PDT 24
Peak memory 205192 kb
Host smart-e71835a6-caf8-41bd-8eb3-455cec127784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924079331 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.924079331
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.984139407
Short name T192
Test name
Test status
Simulation time 309208159 ps
CPU time 2.35 seconds
Started Mar 19 02:43:55 PM PDT 24
Finished Mar 19 02:43:57 PM PDT 24
Peak memory 205164 kb
Host smart-e34c9a50-6e6c-4f92-9938-c6776eb2c150
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=984139407 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_t
l_access.984139407
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.2692366473
Short name T210
Test name
Test status
Simulation time 3127402003 ps
CPU time 11.97 seconds
Started Mar 19 02:43:56 PM PDT 24
Finished Mar 19 02:44:08 PM PDT 24
Peak memory 205256 kb
Host smart-48971101-e2bf-4d81-b9b1-3eaa8765ad9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692366473 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.2692366473
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.4070412170
Short name T44
Test name
Test status
Simulation time 21648706 ps
CPU time 0.75 seconds
Started Mar 19 02:43:54 PM PDT 24
Finished Mar 19 02:43:55 PM PDT 24
Peak memory 204872 kb
Host smart-377ecda1-66e5-44cd-8507-c0f11ec4eb4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070412170 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.4070412170
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.4027612469
Short name T161
Test name
Test status
Simulation time 2081402418 ps
CPU time 6.39 seconds
Started Mar 19 02:43:52 PM PDT 24
Finished Mar 19 02:43:59 PM PDT 24
Peak memory 214356 kb
Host smart-eb164970-5261-4184-a018-6323080cbf40
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4027612469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_
tl_access.4027612469
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.1515184996
Short name T118
Test name
Test status
Simulation time 3341104362 ps
CPU time 6.74 seconds
Started Mar 19 02:43:56 PM PDT 24
Finished Mar 19 02:44:03 PM PDT 24
Peak memory 205108 kb
Host smart-6e6548f3-8705-41f1-bfc6-a40e4d4cf93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515184996 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.1515184996
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.673098628
Short name T152
Test name
Test status
Simulation time 30416289 ps
CPU time 0.74 seconds
Started Mar 19 02:43:53 PM PDT 24
Finished Mar 19 02:43:54 PM PDT 24
Peak memory 204904 kb
Host smart-39424885-a409-4792-9a7d-d1ff3aa991b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673098628 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.673098628
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.1011008492
Short name T15
Test name
Test status
Simulation time 4025451078 ps
CPU time 16.19 seconds
Started Mar 19 02:43:52 PM PDT 24
Finished Mar 19 02:44:09 PM PDT 24
Peak memory 213464 kb
Host smart-690b68d6-aab7-423f-909a-ed037639cbe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011008492 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.1011008492
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.3600959058
Short name T159
Test name
Test status
Simulation time 9260759213 ps
CPU time 32.46 seconds
Started Mar 19 02:43:55 PM PDT 24
Finished Mar 19 02:44:27 PM PDT 24
Peak memory 213420 kb
Host smart-be072ffe-a3b6-4c9c-80c1-64ff3c3ddf77
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3600959058 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_
tl_access.3600959058
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.8265173
Short name T53
Test name
Test status
Simulation time 4172835694 ps
CPU time 15.22 seconds
Started Mar 19 02:43:58 PM PDT 24
Finished Mar 19 02:44:13 PM PDT 24
Peak memory 205232 kb
Host smart-3bdf6553-4457-4be4-8254-d64934f3f18a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8265173 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.8265173
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.647066500
Short name T151
Test name
Test status
Simulation time 21284371 ps
CPU time 0.71 seconds
Started Mar 19 02:44:05 PM PDT 24
Finished Mar 19 02:44:06 PM PDT 24
Peak memory 204896 kb
Host smart-f239b72b-6a97-443b-a552-99a533016618
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647066500 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.647066500
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.3298052471
Short name T67
Test name
Test status
Simulation time 729548980 ps
CPU time 1.53 seconds
Started Mar 19 02:43:54 PM PDT 24
Finished Mar 19 02:43:55 PM PDT 24
Peak memory 205176 kb
Host smart-6b1a77d1-afe3-42c1-9d6c-395ddd17804f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3298052471 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_
tl_access.3298052471
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.4246421258
Short name T204
Test name
Test status
Simulation time 1302168714 ps
CPU time 4.55 seconds
Started Mar 19 02:43:55 PM PDT 24
Finished Mar 19 02:43:59 PM PDT 24
Peak memory 205140 kb
Host smart-9a527adf-d582-4c0d-afbb-9bee59d0546d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246421258 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.4246421258
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.1861833539
Short name T54
Test name
Test status
Simulation time 78842564 ps
CPU time 0.72 seconds
Started Mar 19 02:43:31 PM PDT 24
Finished Mar 19 02:43:32 PM PDT 24
Peak memory 204892 kb
Host smart-47fa1ff3-7468-41d4-a561-a40f61ac7f6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861833539 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.1861833539
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.2950299322
Short name T213
Test name
Test status
Simulation time 2751725393 ps
CPU time 13.32 seconds
Started Mar 19 02:43:28 PM PDT 24
Finished Mar 19 02:43:42 PM PDT 24
Peak memory 205264 kb
Host smart-189f6676-6c73-410b-9d76-b949f56a4d0c
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2950299322 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.2950299322
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.926370233
Short name T162
Test name
Test status
Simulation time 77940990 ps
CPU time 0.8 seconds
Started Mar 19 02:43:30 PM PDT 24
Finished Mar 19 02:43:31 PM PDT 24
Peak memory 204680 kb
Host smart-5a70adb7-25ed-46cd-ae6a-7b9555783385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926370233 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.926370233
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.425328781
Short name T52
Test name
Test status
Simulation time 230464396 ps
CPU time 1.15 seconds
Started Mar 19 02:43:30 PM PDT 24
Finished Mar 19 02:43:32 PM PDT 24
Peak memory 229276 kb
Host smart-26f7ead4-4acf-4006-a754-2b7bfb913652
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425328781 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.425328781
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.590338627
Short name T139
Test name
Test status
Simulation time 164266100 ps
CPU time 0.74 seconds
Started Mar 19 02:44:05 PM PDT 24
Finished Mar 19 02:44:06 PM PDT 24
Peak memory 204884 kb
Host smart-a20b5d2f-4282-47ef-9c52-5c29fa7f7fd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590338627 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.590338627
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.3660658736
Short name T144
Test name
Test status
Simulation time 16316996 ps
CPU time 0.72 seconds
Started Mar 19 02:44:05 PM PDT 24
Finished Mar 19 02:44:06 PM PDT 24
Peak memory 204828 kb
Host smart-3c3fdeb3-e164-4adf-b521-6b2fcd1afcd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660658736 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.3660658736
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.446624410
Short name T149
Test name
Test status
Simulation time 43545136 ps
CPU time 0.71 seconds
Started Mar 19 02:44:05 PM PDT 24
Finished Mar 19 02:44:06 PM PDT 24
Peak memory 204896 kb
Host smart-94da1a62-575d-43c3-b64f-08d2d98e9201
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446624410 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.446624410
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.502664198
Short name T145
Test name
Test status
Simulation time 37687023 ps
CPU time 0.73 seconds
Started Mar 19 02:44:04 PM PDT 24
Finished Mar 19 02:44:05 PM PDT 24
Peak memory 204892 kb
Host smart-2f7c3f7d-baf5-4ed0-9ca4-1ca10692a57a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502664198 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.502664198
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.227033113
Short name T164
Test name
Test status
Simulation time 63917066 ps
CPU time 0.74 seconds
Started Mar 19 02:44:06 PM PDT 24
Finished Mar 19 02:44:06 PM PDT 24
Peak memory 204884 kb
Host smart-c2d45746-9281-4632-8552-afde87d44e41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227033113 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.227033113
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.1055627124
Short name T181
Test name
Test status
Simulation time 54570090 ps
CPU time 0.7 seconds
Started Mar 19 02:44:05 PM PDT 24
Finished Mar 19 02:44:05 PM PDT 24
Peak memory 204884 kb
Host smart-a2767681-30e5-4040-9fdf-842b2157ad6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055627124 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.1055627124
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.2181535799
Short name T137
Test name
Test status
Simulation time 27535090 ps
CPU time 0.73 seconds
Started Mar 19 02:44:05 PM PDT 24
Finished Mar 19 02:44:06 PM PDT 24
Peak memory 204884 kb
Host smart-b59a85b0-64da-4125-b015-ba29e7b7b2d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181535799 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.2181535799
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.520238422
Short name T71
Test name
Test status
Simulation time 74142888 ps
CPU time 0.73 seconds
Started Mar 19 02:44:06 PM PDT 24
Finished Mar 19 02:44:07 PM PDT 24
Peak memory 204808 kb
Host smart-f3f782db-9b0f-46d5-b49f-6ca731b52b91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520238422 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.520238422
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.957232243
Short name T3
Test name
Test status
Simulation time 24685988 ps
CPU time 0.71 seconds
Started Mar 19 02:44:03 PM PDT 24
Finished Mar 19 02:44:03 PM PDT 24
Peak memory 204888 kb
Host smart-c4e51fe9-7ae6-475b-a922-80521b42dd20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957232243 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.957232243
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.3103674831
Short name T35
Test name
Test status
Simulation time 31217927 ps
CPU time 0.73 seconds
Started Mar 19 02:44:03 PM PDT 24
Finished Mar 19 02:44:03 PM PDT 24
Peak memory 204876 kb
Host smart-c49d5283-3703-4e98-8056-84f73c05fc6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103674831 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.3103674831
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.3096583298
Short name T146
Test name
Test status
Simulation time 29893777 ps
CPU time 0.74 seconds
Started Mar 19 02:43:30 PM PDT 24
Finished Mar 19 02:43:31 PM PDT 24
Peak memory 204828 kb
Host smart-67df6708-b246-4066-8c1a-7c28d223e697
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096583298 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.3096583298
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.1802037001
Short name T208
Test name
Test status
Simulation time 9947823981 ps
CPU time 19.42 seconds
Started Mar 19 02:43:31 PM PDT 24
Finished Mar 19 02:43:51 PM PDT 24
Peak memory 215084 kb
Host smart-b4cb02d0-f844-4855-95d1-686c0693a836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802037001 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.1802037001
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.2721354296
Short name T160
Test name
Test status
Simulation time 4127305861 ps
CPU time 10.05 seconds
Started Mar 19 02:43:32 PM PDT 24
Finished Mar 19 02:43:42 PM PDT 24
Peak memory 213388 kb
Host smart-bba039b1-6dde-4343-9c2f-2f40ef701b65
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2721354296 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.2721354296
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.1315562805
Short name T174
Test name
Test status
Simulation time 51658073 ps
CPU time 0.83 seconds
Started Mar 19 02:43:31 PM PDT 24
Finished Mar 19 02:43:32 PM PDT 24
Peak memory 204728 kb
Host smart-be81f48f-cdc6-4d14-bdda-5064a1f08d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315562805 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.1315562805
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.90257667
Short name T180
Test name
Test status
Simulation time 3964714793 ps
CPU time 7.2 seconds
Started Mar 19 02:43:29 PM PDT 24
Finished Mar 19 02:43:36 PM PDT 24
Peak memory 205280 kb
Host smart-7be17f7e-a481-40cf-a9f7-368f102c3251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90257667 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.90257667
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.208134122
Short name T163
Test name
Test status
Simulation time 32623192 ps
CPU time 0.73 seconds
Started Mar 19 02:44:05 PM PDT 24
Finished Mar 19 02:44:06 PM PDT 24
Peak memory 204876 kb
Host smart-415243b1-5070-405f-a98f-86b756da9ca2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208134122 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.208134122
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.1730357067
Short name T47
Test name
Test status
Simulation time 53572412 ps
CPU time 0.75 seconds
Started Mar 19 02:44:06 PM PDT 24
Finished Mar 19 02:44:07 PM PDT 24
Peak memory 204832 kb
Host smart-93f80c87-0796-4d94-9d84-abcf6f519341
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730357067 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.1730357067
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.2817463144
Short name T155
Test name
Test status
Simulation time 37241225 ps
CPU time 0.74 seconds
Started Mar 19 02:44:07 PM PDT 24
Finished Mar 19 02:44:08 PM PDT 24
Peak memory 204872 kb
Host smart-ebcd27d5-996a-4b3c-84ca-187683e2ef5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817463144 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.2817463144
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.1088272142
Short name T157
Test name
Test status
Simulation time 41155881 ps
CPU time 0.69 seconds
Started Mar 19 02:44:06 PM PDT 24
Finished Mar 19 02:44:06 PM PDT 24
Peak memory 204892 kb
Host smart-9a2326b1-f443-4a18-8d60-c5d76bbbc883
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088272142 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.1088272142
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.628277067
Short name T147
Test name
Test status
Simulation time 18786647 ps
CPU time 0.76 seconds
Started Mar 19 02:44:04 PM PDT 24
Finished Mar 19 02:44:05 PM PDT 24
Peak memory 204904 kb
Host smart-dd77088a-35c2-4a38-9d24-4e7cc8dc7d2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628277067 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.628277067
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.3616269168
Short name T167
Test name
Test status
Simulation time 47737979 ps
CPU time 0.72 seconds
Started Mar 19 02:44:05 PM PDT 24
Finished Mar 19 02:44:06 PM PDT 24
Peak memory 204876 kb
Host smart-40c0ddeb-dbe1-4ef9-a863-cd893a984314
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616269168 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.3616269168
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.1961760594
Short name T135
Test name
Test status
Simulation time 47421883 ps
CPU time 0.67 seconds
Started Mar 19 02:44:07 PM PDT 24
Finished Mar 19 02:44:07 PM PDT 24
Peak memory 204892 kb
Host smart-e36bbb3d-a1a8-4a7a-b6ce-c71e199b4a0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961760594 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.1961760594
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.3668353439
Short name T142
Test name
Test status
Simulation time 55704648 ps
CPU time 0.73 seconds
Started Mar 19 02:44:08 PM PDT 24
Finished Mar 19 02:44:08 PM PDT 24
Peak memory 204868 kb
Host smart-3127df48-8c58-41c3-97b2-f010c8242c1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668353439 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.3668353439
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.4024125470
Short name T156
Test name
Test status
Simulation time 82355236 ps
CPU time 0.7 seconds
Started Mar 19 02:44:08 PM PDT 24
Finished Mar 19 02:44:08 PM PDT 24
Peak memory 204820 kb
Host smart-e3e4116a-4108-4bc0-890e-dd7208d2f195
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024125470 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.4024125470
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.1443422568
Short name T179
Test name
Test status
Simulation time 27179121 ps
CPU time 0.72 seconds
Started Mar 19 02:44:09 PM PDT 24
Finished Mar 19 02:44:10 PM PDT 24
Peak memory 204876 kb
Host smart-e6457b39-ab59-4b28-ac5c-8d941eb763e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443422568 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.1443422568
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.2821653253
Short name T199
Test name
Test status
Simulation time 49575646 ps
CPU time 0.72 seconds
Started Mar 19 02:43:42 PM PDT 24
Finished Mar 19 02:43:44 PM PDT 24
Peak memory 204768 kb
Host smart-063e7954-0a5b-47e1-826d-8f6adc4fd425
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821653253 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.2821653253
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.1106412807
Short name T21
Test name
Test status
Simulation time 16956733112 ps
CPU time 20.87 seconds
Started Mar 19 02:43:40 PM PDT 24
Finished Mar 19 02:44:01 PM PDT 24
Peak memory 213480 kb
Host smart-316feb4c-5934-4f8e-affe-06df30fbe4e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106412807 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.1106412807
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.1609738290
Short name T45
Test name
Test status
Simulation time 853820187 ps
CPU time 4.07 seconds
Started Mar 19 02:43:41 PM PDT 24
Finished Mar 19 02:43:47 PM PDT 24
Peak memory 205204 kb
Host smart-99ae0a99-eb7a-419c-8eff-af576deba949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609738290 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.1609738290
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.24738764
Short name T186
Test name
Test status
Simulation time 3415507882 ps
CPU time 5.94 seconds
Started Mar 19 02:43:42 PM PDT 24
Finished Mar 19 02:43:50 PM PDT 24
Peak memory 213448 kb
Host smart-80d47342-8d3f-4a4e-a700-baccfa9215e6
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=24738764 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_tl_
access.24738764
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.3241519952
Short name T207
Test name
Test status
Simulation time 85595114 ps
CPU time 0.73 seconds
Started Mar 19 02:43:41 PM PDT 24
Finished Mar 19 02:43:42 PM PDT 24
Peak memory 204704 kb
Host smart-866f794d-5174-4029-9726-57b2100a29c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241519952 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.3241519952
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.2282971902
Short name T194
Test name
Test status
Simulation time 1219957305 ps
CPU time 4.22 seconds
Started Mar 19 02:43:29 PM PDT 24
Finished Mar 19 02:43:33 PM PDT 24
Peak memory 205152 kb
Host smart-8bb58981-7747-49db-8131-671e8cef4656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282971902 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.2282971902
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.2202352065
Short name T28
Test name
Test status
Simulation time 103707302 ps
CPU time 1.33 seconds
Started Mar 19 02:43:46 PM PDT 24
Finished Mar 19 02:43:48 PM PDT 24
Peak memory 229336 kb
Host smart-28d6e89f-b118-4b20-b3dd-cbd46f11800e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202352065 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.2202352065
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.1392142921
Short name T56
Test name
Test status
Simulation time 23862552 ps
CPU time 0.68 seconds
Started Mar 19 02:44:14 PM PDT 24
Finished Mar 19 02:44:15 PM PDT 24
Peak memory 204784 kb
Host smart-400691a3-3184-453e-9cdf-a982659802b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392142921 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.1392142921
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.267668238
Short name T140
Test name
Test status
Simulation time 31429457 ps
CPU time 0.7 seconds
Started Mar 19 02:44:14 PM PDT 24
Finished Mar 19 02:44:15 PM PDT 24
Peak memory 204808 kb
Host smart-72b25be9-811a-4ffb-ab2c-53a84e3ccca1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267668238 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.267668238
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_stress_all.178693964
Short name T33
Test name
Test status
Simulation time 433877267 ps
CPU time 2.19 seconds
Started Mar 19 02:44:09 PM PDT 24
Finished Mar 19 02:44:12 PM PDT 24
Peak memory 205072 kb
Host smart-d92ff15e-f9a7-4297-95f7-0d09485fb386
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178693964 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.178693964
Directory /workspace/41.rv_dm_stress_all/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.1390177582
Short name T171
Test name
Test status
Simulation time 27616633 ps
CPU time 0.75 seconds
Started Mar 19 02:44:09 PM PDT 24
Finished Mar 19 02:44:09 PM PDT 24
Peak memory 204876 kb
Host smart-f937811e-d884-4670-b03b-450dc5b31ae8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390177582 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.1390177582
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.4202628701
Short name T141
Test name
Test status
Simulation time 34856583 ps
CPU time 0.76 seconds
Started Mar 19 02:44:09 PM PDT 24
Finished Mar 19 02:44:10 PM PDT 24
Peak memory 204808 kb
Host smart-6046be6d-f8c4-4b00-b11c-ec2e3e8aa8ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202628701 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.4202628701
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.1676778365
Short name T154
Test name
Test status
Simulation time 97252973 ps
CPU time 0.76 seconds
Started Mar 19 02:44:13 PM PDT 24
Finished Mar 19 02:44:14 PM PDT 24
Peak memory 204880 kb
Host smart-63885868-9edc-4349-8a05-ca444bb35e28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676778365 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.1676778365
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.3999685149
Short name T89
Test name
Test status
Simulation time 92844189 ps
CPU time 0.7 seconds
Started Mar 19 02:44:14 PM PDT 24
Finished Mar 19 02:44:15 PM PDT 24
Peak memory 204828 kb
Host smart-f27ec165-b234-4ba1-b13d-fd0f2c49e80e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999685149 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.3999685149
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.1067943151
Short name T134
Test name
Test status
Simulation time 25938244 ps
CPU time 0.76 seconds
Started Mar 19 02:44:14 PM PDT 24
Finished Mar 19 02:44:15 PM PDT 24
Peak memory 204860 kb
Host smart-2ed02d36-3ffb-4733-8abd-03e519515d65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067943151 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.1067943151
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.2438007910
Short name T136
Test name
Test status
Simulation time 34218292 ps
CPU time 0.69 seconds
Started Mar 19 02:44:13 PM PDT 24
Finished Mar 19 02:44:14 PM PDT 24
Peak memory 204892 kb
Host smart-81ffa14c-9f6d-4bd6-a0cd-5b18c0d18377
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438007910 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.2438007910
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.1100756926
Short name T143
Test name
Test status
Simulation time 29448790 ps
CPU time 0.74 seconds
Started Mar 19 02:44:16 PM PDT 24
Finished Mar 19 02:44:17 PM PDT 24
Peak memory 204868 kb
Host smart-874f0f88-28e3-45b0-8aa3-f31d2eedfb47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100756926 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.1100756926
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.2598387522
Short name T48
Test name
Test status
Simulation time 33751017 ps
CPU time 0.69 seconds
Started Mar 19 02:43:43 PM PDT 24
Finished Mar 19 02:43:45 PM PDT 24
Peak memory 204872 kb
Host smart-0f8f72b7-eaf0-4e2f-8a7c-0100cdcf803f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598387522 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.2598387522
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.3281527628
Short name T55
Test name
Test status
Simulation time 3439175342 ps
CPU time 16.62 seconds
Started Mar 19 02:43:40 PM PDT 24
Finished Mar 19 02:43:57 PM PDT 24
Peak memory 213448 kb
Host smart-83675755-6bcb-49d0-8e95-6be54736f4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281527628 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.3281527628
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.3030051294
Short name T220
Test name
Test status
Simulation time 4702304513 ps
CPU time 12.07 seconds
Started Mar 19 02:43:42 PM PDT 24
Finished Mar 19 02:43:56 PM PDT 24
Peak memory 213380 kb
Host smart-8c863b0c-ba37-48a7-8352-563b327586ba
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3030051294 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t
l_access.3030051294
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.1215337350
Short name T158
Test name
Test status
Simulation time 841163022 ps
CPU time 1.8 seconds
Started Mar 19 02:43:41 PM PDT 24
Finished Mar 19 02:43:44 PM PDT 24
Peak memory 205192 kb
Host smart-431ed9da-0d9f-47ff-b0d3-b1d87e6b022f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215337350 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.1215337350
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.2177473052
Short name T153
Test name
Test status
Simulation time 49071929 ps
CPU time 0.72 seconds
Started Mar 19 02:43:42 PM PDT 24
Finished Mar 19 02:43:44 PM PDT 24
Peak memory 204840 kb
Host smart-55baf4b9-b0fc-4cff-895f-854ad7c41ac0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177473052 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.2177473052
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.2269258947
Short name T188
Test name
Test status
Simulation time 10941201940 ps
CPU time 9.61 seconds
Started Mar 19 02:43:41 PM PDT 24
Finished Mar 19 02:43:51 PM PDT 24
Peak memory 215580 kb
Host smart-6ad477bc-10e5-4937-b08b-fa6291044644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269258947 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.2269258947
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.847783576
Short name T203
Test name
Test status
Simulation time 2677587160 ps
CPU time 10.84 seconds
Started Mar 19 02:43:40 PM PDT 24
Finished Mar 19 02:43:52 PM PDT 24
Peak memory 205160 kb
Host smart-2bb9696b-7504-4e02-ab55-4156b3e4c182
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=847783576 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_tl
_access.847783576
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.2676889135
Short name T195
Test name
Test status
Simulation time 2785701718 ps
CPU time 8.53 seconds
Started Mar 19 02:43:43 PM PDT 24
Finished Mar 19 02:43:53 PM PDT 24
Peak memory 205280 kb
Host smart-0f051dcb-2127-4817-932f-f68dc39dda35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676889135 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.2676889135
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.2404593468
Short name T150
Test name
Test status
Simulation time 33672319 ps
CPU time 0.74 seconds
Started Mar 19 02:43:40 PM PDT 24
Finished Mar 19 02:43:41 PM PDT 24
Peak memory 204904 kb
Host smart-63cd5e61-0d8a-4c42-b9fd-c92e39522faa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404593468 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.2404593468
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.4025824988
Short name T20
Test name
Test status
Simulation time 4915124265 ps
CPU time 9.3 seconds
Started Mar 19 02:43:40 PM PDT 24
Finished Mar 19 02:43:50 PM PDT 24
Peak memory 205176 kb
Host smart-63114d6c-0f8c-4430-a8e2-e0c0388a90e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025824988 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.4025824988
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.622334840
Short name T223
Test name
Test status
Simulation time 3630202863 ps
CPU time 15.8 seconds
Started Mar 19 02:43:43 PM PDT 24
Finished Mar 19 02:44:00 PM PDT 24
Peak memory 214908 kb
Host smart-3100b773-2120-4732-925d-736cbaba24eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622334840 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.622334840
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.3254162500
Short name T191
Test name
Test status
Simulation time 1831391321 ps
CPU time 9.75 seconds
Started Mar 19 02:43:40 PM PDT 24
Finished Mar 19 02:43:50 PM PDT 24
Peak memory 205204 kb
Host smart-529aa7da-d9ed-42df-b3d9-755508b38086
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3254162500 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.3254162500
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.3591893943
Short name T197
Test name
Test status
Simulation time 3374371953 ps
CPU time 8 seconds
Started Mar 19 02:43:42 PM PDT 24
Finished Mar 19 02:43:52 PM PDT 24
Peak memory 205188 kb
Host smart-a34f09f9-c003-4f44-9ee7-098370ded9fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591893943 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.3591893943
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.245792792
Short name T49
Test name
Test status
Simulation time 49556644 ps
CPU time 0.7 seconds
Started Mar 19 02:43:41 PM PDT 24
Finished Mar 19 02:43:44 PM PDT 24
Peak memory 204860 kb
Host smart-9153ce7b-8648-439d-a0ad-c246ebd1cf8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245792792 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.245792792
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.3775820455
Short name T219
Test name
Test status
Simulation time 1050137713 ps
CPU time 4.65 seconds
Started Mar 19 02:43:41 PM PDT 24
Finished Mar 19 02:43:48 PM PDT 24
Peak memory 205236 kb
Host smart-c1bd42f2-f8d1-4bbf-b426-2b59db37df18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775820455 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.3775820455
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.3572837810
Short name T189
Test name
Test status
Simulation time 2307849554 ps
CPU time 8.4 seconds
Started Mar 19 02:43:41 PM PDT 24
Finished Mar 19 02:43:51 PM PDT 24
Peak memory 205204 kb
Host smart-5060c5bc-bb50-4173-95b4-4e82423fd8de
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3572837810 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t
l_access.3572837810
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.3800810169
Short name T224
Test name
Test status
Simulation time 8350045995 ps
CPU time 16.78 seconds
Started Mar 19 02:43:41 PM PDT 24
Finished Mar 19 02:44:00 PM PDT 24
Peak memory 213432 kb
Host smart-aacc718d-9ebd-4126-90a3-81d1839baea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800810169 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.3800810169
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.2276957013
Short name T50
Test name
Test status
Simulation time 51738042 ps
CPU time 0.72 seconds
Started Mar 19 02:43:42 PM PDT 24
Finished Mar 19 02:43:44 PM PDT 24
Peak memory 204864 kb
Host smart-44a155f8-5b2d-4d40-bf7c-fdc4073dc631
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276957013 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.2276957013
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.1303846879
Short name T222
Test name
Test status
Simulation time 48942907282 ps
CPU time 39.51 seconds
Started Mar 19 02:43:43 PM PDT 24
Finished Mar 19 02:44:24 PM PDT 24
Peak memory 213440 kb
Host smart-dd721ee5-87fd-4007-9f68-7d4d86924467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303846879 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.1303846879
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.1316463780
Short name T226
Test name
Test status
Simulation time 4056622613 ps
CPU time 15.87 seconds
Started Mar 19 02:43:43 PM PDT 24
Finished Mar 19 02:44:01 PM PDT 24
Peak memory 215264 kb
Host smart-096b2696-cf1b-4403-ad25-4dddfba6c81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316463780 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.1316463780
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.95452171
Short name T185
Test name
Test status
Simulation time 4343207204 ps
CPU time 6.52 seconds
Started Mar 19 02:43:45 PM PDT 24
Finished Mar 19 02:43:52 PM PDT 24
Peak memory 213440 kb
Host smart-e30df673-2641-49ea-8f71-f3465d58d367
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=95452171 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_tl_
access.95452171
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.3996695793
Short name T173
Test name
Test status
Simulation time 2263641255 ps
CPU time 5.79 seconds
Started Mar 19 02:43:39 PM PDT 24
Finished Mar 19 02:43:45 PM PDT 24
Peak memory 205160 kb
Host smart-5d008914-3f65-49d1-a81b-6db481924f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996695793 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.3996695793
Directory /workspace/9.rv_dm_sba_tl_access/latest
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