Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
80.32 94.44 79.92 87.69 78.21 83.66 98.42 39.88


Total test records in report: 381
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T274 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.4129882154 Mar 21 03:10:06 PM PDT 24 Mar 21 03:10:07 PM PDT 24 27516264 ps
T97 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.3388576428 Mar 21 03:10:18 PM PDT 24 Mar 21 03:10:20 PM PDT 24 48973090 ps
T275 /workspace/coverage/cover_reg_top/35.rv_dm_tap_fsm_rand_reset.2930143138 Mar 21 03:11:01 PM PDT 24 Mar 21 03:11:24 PM PDT 24 6175163024 ps
T276 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2034906827 Mar 21 03:10:09 PM PDT 24 Mar 21 03:10:11 PM PDT 24 44100602 ps
T277 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2675057224 Mar 21 03:09:40 PM PDT 24 Mar 21 03:09:41 PM PDT 24 575447296 ps
T98 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.1975322912 Mar 21 03:09:38 PM PDT 24 Mar 21 03:09:47 PM PDT 24 522084471 ps
T278 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2800115946 Mar 21 03:09:39 PM PDT 24 Mar 21 03:09:40 PM PDT 24 46419254 ps
T99 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.3241970657 Mar 21 03:09:38 PM PDT 24 Mar 21 03:09:41 PM PDT 24 313135199 ps
T100 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.3203353753 Mar 21 03:10:19 PM PDT 24 Mar 21 03:10:58 PM PDT 24 15139296218 ps
T101 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.2182665288 Mar 21 03:10:11 PM PDT 24 Mar 21 03:10:20 PM PDT 24 411293475 ps
T279 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2275740554 Mar 21 03:10:50 PM PDT 24 Mar 21 03:10:51 PM PDT 24 408533341 ps
T280 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.3769806273 Mar 21 03:09:38 PM PDT 24 Mar 21 03:10:16 PM PDT 24 6471977013 ps
T281 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.1633940977 Mar 21 03:09:39 PM PDT 24 Mar 21 03:09:39 PM PDT 24 54258067 ps
T282 /workspace/coverage/cover_reg_top/17.rv_dm_tap_fsm_rand_reset.2349643869 Mar 21 03:10:47 PM PDT 24 Mar 21 03:10:59 PM PDT 24 14161772875 ps
T283 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.2130537709 Mar 21 03:10:21 PM PDT 24 Mar 21 03:10:22 PM PDT 24 446601140 ps
T126 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.1401557851 Mar 21 03:10:18 PM PDT 24 Mar 21 03:10:24 PM PDT 24 328328242 ps
T284 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.139441630 Mar 21 03:09:56 PM PDT 24 Mar 21 03:09:57 PM PDT 24 69573896 ps
T285 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.4072166901 Mar 21 03:10:48 PM PDT 24 Mar 21 03:10:49 PM PDT 24 40178217 ps
T286 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.4006922671 Mar 21 03:10:12 PM PDT 24 Mar 21 03:10:13 PM PDT 24 50984647 ps
T287 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.4077070060 Mar 21 03:10:07 PM PDT 24 Mar 21 03:10:37 PM PDT 24 29568233388 ps
T102 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.2316295400 Mar 21 03:10:34 PM PDT 24 Mar 21 03:10:43 PM PDT 24 166055291 ps
T288 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.2411579852 Mar 21 03:10:26 PM PDT 24 Mar 21 03:10:28 PM PDT 24 436989584 ps
T289 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.126979965 Mar 21 03:10:46 PM PDT 24 Mar 21 03:10:51 PM PDT 24 1634724267 ps
T290 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1984670597 Mar 21 03:09:39 PM PDT 24 Mar 21 03:09:44 PM PDT 24 1909145172 ps
T291 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.80044394 Mar 21 03:09:57 PM PDT 24 Mar 21 03:10:07 PM PDT 24 2021651327 ps
T292 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.1172385876 Mar 21 03:10:46 PM PDT 24 Mar 21 03:10:53 PM PDT 24 5159658583 ps
T293 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.3761594534 Mar 21 03:09:56 PM PDT 24 Mar 21 03:09:57 PM PDT 24 18872926 ps
T294 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3148527048 Mar 21 03:10:11 PM PDT 24 Mar 21 03:10:13 PM PDT 24 71014713 ps
T295 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.2746408796 Mar 21 03:10:26 PM PDT 24 Mar 21 03:10:30 PM PDT 24 530234974 ps
T103 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.888480641 Mar 21 03:09:56 PM PDT 24 Mar 21 03:09:58 PM PDT 24 77006498 ps
T296 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.940878024 Mar 21 03:09:25 PM PDT 24 Mar 21 03:09:32 PM PDT 24 276424675 ps
T297 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3193378707 Mar 21 03:10:19 PM PDT 24 Mar 21 03:10:24 PM PDT 24 215186594 ps
T298 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.3658925018 Mar 21 03:10:08 PM PDT 24 Mar 21 03:10:09 PM PDT 24 39055686 ps
T104 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.1378607196 Mar 21 03:09:39 PM PDT 24 Mar 21 03:09:40 PM PDT 24 68948222 ps
T299 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.4089904211 Mar 21 03:09:26 PM PDT 24 Mar 21 03:09:27 PM PDT 24 370821337 ps
T300 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1166352940 Mar 21 03:10:07 PM PDT 24 Mar 21 03:10:35 PM PDT 24 715674995 ps
T301 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.2725160950 Mar 21 03:10:16 PM PDT 24 Mar 21 03:10:21 PM PDT 24 80231676 ps
T105 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.415591093 Mar 21 03:10:35 PM PDT 24 Mar 21 03:10:40 PM PDT 24 894162368 ps
T302 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2876819984 Mar 21 03:10:08 PM PDT 24 Mar 21 03:10:42 PM PDT 24 34246861107 ps
T106 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.4247208833 Mar 21 03:10:48 PM PDT 24 Mar 21 03:10:50 PM PDT 24 61718591 ps
T303 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1704515422 Mar 21 03:09:39 PM PDT 24 Mar 21 03:10:25 PM PDT 24 12738437821 ps
T304 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.2313181301 Mar 21 03:10:47 PM PDT 24 Mar 21 03:11:03 PM PDT 24 409499796 ps
T305 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.945777002 Mar 21 03:09:58 PM PDT 24 Mar 21 03:09:59 PM PDT 24 316898699 ps
T108 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2878069505 Mar 21 03:10:48 PM PDT 24 Mar 21 03:10:50 PM PDT 24 57006829 ps
T90 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.3225159425 Mar 21 03:09:40 PM PDT 24 Mar 21 03:09:42 PM PDT 24 1510805604 ps
T127 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.1986456886 Mar 21 03:10:06 PM PDT 24 Mar 21 03:10:12 PM PDT 24 664525985 ps
T306 /workspace/coverage/cover_reg_top/25.rv_dm_tap_fsm_rand_reset.2116970945 Mar 21 03:10:58 PM PDT 24 Mar 21 03:11:21 PM PDT 24 6219417747 ps
T91 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.1013793547 Mar 21 03:10:07 PM PDT 24 Mar 21 03:10:09 PM PDT 24 1130121994 ps
T307 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.338938194 Mar 21 03:09:56 PM PDT 24 Mar 21 03:10:01 PM PDT 24 136343800 ps
T308 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.4275309800 Mar 21 03:09:26 PM PDT 24 Mar 21 03:09:27 PM PDT 24 16548697 ps
T309 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.1685594562 Mar 21 03:10:17 PM PDT 24 Mar 21 03:10:19 PM PDT 24 65291601 ps
T310 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.40560458 Mar 21 03:10:34 PM PDT 24 Mar 21 03:10:38 PM PDT 24 188472809 ps
T311 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3426448458 Mar 21 03:10:48 PM PDT 24 Mar 21 03:10:52 PM PDT 24 65028910 ps
T312 /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.1771629769 Mar 21 03:09:27 PM PDT 24 Mar 21 03:09:46 PM PDT 24 5889184738 ps
T313 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.1561695065 Mar 21 03:10:48 PM PDT 24 Mar 21 03:10:56 PM PDT 24 407534623 ps
T314 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3712598555 Mar 21 03:09:38 PM PDT 24 Mar 21 03:09:42 PM PDT 24 129078858 ps
T315 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.368772891 Mar 21 03:10:46 PM PDT 24 Mar 21 03:10:50 PM PDT 24 808745212 ps
T92 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.1368074120 Mar 21 03:09:27 PM PDT 24 Mar 21 03:09:30 PM PDT 24 471498420 ps
T316 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.3183453981 Mar 21 03:10:06 PM PDT 24 Mar 21 03:10:12 PM PDT 24 3090947759 ps
T317 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.3445870736 Mar 21 03:10:09 PM PDT 24 Mar 21 03:10:11 PM PDT 24 98089362 ps
T318 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2243393271 Mar 21 03:10:18 PM PDT 24 Mar 21 03:10:23 PM PDT 24 2738357655 ps
T319 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2545792664 Mar 21 03:09:56 PM PDT 24 Mar 21 03:09:57 PM PDT 24 19200141 ps
T320 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2547632166 Mar 21 03:10:34 PM PDT 24 Mar 21 03:10:42 PM PDT 24 1307371239 ps
T321 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2511358263 Mar 21 03:10:16 PM PDT 24 Mar 21 03:10:26 PM PDT 24 3392525625 ps
T322 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.3348369467 Mar 21 03:10:47 PM PDT 24 Mar 21 03:10:55 PM PDT 24 3388166680 ps
T323 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.713820744 Mar 21 03:10:50 PM PDT 24 Mar 21 03:10:57 PM PDT 24 168003839 ps
T324 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.2360959669 Mar 21 03:09:27 PM PDT 24 Mar 21 03:09:28 PM PDT 24 77015117 ps
T107 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.3960591821 Mar 21 03:10:13 PM PDT 24 Mar 21 03:11:20 PM PDT 24 22008866079 ps
T325 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2636229069 Mar 21 03:10:26 PM PDT 24 Mar 21 03:10:35 PM PDT 24 2728763427 ps
T326 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.324831771 Mar 21 03:10:17 PM PDT 24 Mar 21 03:10:21 PM PDT 24 61669289 ps
T327 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.4097549349 Mar 21 03:09:56 PM PDT 24 Mar 21 03:11:07 PM PDT 24 19347609223 ps
T328 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.1519923453 Mar 21 03:10:34 PM PDT 24 Mar 21 03:10:40 PM PDT 24 73579010 ps
T329 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.4001948497 Mar 21 03:10:46 PM PDT 24 Mar 21 03:10:50 PM PDT 24 287864594 ps
T330 /workspace/coverage/cover_reg_top/19.rv_dm_tap_fsm_rand_reset.3290029279 Mar 21 03:10:49 PM PDT 24 Mar 21 03:11:22 PM PDT 24 11345005195 ps
T109 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.843738602 Mar 21 03:10:33 PM PDT 24 Mar 21 03:10:38 PM PDT 24 490936668 ps
T331 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.4292176099 Mar 21 03:10:33 PM PDT 24 Mar 21 03:10:40 PM PDT 24 432434463 ps
T332 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3691635600 Mar 21 03:10:16 PM PDT 24 Mar 21 03:10:17 PM PDT 24 90326327 ps
T333 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.1750409214 Mar 21 03:10:14 PM PDT 24 Mar 21 03:10:19 PM PDT 24 714430565 ps
T334 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1834335894 Mar 21 03:09:56 PM PDT 24 Mar 21 03:10:01 PM PDT 24 3978145762 ps
T335 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.1294273963 Mar 21 03:10:33 PM PDT 24 Mar 21 03:10:40 PM PDT 24 2568391847 ps
T336 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.875327905 Mar 21 03:09:41 PM PDT 24 Mar 21 03:09:43 PM PDT 24 65677852 ps
T134 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2178459262 Mar 21 03:10:25 PM PDT 24 Mar 21 03:10:43 PM PDT 24 1065943213 ps
T337 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.2900203310 Mar 21 03:10:34 PM PDT 24 Mar 21 03:10:41 PM PDT 24 937498021 ps
T338 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1858415667 Mar 21 03:09:30 PM PDT 24 Mar 21 03:09:40 PM PDT 24 2907595949 ps
T110 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.3775625453 Mar 21 03:10:33 PM PDT 24 Mar 21 03:10:36 PM PDT 24 155526150 ps
T339 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.1487881844 Mar 21 03:10:51 PM PDT 24 Mar 21 03:10:57 PM PDT 24 549388420 ps
T340 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.803972246 Mar 21 03:10:21 PM PDT 24 Mar 21 03:10:24 PM PDT 24 1426135676 ps
T341 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3926823537 Mar 21 03:09:26 PM PDT 24 Mar 21 03:09:27 PM PDT 24 310277749 ps
T342 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1207349539 Mar 21 03:10:06 PM PDT 24 Mar 21 03:10:07 PM PDT 24 31805652 ps
T343 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.4243286825 Mar 21 03:10:15 PM PDT 24 Mar 21 03:10:17 PM PDT 24 48180161 ps
T344 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2370358503 Mar 21 03:10:50 PM PDT 24 Mar 21 03:10:51 PM PDT 24 67829963 ps
T345 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.3483541277 Mar 21 03:10:17 PM PDT 24 Mar 21 03:10:19 PM PDT 24 144966031 ps
T346 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1037062213 Mar 21 03:10:35 PM PDT 24 Mar 21 03:10:38 PM PDT 24 50058477 ps
T347 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3323911711 Mar 21 03:09:26 PM PDT 24 Mar 21 03:09:29 PM PDT 24 110000598 ps
T348 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.14508010 Mar 21 03:10:06 PM PDT 24 Mar 21 03:10:08 PM PDT 24 311841216 ps
T349 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1118404952 Mar 21 03:10:34 PM PDT 24 Mar 21 03:10:37 PM PDT 24 97643878 ps
T350 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.870265562 Mar 21 03:10:47 PM PDT 24 Mar 21 03:10:48 PM PDT 24 54310263 ps
T351 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.1027723944 Mar 21 03:10:48 PM PDT 24 Mar 21 03:10:50 PM PDT 24 58128410 ps
T352 /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.890047636 Mar 21 03:10:06 PM PDT 24 Mar 21 03:10:28 PM PDT 24 7383259193 ps
T353 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.1512667440 Mar 21 03:10:50 PM PDT 24 Mar 21 03:10:52 PM PDT 24 383171041 ps
T354 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.4264357440 Mar 21 03:10:34 PM PDT 24 Mar 21 03:10:44 PM PDT 24 3414127237 ps
T355 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3436514866 Mar 21 03:10:17 PM PDT 24 Mar 21 03:10:18 PM PDT 24 461545511 ps
T356 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.139886254 Mar 21 03:10:08 PM PDT 24 Mar 21 03:10:09 PM PDT 24 15127729 ps
T357 /workspace/coverage/cover_reg_top/36.rv_dm_tap_fsm_rand_reset.586042066 Mar 21 03:10:59 PM PDT 24 Mar 21 03:11:16 PM PDT 24 9334498492 ps
T358 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1452000623 Mar 21 03:09:27 PM PDT 24 Mar 21 03:09:42 PM PDT 24 4845039858 ps
T359 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1777067891 Mar 21 03:09:39 PM PDT 24 Mar 21 03:09:40 PM PDT 24 49100716 ps
T360 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.1119187463 Mar 21 03:10:36 PM PDT 24 Mar 21 03:10:38 PM PDT 24 204261129 ps
T130 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2112518934 Mar 21 03:10:25 PM PDT 24 Mar 21 03:10:46 PM PDT 24 1908416218 ps
T137 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.1999104622 Mar 21 03:09:27 PM PDT 24 Mar 21 03:09:47 PM PDT 24 8885921742 ps
T361 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.2194862871 Mar 21 03:10:48 PM PDT 24 Mar 21 03:10:57 PM PDT 24 414233969 ps
T362 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.950073472 Mar 21 03:10:46 PM PDT 24 Mar 21 03:10:47 PM PDT 24 63688356 ps
T363 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.1345579118 Mar 21 03:10:46 PM PDT 24 Mar 21 03:10:49 PM PDT 24 635860762 ps
T364 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.1322932094 Mar 21 03:10:46 PM PDT 24 Mar 21 03:10:47 PM PDT 24 109418843 ps
T365 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.1472667032 Mar 21 03:10:43 PM PDT 24 Mar 21 03:10:47 PM PDT 24 1345724004 ps
T366 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1676086024 Mar 21 03:10:07 PM PDT 24 Mar 21 03:12:49 PM PDT 24 48968261933 ps
T367 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.1777453 Mar 21 03:10:48 PM PDT 24 Mar 21 03:10:51 PM PDT 24 248001545 ps
T368 /workspace/coverage/cover_reg_top/12.rv_dm_tap_fsm_rand_reset.3062585999 Mar 21 03:10:35 PM PDT 24 Mar 21 03:10:55 PM PDT 24 7678665132 ps
T369 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.4070756486 Mar 21 03:10:07 PM PDT 24 Mar 21 03:10:12 PM PDT 24 1306231911 ps
T138 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.393140471 Mar 21 03:10:50 PM PDT 24 Mar 21 03:10:59 PM PDT 24 367911118 ps
T370 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3688955872 Mar 21 03:10:09 PM PDT 24 Mar 21 03:10:13 PM PDT 24 905126777 ps
T371 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.1570078105 Mar 21 03:10:48 PM PDT 24 Mar 21 03:10:54 PM PDT 24 3026439920 ps
T372 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2358678218 Mar 21 03:09:57 PM PDT 24 Mar 21 03:09:58 PM PDT 24 44496819 ps
T373 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2641679007 Mar 21 03:10:07 PM PDT 24 Mar 21 03:10:40 PM PDT 24 6900559459 ps
T374 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2035753969 Mar 21 03:10:51 PM PDT 24 Mar 21 03:11:07 PM PDT 24 802943384 ps
T375 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.11990618 Mar 21 03:09:57 PM PDT 24 Mar 21 03:10:23 PM PDT 24 1503134290 ps
T376 /workspace/coverage/cover_reg_top/32.rv_dm_tap_fsm_rand_reset.1286845091 Mar 21 03:11:06 PM PDT 24 Mar 21 03:11:15 PM PDT 24 18355311776 ps
T377 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1472458843 Mar 21 03:10:33 PM PDT 24 Mar 21 03:10:38 PM PDT 24 714863034 ps
T378 /workspace/coverage/cover_reg_top/23.rv_dm_tap_fsm_rand_reset.522091681 Mar 21 03:11:11 PM PDT 24 Mar 21 03:11:34 PM PDT 24 9761426772 ps
T379 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.2406305139 Mar 21 03:09:56 PM PDT 24 Mar 21 03:10:29 PM PDT 24 17001565970 ps
T380 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.2620772728 Mar 21 03:10:35 PM PDT 24 Mar 21 03:10:37 PM PDT 24 69840717 ps
T381 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.3290329560 Mar 21 03:10:50 PM PDT 24 Mar 21 03:10:53 PM PDT 24 141912166 ps

Test location /workspace/coverage/default/28.rv_dm_stress_all.2634233507
Short name T4
Test name
Test status
Simulation time 3191292221 ps
CPU time 11.18 seconds
Started Mar 21 01:32:58 PM PDT 24
Finished Mar 21 01:33:10 PM PDT 24
Peak memory 205092 kb
Host smart-64cb5b88-75fe-4c8d-919c-c475fdcc310d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634233507 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.2634233507
Directory /workspace/28.rv_dm_stress_all/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.3751766774
Short name T12
Test name
Test status
Simulation time 4611094836 ps
CPU time 6.43 seconds
Started Mar 21 01:32:44 PM PDT 24
Finished Mar 21 01:32:50 PM PDT 24
Peak memory 213456 kb
Host smart-c7fce92e-87b8-4005-b47b-d54af6439004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751766774 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.3751766774
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3310260955
Short name T31
Test name
Test status
Simulation time 653138705 ps
CPU time 10.41 seconds
Started Mar 21 03:10:05 PM PDT 24
Finished Mar 21 03:10:16 PM PDT 24
Peak memory 212952 kb
Host smart-3066588e-75a2-4c67-9e65-442b66766ad6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310260955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.3310260955
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/31.rv_dm_tap_fsm_rand_reset.1183995627
Short name T139
Test name
Test status
Simulation time 5579849919 ps
CPU time 19.53 seconds
Started Mar 21 03:10:59 PM PDT 24
Finished Mar 21 03:11:19 PM PDT 24
Peak memory 218176 kb
Host smart-045bdeca-8486-42bd-a99c-786dd3437976
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183995627 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 31.rv_dm_tap_fsm_rand_reset.1183995627
Directory /workspace/31.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.325159953
Short name T25
Test name
Test status
Simulation time 204146231 ps
CPU time 0.7 seconds
Started Mar 21 01:32:32 PM PDT 24
Finished Mar 21 01:32:33 PM PDT 24
Peak memory 204872 kb
Host smart-2649b32c-aaf6-427a-b5bf-17173b18e821
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325159953 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.325159953
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_stress_all.13454525
Short name T17
Test name
Test status
Simulation time 7692841330 ps
CPU time 9.23 seconds
Started Mar 21 01:32:31 PM PDT 24
Finished Mar 21 01:32:40 PM PDT 24
Peak memory 213304 kb
Host smart-8b310f0d-9f7d-4be6-8001-b73de40cc62a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13454525 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.13454525
Directory /workspace/8.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3640038554
Short name T71
Test name
Test status
Simulation time 202919634 ps
CPU time 2.89 seconds
Started Mar 21 03:10:51 PM PDT 24
Finished Mar 21 03:10:54 PM PDT 24
Peak memory 212972 kb
Host smart-2c566ffa-0e6e-4ba3-94d2-b9b3c5f65383
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640038554 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.3640038554
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all.3452961028
Short name T28
Test name
Test status
Simulation time 1191824696 ps
CPU time 5.06 seconds
Started Mar 21 01:32:24 PM PDT 24
Finished Mar 21 01:32:30 PM PDT 24
Peak memory 205016 kb
Host smart-6a4c77e7-d1e6-412f-8b06-8070101df65b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452961028 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.3452961028
Directory /workspace/1.rv_dm_stress_all/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.3274052013
Short name T221
Test name
Test status
Simulation time 8543045349 ps
CPU time 19.01 seconds
Started Mar 21 01:32:24 PM PDT 24
Finished Mar 21 01:32:44 PM PDT 24
Peak memory 215656 kb
Host smart-9e73c1ea-e8ff-49e2-ade7-8f252d37e688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274052013 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.3274052013
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.3561590521
Short name T125
Test name
Test status
Simulation time 348916945 ps
CPU time 3.38 seconds
Started Mar 21 03:10:33 PM PDT 24
Finished Mar 21 03:10:39 PM PDT 24
Peak memory 213020 kb
Host smart-e18ca855-c114-4205-9174-6aa632dec4f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561590521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.3561590521
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/14.rv_dm_stress_all.3034849664
Short name T5
Test name
Test status
Simulation time 2726641969 ps
CPU time 6.9 seconds
Started Mar 21 01:32:37 PM PDT 24
Finished Mar 21 01:32:44 PM PDT 24
Peak memory 205180 kb
Host smart-e67986a8-28f1-41ec-93ce-40a5b7ef91d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034849664 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.3034849664
Directory /workspace/14.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.3388576428
Short name T97
Test name
Test status
Simulation time 48973090 ps
CPU time 2.09 seconds
Started Mar 21 03:10:18 PM PDT 24
Finished Mar 21 03:10:20 PM PDT 24
Peak memory 218296 kb
Host smart-2d47df0a-d782-48bb-bdac-792d63262efd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388576428 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.3388576428
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1683477287
Short name T133
Test name
Test status
Simulation time 1699044252 ps
CPU time 19.55 seconds
Started Mar 21 03:10:08 PM PDT 24
Finished Mar 21 03:10:28 PM PDT 24
Peak memory 212972 kb
Host smart-9dff9e37-ec7a-44e6-a3ad-b09b11793dde
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683477287 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.1683477287
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.3138643997
Short name T42
Test name
Test status
Simulation time 224931578 ps
CPU time 1.05 seconds
Started Mar 21 01:32:16 PM PDT 24
Finished Mar 21 01:32:17 PM PDT 24
Peak memory 228404 kb
Host smart-814bfc1d-6c0b-4466-93c9-b966895326ff
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138643997 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.3138643997
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.137771505
Short name T53
Test name
Test status
Simulation time 121800535 ps
CPU time 0.82 seconds
Started Mar 21 01:32:15 PM PDT 24
Finished Mar 21 01:32:16 PM PDT 24
Peak memory 213104 kb
Host smart-a182de09-a858-40ac-9991-c513d63d3d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137771505 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.137771505
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1227533745
Short name T81
Test name
Test status
Simulation time 574074233 ps
CPU time 4.51 seconds
Started Mar 21 03:10:46 PM PDT 24
Finished Mar 21 03:10:51 PM PDT 24
Peak memory 204744 kb
Host smart-7a751d61-bd1e-4798-aa24-cea2d11ead6b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227533745 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.1227533745
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.4219265697
Short name T57
Test name
Test status
Simulation time 720206413 ps
CPU time 1.29 seconds
Started Mar 21 01:32:14 PM PDT 24
Finished Mar 21 01:32:16 PM PDT 24
Peak memory 204864 kb
Host smart-807af220-df4e-476b-86bb-55a17a2fbd65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219265697 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.4219265697
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.2964728995
Short name T122
Test name
Test status
Simulation time 2930712532 ps
CPU time 14.54 seconds
Started Mar 21 01:32:32 PM PDT 24
Finished Mar 21 01:32:46 PM PDT 24
Peak memory 214888 kb
Host smart-2fa12fe9-b55c-4e57-abc3-71466013c417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964728995 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.2964728995
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.3241056115
Short name T2
Test name
Test status
Simulation time 22564663 ps
CPU time 0.74 seconds
Started Mar 21 01:32:18 PM PDT 24
Finished Mar 21 01:32:19 PM PDT 24
Peak memory 204844 kb
Host smart-f4ff66be-3b6d-4a73-bda3-53f1e471e84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241056115 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.3241056115
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.2003241423
Short name T46
Test name
Test status
Simulation time 88838672 ps
CPU time 0.99 seconds
Started Mar 21 01:32:15 PM PDT 24
Finished Mar 21 01:32:16 PM PDT 24
Peak memory 204736 kb
Host smart-624f6b13-365e-49b6-8153-eaee6e8fded9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003241423 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.2003241423
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.3910938998
Short name T152
Test name
Test status
Simulation time 49694996 ps
CPU time 0.74 seconds
Started Mar 21 01:32:48 PM PDT 24
Finished Mar 21 01:32:48 PM PDT 24
Peak memory 204872 kb
Host smart-3dc1cbf4-feff-41c8-b1d6-454e21604d2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910938998 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.3910938998
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2854209648
Short name T129
Test name
Test status
Simulation time 3235465811 ps
CPU time 19.29 seconds
Started Mar 21 03:10:36 PM PDT 24
Finished Mar 21 03:10:57 PM PDT 24
Peak memory 219364 kb
Host smart-f18c310b-c309-456b-a543-b60948b2e6f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854209648 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.2
854209648
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.1243676315
Short name T250
Test name
Test status
Simulation time 936474087 ps
CPU time 1.43 seconds
Started Mar 21 03:09:39 PM PDT 24
Finished Mar 21 03:09:41 PM PDT 24
Peak memory 204688 kb
Host smart-fd307d3e-88d8-4d24-9fd0-7f320215a657
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243676315 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.1243676315
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.1368074120
Short name T92
Test name
Test status
Simulation time 471498420 ps
CPU time 2.39 seconds
Started Mar 21 03:09:27 PM PDT 24
Finished Mar 21 03:09:30 PM PDT 24
Peak memory 204768 kb
Host smart-d3243a6a-13dc-4d65-941a-6288a76e5bf2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368074120 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.1368074120
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.893072430
Short name T113
Test name
Test status
Simulation time 13919280377 ps
CPU time 78.27 seconds
Started Mar 21 03:09:26 PM PDT 24
Finished Mar 21 03:10:45 PM PDT 24
Peak memory 213024 kb
Host smart-ee71b931-6279-4bd3-8c06-63eb8be6b404
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893072430 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.rv_dm_csr_aliasing.893072430
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.1704423729
Short name T52
Test name
Test status
Simulation time 250185910 ps
CPU time 1.41 seconds
Started Mar 21 01:32:19 PM PDT 24
Finished Mar 21 01:32:21 PM PDT 24
Peak memory 204704 kb
Host smart-b8177af6-75a8-4a9f-b489-6871c02dbdae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704423729 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.1704423729
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.1379820569
Short name T124
Test name
Test status
Simulation time 39743031143 ps
CPU time 54.05 seconds
Started Mar 21 01:32:41 PM PDT 24
Finished Mar 21 01:33:35 PM PDT 24
Peak memory 213496 kb
Host smart-00498a9a-7684-4610-a57f-e0572b0cccc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379820569 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.1379820569
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.1409292071
Short name T79
Test name
Test status
Simulation time 73854108 ps
CPU time 2.17 seconds
Started Mar 21 03:09:27 PM PDT 24
Finished Mar 21 03:09:29 PM PDT 24
Peak memory 213020 kb
Host smart-03864184-71ad-4d84-9819-91f52782375e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409292071 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.1409292071
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.1999104622
Short name T137
Test name
Test status
Simulation time 8885921742 ps
CPU time 20.05 seconds
Started Mar 21 03:09:27 PM PDT 24
Finished Mar 21 03:09:47 PM PDT 24
Peak memory 213080 kb
Host smart-4444c328-e172-4033-aa44-775e6303117e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999104622 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.1999104622
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.740519544
Short name T118
Test name
Test status
Simulation time 7373046851 ps
CPU time 36.91 seconds
Started Mar 21 03:09:25 PM PDT 24
Finished Mar 21 03:10:02 PM PDT 24
Peak memory 213124 kb
Host smart-e8c45854-b9ea-4a8a-a7c9-42d1cdaacc93
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740519544 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.740519544
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3323911711
Short name T347
Test name
Test status
Simulation time 110000598 ps
CPU time 2.54 seconds
Started Mar 21 03:09:26 PM PDT 24
Finished Mar 21 03:09:29 PM PDT 24
Peak memory 212964 kb
Host smart-2853ce80-43bd-40ee-b21b-856046503e07
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323911711 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.3323911711
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1984670597
Short name T290
Test name
Test status
Simulation time 1909145172 ps
CPU time 4.99 seconds
Started Mar 21 03:09:39 PM PDT 24
Finished Mar 21 03:09:44 PM PDT 24
Peak memory 218396 kb
Host smart-74e22ea4-8711-4420-8e6a-e1618b5e184a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984670597 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.1984670597
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.532820155
Short name T258
Test name
Test status
Simulation time 7569956383 ps
CPU time 7.16 seconds
Started Mar 21 03:09:27 PM PDT 24
Finished Mar 21 03:09:34 PM PDT 24
Peak memory 204736 kb
Host smart-4c3a2c97-500f-4d00-8cb1-7818e46a33ed
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532820155 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr
_aliasing.532820155
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1452000623
Short name T358
Test name
Test status
Simulation time 4845039858 ps
CPU time 14.57 seconds
Started Mar 21 03:09:27 PM PDT 24
Finished Mar 21 03:09:42 PM PDT 24
Peak memory 204772 kb
Host smart-43790e77-f02e-4dcb-807b-aa7f90725363
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452000623 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_bit_bash.1452000623
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.388340740
Short name T246
Test name
Test status
Simulation time 839156080 ps
CPU time 3.25 seconds
Started Mar 21 03:09:27 PM PDT 24
Finished Mar 21 03:09:30 PM PDT 24
Peak memory 204672 kb
Host smart-c9ce31b0-0646-442f-bf7e-8f287962e1fb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388340740 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.388340740
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.4089904211
Short name T299
Test name
Test status
Simulation time 370821337 ps
CPU time 1.3 seconds
Started Mar 21 03:09:26 PM PDT 24
Finished Mar 21 03:09:27 PM PDT 24
Peak memory 204468 kb
Host smart-d2b13d10-75a0-4a86-acd0-606b51486d45
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089904211 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.4089904211
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1858415667
Short name T338
Test name
Test status
Simulation time 2907595949 ps
CPU time 9.51 seconds
Started Mar 21 03:09:30 PM PDT 24
Finished Mar 21 03:09:40 PM PDT 24
Peak memory 204808 kb
Host smart-63946bd0-df45-41b6-ab92-df8d9f2bc922
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858415667 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.1858415667
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3926823537
Short name T341
Test name
Test status
Simulation time 310277749 ps
CPU time 0.73 seconds
Started Mar 21 03:09:26 PM PDT 24
Finished Mar 21 03:09:27 PM PDT 24
Peak memory 204540 kb
Host smart-b347cd64-f342-4b2b-8bdf-449ab1e868c1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926823537 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.3926823537
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.2360959669
Short name T324
Test name
Test status
Simulation time 77015117 ps
CPU time 0.69 seconds
Started Mar 21 03:09:27 PM PDT 24
Finished Mar 21 03:09:28 PM PDT 24
Peak memory 204408 kb
Host smart-b0aa7bda-377b-4ca9-9bf5-7fed03fd499b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360959669 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.2
360959669
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.4275309800
Short name T308
Test name
Test status
Simulation time 16548697 ps
CPU time 0.7 seconds
Started Mar 21 03:09:26 PM PDT 24
Finished Mar 21 03:09:27 PM PDT 24
Peak memory 204472 kb
Host smart-bd52a63c-6613-44b2-905c-ad92cd7cc3e6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275309800 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.4275309800
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.3419932394
Short name T253
Test name
Test status
Simulation time 46844989 ps
CPU time 0.71 seconds
Started Mar 21 03:09:27 PM PDT 24
Finished Mar 21 03:09:28 PM PDT 24
Peak memory 204496 kb
Host smart-b568ec6c-d280-484e-9cc1-f5d49a36967a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419932394 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.3419932394
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.940878024
Short name T296
Test name
Test status
Simulation time 276424675 ps
CPU time 6.56 seconds
Started Mar 21 03:09:25 PM PDT 24
Finished Mar 21 03:09:32 PM PDT 24
Peak memory 204776 kb
Host smart-81185955-7c8c-4159-be4d-a09756d4a4f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940878024 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_c
sr_outstanding.940878024
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.1771629769
Short name T312
Test name
Test status
Simulation time 5889184738 ps
CPU time 19.05 seconds
Started Mar 21 03:09:27 PM PDT 24
Finished Mar 21 03:09:46 PM PDT 24
Peak memory 214664 kb
Host smart-79eb1482-92cc-4043-848d-3bd2f44b0316
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771629769 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.1771629769
Directory /workspace/0.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.560439605
Short name T269
Test name
Test status
Simulation time 2039710282 ps
CPU time 5.93 seconds
Started Mar 21 03:09:27 PM PDT 24
Finished Mar 21 03:09:33 PM PDT 24
Peak memory 213012 kb
Host smart-142a8880-7019-4ff0-89a8-0f89e536c2d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560439605 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.560439605
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.478406771
Short name T115
Test name
Test status
Simulation time 2252242904 ps
CPU time 33.44 seconds
Started Mar 21 03:09:40 PM PDT 24
Finished Mar 21 03:10:14 PM PDT 24
Peak memory 204840 kb
Host smart-e4de8b3a-5a5b-4916-8131-493a2003a1a6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478406771 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.rv_dm_csr_aliasing.478406771
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.3769806273
Short name T280
Test name
Test status
Simulation time 6471977013 ps
CPU time 37.95 seconds
Started Mar 21 03:09:38 PM PDT 24
Finished Mar 21 03:10:16 PM PDT 24
Peak memory 204976 kb
Host smart-3096ce5c-745e-43ff-8dad-fe35c1b92e64
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769806273 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.3769806273
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.3241970657
Short name T99
Test name
Test status
Simulation time 313135199 ps
CPU time 2.48 seconds
Started Mar 21 03:09:38 PM PDT 24
Finished Mar 21 03:09:41 PM PDT 24
Peak memory 212924 kb
Host smart-81cd3a06-4d41-4e33-8970-4b1859248d48
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241970657 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.3241970657
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3712598555
Short name T314
Test name
Test status
Simulation time 129078858 ps
CPU time 3.72 seconds
Started Mar 21 03:09:38 PM PDT 24
Finished Mar 21 03:09:42 PM PDT 24
Peak memory 217992 kb
Host smart-2b49ed28-56d4-4344-ba7b-f91ee9745d0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712598555 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.3712598555
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.1378607196
Short name T104
Test name
Test status
Simulation time 68948222 ps
CPU time 1.63 seconds
Started Mar 21 03:09:39 PM PDT 24
Finished Mar 21 03:09:40 PM PDT 24
Peak memory 218012 kb
Host smart-32b0334f-79e8-45be-b622-710a53dffe5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378607196 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.1378607196
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1224757156
Short name T251
Test name
Test status
Simulation time 13390846704 ps
CPU time 20.06 seconds
Started Mar 21 03:09:41 PM PDT 24
Finished Mar 21 03:10:01 PM PDT 24
Peak memory 204744 kb
Host smart-57c296df-0abd-476d-b785-316999f3754e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224757156 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.1224757156
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1704515422
Short name T303
Test name
Test status
Simulation time 12738437821 ps
CPU time 46.54 seconds
Started Mar 21 03:09:39 PM PDT 24
Finished Mar 21 03:10:25 PM PDT 24
Peak memory 204816 kb
Host smart-05538777-2fe7-4276-834c-c11d29b4e61f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704515422 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_bit_bash.1704515422
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.3225159425
Short name T90
Test name
Test status
Simulation time 1510805604 ps
CPU time 2.32 seconds
Started Mar 21 03:09:40 PM PDT 24
Finished Mar 21 03:09:42 PM PDT 24
Peak memory 204796 kb
Host smart-452c22a8-22e3-4f2f-ab2a-7d2722ae7135
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225159425 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.3225159425
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2675057224
Short name T277
Test name
Test status
Simulation time 575447296 ps
CPU time 1.63 seconds
Started Mar 21 03:09:40 PM PDT 24
Finished Mar 21 03:09:41 PM PDT 24
Peak memory 204688 kb
Host smart-a084c3bf-c739-48a6-a29d-c8863dd9f95f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675057224 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.2
675057224
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2800115946
Short name T278
Test name
Test status
Simulation time 46419254 ps
CPU time 0.81 seconds
Started Mar 21 03:09:39 PM PDT 24
Finished Mar 21 03:09:40 PM PDT 24
Peak memory 204488 kb
Host smart-dee8f1ee-9def-4613-b6d7-7e0e2334fe57
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800115946 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.2800115946
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1649736477
Short name T259
Test name
Test status
Simulation time 62591755 ps
CPU time 0.71 seconds
Started Mar 21 03:09:39 PM PDT 24
Finished Mar 21 03:09:40 PM PDT 24
Peak memory 204496 kb
Host smart-da8ded2b-6869-4e28-bc5d-0f848f8bbdb7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649736477 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.1649736477
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.4054260594
Short name T248
Test name
Test status
Simulation time 155574475 ps
CPU time 0.82 seconds
Started Mar 21 03:09:40 PM PDT 24
Finished Mar 21 03:09:41 PM PDT 24
Peak memory 204468 kb
Host smart-c9177e90-b972-413e-9470-13c6519bac3d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054260594 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.4
054260594
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1777067891
Short name T359
Test name
Test status
Simulation time 49100716 ps
CPU time 0.69 seconds
Started Mar 21 03:09:39 PM PDT 24
Finished Mar 21 03:09:40 PM PDT 24
Peak memory 204552 kb
Host smart-154574f3-9646-4b80-b2b6-56362e5ae342
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777067891 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.1777067891
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.1633940977
Short name T281
Test name
Test status
Simulation time 54258067 ps
CPU time 0.7 seconds
Started Mar 21 03:09:39 PM PDT 24
Finished Mar 21 03:09:39 PM PDT 24
Peak memory 204484 kb
Host smart-5bb864e6-8233-4203-93d1-ce6367dbfa13
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633940977 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.1633940977
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.1975322912
Short name T98
Test name
Test status
Simulation time 522084471 ps
CPU time 8.15 seconds
Started Mar 21 03:09:38 PM PDT 24
Finished Mar 21 03:09:47 PM PDT 24
Peak memory 204704 kb
Host smart-247ab708-5c9a-4eee-82a9-8e0b94c33174
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975322912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_
csr_outstanding.1975322912
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.875327905
Short name T336
Test name
Test status
Simulation time 65677852 ps
CPU time 2.07 seconds
Started Mar 21 03:09:41 PM PDT 24
Finished Mar 21 03:09:43 PM PDT 24
Peak memory 212940 kb
Host smart-8ab3907f-426f-4472-970f-97530cb6dbf7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875327905 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.875327905
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.702882142
Short name T128
Test name
Test status
Simulation time 3416371655 ps
CPU time 20.91 seconds
Started Mar 21 03:09:39 PM PDT 24
Finished Mar 21 03:10:00 PM PDT 24
Peak memory 213056 kb
Host smart-0ec6c2c6-161b-46cc-9739-75cfe1cc6db4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702882142 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.702882142
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.4264357440
Short name T354
Test name
Test status
Simulation time 3414127237 ps
CPU time 7.3 seconds
Started Mar 21 03:10:34 PM PDT 24
Finished Mar 21 03:10:44 PM PDT 24
Peak memory 215436 kb
Host smart-1c0f3c39-cd02-4535-aff9-59ba047b3f9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264357440 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.4264357440
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.415591093
Short name T105
Test name
Test status
Simulation time 894162368 ps
CPU time 2.57 seconds
Started Mar 21 03:10:35 PM PDT 24
Finished Mar 21 03:10:40 PM PDT 24
Peak memory 218640 kb
Host smart-c34a671d-20ef-41c8-a271-17b854328466
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415591093 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.415591093
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.1119187463
Short name T360
Test name
Test status
Simulation time 204261129 ps
CPU time 0.95 seconds
Started Mar 21 03:10:36 PM PDT 24
Finished Mar 21 03:10:38 PM PDT 24
Peak memory 204696 kb
Host smart-0da405d2-98ae-4f6b-9847-b6b88d1c746a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119187463 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
1119187463
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1118404952
Short name T349
Test name
Test status
Simulation time 97643878 ps
CPU time 0.71 seconds
Started Mar 21 03:10:34 PM PDT 24
Finished Mar 21 03:10:37 PM PDT 24
Peak memory 204484 kb
Host smart-d368e4c4-a3db-4a57-91b8-f13a2cc9f93b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118404952 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
1118404952
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.2900203310
Short name T337
Test name
Test status
Simulation time 937498021 ps
CPU time 4.33 seconds
Started Mar 21 03:10:34 PM PDT 24
Finished Mar 21 03:10:41 PM PDT 24
Peak memory 204772 kb
Host smart-a70a5c7d-5a06-4cad-88d0-84549f76fbb3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900203310 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.2900203310
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.4109661435
Short name T35
Test name
Test status
Simulation time 352671341 ps
CPU time 2.84 seconds
Started Mar 21 03:10:35 PM PDT 24
Finished Mar 21 03:10:40 PM PDT 24
Peak memory 212968 kb
Host smart-a3b9ba06-757b-4080-8b98-2b023919e57f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109661435 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.4109661435
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.4292176099
Short name T331
Test name
Test status
Simulation time 432434463 ps
CPU time 4.29 seconds
Started Mar 21 03:10:33 PM PDT 24
Finished Mar 21 03:10:40 PM PDT 24
Peak memory 221080 kb
Host smart-c4a2e203-33d1-44cd-bf5a-305ea600892f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292176099 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.4292176099
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.1791197138
Short name T36
Test name
Test status
Simulation time 50823369 ps
CPU time 1.59 seconds
Started Mar 21 03:10:36 PM PDT 24
Finished Mar 21 03:10:39 PM PDT 24
Peak memory 212904 kb
Host smart-b4ef3f9c-c1bb-4c7d-8003-51bd0d1e0409
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791197138 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.1791197138
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.1472667032
Short name T365
Test name
Test status
Simulation time 1345724004 ps
CPU time 4.73 seconds
Started Mar 21 03:10:43 PM PDT 24
Finished Mar 21 03:10:47 PM PDT 24
Peak memory 204692 kb
Host smart-cbac61dc-36f0-4e16-86b7-bf854ca04bf3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472667032 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
1472667032
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.2620772728
Short name T380
Test name
Test status
Simulation time 69840717 ps
CPU time 0.89 seconds
Started Mar 21 03:10:35 PM PDT 24
Finished Mar 21 03:10:37 PM PDT 24
Peak memory 204416 kb
Host smart-609580e4-3de8-4b6d-844c-aaac05f63bc5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620772728 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.
2620772728
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.3410167319
Short name T112
Test name
Test status
Simulation time 291802557 ps
CPU time 3.71 seconds
Started Mar 21 03:10:36 PM PDT 24
Finished Mar 21 03:10:41 PM PDT 24
Peak memory 204720 kb
Host smart-f2db9da1-39ad-4854-b9cc-41e5093c8dee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410167319 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same
_csr_outstanding.3410167319
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tap_fsm_rand_reset.1464701283
Short name T140
Test name
Test status
Simulation time 14571014688 ps
CPU time 13.13 seconds
Started Mar 21 03:10:33 PM PDT 24
Finished Mar 21 03:10:48 PM PDT 24
Peak memory 221172 kb
Host smart-065b8dd3-e9d8-47aa-8cfb-f73d2b6ea51f
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464701283 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rv_dm_tap_fsm_rand_reset.1464701283
Directory /workspace/11.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.1290875013
Short name T131
Test name
Test status
Simulation time 728125487 ps
CPU time 8.54 seconds
Started Mar 21 03:10:35 PM PDT 24
Finished Mar 21 03:10:45 PM PDT 24
Peak memory 212976 kb
Host smart-7500db17-df89-4d46-bec5-4cde1ca6d142
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290875013 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.1
290875013
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1472458843
Short name T377
Test name
Test status
Simulation time 714863034 ps
CPU time 2.99 seconds
Started Mar 21 03:10:33 PM PDT 24
Finished Mar 21 03:10:38 PM PDT 24
Peak memory 217000 kb
Host smart-0d1c48a0-0fdc-4a36-9069-79ed74f9b00b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472458843 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.1472458843
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.2161225558
Short name T83
Test name
Test status
Simulation time 181656191 ps
CPU time 1.53 seconds
Started Mar 21 03:10:34 PM PDT 24
Finished Mar 21 03:10:38 PM PDT 24
Peak memory 221108 kb
Host smart-5f0bdb80-9119-49ef-9f15-2764ef7f48af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161225558 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.2161225558
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.4069034576
Short name T247
Test name
Test status
Simulation time 159507623 ps
CPU time 1.06 seconds
Started Mar 21 03:10:36 PM PDT 24
Finished Mar 21 03:10:38 PM PDT 24
Peak memory 204668 kb
Host smart-dcef8388-3fd9-4c87-951c-bd02f00d316c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069034576 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
4069034576
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1037062213
Short name T346
Test name
Test status
Simulation time 50058477 ps
CPU time 0.75 seconds
Started Mar 21 03:10:35 PM PDT 24
Finished Mar 21 03:10:38 PM PDT 24
Peak memory 204472 kb
Host smart-e5cf325d-127c-41a3-a8c2-8437bde26c0e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037062213 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
1037062213
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.2316295400
Short name T102
Test name
Test status
Simulation time 166055291 ps
CPU time 6.75 seconds
Started Mar 21 03:10:34 PM PDT 24
Finished Mar 21 03:10:43 PM PDT 24
Peak memory 204724 kb
Host smart-2d412eeb-9229-4478-8732-31bc9fb27f24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316295400 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.2316295400
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tap_fsm_rand_reset.3062585999
Short name T368
Test name
Test status
Simulation time 7678665132 ps
CPU time 17.79 seconds
Started Mar 21 03:10:35 PM PDT 24
Finished Mar 21 03:10:55 PM PDT 24
Peak memory 214452 kb
Host smart-a892bda8-24d0-4aea-806b-456d250fe85f
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062585999 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rv_dm_tap_fsm_rand_reset.3062585999
Directory /workspace/12.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.4094622342
Short name T264
Test name
Test status
Simulation time 1071659042 ps
CPU time 3.11 seconds
Started Mar 21 03:10:34 PM PDT 24
Finished Mar 21 03:10:39 PM PDT 24
Peak memory 212940 kb
Host smart-abd50c60-fe8c-497b-a999-0fccf199d406
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094622342 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.4094622342
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2466569449
Short name T84
Test name
Test status
Simulation time 1769522728 ps
CPU time 20.53 seconds
Started Mar 21 03:10:33 PM PDT 24
Finished Mar 21 03:10:56 PM PDT 24
Peak memory 221120 kb
Host smart-5ea5d4d5-ddd7-4bd4-ba7c-a9f25078867c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466569449 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.2
466569449
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.1528616606
Short name T271
Test name
Test status
Simulation time 512887570 ps
CPU time 3.73 seconds
Started Mar 21 03:10:51 PM PDT 24
Finished Mar 21 03:10:54 PM PDT 24
Peak memory 217808 kb
Host smart-9b8ef84e-6736-40eb-aeaf-19f6e19c14f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528616606 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.1528616606
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.843738602
Short name T109
Test name
Test status
Simulation time 490936668 ps
CPU time 2.37 seconds
Started Mar 21 03:10:33 PM PDT 24
Finished Mar 21 03:10:38 PM PDT 24
Peak memory 213056 kb
Host smart-5a251a6a-277a-49cc-bebb-35eb05d3eeed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843738602 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.843738602
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.4211373759
Short name T245
Test name
Test status
Simulation time 447887533 ps
CPU time 2.22 seconds
Started Mar 21 03:10:35 PM PDT 24
Finished Mar 21 03:10:39 PM PDT 24
Peak memory 204684 kb
Host smart-d60f6eb0-d713-4029-ad5c-fecb75806091
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211373759 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
4211373759
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1311511116
Short name T255
Test name
Test status
Simulation time 193648113 ps
CPU time 0.7 seconds
Started Mar 21 03:10:34 PM PDT 24
Finished Mar 21 03:10:37 PM PDT 24
Peak memory 204468 kb
Host smart-b93a21c6-0f2a-4ddf-bb1d-a987a8781603
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311511116 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
1311511116
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.1487881844
Short name T339
Test name
Test status
Simulation time 549388420 ps
CPU time 6.22 seconds
Started Mar 21 03:10:51 PM PDT 24
Finished Mar 21 03:10:57 PM PDT 24
Peak memory 204784 kb
Host smart-3aefdf96-1ab8-44ec-8ea6-e087a7970a1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487881844 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.1487881844
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.1519923453
Short name T328
Test name
Test status
Simulation time 73579010 ps
CPU time 4.15 seconds
Started Mar 21 03:10:34 PM PDT 24
Finished Mar 21 03:10:40 PM PDT 24
Peak memory 213000 kb
Host smart-5e6fd038-4c4c-4b44-93f0-77a0d29bf403
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519923453 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.1519923453
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2702473832
Short name T33
Test name
Test status
Simulation time 1297500326 ps
CPU time 20.62 seconds
Started Mar 21 03:10:35 PM PDT 24
Finished Mar 21 03:10:57 PM PDT 24
Peak memory 221044 kb
Host smart-83b29ff0-536d-4cc5-8fdc-0cedf18795e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702473832 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.2
702473832
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.1172385876
Short name T292
Test name
Test status
Simulation time 5159658583 ps
CPU time 5.43 seconds
Started Mar 21 03:10:46 PM PDT 24
Finished Mar 21 03:10:53 PM PDT 24
Peak memory 218104 kb
Host smart-45c794dd-cb80-45eb-bbc1-73bbff0c840e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172385876 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.1172385876
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.1027723944
Short name T351
Test name
Test status
Simulation time 58128410 ps
CPU time 1.49 seconds
Started Mar 21 03:10:48 PM PDT 24
Finished Mar 21 03:10:50 PM PDT 24
Peak memory 221124 kb
Host smart-3de22f8b-9c4b-43bc-a718-714ce09e9362
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027723944 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.1027723944
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.368772891
Short name T315
Test name
Test status
Simulation time 808745212 ps
CPU time 3.37 seconds
Started Mar 21 03:10:46 PM PDT 24
Finished Mar 21 03:10:50 PM PDT 24
Peak memory 204688 kb
Host smart-ca219dcc-6942-44fe-98f8-dd0ca89b6eed
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368772891 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.368772891
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.1322932094
Short name T364
Test name
Test status
Simulation time 109418843 ps
CPU time 0.85 seconds
Started Mar 21 03:10:46 PM PDT 24
Finished Mar 21 03:10:47 PM PDT 24
Peak memory 204524 kb
Host smart-12dd966a-b4ea-4a85-9c4a-c4da1956689a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322932094 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
1322932094
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.1570078105
Short name T371
Test name
Test status
Simulation time 3026439920 ps
CPU time 6.44 seconds
Started Mar 21 03:10:48 PM PDT 24
Finished Mar 21 03:10:54 PM PDT 24
Peak memory 212992 kb
Host smart-8e7fb630-9113-4b92-950d-4e7838927358
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570078105 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.1570078105
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.2313181301
Short name T304
Test name
Test status
Simulation time 409499796 ps
CPU time 15.67 seconds
Started Mar 21 03:10:47 PM PDT 24
Finished Mar 21 03:11:03 PM PDT 24
Peak memory 213012 kb
Host smart-d0a0eae2-744b-4f3a-b0ab-6a6dd5b2cc5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313181301 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.2
313181301
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.3348369467
Short name T322
Test name
Test status
Simulation time 3388166680 ps
CPU time 7.45 seconds
Started Mar 21 03:10:47 PM PDT 24
Finished Mar 21 03:10:55 PM PDT 24
Peak memory 219284 kb
Host smart-8967dc5d-bfe0-467e-bec6-30837d0ad1e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348369467 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.3348369467
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2878069505
Short name T108
Test name
Test status
Simulation time 57006829 ps
CPU time 1.61 seconds
Started Mar 21 03:10:48 PM PDT 24
Finished Mar 21 03:10:50 PM PDT 24
Peak memory 212828 kb
Host smart-51d1c7da-c3d5-40f9-a4f2-73c5598ad77e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878069505 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.2878069505
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.2930497609
Short name T263
Test name
Test status
Simulation time 233429664 ps
CPU time 1.32 seconds
Started Mar 21 03:10:48 PM PDT 24
Finished Mar 21 03:10:49 PM PDT 24
Peak memory 204676 kb
Host smart-6505f2ad-aa04-4b89-ab80-11363b034a0d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930497609 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
2930497609
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.950073472
Short name T362
Test name
Test status
Simulation time 63688356 ps
CPU time 0.72 seconds
Started Mar 21 03:10:46 PM PDT 24
Finished Mar 21 03:10:47 PM PDT 24
Peak memory 204492 kb
Host smart-e18b52d6-098f-414b-9c6f-ae0880d2b929
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950073472 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.950073472
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.2567940035
Short name T76
Test name
Test status
Simulation time 3686625601 ps
CPU time 9.23 seconds
Started Mar 21 03:10:49 PM PDT 24
Finished Mar 21 03:10:58 PM PDT 24
Peak memory 204832 kb
Host smart-539b2641-997b-452f-b031-c5d81c65487c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567940035 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.2567940035
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.1777453
Short name T367
Test name
Test status
Simulation time 248001545 ps
CPU time 3.06 seconds
Started Mar 21 03:10:48 PM PDT 24
Finished Mar 21 03:10:51 PM PDT 24
Peak memory 212872 kb
Host smart-1bb0a081-4180-48ae-9dcb-74c5620bf004
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777453 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.1777453
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2776956999
Short name T119
Test name
Test status
Simulation time 1248126037 ps
CPU time 19.49 seconds
Started Mar 21 03:10:51 PM PDT 24
Finished Mar 21 03:11:10 PM PDT 24
Peak memory 212932 kb
Host smart-ff3bad28-fc6c-4d61-a5eb-38f046fd8925
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776956999 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.2
776956999
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.1345579118
Short name T363
Test name
Test status
Simulation time 635860762 ps
CPU time 3.48 seconds
Started Mar 21 03:10:46 PM PDT 24
Finished Mar 21 03:10:49 PM PDT 24
Peak memory 221180 kb
Host smart-297ce06e-5fcf-4a1b-9fd4-1a20966b96b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345579118 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.1345579118
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.3255030860
Short name T96
Test name
Test status
Simulation time 59845936 ps
CPU time 2.34 seconds
Started Mar 21 03:10:46 PM PDT 24
Finished Mar 21 03:10:49 PM PDT 24
Peak memory 212948 kb
Host smart-a6645c9f-9550-466f-a7cc-7f3c20b484d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255030860 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.3255030860
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.3304321294
Short name T257
Test name
Test status
Simulation time 381955011 ps
CPU time 1.88 seconds
Started Mar 21 03:10:49 PM PDT 24
Finished Mar 21 03:10:51 PM PDT 24
Peak memory 204696 kb
Host smart-c1d7e487-82d0-44c0-bd36-fb39d9ecb6fa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304321294 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
3304321294
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.870265562
Short name T350
Test name
Test status
Simulation time 54310263 ps
CPU time 0.73 seconds
Started Mar 21 03:10:47 PM PDT 24
Finished Mar 21 03:10:48 PM PDT 24
Peak memory 204464 kb
Host smart-cbf5aa75-3786-429d-8500-486b0e10216a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870265562 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.870265562
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.126979965
Short name T289
Test name
Test status
Simulation time 1634724267 ps
CPU time 4.65 seconds
Started Mar 21 03:10:46 PM PDT 24
Finished Mar 21 03:10:51 PM PDT 24
Peak memory 204688 kb
Host smart-1d83bd0e-1f01-443b-951b-a7306fa5efd9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126979965 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same_
csr_outstanding.126979965
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3426448458
Short name T311
Test name
Test status
Simulation time 65028910 ps
CPU time 4.36 seconds
Started Mar 21 03:10:48 PM PDT 24
Finished Mar 21 03:10:52 PM PDT 24
Peak memory 212948 kb
Host smart-57b969a7-b2a4-4240-87ab-298cee193c5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426448458 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.3426448458
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.202038223
Short name T135
Test name
Test status
Simulation time 3890007128 ps
CPU time 20.28 seconds
Started Mar 21 03:10:48 PM PDT 24
Finished Mar 21 03:11:08 PM PDT 24
Peak memory 213028 kb
Host smart-35e24705-0d02-4959-931a-6639e2f70f76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202038223 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.202038223
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.3290329560
Short name T381
Test name
Test status
Simulation time 141912166 ps
CPU time 2.68 seconds
Started Mar 21 03:10:50 PM PDT 24
Finished Mar 21 03:10:53 PM PDT 24
Peak memory 218236 kb
Host smart-c884658c-2e84-4a5c-8f82-088ce1146c03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290329560 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.3290329560
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.4247208833
Short name T106
Test name
Test status
Simulation time 61718591 ps
CPU time 1.6 seconds
Started Mar 21 03:10:48 PM PDT 24
Finished Mar 21 03:10:50 PM PDT 24
Peak memory 212952 kb
Host smart-c9f4c24d-1d20-4593-a4c4-12e6a92791db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247208833 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.4247208833
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2275740554
Short name T279
Test name
Test status
Simulation time 408533341 ps
CPU time 1.32 seconds
Started Mar 21 03:10:50 PM PDT 24
Finished Mar 21 03:10:51 PM PDT 24
Peak memory 204632 kb
Host smart-ebc26d5d-a8d8-474a-9b67-de6ff2d3f07f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275740554 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
2275740554
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.4072166901
Short name T285
Test name
Test status
Simulation time 40178217 ps
CPU time 0.76 seconds
Started Mar 21 03:10:48 PM PDT 24
Finished Mar 21 03:10:49 PM PDT 24
Peak memory 204480 kb
Host smart-72e6cbb2-f831-4657-85c8-65da014ef8da
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072166901 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
4072166901
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.1561695065
Short name T313
Test name
Test status
Simulation time 407534623 ps
CPU time 7.69 seconds
Started Mar 21 03:10:48 PM PDT 24
Finished Mar 21 03:10:56 PM PDT 24
Peak memory 204780 kb
Host smart-b726f249-384e-4e10-b51b-a35992de02e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561695065 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.1561695065
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tap_fsm_rand_reset.2349643869
Short name T282
Test name
Test status
Simulation time 14161772875 ps
CPU time 11.58 seconds
Started Mar 21 03:10:47 PM PDT 24
Finished Mar 21 03:10:59 PM PDT 24
Peak memory 220696 kb
Host smart-1996d4b9-a8e9-4050-93ab-5e38155f1908
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349643869 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rv_dm_tap_fsm_rand_reset.2349643869
Directory /workspace/17.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.4001948497
Short name T329
Test name
Test status
Simulation time 287864594 ps
CPU time 3.08 seconds
Started Mar 21 03:10:46 PM PDT 24
Finished Mar 21 03:10:50 PM PDT 24
Peak memory 212888 kb
Host smart-7e664b21-1c4d-454a-9b49-3dd3505796b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001948497 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.4001948497
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.393140471
Short name T138
Test name
Test status
Simulation time 367911118 ps
CPU time 8.61 seconds
Started Mar 21 03:10:50 PM PDT 24
Finished Mar 21 03:10:59 PM PDT 24
Peak memory 212916 kb
Host smart-08438689-181f-45c6-b900-5d8bc4ee942f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393140471 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.393140471
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2858002424
Short name T74
Test name
Test status
Simulation time 1749440184 ps
CPU time 6.11 seconds
Started Mar 21 03:10:52 PM PDT 24
Finished Mar 21 03:10:58 PM PDT 24
Peak memory 221164 kb
Host smart-e4975b5f-0623-47e3-9b47-1e8408686a0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858002424 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.2858002424
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.3334397422
Short name T93
Test name
Test status
Simulation time 81177010 ps
CPU time 2.32 seconds
Started Mar 21 03:10:49 PM PDT 24
Finished Mar 21 03:10:52 PM PDT 24
Peak memory 212968 kb
Host smart-6df23b2d-4b47-4cde-ba3e-4b408370ec26
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334397422 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.3334397422
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.3427148100
Short name T260
Test name
Test status
Simulation time 342931489 ps
CPU time 2.06 seconds
Started Mar 21 03:10:48 PM PDT 24
Finished Mar 21 03:10:51 PM PDT 24
Peak memory 204684 kb
Host smart-3a4d80ba-150a-498f-9cd4-53bc2d8034b6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427148100 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
3427148100
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2370358503
Short name T344
Test name
Test status
Simulation time 67829963 ps
CPU time 0.85 seconds
Started Mar 21 03:10:50 PM PDT 24
Finished Mar 21 03:10:51 PM PDT 24
Peak memory 204480 kb
Host smart-f10ee302-4353-4753-9ba9-c6a4663b30a1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370358503 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
2370358503
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.713820744
Short name T323
Test name
Test status
Simulation time 168003839 ps
CPU time 6.6 seconds
Started Mar 21 03:10:50 PM PDT 24
Finished Mar 21 03:10:57 PM PDT 24
Peak memory 204732 kb
Host smart-13471152-e073-4794-8dc7-63a4c5c16d45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713820744 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same_
csr_outstanding.713820744
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.4097411136
Short name T267
Test name
Test status
Simulation time 63697490 ps
CPU time 3.27 seconds
Started Mar 21 03:10:51 PM PDT 24
Finished Mar 21 03:10:55 PM PDT 24
Peak memory 212948 kb
Host smart-853d9b70-5438-4c3f-927a-a88ace2fea3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097411136 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.4097411136
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.2194862871
Short name T361
Test name
Test status
Simulation time 414233969 ps
CPU time 8.41 seconds
Started Mar 21 03:10:48 PM PDT 24
Finished Mar 21 03:10:57 PM PDT 24
Peak memory 221064 kb
Host smart-8c636c09-d154-4983-86bc-9051570e4248
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194862871 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.2
194862871
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2261193028
Short name T154
Test name
Test status
Simulation time 291125888 ps
CPU time 4.1 seconds
Started Mar 21 03:10:46 PM PDT 24
Finished Mar 21 03:10:50 PM PDT 24
Peak memory 218596 kb
Host smart-8d4b7ace-5dd6-40fe-90a8-06def05e0d2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261193028 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.2261193028
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.562274757
Short name T95
Test name
Test status
Simulation time 125050049 ps
CPU time 1.5 seconds
Started Mar 21 03:10:50 PM PDT 24
Finished Mar 21 03:10:52 PM PDT 24
Peak memory 213000 kb
Host smart-652298a9-6107-4359-b573-20237e2ac572
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562274757 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.562274757
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.1512667440
Short name T353
Test name
Test status
Simulation time 383171041 ps
CPU time 1.19 seconds
Started Mar 21 03:10:50 PM PDT 24
Finished Mar 21 03:10:52 PM PDT 24
Peak memory 204644 kb
Host smart-c0a488dd-518c-45f2-a840-7ce569e2b34d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512667440 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
1512667440
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.591106700
Short name T65
Test name
Test status
Simulation time 94968271 ps
CPU time 0.75 seconds
Started Mar 21 03:10:50 PM PDT 24
Finished Mar 21 03:10:51 PM PDT 24
Peak memory 204428 kb
Host smart-d293cf1d-0142-4d32-98dc-173f65083473
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591106700 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.591106700
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.3964944568
Short name T37
Test name
Test status
Simulation time 2577956963 ps
CPU time 8.1 seconds
Started Mar 21 03:10:49 PM PDT 24
Finished Mar 21 03:10:57 PM PDT 24
Peak memory 204816 kb
Host smart-0280724e-b9cb-4dc2-a54e-0ebd3bdd3db0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964944568 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.3964944568
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tap_fsm_rand_reset.3290029279
Short name T330
Test name
Test status
Simulation time 11345005195 ps
CPU time 33.23 seconds
Started Mar 21 03:10:49 PM PDT 24
Finished Mar 21 03:11:22 PM PDT 24
Peak memory 221236 kb
Host smart-4bd6ae33-dbe4-4b45-a7f1-d4cd06c044da
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290029279 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rv_dm_tap_fsm_rand_reset.3290029279
Directory /workspace/19.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2035753969
Short name T374
Test name
Test status
Simulation time 802943384 ps
CPU time 15.89 seconds
Started Mar 21 03:10:51 PM PDT 24
Finished Mar 21 03:11:07 PM PDT 24
Peak memory 212984 kb
Host smart-a658b64e-2dbd-4db5-83d3-6814ec1896bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035753969 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.2
035753969
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.11990618
Short name T375
Test name
Test status
Simulation time 1503134290 ps
CPU time 25.46 seconds
Started Mar 21 03:09:57 PM PDT 24
Finished Mar 21 03:10:23 PM PDT 24
Peak memory 214008 kb
Host smart-0343ce69-49d1-46d9-9e8b-dbf3ceac121a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11990618 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UV
M_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 2.rv_dm_csr_aliasing.11990618
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.4200007734
Short name T80
Test name
Test status
Simulation time 3807104705 ps
CPU time 36.4 seconds
Started Mar 21 03:09:57 PM PDT 24
Finished Mar 21 03:10:33 PM PDT 24
Peak memory 213056 kb
Host smart-f8375e0d-29ee-4dda-878a-1fd0af163be4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200007734 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.4200007734
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.2144530478
Short name T82
Test name
Test status
Simulation time 222610048 ps
CPU time 1.56 seconds
Started Mar 21 03:09:56 PM PDT 24
Finished Mar 21 03:09:58 PM PDT 24
Peak memory 212912 kb
Host smart-eb2ddbcc-7ff9-41da-922f-73a72ffd9afd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144530478 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.2144530478
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3248801915
Short name T72
Test name
Test status
Simulation time 2849609066 ps
CPU time 4.13 seconds
Started Mar 21 03:10:07 PM PDT 24
Finished Mar 21 03:10:11 PM PDT 24
Peak memory 220852 kb
Host smart-c915b39f-0848-421a-b98d-554db803c39f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248801915 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.3248801915
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.888480641
Short name T103
Test name
Test status
Simulation time 77006498 ps
CPU time 1.62 seconds
Started Mar 21 03:09:56 PM PDT 24
Finished Mar 21 03:09:58 PM PDT 24
Peak memory 213020 kb
Host smart-67efe469-047e-4712-bd81-d3bdcd7e318d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888480641 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.888480641
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.4097549349
Short name T327
Test name
Test status
Simulation time 19347609223 ps
CPU time 70.88 seconds
Started Mar 21 03:09:56 PM PDT 24
Finished Mar 21 03:11:07 PM PDT 24
Peak memory 204772 kb
Host smart-aa687452-f2bd-475b-a241-176aa62248a5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097549349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.4097549349
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.2406305139
Short name T379
Test name
Test status
Simulation time 17001565970 ps
CPU time 32.11 seconds
Started Mar 21 03:09:56 PM PDT 24
Finished Mar 21 03:10:29 PM PDT 24
Peak memory 204772 kb
Host smart-0fdcbbee-dff1-47d0-bd28-6ebda0f76557
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406305139 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_bit_bash.2406305139
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.626371931
Short name T89
Test name
Test status
Simulation time 539538951 ps
CPU time 2.36 seconds
Started Mar 21 03:09:55 PM PDT 24
Finished Mar 21 03:09:58 PM PDT 24
Peak memory 204764 kb
Host smart-de3cd02b-2e6a-4442-b024-0c1e1a8e205c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626371931 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr
_hw_reset.626371931
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.945777002
Short name T305
Test name
Test status
Simulation time 316898699 ps
CPU time 1 seconds
Started Mar 21 03:09:58 PM PDT 24
Finished Mar 21 03:09:59 PM PDT 24
Peak memory 204740 kb
Host smart-e4153217-cb90-4db3-bb96-490f3857b400
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945777002 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.945777002
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.139441630
Short name T284
Test name
Test status
Simulation time 69573896 ps
CPU time 0.77 seconds
Started Mar 21 03:09:56 PM PDT 24
Finished Mar 21 03:09:57 PM PDT 24
Peak memory 204500 kb
Host smart-d85892f4-0882-4138-b54a-32dfbad3ff6d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139441630 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_aliasing.139441630
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1834335894
Short name T334
Test name
Test status
Simulation time 3978145762 ps
CPU time 4.66 seconds
Started Mar 21 03:09:56 PM PDT 24
Finished Mar 21 03:10:01 PM PDT 24
Peak memory 204696 kb
Host smart-76a4308d-75d9-41b4-8cff-0169571632ab
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834335894 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.1834335894
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2358678218
Short name T372
Test name
Test status
Simulation time 44496819 ps
CPU time 0.8 seconds
Started Mar 21 03:09:57 PM PDT 24
Finished Mar 21 03:09:58 PM PDT 24
Peak memory 204476 kb
Host smart-d8baa5d1-08e4-4364-b350-9493f87a094d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358678218 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.2358678218
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.57948065
Short name T249
Test name
Test status
Simulation time 48306739 ps
CPU time 0.72 seconds
Started Mar 21 03:09:57 PM PDT 24
Finished Mar 21 03:09:58 PM PDT 24
Peak memory 204464 kb
Host smart-afb3ce68-72f1-4145-b824-adca5a1b63fb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57948065 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.57948065
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2545792664
Short name T319
Test name
Test status
Simulation time 19200141 ps
CPU time 0.73 seconds
Started Mar 21 03:09:56 PM PDT 24
Finished Mar 21 03:09:57 PM PDT 24
Peak memory 204488 kb
Host smart-d457f31e-e543-4314-825f-ddc3356b00d3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545792664 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.2545792664
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.3761594534
Short name T293
Test name
Test status
Simulation time 18872926 ps
CPU time 0.68 seconds
Started Mar 21 03:09:56 PM PDT 24
Finished Mar 21 03:09:57 PM PDT 24
Peak memory 204508 kb
Host smart-876531b5-d70c-4225-978d-251dbbe814c8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761594534 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.3761594534
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.2182665288
Short name T101
Test name
Test status
Simulation time 411293475 ps
CPU time 8.15 seconds
Started Mar 21 03:10:11 PM PDT 24
Finished Mar 21 03:10:20 PM PDT 24
Peak memory 204756 kb
Host smart-d2587900-a223-4b4c-9607-f907c5adcd4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182665288 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.2182665288
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.338938194
Short name T307
Test name
Test status
Simulation time 136343800 ps
CPU time 4.19 seconds
Started Mar 21 03:09:56 PM PDT 24
Finished Mar 21 03:10:01 PM PDT 24
Peak memory 212944 kb
Host smart-4ffb3790-21d8-4ba1-8017-36786e8a9aea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338938194 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.338938194
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.80044394
Short name T291
Test name
Test status
Simulation time 2021651327 ps
CPU time 10.51 seconds
Started Mar 21 03:09:57 PM PDT 24
Finished Mar 21 03:10:07 PM PDT 24
Peak memory 213004 kb
Host smart-7c32dd8d-e76c-4c5c-905d-2dfe4a4454a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80044394 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.80044394
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_dm_tap_fsm_rand_reset.608578388
Short name T32
Test name
Test status
Simulation time 10695424602 ps
CPU time 11.67 seconds
Started Mar 21 03:10:45 PM PDT 24
Finished Mar 21 03:10:57 PM PDT 24
Peak memory 220828 kb
Host smart-bbe3fb5c-9f41-41b8-b58c-17012dfb3a0d
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608578388 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 20.rv_dm_tap_fsm_rand_reset.608578388
Directory /workspace/20.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/23.rv_dm_tap_fsm_rand_reset.522091681
Short name T378
Test name
Test status
Simulation time 9761426772 ps
CPU time 23.1 seconds
Started Mar 21 03:11:11 PM PDT 24
Finished Mar 21 03:11:34 PM PDT 24
Peak memory 219564 kb
Host smart-093a341a-90d5-425f-990a-02079e5cebfe
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522091681 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 23.rv_dm_tap_fsm_rand_reset.522091681
Directory /workspace/23.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/25.rv_dm_tap_fsm_rand_reset.2116970945
Short name T306
Test name
Test status
Simulation time 6219417747 ps
CPU time 23.2 seconds
Started Mar 21 03:10:58 PM PDT 24
Finished Mar 21 03:11:21 PM PDT 24
Peak memory 218504 kb
Host smart-da984210-fcdc-44ce-a187-ca11109db0c9
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116970945 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 25.rv_dm_tap_fsm_rand_reset.2116970945
Directory /workspace/25.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.3960591821
Short name T107
Test name
Test status
Simulation time 22008866079 ps
CPU time 67.07 seconds
Started Mar 21 03:10:13 PM PDT 24
Finished Mar 21 03:11:20 PM PDT 24
Peak memory 213104 kb
Host smart-15558791-0839-4bf4-a480-069d5d13a2a0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960591821 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.3960591821
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1166352940
Short name T300
Test name
Test status
Simulation time 715674995 ps
CPU time 27.91 seconds
Started Mar 21 03:10:07 PM PDT 24
Finished Mar 21 03:10:35 PM PDT 24
Peak memory 212944 kb
Host smart-d46f7488-6e82-4c5b-99de-f47786cf956e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166352940 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.1166352940
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1385465248
Short name T114
Test name
Test status
Simulation time 456393403 ps
CPU time 2.43 seconds
Started Mar 21 03:10:07 PM PDT 24
Finished Mar 21 03:10:10 PM PDT 24
Peak memory 213000 kb
Host smart-c976f05c-443f-4ecb-8e3e-5e97adf3ed1a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385465248 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.1385465248
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.3183453981
Short name T316
Test name
Test status
Simulation time 3090947759 ps
CPU time 4.93 seconds
Started Mar 21 03:10:06 PM PDT 24
Finished Mar 21 03:10:12 PM PDT 24
Peak memory 217644 kb
Host smart-ade396ee-7771-468e-98d7-8e652b3a0500
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183453981 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.3183453981
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.3483541277
Short name T345
Test name
Test status
Simulation time 144966031 ps
CPU time 2.22 seconds
Started Mar 21 03:10:17 PM PDT 24
Finished Mar 21 03:10:19 PM PDT 24
Peak memory 212920 kb
Host smart-22789e74-f414-498f-a50f-62ad8e3a1335
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483541277 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.3483541277
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.4077070060
Short name T287
Test name
Test status
Simulation time 29568233388 ps
CPU time 29.78 seconds
Started Mar 21 03:10:07 PM PDT 24
Finished Mar 21 03:10:37 PM PDT 24
Peak memory 204756 kb
Host smart-7f7dc8ac-cc5a-4936-a2cd-88f7b1705781
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077070060 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.4077070060
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1676086024
Short name T366
Test name
Test status
Simulation time 48968261933 ps
CPU time 162.03 seconds
Started Mar 21 03:10:07 PM PDT 24
Finished Mar 21 03:12:49 PM PDT 24
Peak memory 204684 kb
Host smart-c1ba77ac-38e4-4b23-87a4-d65fee795141
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676086024 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_bit_bash.1676086024
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2769784224
Short name T88
Test name
Test status
Simulation time 565788319 ps
CPU time 1.86 seconds
Started Mar 21 03:10:07 PM PDT 24
Finished Mar 21 03:10:09 PM PDT 24
Peak memory 204780 kb
Host smart-b705f9c7-6149-47a1-b28f-4f20ff286767
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769784224 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.2769784224
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.14508010
Short name T348
Test name
Test status
Simulation time 311841216 ps
CPU time 1.19 seconds
Started Mar 21 03:10:06 PM PDT 24
Finished Mar 21 03:10:08 PM PDT 24
Peak memory 204648 kb
Host smart-02e942e7-3bb5-4b8e-9077-ca32f2bba702
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14508010 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.14508010
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.4006922671
Short name T286
Test name
Test status
Simulation time 50984647 ps
CPU time 0.72 seconds
Started Mar 21 03:10:12 PM PDT 24
Finished Mar 21 03:10:13 PM PDT 24
Peak memory 204492 kb
Host smart-dd77a782-e41b-4525-8f96-769474c55306
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006922671 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.4006922671
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.3616692116
Short name T63
Test name
Test status
Simulation time 1849527070 ps
CPU time 7.19 seconds
Started Mar 21 03:10:08 PM PDT 24
Finished Mar 21 03:10:16 PM PDT 24
Peak memory 204776 kb
Host smart-9eeba147-e552-4cbb-bc40-ff33109cb456
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616692116 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.3616692116
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3148527048
Short name T294
Test name
Test status
Simulation time 71014713 ps
CPU time 0.87 seconds
Started Mar 21 03:10:11 PM PDT 24
Finished Mar 21 03:10:13 PM PDT 24
Peak memory 204428 kb
Host smart-0990f4b1-daac-4fea-8a7f-c8ca34e73bfc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148527048 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.3148527048
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.3658925018
Short name T298
Test name
Test status
Simulation time 39055686 ps
CPU time 0.79 seconds
Started Mar 21 03:10:08 PM PDT 24
Finished Mar 21 03:10:09 PM PDT 24
Peak memory 204536 kb
Host smart-1735ead1-5156-401d-9a8a-b0d16ae960c1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658925018 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.3
658925018
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.4129882154
Short name T274
Test name
Test status
Simulation time 27516264 ps
CPU time 0.69 seconds
Started Mar 21 03:10:06 PM PDT 24
Finished Mar 21 03:10:07 PM PDT 24
Peak memory 204484 kb
Host smart-e4cf00eb-a75e-47e8-b5e5-0bed53a5ac5d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129882154 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.4129882154
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.2115558947
Short name T261
Test name
Test status
Simulation time 16631641 ps
CPU time 0.7 seconds
Started Mar 21 03:10:08 PM PDT 24
Finished Mar 21 03:10:09 PM PDT 24
Peak memory 204540 kb
Host smart-350a344b-bc87-440c-875d-d8d3177e9539
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115558947 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.2115558947
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.1750409214
Short name T333
Test name
Test status
Simulation time 714430565 ps
CPU time 4.07 seconds
Started Mar 21 03:10:14 PM PDT 24
Finished Mar 21 03:10:19 PM PDT 24
Peak memory 204640 kb
Host smart-c42c283f-82d3-4ace-97c8-89bbd220592e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750409214 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.1750409214
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.890047636
Short name T352
Test name
Test status
Simulation time 7383259193 ps
CPU time 21.35 seconds
Started Mar 21 03:10:06 PM PDT 24
Finished Mar 21 03:10:28 PM PDT 24
Peak memory 214104 kb
Host smart-4464628c-c559-4792-bfef-590195e0ae2a
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890047636 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.890047636
Directory /workspace/3.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.1986456886
Short name T127
Test name
Test status
Simulation time 664525985 ps
CPU time 4.91 seconds
Started Mar 21 03:10:06 PM PDT 24
Finished Mar 21 03:10:12 PM PDT 24
Peak memory 213016 kb
Host smart-2b5fd069-aead-4064-bf83-12e795dc8a93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986456886 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.1986456886
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/32.rv_dm_tap_fsm_rand_reset.1286845091
Short name T376
Test name
Test status
Simulation time 18355311776 ps
CPU time 8.76 seconds
Started Mar 21 03:11:06 PM PDT 24
Finished Mar 21 03:11:15 PM PDT 24
Peak memory 221040 kb
Host smart-2e03d1fd-e0d8-4934-bc7d-b24457ca4a7c
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286845091 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 32.rv_dm_tap_fsm_rand_reset.1286845091
Directory /workspace/32.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/34.rv_dm_tap_fsm_rand_reset.3788941641
Short name T272
Test name
Test status
Simulation time 13321706622 ps
CPU time 13.71 seconds
Started Mar 21 03:10:59 PM PDT 24
Finished Mar 21 03:11:12 PM PDT 24
Peak memory 213592 kb
Host smart-0ec5bedf-226b-41b3-83dd-c80a198b70ab
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788941641 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 34.rv_dm_tap_fsm_rand_reset.3788941641
Directory /workspace/34.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/35.rv_dm_tap_fsm_rand_reset.2930143138
Short name T275
Test name
Test status
Simulation time 6175163024 ps
CPU time 22.3 seconds
Started Mar 21 03:11:01 PM PDT 24
Finished Mar 21 03:11:24 PM PDT 24
Peak memory 213892 kb
Host smart-5ad13d2e-28cb-4f14-9834-c5e34f76c089
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930143138 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 35.rv_dm_tap_fsm_rand_reset.2930143138
Directory /workspace/35.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/36.rv_dm_tap_fsm_rand_reset.586042066
Short name T357
Test name
Test status
Simulation time 9334498492 ps
CPU time 16.99 seconds
Started Mar 21 03:10:59 PM PDT 24
Finished Mar 21 03:11:16 PM PDT 24
Peak memory 213012 kb
Host smart-65511128-7289-41c0-ad43-b5030a46b7d6
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586042066 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 36.rv_dm_tap_fsm_rand_reset.586042066
Directory /workspace/36.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2641679007
Short name T373
Test name
Test status
Simulation time 6900559459 ps
CPU time 32.82 seconds
Started Mar 21 03:10:07 PM PDT 24
Finished Mar 21 03:10:40 PM PDT 24
Peak memory 204840 kb
Host smart-51fa7d16-18b1-4ed8-ad1d-584fc7fe00bf
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641679007 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.2641679007
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.3203353753
Short name T100
Test name
Test status
Simulation time 15139296218 ps
CPU time 38.59 seconds
Started Mar 21 03:10:19 PM PDT 24
Finished Mar 21 03:10:58 PM PDT 24
Peak memory 213048 kb
Host smart-493a8270-2d50-4151-a25e-fae11470cf54
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203353753 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.3203353753
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.1685594562
Short name T309
Test name
Test status
Simulation time 65291601 ps
CPU time 1.58 seconds
Started Mar 21 03:10:17 PM PDT 24
Finished Mar 21 03:10:19 PM PDT 24
Peak memory 212936 kb
Host smart-a8726f1c-7fdf-4603-bbae-d632295cf6ec
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685594562 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.1685594562
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2243393271
Short name T318
Test name
Test status
Simulation time 2738357655 ps
CPU time 5.16 seconds
Started Mar 21 03:10:18 PM PDT 24
Finished Mar 21 03:10:23 PM PDT 24
Peak memory 217868 kb
Host smart-9abfbf2b-07d9-4686-8b5b-f47b7d5e8f3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243393271 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.2243393271
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.4243286825
Short name T343
Test name
Test status
Simulation time 48180161 ps
CPU time 1.5 seconds
Started Mar 21 03:10:15 PM PDT 24
Finished Mar 21 03:10:17 PM PDT 24
Peak memory 212920 kb
Host smart-a7d31428-10e9-4d38-a8e6-2bb60d9cbf4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243286825 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.4243286825
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2876819984
Short name T302
Test name
Test status
Simulation time 34246861107 ps
CPU time 33.89 seconds
Started Mar 21 03:10:08 PM PDT 24
Finished Mar 21 03:10:42 PM PDT 24
Peak memory 204752 kb
Host smart-78ebcdd7-6238-49c2-9553-45a567edfb7b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876819984 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.2876819984
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.1013793547
Short name T91
Test name
Test status
Simulation time 1130121994 ps
CPU time 1.61 seconds
Started Mar 21 03:10:07 PM PDT 24
Finished Mar 21 03:10:09 PM PDT 24
Peak memory 204692 kb
Host smart-2e54765f-6bb8-4d2a-9425-f8f8ce1005db
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013793547 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.1013793547
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3688955872
Short name T370
Test name
Test status
Simulation time 905126777 ps
CPU time 3.49 seconds
Started Mar 21 03:10:09 PM PDT 24
Finished Mar 21 03:10:13 PM PDT 24
Peak memory 204628 kb
Host smart-5601257a-c7e1-45d7-a38e-dc5324478bac
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688955872 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.3
688955872
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.478429836
Short name T252
Test name
Test status
Simulation time 62246935 ps
CPU time 0.9 seconds
Started Mar 21 03:10:06 PM PDT 24
Finished Mar 21 03:10:08 PM PDT 24
Peak memory 204548 kb
Host smart-c9d5bfcd-f957-4810-ada6-19237200eb59
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478429836 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr
_aliasing.478429836
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.4070756486
Short name T369
Test name
Test status
Simulation time 1306231911 ps
CPU time 4.78 seconds
Started Mar 21 03:10:07 PM PDT 24
Finished Mar 21 03:10:12 PM PDT 24
Peak memory 204764 kb
Host smart-7ed33d28-a98d-4623-ac05-f750745e9124
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070756486 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.4070756486
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2034906827
Short name T276
Test name
Test status
Simulation time 44100602 ps
CPU time 0.84 seconds
Started Mar 21 03:10:09 PM PDT 24
Finished Mar 21 03:10:11 PM PDT 24
Peak memory 204484 kb
Host smart-44d02dc5-3088-4b37-91d5-66d0ad3b13fa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034906827 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.2034906827
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.3445870736
Short name T317
Test name
Test status
Simulation time 98089362 ps
CPU time 0.79 seconds
Started Mar 21 03:10:09 PM PDT 24
Finished Mar 21 03:10:11 PM PDT 24
Peak memory 204484 kb
Host smart-86cf5bc1-1a70-4e38-a36e-b5c22114e8c5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445870736 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.3
445870736
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1207349539
Short name T342
Test name
Test status
Simulation time 31805652 ps
CPU time 0.73 seconds
Started Mar 21 03:10:06 PM PDT 24
Finished Mar 21 03:10:07 PM PDT 24
Peak memory 204480 kb
Host smart-902ec73f-1a0b-4f8d-a121-87e094045a03
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207349539 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.1207349539
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.139886254
Short name T356
Test name
Test status
Simulation time 15127729 ps
CPU time 0.68 seconds
Started Mar 21 03:10:08 PM PDT 24
Finished Mar 21 03:10:09 PM PDT 24
Peak memory 204524 kb
Host smart-be34281d-17d0-4fe2-b95f-f97b2c962757
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139886254 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.139886254
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3193378707
Short name T297
Test name
Test status
Simulation time 215186594 ps
CPU time 4.22 seconds
Started Mar 21 03:10:19 PM PDT 24
Finished Mar 21 03:10:24 PM PDT 24
Peak memory 204748 kb
Host smart-77446fbd-bdfc-49f5-9f19-6e9688dfb4c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193378707 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.3193378707
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2640765456
Short name T66
Test name
Test status
Simulation time 204214552 ps
CPU time 4.73 seconds
Started Mar 21 03:10:12 PM PDT 24
Finished Mar 21 03:10:16 PM PDT 24
Peak memory 212856 kb
Host smart-153fa6cf-ac2f-410e-9488-e975e79fd077
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640765456 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.2640765456
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.1430896308
Short name T73
Test name
Test status
Simulation time 1752929618 ps
CPU time 4.42 seconds
Started Mar 21 03:10:18 PM PDT 24
Finished Mar 21 03:10:23 PM PDT 24
Peak memory 218240 kb
Host smart-6bf657ab-c3fc-4911-94ee-986da76c8a01
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430896308 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.1430896308
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.50024288
Short name T78
Test name
Test status
Simulation time 92721680 ps
CPU time 1.52 seconds
Started Mar 21 03:10:16 PM PDT 24
Finished Mar 21 03:10:18 PM PDT 24
Peak memory 218172 kb
Host smart-40921270-cbc0-4d28-97ac-ae26c54687ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50024288 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.50024288
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3436514866
Short name T355
Test name
Test status
Simulation time 461545511 ps
CPU time 1.23 seconds
Started Mar 21 03:10:17 PM PDT 24
Finished Mar 21 03:10:18 PM PDT 24
Peak memory 204804 kb
Host smart-ec4382b3-e12c-4ad8-9630-031968011db8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436514866 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.3
436514866
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3691635600
Short name T332
Test name
Test status
Simulation time 90326327 ps
CPU time 0.68 seconds
Started Mar 21 03:10:16 PM PDT 24
Finished Mar 21 03:10:17 PM PDT 24
Peak memory 204480 kb
Host smart-867862fd-019e-4d9b-b321-f727d2e936af
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691635600 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.3
691635600
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.2746408796
Short name T295
Test name
Test status
Simulation time 530234974 ps
CPU time 3.46 seconds
Started Mar 21 03:10:26 PM PDT 24
Finished Mar 21 03:10:30 PM PDT 24
Peak memory 204784 kb
Host smart-141c7281-2879-4c41-817e-7c5288bf2b66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746408796 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.2746408796
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.4135840092
Short name T61
Test name
Test status
Simulation time 12014460599 ps
CPU time 13.15 seconds
Started Mar 21 03:10:18 PM PDT 24
Finished Mar 21 03:10:31 PM PDT 24
Peak memory 214340 kb
Host smart-e863d955-7b5d-4270-ba71-838aa379a34f
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135840092 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.4135840092
Directory /workspace/5.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.2725160950
Short name T301
Test name
Test status
Simulation time 80231676 ps
CPU time 4.67 seconds
Started Mar 21 03:10:16 PM PDT 24
Finished Mar 21 03:10:21 PM PDT 24
Peak memory 212928 kb
Host smart-4b3b1d0f-70c0-4804-8a97-09872d9c739d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725160950 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.2725160950
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2038052912
Short name T136
Test name
Test status
Simulation time 1224144394 ps
CPU time 21.17 seconds
Started Mar 21 03:10:16 PM PDT 24
Finished Mar 21 03:10:37 PM PDT 24
Peak memory 221196 kb
Host smart-3a822520-96ff-45be-af5a-89b6b8ab2a4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038052912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.2038052912
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.1976152640
Short name T273
Test name
Test status
Simulation time 2879000180 ps
CPU time 6.25 seconds
Started Mar 21 03:10:18 PM PDT 24
Finished Mar 21 03:10:25 PM PDT 24
Peak memory 218980 kb
Host smart-27bdd638-3884-4ca5-9456-579e803f1334
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976152640 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.1976152640
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.2411579852
Short name T288
Test name
Test status
Simulation time 436989584 ps
CPU time 1.8 seconds
Started Mar 21 03:10:26 PM PDT 24
Finished Mar 21 03:10:28 PM PDT 24
Peak memory 218392 kb
Host smart-ba9fdd22-f0dd-4928-8ad2-c489f79b3d95
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411579852 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.2411579852
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.803972246
Short name T340
Test name
Test status
Simulation time 1426135676 ps
CPU time 3.11 seconds
Started Mar 21 03:10:21 PM PDT 24
Finished Mar 21 03:10:24 PM PDT 24
Peak memory 204676 kb
Host smart-a8cce436-cdfa-42bd-9480-cab2e3772f32
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803972246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.803972246
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.1133480398
Short name T265
Test name
Test status
Simulation time 117928750 ps
CPU time 0.75 seconds
Started Mar 21 03:10:18 PM PDT 24
Finished Mar 21 03:10:19 PM PDT 24
Peak memory 204476 kb
Host smart-f935f2e2-9193-471c-993a-30e4bdef5ced
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133480398 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.1
133480398
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2636229069
Short name T325
Test name
Test status
Simulation time 2728763427 ps
CPU time 8.53 seconds
Started Mar 21 03:10:26 PM PDT 24
Finished Mar 21 03:10:35 PM PDT 24
Peak memory 204792 kb
Host smart-fe83a73d-0e83-4a19-913b-5dc687346ed5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636229069 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.2636229069
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.1401557851
Short name T126
Test name
Test status
Simulation time 328328242 ps
CPU time 6 seconds
Started Mar 21 03:10:18 PM PDT 24
Finished Mar 21 03:10:24 PM PDT 24
Peak memory 212952 kb
Host smart-281a6d75-83dd-4cde-a1f3-af798ffc9841
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401557851 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.1401557851
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2178459262
Short name T134
Test name
Test status
Simulation time 1065943213 ps
CPU time 18.33 seconds
Started Mar 21 03:10:25 PM PDT 24
Finished Mar 21 03:10:43 PM PDT 24
Peak memory 221028 kb
Host smart-c4ce8701-1251-4ff1-b619-7397ad133c5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178459262 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.2178459262
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2511358263
Short name T321
Test name
Test status
Simulation time 3392525625 ps
CPU time 9.46 seconds
Started Mar 21 03:10:16 PM PDT 24
Finished Mar 21 03:10:26 PM PDT 24
Peak memory 220520 kb
Host smart-408ae54b-7fcc-4007-806c-deab69f1c287
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511358263 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.2511358263
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2631774472
Short name T268
Test name
Test status
Simulation time 585993321 ps
CPU time 1.36 seconds
Started Mar 21 03:10:26 PM PDT 24
Finished Mar 21 03:10:27 PM PDT 24
Peak memory 204636 kb
Host smart-f5284d72-d3fc-4b72-ba26-461df367a90a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631774472 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.2
631774472
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1463297727
Short name T256
Test name
Test status
Simulation time 125246447 ps
CPU time 0.72 seconds
Started Mar 21 03:10:17 PM PDT 24
Finished Mar 21 03:10:18 PM PDT 24
Peak memory 204484 kb
Host smart-8055acb6-b7d0-4f52-b78c-92990041cff3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463297727 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.1
463297727
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.915418770
Short name T111
Test name
Test status
Simulation time 1382784646 ps
CPU time 3.5 seconds
Started Mar 21 03:10:18 PM PDT 24
Finished Mar 21 03:10:22 PM PDT 24
Peak memory 204748 kb
Host smart-797c3d06-08ce-4f8d-9b6d-3021dc6a3b2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915418770 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_c
sr_outstanding.915418770
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.324831771
Short name T326
Test name
Test status
Simulation time 61669289 ps
CPU time 3.85 seconds
Started Mar 21 03:10:17 PM PDT 24
Finished Mar 21 03:10:21 PM PDT 24
Peak memory 212940 kb
Host smart-28f8d97d-cffe-4ee9-80da-cec9ec0fc233
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324831771 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.324831771
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2112518934
Short name T130
Test name
Test status
Simulation time 1908416218 ps
CPU time 20.95 seconds
Started Mar 21 03:10:25 PM PDT 24
Finished Mar 21 03:10:46 PM PDT 24
Peak memory 221072 kb
Host smart-a7c1b5bb-ac48-4908-985c-888ac2300512
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112518934 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.2112518934
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2547632166
Short name T320
Test name
Test status
Simulation time 1307371239 ps
CPU time 5.59 seconds
Started Mar 21 03:10:34 PM PDT 24
Finished Mar 21 03:10:42 PM PDT 24
Peak memory 215264 kb
Host smart-61b45d37-f149-479a-9d05-0f8733231981
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547632166 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.2547632166
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.3775625453
Short name T110
Test name
Test status
Simulation time 155526150 ps
CPU time 2.3 seconds
Started Mar 21 03:10:33 PM PDT 24
Finished Mar 21 03:10:36 PM PDT 24
Peak memory 218324 kb
Host smart-1e380df0-269b-44b1-bdb1-6ccac2778a33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775625453 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.3775625453
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.2130537709
Short name T283
Test name
Test status
Simulation time 446601140 ps
CPU time 1.18 seconds
Started Mar 21 03:10:21 PM PDT 24
Finished Mar 21 03:10:22 PM PDT 24
Peak memory 204760 kb
Host smart-3acc709c-0385-44d5-bb0d-eb6f8a19bdbd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130537709 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.2
130537709
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.730165200
Short name T266
Test name
Test status
Simulation time 41554178 ps
CPU time 0.77 seconds
Started Mar 21 03:10:17 PM PDT 24
Finished Mar 21 03:10:18 PM PDT 24
Peak memory 204524 kb
Host smart-e1e5d9ff-33a7-48ba-8572-3e26e67d43fe
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730165200 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.730165200
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.545486723
Short name T77
Test name
Test status
Simulation time 3921434074 ps
CPU time 7.43 seconds
Started Mar 21 03:10:35 PM PDT 24
Finished Mar 21 03:10:44 PM PDT 24
Peak memory 204856 kb
Host smart-c248109a-856f-4638-b54e-c707cbd4d42c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545486723 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_c
sr_outstanding.545486723
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.984904220
Short name T34
Test name
Test status
Simulation time 82472503 ps
CPU time 2.36 seconds
Started Mar 21 03:10:33 PM PDT 24
Finished Mar 21 03:10:38 PM PDT 24
Peak memory 212940 kb
Host smart-526c8580-c58b-4e78-9805-5ef363c87544
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984904220 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.984904220
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.250488834
Short name T132
Test name
Test status
Simulation time 2253661439 ps
CPU time 17.82 seconds
Started Mar 21 03:10:36 PM PDT 24
Finished Mar 21 03:10:55 PM PDT 24
Peak memory 221112 kb
Host smart-472e2532-0bab-45e0-96bd-058eb7d94e0e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250488834 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.250488834
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.1294273963
Short name T335
Test name
Test status
Simulation time 2568391847 ps
CPU time 5.62 seconds
Started Mar 21 03:10:33 PM PDT 24
Finished Mar 21 03:10:40 PM PDT 24
Peak memory 219280 kb
Host smart-b1b6caab-7799-414c-aa7b-a2d1a4b65da5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294273963 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.1294273963
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.40560458
Short name T310
Test name
Test status
Simulation time 188472809 ps
CPU time 2.25 seconds
Started Mar 21 03:10:34 PM PDT 24
Finished Mar 21 03:10:38 PM PDT 24
Peak memory 218532 kb
Host smart-3b1e6fcf-353d-4f7e-9ef7-d0824306b415
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40560458 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.40560458
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.1211131789
Short name T254
Test name
Test status
Simulation time 238223053 ps
CPU time 1.19 seconds
Started Mar 21 03:10:36 PM PDT 24
Finished Mar 21 03:10:38 PM PDT 24
Peak memory 204672 kb
Host smart-c4d41aee-157c-4fbe-a75e-6b990ed4e84c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211131789 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.1
211131789
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.366640449
Short name T64
Test name
Test status
Simulation time 162605530 ps
CPU time 0.71 seconds
Started Mar 21 03:10:34 PM PDT 24
Finished Mar 21 03:10:37 PM PDT 24
Peak memory 204488 kb
Host smart-ecbd5c62-0026-47b1-81ed-1461ebf75cac
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366640449 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.366640449
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.623892784
Short name T94
Test name
Test status
Simulation time 536275344 ps
CPU time 6.26 seconds
Started Mar 21 03:10:40 PM PDT 24
Finished Mar 21 03:10:47 PM PDT 24
Peak memory 204768 kb
Host smart-2b936cd7-320a-4f56-9c54-7a268011ba6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623892784 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_c
sr_outstanding.623892784
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.2561971412
Short name T141
Test name
Test status
Simulation time 8655623056 ps
CPU time 19.59 seconds
Started Mar 21 03:10:34 PM PDT 24
Finished Mar 21 03:10:56 PM PDT 24
Peak memory 214384 kb
Host smart-182eb37b-45d3-4b8f-8c59-d6cc4f18c4a2
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561971412 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.2561971412
Directory /workspace/9.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.3821749726
Short name T262
Test name
Test status
Simulation time 349536716 ps
CPU time 5.61 seconds
Started Mar 21 03:10:33 PM PDT 24
Finished Mar 21 03:10:41 PM PDT 24
Peak memory 212940 kb
Host smart-38a78223-b427-4719-b1af-441802e8ca70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821749726 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.3821749726
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.3679980622
Short name T270
Test name
Test status
Simulation time 882841954 ps
CPU time 16.4 seconds
Started Mar 21 03:10:33 PM PDT 24
Finished Mar 21 03:10:52 PM PDT 24
Peak memory 213028 kb
Host smart-0fa96f14-0fe3-4e83-82ea-4487a5fe40b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679980622 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.3679980622
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.3765339489
Short name T212
Test name
Test status
Simulation time 50885149 ps
CPU time 0.71 seconds
Started Mar 21 01:32:15 PM PDT 24
Finished Mar 21 01:32:16 PM PDT 24
Peak memory 204804 kb
Host smart-aa1803ce-e428-4045-bca6-89457ed807fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765339489 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.3765339489
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.2948916506
Short name T188
Test name
Test status
Simulation time 2317904867 ps
CPU time 8.09 seconds
Started Mar 21 01:32:16 PM PDT 24
Finished Mar 21 01:32:24 PM PDT 24
Peak memory 205176 kb
Host smart-e7917825-ba39-408f-868e-d5a23ba29682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948916506 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.2948916506
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.3624766873
Short name T150
Test name
Test status
Simulation time 8197821024 ps
CPU time 6.3 seconds
Started Mar 21 01:32:17 PM PDT 24
Finished Mar 21 01:32:24 PM PDT 24
Peak memory 205124 kb
Host smart-d0cecdb3-4a54-4a5d-8d23-dacdf7dc11bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624766873 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.3624766873
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.2517928680
Short name T143
Test name
Test status
Simulation time 6605635533 ps
CPU time 3.99 seconds
Started Mar 21 01:32:16 PM PDT 24
Finished Mar 21 01:32:21 PM PDT 24
Peak memory 205140 kb
Host smart-3813578e-ea1a-4ef1-b4c1-fc1392744c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517928680 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.2517928680
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.1519976811
Short name T6
Test name
Test status
Simulation time 117472875 ps
CPU time 0.76 seconds
Started Mar 21 01:32:16 PM PDT 24
Finished Mar 21 01:32:17 PM PDT 24
Peak memory 204848 kb
Host smart-bbbe19bc-07b4-474a-ada9-4070eebb86bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519976811 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.1519976811
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.2913924735
Short name T204
Test name
Test status
Simulation time 5025432566 ps
CPU time 8.83 seconds
Started Mar 21 01:32:15 PM PDT 24
Finished Mar 21 01:32:24 PM PDT 24
Peak memory 213380 kb
Host smart-1ba1349a-b95c-426c-81e6-1e2e726dbcfb
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2913924735 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t
l_access.2913924735
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.3983840173
Short name T55
Test name
Test status
Simulation time 484132345 ps
CPU time 1.69 seconds
Started Mar 21 01:32:14 PM PDT 24
Finished Mar 21 01:32:15 PM PDT 24
Peak memory 205108 kb
Host smart-58273cbb-d82a-4839-b845-1045210a7820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983840173 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.3983840173
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.3837986649
Short name T232
Test name
Test status
Simulation time 115354127 ps
CPU time 0.82 seconds
Started Mar 21 01:32:18 PM PDT 24
Finished Mar 21 01:32:19 PM PDT 24
Peak memory 204708 kb
Host smart-01de92f7-f4e0-4d07-b7b2-cc1a550a084f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837986649 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.3837986649
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.772429947
Short name T27
Test name
Test status
Simulation time 255373140 ps
CPU time 1.06 seconds
Started Mar 21 01:32:16 PM PDT 24
Finished Mar 21 01:32:18 PM PDT 24
Peak memory 204704 kb
Host smart-7b49c56d-eca7-4980-b0bd-2e74980176d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772429947 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.772429947
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.1665415619
Short name T225
Test name
Test status
Simulation time 202798315 ps
CPU time 0.86 seconds
Started Mar 21 01:32:15 PM PDT 24
Finished Mar 21 01:32:16 PM PDT 24
Peak memory 204740 kb
Host smart-0eb88606-c261-4f6d-884b-39d70d1ee044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665415619 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.1665415619
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.1125741501
Short name T120
Test name
Test status
Simulation time 171726260 ps
CPU time 0.89 seconds
Started Mar 21 01:32:17 PM PDT 24
Finished Mar 21 01:32:18 PM PDT 24
Peak memory 204740 kb
Host smart-ae67986e-6558-4f2b-ba36-93b19ee1f1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125741501 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.1125741501
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.2472754883
Short name T60
Test name
Test status
Simulation time 55551661 ps
CPU time 0.73 seconds
Started Mar 21 01:32:21 PM PDT 24
Finished Mar 21 01:32:22 PM PDT 24
Peak memory 204708 kb
Host smart-7213a4bc-b94a-4d74-9780-15fc0a23b056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472754883 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.2472754883
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.3307340758
Short name T148
Test name
Test status
Simulation time 48781315 ps
CPU time 0.78 seconds
Started Mar 21 01:32:17 PM PDT 24
Finished Mar 21 01:32:18 PM PDT 24
Peak memory 204836 kb
Host smart-a9159b36-6a44-4a51-a6db-0f37f2ea487a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307340758 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.3307340758
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.3889997998
Short name T146
Test name
Test status
Simulation time 362607462 ps
CPU time 1.11 seconds
Started Mar 21 01:32:19 PM PDT 24
Finished Mar 21 01:32:20 PM PDT 24
Peak memory 204944 kb
Host smart-13f7d1c4-6413-465f-a8e1-cbff69da6871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889997998 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.3889997998
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.3168035266
Short name T16
Test name
Test status
Simulation time 550072757 ps
CPU time 0.89 seconds
Started Mar 21 01:32:14 PM PDT 24
Finished Mar 21 01:32:15 PM PDT 24
Peak memory 204812 kb
Host smart-9c5c5872-c334-4ac7-bafd-4684a915778e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168035266 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.3168035266
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.2660831665
Short name T237
Test name
Test status
Simulation time 2038357603 ps
CPU time 6.86 seconds
Started Mar 21 01:32:16 PM PDT 24
Finished Mar 21 01:32:23 PM PDT 24
Peak memory 205144 kb
Host smart-c480f616-69b6-4056-ac8d-565f58472817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660831665 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.2660831665
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.1955087984
Short name T185
Test name
Test status
Simulation time 415913560 ps
CPU time 2.03 seconds
Started Mar 21 01:32:17 PM PDT 24
Finished Mar 21 01:32:20 PM PDT 24
Peak memory 204948 kb
Host smart-fd0778ad-fc21-4030-80f0-e930b7d2243d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955087984 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.1955087984
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.3701736312
Short name T59
Test name
Test status
Simulation time 1636720729 ps
CPU time 5.22 seconds
Started Mar 21 01:32:15 PM PDT 24
Finished Mar 21 01:32:20 PM PDT 24
Peak memory 205056 kb
Host smart-ccaac6c2-ba8b-42e9-9e46-ab0334f1a661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701736312 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.3701736312
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.2488794023
Short name T157
Test name
Test status
Simulation time 36872700 ps
CPU time 0.76 seconds
Started Mar 21 01:32:25 PM PDT 24
Finished Mar 21 01:32:27 PM PDT 24
Peak memory 204892 kb
Host smart-22a1f357-1ea4-466c-bac5-23301ed1fcc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488794023 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.2488794023
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.3449335534
Short name T223
Test name
Test status
Simulation time 1661558208 ps
CPU time 8.5 seconds
Started Mar 21 01:32:19 PM PDT 24
Finished Mar 21 01:32:27 PM PDT 24
Peak memory 213396 kb
Host smart-bb83d3ba-5f8e-4e80-8b51-28bf5dc95391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449335534 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.3449335534
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.245634906
Short name T147
Test name
Test status
Simulation time 2117917174 ps
CPU time 6.92 seconds
Started Mar 21 01:32:18 PM PDT 24
Finished Mar 21 01:32:25 PM PDT 24
Peak memory 205124 kb
Host smart-dbd7ad38-5329-406c-a0dc-2e8b6280869b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245634906 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.245634906
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.2628233668
Short name T11
Test name
Test status
Simulation time 162124530 ps
CPU time 1.23 seconds
Started Mar 21 01:32:17 PM PDT 24
Finished Mar 21 01:32:19 PM PDT 24
Peak memory 204840 kb
Host smart-84718ce2-a074-4a49-953d-03b0ab27b213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628233668 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.2628233668
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.596346320
Short name T51
Test name
Test status
Simulation time 221229828 ps
CPU time 0.86 seconds
Started Mar 21 01:32:18 PM PDT 24
Finished Mar 21 01:32:19 PM PDT 24
Peak memory 204716 kb
Host smart-f83ee644-6bd3-4675-9e43-79622b0ba244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596346320 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.596346320
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.110291365
Short name T20
Test name
Test status
Simulation time 659776044 ps
CPU time 2.88 seconds
Started Mar 21 01:32:20 PM PDT 24
Finished Mar 21 01:32:24 PM PDT 24
Peak memory 205056 kb
Host smart-10b51502-b56b-4450-a5bd-e70e359df41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110291365 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.110291365
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.2676337970
Short name T178
Test name
Test status
Simulation time 52964957 ps
CPU time 0.75 seconds
Started Mar 21 01:32:16 PM PDT 24
Finished Mar 21 01:32:17 PM PDT 24
Peak memory 204860 kb
Host smart-7145c889-a37a-4e4a-b229-187fc9edb86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676337970 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.2676337970
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.3242897076
Short name T213
Test name
Test status
Simulation time 4723928122 ps
CPU time 18.42 seconds
Started Mar 21 01:32:19 PM PDT 24
Finished Mar 21 01:32:37 PM PDT 24
Peak memory 221600 kb
Host smart-ef3c2a17-2843-4ee9-937d-cc48f4070826
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3242897076 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.3242897076
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.1261601836
Short name T145
Test name
Test status
Simulation time 810513706 ps
CPU time 1.59 seconds
Started Mar 21 01:32:19 PM PDT 24
Finished Mar 21 01:32:21 PM PDT 24
Peak memory 205104 kb
Host smart-a0fc4549-9bd8-4a31-9fe5-576ec690e77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261601836 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.1261601836
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.129709909
Short name T200
Test name
Test status
Simulation time 40769379 ps
CPU time 0.74 seconds
Started Mar 21 01:32:16 PM PDT 24
Finished Mar 21 01:32:17 PM PDT 24
Peak memory 204712 kb
Host smart-33bfddf6-9658-4e71-bd85-e03f2ce927ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129709909 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.129709909
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.4222736777
Short name T3
Test name
Test status
Simulation time 119254576 ps
CPU time 0.85 seconds
Started Mar 21 01:32:31 PM PDT 24
Finished Mar 21 01:32:32 PM PDT 24
Peak memory 204632 kb
Host smart-4fdae110-6317-4a61-8937-e16597bcc140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222736777 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.4222736777
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.3884259930
Short name T121
Test name
Test status
Simulation time 563399624 ps
CPU time 1.29 seconds
Started Mar 21 01:32:23 PM PDT 24
Finished Mar 21 01:32:26 PM PDT 24
Peak memory 204908 kb
Host smart-26d28312-e484-4128-b448-33965e8e28d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884259930 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.3884259930
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.69836020
Short name T230
Test name
Test status
Simulation time 75872175 ps
CPU time 0.7 seconds
Started Mar 21 01:32:16 PM PDT 24
Finished Mar 21 01:32:18 PM PDT 24
Peak memory 204616 kb
Host smart-bfdb0d1f-6223-4150-b9fa-fb23187db217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69836020 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.69836020
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.4106858435
Short name T149
Test name
Test status
Simulation time 91831079 ps
CPU time 0.74 seconds
Started Mar 21 01:32:18 PM PDT 24
Finished Mar 21 01:32:19 PM PDT 24
Peak memory 204844 kb
Host smart-d563f1e6-29ed-432c-9841-6b51ca564fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106858435 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.4106858435
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.1341171516
Short name T14
Test name
Test status
Simulation time 268760858 ps
CPU time 1.54 seconds
Started Mar 21 01:32:18 PM PDT 24
Finished Mar 21 01:32:19 PM PDT 24
Peak memory 204856 kb
Host smart-26b3d8fc-bdab-4a59-9ed0-74785c65e8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341171516 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.1341171516
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.2938274419
Short name T75
Test name
Test status
Simulation time 388761603 ps
CPU time 1.94 seconds
Started Mar 21 01:32:16 PM PDT 24
Finished Mar 21 01:32:19 PM PDT 24
Peak memory 205100 kb
Host smart-a16a6b67-3784-4318-9584-38a2d0c6f275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938274419 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.2938274419
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.2334272046
Short name T58
Test name
Test status
Simulation time 54117995 ps
CPU time 0.88 seconds
Started Mar 21 01:32:31 PM PDT 24
Finished Mar 21 01:32:32 PM PDT 24
Peak memory 204768 kb
Host smart-0bda2784-ac9f-49ec-9ff4-34566c397fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334272046 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.2334272046
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.63713306
Short name T54
Test name
Test status
Simulation time 69743169 ps
CPU time 0.86 seconds
Started Mar 21 01:32:26 PM PDT 24
Finished Mar 21 01:32:29 PM PDT 24
Peak memory 213116 kb
Host smart-ed8834fc-614c-4c31-9a7c-f808b8cdde4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63713306 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.63713306
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.2500121699
Short name T10
Test name
Test status
Simulation time 823942456 ps
CPU time 1.38 seconds
Started Mar 21 01:32:18 PM PDT 24
Finished Mar 21 01:32:19 PM PDT 24
Peak memory 205164 kb
Host smart-0104ca4d-b88f-4cf6-a3e3-76e5e54a12b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500121699 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.2500121699
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.3614096850
Short name T21
Test name
Test status
Simulation time 170771906 ps
CPU time 1.54 seconds
Started Mar 21 01:32:23 PM PDT 24
Finished Mar 21 01:32:26 PM PDT 24
Peak memory 229076 kb
Host smart-fe309915-a27f-47d7-925b-8fdbe45370f2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614096850 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.3614096850
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.73887050
Short name T233
Test name
Test status
Simulation time 822520794 ps
CPU time 2.6 seconds
Started Mar 21 01:32:17 PM PDT 24
Finished Mar 21 01:32:20 PM PDT 24
Peak memory 204908 kb
Host smart-dd9c29ca-33bb-438f-949f-02d26564378a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73887050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.73887050
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.1034000279
Short name T217
Test name
Test status
Simulation time 141747186 ps
CPU time 0.7 seconds
Started Mar 21 01:32:37 PM PDT 24
Finished Mar 21 01:32:38 PM PDT 24
Peak memory 204868 kb
Host smart-d5958942-e7fe-4286-b2ea-5e0579049ab9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034000279 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.1034000279
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.2803566057
Short name T227
Test name
Test status
Simulation time 14781968215 ps
CPU time 59.17 seconds
Started Mar 21 01:32:32 PM PDT 24
Finished Mar 21 01:33:32 PM PDT 24
Peak memory 213416 kb
Host smart-0234c4e3-5bc1-4a89-a9df-f2312223cb17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803566057 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.2803566057
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.1206787166
Short name T194
Test name
Test status
Simulation time 2352157424 ps
CPU time 6.02 seconds
Started Mar 21 01:32:33 PM PDT 24
Finished Mar 21 01:32:39 PM PDT 24
Peak memory 205232 kb
Host smart-9c4cf2ba-7eb6-4cb1-aa60-7568218c7c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206787166 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.1206787166
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.2833241461
Short name T243
Test name
Test status
Simulation time 1861842848 ps
CPU time 4.44 seconds
Started Mar 21 01:32:32 PM PDT 24
Finished Mar 21 01:32:37 PM PDT 24
Peak memory 205120 kb
Host smart-44b1044e-cc22-40df-9144-4b5417941f4a
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2833241461 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.2833241461
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.3836536707
Short name T193
Test name
Test status
Simulation time 2861649956 ps
CPU time 7.55 seconds
Started Mar 21 01:32:34 PM PDT 24
Finished Mar 21 01:32:42 PM PDT 24
Peak memory 205296 kb
Host smart-738df3a5-6ec5-4811-9e46-433b35d670ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836536707 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.3836536707
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.25061095
Short name T196
Test name
Test status
Simulation time 38609412 ps
CPU time 0.71 seconds
Started Mar 21 01:32:32 PM PDT 24
Finished Mar 21 01:32:33 PM PDT 24
Peak memory 204880 kb
Host smart-c63ef8e4-a76f-48bc-8d48-21392e7efa39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25061095 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.25061095
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.2983648896
Short name T216
Test name
Test status
Simulation time 1384253452 ps
CPU time 5.62 seconds
Started Mar 21 01:32:31 PM PDT 24
Finished Mar 21 01:32:37 PM PDT 24
Peak memory 213324 kb
Host smart-68e22272-1e69-48e7-96fb-998702377464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983648896 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.2983648896
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.3105363999
Short name T219
Test name
Test status
Simulation time 2965998251 ps
CPU time 8.82 seconds
Started Mar 21 01:32:36 PM PDT 24
Finished Mar 21 01:32:45 PM PDT 24
Peak memory 205264 kb
Host smart-c7d44f11-486c-456b-b3e0-80990dabadcc
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3105363999 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_
tl_access.3105363999
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.2600712708
Short name T206
Test name
Test status
Simulation time 256482432 ps
CPU time 2 seconds
Started Mar 21 01:32:36 PM PDT 24
Finished Mar 21 01:32:38 PM PDT 24
Peak memory 205180 kb
Host smart-b6f5870a-1adc-46c4-89f3-a174702cee00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600712708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.2600712708
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.1694270047
Short name T238
Test name
Test status
Simulation time 139374670 ps
CPU time 0.77 seconds
Started Mar 21 01:32:38 PM PDT 24
Finished Mar 21 01:32:39 PM PDT 24
Peak memory 204692 kb
Host smart-81fb30f8-a9ae-4a12-a70e-6c04b49685ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694270047 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.1694270047
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.3062357141
Short name T244
Test name
Test status
Simulation time 10003924504 ps
CPU time 21.01 seconds
Started Mar 21 01:32:33 PM PDT 24
Finished Mar 21 01:32:54 PM PDT 24
Peak memory 215520 kb
Host smart-1ffd8e19-fe55-4cef-885f-79cb5d40258e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062357141 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.3062357141
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.4280549109
Short name T229
Test name
Test status
Simulation time 3235307356 ps
CPU time 11.74 seconds
Started Mar 21 01:32:34 PM PDT 24
Finished Mar 21 01:32:46 PM PDT 24
Peak memory 205228 kb
Host smart-b0204c11-6a15-4c30-a0da-8308e5ff6725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280549109 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.4280549109
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.250965837
Short name T240
Test name
Test status
Simulation time 15503266792 ps
CPU time 21.59 seconds
Started Mar 21 01:32:34 PM PDT 24
Finished Mar 21 01:32:56 PM PDT 24
Peak memory 213444 kb
Host smart-9494900c-79cc-4f9e-978a-fb0a692effb7
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=250965837 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_t
l_access.250965837
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.3576115157
Short name T224
Test name
Test status
Simulation time 539745132 ps
CPU time 1.3 seconds
Started Mar 21 01:32:32 PM PDT 24
Finished Mar 21 01:32:33 PM PDT 24
Peak memory 205208 kb
Host smart-15cb66b2-1ee3-45dc-ad28-c8bb2764f320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576115157 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.3576115157
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.3381306483
Short name T176
Test name
Test status
Simulation time 37289219 ps
CPU time 0.7 seconds
Started Mar 21 01:32:35 PM PDT 24
Finished Mar 21 01:32:36 PM PDT 24
Peak memory 204784 kb
Host smart-94bdfa1d-c96b-46c5-9533-edddb8b85a6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381306483 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.3381306483
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.1106408090
Short name T184
Test name
Test status
Simulation time 6641777209 ps
CPU time 21.99 seconds
Started Mar 21 01:32:34 PM PDT 24
Finished Mar 21 01:32:56 PM PDT 24
Peak memory 214568 kb
Host smart-b0f93a27-8b57-4887-9a9e-2769de3f8525
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1106408090 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_
tl_access.1106408090
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.2663604050
Short name T192
Test name
Test status
Simulation time 4401527559 ps
CPU time 7.03 seconds
Started Mar 21 01:32:32 PM PDT 24
Finished Mar 21 01:32:39 PM PDT 24
Peak memory 213404 kb
Host smart-5819e270-3763-4915-8c86-80bdfd8119f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663604050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.2663604050
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_stress_all.4039670998
Short name T15
Test name
Test status
Simulation time 1796279778 ps
CPU time 6.58 seconds
Started Mar 21 01:32:33 PM PDT 24
Finished Mar 21 01:32:40 PM PDT 24
Peak memory 205060 kb
Host smart-92a03b08-90f0-4da1-b0ba-222c89e7a1ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039670998 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.4039670998
Directory /workspace/13.rv_dm_stress_all/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.692417636
Short name T202
Test name
Test status
Simulation time 17988933 ps
CPU time 0.73 seconds
Started Mar 21 01:32:35 PM PDT 24
Finished Mar 21 01:32:36 PM PDT 24
Peak memory 204876 kb
Host smart-67bba1b2-9c17-40e1-afff-0e4bd69938ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692417636 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.692417636
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.3898640179
Short name T13
Test name
Test status
Simulation time 7637542631 ps
CPU time 24.85 seconds
Started Mar 21 01:32:36 PM PDT 24
Finished Mar 21 01:33:01 PM PDT 24
Peak memory 213452 kb
Host smart-4b8a1509-b060-4e67-a635-29fa4deaa909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898640179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.3898640179
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.2482810474
Short name T207
Test name
Test status
Simulation time 696793994 ps
CPU time 2.29 seconds
Started Mar 21 01:32:30 PM PDT 24
Finished Mar 21 01:32:32 PM PDT 24
Peak memory 205108 kb
Host smart-e5476f69-8636-4dee-891e-425d7f29e4c3
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2482810474 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.2482810474
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.1567810327
Short name T187
Test name
Test status
Simulation time 6963530744 ps
CPU time 27.43 seconds
Started Mar 21 01:32:33 PM PDT 24
Finished Mar 21 01:33:01 PM PDT 24
Peak memory 213420 kb
Host smart-495dcb5f-e3bc-4c34-bb04-2ccb931e73ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567810327 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.1567810327
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.917219415
Short name T208
Test name
Test status
Simulation time 7660705992 ps
CPU time 35.89 seconds
Started Mar 21 01:32:35 PM PDT 24
Finished Mar 21 01:33:11 PM PDT 24
Peak memory 213456 kb
Host smart-31dbbf18-7a1b-459d-8758-f762f8717d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917219415 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.917219415
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.2177268478
Short name T195
Test name
Test status
Simulation time 1904648470 ps
CPU time 5.16 seconds
Started Mar 21 01:32:37 PM PDT 24
Finished Mar 21 01:32:43 PM PDT 24
Peak memory 205164 kb
Host smart-d9178ec0-7358-42a1-80e9-1c713a0b3462
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2177268478 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_
tl_access.2177268478
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.3589198395
Short name T242
Test name
Test status
Simulation time 1171105123 ps
CPU time 3.14 seconds
Started Mar 21 01:32:35 PM PDT 24
Finished Mar 21 01:32:38 PM PDT 24
Peak memory 205160 kb
Host smart-56d4a5d1-a7f2-4a3b-99f6-1bbdaa38ce79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589198395 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.3589198395
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.368621954
Short name T47
Test name
Test status
Simulation time 17076066 ps
CPU time 0.72 seconds
Started Mar 21 01:32:41 PM PDT 24
Finished Mar 21 01:32:42 PM PDT 24
Peak memory 204888 kb
Host smart-21ec7e6e-e008-4615-be41-c7b01cf51783
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368621954 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.368621954
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.3517360034
Short name T9
Test name
Test status
Simulation time 2133392712 ps
CPU time 3.55 seconds
Started Mar 21 01:32:51 PM PDT 24
Finished Mar 21 01:32:55 PM PDT 24
Peak memory 205160 kb
Host smart-ba76dc37-0034-460e-8500-0be18b0efe46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517360034 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.3517360034
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.2053807368
Short name T181
Test name
Test status
Simulation time 1309835769 ps
CPU time 6.45 seconds
Started Mar 21 01:32:39 PM PDT 24
Finished Mar 21 01:32:46 PM PDT 24
Peak memory 205196 kb
Host smart-f311833b-62b1-4110-8076-b0c3f139a8b6
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2053807368 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_
tl_access.2053807368
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.3632829013
Short name T86
Test name
Test status
Simulation time 1598583878 ps
CPU time 6.7 seconds
Started Mar 21 01:32:39 PM PDT 24
Finished Mar 21 01:32:46 PM PDT 24
Peak memory 205248 kb
Host smart-0a5cfb21-9526-4c2e-858a-60357c60a2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632829013 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.3632829013
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.987328033
Short name T172
Test name
Test status
Simulation time 19741691 ps
CPU time 0.71 seconds
Started Mar 21 01:32:43 PM PDT 24
Finished Mar 21 01:32:43 PM PDT 24
Peak memory 204884 kb
Host smart-7975191c-50ba-443c-bd5e-710f7d0fbf3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987328033 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.987328033
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.1734537687
Short name T209
Test name
Test status
Simulation time 1276226349 ps
CPU time 2.58 seconds
Started Mar 21 01:32:41 PM PDT 24
Finished Mar 21 01:32:44 PM PDT 24
Peak memory 205216 kb
Host smart-d14a364b-7d80-4557-9dca-1d21b548cf9e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1734537687 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_
tl_access.1734537687
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.3534175469
Short name T40
Test name
Test status
Simulation time 7182536681 ps
CPU time 27.27 seconds
Started Mar 21 01:32:45 PM PDT 24
Finished Mar 21 01:33:13 PM PDT 24
Peak memory 213464 kb
Host smart-89b46a47-e299-4da2-afef-a829e8821fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534175469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.3534175469
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_stress_all.2761315470
Short name T56
Test name
Test status
Simulation time 1942556333 ps
CPU time 6.95 seconds
Started Mar 21 01:32:42 PM PDT 24
Finished Mar 21 01:32:49 PM PDT 24
Peak memory 205076 kb
Host smart-01876bb2-b6c3-4af3-9460-2e36eed2de08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761315470 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.2761315470
Directory /workspace/17.rv_dm_stress_all/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.622668117
Short name T117
Test name
Test status
Simulation time 15074800 ps
CPU time 0.73 seconds
Started Mar 21 01:32:42 PM PDT 24
Finished Mar 21 01:32:43 PM PDT 24
Peak memory 204880 kb
Host smart-8e819727-7dd8-4032-a6ec-a5c9c4672fbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622668117 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.622668117
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.755227090
Short name T182
Test name
Test status
Simulation time 452893440 ps
CPU time 2.92 seconds
Started Mar 21 01:32:43 PM PDT 24
Finished Mar 21 01:32:46 PM PDT 24
Peak memory 205120 kb
Host smart-ea9d77cd-e517-4b05-a2fa-43efdb7cf6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755227090 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.755227090
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.2057746617
Short name T183
Test name
Test status
Simulation time 1564651291 ps
CPU time 3.67 seconds
Started Mar 21 01:32:41 PM PDT 24
Finished Mar 21 01:32:45 PM PDT 24
Peak memory 205104 kb
Host smart-d130ac91-dd6b-4c11-b94d-ee6f5a8207c8
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2057746617 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_
tl_access.2057746617
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.149744155
Short name T222
Test name
Test status
Simulation time 2665418745 ps
CPU time 6.72 seconds
Started Mar 21 01:32:45 PM PDT 24
Finished Mar 21 01:32:51 PM PDT 24
Peak memory 205236 kb
Host smart-64c1be3b-e962-456b-8518-0e7a93cf8cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149744155 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.149744155
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.2040982559
Short name T205
Test name
Test status
Simulation time 61640147 ps
CPU time 0.72 seconds
Started Mar 21 01:32:44 PM PDT 24
Finished Mar 21 01:32:45 PM PDT 24
Peak memory 204876 kb
Host smart-23f08cb6-b55a-4685-a3d2-608fcf0ddccb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040982559 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.2040982559
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.1545406868
Short name T19
Test name
Test status
Simulation time 11338407349 ps
CPU time 12.03 seconds
Started Mar 21 01:32:42 PM PDT 24
Finished Mar 21 01:32:55 PM PDT 24
Peak memory 205212 kb
Host smart-f1a921a1-2932-423a-a21c-47124a8aa115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545406868 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.1545406868
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.2996712435
Short name T235
Test name
Test status
Simulation time 7193151748 ps
CPU time 28.73 seconds
Started Mar 21 01:32:42 PM PDT 24
Finished Mar 21 01:33:11 PM PDT 24
Peak memory 213376 kb
Host smart-533f6c1b-28dd-4743-a522-cb9263f5e954
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2996712435 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_
tl_access.2996712435
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.2518253246
Short name T167
Test name
Test status
Simulation time 54964683 ps
CPU time 0.73 seconds
Started Mar 21 01:32:25 PM PDT 24
Finished Mar 21 01:32:27 PM PDT 24
Peak memory 204892 kb
Host smart-d78fa4cc-9520-4856-8696-63cf95fdd51f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518253246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.2518253246
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.3668387237
Short name T236
Test name
Test status
Simulation time 3176703355 ps
CPU time 12.64 seconds
Started Mar 21 01:32:24 PM PDT 24
Finished Mar 21 01:32:38 PM PDT 24
Peak memory 215280 kb
Host smart-56246687-b14b-4c65-9492-d96ade990951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668387237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.3668387237
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.677335645
Short name T201
Test name
Test status
Simulation time 1924920151 ps
CPU time 4.59 seconds
Started Mar 21 01:32:30 PM PDT 24
Finished Mar 21 01:32:35 PM PDT 24
Peak memory 205196 kb
Host smart-f2f6e476-d813-41eb-8ec2-a5da4047a74d
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=677335645 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_tl
_access.677335645
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.1717301218
Short name T239
Test name
Test status
Simulation time 30511867 ps
CPU time 0.72 seconds
Started Mar 21 01:32:24 PM PDT 24
Finished Mar 21 01:32:26 PM PDT 24
Peak memory 204620 kb
Host smart-b580c589-2220-4311-b63e-a598ee645d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717301218 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.1717301218
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.3846332243
Short name T199
Test name
Test status
Simulation time 3215305662 ps
CPU time 4.27 seconds
Started Mar 21 01:32:25 PM PDT 24
Finished Mar 21 01:32:31 PM PDT 24
Peak memory 205252 kb
Host smart-cda671cf-6b02-40b4-b7fa-c593c103b0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846332243 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.3846332243
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.1864983094
Short name T23
Test name
Test status
Simulation time 136835167 ps
CPU time 1.05 seconds
Started Mar 21 01:32:28 PM PDT 24
Finished Mar 21 01:32:30 PM PDT 24
Peak memory 229080 kb
Host smart-c95b2fa6-386a-4c91-903c-cebe85f4fa54
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864983094 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.1864983094
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.1147547639
Short name T70
Test name
Test status
Simulation time 22024838 ps
CPU time 0.71 seconds
Started Mar 21 01:32:45 PM PDT 24
Finished Mar 21 01:32:46 PM PDT 24
Peak memory 204884 kb
Host smart-4432fbce-54f9-4d36-a3b5-43c91a706c54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147547639 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.1147547639
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.4271143537
Short name T30
Test name
Test status
Simulation time 19184225 ps
CPU time 0.75 seconds
Started Mar 21 01:32:41 PM PDT 24
Finished Mar 21 01:32:42 PM PDT 24
Peak memory 204864 kb
Host smart-a5da848f-e6c6-4ed9-a212-57f24f73faf1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271143537 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.4271143537
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_stress_all.1378421565
Short name T62
Test name
Test status
Simulation time 1588505582 ps
CPU time 6.49 seconds
Started Mar 21 01:32:45 PM PDT 24
Finished Mar 21 01:32:51 PM PDT 24
Peak memory 205056 kb
Host smart-759ff852-1628-4a5b-ae9a-2a6e7494d8ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378421565 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.1378421565
Directory /workspace/21.rv_dm_stress_all/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.2473080421
Short name T166
Test name
Test status
Simulation time 17057283 ps
CPU time 0.69 seconds
Started Mar 21 01:32:44 PM PDT 24
Finished Mar 21 01:32:45 PM PDT 24
Peak memory 204844 kb
Host smart-94c09bed-625d-4338-a2cd-82f7fd4cd605
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473080421 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.2473080421
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.3518558664
Short name T160
Test name
Test status
Simulation time 57784261 ps
CPU time 0.75 seconds
Started Mar 21 01:32:47 PM PDT 24
Finished Mar 21 01:32:48 PM PDT 24
Peak memory 204896 kb
Host smart-c9347bd3-d52c-461c-97c1-87871a4bdfcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518558664 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.3518558664
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.210491458
Short name T67
Test name
Test status
Simulation time 64880144 ps
CPU time 0.74 seconds
Started Mar 21 01:32:44 PM PDT 24
Finished Mar 21 01:32:45 PM PDT 24
Peak memory 204864 kb
Host smart-282c3511-1b04-4793-83b5-f3495ea7c19f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210491458 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.210491458
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.200031757
Short name T203
Test name
Test status
Simulation time 43865076 ps
CPU time 0.72 seconds
Started Mar 21 01:32:47 PM PDT 24
Finished Mar 21 01:32:48 PM PDT 24
Peak memory 204876 kb
Host smart-92ac1449-d85f-4f43-8f14-7b9dbe6cfb04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200031757 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.200031757
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.940684754
Short name T44
Test name
Test status
Simulation time 117751159 ps
CPU time 0.77 seconds
Started Mar 21 01:32:58 PM PDT 24
Finished Mar 21 01:32:59 PM PDT 24
Peak memory 204844 kb
Host smart-d81c388e-7096-4d1e-9f8a-7e88ee9a2f79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940684754 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.940684754
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_stress_all.605116949
Short name T7
Test name
Test status
Simulation time 4042557246 ps
CPU time 8.09 seconds
Started Mar 21 01:32:44 PM PDT 24
Finished Mar 21 01:32:52 PM PDT 24
Peak memory 205096 kb
Host smart-44e68f65-872b-4cff-bbb6-54ebe7c77f58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605116949 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.605116949
Directory /workspace/27.rv_dm_stress_all/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.3921939829
Short name T165
Test name
Test status
Simulation time 27270488 ps
CPU time 0.74 seconds
Started Mar 21 01:32:54 PM PDT 24
Finished Mar 21 01:32:54 PM PDT 24
Peak memory 204876 kb
Host smart-011752e5-f82e-43ad-90ae-1a75d6969b92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921939829 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.3921939829
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.3752051882
Short name T168
Test name
Test status
Simulation time 18785576 ps
CPU time 0.71 seconds
Started Mar 21 01:32:55 PM PDT 24
Finished Mar 21 01:32:56 PM PDT 24
Peak memory 204868 kb
Host smart-8e2ceffe-821e-4abb-9725-b256df0a9820
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752051882 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.3752051882
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.3325116405
Short name T151
Test name
Test status
Simulation time 50223842 ps
CPU time 0.75 seconds
Started Mar 21 01:32:25 PM PDT 24
Finished Mar 21 01:32:27 PM PDT 24
Peak memory 204868 kb
Host smart-1e5b215d-697a-43f2-bf59-c881171d45dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325116405 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.3325116405
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.943485235
Short name T241
Test name
Test status
Simulation time 12649792225 ps
CPU time 49.79 seconds
Started Mar 21 01:32:24 PM PDT 24
Finished Mar 21 01:33:15 PM PDT 24
Peak memory 213472 kb
Host smart-95acbcb2-51f3-43c0-bd93-55c2dfababaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943485235 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.943485235
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.3351936694
Short name T214
Test name
Test status
Simulation time 835738792 ps
CPU time 1.64 seconds
Started Mar 21 01:32:27 PM PDT 24
Finished Mar 21 01:32:30 PM PDT 24
Peak memory 205192 kb
Host smart-33fdd2ff-7af6-44b7-9682-946cea75fa93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351936694 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.3351936694
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.2618874124
Short name T180
Test name
Test status
Simulation time 615567078 ps
CPU time 1.18 seconds
Started Mar 21 01:32:25 PM PDT 24
Finished Mar 21 01:32:27 PM PDT 24
Peak memory 205208 kb
Host smart-4a384496-5bf9-47de-a8ac-31e33b8a4b5b
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2618874124 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.2618874124
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.805301483
Short name T228
Test name
Test status
Simulation time 77365685 ps
CPU time 0.71 seconds
Started Mar 21 01:32:24 PM PDT 24
Finished Mar 21 01:32:26 PM PDT 24
Peak memory 204716 kb
Host smart-3d213d2c-b20e-4d51-965f-86ef9fa49b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805301483 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.805301483
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.2628277438
Short name T87
Test name
Test status
Simulation time 733736819 ps
CPU time 4.28 seconds
Started Mar 21 01:32:25 PM PDT 24
Finished Mar 21 01:32:31 PM PDT 24
Peak memory 205192 kb
Host smart-426a8444-948e-4503-acbf-6c53bd8360bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628277438 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.2628277438
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.4002532375
Short name T43
Test name
Test status
Simulation time 186493694 ps
CPU time 1.27 seconds
Started Mar 21 01:32:22 PM PDT 24
Finished Mar 21 01:32:26 PM PDT 24
Peak memory 229024 kb
Host smart-4bb0aaad-c419-40c2-b453-497bb33117de
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002532375 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.4002532375
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.2016197279
Short name T174
Test name
Test status
Simulation time 18405826 ps
CPU time 0.73 seconds
Started Mar 21 01:32:52 PM PDT 24
Finished Mar 21 01:32:53 PM PDT 24
Peak memory 204812 kb
Host smart-f944af85-d9a2-4ae2-b368-dc3cb4af93ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016197279 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.2016197279
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.3540909924
Short name T116
Test name
Test status
Simulation time 28979057 ps
CPU time 0.7 seconds
Started Mar 21 01:32:55 PM PDT 24
Finished Mar 21 01:32:56 PM PDT 24
Peak memory 204820 kb
Host smart-458ef1d2-e8bf-4b74-b5e3-7283f9c6c490
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540909924 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.3540909924
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.3207160583
Short name T161
Test name
Test status
Simulation time 26010302 ps
CPU time 0.72 seconds
Started Mar 21 01:32:54 PM PDT 24
Finished Mar 21 01:32:55 PM PDT 24
Peak memory 204952 kb
Host smart-577ae649-1590-4885-8b1e-73fa9aa25f4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207160583 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.3207160583
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.492126136
Short name T49
Test name
Test status
Simulation time 51927460 ps
CPU time 0.73 seconds
Started Mar 21 01:32:51 PM PDT 24
Finished Mar 21 01:32:52 PM PDT 24
Peak memory 204860 kb
Host smart-040064d1-bf7d-426c-83f7-2a5b059f3624
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492126136 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.492126136
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.1104574664
Short name T68
Test name
Test status
Simulation time 19794092 ps
CPU time 0.75 seconds
Started Mar 21 01:32:52 PM PDT 24
Finished Mar 21 01:32:53 PM PDT 24
Peak memory 204868 kb
Host smart-eb494671-d6cb-4338-b482-607fcef62466
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104574664 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.1104574664
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.1894834484
Short name T39
Test name
Test status
Simulation time 31110385 ps
CPU time 0.71 seconds
Started Mar 21 01:32:53 PM PDT 24
Finished Mar 21 01:32:54 PM PDT 24
Peak memory 204848 kb
Host smart-cac616d2-e0aa-4eda-b065-b256c1f85846
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894834484 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.1894834484
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.3831915204
Short name T170
Test name
Test status
Simulation time 55791715 ps
CPU time 0.73 seconds
Started Mar 21 01:32:55 PM PDT 24
Finished Mar 21 01:32:56 PM PDT 24
Peak memory 204868 kb
Host smart-ee490493-6d17-426e-a8c2-81ae0ce69ded
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831915204 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.3831915204
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.4270791571
Short name T48
Test name
Test status
Simulation time 23821171 ps
CPU time 0.73 seconds
Started Mar 21 01:32:54 PM PDT 24
Finished Mar 21 01:32:54 PM PDT 24
Peak memory 204768 kb
Host smart-48d2df3d-33b2-4377-82e6-f8a688473772
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270791571 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.4270791571
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.3984894499
Short name T159
Test name
Test status
Simulation time 35805129 ps
CPU time 0.73 seconds
Started Mar 21 01:32:56 PM PDT 24
Finished Mar 21 01:32:57 PM PDT 24
Peak memory 204868 kb
Host smart-c5b7038e-26cf-46c4-b27b-e261a09c750e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984894499 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.3984894499
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.719818669
Short name T155
Test name
Test status
Simulation time 22099134 ps
CPU time 0.77 seconds
Started Mar 21 01:32:54 PM PDT 24
Finished Mar 21 01:32:55 PM PDT 24
Peak memory 204896 kb
Host smart-28439f7b-b205-4ef6-aff3-930660dd7d43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719818669 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.719818669
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.1345576855
Short name T156
Test name
Test status
Simulation time 18917559 ps
CPU time 0.73 seconds
Started Mar 21 01:32:25 PM PDT 24
Finished Mar 21 01:32:27 PM PDT 24
Peak memory 204864 kb
Host smart-48ceb821-fac2-4012-9f75-51050f31194a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345576855 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.1345576855
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.3981238262
Short name T45
Test name
Test status
Simulation time 17516853109 ps
CPU time 24.68 seconds
Started Mar 21 01:32:27 PM PDT 24
Finished Mar 21 01:32:53 PM PDT 24
Peak memory 213428 kb
Host smart-e811ec2a-97d6-4088-b578-cfdad2a4b866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981238262 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.3981238262
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.3426388269
Short name T191
Test name
Test status
Simulation time 4153799537 ps
CPU time 14.19 seconds
Started Mar 21 01:32:24 PM PDT 24
Finished Mar 21 01:32:40 PM PDT 24
Peak memory 213408 kb
Host smart-11ee9fa5-0a0f-494e-9eba-19b1cabe83cb
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3426388269 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.3426388269
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.3758561074
Short name T179
Test name
Test status
Simulation time 152588179 ps
CPU time 0.84 seconds
Started Mar 21 01:32:27 PM PDT 24
Finished Mar 21 01:32:29 PM PDT 24
Peak memory 204728 kb
Host smart-1a405b99-0dbd-4b1e-a8d2-7dc38ca69bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758561074 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.3758561074
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.1873153317
Short name T234
Test name
Test status
Simulation time 1405061889 ps
CPU time 4.78 seconds
Started Mar 21 01:32:27 PM PDT 24
Finished Mar 21 01:32:33 PM PDT 24
Peak memory 205192 kb
Host smart-09d5db32-1bb6-4833-9ebe-1cfca8caa7b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873153317 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.1873153317
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.1002219402
Short name T22
Test name
Test status
Simulation time 391521872 ps
CPU time 1.05 seconds
Started Mar 21 01:32:25 PM PDT 24
Finished Mar 21 01:32:27 PM PDT 24
Peak memory 228368 kb
Host smart-b54176ab-1e7d-4cf4-9dd2-d2c2fe48a528
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002219402 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.1002219402
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.1550081190
Short name T177
Test name
Test status
Simulation time 37703757 ps
CPU time 0.72 seconds
Started Mar 21 01:32:53 PM PDT 24
Finished Mar 21 01:32:54 PM PDT 24
Peak memory 204868 kb
Host smart-95009fc4-0143-4a8c-a13e-4589c35b06a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550081190 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.1550081190
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.2652272826
Short name T175
Test name
Test status
Simulation time 50569298 ps
CPU time 0.7 seconds
Started Mar 21 01:32:58 PM PDT 24
Finished Mar 21 01:32:59 PM PDT 24
Peak memory 204868 kb
Host smart-ce9d3e02-3cb2-46d6-87b9-f7c35f3accd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652272826 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.2652272826
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.598580295
Short name T162
Test name
Test status
Simulation time 26593261 ps
CPU time 0.71 seconds
Started Mar 21 01:32:55 PM PDT 24
Finished Mar 21 01:32:56 PM PDT 24
Peak memory 204860 kb
Host smart-463f947c-cce6-4094-83f2-0563d09c354e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598580295 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.598580295
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.3680694435
Short name T164
Test name
Test status
Simulation time 60749992 ps
CPU time 0.73 seconds
Started Mar 21 01:33:01 PM PDT 24
Finished Mar 21 01:33:01 PM PDT 24
Peak memory 204880 kb
Host smart-b74d1fad-3a53-4ec9-adb0-482512566312
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680694435 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.3680694435
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.1758090663
Short name T123
Test name
Test status
Simulation time 28001370 ps
CPU time 0.77 seconds
Started Mar 21 01:33:05 PM PDT 24
Finished Mar 21 01:33:06 PM PDT 24
Peak memory 204916 kb
Host smart-5ffa3af0-c552-4aca-b2bb-805f0174deb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758090663 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.1758090663
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_stress_all.142596685
Short name T142
Test name
Test status
Simulation time 5629083755 ps
CPU time 5.81 seconds
Started Mar 21 01:33:03 PM PDT 24
Finished Mar 21 01:33:09 PM PDT 24
Peak memory 205184 kb
Host smart-7184928a-3960-4f1e-adaf-50589cbc5520
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142596685 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.142596685
Directory /workspace/44.rv_dm_stress_all/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.935736981
Short name T26
Test name
Test status
Simulation time 31519262 ps
CPU time 0.7 seconds
Started Mar 21 01:33:08 PM PDT 24
Finished Mar 21 01:33:08 PM PDT 24
Peak memory 204844 kb
Host smart-c2e99858-b939-4c1d-ab1b-1ca236735d8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935736981 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.935736981
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_stress_all.358960882
Short name T29
Test name
Test status
Simulation time 3140152216 ps
CPU time 10.08 seconds
Started Mar 21 01:33:06 PM PDT 24
Finished Mar 21 01:33:16 PM PDT 24
Peak memory 205184 kb
Host smart-fb24543e-0ba5-43ef-823a-7ae282c17501
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358960882 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.358960882
Directory /workspace/45.rv_dm_stress_all/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.956701166
Short name T153
Test name
Test status
Simulation time 43742185 ps
CPU time 0.81 seconds
Started Mar 21 01:33:03 PM PDT 24
Finished Mar 21 01:33:04 PM PDT 24
Peak memory 204796 kb
Host smart-198a47d8-6fa4-4f9b-83d8-85b4ab3b9602
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956701166 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.956701166
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_stress_all.3258257190
Short name T144
Test name
Test status
Simulation time 4278953942 ps
CPU time 13.99 seconds
Started Mar 21 01:33:03 PM PDT 24
Finished Mar 21 01:33:17 PM PDT 24
Peak memory 205032 kb
Host smart-b450af6d-fe94-47a2-841b-39292e83676d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258257190 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.3258257190
Directory /workspace/46.rv_dm_stress_all/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.3333686746
Short name T171
Test name
Test status
Simulation time 24879393 ps
CPU time 0.74 seconds
Started Mar 21 01:33:07 PM PDT 24
Finished Mar 21 01:33:07 PM PDT 24
Peak memory 204868 kb
Host smart-41c06a79-6eb5-4efe-89fa-f1fa0ef3f699
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333686746 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.3333686746
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.1979073107
Short name T169
Test name
Test status
Simulation time 47295077 ps
CPU time 0.71 seconds
Started Mar 21 01:33:03 PM PDT 24
Finished Mar 21 01:33:04 PM PDT 24
Peak memory 204816 kb
Host smart-d2e6dbd5-3d48-45e5-aa03-f902d75aa551
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979073107 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.1979073107
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_stress_all.4257411900
Short name T41
Test name
Test status
Simulation time 3177752124 ps
CPU time 4.1 seconds
Started Mar 21 01:33:07 PM PDT 24
Finished Mar 21 01:33:11 PM PDT 24
Peak memory 205132 kb
Host smart-808a03a0-bb04-498f-b592-9496ff74c002
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257411900 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.4257411900
Directory /workspace/48.rv_dm_stress_all/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.1113368722
Short name T158
Test name
Test status
Simulation time 30831690 ps
CPU time 0.72 seconds
Started Mar 21 01:33:04 PM PDT 24
Finished Mar 21 01:33:05 PM PDT 24
Peak memory 204868 kb
Host smart-bfeb74c1-37de-4b69-bf48-60596d736ddc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113368722 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.1113368722
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.3473053667
Short name T24
Test name
Test status
Simulation time 30099211 ps
CPU time 0.75 seconds
Started Mar 21 01:32:33 PM PDT 24
Finished Mar 21 01:32:34 PM PDT 24
Peak memory 204468 kb
Host smart-70356864-d0fe-46b1-bf01-443841c5bcf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473053667 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.3473053667
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.3264286662
Short name T186
Test name
Test status
Simulation time 10935335272 ps
CPU time 20.34 seconds
Started Mar 21 01:32:25 PM PDT 24
Finished Mar 21 01:32:47 PM PDT 24
Peak memory 213436 kb
Host smart-50bcc845-6af9-4c48-8de1-01270939c36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264286662 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.3264286662
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.1054008667
Short name T8
Test name
Test status
Simulation time 8005559089 ps
CPU time 13.94 seconds
Started Mar 21 01:32:24 PM PDT 24
Finished Mar 21 01:32:39 PM PDT 24
Peak memory 213360 kb
Host smart-ac7ca5c0-04a6-4ce1-b034-91ae5d4cbf58
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1054008667 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t
l_access.1054008667
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.4164900446
Short name T220
Test name
Test status
Simulation time 13527526092 ps
CPU time 11.47 seconds
Started Mar 21 01:32:27 PM PDT 24
Finished Mar 21 01:32:39 PM PDT 24
Peak memory 213380 kb
Host smart-2047bf76-29cc-4c28-a41c-e8a585d846d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164900446 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.4164900446
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.2143712223
Short name T69
Test name
Test status
Simulation time 29517864 ps
CPU time 0.71 seconds
Started Mar 21 01:32:25 PM PDT 24
Finished Mar 21 01:32:27 PM PDT 24
Peak memory 204844 kb
Host smart-3449e45d-f80e-46f4-b8d5-b17bbe632bf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143712223 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.2143712223
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.2954317032
Short name T218
Test name
Test status
Simulation time 13337763379 ps
CPU time 21.21 seconds
Started Mar 21 01:32:24 PM PDT 24
Finished Mar 21 01:32:47 PM PDT 24
Peak memory 215400 kb
Host smart-f0e603bd-a35d-4060-8389-65932f232e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954317032 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.2954317032
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.3691134444
Short name T190
Test name
Test status
Simulation time 541979531 ps
CPU time 1.95 seconds
Started Mar 21 01:32:25 PM PDT 24
Finished Mar 21 01:32:28 PM PDT 24
Peak memory 205236 kb
Host smart-06f6fcba-eef2-4237-bc7f-07783fd41602
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3691134444 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t
l_access.3691134444
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.1240706156
Short name T215
Test name
Test status
Simulation time 1471834244 ps
CPU time 2.4 seconds
Started Mar 21 01:32:26 PM PDT 24
Finished Mar 21 01:32:30 PM PDT 24
Peak memory 205156 kb
Host smart-9ddbbc59-9628-4e50-9f65-e291856a9219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240706156 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.1240706156
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_stress_all.565620042
Short name T1
Test name
Test status
Simulation time 6099066020 ps
CPU time 10.95 seconds
Started Mar 21 01:32:25 PM PDT 24
Finished Mar 21 01:32:37 PM PDT 24
Peak memory 205112 kb
Host smart-cdcd8418-9f94-4a83-be77-a3633224214b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565620042 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.565620042
Directory /workspace/6.rv_dm_stress_all/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.1773726594
Short name T163
Test name
Test status
Simulation time 27244215 ps
CPU time 0.8 seconds
Started Mar 21 01:32:32 PM PDT 24
Finished Mar 21 01:32:34 PM PDT 24
Peak memory 204852 kb
Host smart-efd9c7db-7f98-4776-a895-fc4d3fd2e41c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773726594 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.1773726594
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.2478157986
Short name T18
Test name
Test status
Simulation time 2981009862 ps
CPU time 8.21 seconds
Started Mar 21 01:32:25 PM PDT 24
Finished Mar 21 01:32:34 PM PDT 24
Peak memory 205232 kb
Host smart-2d090fa5-7d2e-4bd2-89bd-11905ec08003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478157986 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.2478157986
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.4022981544
Short name T211
Test name
Test status
Simulation time 6519736667 ps
CPU time 6.48 seconds
Started Mar 21 01:32:32 PM PDT 24
Finished Mar 21 01:32:39 PM PDT 24
Peak memory 213388 kb
Host smart-ab37024a-df05-4242-a5ba-284f9ad1fd8f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4022981544 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.4022981544
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.3941744474
Short name T85
Test name
Test status
Simulation time 7605044166 ps
CPU time 10.5 seconds
Started Mar 21 01:32:26 PM PDT 24
Finished Mar 21 01:32:38 PM PDT 24
Peak memory 205284 kb
Host smart-8482863b-65d8-4b5a-a0cc-3388b2c20e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941744474 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.3941744474
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.3009946090
Short name T173
Test name
Test status
Simulation time 20565726 ps
CPU time 0.71 seconds
Started Mar 21 01:32:37 PM PDT 24
Finished Mar 21 01:32:38 PM PDT 24
Peak memory 204872 kb
Host smart-54a82dcc-94ab-49f8-9f4f-fef2d3aa78e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009946090 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.3009946090
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.2422836611
Short name T198
Test name
Test status
Simulation time 33840800859 ps
CPU time 119.44 seconds
Started Mar 21 01:32:27 PM PDT 24
Finished Mar 21 01:34:27 PM PDT 24
Peak memory 213460 kb
Host smart-bd1f4852-401f-4f06-ae78-bed8595f620f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422836611 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.2422836611
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.1465020185
Short name T189
Test name
Test status
Simulation time 727377324 ps
CPU time 2.82 seconds
Started Mar 21 01:32:32 PM PDT 24
Finished Mar 21 01:32:35 PM PDT 24
Peak memory 205112 kb
Host smart-a03bfdc7-8d30-41ce-9236-6444ee14178d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465020185 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.1465020185
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.61251549
Short name T231
Test name
Test status
Simulation time 2273306628 ps
CPU time 10.71 seconds
Started Mar 21 01:32:26 PM PDT 24
Finished Mar 21 01:32:38 PM PDT 24
Peak memory 205144 kb
Host smart-abe3bdb8-1a70-4b4b-90ea-5c39df6919e9
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=61251549 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_tl_
access.61251549
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.1288543544
Short name T197
Test name
Test status
Simulation time 773587521 ps
CPU time 3.81 seconds
Started Mar 21 01:32:27 PM PDT 24
Finished Mar 21 01:32:32 PM PDT 24
Peak memory 205196 kb
Host smart-9bd2000e-2522-4f25-82d3-121a62b82a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288543544 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.1288543544
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.1971437828
Short name T38
Test name
Test status
Simulation time 27445351 ps
CPU time 0.75 seconds
Started Mar 21 01:32:33 PM PDT 24
Finished Mar 21 01:32:34 PM PDT 24
Peak memory 204800 kb
Host smart-d243d2c2-09e6-411a-80e2-dca95e1e57ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971437828 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.1971437828
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.2875383402
Short name T226
Test name
Test status
Simulation time 14188818963 ps
CPU time 25.8 seconds
Started Mar 21 01:32:34 PM PDT 24
Finished Mar 21 01:32:59 PM PDT 24
Peak memory 215800 kb
Host smart-82badda7-0a47-4d2a-877a-be4fc0883149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875383402 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.2875383402
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.1203280013
Short name T50
Test name
Test status
Simulation time 3942007822 ps
CPU time 15.58 seconds
Started Mar 21 01:32:36 PM PDT 24
Finished Mar 21 01:32:52 PM PDT 24
Peak memory 213468 kb
Host smart-fe12919c-10d0-41e7-be46-41e88ffc7721
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1203280013 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t
l_access.1203280013
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.2548941921
Short name T210
Test name
Test status
Simulation time 1703865566 ps
CPU time 4.77 seconds
Started Mar 21 01:32:36 PM PDT 24
Finished Mar 21 01:32:41 PM PDT 24
Peak memory 205152 kb
Host smart-afc27fe7-8356-45d5-b48b-95820d2b348f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548941921 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.2548941921
Directory /workspace/9.rv_dm_sba_tl_access/latest
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