Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
80.51 94.44 80.05 87.69 78.21 83.66 98.42 41.11


Total test records in report: 372
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html
T276 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.3375334148 Mar 24 12:37:46 PM PDT 24 Mar 24 12:37:49 PM PDT 24 54250242 ps
T277 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.354885252 Mar 24 12:37:39 PM PDT 24 Mar 24 12:37:43 PM PDT 24 242902596 ps
T105 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2560097358 Mar 24 12:37:59 PM PDT 24 Mar 24 12:38:53 PM PDT 24 10816666446 ps
T278 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.1381564665 Mar 24 12:37:38 PM PDT 24 Mar 24 12:37:39 PM PDT 24 252387586 ps
T279 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1540621131 Mar 24 12:37:37 PM PDT 24 Mar 24 12:37:41 PM PDT 24 2024983631 ps
T116 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.1869373455 Mar 24 12:37:49 PM PDT 24 Mar 24 12:37:59 PM PDT 24 4021275429 ps
T106 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.4088912657 Mar 24 12:37:41 PM PDT 24 Mar 24 12:38:55 PM PDT 24 7379623598 ps
T280 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.3390864680 Mar 24 12:37:29 PM PDT 24 Mar 24 12:37:32 PM PDT 24 2266745395 ps
T281 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.1327447082 Mar 24 12:37:47 PM PDT 24 Mar 24 12:37:49 PM PDT 24 39595733 ps
T282 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1696569069 Mar 24 12:37:28 PM PDT 24 Mar 24 12:37:28 PM PDT 24 154601857 ps
T95 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3256053094 Mar 24 12:37:41 PM PDT 24 Mar 24 12:37:43 PM PDT 24 57834785 ps
T283 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.280416996 Mar 24 12:38:22 PM PDT 24 Mar 24 12:38:24 PM PDT 24 97010992 ps
T96 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.388940387 Mar 24 12:37:50 PM PDT 24 Mar 24 12:37:58 PM PDT 24 407675382 ps
T284 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.3337402652 Mar 24 12:37:41 PM PDT 24 Mar 24 12:37:42 PM PDT 24 66076195 ps
T285 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.4167848946 Mar 24 12:37:42 PM PDT 24 Mar 24 12:37:48 PM PDT 24 558975436 ps
T132 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3164707637 Mar 24 12:37:40 PM PDT 24 Mar 24 12:38:01 PM PDT 24 4010251954 ps
T97 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.1290637793 Mar 24 12:37:41 PM PDT 24 Mar 24 12:37:50 PM PDT 24 216893737 ps
T286 /workspace/coverage/cover_reg_top/24.rv_dm_tap_fsm_rand_reset.1751591055 Mar 24 12:37:55 PM PDT 24 Mar 24 12:38:10 PM PDT 24 8421491695 ps
T129 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1561525092 Mar 24 12:37:56 PM PDT 24 Mar 24 12:38:02 PM PDT 24 1065177743 ps
T287 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1734960784 Mar 24 12:37:44 PM PDT 24 Mar 24 12:37:57 PM PDT 24 9433794295 ps
T137 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.377308770 Mar 24 12:37:39 PM PDT 24 Mar 24 12:37:50 PM PDT 24 2922063339 ps
T288 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.3280154248 Mar 24 12:37:47 PM PDT 24 Mar 24 12:37:50 PM PDT 24 60429174 ps
T289 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.3361870490 Mar 24 12:37:42 PM PDT 24 Mar 24 12:37:44 PM PDT 24 195579306 ps
T290 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2294650330 Mar 24 12:37:48 PM PDT 24 Mar 24 12:37:52 PM PDT 24 322650356 ps
T291 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.826769143 Mar 24 12:38:50 PM PDT 24 Mar 24 12:39:28 PM PDT 24 28424092897 ps
T292 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.4264725863 Mar 24 12:37:56 PM PDT 24 Mar 24 12:37:59 PM PDT 24 534340460 ps
T293 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.1700386915 Mar 24 12:37:37 PM PDT 24 Mar 24 12:37:38 PM PDT 24 52630270 ps
T294 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.570029259 Mar 24 12:37:40 PM PDT 24 Mar 24 12:38:08 PM PDT 24 1443641816 ps
T295 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.2227231011 Mar 24 12:37:19 PM PDT 24 Mar 24 12:38:13 PM PDT 24 24840964033 ps
T98 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.2137217392 Mar 24 12:37:17 PM PDT 24 Mar 24 12:38:21 PM PDT 24 1096594618 ps
T296 /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.4221809028 Mar 24 12:37:44 PM PDT 24 Mar 24 12:38:14 PM PDT 24 29451456567 ps
T297 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.4145207218 Mar 24 12:38:01 PM PDT 24 Mar 24 12:38:04 PM PDT 24 40294593 ps
T298 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.125576314 Mar 24 12:37:51 PM PDT 24 Mar 24 12:37:55 PM PDT 24 660408719 ps
T131 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.1948597760 Mar 24 12:37:40 PM PDT 24 Mar 24 12:37:55 PM PDT 24 467164583 ps
T299 /workspace/coverage/cover_reg_top/27.rv_dm_tap_fsm_rand_reset.2764826923 Mar 24 12:37:50 PM PDT 24 Mar 24 12:38:12 PM PDT 24 25030913476 ps
T99 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2510586311 Mar 24 12:38:07 PM PDT 24 Mar 24 12:38:10 PM PDT 24 150846080 ps
T300 /workspace/coverage/cover_reg_top/36.rv_dm_tap_fsm_rand_reset.67168296 Mar 24 12:37:47 PM PDT 24 Mar 24 12:38:03 PM PDT 24 8289255007 ps
T301 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.778771141 Mar 24 12:37:46 PM PDT 24 Mar 24 12:38:14 PM PDT 24 3214693813 ps
T302 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.2186293512 Mar 24 12:37:46 PM PDT 24 Mar 24 12:37:50 PM PDT 24 98783572 ps
T107 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.331114572 Mar 24 12:38:11 PM PDT 24 Mar 24 12:38:14 PM PDT 24 173161197 ps
T100 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3244424101 Mar 24 12:37:48 PM PDT 24 Mar 24 12:37:57 PM PDT 24 744766890 ps
T303 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.1145279497 Mar 24 12:37:45 PM PDT 24 Mar 24 12:37:47 PM PDT 24 127517011 ps
T304 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.227795684 Mar 24 12:37:24 PM PDT 24 Mar 24 12:37:35 PM PDT 24 1594918169 ps
T305 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3897999641 Mar 24 12:37:37 PM PDT 24 Mar 24 12:37:40 PM PDT 24 333695053 ps
T138 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.1585271391 Mar 24 12:38:14 PM PDT 24 Mar 24 12:38:30 PM PDT 24 470436904 ps
T306 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1251077797 Mar 24 12:37:55 PM PDT 24 Mar 24 12:38:03 PM PDT 24 2091767095 ps
T130 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.1964572953 Mar 24 12:38:01 PM PDT 24 Mar 24 12:38:06 PM PDT 24 948968420 ps
T136 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.2137591595 Mar 24 12:37:46 PM PDT 24 Mar 24 12:38:03 PM PDT 24 2920701688 ps
T307 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.4081975004 Mar 24 12:37:18 PM PDT 24 Mar 24 12:37:22 PM PDT 24 91685829 ps
T308 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.1856317237 Mar 24 12:37:34 PM PDT 24 Mar 24 12:38:16 PM PDT 24 13652176728 ps
T101 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1053818761 Mar 24 12:39:00 PM PDT 24 Mar 24 12:39:04 PM PDT 24 83194586 ps
T309 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.142583130 Mar 24 12:37:55 PM PDT 24 Mar 24 12:37:58 PM PDT 24 174599712 ps
T310 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.3532647774 Mar 24 12:37:42 PM PDT 24 Mar 24 12:37:50 PM PDT 24 754507703 ps
T311 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3491608972 Mar 24 12:37:35 PM PDT 24 Mar 24 12:37:36 PM PDT 24 42515767 ps
T312 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.2860397325 Mar 24 12:37:45 PM PDT 24 Mar 24 12:37:48 PM PDT 24 52816973 ps
T313 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.2135329609 Mar 24 12:37:36 PM PDT 24 Mar 24 12:38:15 PM PDT 24 21709026570 ps
T314 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.3381385649 Mar 24 12:37:42 PM PDT 24 Mar 24 12:37:47 PM PDT 24 756100926 ps
T315 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1428520452 Mar 24 12:37:42 PM PDT 24 Mar 24 12:37:43 PM PDT 24 705353867 ps
T316 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3832210133 Mar 24 12:37:44 PM PDT 24 Mar 24 12:37:46 PM PDT 24 63909442 ps
T317 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.2530450824 Mar 24 12:37:57 PM PDT 24 Mar 24 12:38:04 PM PDT 24 73950185 ps
T318 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.4179493152 Mar 24 12:38:48 PM PDT 24 Mar 24 12:38:48 PM PDT 24 44785811 ps
T139 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3498203601 Mar 24 12:37:53 PM PDT 24 Mar 24 12:38:11 PM PDT 24 3442461657 ps
T319 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3746259122 Mar 24 12:37:56 PM PDT 24 Mar 24 12:37:58 PM PDT 24 258433833 ps
T320 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.218033981 Mar 24 12:37:37 PM PDT 24 Mar 24 12:37:42 PM PDT 24 1239641177 ps
T133 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2139953527 Mar 24 12:38:00 PM PDT 24 Mar 24 12:38:11 PM PDT 24 669963396 ps
T321 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.4139402181 Mar 24 12:37:34 PM PDT 24 Mar 24 12:37:38 PM PDT 24 164435984 ps
T102 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.911077566 Mar 24 12:37:40 PM PDT 24 Mar 24 12:37:44 PM PDT 24 79771104 ps
T322 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.3146605450 Mar 24 12:37:38 PM PDT 24 Mar 24 12:37:47 PM PDT 24 1733412651 ps
T323 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.4290628286 Mar 24 12:37:52 PM PDT 24 Mar 24 12:37:53 PM PDT 24 65051848 ps
T324 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.471830282 Mar 24 12:37:22 PM PDT 24 Mar 24 12:38:01 PM PDT 24 4639967291 ps
T325 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.3074325358 Mar 24 12:37:35 PM PDT 24 Mar 24 12:37:38 PM PDT 24 38249205 ps
T326 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.3009642482 Mar 24 12:37:47 PM PDT 24 Mar 24 12:37:59 PM PDT 24 1576341758 ps
T327 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.4099521560 Mar 24 12:37:39 PM PDT 24 Mar 24 12:37:43 PM PDT 24 4093453194 ps
T328 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.151901661 Mar 24 12:37:48 PM PDT 24 Mar 24 12:37:55 PM PDT 24 345501502 ps
T329 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.1942868906 Mar 24 12:37:38 PM PDT 24 Mar 24 12:38:08 PM PDT 24 14485057705 ps
T330 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.2166523572 Mar 24 12:37:40 PM PDT 24 Mar 24 12:37:41 PM PDT 24 82158672 ps
T331 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2028329856 Mar 24 12:37:38 PM PDT 24 Mar 24 12:37:39 PM PDT 24 53190967 ps
T332 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2208420706 Mar 24 12:37:43 PM PDT 24 Mar 24 12:37:44 PM PDT 24 33960604 ps
T333 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.64410491 Mar 24 12:37:45 PM PDT 24 Mar 24 12:37:48 PM PDT 24 39414316 ps
T334 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.855895670 Mar 24 12:37:30 PM PDT 24 Mar 24 12:37:41 PM PDT 24 1505623425 ps
T335 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1082358271 Mar 24 12:37:34 PM PDT 24 Mar 24 12:38:01 PM PDT 24 14762336378 ps
T134 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3785909280 Mar 24 12:37:56 PM PDT 24 Mar 24 12:38:07 PM PDT 24 1118180158 ps
T336 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.464405567 Mar 24 12:37:38 PM PDT 24 Mar 24 12:38:13 PM PDT 24 9641704606 ps
T108 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3178691728 Mar 24 12:37:52 PM PDT 24 Mar 24 12:37:54 PM PDT 24 70864478 ps
T337 /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.1568688405 Mar 24 12:37:38 PM PDT 24 Mar 24 12:37:50 PM PDT 24 12392112858 ps
T338 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2602525319 Mar 24 12:37:45 PM PDT 24 Mar 24 12:37:50 PM PDT 24 4069163008 ps
T339 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.740763909 Mar 24 12:37:30 PM PDT 24 Mar 24 12:38:12 PM PDT 24 15389252968 ps
T340 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.3887925478 Mar 24 12:37:47 PM PDT 24 Mar 24 12:38:20 PM PDT 24 6236937360 ps
T341 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.2601916807 Mar 24 12:37:24 PM PDT 24 Mar 24 12:37:27 PM PDT 24 474455487 ps
T342 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.179349443 Mar 24 12:37:58 PM PDT 24 Mar 24 12:38:00 PM PDT 24 271807803 ps
T343 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3781941962 Mar 24 12:37:53 PM PDT 24 Mar 24 12:37:55 PM PDT 24 148137542 ps
T344 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.444433082 Mar 24 12:37:57 PM PDT 24 Mar 24 12:38:01 PM PDT 24 120659277 ps
T345 /workspace/coverage/cover_reg_top/32.rv_dm_tap_fsm_rand_reset.3077774432 Mar 24 12:37:49 PM PDT 24 Mar 24 12:38:06 PM PDT 24 7843329192 ps
T103 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.984656927 Mar 24 12:37:47 PM PDT 24 Mar 24 12:37:51 PM PDT 24 50423208 ps
T346 /workspace/coverage/cover_reg_top/25.rv_dm_tap_fsm_rand_reset.3227301346 Mar 24 12:37:48 PM PDT 24 Mar 24 12:38:04 PM PDT 24 7130647053 ps
T347 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.424094636 Mar 24 12:38:10 PM PDT 24 Mar 24 12:38:12 PM PDT 24 397625412 ps
T348 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.3739738458 Mar 24 12:39:07 PM PDT 24 Mar 24 12:39:11 PM PDT 24 836091879 ps
T349 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.1082781614 Mar 24 12:37:42 PM PDT 24 Mar 24 12:37:50 PM PDT 24 3426746211 ps
T350 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2165016050 Mar 24 12:37:35 PM PDT 24 Mar 24 12:37:37 PM PDT 24 61499057 ps
T351 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.2235127564 Mar 24 12:37:19 PM PDT 24 Mar 24 12:37:22 PM PDT 24 95164426 ps
T352 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3891797203 Mar 24 12:37:50 PM PDT 24 Mar 24 12:37:54 PM PDT 24 143039203 ps
T353 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.4155350557 Mar 24 12:37:37 PM PDT 24 Mar 24 12:37:41 PM PDT 24 64910066 ps
T354 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3129057117 Mar 24 12:38:02 PM PDT 24 Mar 24 12:38:10 PM PDT 24 1600972158 ps
T355 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.560965136 Mar 24 12:37:39 PM PDT 24 Mar 24 12:37:44 PM PDT 24 686456977 ps
T356 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.672344871 Mar 24 12:37:44 PM PDT 24 Mar 24 12:37:46 PM PDT 24 184227767 ps
T357 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3050074047 Mar 24 12:37:36 PM PDT 24 Mar 24 12:37:38 PM PDT 24 312797257 ps
T358 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.329309778 Mar 24 12:37:40 PM PDT 24 Mar 24 12:37:51 PM PDT 24 4463560018 ps
T359 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.489384968 Mar 24 12:37:58 PM PDT 24 Mar 24 12:38:07 PM PDT 24 463116595 ps
T360 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2377326555 Mar 24 12:37:42 PM PDT 24 Mar 24 12:37:43 PM PDT 24 177519076 ps
T361 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.3313783152 Mar 24 12:37:56 PM PDT 24 Mar 24 12:38:01 PM PDT 24 311092127 ps
T362 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.88619508 Mar 24 12:37:20 PM PDT 24 Mar 24 12:37:22 PM PDT 24 44277799 ps
T93 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.1990973391 Mar 24 12:37:31 PM PDT 24 Mar 24 12:37:40 PM PDT 24 2731356991 ps
T363 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.2612490750 Mar 24 12:37:39 PM PDT 24 Mar 24 12:37:49 PM PDT 24 3098039531 ps
T364 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.2961835419 Mar 24 12:37:37 PM PDT 24 Mar 24 12:37:37 PM PDT 24 84800262 ps
T365 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.599182806 Mar 24 12:37:37 PM PDT 24 Mar 24 12:37:39 PM PDT 24 86633356 ps
T366 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.1371237167 Mar 24 12:37:54 PM PDT 24 Mar 24 12:38:03 PM PDT 24 2160971469 ps
T367 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.58882862 Mar 24 12:37:22 PM PDT 24 Mar 24 12:37:23 PM PDT 24 107512601 ps
T368 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.692801003 Mar 24 12:37:42 PM PDT 24 Mar 24 12:37:43 PM PDT 24 322760977 ps
T369 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.2824200746 Mar 24 12:37:23 PM PDT 24 Mar 24 12:37:29 PM PDT 24 150403964 ps
T370 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.201290838 Mar 24 12:37:45 PM PDT 24 Mar 24 12:37:47 PM PDT 24 83614901 ps
T371 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.2424598492 Mar 24 12:37:41 PM PDT 24 Mar 24 12:37:47 PM PDT 24 1267716185 ps
T372 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.3064371420 Mar 24 12:37:40 PM PDT 24 Mar 24 12:37:40 PM PDT 24 35760444 ps

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.437921839
Short name T12
Test name
Test status
Simulation time 1698761056 ps
CPU time 2.79 seconds
Started Mar 24 12:38:17 PM PDT 24
Finished Mar 24 12:38:21 PM PDT 24
Peak memory 205020 kb
Host smart-62d4b5c7-26be-4be9-99d5-def39fde94ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437921839 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.437921839
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_stress_all.2666156172
Short name T5
Test name
Test status
Simulation time 5473937401 ps
CPU time 6.02 seconds
Started Mar 24 12:38:19 PM PDT 24
Finished Mar 24 12:38:25 PM PDT 24
Peak memory 204992 kb
Host smart-687d9de1-a8d8-4e3e-b411-960899ada2f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666156172 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.2666156172
Directory /workspace/15.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3808600104
Short name T37
Test name
Test status
Simulation time 580074893 ps
CPU time 4.01 seconds
Started Mar 24 12:37:55 PM PDT 24
Finished Mar 24 12:37:59 PM PDT 24
Peak memory 217124 kb
Host smart-f592e5e5-356f-4397-9354-77cdb4a466b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808600104 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.3808600104
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/35.rv_dm_tap_fsm_rand_reset.1611147182
Short name T60
Test name
Test status
Simulation time 11107106975 ps
CPU time 12.4 seconds
Started Mar 24 12:37:56 PM PDT 24
Finished Mar 24 12:38:09 PM PDT 24
Peak memory 217496 kb
Host smart-69e77cfc-63c8-4686-ae7b-807fa1e2dc98
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611147182 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 35.rv_dm_tap_fsm_rand_reset.1611147182
Directory /workspace/35.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.4214051944
Short name T3
Test name
Test status
Simulation time 20141772 ps
CPU time 0.73 seconds
Started Mar 24 12:38:08 PM PDT 24
Finished Mar 24 12:38:09 PM PDT 24
Peak memory 204708 kb
Host smart-89e83bd7-518d-4bff-804c-ca866de6cf4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214051944 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.4214051944
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_stress_all.1369123122
Short name T32
Test name
Test status
Simulation time 3841765347 ps
CPU time 13.7 seconds
Started Mar 24 12:38:27 PM PDT 24
Finished Mar 24 12:38:41 PM PDT 24
Peak memory 205348 kb
Host smart-abbbc4d6-906b-47af-9de8-0c00ed223d5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369123122 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.1369123122
Directory /workspace/23.rv_dm_stress_all/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.271956023
Short name T19
Test name
Test status
Simulation time 43948459667 ps
CPU time 178.28 seconds
Started Mar 24 12:38:13 PM PDT 24
Finished Mar 24 12:41:12 PM PDT 24
Peak memory 213368 kb
Host smart-2420abe1-d467-4b6a-a521-adb5727f8c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271956023 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.271956023
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3874751494
Short name T71
Test name
Test status
Simulation time 949170622 ps
CPU time 17.46 seconds
Started Mar 24 12:37:35 PM PDT 24
Finished Mar 24 12:37:52 PM PDT 24
Peak memory 220932 kb
Host smart-8af0df72-7916-4df3-a8a0-d38e82e56901
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874751494 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.3874751494
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.1995670148
Short name T82
Test name
Test status
Simulation time 127523990 ps
CPU time 2.09 seconds
Started Mar 24 12:37:44 PM PDT 24
Finished Mar 24 12:37:48 PM PDT 24
Peak memory 218432 kb
Host smart-48b05d23-223a-4a6c-8a33-98a5c437b903
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995670148 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.1995670148
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.139849066
Short name T156
Test name
Test status
Simulation time 139224414 ps
CPU time 4.68 seconds
Started Mar 24 12:37:39 PM PDT 24
Finished Mar 24 12:37:44 PM PDT 24
Peak memory 215488 kb
Host smart-3e71272d-7834-4736-a874-1368069467e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139849066 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.139849066
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all.2605730428
Short name T29
Test name
Test status
Simulation time 2644831146 ps
CPU time 2.87 seconds
Started Mar 24 12:37:47 PM PDT 24
Finished Mar 24 12:37:52 PM PDT 24
Peak memory 205008 kb
Host smart-c2f80ba6-72e4-4e34-afcc-44b48045eb14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605730428 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.2605730428
Directory /workspace/0.rv_dm_stress_all/latest

Test location /workspace/coverage/default/37.rv_dm_stress_all.3260846258
Short name T4
Test name
Test status
Simulation time 2935715487 ps
CPU time 3.16 seconds
Started Mar 24 12:38:32 PM PDT 24
Finished Mar 24 12:38:35 PM PDT 24
Peak memory 205012 kb
Host smart-9a36e912-2480-4410-adc4-fbf6c78524ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260846258 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.3260846258
Directory /workspace/37.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.960216807
Short name T121
Test name
Test status
Simulation time 3536531771 ps
CPU time 19.13 seconds
Started Mar 24 12:37:49 PM PDT 24
Finished Mar 24 12:38:09 PM PDT 24
Peak memory 212820 kb
Host smart-98df0898-2604-4fc8-bdde-46e1d0b7b4b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960216807 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.960216807
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.233199212
Short name T45
Test name
Test status
Simulation time 352127805 ps
CPU time 1.45 seconds
Started Mar 24 12:38:24 PM PDT 24
Finished Mar 24 12:38:26 PM PDT 24
Peak memory 229084 kb
Host smart-1acd3ea2-6b23-49fa-b839-b33bf4a14157
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233199212 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.233199212
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.929768993
Short name T50
Test name
Test status
Simulation time 88235582 ps
CPU time 0.81 seconds
Started Mar 24 12:37:55 PM PDT 24
Finished Mar 24 12:37:56 PM PDT 24
Peak memory 212948 kb
Host smart-d53353d7-beb3-4f99-9094-a4d9730fb871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929768993 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.929768993
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.2981736487
Short name T53
Test name
Test status
Simulation time 268680280 ps
CPU time 1.4 seconds
Started Mar 24 12:37:54 PM PDT 24
Finished Mar 24 12:37:56 PM PDT 24
Peak memory 204692 kb
Host smart-2f3a19f5-d750-4038-82b5-3b862514dc01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981736487 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.2981736487
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2848639541
Short name T62
Test name
Test status
Simulation time 89232436 ps
CPU time 0.84 seconds
Started Mar 24 12:38:23 PM PDT 24
Finished Mar 24 12:38:23 PM PDT 24
Peak memory 203948 kb
Host smart-331e371a-2e4f-4d51-9b53-03fc307b08bd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848639541 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.2848639541
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.1128498980
Short name T6
Test name
Test status
Simulation time 124689768 ps
CPU time 1.16 seconds
Started Mar 24 12:37:50 PM PDT 24
Finished Mar 24 12:37:52 PM PDT 24
Peak memory 204952 kb
Host smart-746479dc-f01f-4001-8bea-664f9e07ec43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128498980 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.1128498980
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.1025488868
Short name T168
Test name
Test status
Simulation time 261309282 ps
CPU time 4.62 seconds
Started Mar 24 12:37:53 PM PDT 24
Finished Mar 24 12:37:58 PM PDT 24
Peak memory 212804 kb
Host smart-5721fb70-9915-47fc-ba82-6789d0c4b8c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025488868 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.1025488868
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.1477311553
Short name T54
Test name
Test status
Simulation time 60633912 ps
CPU time 0.72 seconds
Started Mar 24 12:38:03 PM PDT 24
Finished Mar 24 12:38:04 PM PDT 24
Peak memory 204700 kb
Host smart-c862cdbc-7dbd-4b16-a577-80909f4a9acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477311553 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.1477311553
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.2471541592
Short name T68
Test name
Test status
Simulation time 88289926 ps
CPU time 0.74 seconds
Started Mar 24 12:38:06 PM PDT 24
Finished Mar 24 12:38:06 PM PDT 24
Peak memory 204704 kb
Host smart-e677be3f-976c-47db-9d3a-6b9143a6064b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471541592 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.2471541592
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3498203601
Short name T139
Test name
Test status
Simulation time 3442461657 ps
CPU time 18.07 seconds
Started Mar 24 12:37:53 PM PDT 24
Finished Mar 24 12:38:11 PM PDT 24
Peak memory 221336 kb
Host smart-81b9de37-ba9f-43c0-b6e1-fd847fb8a83c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498203601 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.3
498203601
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.1990973391
Short name T93
Test name
Test status
Simulation time 2731356991 ps
CPU time 9.48 seconds
Started Mar 24 12:37:31 PM PDT 24
Finished Mar 24 12:37:40 PM PDT 24
Peak memory 204680 kb
Host smart-ce03a338-8964-404a-926b-583a95796f35
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990973391 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.1990973391
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.71106106
Short name T114
Test name
Test status
Simulation time 422130568 ps
CPU time 3.97 seconds
Started Mar 24 12:37:33 PM PDT 24
Finished Mar 24 12:37:37 PM PDT 24
Peak memory 204572 kb
Host smart-61480232-ad1b-491f-8fd8-d9664e1775f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71106106 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_cs
r_outstanding.71106106
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.2796450521
Short name T64
Test name
Test status
Simulation time 39980222 ps
CPU time 0.73 seconds
Started Mar 24 12:38:33 PM PDT 24
Finished Mar 24 12:38:34 PM PDT 24
Peak memory 204668 kb
Host smart-5d8e79c3-1b28-4aca-8512-638fd3b1f283
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796450521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.2796450521
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2207769060
Short name T39
Test name
Test status
Simulation time 764120382 ps
CPU time 2.28 seconds
Started Mar 24 12:37:28 PM PDT 24
Finished Mar 24 12:37:30 PM PDT 24
Peak memory 212792 kb
Host smart-0b86c9ad-7905-4aba-a49a-efe9f7c70fce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207769060 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.2207769060
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.1139614135
Short name T18
Test name
Test status
Simulation time 539763293 ps
CPU time 1.06 seconds
Started Mar 24 12:37:52 PM PDT 24
Finished Mar 24 12:37:54 PM PDT 24
Peak memory 204504 kb
Host smart-36068ed0-fc63-4115-9220-79c05a44143b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139614135 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.1139614135
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/27.rv_dm_stress_all.342068514
Short name T10
Test name
Test status
Simulation time 9583936611 ps
CPU time 5.39 seconds
Started Mar 24 12:38:15 PM PDT 24
Finished Mar 24 12:38:21 PM PDT 24
Peak memory 205040 kb
Host smart-aeb23c44-27f8-47a0-bf01-9475e1a369b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342068514 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.342068514
Directory /workspace/27.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1561525092
Short name T129
Test name
Test status
Simulation time 1065177743 ps
CPU time 6.56 seconds
Started Mar 24 12:37:56 PM PDT 24
Finished Mar 24 12:38:02 PM PDT 24
Peak memory 212828 kb
Host smart-51b21720-5ed4-485a-98c6-263187a5ac4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561525092 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.1561525092
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3785909280
Short name T134
Test name
Test status
Simulation time 1118180158 ps
CPU time 10.88 seconds
Started Mar 24 12:37:56 PM PDT 24
Finished Mar 24 12:38:07 PM PDT 24
Peak memory 220972 kb
Host smart-d3b657d5-12d0-47cb-98cb-37b19c1052ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785909280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.3
785909280
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.2137217392
Short name T98
Test name
Test status
Simulation time 1096594618 ps
CPU time 63.75 seconds
Started Mar 24 12:37:17 PM PDT 24
Finished Mar 24 12:38:21 PM PDT 24
Peak memory 212792 kb
Host smart-408993b6-812c-4952-bbfa-3c60878d2f7e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137217392 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.2137217392
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.471830282
Short name T324
Test name
Test status
Simulation time 4639967291 ps
CPU time 37.96 seconds
Started Mar 24 12:37:22 PM PDT 24
Finished Mar 24 12:38:01 PM PDT 24
Peak memory 204644 kb
Host smart-6c0bcc1b-a9d4-4454-baed-eca277b60cc7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471830282 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.471830282
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.280416996
Short name T283
Test name
Test status
Simulation time 97010992 ps
CPU time 1.65 seconds
Started Mar 24 12:38:22 PM PDT 24
Finished Mar 24 12:38:24 PM PDT 24
Peak memory 211856 kb
Host smart-0a92f3fd-acde-4e94-83b0-287c9db412d7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280416996 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.280416996
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.2530450824
Short name T317
Test name
Test status
Simulation time 73950185 ps
CPU time 4.06 seconds
Started Mar 24 12:37:57 PM PDT 24
Finished Mar 24 12:38:04 PM PDT 24
Peak memory 218348 kb
Host smart-c4d6557c-bc78-421f-a248-03412a30a798
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530450824 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.2530450824
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.2227231011
Short name T295
Test name
Test status
Simulation time 24840964033 ps
CPU time 47.57 seconds
Started Mar 24 12:37:19 PM PDT 24
Finished Mar 24 12:38:13 PM PDT 24
Peak memory 204564 kb
Host smart-1632b816-930b-4740-a2c7-72a0f3407062
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227231011 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.2227231011
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1082358271
Short name T335
Test name
Test status
Simulation time 14762336378 ps
CPU time 26.35 seconds
Started Mar 24 12:37:34 PM PDT 24
Finished Mar 24 12:38:01 PM PDT 24
Peak memory 204572 kb
Host smart-0369a0a4-3c7b-40f6-8ea5-c0b2cb8436de
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082358271 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_bit_bash.1082358271
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3757549520
Short name T241
Test name
Test status
Simulation time 832992113 ps
CPU time 1.19 seconds
Started Mar 24 12:38:54 PM PDT 24
Finished Mar 24 12:38:55 PM PDT 24
Peak memory 204492 kb
Host smart-07bd2a5f-3f04-4896-abbe-b23b2daeb6df
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757549520 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.3
757549520
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.482798676
Short name T271
Test name
Test status
Simulation time 156197528 ps
CPU time 0.82 seconds
Started Mar 24 12:37:09 PM PDT 24
Finished Mar 24 12:37:12 PM PDT 24
Peak memory 204312 kb
Host smart-ed6b1598-911c-4bf3-984c-a7ced7fa4a57
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482798676 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr
_aliasing.482798676
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.2601916807
Short name T341
Test name
Test status
Simulation time 474455487 ps
CPU time 2.42 seconds
Started Mar 24 12:37:24 PM PDT 24
Finished Mar 24 12:37:27 PM PDT 24
Peak memory 204604 kb
Host smart-31d74395-cf98-47ca-9821-c892fd430aa6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601916807 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.2601916807
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3881855977
Short name T264
Test name
Test status
Simulation time 117190740 ps
CPU time 0.76 seconds
Started Mar 24 12:37:34 PM PDT 24
Finished Mar 24 12:37:35 PM PDT 24
Peak memory 204276 kb
Host smart-83f94974-c34f-4031-810f-f50a09014279
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881855977 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.3881855977
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.2235127564
Short name T351
Test name
Test status
Simulation time 95164426 ps
CPU time 0.7 seconds
Started Mar 24 12:37:19 PM PDT 24
Finished Mar 24 12:37:22 PM PDT 24
Peak memory 204292 kb
Host smart-a040f0ef-881c-4fa4-a986-171093b02479
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235127564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.2
235127564
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1911235202
Short name T266
Test name
Test status
Simulation time 14800112 ps
CPU time 0.7 seconds
Started Mar 24 12:37:46 PM PDT 24
Finished Mar 24 12:37:49 PM PDT 24
Peak memory 204308 kb
Host smart-fa121ebe-5071-459c-810e-60678a5e8642
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911235202 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.1911235202
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.1508564601
Short name T267
Test name
Test status
Simulation time 49282243 ps
CPU time 0.67 seconds
Started Mar 24 12:37:10 PM PDT 24
Finished Mar 24 12:37:12 PM PDT 24
Peak memory 204312 kb
Host smart-97728db7-4788-4e25-b4f9-451bd81d0e14
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508564601 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.1508564601
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1053818761
Short name T101
Test name
Test status
Simulation time 83194586 ps
CPU time 3.43 seconds
Started Mar 24 12:39:00 PM PDT 24
Finished Mar 24 12:39:04 PM PDT 24
Peak memory 204540 kb
Host smart-bf85876e-ebce-4161-992a-8ac8604e2b5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053818761 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.1053818761
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.560965136
Short name T355
Test name
Test status
Simulation time 686456977 ps
CPU time 4.86 seconds
Started Mar 24 12:37:39 PM PDT 24
Finished Mar 24 12:37:44 PM PDT 24
Peak memory 212832 kb
Host smart-2b87c1a4-f748-45c6-b4c0-568b4588e1f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560965136 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.560965136
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.826769143
Short name T291
Test name
Test status
Simulation time 28424092897 ps
CPU time 38.01 seconds
Started Mar 24 12:38:50 PM PDT 24
Finished Mar 24 12:39:28 PM PDT 24
Peak memory 212836 kb
Host smart-5dadac89-5deb-475d-a0e2-33c0d12b0cf1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826769143 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.rv_dm_csr_aliasing.826769143
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.4088912657
Short name T106
Test name
Test status
Simulation time 7379623598 ps
CPU time 73.64 seconds
Started Mar 24 12:37:41 PM PDT 24
Finished Mar 24 12:38:55 PM PDT 24
Peak memory 204780 kb
Host smart-b2fb6cf8-4c8f-4c7f-8ea7-1e6fd7f164b6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088912657 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.4088912657
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.3705237636
Short name T117
Test name
Test status
Simulation time 136392296 ps
CPU time 1.66 seconds
Started Mar 24 12:37:32 PM PDT 24
Finished Mar 24 12:37:33 PM PDT 24
Peak memory 212804 kb
Host smart-4e6c634b-5189-42ba-bd5f-9439c548465a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705237636 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.3705237636
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.4145207218
Short name T297
Test name
Test status
Simulation time 40294593 ps
CPU time 2.13 seconds
Started Mar 24 12:38:01 PM PDT 24
Finished Mar 24 12:38:04 PM PDT 24
Peak memory 213680 kb
Host smart-8a043f43-883b-4662-b96a-445fcbae11ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145207218 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.4145207218
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.898898683
Short name T81
Test name
Test status
Simulation time 40435490 ps
CPU time 2.14 seconds
Started Mar 24 12:37:40 PM PDT 24
Finished Mar 24 12:37:43 PM PDT 24
Peak memory 218012 kb
Host smart-7dcab635-5953-4633-a6c3-56d718153d45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898898683 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.898898683
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1734960784
Short name T287
Test name
Test status
Simulation time 9433794295 ps
CPU time 11.2 seconds
Started Mar 24 12:37:44 PM PDT 24
Finished Mar 24 12:37:57 PM PDT 24
Peak memory 204564 kb
Host smart-55788b57-1a5d-428f-af0c-d9b17de411f5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734960784 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.1734960784
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3594072985
Short name T252
Test name
Test status
Simulation time 33955550967 ps
CPU time 108.39 seconds
Started Mar 24 12:37:50 PM PDT 24
Finished Mar 24 12:39:44 PM PDT 24
Peak memory 204636 kb
Host smart-ebe1c10f-b676-4f97-abcd-403f6bd92bae
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594072985 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_bit_bash.3594072985
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.3016994745
Short name T92
Test name
Test status
Simulation time 307927257 ps
CPU time 1.74 seconds
Started Mar 24 12:37:18 PM PDT 24
Finished Mar 24 12:37:23 PM PDT 24
Peak memory 204520 kb
Host smart-d50a5714-516b-4d21-95f8-7a9e827703e9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016994745 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.3016994745
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.3739738458
Short name T348
Test name
Test status
Simulation time 836091879 ps
CPU time 3.06 seconds
Started Mar 24 12:39:07 PM PDT 24
Finished Mar 24 12:39:11 PM PDT 24
Peak memory 204436 kb
Host smart-eb2f4998-11e1-4108-87bc-fe4aaa42ca03
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739738458 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.3
739738458
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.4179493152
Short name T318
Test name
Test status
Simulation time 44785811 ps
CPU time 0.76 seconds
Started Mar 24 12:38:48 PM PDT 24
Finished Mar 24 12:38:48 PM PDT 24
Peak memory 204224 kb
Host smart-8391b385-5a30-4f09-92ff-74deea2b4c49
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179493152 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.4179493152
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.1665367681
Short name T261
Test name
Test status
Simulation time 2739920682 ps
CPU time 4.33 seconds
Started Mar 24 12:37:44 PM PDT 24
Finished Mar 24 12:37:50 PM PDT 24
Peak memory 204596 kb
Host smart-e1b06160-fa8a-45b1-84e2-69c0bcd068b2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665367681 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.1665367681
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3507839772
Short name T61
Test name
Test status
Simulation time 22949715 ps
CPU time 0.66 seconds
Started Mar 24 12:38:53 PM PDT 24
Finished Mar 24 12:38:54 PM PDT 24
Peak memory 204232 kb
Host smart-39908cb4-bf81-420b-ba4c-56dae50702bc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507839772 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.3
507839772
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3764500743
Short name T240
Test name
Test status
Simulation time 53031408 ps
CPU time 0.71 seconds
Started Mar 24 12:37:42 PM PDT 24
Finished Mar 24 12:37:43 PM PDT 24
Peak memory 204312 kb
Host smart-1a641c4f-13fa-4c86-b2a2-51eb7d5df8f9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764500743 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.3764500743
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.3064371420
Short name T372
Test name
Test status
Simulation time 35760444 ps
CPU time 0.66 seconds
Started Mar 24 12:37:40 PM PDT 24
Finished Mar 24 12:37:40 PM PDT 24
Peak memory 204308 kb
Host smart-78d24a2c-8aa9-409d-b090-a7e84a28efba
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064371420 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.3064371420
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.855895670
Short name T334
Test name
Test status
Simulation time 1505623425 ps
CPU time 6.01 seconds
Started Mar 24 12:37:30 PM PDT 24
Finished Mar 24 12:37:41 PM PDT 24
Peak memory 212780 kb
Host smart-bbcd133b-3222-48b2-a027-ab988b5d8031
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855895670 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.855895670
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.3532647774
Short name T310
Test name
Test status
Simulation time 754507703 ps
CPU time 8.38 seconds
Started Mar 24 12:37:42 PM PDT 24
Finished Mar 24 12:37:50 PM PDT 24
Peak memory 220800 kb
Host smart-98e01dd1-3284-441a-9e12-b62626bd142b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532647774 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.3532647774
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.1082781614
Short name T349
Test name
Test status
Simulation time 3426746211 ps
CPU time 7.98 seconds
Started Mar 24 12:37:42 PM PDT 24
Finished Mar 24 12:37:50 PM PDT 24
Peak memory 220316 kb
Host smart-da707e70-7a19-47ee-87cf-1dff64cdea9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082781614 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.1082781614
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.984656927
Short name T103
Test name
Test status
Simulation time 50423208 ps
CPU time 1.46 seconds
Started Mar 24 12:37:47 PM PDT 24
Finished Mar 24 12:37:51 PM PDT 24
Peak memory 212784 kb
Host smart-47c0cd11-56f5-47e3-bde1-b9e2039e1d91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984656927 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.984656927
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.1381564665
Short name T278
Test name
Test status
Simulation time 252387586 ps
CPU time 1.45 seconds
Started Mar 24 12:37:38 PM PDT 24
Finished Mar 24 12:37:39 PM PDT 24
Peak memory 204540 kb
Host smart-3f6c55f5-73e2-43de-944d-488bf009db85
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381564665 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
1381564665
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.3531836326
Short name T251
Test name
Test status
Simulation time 69460249 ps
CPU time 0.75 seconds
Started Mar 24 12:37:34 PM PDT 24
Finished Mar 24 12:37:35 PM PDT 24
Peak memory 204272 kb
Host smart-c2798085-55be-4eed-8ebe-6b40c4af4300
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531836326 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
3531836326
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3890541679
Short name T111
Test name
Test status
Simulation time 158202403 ps
CPU time 6.48 seconds
Started Mar 24 12:37:44 PM PDT 24
Finished Mar 24 12:37:53 PM PDT 24
Peak memory 204624 kb
Host smart-327e2218-0fb6-4db0-90e2-bfe986d74677
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890541679 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.3890541679
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.2424598492
Short name T371
Test name
Test status
Simulation time 1267716185 ps
CPU time 6.38 seconds
Started Mar 24 12:37:41 PM PDT 24
Finished Mar 24 12:37:47 PM PDT 24
Peak memory 212724 kb
Host smart-4869babe-6b91-4880-9ce4-4a5d230b373d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424598492 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.2424598492
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.489384968
Short name T359
Test name
Test status
Simulation time 463116595 ps
CPU time 8.48 seconds
Started Mar 24 12:37:58 PM PDT 24
Finished Mar 24 12:38:07 PM PDT 24
Peak memory 212768 kb
Host smart-e997401e-3976-4afc-b086-457b2c27aa15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489384968 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.489384968
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3781941962
Short name T343
Test name
Test status
Simulation time 148137542 ps
CPU time 2.33 seconds
Started Mar 24 12:37:53 PM PDT 24
Finished Mar 24 12:37:55 PM PDT 24
Peak memory 212784 kb
Host smart-690e9890-cf82-459f-9ea1-1e111216f5f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781941962 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.3781941962
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.142583130
Short name T309
Test name
Test status
Simulation time 174599712 ps
CPU time 2.18 seconds
Started Mar 24 12:37:55 PM PDT 24
Finished Mar 24 12:37:58 PM PDT 24
Peak memory 218272 kb
Host smart-edb78744-05c3-4284-8e3a-d12e57b971af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142583130 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.142583130
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.692801003
Short name T368
Test name
Test status
Simulation time 322760977 ps
CPU time 1.11 seconds
Started Mar 24 12:37:42 PM PDT 24
Finished Mar 24 12:37:43 PM PDT 24
Peak memory 204444 kb
Host smart-c6349f0a-3923-43b5-86df-3c777b24c9a0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692801003 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.692801003
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3832210133
Short name T316
Test name
Test status
Simulation time 63909442 ps
CPU time 0.74 seconds
Started Mar 24 12:37:44 PM PDT 24
Finished Mar 24 12:37:46 PM PDT 24
Peak memory 204308 kb
Host smart-f7f23ec7-f3be-42a7-b129-265971e64ab2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832210133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.
3832210133
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.388940387
Short name T96
Test name
Test status
Simulation time 407675382 ps
CPU time 7.59 seconds
Started Mar 24 12:37:50 PM PDT 24
Finished Mar 24 12:37:58 PM PDT 24
Peak memory 204604 kb
Host smart-3d86ba1b-63c5-4a7b-973d-3fe564a2680f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388940387 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same_
csr_outstanding.388940387
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.1371237167
Short name T366
Test name
Test status
Simulation time 2160971469 ps
CPU time 9.1 seconds
Started Mar 24 12:37:54 PM PDT 24
Finished Mar 24 12:38:03 PM PDT 24
Peak memory 214876 kb
Host smart-3a06d837-7db1-4d27-811e-6c1471666450
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371237167 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.1
371237167
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.2186293512
Short name T302
Test name
Test status
Simulation time 98783572 ps
CPU time 2.23 seconds
Started Mar 24 12:37:46 PM PDT 24
Finished Mar 24 12:37:50 PM PDT 24
Peak memory 216196 kb
Host smart-fa3ba7aa-847d-4454-b7e9-1495062e3d29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186293512 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.2186293512
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.559312198
Short name T94
Test name
Test status
Simulation time 29667932 ps
CPU time 1.51 seconds
Started Mar 24 12:37:46 PM PDT 24
Finished Mar 24 12:37:48 PM PDT 24
Peak memory 212788 kb
Host smart-bbf74633-0dd9-4195-b14d-475912a9fb81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559312198 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.559312198
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.586903048
Short name T269
Test name
Test status
Simulation time 359712522 ps
CPU time 2.02 seconds
Started Mar 24 12:38:02 PM PDT 24
Finished Mar 24 12:38:04 PM PDT 24
Peak memory 204544 kb
Host smart-2aca36fd-ec38-4536-bc2a-607b714af44b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586903048 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.586903048
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3491608972
Short name T311
Test name
Test status
Simulation time 42515767 ps
CPU time 0.68 seconds
Started Mar 24 12:37:35 PM PDT 24
Finished Mar 24 12:37:36 PM PDT 24
Peak memory 204312 kb
Host smart-005e32f6-885c-4c4d-bdb2-3d0e479efa1d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491608972 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
3491608972
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.4085108586
Short name T115
Test name
Test status
Simulation time 151636514 ps
CPU time 6.66 seconds
Started Mar 24 12:37:43 PM PDT 24
Finished Mar 24 12:37:50 PM PDT 24
Peak memory 204608 kb
Host smart-b40a35ef-5595-4ccd-a0eb-15546d46ab01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085108586 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.4085108586
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.151901661
Short name T328
Test name
Test status
Simulation time 345501502 ps
CPU time 4.92 seconds
Started Mar 24 12:37:48 PM PDT 24
Finished Mar 24 12:37:55 PM PDT 24
Peak memory 212776 kb
Host smart-ec3f6d60-f9ee-48dd-8dd8-57c84f20dbf2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151901661 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.151901661
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2952193437
Short name T123
Test name
Test status
Simulation time 1078581209 ps
CPU time 10.91 seconds
Started Mar 24 12:37:45 PM PDT 24
Finished Mar 24 12:37:57 PM PDT 24
Peak memory 212792 kb
Host smart-fe5f715c-ca6a-4e7a-9c55-dde5ae3ab6da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952193437 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.2
952193437
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.171313400
Short name T40
Test name
Test status
Simulation time 92950088 ps
CPU time 1.45 seconds
Started Mar 24 12:37:53 PM PDT 24
Finished Mar 24 12:37:54 PM PDT 24
Peak memory 212476 kb
Host smart-9e29b8b3-200f-4b61-bbab-3037edf027ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171313400 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.171313400
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.424094636
Short name T347
Test name
Test status
Simulation time 397625412 ps
CPU time 1.43 seconds
Started Mar 24 12:38:10 PM PDT 24
Finished Mar 24 12:38:12 PM PDT 24
Peak memory 204472 kb
Host smart-0c6fb209-f240-4ada-a2c2-138d9c4cc796
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424094636 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.424094636
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1512270303
Short name T249
Test name
Test status
Simulation time 59500674 ps
CPU time 0.73 seconds
Started Mar 24 12:38:00 PM PDT 24
Finished Mar 24 12:38:01 PM PDT 24
Peak memory 204304 kb
Host smart-8e496d83-b6fa-42f9-b18d-e2d0bef808a4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512270303 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
1512270303
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.1727327818
Short name T109
Test name
Test status
Simulation time 520352572 ps
CPU time 3.78 seconds
Started Mar 24 12:37:48 PM PDT 24
Finished Mar 24 12:37:54 PM PDT 24
Peak memory 204588 kb
Host smart-e96f266c-c774-4af4-abc9-37b3707c1b1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727327818 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.1727327818
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.1044131920
Short name T65
Test name
Test status
Simulation time 343298150 ps
CPU time 5.09 seconds
Started Mar 24 12:38:14 PM PDT 24
Finished Mar 24 12:38:19 PM PDT 24
Peak memory 212764 kb
Host smart-9df4d279-7913-494d-a573-56b3cc6f3640
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044131920 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.1044131920
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3746259122
Short name T319
Test name
Test status
Simulation time 258433833 ps
CPU time 2.1 seconds
Started Mar 24 12:37:56 PM PDT 24
Finished Mar 24 12:37:58 PM PDT 24
Peak memory 215048 kb
Host smart-873708cb-2d19-4574-9b20-20100d37379c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746259122 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.3746259122
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.3074325358
Short name T325
Test name
Test status
Simulation time 38249205 ps
CPU time 2.11 seconds
Started Mar 24 12:37:35 PM PDT 24
Finished Mar 24 12:37:38 PM PDT 24
Peak memory 212772 kb
Host smart-661ea768-d52f-42df-bb68-dc048ae3a5f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074325358 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.3074325358
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2294650330
Short name T290
Test name
Test status
Simulation time 322650356 ps
CPU time 1.9 seconds
Started Mar 24 12:37:48 PM PDT 24
Finished Mar 24 12:37:52 PM PDT 24
Peak memory 204548 kb
Host smart-94a0ea3e-3ff0-4d66-840b-6fcc3f8ed7c9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294650330 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
2294650330
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.1327447082
Short name T281
Test name
Test status
Simulation time 39595733 ps
CPU time 0.68 seconds
Started Mar 24 12:37:47 PM PDT 24
Finished Mar 24 12:37:49 PM PDT 24
Peak memory 204288 kb
Host smart-6cf2814a-d131-4fe6-a9e6-1fce5a40f6b8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327447082 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
1327447082
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2510586311
Short name T99
Test name
Test status
Simulation time 150846080 ps
CPU time 3.51 seconds
Started Mar 24 12:38:07 PM PDT 24
Finished Mar 24 12:38:10 PM PDT 24
Peak memory 204712 kb
Host smart-8977654f-15d2-4198-87c3-b22aeab6982c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510586311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.2510586311
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.444433082
Short name T344
Test name
Test status
Simulation time 120659277 ps
CPU time 3.8 seconds
Started Mar 24 12:37:57 PM PDT 24
Finished Mar 24 12:38:01 PM PDT 24
Peak memory 212832 kb
Host smart-57a47462-ef0d-45a7-8a77-e7c8f42797a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444433082 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.444433082
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3299465918
Short name T73
Test name
Test status
Simulation time 1339253619 ps
CPU time 15.52 seconds
Started Mar 24 12:37:51 PM PDT 24
Finished Mar 24 12:38:07 PM PDT 24
Peak memory 212784 kb
Host smart-dcd06c70-51df-4822-a504-ae1bb559e647
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299465918 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.3
299465918
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.200800148
Short name T76
Test name
Test status
Simulation time 61192883 ps
CPU time 2.41 seconds
Started Mar 24 12:37:53 PM PDT 24
Finished Mar 24 12:37:56 PM PDT 24
Peak memory 218300 kb
Host smart-17c2ddd1-56c4-4d5a-86be-7a1de41fdfd8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200800148 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.200800148
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2028329856
Short name T331
Test name
Test status
Simulation time 53190967 ps
CPU time 1.54 seconds
Started Mar 24 12:37:38 PM PDT 24
Finished Mar 24 12:37:39 PM PDT 24
Peak memory 212732 kb
Host smart-e3a56ec2-e135-4fec-8a53-042489cd5d47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028329856 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.2028329856
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3091877135
Short name T248
Test name
Test status
Simulation time 360940462 ps
CPU time 2.03 seconds
Started Mar 24 12:37:58 PM PDT 24
Finished Mar 24 12:38:00 PM PDT 24
Peak memory 204588 kb
Host smart-6cd026b1-bd0f-43cc-8ffc-14aa7451433b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091877135 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
3091877135
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.4290628286
Short name T323
Test name
Test status
Simulation time 65051848 ps
CPU time 0.69 seconds
Started Mar 24 12:37:52 PM PDT 24
Finished Mar 24 12:37:53 PM PDT 24
Peak memory 204300 kb
Host smart-aac57ea5-ec38-4b84-a6fe-2417525622aa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290628286 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
4290628286
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.1290637793
Short name T97
Test name
Test status
Simulation time 216893737 ps
CPU time 4.11 seconds
Started Mar 24 12:37:41 PM PDT 24
Finished Mar 24 12:37:50 PM PDT 24
Peak memory 204608 kb
Host smart-2cc3130e-9002-4d09-9519-54e9750f8ecd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290637793 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.1290637793
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.1196222188
Short name T87
Test name
Test status
Simulation time 211089519 ps
CPU time 3.02 seconds
Started Mar 24 12:37:53 PM PDT 24
Finished Mar 24 12:37:56 PM PDT 24
Peak memory 212740 kb
Host smart-4694c1fd-73df-4e1f-8be1-def7f9e93c31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196222188 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.1196222188
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2709300394
Short name T124
Test name
Test status
Simulation time 1770233106 ps
CPU time 10.44 seconds
Started Mar 24 12:37:43 PM PDT 24
Finished Mar 24 12:37:54 PM PDT 24
Peak memory 212696 kb
Host smart-2531cc5a-4fa1-4489-89aa-344f5d8ef6f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709300394 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.2
709300394
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2133837086
Short name T268
Test name
Test status
Simulation time 2622105251 ps
CPU time 7.87 seconds
Started Mar 24 12:37:49 PM PDT 24
Finished Mar 24 12:37:58 PM PDT 24
Peak memory 218180 kb
Host smart-06ee643a-7213-4456-899c-27acd60056ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133837086 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.2133837086
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.4133058128
Short name T243
Test name
Test status
Simulation time 269854204 ps
CPU time 1.19 seconds
Started Mar 24 12:37:58 PM PDT 24
Finished Mar 24 12:38:00 PM PDT 24
Peak memory 204484 kb
Host smart-43539b86-df1b-4f9b-8270-9bdbc6b674f5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133058128 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
4133058128
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3281517901
Short name T254
Test name
Test status
Simulation time 62446235 ps
CPU time 0.81 seconds
Started Mar 24 12:37:53 PM PDT 24
Finished Mar 24 12:37:54 PM PDT 24
Peak memory 204304 kb
Host smart-528c8507-a4c2-4098-9f99-89c2faf6d00b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281517901 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
3281517901
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1251077797
Short name T306
Test name
Test status
Simulation time 2091767095 ps
CPU time 7.51 seconds
Started Mar 24 12:37:55 PM PDT 24
Finished Mar 24 12:38:03 PM PDT 24
Peak memory 204652 kb
Host smart-2da004ad-a5fd-4bf1-ad5c-47e1705782aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251077797 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.1251077797
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3897999641
Short name T305
Test name
Test status
Simulation time 333695053 ps
CPU time 3.03 seconds
Started Mar 24 12:37:37 PM PDT 24
Finished Mar 24 12:37:40 PM PDT 24
Peak memory 212832 kb
Host smart-b04b1d06-db46-4135-bc51-a6db37d547ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897999641 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.3897999641
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.1948597760
Short name T131
Test name
Test status
Simulation time 467164583 ps
CPU time 14.81 seconds
Started Mar 24 12:37:40 PM PDT 24
Finished Mar 24 12:37:55 PM PDT 24
Peak memory 220884 kb
Host smart-9c4e56fa-eb49-459b-aa09-57cebbff4db1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948597760 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.1
948597760
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.938854490
Short name T272
Test name
Test status
Simulation time 4068597638 ps
CPU time 5.44 seconds
Started Mar 24 12:38:00 PM PDT 24
Finished Mar 24 12:38:06 PM PDT 24
Peak memory 218008 kb
Host smart-42daa0d2-b910-4cf2-8f4c-530060387b49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938854490 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.938854490
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.3375334148
Short name T276
Test name
Test status
Simulation time 54250242 ps
CPU time 1.54 seconds
Started Mar 24 12:37:46 PM PDT 24
Finished Mar 24 12:37:49 PM PDT 24
Peak memory 217964 kb
Host smart-79985794-ef68-464d-a677-1597b94dca7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375334148 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.3375334148
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.218033981
Short name T320
Test name
Test status
Simulation time 1239641177 ps
CPU time 4.91 seconds
Started Mar 24 12:37:37 PM PDT 24
Finished Mar 24 12:37:42 PM PDT 24
Peak memory 204908 kb
Host smart-1fef594a-0e7b-42e3-9219-846ac917555f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218033981 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.218033981
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.1338400879
Short name T258
Test name
Test status
Simulation time 145109301 ps
CPU time 0.89 seconds
Started Mar 24 12:37:53 PM PDT 24
Finished Mar 24 12:37:54 PM PDT 24
Peak memory 203988 kb
Host smart-db974de8-4ed6-4746-85fe-0277cd7981f0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338400879 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
1338400879
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.1869373455
Short name T116
Test name
Test status
Simulation time 4021275429 ps
CPU time 8.19 seconds
Started Mar 24 12:37:49 PM PDT 24
Finished Mar 24 12:37:59 PM PDT 24
Peak memory 204640 kb
Host smart-07eec165-a4df-4206-8cc8-3ece61c7ba68
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869373455 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.1869373455
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2139953527
Short name T133
Test name
Test status
Simulation time 669963396 ps
CPU time 10.48 seconds
Started Mar 24 12:38:00 PM PDT 24
Finished Mar 24 12:38:11 PM PDT 24
Peak memory 212868 kb
Host smart-aa0bc117-4131-4467-ab58-5492e6df4fc9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139953527 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.2
139953527
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.299856983
Short name T74
Test name
Test status
Simulation time 57160144 ps
CPU time 3.9 seconds
Started Mar 24 12:37:40 PM PDT 24
Finished Mar 24 12:37:44 PM PDT 24
Peak memory 221044 kb
Host smart-1b7ec142-e808-4e61-bf2f-e82c71c2c174
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299856983 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.299856983
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.122693454
Short name T84
Test name
Test status
Simulation time 40915863 ps
CPU time 2.24 seconds
Started Mar 24 12:37:41 PM PDT 24
Finished Mar 24 12:37:43 PM PDT 24
Peak memory 212768 kb
Host smart-8ca67645-5358-4e3e-8556-08131796d474
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122693454 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.122693454
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.179349443
Short name T342
Test name
Test status
Simulation time 271807803 ps
CPU time 1.73 seconds
Started Mar 24 12:37:58 PM PDT 24
Finished Mar 24 12:38:00 PM PDT 24
Peak memory 204508 kb
Host smart-088e7ba2-1769-494e-9609-4bbfd9d9f7d2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179349443 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.179349443
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.646135626
Short name T255
Test name
Test status
Simulation time 39059421 ps
CPU time 0.75 seconds
Started Mar 24 12:37:48 PM PDT 24
Finished Mar 24 12:37:51 PM PDT 24
Peak memory 204308 kb
Host smart-8b1f7230-51eb-4440-8965-85cf89e973d2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646135626 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.646135626
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.7329786
Short name T113
Test name
Test status
Simulation time 425419282 ps
CPU time 4.35 seconds
Started Mar 24 12:37:53 PM PDT 24
Finished Mar 24 12:37:58 PM PDT 24
Peak memory 204980 kb
Host smart-fed7fe78-9d08-4cc1-9779-7fe21ab052f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7329786 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same_cs
r_outstanding.7329786
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.1964572953
Short name T130
Test name
Test status
Simulation time 948968420 ps
CPU time 5.06 seconds
Started Mar 24 12:38:01 PM PDT 24
Finished Mar 24 12:38:06 PM PDT 24
Peak memory 212904 kb
Host smart-0510f264-47c9-4180-ac51-091c68120d19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964572953 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.1964572953
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.325164669
Short name T35
Test name
Test status
Simulation time 116444507 ps
CPU time 4.2 seconds
Started Mar 24 12:37:49 PM PDT 24
Finished Mar 24 12:37:54 PM PDT 24
Peak memory 219412 kb
Host smart-f6baabb4-1118-4de7-ac7e-122ef67365dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325164669 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.325164669
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.331114572
Short name T107
Test name
Test status
Simulation time 173161197 ps
CPU time 2.24 seconds
Started Mar 24 12:38:11 PM PDT 24
Finished Mar 24 12:38:14 PM PDT 24
Peak memory 218720 kb
Host smart-a43654dc-4532-4306-aad4-9499b243694f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331114572 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.331114572
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.4264725863
Short name T292
Test name
Test status
Simulation time 534340460 ps
CPU time 2.54 seconds
Started Mar 24 12:37:56 PM PDT 24
Finished Mar 24 12:37:59 PM PDT 24
Peak memory 204460 kb
Host smart-03b1ba7a-b306-4742-b659-ecef1928c8fa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264725863 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
4264725863
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2208420706
Short name T332
Test name
Test status
Simulation time 33960604 ps
CPU time 0.73 seconds
Started Mar 24 12:37:43 PM PDT 24
Finished Mar 24 12:37:44 PM PDT 24
Peak memory 204320 kb
Host smart-bd124d01-0883-4b3a-9262-ec7c0d59e6b7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208420706 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
2208420706
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.3480409471
Short name T83
Test name
Test status
Simulation time 221452946 ps
CPU time 4.12 seconds
Started Mar 24 12:37:49 PM PDT 24
Finished Mar 24 12:37:54 PM PDT 24
Peak memory 204628 kb
Host smart-0284925a-bbcd-4522-82ef-8366a5075cbc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480409471 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.3480409471
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3891797203
Short name T352
Test name
Test status
Simulation time 143039203 ps
CPU time 3.29 seconds
Started Mar 24 12:37:50 PM PDT 24
Finished Mar 24 12:37:54 PM PDT 24
Peak memory 215604 kb
Host smart-2a9beb38-7a36-46e1-8424-9a3cfdc894ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891797203 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.3891797203
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.1585271391
Short name T138
Test name
Test status
Simulation time 470436904 ps
CPU time 15.47 seconds
Started Mar 24 12:38:14 PM PDT 24
Finished Mar 24 12:38:30 PM PDT 24
Peak memory 212796 kb
Host smart-0f4188ab-76b1-4e48-b0d1-0179bdfbc6fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585271391 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.1
585271391
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.464405567
Short name T336
Test name
Test status
Simulation time 9641704606 ps
CPU time 35.74 seconds
Started Mar 24 12:37:38 PM PDT 24
Finished Mar 24 12:38:13 PM PDT 24
Peak memory 204632 kb
Host smart-38cc70ed-d7a6-42e5-9ddc-d4fc922b265f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464405567 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.rv_dm_csr_aliasing.464405567
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2560097358
Short name T105
Test name
Test status
Simulation time 10816666446 ps
CPU time 53.92 seconds
Started Mar 24 12:37:59 PM PDT 24
Finished Mar 24 12:38:53 PM PDT 24
Peak memory 204640 kb
Host smart-4f9d1a99-9211-43c7-8963-99773dac4b1a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560097358 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.2560097358
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3256053094
Short name T95
Test name
Test status
Simulation time 57834785 ps
CPU time 2.23 seconds
Started Mar 24 12:37:41 PM PDT 24
Finished Mar 24 12:37:43 PM PDT 24
Peak memory 212852 kb
Host smart-32044d1e-c975-4e35-8da4-29a47a606840
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256053094 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.3256053094
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.4139402181
Short name T321
Test name
Test status
Simulation time 164435984 ps
CPU time 3.76 seconds
Started Mar 24 12:37:34 PM PDT 24
Finished Mar 24 12:37:38 PM PDT 24
Peak memory 218180 kb
Host smart-d062b743-edad-42c6-92ea-ee693e1c4b72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139402181 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.4139402181
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3178691728
Short name T108
Test name
Test status
Simulation time 70864478 ps
CPU time 1.42 seconds
Started Mar 24 12:37:52 PM PDT 24
Finished Mar 24 12:37:54 PM PDT 24
Peak memory 212792 kb
Host smart-030a97fb-c6fb-4008-a6d8-9c6a93e829f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178691728 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.3178691728
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.1856317237
Short name T308
Test name
Test status
Simulation time 13652176728 ps
CPU time 41.68 seconds
Started Mar 24 12:37:34 PM PDT 24
Finished Mar 24 12:38:16 PM PDT 24
Peak memory 204572 kb
Host smart-7b23ab4a-edd2-43eb-bcbc-9d9cd5dcd8ac
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856317237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.1856317237
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.2135329609
Short name T313
Test name
Test status
Simulation time 21709026570 ps
CPU time 39.12 seconds
Started Mar 24 12:37:36 PM PDT 24
Finished Mar 24 12:38:15 PM PDT 24
Peak memory 204544 kb
Host smart-dc261f82-ed36-42d0-852c-4776a6179bf0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135329609 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_bit_bash.2135329609
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.1091715391
Short name T259
Test name
Test status
Simulation time 597931758 ps
CPU time 2.41 seconds
Started Mar 24 12:37:34 PM PDT 24
Finished Mar 24 12:37:36 PM PDT 24
Peak memory 204532 kb
Host smart-96becd63-4d01-46b3-bf37-ad5b56c1c4f9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091715391 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.1091715391
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1428520452
Short name T315
Test name
Test status
Simulation time 705353867 ps
CPU time 1.58 seconds
Started Mar 24 12:37:42 PM PDT 24
Finished Mar 24 12:37:43 PM PDT 24
Peak memory 204544 kb
Host smart-c7aeae1b-a52d-4bd3-ae23-87fe06aa9ff1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428520452 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.1
428520452
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.2166523572
Short name T330
Test name
Test status
Simulation time 82158672 ps
CPU time 0.75 seconds
Started Mar 24 12:37:40 PM PDT 24
Finished Mar 24 12:37:41 PM PDT 24
Peak memory 204284 kb
Host smart-4cd93369-584d-426a-ab0b-9305af92f679
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166523572 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_aliasing.2166523572
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.22381693
Short name T273
Test name
Test status
Simulation time 1144352114 ps
CPU time 3.12 seconds
Started Mar 24 12:38:11 PM PDT 24
Finished Mar 24 12:38:14 PM PDT 24
Peak memory 204444 kb
Host smart-9ce2e66f-1120-411b-b283-6aa76c4c0e76
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22381693 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_
bit_bash.22381693
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1187721233
Short name T244
Test name
Test status
Simulation time 167975288 ps
CPU time 1.18 seconds
Started Mar 24 12:37:34 PM PDT 24
Finished Mar 24 12:37:35 PM PDT 24
Peak memory 204272 kb
Host smart-e6aaa609-b6f7-41f2-b45b-ef8ce9685b7b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187721233 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.1187721233
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.531416351
Short name T257
Test name
Test status
Simulation time 31585381 ps
CPU time 0.66 seconds
Started Mar 24 12:37:52 PM PDT 24
Finished Mar 24 12:37:53 PM PDT 24
Peak memory 204244 kb
Host smart-e527ae56-3d89-493f-a875-80cc7030080d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531416351 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.531416351
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1696569069
Short name T282
Test name
Test status
Simulation time 154601857 ps
CPU time 0.72 seconds
Started Mar 24 12:37:28 PM PDT 24
Finished Mar 24 12:37:28 PM PDT 24
Peak memory 204304 kb
Host smart-07896fbb-082c-4233-abe5-081065083b1b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696569069 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.1696569069
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.1145279497
Short name T303
Test name
Test status
Simulation time 127517011 ps
CPU time 0.68 seconds
Started Mar 24 12:37:45 PM PDT 24
Finished Mar 24 12:37:47 PM PDT 24
Peak memory 204328 kb
Host smart-39ed01da-5a61-42c0-b7f0-431ccb5b3f31
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145279497 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.1145279497
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.2824200746
Short name T369
Test name
Test status
Simulation time 150403964 ps
CPU time 6.45 seconds
Started Mar 24 12:37:23 PM PDT 24
Finished Mar 24 12:37:29 PM PDT 24
Peak memory 204568 kb
Host smart-8eb62c31-1cca-4bcd-8a69-36f803e1d06f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824200746 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.2824200746
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.3009642482
Short name T326
Test name
Test status
Simulation time 1576341758 ps
CPU time 10 seconds
Started Mar 24 12:37:47 PM PDT 24
Finished Mar 24 12:37:59 PM PDT 24
Peak memory 220936 kb
Host smart-2f433b6c-3faa-4f96-982b-67bc8a4803ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009642482 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.3009642482
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/24.rv_dm_tap_fsm_rand_reset.1751591055
Short name T286
Test name
Test status
Simulation time 8421491695 ps
CPU time 14.15 seconds
Started Mar 24 12:37:55 PM PDT 24
Finished Mar 24 12:38:10 PM PDT 24
Peak memory 213584 kb
Host smart-49f9d042-2301-4db4-ae55-f976dea3428f
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751591055 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 24.rv_dm_tap_fsm_rand_reset.1751591055
Directory /workspace/24.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/25.rv_dm_tap_fsm_rand_reset.3227301346
Short name T346
Test name
Test status
Simulation time 7130647053 ps
CPU time 13.7 seconds
Started Mar 24 12:37:48 PM PDT 24
Finished Mar 24 12:38:04 PM PDT 24
Peak memory 220088 kb
Host smart-9de9ac43-f876-45ea-8b66-0d35ab27268f
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227301346 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 25.rv_dm_tap_fsm_rand_reset.3227301346
Directory /workspace/25.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/27.rv_dm_tap_fsm_rand_reset.2764826923
Short name T299
Test name
Test status
Simulation time 25030913476 ps
CPU time 21.38 seconds
Started Mar 24 12:37:50 PM PDT 24
Finished Mar 24 12:38:12 PM PDT 24
Peak memory 220976 kb
Host smart-f8dfe2b4-1b54-4e94-9ff8-2f5e82f2510a
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764826923 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 27.rv_dm_tap_fsm_rand_reset.2764826923
Directory /workspace/27.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/29.rv_dm_tap_fsm_rand_reset.921875472
Short name T122
Test name
Test status
Simulation time 7579746046 ps
CPU time 14.21 seconds
Started Mar 24 12:37:57 PM PDT 24
Finished Mar 24 12:38:12 PM PDT 24
Peak memory 219132 kb
Host smart-6740fd38-6411-4a1f-808b-ee69efc91620
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921875472 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 29.rv_dm_tap_fsm_rand_reset.921875472
Directory /workspace/29.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.3226202108
Short name T104
Test name
Test status
Simulation time 1877932609 ps
CPU time 30.92 seconds
Started Mar 24 12:37:41 PM PDT 24
Finished Mar 24 12:38:12 PM PDT 24
Peak memory 204552 kb
Host smart-0bb946fb-7b3d-4fe3-8bc5-27ba04b574f3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226202108 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.3226202108
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.570029259
Short name T294
Test name
Test status
Simulation time 1443641816 ps
CPU time 27.67 seconds
Started Mar 24 12:37:40 PM PDT 24
Finished Mar 24 12:38:08 PM PDT 24
Peak memory 204580 kb
Host smart-b962d387-8132-4415-b64d-1e9b0f3bc640
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570029259 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.570029259
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.599182806
Short name T365
Test name
Test status
Simulation time 86633356 ps
CPU time 2.07 seconds
Started Mar 24 12:37:37 PM PDT 24
Finished Mar 24 12:37:39 PM PDT 24
Peak memory 212824 kb
Host smart-24403db3-554b-41a6-815f-f88423da93e0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599182806 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.599182806
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1540621131
Short name T279
Test name
Test status
Simulation time 2024983631 ps
CPU time 3.71 seconds
Started Mar 24 12:37:37 PM PDT 24
Finished Mar 24 12:37:41 PM PDT 24
Peak memory 217108 kb
Host smart-b04762f0-5846-40a5-a353-5e4a226f17f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540621131 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.1540621131
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2165016050
Short name T350
Test name
Test status
Simulation time 61499057 ps
CPU time 1.46 seconds
Started Mar 24 12:37:35 PM PDT 24
Finished Mar 24 12:37:37 PM PDT 24
Peak memory 212724 kb
Host smart-da9219a3-ab6a-4218-9b17-ed8da76fb97f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165016050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.2165016050
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.2612490750
Short name T363
Test name
Test status
Simulation time 3098039531 ps
CPU time 9.99 seconds
Started Mar 24 12:37:39 PM PDT 24
Finished Mar 24 12:37:49 PM PDT 24
Peak memory 204648 kb
Host smart-f34d8732-380c-4b54-b091-e891add72164
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612490750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.2612490750
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.740763909
Short name T339
Test name
Test status
Simulation time 15389252968 ps
CPU time 41.88 seconds
Started Mar 24 12:37:30 PM PDT 24
Finished Mar 24 12:38:12 PM PDT 24
Peak memory 204524 kb
Host smart-aae22ce7-5020-4099-b122-56d2e3efa9aa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740763909 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr
_bit_bash.740763909
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.821255361
Short name T253
Test name
Test status
Simulation time 2298157032 ps
CPU time 3.05 seconds
Started Mar 24 12:37:43 PM PDT 24
Finished Mar 24 12:37:47 PM PDT 24
Peak memory 204568 kb
Host smart-db2ebe8d-059e-4107-ae0e-b2a335e9d4ce
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821255361 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr
_hw_reset.821255361
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.227795684
Short name T304
Test name
Test status
Simulation time 1594918169 ps
CPU time 5.19 seconds
Started Mar 24 12:37:24 PM PDT 24
Finished Mar 24 12:37:35 PM PDT 24
Peak memory 204456 kb
Host smart-a773a339-6ba5-49e4-9ddb-6802db8e7e51
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227795684 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.227795684
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.2961835419
Short name T364
Test name
Test status
Simulation time 84800262 ps
CPU time 0.85 seconds
Started Mar 24 12:37:37 PM PDT 24
Finished Mar 24 12:37:37 PM PDT 24
Peak memory 204312 kb
Host smart-7c03734e-89a1-4bee-8361-5200987ed15c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961835419 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.2961835419
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.823324059
Short name T263
Test name
Test status
Simulation time 775457362 ps
CPU time 2.09 seconds
Started Mar 24 12:37:36 PM PDT 24
Finished Mar 24 12:37:38 PM PDT 24
Peak memory 204484 kb
Host smart-b8c022c6-5174-4858-b917-a85947a4d895
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823324059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr
_bit_bash.823324059
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.2277469913
Short name T246
Test name
Test status
Simulation time 110214641 ps
CPU time 0.75 seconds
Started Mar 24 12:37:29 PM PDT 24
Finished Mar 24 12:37:30 PM PDT 24
Peak memory 204312 kb
Host smart-43793dcb-ce73-4546-8dd8-0bdc18c92a53
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277469913 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.2277469913
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.3280154248
Short name T288
Test name
Test status
Simulation time 60429174 ps
CPU time 0.76 seconds
Started Mar 24 12:37:47 PM PDT 24
Finished Mar 24 12:37:50 PM PDT 24
Peak memory 204304 kb
Host smart-07842591-27be-4f1d-93eb-435801a14f8e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280154248 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.3
280154248
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.3361870490
Short name T289
Test name
Test status
Simulation time 195579306 ps
CPU time 0.65 seconds
Started Mar 24 12:37:42 PM PDT 24
Finished Mar 24 12:37:44 PM PDT 24
Peak memory 204316 kb
Host smart-9cbb2b18-e9a1-4749-8214-ef76b518903f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361870490 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.3361870490
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1247933564
Short name T260
Test name
Test status
Simulation time 39725444 ps
CPU time 0.65 seconds
Started Mar 24 12:37:50 PM PDT 24
Finished Mar 24 12:37:51 PM PDT 24
Peak memory 204392 kb
Host smart-fc1cbfdc-8ebb-4ae4-b6f1-74a3d1a9a242
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247933564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.1247933564
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.4167848946
Short name T285
Test name
Test status
Simulation time 558975436 ps
CPU time 6.41 seconds
Started Mar 24 12:37:42 PM PDT 24
Finished Mar 24 12:37:48 PM PDT 24
Peak memory 204576 kb
Host smart-1a2a2d9d-761e-4b00-9c6d-c0dfa8d72469
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167848946 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.4167848946
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.4221809028
Short name T296
Test name
Test status
Simulation time 29451456567 ps
CPU time 28.72 seconds
Started Mar 24 12:37:44 PM PDT 24
Finished Mar 24 12:38:14 PM PDT 24
Peak memory 229216 kb
Host smart-31c07d81-9ab5-437d-83d5-9137c111d8a9
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221809028 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.4221809028
Directory /workspace/3.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.354885252
Short name T277
Test name
Test status
Simulation time 242902596 ps
CPU time 3.19 seconds
Started Mar 24 12:37:39 PM PDT 24
Finished Mar 24 12:37:43 PM PDT 24
Peak memory 212808 kb
Host smart-dbf4397f-1182-46c9-b1a1-4537fdb34d27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354885252 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.354885252
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.377308770
Short name T137
Test name
Test status
Simulation time 2922063339 ps
CPU time 10.02 seconds
Started Mar 24 12:37:39 PM PDT 24
Finished Mar 24 12:37:50 PM PDT 24
Peak memory 212852 kb
Host smart-a3cf2484-12e7-4858-8410-069e4f235a54
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377308770 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.377308770
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/32.rv_dm_tap_fsm_rand_reset.3077774432
Short name T345
Test name
Test status
Simulation time 7843329192 ps
CPU time 15.98 seconds
Started Mar 24 12:37:49 PM PDT 24
Finished Mar 24 12:38:06 PM PDT 24
Peak memory 221060 kb
Host smart-8351cf1d-b9d9-4886-b528-d90f3f9d68c6
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077774432 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 32.rv_dm_tap_fsm_rand_reset.3077774432
Directory /workspace/32.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/36.rv_dm_tap_fsm_rand_reset.67168296
Short name T300
Test name
Test status
Simulation time 8289255007 ps
CPU time 14.37 seconds
Started Mar 24 12:37:47 PM PDT 24
Finished Mar 24 12:38:03 PM PDT 24
Peak memory 214212 kb
Host smart-8491719f-4651-40c2-9ef5-36be5b26ebfe
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67168296 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 36.rv_dm_tap_fsm_rand_reset.67168296
Directory /workspace/36.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/37.rv_dm_tap_fsm_rand_reset.4078439580
Short name T125
Test name
Test status
Simulation time 5388110960 ps
CPU time 17.9 seconds
Started Mar 24 12:38:06 PM PDT 24
Finished Mar 24 12:38:24 PM PDT 24
Peak memory 218636 kb
Host smart-f721e9c0-5220-40ef-bfb2-d7a56ca46a16
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078439580 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 37.rv_dm_tap_fsm_rand_reset.4078439580
Directory /workspace/37.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.3887925478
Short name T340
Test name
Test status
Simulation time 6236937360 ps
CPU time 31.23 seconds
Started Mar 24 12:37:47 PM PDT 24
Finished Mar 24 12:38:20 PM PDT 24
Peak memory 204624 kb
Host smart-2c6b9417-dd8e-40f6-8202-25a9988e6934
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887925478 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.3887925478
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.778771141
Short name T301
Test name
Test status
Simulation time 3214693813 ps
CPU time 26.78 seconds
Started Mar 24 12:37:46 PM PDT 24
Finished Mar 24 12:38:14 PM PDT 24
Peak memory 204636 kb
Host smart-89653b54-c39c-480c-87f1-dd107084e49c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778771141 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.778771141
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.547010036
Short name T41
Test name
Test status
Simulation time 55804125 ps
CPU time 1.62 seconds
Started Mar 24 12:37:45 PM PDT 24
Finished Mar 24 12:37:48 PM PDT 24
Peak memory 212764 kb
Host smart-8e2630df-add7-492d-924f-d70cf82d2c09
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547010036 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.547010036
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.1503852799
Short name T66
Test name
Test status
Simulation time 1740500513 ps
CPU time 6.9 seconds
Started Mar 24 12:37:39 PM PDT 24
Finished Mar 24 12:37:47 PM PDT 24
Peak memory 220992 kb
Host smart-b5ec0d63-7989-463f-bc10-e311fb4a6059
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503852799 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.1503852799
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.3328572215
Short name T80
Test name
Test status
Simulation time 148418405 ps
CPU time 2.12 seconds
Started Mar 24 12:37:44 PM PDT 24
Finished Mar 24 12:37:48 PM PDT 24
Peak memory 218288 kb
Host smart-cc78a2de-9877-4ebc-8fa2-d0021d352abf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328572215 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.3328572215
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2891965988
Short name T250
Test name
Test status
Simulation time 3822815909 ps
CPU time 13.13 seconds
Started Mar 24 12:37:54 PM PDT 24
Finished Mar 24 12:38:07 PM PDT 24
Peak memory 204564 kb
Host smart-799b133e-e5a8-4ded-b460-48fa28750627
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891965988 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.2891965988
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.1942868906
Short name T329
Test name
Test status
Simulation time 14485057705 ps
CPU time 29.77 seconds
Started Mar 24 12:37:38 PM PDT 24
Finished Mar 24 12:38:08 PM PDT 24
Peak memory 204576 kb
Host smart-2e3b2203-bc83-4c74-bbc1-18e56f40d889
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942868906 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_bit_bash.1942868906
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.4098933789
Short name T91
Test name
Test status
Simulation time 1612671571 ps
CPU time 5.88 seconds
Started Mar 24 12:37:30 PM PDT 24
Finished Mar 24 12:37:36 PM PDT 24
Peak memory 204588 kb
Host smart-985d6777-6a41-424b-b319-0551b3271037
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098933789 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.4098933789
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.2759928024
Short name T247
Test name
Test status
Simulation time 1046969888 ps
CPU time 4.14 seconds
Started Mar 24 12:37:44 PM PDT 24
Finished Mar 24 12:37:50 PM PDT 24
Peak memory 204504 kb
Host smart-743d6d19-d488-465f-a920-52d66daae18c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759928024 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.2
759928024
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.1700386915
Short name T293
Test name
Test status
Simulation time 52630270 ps
CPU time 0.77 seconds
Started Mar 24 12:37:37 PM PDT 24
Finished Mar 24 12:37:38 PM PDT 24
Peak memory 204328 kb
Host smart-85d38d54-fc5d-4d33-80cb-8a70fd4086af
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700386915 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.1700386915
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.3390864680
Short name T280
Test name
Test status
Simulation time 2266745395 ps
CPU time 2.85 seconds
Started Mar 24 12:37:29 PM PDT 24
Finished Mar 24 12:37:32 PM PDT 24
Peak memory 204640 kb
Host smart-9e33b8ce-85bd-4086-9305-49de46e2a1ab
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390864680 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.3390864680
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.88619508
Short name T362
Test name
Test status
Simulation time 44277799 ps
CPU time 0.76 seconds
Started Mar 24 12:37:20 PM PDT 24
Finished Mar 24 12:37:22 PM PDT 24
Peak memory 204256 kb
Host smart-a3bb889c-dd19-4b44-b2ae-9d5d6ae63246
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88619508 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_
hw_reset.88619508
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2819331509
Short name T59
Test name
Test status
Simulation time 77323440 ps
CPU time 0.75 seconds
Started Mar 24 12:37:42 PM PDT 24
Finished Mar 24 12:37:43 PM PDT 24
Peak memory 204304 kb
Host smart-7d061a27-88dc-47f5-b3ee-930efb5966cb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819331509 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.2
819331509
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.463216366
Short name T275
Test name
Test status
Simulation time 25752055 ps
CPU time 0.69 seconds
Started Mar 24 12:37:31 PM PDT 24
Finished Mar 24 12:37:33 PM PDT 24
Peak memory 204324 kb
Host smart-ab069cb6-23fb-41be-a86f-6b2da22e71ab
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463216366 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_part
ial_access.463216366
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.1103420077
Short name T245
Test name
Test status
Simulation time 24661476 ps
CPU time 0.66 seconds
Started Mar 24 12:37:35 PM PDT 24
Finished Mar 24 12:37:35 PM PDT 24
Peak memory 204336 kb
Host smart-b7e25d88-6e36-4dc1-b796-e355bb6cac03
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103420077 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.1103420077
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3244424101
Short name T100
Test name
Test status
Simulation time 744766890 ps
CPU time 7.39 seconds
Started Mar 24 12:37:48 PM PDT 24
Finished Mar 24 12:37:57 PM PDT 24
Peak memory 204532 kb
Host smart-ae137559-1610-4caa-8b9c-6b4673e51e4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244424101 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.3244424101
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.3313783152
Short name T361
Test name
Test status
Simulation time 311092127 ps
CPU time 4.82 seconds
Started Mar 24 12:37:56 PM PDT 24
Finished Mar 24 12:38:01 PM PDT 24
Peak memory 212828 kb
Host smart-27afaf7f-bcad-4c48-88ad-ff10c571cf85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313783152 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.3313783152
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.2137591595
Short name T136
Test name
Test status
Simulation time 2920701688 ps
CPU time 15.57 seconds
Started Mar 24 12:37:46 PM PDT 24
Finished Mar 24 12:38:03 PM PDT 24
Peak memory 212892 kb
Host smart-dce10b04-c856-4465-ae95-f5f555c9731e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137591595 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.2137591595
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.20670924
Short name T265
Test name
Test status
Simulation time 59783203 ps
CPU time 3.89 seconds
Started Mar 24 12:37:41 PM PDT 24
Finished Mar 24 12:37:45 PM PDT 24
Peak memory 220816 kb
Host smart-77a020db-c66a-4f15-9107-21166386ccf5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20670924 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.20670924
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.170414469
Short name T86
Test name
Test status
Simulation time 607009761 ps
CPU time 1.57 seconds
Started Mar 24 12:37:56 PM PDT 24
Finished Mar 24 12:37:58 PM PDT 24
Peak memory 212728 kb
Host smart-2ce16706-2a7f-48b8-8a34-7dbd3b9aa1ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170414469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.170414469
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.2600738189
Short name T270
Test name
Test status
Simulation time 1448104221 ps
CPU time 1.39 seconds
Started Mar 24 12:37:47 PM PDT 24
Finished Mar 24 12:37:50 PM PDT 24
Peak memory 204512 kb
Host smart-82d3db2e-950f-4c42-a2cf-03cf223f0586
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600738189 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.2
600738189
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.58882862
Short name T367
Test name
Test status
Simulation time 107512601 ps
CPU time 0.74 seconds
Started Mar 24 12:37:22 PM PDT 24
Finished Mar 24 12:37:23 PM PDT 24
Peak memory 204272 kb
Host smart-b1933198-31f3-49bb-bf3f-3cd438cab7b2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58882862 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.58882862
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1401703862
Short name T112
Test name
Test status
Simulation time 143796169 ps
CPU time 6.1 seconds
Started Mar 24 12:37:54 PM PDT 24
Finished Mar 24 12:38:01 PM PDT 24
Peak memory 204516 kb
Host smart-43076768-4381-4478-8d43-13613c83a81c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401703862 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.1401703862
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.1499096101
Short name T274
Test name
Test status
Simulation time 272956735 ps
CPU time 2.32 seconds
Started Mar 24 12:37:30 PM PDT 24
Finished Mar 24 12:37:33 PM PDT 24
Peak memory 212732 kb
Host smart-bd159de8-4d8d-40ac-ad3b-0353d98c457b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499096101 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.1499096101
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3164707637
Short name T132
Test name
Test status
Simulation time 4010251954 ps
CPU time 20.36 seconds
Started Mar 24 12:37:40 PM PDT 24
Finished Mar 24 12:38:01 PM PDT 24
Peak memory 220988 kb
Host smart-00af706d-f709-4664-8b9b-d37a3eb7ca3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164707637 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.3164707637
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2602525319
Short name T338
Test name
Test status
Simulation time 4069163008 ps
CPU time 3.87 seconds
Started Mar 24 12:37:45 PM PDT 24
Finished Mar 24 12:37:50 PM PDT 24
Peak memory 216916 kb
Host smart-7ee7dbdd-5bce-4b4d-b1d0-01e40e3eb5fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602525319 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.2602525319
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1341711013
Short name T85
Test name
Test status
Simulation time 187178731 ps
CPU time 1.54 seconds
Started Mar 24 12:37:47 PM PDT 24
Finished Mar 24 12:37:51 PM PDT 24
Peak memory 212828 kb
Host smart-b192a9a7-5ae1-4432-bad3-07d11e386232
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341711013 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.1341711013
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2377326555
Short name T360
Test name
Test status
Simulation time 177519076 ps
CPU time 0.86 seconds
Started Mar 24 12:37:42 PM PDT 24
Finished Mar 24 12:37:43 PM PDT 24
Peak memory 204480 kb
Host smart-a4775d94-631a-45a8-9412-b9f8a337f722
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377326555 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.2
377326555
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.3337402652
Short name T284
Test name
Test status
Simulation time 66076195 ps
CPU time 0.83 seconds
Started Mar 24 12:37:41 PM PDT 24
Finished Mar 24 12:37:42 PM PDT 24
Peak memory 204292 kb
Host smart-a106ff7f-9511-4833-9f6c-5d12bd7622f3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337402652 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.3
337402652
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.1851737127
Short name T110
Test name
Test status
Simulation time 79709767 ps
CPU time 3.45 seconds
Started Mar 24 12:38:02 PM PDT 24
Finished Mar 24 12:38:05 PM PDT 24
Peak memory 204560 kb
Host smart-0c256ca6-1d08-49b7-9e6b-05f82442ec94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851737127 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.1851737127
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.2379765986
Short name T36
Test name
Test status
Simulation time 14284984307 ps
CPU time 14.35 seconds
Started Mar 24 12:37:50 PM PDT 24
Finished Mar 24 12:38:05 PM PDT 24
Peak memory 214508 kb
Host smart-8654c4eb-ef07-4a7f-a677-75ea250b9ab4
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379765986 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.2379765986
Directory /workspace/6.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.2384898268
Short name T262
Test name
Test status
Simulation time 2182249473 ps
CPU time 5.79 seconds
Started Mar 24 12:37:25 PM PDT 24
Finished Mar 24 12:37:31 PM PDT 24
Peak memory 212840 kb
Host smart-c4068c94-ac49-4050-985d-f9049e2a5464
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384898268 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.2384898268
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.4028724162
Short name T135
Test name
Test status
Simulation time 1026032248 ps
CPU time 19.24 seconds
Started Mar 24 12:37:44 PM PDT 24
Finished Mar 24 12:38:05 PM PDT 24
Peak memory 221028 kb
Host smart-b0f5e4cc-4279-4ff2-b2b6-6b97cb4b9714
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028724162 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.4028724162
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.270147251
Short name T72
Test name
Test status
Simulation time 2475674598 ps
CPU time 6.27 seconds
Started Mar 24 12:37:50 PM PDT 24
Finished Mar 24 12:37:57 PM PDT 24
Peak memory 219288 kb
Host smart-24140c79-bade-4a69-a924-fea60bee3565
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270147251 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.270147251
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.2860397325
Short name T312
Test name
Test status
Simulation time 52816973 ps
CPU time 1.45 seconds
Started Mar 24 12:37:45 PM PDT 24
Finished Mar 24 12:37:48 PM PDT 24
Peak memory 212756 kb
Host smart-cdd0a4a3-56d3-47ca-bb60-35201195c776
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860397325 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.2860397325
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.958180450
Short name T242
Test name
Test status
Simulation time 365938611 ps
CPU time 1.13 seconds
Started Mar 24 12:37:30 PM PDT 24
Finished Mar 24 12:37:32 PM PDT 24
Peak memory 204456 kb
Host smart-0116ea3b-24e6-4ccf-adf8-da502e37b3cb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958180450 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.958180450
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1565246166
Short name T256
Test name
Test status
Simulation time 158411137 ps
CPU time 0.74 seconds
Started Mar 24 12:38:07 PM PDT 24
Finished Mar 24 12:38:07 PM PDT 24
Peak memory 204236 kb
Host smart-71e2326b-94a2-429c-847a-188024dafd94
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565246166 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.1
565246166
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3129057117
Short name T354
Test name
Test status
Simulation time 1600972158 ps
CPU time 8.32 seconds
Started Mar 24 12:38:02 PM PDT 24
Finished Mar 24 12:38:10 PM PDT 24
Peak memory 205004 kb
Host smart-d9fc45cb-0349-458f-9a49-85c50bcc0d87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129057117 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.3129057117
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.1568688405
Short name T337
Test name
Test status
Simulation time 12392112858 ps
CPU time 12.07 seconds
Started Mar 24 12:37:38 PM PDT 24
Finished Mar 24 12:37:50 PM PDT 24
Peak memory 214204 kb
Host smart-60a0e576-91ea-4545-8ac7-528fa751c32b
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568688405 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.1568688405
Directory /workspace/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.104781532
Short name T38
Test name
Test status
Simulation time 43065600 ps
CPU time 2.54 seconds
Started Mar 24 12:37:49 PM PDT 24
Finished Mar 24 12:37:53 PM PDT 24
Peak memory 212808 kb
Host smart-93af6a0d-61b1-4e9c-84e5-c5951200671e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104781532 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.104781532
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.3146605450
Short name T322
Test name
Test status
Simulation time 1733412651 ps
CPU time 9.35 seconds
Started Mar 24 12:37:38 PM PDT 24
Finished Mar 24 12:37:47 PM PDT 24
Peak memory 214952 kb
Host smart-ca20afb7-e57e-4edd-941e-41c20c016811
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146605450 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.3146605450
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.329309778
Short name T358
Test name
Test status
Simulation time 4463560018 ps
CPU time 11.02 seconds
Started Mar 24 12:37:40 PM PDT 24
Finished Mar 24 12:37:51 PM PDT 24
Peak memory 218836 kb
Host smart-2a2d2bc7-7302-48dd-8045-8116e3870ddf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329309778 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.329309778
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.672344871
Short name T356
Test name
Test status
Simulation time 184227767 ps
CPU time 1.58 seconds
Started Mar 24 12:37:44 PM PDT 24
Finished Mar 24 12:37:46 PM PDT 24
Peak memory 212792 kb
Host smart-88c649b0-00db-42e0-a1a1-8e36f8c66ac3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672344871 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.672344871
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.587737089
Short name T239
Test name
Test status
Simulation time 195028085 ps
CPU time 1.19 seconds
Started Mar 24 12:37:36 PM PDT 24
Finished Mar 24 12:37:37 PM PDT 24
Peak memory 204480 kb
Host smart-56c8e0d4-98c1-481e-8066-bb78cc834d7d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587737089 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.587737089
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.201290838
Short name T370
Test name
Test status
Simulation time 83614901 ps
CPU time 0.77 seconds
Started Mar 24 12:37:45 PM PDT 24
Finished Mar 24 12:37:47 PM PDT 24
Peak memory 204288 kb
Host smart-0aaaa912-0d5c-40d1-913e-1c9baf4df93d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201290838 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.201290838
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.3381385649
Short name T314
Test name
Test status
Simulation time 756100926 ps
CPU time 4.13 seconds
Started Mar 24 12:37:42 PM PDT 24
Finished Mar 24 12:37:47 PM PDT 24
Peak memory 204628 kb
Host smart-dc06777b-dc4f-4228-9b5b-b55dcbc3e642
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381385649 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_
csr_outstanding.3381385649
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.4155350557
Short name T353
Test name
Test status
Simulation time 64910066 ps
CPU time 3.66 seconds
Started Mar 24 12:37:37 PM PDT 24
Finished Mar 24 12:37:41 PM PDT 24
Peak memory 212832 kb
Host smart-828dd2cf-799e-4211-8311-f6590fa927ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155350557 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.4155350557
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.546014554
Short name T75
Test name
Test status
Simulation time 1123202193 ps
CPU time 9.8 seconds
Started Mar 24 12:37:41 PM PDT 24
Finished Mar 24 12:37:50 PM PDT 24
Peak memory 212768 kb
Host smart-6a482c47-cfe0-4011-9349-4172acc7c044
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546014554 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.546014554
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.4099521560
Short name T327
Test name
Test status
Simulation time 4093453194 ps
CPU time 3.28 seconds
Started Mar 24 12:37:39 PM PDT 24
Finished Mar 24 12:37:43 PM PDT 24
Peak memory 214736 kb
Host smart-a6fb69af-84b6-4945-85a1-593e6e0c278d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099521560 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.4099521560
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.64410491
Short name T333
Test name
Test status
Simulation time 39414316 ps
CPU time 2.09 seconds
Started Mar 24 12:37:45 PM PDT 24
Finished Mar 24 12:37:48 PM PDT 24
Peak memory 212764 kb
Host smart-b31d8f59-6a85-489e-bc48-0ffd3f3941d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64410491 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.64410491
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3050074047
Short name T357
Test name
Test status
Simulation time 312797257 ps
CPU time 1.88 seconds
Started Mar 24 12:37:36 PM PDT 24
Finished Mar 24 12:37:38 PM PDT 24
Peak memory 204648 kb
Host smart-3caf6f28-e82a-462d-b097-7b9c08a1a81e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050074047 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.3
050074047
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.4081975004
Short name T307
Test name
Test status
Simulation time 91685829 ps
CPU time 0.77 seconds
Started Mar 24 12:37:18 PM PDT 24
Finished Mar 24 12:37:22 PM PDT 24
Peak memory 204708 kb
Host smart-17bec2e8-02ec-4710-b021-99b8109c49d1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081975004 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.4
081975004
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.911077566
Short name T102
Test name
Test status
Simulation time 79771104 ps
CPU time 3.5 seconds
Started Mar 24 12:37:40 PM PDT 24
Finished Mar 24 12:37:44 PM PDT 24
Peak memory 204576 kb
Host smart-1076ecc8-559b-481e-a12f-fd17399d972b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911077566 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_c
sr_outstanding.911077566
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.125576314
Short name T298
Test name
Test status
Simulation time 660408719 ps
CPU time 4.24 seconds
Started Mar 24 12:37:51 PM PDT 24
Finished Mar 24 12:37:55 PM PDT 24
Peak memory 212772 kb
Host smart-34fec0ec-ee68-42e9-acbd-042225e3eb1e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125576314 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.125576314
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.1633792663
Short name T160
Test name
Test status
Simulation time 51129735 ps
CPU time 0.69 seconds
Started Mar 24 12:38:04 PM PDT 24
Finished Mar 24 12:38:05 PM PDT 24
Peak memory 204652 kb
Host smart-10b8709c-188d-42a4-941f-3d360a799cd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633792663 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.1633792663
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.4200366878
Short name T13
Test name
Test status
Simulation time 3446654435 ps
CPU time 10.43 seconds
Started Mar 24 12:37:48 PM PDT 24
Finished Mar 24 12:38:00 PM PDT 24
Peak memory 204988 kb
Host smart-b5d853c4-3c16-422e-8b78-39291535bdd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200366878 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.4200366878
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.111027691
Short name T142
Test name
Test status
Simulation time 1242603541 ps
CPU time 2.78 seconds
Started Mar 24 12:38:01 PM PDT 24
Finished Mar 24 12:38:04 PM PDT 24
Peak memory 204928 kb
Host smart-c82b22dd-531f-46a5-b74b-a7a82dbee34f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111027691 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.111027691
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.874223805
Short name T70
Test name
Test status
Simulation time 31170482 ps
CPU time 0.73 seconds
Started Mar 24 12:37:53 PM PDT 24
Finished Mar 24 12:37:54 PM PDT 24
Peak memory 205076 kb
Host smart-764c2676-245f-48cc-8d2b-06f6a3c1447b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874223805 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.874223805
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.2063384112
Short name T224
Test name
Test status
Simulation time 14303425738 ps
CPU time 25.99 seconds
Started Mar 24 12:37:45 PM PDT 24
Finished Mar 24 12:38:12 PM PDT 24
Peak memory 213384 kb
Host smart-a21076e1-b974-4e1c-8252-5f45eb7c06af
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2063384112 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t
l_access.2063384112
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.3258105723
Short name T221
Test name
Test status
Simulation time 702257187 ps
CPU time 1.32 seconds
Started Mar 24 12:37:57 PM PDT 24
Finished Mar 24 12:37:58 PM PDT 24
Peak memory 204968 kb
Host smart-f16b1479-3691-4cbb-8b47-5e62200a6e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258105723 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.3258105723
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.1586588401
Short name T34
Test name
Test status
Simulation time 50600630 ps
CPU time 0.81 seconds
Started Mar 24 12:38:04 PM PDT 24
Finished Mar 24 12:38:05 PM PDT 24
Peak memory 204548 kb
Host smart-fe8365f0-ee5f-42e3-8acf-d83af58894fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586588401 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.1586588401
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.2492743894
Short name T16
Test name
Test status
Simulation time 72406743 ps
CPU time 0.85 seconds
Started Mar 24 12:37:55 PM PDT 24
Finished Mar 24 12:37:56 PM PDT 24
Peak memory 204592 kb
Host smart-d7ced4dc-d0b4-49cf-affb-0f8cbd72093f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492743894 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.2492743894
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.2206282331
Short name T56
Test name
Test status
Simulation time 298046705 ps
CPU time 1.5 seconds
Started Mar 24 12:38:03 PM PDT 24
Finished Mar 24 12:38:04 PM PDT 24
Peak memory 204772 kb
Host smart-aa675145-1b23-4191-a387-859278c601cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206282331 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.2206282331
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.660442370
Short name T58
Test name
Test status
Simulation time 43106539 ps
CPU time 0.78 seconds
Started Mar 24 12:38:02 PM PDT 24
Finished Mar 24 12:38:03 PM PDT 24
Peak memory 204576 kb
Host smart-749034a1-97e5-46c7-88f4-eb0777f311bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660442370 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.660442370
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.1944408874
Short name T223
Test name
Test status
Simulation time 127158212 ps
CPU time 1.11 seconds
Started Mar 24 12:37:52 PM PDT 24
Finished Mar 24 12:37:54 PM PDT 24
Peak memory 204624 kb
Host smart-c11402e8-6494-45a2-a8c9-0f43098758df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944408874 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.1944408874
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.4224123335
Short name T15
Test name
Test status
Simulation time 325985742 ps
CPU time 1.74 seconds
Started Mar 24 12:38:00 PM PDT 24
Finished Mar 24 12:38:02 PM PDT 24
Peak memory 204688 kb
Host smart-1a0d9c82-a432-43ec-b57a-d146af295c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224123335 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.4224123335
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.930379077
Short name T79
Test name
Test status
Simulation time 165197745 ps
CPU time 0.82 seconds
Started Mar 24 12:37:53 PM PDT 24
Finished Mar 24 12:37:54 PM PDT 24
Peak memory 204708 kb
Host smart-9b579ecc-1b28-4665-b35f-33a86568c207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930379077 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.930379077
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.3621361259
Short name T194
Test name
Test status
Simulation time 2969056839 ps
CPU time 3.49 seconds
Started Mar 24 12:38:01 PM PDT 24
Finished Mar 24 12:38:05 PM PDT 24
Peak memory 204980 kb
Host smart-f7bdf778-961a-409c-aa57-d5f5c8ade224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621361259 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.3621361259
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.873918617
Short name T1
Test name
Test status
Simulation time 1128020445 ps
CPU time 1.23 seconds
Started Mar 24 12:37:53 PM PDT 24
Finished Mar 24 12:37:55 PM PDT 24
Peak memory 205156 kb
Host smart-a4f9a7fe-64fc-4287-bbb7-2713ca7ba8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873918617 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.873918617
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.688573342
Short name T55
Test name
Test status
Simulation time 1132002656 ps
CPU time 3.82 seconds
Started Mar 24 12:37:59 PM PDT 24
Finished Mar 24 12:38:04 PM PDT 24
Peak memory 204748 kb
Host smart-dbe9dcef-9c22-4196-91c9-ea69d9feea40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688573342 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.688573342
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.836923694
Short name T162
Test name
Test status
Simulation time 18338996 ps
CPU time 0.69 seconds
Started Mar 24 12:38:04 PM PDT 24
Finished Mar 24 12:38:05 PM PDT 24
Peak memory 205068 kb
Host smart-f6a5907a-0ac7-4c4e-b3ea-a5483bada9ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836923694 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.836923694
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.2849374611
Short name T21
Test name
Test status
Simulation time 45057989809 ps
CPU time 136.3 seconds
Started Mar 24 12:37:51 PM PDT 24
Finished Mar 24 12:40:08 PM PDT 24
Peak memory 213692 kb
Host smart-293d3ced-90ef-49fa-91bc-575b2051d11d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849374611 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.2849374611
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.2108313010
Short name T176
Test name
Test status
Simulation time 1144810227 ps
CPU time 1.96 seconds
Started Mar 24 12:38:12 PM PDT 24
Finished Mar 24 12:38:14 PM PDT 24
Peak memory 205004 kb
Host smart-c5b37d20-7f8e-4f36-878f-9f3f3dfa5e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108313010 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.2108313010
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.3953124644
Short name T140
Test name
Test status
Simulation time 8208253387 ps
CPU time 5.9 seconds
Started Mar 24 12:38:04 PM PDT 24
Finished Mar 24 12:38:10 PM PDT 24
Peak memory 205140 kb
Host smart-e2807053-da9e-4bde-941f-95a312c054cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953124644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.3953124644
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.913386922
Short name T48
Test name
Test status
Simulation time 120751977 ps
CPU time 0.81 seconds
Started Mar 24 12:37:56 PM PDT 24
Finished Mar 24 12:37:56 PM PDT 24
Peak memory 204540 kb
Host smart-6e49f09c-711b-4918-bfd8-14d348d80bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913386922 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.913386922
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.919156567
Short name T22
Test name
Test status
Simulation time 3663892949 ps
CPU time 3.59 seconds
Started Mar 24 12:38:09 PM PDT 24
Finished Mar 24 12:38:13 PM PDT 24
Peak memory 205364 kb
Host smart-42404f72-b260-426b-88cc-21307fd0131a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919156567 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.919156567
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.4134089144
Short name T143
Test name
Test status
Simulation time 45650399 ps
CPU time 0.74 seconds
Started Mar 24 12:37:53 PM PDT 24
Finished Mar 24 12:37:54 PM PDT 24
Peak memory 204716 kb
Host smart-77ea14ce-7080-42e6-8acc-c04e4af788db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134089144 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.4134089144
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.2105726326
Short name T11
Test name
Test status
Simulation time 1272698083 ps
CPU time 4.97 seconds
Started Mar 24 12:38:14 PM PDT 24
Finished Mar 24 12:38:19 PM PDT 24
Peak memory 204988 kb
Host smart-c8d2018f-90b8-4526-9599-bce1f2b74114
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2105726326 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.2105726326
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.2889357665
Short name T51
Test name
Test status
Simulation time 106046990 ps
CPU time 1.04 seconds
Started Mar 24 12:37:55 PM PDT 24
Finished Mar 24 12:37:57 PM PDT 24
Peak memory 204668 kb
Host smart-fa1b4765-8ec2-4f15-b305-baee5dc712e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889357665 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.2889357665
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.3122584218
Short name T226
Test name
Test status
Simulation time 273633012 ps
CPU time 1.45 seconds
Started Mar 24 12:37:59 PM PDT 24
Finished Mar 24 12:38:00 PM PDT 24
Peak memory 204780 kb
Host smart-9f27b706-2780-48fd-abe4-d32799647784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122584218 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.3122584218
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.3950103556
Short name T23
Test name
Test status
Simulation time 139216122 ps
CPU time 0.68 seconds
Started Mar 24 12:38:02 PM PDT 24
Finished Mar 24 12:38:03 PM PDT 24
Peak memory 204576 kb
Host smart-3ee21a9a-33a9-4407-9ebe-d55b01b65369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950103556 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.3950103556
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.2601247945
Short name T118
Test name
Test status
Simulation time 245553565 ps
CPU time 0.84 seconds
Started Mar 24 12:38:22 PM PDT 24
Finished Mar 24 12:38:22 PM PDT 24
Peak memory 204680 kb
Host smart-ec1da323-6537-402d-9fa2-dd866abe3d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601247945 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.2601247945
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.1135002030
Short name T144
Test name
Test status
Simulation time 152411402 ps
CPU time 0.88 seconds
Started Mar 24 12:37:54 PM PDT 24
Finished Mar 24 12:37:55 PM PDT 24
Peak memory 204796 kb
Host smart-1c2dc914-8f75-4ebc-85d8-44dd28d4951f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135002030 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.1135002030
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.2860592875
Short name T17
Test name
Test status
Simulation time 205306786 ps
CPU time 1.14 seconds
Started Mar 24 12:38:00 PM PDT 24
Finished Mar 24 12:38:01 PM PDT 24
Peak memory 204708 kb
Host smart-3738877a-d351-4d9b-b589-13fb3d2ff9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860592875 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.2860592875
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.2780927344
Short name T52
Test name
Test status
Simulation time 63909421 ps
CPU time 0.9 seconds
Started Mar 24 12:38:04 PM PDT 24
Finished Mar 24 12:38:10 PM PDT 24
Peak memory 204668 kb
Host smart-c5dd3c91-ebf7-411a-b421-58933e58e64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780927344 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.2780927344
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.2640780193
Short name T49
Test name
Test status
Simulation time 23108245 ps
CPU time 0.83 seconds
Started Mar 24 12:38:14 PM PDT 24
Finished Mar 24 12:38:15 PM PDT 24
Peak memory 212956 kb
Host smart-1ebdaf16-ade0-4de8-bac6-90f2c42b94c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640780193 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.2640780193
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.3262400186
Short name T233
Test name
Test status
Simulation time 749134463 ps
CPU time 2.13 seconds
Started Mar 24 12:37:46 PM PDT 24
Finished Mar 24 12:37:48 PM PDT 24
Peak memory 204988 kb
Host smart-5d37e68d-eb1c-46cb-bc51-cdef099367c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262400186 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.3262400186
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.504101781
Short name T25
Test name
Test status
Simulation time 367934078 ps
CPU time 1.23 seconds
Started Mar 24 12:38:03 PM PDT 24
Finished Mar 24 12:38:04 PM PDT 24
Peak memory 236888 kb
Host smart-dccf4864-c3cb-42f4-8a74-3a31efc2c798
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504101781 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.504101781
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.2427301176
Short name T57
Test name
Test status
Simulation time 365036854 ps
CPU time 1.05 seconds
Started Mar 24 12:38:00 PM PDT 24
Finished Mar 24 12:38:02 PM PDT 24
Peak memory 204552 kb
Host smart-0d86fdcb-5db4-4c31-9b77-31a04383c3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427301176 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.2427301176
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.3726426037
Short name T158
Test name
Test status
Simulation time 21887904 ps
CPU time 0.72 seconds
Started Mar 24 12:38:00 PM PDT 24
Finished Mar 24 12:38:01 PM PDT 24
Peak memory 204704 kb
Host smart-f04c3605-1f7d-4d5e-84ec-674d4d6d548e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726426037 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.3726426037
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.3290211238
Short name T178
Test name
Test status
Simulation time 381482501 ps
CPU time 2.04 seconds
Started Mar 24 12:38:02 PM PDT 24
Finished Mar 24 12:38:04 PM PDT 24
Peak memory 204956 kb
Host smart-068066d7-2783-4b80-ba87-d57037fbaa0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290211238 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.3290211238
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.449407076
Short name T8
Test name
Test status
Simulation time 4694155033 ps
CPU time 4.34 seconds
Started Mar 24 12:38:02 PM PDT 24
Finished Mar 24 12:38:06 PM PDT 24
Peak memory 213388 kb
Host smart-888e30ec-4e28-41ca-b3f1-4b7dd0590a83
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=449407076 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_t
l_access.449407076
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.1864395068
Short name T198
Test name
Test status
Simulation time 3299529183 ps
CPU time 11.27 seconds
Started Mar 24 12:38:21 PM PDT 24
Finished Mar 24 12:38:32 PM PDT 24
Peak memory 205148 kb
Host smart-28bac244-9e19-43d2-a41d-ba05ae944eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864395068 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.1864395068
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.2102650015
Short name T164
Test name
Test status
Simulation time 28689034 ps
CPU time 0.7 seconds
Started Mar 24 12:38:21 PM PDT 24
Finished Mar 24 12:38:22 PM PDT 24
Peak memory 204664 kb
Host smart-bec43115-7a5a-445f-b552-0676696c685c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102650015 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.2102650015
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.3942998165
Short name T212
Test name
Test status
Simulation time 23411153399 ps
CPU time 16.1 seconds
Started Mar 24 12:38:21 PM PDT 24
Finished Mar 24 12:38:37 PM PDT 24
Peak memory 213336 kb
Host smart-acac5eca-2b46-4391-90a7-135404c6fa78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942998165 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.3942998165
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.1765147146
Short name T214
Test name
Test status
Simulation time 4681361770 ps
CPU time 8.76 seconds
Started Mar 24 12:38:31 PM PDT 24
Finished Mar 24 12:38:40 PM PDT 24
Peak memory 215488 kb
Host smart-b6db3ef5-358e-4a57-9c1d-ca9162a6efaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765147146 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.1765147146
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.3559284390
Short name T204
Test name
Test status
Simulation time 6360242473 ps
CPU time 8.92 seconds
Started Mar 24 12:38:06 PM PDT 24
Finished Mar 24 12:38:15 PM PDT 24
Peak memory 213320 kb
Host smart-d97320d4-7acd-44e5-bcca-cd7be36dcb00
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3559284390 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_
tl_access.3559284390
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.2711379491
Short name T154
Test name
Test status
Simulation time 33151305 ps
CPU time 0.68 seconds
Started Mar 24 12:38:10 PM PDT 24
Finished Mar 24 12:38:11 PM PDT 24
Peak memory 204664 kb
Host smart-f8ff49c8-eb16-46ed-add2-44fa217c3c7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711379491 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.2711379491
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.1436591556
Short name T217
Test name
Test status
Simulation time 1562960252 ps
CPU time 3.31 seconds
Started Mar 24 12:38:16 PM PDT 24
Finished Mar 24 12:38:19 PM PDT 24
Peak memory 205028 kb
Host smart-f9c3f056-b8aa-4b14-8db9-7748200c3441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436591556 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.1436591556
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.1310485880
Short name T175
Test name
Test status
Simulation time 10812022788 ps
CPU time 7.59 seconds
Started Mar 24 12:38:14 PM PDT 24
Finished Mar 24 12:38:22 PM PDT 24
Peak memory 205300 kb
Host smart-859a3568-ea9b-4348-984c-61e7c7fe4068
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1310485880 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.1310485880
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.1709921659
Short name T185
Test name
Test status
Simulation time 7669721369 ps
CPU time 14.27 seconds
Started Mar 24 12:38:04 PM PDT 24
Finished Mar 24 12:38:19 PM PDT 24
Peak memory 205152 kb
Host smart-bd666f29-b078-40f9-a65e-c6627392d6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709921659 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.1709921659
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_stress_all.3830180522
Short name T30
Test name
Test status
Simulation time 1573222673 ps
CPU time 3.61 seconds
Started Mar 24 12:38:20 PM PDT 24
Finished Mar 24 12:38:24 PM PDT 24
Peak memory 204912 kb
Host smart-aa9ad00a-a05f-44c5-b0a7-84f98423b31d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830180522 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.3830180522
Directory /workspace/12.rv_dm_stress_all/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.3403205698
Short name T153
Test name
Test status
Simulation time 23953008 ps
CPU time 0.76 seconds
Started Mar 24 12:38:32 PM PDT 24
Finished Mar 24 12:38:33 PM PDT 24
Peak memory 204644 kb
Host smart-4d6de5c6-b76b-463e-9567-55c2b9ad7a7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403205698 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.3403205698
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.1201063660
Short name T229
Test name
Test status
Simulation time 7441969825 ps
CPU time 20.96 seconds
Started Mar 24 12:38:15 PM PDT 24
Finished Mar 24 12:38:36 PM PDT 24
Peak memory 213300 kb
Host smart-adddb5a0-9ac4-4e80-9057-ece167a5ba97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201063660 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.1201063660
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.3845543677
Short name T192
Test name
Test status
Simulation time 2639255310 ps
CPU time 8.77 seconds
Started Mar 24 12:38:13 PM PDT 24
Finished Mar 24 12:38:22 PM PDT 24
Peak memory 205088 kb
Host smart-31854c0d-1364-45a9-85bc-d2b59e04ce97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845543677 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.3845543677
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.2168522053
Short name T199
Test name
Test status
Simulation time 603115605 ps
CPU time 1.96 seconds
Started Mar 24 12:38:00 PM PDT 24
Finished Mar 24 12:38:03 PM PDT 24
Peak memory 205092 kb
Host smart-3537790e-1a74-4e15-b4af-60a93f327591
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2168522053 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_
tl_access.2168522053
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.2866914538
Short name T88
Test name
Test status
Simulation time 4601455521 ps
CPU time 10.56 seconds
Started Mar 24 12:38:25 PM PDT 24
Finished Mar 24 12:38:36 PM PDT 24
Peak memory 205136 kb
Host smart-bab8393b-d096-4fd2-b271-3cd1e790d4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866914538 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.2866914538
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.2177000349
Short name T172
Test name
Test status
Simulation time 24712525 ps
CPU time 0.71 seconds
Started Mar 24 12:38:16 PM PDT 24
Finished Mar 24 12:38:17 PM PDT 24
Peak memory 204648 kb
Host smart-96fb3063-6161-4517-8696-71fd0494fc77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177000349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.2177000349
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.1066522036
Short name T197
Test name
Test status
Simulation time 30366298034 ps
CPU time 47.67 seconds
Started Mar 24 12:38:02 PM PDT 24
Finished Mar 24 12:38:50 PM PDT 24
Peak memory 213324 kb
Host smart-16777851-7565-48c9-b33a-fe1cd1c6d3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066522036 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.1066522036
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.2018598081
Short name T177
Test name
Test status
Simulation time 471009735 ps
CPU time 1.77 seconds
Started Mar 24 12:37:57 PM PDT 24
Finished Mar 24 12:37:59 PM PDT 24
Peak memory 205004 kb
Host smart-ec75f2e7-d313-4012-ae8e-17ce13394f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018598081 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.2018598081
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.491189865
Short name T215
Test name
Test status
Simulation time 1196517040 ps
CPU time 3.44 seconds
Started Mar 24 12:38:24 PM PDT 24
Finished Mar 24 12:38:27 PM PDT 24
Peak memory 205356 kb
Host smart-fcef1230-3de1-479a-b0e4-1a29ea109ae8
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=491189865 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_t
l_access.491189865
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.2237960281
Short name T181
Test name
Test status
Simulation time 4274052916 ps
CPU time 3.93 seconds
Started Mar 24 12:38:13 PM PDT 24
Finished Mar 24 12:38:22 PM PDT 24
Peak memory 205108 kb
Host smart-1e8a4e6e-c654-4738-bf61-dd3f88554b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237960281 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.2237960281
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.2141310507
Short name T27
Test name
Test status
Simulation time 62337560 ps
CPU time 0.71 seconds
Started Mar 24 12:38:20 PM PDT 24
Finished Mar 24 12:38:21 PM PDT 24
Peak memory 204716 kb
Host smart-b3b866ab-55f6-4c2c-9f11-02305006193b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141310507 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.2141310507
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.2153019835
Short name T225
Test name
Test status
Simulation time 2837630179 ps
CPU time 11.22 seconds
Started Mar 24 12:38:25 PM PDT 24
Finished Mar 24 12:38:41 PM PDT 24
Peak memory 213264 kb
Host smart-19001a25-8f99-4360-ace4-aea5f0964655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153019835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.2153019835
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.2998181294
Short name T234
Test name
Test status
Simulation time 2657133689 ps
CPU time 12.68 seconds
Started Mar 24 12:38:20 PM PDT 24
Finished Mar 24 12:38:33 PM PDT 24
Peak memory 204984 kb
Host smart-b774096c-4cf8-4e40-a8e2-50e623d27d63
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2998181294 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_
tl_access.2998181294
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.1562470048
Short name T210
Test name
Test status
Simulation time 2892077510 ps
CPU time 9.83 seconds
Started Mar 24 12:38:18 PM PDT 24
Finished Mar 24 12:38:28 PM PDT 24
Peak memory 205036 kb
Host smart-3b405bab-cc4e-423e-9586-f62e316a8413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562470048 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.1562470048
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.1563486208
Short name T219
Test name
Test status
Simulation time 997841332 ps
CPU time 2.16 seconds
Started Mar 24 12:38:34 PM PDT 24
Finished Mar 24 12:38:36 PM PDT 24
Peak memory 205008 kb
Host smart-fd59477d-c44d-4a73-a01f-930feace949d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563486208 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.1563486208
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.3463875177
Short name T230
Test name
Test status
Simulation time 3158133663 ps
CPU time 2.92 seconds
Started Mar 24 12:38:17 PM PDT 24
Finished Mar 24 12:38:21 PM PDT 24
Peak memory 205056 kb
Host smart-3ff1a7fd-5133-4cdb-a2de-2b13f46ba13e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3463875177 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_
tl_access.3463875177
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.2084439928
Short name T238
Test name
Test status
Simulation time 2575451805 ps
CPU time 12.01 seconds
Started Mar 24 12:38:14 PM PDT 24
Finished Mar 24 12:38:26 PM PDT 24
Peak memory 213268 kb
Host smart-a00883a4-2030-4a69-8092-3afef2864831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084439928 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.2084439928
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.3714570296
Short name T169
Test name
Test status
Simulation time 22343188 ps
CPU time 0.68 seconds
Started Mar 24 12:38:12 PM PDT 24
Finished Mar 24 12:38:13 PM PDT 24
Peak memory 204716 kb
Host smart-55d88364-a9ae-4789-848c-6a69402f5261
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714570296 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.3714570296
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.3636426976
Short name T213
Test name
Test status
Simulation time 24953949169 ps
CPU time 68.75 seconds
Started Mar 24 12:38:18 PM PDT 24
Finished Mar 24 12:39:27 PM PDT 24
Peak memory 216024 kb
Host smart-d2249faa-3e27-401e-aa8c-2749c42082a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636426976 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.3636426976
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.1017592799
Short name T218
Test name
Test status
Simulation time 5846256884 ps
CPU time 20.82 seconds
Started Mar 24 12:38:38 PM PDT 24
Finished Mar 24 12:38:59 PM PDT 24
Peak memory 213316 kb
Host smart-c9a3e983-2b57-4ce1-8fa4-fc01e130c35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017592799 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.1017592799
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.1824466733
Short name T191
Test name
Test status
Simulation time 490568992 ps
CPU time 2.16 seconds
Started Mar 24 12:38:25 PM PDT 24
Finished Mar 24 12:38:28 PM PDT 24
Peak memory 205080 kb
Host smart-a3ff7fb3-4fda-4159-8d84-d070696e7034
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1824466733 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_
tl_access.1824466733
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.3362578257
Short name T200
Test name
Test status
Simulation time 5080213489 ps
CPU time 7.03 seconds
Started Mar 24 12:38:15 PM PDT 24
Finished Mar 24 12:38:23 PM PDT 24
Peak memory 205116 kb
Host smart-f8e0784e-dc8d-4811-b6b9-e7daa2b41b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362578257 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.3362578257
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.213226304
Short name T237
Test name
Test status
Simulation time 157386689 ps
CPU time 0.68 seconds
Started Mar 24 12:38:13 PM PDT 24
Finished Mar 24 12:38:14 PM PDT 24
Peak memory 204724 kb
Host smart-9d550b0b-ca94-49bd-8a4f-b1c07219f371
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213226304 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.213226304
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.2092011415
Short name T187
Test name
Test status
Simulation time 2844272166 ps
CPU time 6.19 seconds
Started Mar 24 12:38:17 PM PDT 24
Finished Mar 24 12:38:23 PM PDT 24
Peak memory 205132 kb
Host smart-d73707f1-caf5-411b-9aae-5e416f056a99
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2092011415 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_
tl_access.2092011415
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.1253526861
Short name T180
Test name
Test status
Simulation time 12317244512 ps
CPU time 41.52 seconds
Started Mar 24 12:38:02 PM PDT 24
Finished Mar 24 12:38:44 PM PDT 24
Peak memory 213360 kb
Host smart-73b8a56c-04e0-4efa-8691-dfa0f2d2838c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253526861 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.1253526861
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_stress_all.843377447
Short name T7
Test name
Test status
Simulation time 5132458415 ps
CPU time 7.4 seconds
Started Mar 24 12:38:16 PM PDT 24
Finished Mar 24 12:38:24 PM PDT 24
Peak memory 204996 kb
Host smart-6d33cc21-d774-404d-aa0c-ef2354e545e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843377447 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.843377447
Directory /workspace/18.rv_dm_stress_all/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.1633600965
Short name T63
Test name
Test status
Simulation time 38249241 ps
CPU time 0.66 seconds
Started Mar 24 12:38:32 PM PDT 24
Finished Mar 24 12:38:32 PM PDT 24
Peak memory 204716 kb
Host smart-232840b7-84ea-4af1-a8bd-3b52fbf5a946
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633600965 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.1633600965
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.4258205613
Short name T182
Test name
Test status
Simulation time 2752617556 ps
CPU time 7.32 seconds
Started Mar 24 12:38:29 PM PDT 24
Finished Mar 24 12:38:36 PM PDT 24
Peak memory 205072 kb
Host smart-2fb03f81-a329-46c9-ba76-71251776723e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258205613 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.4258205613
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.767987137
Short name T183
Test name
Test status
Simulation time 4515115061 ps
CPU time 6.23 seconds
Started Mar 24 12:38:04 PM PDT 24
Finished Mar 24 12:38:11 PM PDT 24
Peak memory 205132 kb
Host smart-5be91ede-dbf5-40a1-8d5c-83c0a1da18a0
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=767987137 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_t
l_access.767987137
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.2319309094
Short name T203
Test name
Test status
Simulation time 14391444442 ps
CPU time 45.07 seconds
Started Mar 24 12:38:32 PM PDT 24
Finished Mar 24 12:39:17 PM PDT 24
Peak memory 213408 kb
Host smart-890be06a-1ac2-481e-adc6-e4655181221e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319309094 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.2319309094
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.3568404526
Short name T77
Test name
Test status
Simulation time 49875025 ps
CPU time 0.7 seconds
Started Mar 24 12:37:58 PM PDT 24
Finished Mar 24 12:37:59 PM PDT 24
Peak memory 204708 kb
Host smart-0fd895ca-5b3e-491c-a2fa-d41f29ce05d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568404526 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.3568404526
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.4039701283
Short name T127
Test name
Test status
Simulation time 4515270036 ps
CPU time 5.6 seconds
Started Mar 24 12:37:56 PM PDT 24
Finished Mar 24 12:38:02 PM PDT 24
Peak memory 213388 kb
Host smart-d4736045-68a5-4911-85a8-91b785e33381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039701283 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.4039701283
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.3694995020
Short name T173
Test name
Test status
Simulation time 4699971990 ps
CPU time 8.42 seconds
Started Mar 24 12:37:56 PM PDT 24
Finished Mar 24 12:38:05 PM PDT 24
Peak memory 213336 kb
Host smart-bbf4091e-0c51-4567-aeb5-596012fd9762
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3694995020 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.3694995020
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.962709471
Short name T231
Test name
Test status
Simulation time 166450690 ps
CPU time 0.93 seconds
Started Mar 24 12:37:56 PM PDT 24
Finished Mar 24 12:37:57 PM PDT 24
Peak memory 204576 kb
Host smart-bd6e6671-7a9f-42ac-a2f8-32b051fb306f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962709471 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.962709471
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.1451431721
Short name T174
Test name
Test status
Simulation time 1731879706 ps
CPU time 3.24 seconds
Started Mar 24 12:37:54 PM PDT 24
Finished Mar 24 12:38:02 PM PDT 24
Peak memory 204972 kb
Host smart-ea42eed0-41c9-44ae-8963-4d96dbe50d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451431721 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.1451431721
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.3876782693
Short name T24
Test name
Test status
Simulation time 336714725 ps
CPU time 1.03 seconds
Started Mar 24 12:37:55 PM PDT 24
Finished Mar 24 12:37:56 PM PDT 24
Peak memory 229292 kb
Host smart-62c93c1c-9406-4d98-8363-566d5bed1c02
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876782693 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.3876782693
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.2764950260
Short name T47
Test name
Test status
Simulation time 25487304 ps
CPU time 0.74 seconds
Started Mar 24 12:38:20 PM PDT 24
Finished Mar 24 12:38:21 PM PDT 24
Peak memory 205092 kb
Host smart-a3e301a5-9748-4ca2-a443-9c76802f1ae6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764950260 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.2764950260
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.3329607341
Short name T157
Test name
Test status
Simulation time 47143673 ps
CPU time 0.7 seconds
Started Mar 24 12:38:24 PM PDT 24
Finished Mar 24 12:38:25 PM PDT 24
Peak memory 204688 kb
Host smart-d8bd615f-cf67-480f-9741-77717d6f3319
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329607341 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.3329607341
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_stress_all.481995060
Short name T31
Test name
Test status
Simulation time 1090288951 ps
CPU time 2.86 seconds
Started Mar 24 12:38:27 PM PDT 24
Finished Mar 24 12:38:30 PM PDT 24
Peak memory 204920 kb
Host smart-16fdf417-421d-4f2c-ab7f-1e1b04d82719
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481995060 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.481995060
Directory /workspace/21.rv_dm_stress_all/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.2729277391
Short name T119
Test name
Test status
Simulation time 44701427 ps
CPU time 0.69 seconds
Started Mar 24 12:38:16 PM PDT 24
Finished Mar 24 12:38:18 PM PDT 24
Peak memory 204660 kb
Host smart-e57c2213-22a8-4170-af75-aba2e004318c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729277391 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.2729277391
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.2830598942
Short name T152
Test name
Test status
Simulation time 20005070 ps
CPU time 0.68 seconds
Started Mar 24 12:38:17 PM PDT 24
Finished Mar 24 12:38:23 PM PDT 24
Peak memory 204788 kb
Host smart-9f830beb-97e1-4d1e-b3b7-ee810cb73e17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830598942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.2830598942
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.739971815
Short name T161
Test name
Test status
Simulation time 42804879 ps
CPU time 0.68 seconds
Started Mar 24 12:38:11 PM PDT 24
Finished Mar 24 12:38:12 PM PDT 24
Peak memory 204676 kb
Host smart-bce77718-8640-4962-ab9a-8842c394a3cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739971815 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.739971815
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.1576068476
Short name T155
Test name
Test status
Simulation time 102290115 ps
CPU time 0.71 seconds
Started Mar 24 12:38:00 PM PDT 24
Finished Mar 24 12:38:01 PM PDT 24
Peak memory 204684 kb
Host smart-770014fe-4411-4cb1-8c0a-984a78b1f703
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576068476 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.1576068476
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.3438946884
Short name T120
Test name
Test status
Simulation time 52593762 ps
CPU time 0.7 seconds
Started Mar 24 12:38:30 PM PDT 24
Finished Mar 24 12:38:31 PM PDT 24
Peak memory 204680 kb
Host smart-8853d1b2-b8d5-439b-92ec-91754fc0ca6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438946884 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.3438946884
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.3111768640
Short name T149
Test name
Test status
Simulation time 29813898 ps
CPU time 0.71 seconds
Started Mar 24 12:38:17 PM PDT 24
Finished Mar 24 12:38:19 PM PDT 24
Peak memory 204680 kb
Host smart-7690c27d-f091-4400-b859-c6ef15bfa049
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111768640 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.3111768640
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.1385253150
Short name T128
Test name
Test status
Simulation time 121127488 ps
CPU time 0.71 seconds
Started Mar 24 12:38:02 PM PDT 24
Finished Mar 24 12:38:03 PM PDT 24
Peak memory 204696 kb
Host smart-d3150f9e-2774-469a-beeb-60393000e804
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385253150 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.1385253150
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_stress_all.865024058
Short name T141
Test name
Test status
Simulation time 1650151691 ps
CPU time 5.89 seconds
Started Mar 24 12:38:20 PM PDT 24
Finished Mar 24 12:38:26 PM PDT 24
Peak memory 204872 kb
Host smart-7a1099a3-5dd2-463e-910e-e232291e4f66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865024058 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.865024058
Directory /workspace/28.rv_dm_stress_all/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.2348922800
Short name T220
Test name
Test status
Simulation time 68804433 ps
CPU time 0.7 seconds
Started Mar 24 12:38:31 PM PDT 24
Finished Mar 24 12:38:31 PM PDT 24
Peak memory 204680 kb
Host smart-8159b768-6dd1-4bff-b33f-59568c93c65b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348922800 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.2348922800
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.3154959748
Short name T150
Test name
Test status
Simulation time 50813032 ps
CPU time 0.78 seconds
Started Mar 24 12:37:58 PM PDT 24
Finished Mar 24 12:38:01 PM PDT 24
Peak memory 204728 kb
Host smart-44d0808b-2e3d-46ed-8ebe-a256f07da6b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154959748 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.3154959748
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.1023888917
Short name T126
Test name
Test status
Simulation time 20016522636 ps
CPU time 37.85 seconds
Started Mar 24 12:37:57 PM PDT 24
Finished Mar 24 12:38:40 PM PDT 24
Peak memory 213392 kb
Host smart-088f10e3-c76b-40f9-9a63-6c45e0e20c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023888917 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.1023888917
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.1491443162
Short name T14
Test name
Test status
Simulation time 1921590970 ps
CPU time 10.07 seconds
Started Mar 24 12:37:56 PM PDT 24
Finished Mar 24 12:38:06 PM PDT 24
Peak memory 213252 kb
Host smart-dbd22e13-cc92-4a60-b165-5e49e1cacc04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491443162 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.1491443162
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.1747433980
Short name T44
Test name
Test status
Simulation time 514806733 ps
CPU time 2.6 seconds
Started Mar 24 12:38:05 PM PDT 24
Finished Mar 24 12:38:08 PM PDT 24
Peak memory 204992 kb
Host smart-d51e48ff-75f7-4805-82d1-7f8d0f335a4c
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1747433980 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.1747433980
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.3661993431
Short name T179
Test name
Test status
Simulation time 121591537 ps
CPU time 0.78 seconds
Started Mar 24 12:38:00 PM PDT 24
Finished Mar 24 12:38:01 PM PDT 24
Peak memory 204524 kb
Host smart-32c1946d-4057-443f-941a-e2d9e442674d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661993431 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.3661993431
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.1950303655
Short name T196
Test name
Test status
Simulation time 2783816395 ps
CPU time 3.24 seconds
Started Mar 24 12:38:06 PM PDT 24
Finished Mar 24 12:38:10 PM PDT 24
Peak memory 205008 kb
Host smart-50a0e51a-de8f-4175-99fa-aedea7c74694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950303655 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.1950303655
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.2089316381
Short name T26
Test name
Test status
Simulation time 105121468 ps
CPU time 1.12 seconds
Started Mar 24 12:38:46 PM PDT 24
Finished Mar 24 12:38:47 PM PDT 24
Peak memory 228304 kb
Host smart-d5af9f09-8e8c-4170-ac41-d72c6704060f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089316381 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.2089316381
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.1095858093
Short name T163
Test name
Test status
Simulation time 113710323 ps
CPU time 0.73 seconds
Started Mar 24 12:38:02 PM PDT 24
Finished Mar 24 12:38:03 PM PDT 24
Peak memory 204732 kb
Host smart-10011b86-afd7-4aa8-96d3-acb90a8097a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095858093 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.1095858093
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.3170904938
Short name T42
Test name
Test status
Simulation time 62353775 ps
CPU time 0.7 seconds
Started Mar 24 12:38:14 PM PDT 24
Finished Mar 24 12:38:15 PM PDT 24
Peak memory 204672 kb
Host smart-d6bfc711-08d0-4468-b0ed-d8874783f27b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170904938 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.3170904938
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.2934433355
Short name T227
Test name
Test status
Simulation time 64163124 ps
CPU time 0.67 seconds
Started Mar 24 12:39:20 PM PDT 24
Finished Mar 24 12:39:20 PM PDT 24
Peak memory 204620 kb
Host smart-f1c87cbb-a154-40b8-9ddd-c74eebe1ab87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934433355 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.2934433355
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.2674556190
Short name T166
Test name
Test status
Simulation time 51649563 ps
CPU time 0.72 seconds
Started Mar 24 12:38:18 PM PDT 24
Finished Mar 24 12:38:19 PM PDT 24
Peak memory 205092 kb
Host smart-1600d8e1-87e5-49d1-b125-bb7f691b13e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674556190 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.2674556190
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.943810155
Short name T167
Test name
Test status
Simulation time 17792297 ps
CPU time 0.72 seconds
Started Mar 24 12:38:35 PM PDT 24
Finished Mar 24 12:38:36 PM PDT 24
Peak memory 204716 kb
Host smart-9639f457-6d77-4d7c-9d54-fbf312918e14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943810155 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.943810155
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.1692627079
Short name T67
Test name
Test status
Simulation time 104755428 ps
CPU time 0.72 seconds
Started Mar 24 12:38:11 PM PDT 24
Finished Mar 24 12:38:12 PM PDT 24
Peak memory 204692 kb
Host smart-d4ef5f08-3e74-4fd4-82da-b2808637f6d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692627079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.1692627079
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.867642674
Short name T78
Test name
Test status
Simulation time 19099371 ps
CPU time 0.72 seconds
Started Mar 24 12:38:09 PM PDT 24
Finished Mar 24 12:38:10 PM PDT 24
Peak memory 204696 kb
Host smart-a0181ba6-dfc2-43fe-8792-61c59211827c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867642674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.867642674
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.6630730
Short name T28
Test name
Test status
Simulation time 43170042 ps
CPU time 0.66 seconds
Started Mar 24 12:38:19 PM PDT 24
Finished Mar 24 12:38:20 PM PDT 24
Peak memory 204680 kb
Host smart-bbf998c8-ec27-46c1-b770-7b4666b4e7be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6630730 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.6630730
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.4242595163
Short name T171
Test name
Test status
Simulation time 20179695 ps
CPU time 0.68 seconds
Started Mar 24 12:38:18 PM PDT 24
Finished Mar 24 12:38:19 PM PDT 24
Peak memory 204696 kb
Host smart-9a43cb10-3310-4069-bbd2-973bbc51c715
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242595163 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.4242595163
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.2547291017
Short name T228
Test name
Test status
Simulation time 15295002 ps
CPU time 0.72 seconds
Started Mar 24 12:38:36 PM PDT 24
Finished Mar 24 12:38:37 PM PDT 24
Peak memory 204696 kb
Host smart-6a4e835b-5afe-4a0a-9a1d-1202f1c14693
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547291017 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.2547291017
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.2793921311
Short name T165
Test name
Test status
Simulation time 31367938 ps
CPU time 0.71 seconds
Started Mar 24 12:37:43 PM PDT 24
Finished Mar 24 12:37:44 PM PDT 24
Peak memory 204740 kb
Host smart-62908c81-2953-47ce-acc7-ad8b5a448766
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793921311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.2793921311
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.3080996055
Short name T193
Test name
Test status
Simulation time 14313692316 ps
CPU time 36.62 seconds
Started Mar 24 12:37:54 PM PDT 24
Finished Mar 24 12:38:31 PM PDT 24
Peak memory 213296 kb
Host smart-e978f3ae-caf3-4b3a-bb0c-6bb5ce63aa44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080996055 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.3080996055
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.776322196
Short name T207
Test name
Test status
Simulation time 2066446551 ps
CPU time 10.46 seconds
Started Mar 24 12:38:23 PM PDT 24
Finished Mar 24 12:38:34 PM PDT 24
Peak memory 213216 kb
Host smart-7c29171d-b028-445f-a05f-7e0d3076a589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776322196 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.776322196
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.907735470
Short name T216
Test name
Test status
Simulation time 1744533771 ps
CPU time 5.6 seconds
Started Mar 24 12:37:52 PM PDT 24
Finished Mar 24 12:37:58 PM PDT 24
Peak memory 205024 kb
Host smart-97c84ead-fbd4-4489-b019-9260b5aa656c
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=907735470 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_tl
_access.907735470
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.208853993
Short name T2
Test name
Test status
Simulation time 66210685 ps
CPU time 0.72 seconds
Started Mar 24 12:38:11 PM PDT 24
Finished Mar 24 12:38:12 PM PDT 24
Peak memory 204536 kb
Host smart-01907026-8148-4dcb-8445-e097c26c36d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208853993 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.208853993
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.1286295463
Short name T206
Test name
Test status
Simulation time 2121617076 ps
CPU time 10.02 seconds
Started Mar 24 12:38:09 PM PDT 24
Finished Mar 24 12:38:19 PM PDT 24
Peak memory 213148 kb
Host smart-f9cbe059-2eca-4e57-aeb7-c3a46f6956d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286295463 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.1286295463
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.3072547919
Short name T46
Test name
Test status
Simulation time 209161865 ps
CPU time 1.2 seconds
Started Mar 24 12:37:49 PM PDT 24
Finished Mar 24 12:37:52 PM PDT 24
Peak memory 229616 kb
Host smart-fb1b7263-26b0-4479-a959-0a4177a4fa5b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072547919 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.3072547919
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.3027720334
Short name T211
Test name
Test status
Simulation time 113329355 ps
CPU time 0.74 seconds
Started Mar 24 12:38:20 PM PDT 24
Finished Mar 24 12:38:21 PM PDT 24
Peak memory 204732 kb
Host smart-06c05e85-7294-42f2-9844-6ce0a94134f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027720334 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.3027720334
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.3631397644
Short name T170
Test name
Test status
Simulation time 18049755 ps
CPU time 0.72 seconds
Started Mar 24 12:38:17 PM PDT 24
Finished Mar 24 12:38:18 PM PDT 24
Peak memory 204692 kb
Host smart-79825463-d646-45b7-ada3-60b5d91735d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631397644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.3631397644
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.2632343028
Short name T222
Test name
Test status
Simulation time 37989094 ps
CPU time 0.71 seconds
Started Mar 24 12:39:10 PM PDT 24
Finished Mar 24 12:39:10 PM PDT 24
Peak memory 204732 kb
Host smart-5223cd9e-e2d2-4c08-a29b-e67bdcecbd91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632343028 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.2632343028
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.4213235730
Short name T151
Test name
Test status
Simulation time 24676097 ps
CPU time 0.75 seconds
Started Mar 24 12:38:35 PM PDT 24
Finished Mar 24 12:38:36 PM PDT 24
Peak memory 204708 kb
Host smart-cf92bac5-9462-498b-a4b7-f0727a1570d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213235730 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.4213235730
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.2244267493
Short name T43
Test name
Test status
Simulation time 28107384 ps
CPU time 0.73 seconds
Started Mar 24 12:38:44 PM PDT 24
Finished Mar 24 12:38:45 PM PDT 24
Peak memory 204692 kb
Host smart-17dfbe03-aa34-4456-b91c-b7563128dcc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244267493 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.2244267493
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_stress_all.3931008325
Short name T33
Test name
Test status
Simulation time 4821935926 ps
CPU time 8.38 seconds
Started Mar 24 12:38:26 PM PDT 24
Finished Mar 24 12:38:35 PM PDT 24
Peak memory 204988 kb
Host smart-cc10cf70-c634-4d24-ac30-84fb9742cfd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931008325 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.3931008325
Directory /workspace/44.rv_dm_stress_all/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.4247056117
Short name T148
Test name
Test status
Simulation time 24525137 ps
CPU time 0.74 seconds
Started Mar 24 12:38:23 PM PDT 24
Finished Mar 24 12:38:23 PM PDT 24
Peak memory 204704 kb
Host smart-a0584ec4-9cf8-4dcf-b592-8283cf019b93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247056117 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.4247056117
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.1671637725
Short name T69
Test name
Test status
Simulation time 34774940 ps
CPU time 0.72 seconds
Started Mar 24 12:38:47 PM PDT 24
Finished Mar 24 12:38:48 PM PDT 24
Peak memory 204720 kb
Host smart-2fb5991f-cb44-4ec8-b49a-7eb899441741
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671637725 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.1671637725
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.430518501
Short name T147
Test name
Test status
Simulation time 107775077 ps
CPU time 0.69 seconds
Started Mar 24 12:38:33 PM PDT 24
Finished Mar 24 12:38:34 PM PDT 24
Peak memory 204740 kb
Host smart-8aa35965-5dc1-40fc-a04e-99e029fd4ea0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430518501 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.430518501
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_stress_all.2038305830
Short name T9
Test name
Test status
Simulation time 6767725266 ps
CPU time 21.58 seconds
Started Mar 24 12:38:16 PM PDT 24
Finished Mar 24 12:38:38 PM PDT 24
Peak memory 205000 kb
Host smart-2b006f7e-039c-4b7c-af1f-0af1399bb1a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038305830 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.2038305830
Directory /workspace/47.rv_dm_stress_all/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.3096445711
Short name T145
Test name
Test status
Simulation time 119435159 ps
CPU time 0.67 seconds
Started Mar 24 12:38:18 PM PDT 24
Finished Mar 24 12:38:19 PM PDT 24
Peak memory 204716 kb
Host smart-10528aef-2eb9-44de-b464-373e5c2b00eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096445711 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.3096445711
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.40366061
Short name T189
Test name
Test status
Simulation time 19832656 ps
CPU time 0.7 seconds
Started Mar 24 12:38:48 PM PDT 24
Finished Mar 24 12:38:49 PM PDT 24
Peak memory 204752 kb
Host smart-a88143a1-09f5-4c4d-8228-ff817e903403
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40366061 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.40366061
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.193497059
Short name T195
Test name
Test status
Simulation time 7213678374 ps
CPU time 23.76 seconds
Started Mar 24 12:38:13 PM PDT 24
Finished Mar 24 12:38:38 PM PDT 24
Peak memory 205096 kb
Host smart-b390289e-9474-4dc4-a376-3c8a9f358626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193497059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.193497059
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.3856917656
Short name T186
Test name
Test status
Simulation time 966692028 ps
CPU time 3.56 seconds
Started Mar 24 12:37:53 PM PDT 24
Finished Mar 24 12:37:56 PM PDT 24
Peak memory 205036 kb
Host smart-13edb7e9-c11d-47f1-a974-a416016f48bf
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3856917656 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t
l_access.3856917656
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.493114932
Short name T202
Test name
Test status
Simulation time 5751814379 ps
CPU time 9.09 seconds
Started Mar 24 12:37:56 PM PDT 24
Finished Mar 24 12:38:09 PM PDT 24
Peak memory 205136 kb
Host smart-58c98227-6279-4c9c-a33e-df7cb4272ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493114932 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.493114932
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.4084902845
Short name T236
Test name
Test status
Simulation time 17883557 ps
CPU time 0.69 seconds
Started Mar 24 12:38:02 PM PDT 24
Finished Mar 24 12:38:03 PM PDT 24
Peak memory 204704 kb
Host smart-38a814d7-e9ea-4bb2-9ef7-94c61e60184b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084902845 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.4084902845
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.4005598107
Short name T235
Test name
Test status
Simulation time 9263385869 ps
CPU time 28.69 seconds
Started Mar 24 12:38:10 PM PDT 24
Finished Mar 24 12:38:39 PM PDT 24
Peak memory 213336 kb
Host smart-5a1dd59b-f096-4da3-85c0-24bcc4f04724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005598107 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.4005598107
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.2896661311
Short name T208
Test name
Test status
Simulation time 4538096898 ps
CPU time 17.67 seconds
Started Mar 24 12:38:07 PM PDT 24
Finished Mar 24 12:38:25 PM PDT 24
Peak memory 213296 kb
Host smart-3379cf89-4e7b-4338-b21f-044dc18f8fc6
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2896661311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t
l_access.2896661311
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.3960287317
Short name T232
Test name
Test status
Simulation time 2880562398 ps
CPU time 12.57 seconds
Started Mar 24 12:38:02 PM PDT 24
Finished Mar 24 12:38:15 PM PDT 24
Peak memory 205056 kb
Host smart-cd608d08-14b4-4e13-8459-4b1c15fed84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960287317 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.3960287317
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.3364160575
Short name T146
Test name
Test status
Simulation time 35898488 ps
CPU time 0.71 seconds
Started Mar 24 12:38:10 PM PDT 24
Finished Mar 24 12:38:11 PM PDT 24
Peak memory 204712 kb
Host smart-23dc3592-5444-4ac1-9a90-88ffa063a874
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364160575 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.3364160575
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.2974944256
Short name T20
Test name
Test status
Simulation time 14516392174 ps
CPU time 56.86 seconds
Started Mar 24 12:38:25 PM PDT 24
Finished Mar 24 12:39:22 PM PDT 24
Peak memory 213332 kb
Host smart-cf494787-c240-43a8-ac96-57cea7335a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974944256 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.2974944256
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.2758533326
Short name T184
Test name
Test status
Simulation time 13490132889 ps
CPU time 24 seconds
Started Mar 24 12:38:10 PM PDT 24
Finished Mar 24 12:38:35 PM PDT 24
Peak memory 215332 kb
Host smart-34c46209-6507-4aa4-bf51-0e5403abb59a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758533326 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.2758533326
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.1174929310
Short name T89
Test name
Test status
Simulation time 2337733763 ps
CPU time 4.16 seconds
Started Mar 24 12:38:21 PM PDT 24
Finished Mar 24 12:38:25 PM PDT 24
Peak memory 205080 kb
Host smart-ab6095f0-718c-42ff-a539-8c015f075b9e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1174929310 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.1174929310
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.2670918088
Short name T190
Test name
Test status
Simulation time 10345653224 ps
CPU time 20.03 seconds
Started Mar 24 12:37:57 PM PDT 24
Finished Mar 24 12:38:17 PM PDT 24
Peak memory 205100 kb
Host smart-2e6bc551-ab9d-4a41-8de5-725036f34a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670918088 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.2670918088
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.572712578
Short name T209
Test name
Test status
Simulation time 6036939981 ps
CPU time 12.18 seconds
Started Mar 24 12:38:19 PM PDT 24
Finished Mar 24 12:38:31 PM PDT 24
Peak memory 205168 kb
Host smart-0f3581b7-4f58-4daa-b6b2-b167a8d12bee
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=572712578 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_tl
_access.572712578
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.1283998038
Short name T205
Test name
Test status
Simulation time 4417439396 ps
CPU time 8.58 seconds
Started Mar 24 12:38:21 PM PDT 24
Finished Mar 24 12:38:29 PM PDT 24
Peak memory 205148 kb
Host smart-93fcfdf8-b071-47dc-8e3c-30a5fac46a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283998038 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.1283998038
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.828501942
Short name T159
Test name
Test status
Simulation time 49010215 ps
CPU time 0.71 seconds
Started Mar 24 12:38:17 PM PDT 24
Finished Mar 24 12:38:18 PM PDT 24
Peak memory 204688 kb
Host smart-4ab151b7-eb3b-43ac-8047-9da3c0a02493
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828501942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.828501942
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.252084497
Short name T201
Test name
Test status
Simulation time 2226299160 ps
CPU time 5.41 seconds
Started Mar 24 12:38:02 PM PDT 24
Finished Mar 24 12:38:07 PM PDT 24
Peak memory 214320 kb
Host smart-b671df20-c9d6-45dd-8435-2d228cd73f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252084497 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.252084497
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.3440708568
Short name T90
Test name
Test status
Simulation time 5453259202 ps
CPU time 18.72 seconds
Started Mar 24 12:38:14 PM PDT 24
Finished Mar 24 12:38:33 PM PDT 24
Peak memory 213320 kb
Host smart-1ada079b-9540-46fe-827d-d7182b639412
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3440708568 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t
l_access.3440708568
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.3481146044
Short name T188
Test name
Test status
Simulation time 14344415857 ps
CPU time 7.65 seconds
Started Mar 24 12:38:21 PM PDT 24
Finished Mar 24 12:38:29 PM PDT 24
Peak memory 205068 kb
Host smart-b9248a10-e207-4686-8fa6-d8b2a81a466c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481146044 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.3481146044
Directory /workspace/9.rv_dm_sba_tl_access/latest
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