Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
80.69 94.49 80.19 87.69 76.92 83.83 97.89 43.86


Total test records in report: 380
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html
T92 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1978203054 Mar 26 01:48:29 PM PDT 24 Mar 26 01:48:39 PM PDT 24 1327202494 ps
T279 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.2784320336 Mar 26 01:46:22 PM PDT 24 Mar 26 01:46:24 PM PDT 24 178502406 ps
T280 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.140563575 Mar 26 01:46:34 PM PDT 24 Mar 26 01:46:35 PM PDT 24 61139375 ps
T129 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2194363515 Mar 26 01:48:00 PM PDT 24 Mar 26 01:48:18 PM PDT 24 1403683487 ps
T281 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.3933654928 Mar 26 01:48:11 PM PDT 24 Mar 26 01:48:15 PM PDT 24 48238013 ps
T282 /workspace/coverage/cover_reg_top/21.rv_dm_tap_fsm_rand_reset.3051003013 Mar 26 01:48:36 PM PDT 24 Mar 26 01:48:51 PM PDT 24 15037573355 ps
T283 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.2245757481 Mar 26 01:48:09 PM PDT 24 Mar 26 01:48:10 PM PDT 24 338776102 ps
T85 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2657819316 Mar 26 01:45:15 PM PDT 24 Mar 26 01:45:16 PM PDT 24 409398872 ps
T107 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.3318911636 Mar 26 01:46:43 PM PDT 24 Mar 26 01:46:51 PM PDT 24 148353258 ps
T284 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2777114522 Mar 26 01:47:35 PM PDT 24 Mar 26 01:47:46 PM PDT 24 6482775509 ps
T285 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.1360736102 Mar 26 01:47:30 PM PDT 24 Mar 26 01:47:33 PM PDT 24 570978980 ps
T286 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.4112511896 Mar 26 01:47:22 PM PDT 24 Mar 26 01:47:24 PM PDT 24 85157882 ps
T287 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.3162813885 Mar 26 01:46:35 PM PDT 24 Mar 26 01:46:46 PM PDT 24 2929844751 ps
T288 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.2522105216 Mar 26 01:47:34 PM PDT 24 Mar 26 01:47:41 PM PDT 24 3311295107 ps
T289 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3009621360 Mar 26 01:47:28 PM PDT 24 Mar 26 01:47:29 PM PDT 24 313521878 ps
T108 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3721917250 Mar 26 01:48:30 PM PDT 24 Mar 26 01:48:35 PM PDT 24 1090197875 ps
T127 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.1392907457 Mar 26 01:46:44 PM PDT 24 Mar 26 01:47:08 PM PDT 24 1273617691 ps
T290 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.733367500 Mar 26 01:46:12 PM PDT 24 Mar 26 01:46:13 PM PDT 24 64136535 ps
T291 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1303794752 Mar 26 01:47:40 PM PDT 24 Mar 26 01:47:41 PM PDT 24 55698150 ps
T292 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2792873173 Mar 26 01:47:32 PM PDT 24 Mar 26 01:47:36 PM PDT 24 189373348 ps
T293 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.1780343995 Mar 26 01:45:22 PM PDT 24 Mar 26 01:45:24 PM PDT 24 51651738 ps
T294 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.3424906654 Mar 26 01:48:19 PM PDT 24 Mar 26 01:48:25 PM PDT 24 74162771 ps
T295 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.1861877776 Mar 26 01:47:23 PM PDT 24 Mar 26 01:47:24 PM PDT 24 309238708 ps
T296 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.951323086 Mar 26 01:45:54 PM PDT 24 Mar 26 01:45:55 PM PDT 24 55122697 ps
T297 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2516198120 Mar 26 01:45:55 PM PDT 24 Mar 26 01:45:56 PM PDT 24 28724321 ps
T86 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.122624084 Mar 26 01:46:51 PM PDT 24 Mar 26 01:46:54 PM PDT 24 654112825 ps
T101 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.4140747352 Mar 26 01:48:29 PM PDT 24 Mar 26 01:48:33 PM PDT 24 205584480 ps
T87 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.3896391161 Mar 26 01:45:39 PM PDT 24 Mar 26 01:45:47 PM PDT 24 2316125820 ps
T93 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.4145172649 Mar 26 01:45:56 PM PDT 24 Mar 26 01:46:03 PM PDT 24 791359693 ps
T298 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.726075801 Mar 26 01:45:12 PM PDT 24 Mar 26 01:45:16 PM PDT 24 1420863017 ps
T299 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.2565357380 Mar 26 01:48:19 PM PDT 24 Mar 26 01:48:23 PM PDT 24 95696213 ps
T300 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.320706440 Mar 26 01:47:36 PM PDT 24 Mar 26 01:47:37 PM PDT 24 54861078 ps
T301 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2500749639 Mar 26 01:48:35 PM PDT 24 Mar 26 01:48:41 PM PDT 24 1709806824 ps
T102 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2336065251 Mar 26 01:48:19 PM PDT 24 Mar 26 01:48:22 PM PDT 24 94011019 ps
T302 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.3100104412 Mar 26 01:47:03 PM PDT 24 Mar 26 01:47:16 PM PDT 24 3983079492 ps
T303 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1158061684 Mar 26 01:45:45 PM PDT 24 Mar 26 01:45:47 PM PDT 24 446242770 ps
T304 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3932534364 Mar 26 01:46:54 PM PDT 24 Mar 26 01:46:56 PM PDT 24 936484906 ps
T305 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.658633630 Mar 26 01:47:36 PM PDT 24 Mar 26 01:47:39 PM PDT 24 791183598 ps
T306 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2049055519 Mar 26 01:48:18 PM PDT 24 Mar 26 01:48:23 PM PDT 24 828861124 ps
T307 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.1361990732 Mar 26 01:46:12 PM PDT 24 Mar 26 01:46:12 PM PDT 24 52192099 ps
T308 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3852051347 Mar 26 01:46:49 PM PDT 24 Mar 26 01:47:32 PM PDT 24 22874649564 ps
T309 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2147871492 Mar 26 01:48:19 PM PDT 24 Mar 26 01:48:31 PM PDT 24 4330120317 ps
T310 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.838298950 Mar 26 01:48:23 PM PDT 24 Mar 26 01:48:32 PM PDT 24 232679350 ps
T311 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1570896915 Mar 26 01:46:22 PM PDT 24 Mar 26 01:46:23 PM PDT 24 59190412 ps
T312 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.3690771178 Mar 26 01:48:08 PM PDT 24 Mar 26 01:48:12 PM PDT 24 412069686 ps
T313 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2157641989 Mar 26 01:47:22 PM PDT 24 Mar 26 01:47:25 PM PDT 24 836431812 ps
T131 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.578670492 Mar 26 01:48:10 PM PDT 24 Mar 26 01:48:26 PM PDT 24 1346737152 ps
T314 /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.3466585287 Mar 26 01:46:43 PM PDT 24 Mar 26 01:47:13 PM PDT 24 14593806503 ps
T315 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2198658647 Mar 26 01:48:09 PM PDT 24 Mar 26 01:48:14 PM PDT 24 1164040206 ps
T94 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1484727172 Mar 26 01:46:44 PM PDT 24 Mar 26 01:48:02 PM PDT 24 8317541672 ps
T316 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1425685742 Mar 26 01:47:35 PM PDT 24 Mar 26 01:47:37 PM PDT 24 52398782 ps
T317 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2781094638 Mar 26 01:48:10 PM PDT 24 Mar 26 01:48:11 PM PDT 24 38519240 ps
T318 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.2978112486 Mar 26 01:45:31 PM PDT 24 Mar 26 01:45:35 PM PDT 24 1221035693 ps
T118 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.2866563950 Mar 26 01:45:47 PM PDT 24 Mar 26 01:45:51 PM PDT 24 162380780 ps
T319 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.4135628657 Mar 26 01:45:48 PM PDT 24 Mar 26 01:46:38 PM PDT 24 11816444828 ps
T128 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.66599648 Mar 26 01:47:31 PM PDT 24 Mar 26 01:47:48 PM PDT 24 1015116580 ps
T320 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.698389713 Mar 26 01:47:11 PM PDT 24 Mar 26 01:47:14 PM PDT 24 86003857 ps
T104 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.763897507 Mar 26 01:47:58 PM PDT 24 Mar 26 01:48:01 PM PDT 24 358164723 ps
T95 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.1730549345 Mar 26 01:45:54 PM PDT 24 Mar 26 01:45:57 PM PDT 24 1054435562 ps
T321 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.279409758 Mar 26 01:48:29 PM PDT 24 Mar 26 01:48:33 PM PDT 24 298033541 ps
T322 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.776834754 Mar 26 01:46:21 PM PDT 24 Mar 26 01:46:24 PM PDT 24 323964679 ps
T323 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3265308729 Mar 26 01:45:57 PM PDT 24 Mar 26 01:45:58 PM PDT 24 121150493 ps
T88 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2216154107 Mar 26 01:46:43 PM PDT 24 Mar 26 01:46:44 PM PDT 24 191696795 ps
T324 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.245845870 Mar 26 01:45:15 PM PDT 24 Mar 26 01:45:16 PM PDT 24 346135178 ps
T325 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.1250675793 Mar 26 01:48:37 PM PDT 24 Mar 26 01:48:39 PM PDT 24 343018660 ps
T326 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.3588901751 Mar 26 01:46:05 PM PDT 24 Mar 26 01:46:08 PM PDT 24 621344829 ps
T105 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.2835233853 Mar 26 01:45:24 PM PDT 24 Mar 26 01:45:25 PM PDT 24 66593012 ps
T327 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.4235689507 Mar 26 01:47:29 PM PDT 24 Mar 26 01:47:32 PM PDT 24 1001226427 ps
T328 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.148607582 Mar 26 01:46:03 PM PDT 24 Mar 26 01:46:05 PM PDT 24 423509026 ps
T329 /workspace/coverage/cover_reg_top/13.rv_dm_tap_fsm_rand_reset.2746645188 Mar 26 01:48:04 PM PDT 24 Mar 26 01:48:36 PM PDT 24 16836027324 ps
T330 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.47860279 Mar 26 01:48:17 PM PDT 24 Mar 26 01:48:19 PM PDT 24 71954035 ps
T331 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.1087548617 Mar 26 01:47:36 PM PDT 24 Mar 26 01:47:39 PM PDT 24 152426290 ps
T332 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1074178763 Mar 26 01:47:24 PM PDT 24 Mar 26 01:47:29 PM PDT 24 283533298 ps
T333 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.688080155 Mar 26 01:48:09 PM PDT 24 Mar 26 01:48:10 PM PDT 24 138023137 ps
T334 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.558583929 Mar 26 01:47:55 PM PDT 24 Mar 26 01:48:06 PM PDT 24 1638849046 ps
T335 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.386865203 Mar 26 01:45:29 PM PDT 24 Mar 26 01:45:56 PM PDT 24 848924298 ps
T106 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2591326946 Mar 26 01:46:43 PM PDT 24 Mar 26 01:46:45 PM PDT 24 308634435 ps
T336 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1070112580 Mar 26 01:48:00 PM PDT 24 Mar 26 01:48:01 PM PDT 24 51313477 ps
T337 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.1619500449 Mar 26 01:46:58 PM PDT 24 Mar 26 01:46:59 PM PDT 24 49123555 ps
T96 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2369486498 Mar 26 01:45:31 PM PDT 24 Mar 26 01:45:35 PM PDT 24 379173497 ps
T133 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.142472389 Mar 26 01:48:28 PM PDT 24 Mar 26 01:48:39 PM PDT 24 506249296 ps
T97 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.4091430428 Mar 26 01:48:17 PM PDT 24 Mar 26 01:48:24 PM PDT 24 555915601 ps
T338 /workspace/coverage/cover_reg_top/27.rv_dm_tap_fsm_rand_reset.1717265453 Mar 26 01:48:45 PM PDT 24 Mar 26 01:48:58 PM PDT 24 14090199399 ps
T339 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.798892675 Mar 26 01:47:52 PM PDT 24 Mar 26 01:47:54 PM PDT 24 112058666 ps
T340 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.247164349 Mar 26 01:45:54 PM PDT 24 Mar 26 01:46:47 PM PDT 24 12750458481 ps
T341 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1195694682 Mar 26 01:47:59 PM PDT 24 Mar 26 01:48:00 PM PDT 24 101105749 ps
T342 /workspace/coverage/cover_reg_top/29.rv_dm_tap_fsm_rand_reset.269227413 Mar 26 01:48:46 PM PDT 24 Mar 26 01:49:06 PM PDT 24 7020750598 ps
T343 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2713587568 Mar 26 01:47:37 PM PDT 24 Mar 26 01:47:38 PM PDT 24 458433049 ps
T344 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.4127065022 Mar 26 01:48:10 PM PDT 24 Mar 26 01:48:12 PM PDT 24 199837378 ps
T345 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1335401552 Mar 26 01:46:21 PM PDT 24 Mar 26 01:46:50 PM PDT 24 3806196718 ps
T346 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.1749309675 Mar 26 01:45:38 PM PDT 24 Mar 26 01:45:44 PM PDT 24 2897159774 ps
T347 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.2765657760 Mar 26 01:46:51 PM PDT 24 Mar 26 01:46:53 PM PDT 24 288413621 ps
T348 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.1694523543 Mar 26 01:45:10 PM PDT 24 Mar 26 01:45:11 PM PDT 24 60249935 ps
T349 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1858365554 Mar 26 01:46:43 PM PDT 24 Mar 26 01:47:05 PM PDT 24 12380085548 ps
T350 /workspace/coverage/cover_reg_top/18.rv_dm_tap_fsm_rand_reset.2321448878 Mar 26 01:48:29 PM PDT 24 Mar 26 01:49:05 PM PDT 24 11195906036 ps
T351 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.3538925113 Mar 26 01:47:30 PM PDT 24 Mar 26 01:47:34 PM PDT 24 220538572 ps
T352 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.576072701 Mar 26 01:47:19 PM PDT 24 Mar 26 01:47:23 PM PDT 24 225732490 ps
T353 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.4119208988 Mar 26 01:47:13 PM PDT 24 Mar 26 01:47:14 PM PDT 24 56761811 ps
T354 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.1753362176 Mar 26 01:47:29 PM PDT 24 Mar 26 01:47:31 PM PDT 24 96994419 ps
T355 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.3168885017 Mar 26 01:48:38 PM PDT 24 Mar 26 01:48:42 PM PDT 24 205887618 ps
T356 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1117843557 Mar 26 01:46:43 PM PDT 24 Mar 26 01:46:44 PM PDT 24 35878240 ps
T134 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2536974579 Mar 26 01:47:44 PM PDT 24 Mar 26 01:47:54 PM PDT 24 1818588224 ps
T357 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.2882621000 Mar 26 01:48:10 PM PDT 24 Mar 26 01:48:15 PM PDT 24 710444354 ps
T358 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.3360570242 Mar 26 01:46:43 PM PDT 24 Mar 26 01:46:47 PM PDT 24 205463262 ps
T359 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.1826570762 Mar 26 01:46:05 PM PDT 24 Mar 26 01:46:06 PM PDT 24 103082960 ps
T119 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.1303350447 Mar 26 01:47:17 PM PDT 24 Mar 26 01:47:22 PM PDT 24 852180928 ps
T360 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.3720582279 Mar 26 01:46:21 PM PDT 24 Mar 26 01:46:59 PM PDT 24 24568284088 ps
T120 /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.4065984162 Mar 26 01:45:47 PM PDT 24 Mar 26 01:46:24 PM PDT 24 10792911869 ps
T361 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2585814893 Mar 26 01:48:35 PM PDT 24 Mar 26 01:48:41 PM PDT 24 1456180641 ps
T362 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3959874756 Mar 26 01:45:38 PM PDT 24 Mar 26 01:45:39 PM PDT 24 113738472 ps
T363 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.3335118138 Mar 26 01:47:06 PM PDT 24 Mar 26 01:47:12 PM PDT 24 122222136 ps
T132 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2175350329 Mar 26 01:48:10 PM PDT 24 Mar 26 01:48:26 PM PDT 24 1341903536 ps
T364 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3920804371 Mar 26 01:47:23 PM PDT 24 Mar 26 01:47:24 PM PDT 24 285865707 ps
T365 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2954229046 Mar 26 01:47:36 PM PDT 24 Mar 26 01:47:44 PM PDT 24 986741967 ps
T366 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3178564176 Mar 26 01:48:35 PM PDT 24 Mar 26 01:48:41 PM PDT 24 127183148 ps
T130 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.614659120 Mar 26 01:47:30 PM PDT 24 Mar 26 01:47:51 PM PDT 24 1304330886 ps
T367 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.4220720681 Mar 26 01:47:54 PM PDT 24 Mar 26 01:47:56 PM PDT 24 293629592 ps
T368 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.1746128941 Mar 26 01:48:19 PM PDT 24 Mar 26 01:48:21 PM PDT 24 74220270 ps
T369 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.2945259848 Mar 26 01:47:57 PM PDT 24 Mar 26 01:48:02 PM PDT 24 833333710 ps
T370 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.2460119658 Mar 26 01:48:01 PM PDT 24 Mar 26 01:48:03 PM PDT 24 30372640 ps
T371 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1034236493 Mar 26 01:47:14 PM PDT 24 Mar 26 01:47:19 PM PDT 24 5072765903 ps
T372 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3473916273 Mar 26 01:46:23 PM PDT 24 Mar 26 01:46:27 PM PDT 24 229903705 ps
T373 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.2222934915 Mar 26 01:48:20 PM PDT 24 Mar 26 01:48:29 PM PDT 24 2139917556 ps
T374 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.2828940337 Mar 26 01:45:24 PM PDT 24 Mar 26 01:45:25 PM PDT 24 15709022 ps
T375 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2894130920 Mar 26 01:48:27 PM PDT 24 Mar 26 01:48:31 PM PDT 24 612816109 ps
T376 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.1295068411 Mar 26 01:48:10 PM PDT 24 Mar 26 01:48:15 PM PDT 24 2478474694 ps
T377 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2160865409 Mar 26 01:47:01 PM PDT 24 Mar 26 01:47:02 PM PDT 24 72049610 ps
T378 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.539437095 Mar 26 01:47:52 PM PDT 24 Mar 26 01:47:54 PM PDT 24 158123828 ps
T379 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1491908884 Mar 26 01:46:34 PM PDT 24 Mar 26 01:46:36 PM PDT 24 355802225 ps
T380 /workspace/coverage/cover_reg_top/38.rv_dm_tap_fsm_rand_reset.3576790898 Mar 26 01:48:55 PM PDT 24 Mar 26 01:49:09 PM PDT 24 7092912160 ps

Test location /workspace/coverage/default/47.rv_dm_stress_all.3641678068
Short name T5
Test name
Test status
Simulation time 1844980280 ps
CPU time 6.91 seconds
Started Mar 26 03:23:54 PM PDT 24
Finished Mar 26 03:24:01 PM PDT 24
Peak memory 205036 kb
Host smart-1f5dc96e-4c6f-42a2-9337-267b1e8800f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641678068 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.3641678068
Directory /workspace/47.rv_dm_stress_all/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.3059803231
Short name T15
Test name
Test status
Simulation time 3467398584 ps
CPU time 13.08 seconds
Started Mar 26 03:23:42 PM PDT 24
Finished Mar 26 03:23:56 PM PDT 24
Peak memory 205116 kb
Host smart-e7948e06-697f-4524-8393-9abbdb58975a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059803231 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.3059803231
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/22.rv_dm_tap_fsm_rand_reset.1591454634
Short name T59
Test name
Test status
Simulation time 7644170822 ps
CPU time 25.88 seconds
Started Mar 26 01:48:37 PM PDT 24
Finished Mar 26 01:49:03 PM PDT 24
Peak memory 213240 kb
Host smart-6afda3bb-a27b-49e0-be3b-4de4331dc4ab
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591454634 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 22.rv_dm_tap_fsm_rand_reset.1591454634
Directory /workspace/22.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/48.rv_dm_stress_all.3883045780
Short name T12
Test name
Test status
Simulation time 3229074762 ps
CPU time 11.28 seconds
Started Mar 26 03:23:53 PM PDT 24
Finished Mar 26 03:24:05 PM PDT 24
Peak memory 205060 kb
Host smart-8472dba4-fe10-426d-ae8a-2813a4b3f19e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883045780 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.3883045780
Directory /workspace/48.rv_dm_stress_all/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.1398122292
Short name T21
Test name
Test status
Simulation time 56398249 ps
CPU time 0.69 seconds
Started Mar 26 03:24:19 PM PDT 24
Finished Mar 26 03:24:19 PM PDT 24
Peak memory 204804 kb
Host smart-a458b761-d84d-4698-a4ed-4db9d93d1bf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398122292 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.1398122292
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3812732030
Short name T28
Test name
Test status
Simulation time 291569817 ps
CPU time 6.43 seconds
Started Mar 26 01:47:50 PM PDT 24
Finished Mar 26 01:47:57 PM PDT 24
Peak memory 204956 kb
Host smart-2746854a-0e7e-4510-8a55-d2346984078b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812732030 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.3812732030
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1901377781
Short name T112
Test name
Test status
Simulation time 569578697 ps
CPU time 10.77 seconds
Started Mar 26 01:47:10 PM PDT 24
Finished Mar 26 01:47:21 PM PDT 24
Peak memory 215660 kb
Host smart-b16e114b-99bf-4cdc-a5a2-4416916cd2ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901377781 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.1901377781
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.2428556199
Short name T27
Test name
Test status
Simulation time 460607907 ps
CPU time 5.46 seconds
Started Mar 26 01:47:49 PM PDT 24
Finished Mar 26 01:47:55 PM PDT 24
Peak memory 213064 kb
Host smart-3a41bcf5-b193-4479-b2a6-e82bf3cca02e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428556199 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.2428556199
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.2471466790
Short name T17
Test name
Test status
Simulation time 356176677 ps
CPU time 1.58 seconds
Started Mar 26 03:23:37 PM PDT 24
Finished Mar 26 03:23:39 PM PDT 24
Peak memory 229188 kb
Host smart-12de601b-044e-4a26-8f52-68645c2215c1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471466790 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.2471466790
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.3387978171
Short name T52
Test name
Test status
Simulation time 1804836611 ps
CPU time 6.3 seconds
Started Mar 26 03:23:41 PM PDT 24
Finished Mar 26 03:23:48 PM PDT 24
Peak memory 204952 kb
Host smart-27e97923-992c-4418-9c9c-461af78f0706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387978171 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.3387978171
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.2820120226
Short name T50
Test name
Test status
Simulation time 86003481 ps
CPU time 0.89 seconds
Started Mar 26 03:23:32 PM PDT 24
Finished Mar 26 03:23:33 PM PDT 24
Peak memory 204836 kb
Host smart-0b56fb7a-f5af-4779-9840-9cc780c8c60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820120226 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.2820120226
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.3298773664
Short name T10
Test name
Test status
Simulation time 19297537630 ps
CPU time 71.08 seconds
Started Mar 26 03:23:49 PM PDT 24
Finished Mar 26 03:25:01 PM PDT 24
Peak memory 213404 kb
Host smart-2999c8ff-c060-46b8-aafc-c4835a9d3a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298773664 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.3298773664
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.264528129
Short name T48
Test name
Test status
Simulation time 283794017 ps
CPU time 1.58 seconds
Started Mar 26 03:23:36 PM PDT 24
Finished Mar 26 03:23:38 PM PDT 24
Peak memory 204792 kb
Host smart-735baad2-6c9a-4a25-afaf-7ffc6a2b0956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264528129 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.264528129
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.1759012349
Short name T3
Test name
Test status
Simulation time 33430912 ps
CPU time 0.81 seconds
Started Mar 26 03:23:36 PM PDT 24
Finished Mar 26 03:23:38 PM PDT 24
Peak memory 213056 kb
Host smart-207ef513-d04a-47e0-a47f-b53ff092c0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759012349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.1759012349
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2194363515
Short name T129
Test name
Test status
Simulation time 1403683487 ps
CPU time 17.94 seconds
Started Mar 26 01:48:00 PM PDT 24
Finished Mar 26 01:48:18 PM PDT 24
Peak memory 221188 kb
Host smart-ce1d790c-03e9-493c-8548-d8868f0f5c95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194363515 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.2
194363515
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2303132157
Short name T98
Test name
Test status
Simulation time 29071440 ps
CPU time 1.49 seconds
Started Mar 26 01:45:55 PM PDT 24
Finished Mar 26 01:45:57 PM PDT 24
Peak memory 213160 kb
Host smart-75443672-bef8-42eb-b2dd-756c2571baa9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303132157 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.2303132157
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.44494817
Short name T20
Test name
Test status
Simulation time 148819945 ps
CPU time 0.74 seconds
Started Mar 26 03:23:50 PM PDT 24
Finished Mar 26 03:23:51 PM PDT 24
Peak memory 204804 kb
Host smart-1bebb72a-c020-4e91-9bb8-efcfbba636b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44494817 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.44494817
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.164286387
Short name T45
Test name
Test status
Simulation time 340006618 ps
CPU time 1.72 seconds
Started Mar 26 03:23:38 PM PDT 24
Finished Mar 26 03:23:40 PM PDT 24
Peak memory 204968 kb
Host smart-15257845-fcf1-4789-9d70-ac638225e506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164286387 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.164286387
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.614659120
Short name T130
Test name
Test status
Simulation time 1304330886 ps
CPU time 21 seconds
Started Mar 26 01:47:30 PM PDT 24
Finished Mar 26 01:47:51 PM PDT 24
Peak memory 213184 kb
Host smart-21329f55-1a71-4cce-b0c5-34d1e3243932
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614659120 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.614659120
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3350867703
Short name T264
Test name
Test status
Simulation time 62384331 ps
CPU time 0.72 seconds
Started Mar 26 01:45:10 PM PDT 24
Finished Mar 26 01:45:12 PM PDT 24
Peak memory 204648 kb
Host smart-ea719d79-9ed8-4220-917a-a382a3092510
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350867703 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.3
350867703
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.1796725812
Short name T54
Test name
Test status
Simulation time 140708946 ps
CPU time 0.7 seconds
Started Mar 26 03:23:54 PM PDT 24
Finished Mar 26 03:23:55 PM PDT 24
Peak memory 204820 kb
Host smart-f84220e5-af36-4bac-a66e-80523e29f93b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796725812 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.1796725812
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.3151788069
Short name T124
Test name
Test status
Simulation time 6362148517 ps
CPU time 19.94 seconds
Started Mar 26 01:48:36 PM PDT 24
Finished Mar 26 01:48:56 PM PDT 24
Peak memory 213188 kb
Host smart-a96f89b6-dd20-4d79-a839-e6108bf5e439
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151788069 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.3
151788069
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.877856472
Short name T137
Test name
Test status
Simulation time 267488149 ps
CPU time 1.8 seconds
Started Mar 26 03:23:32 PM PDT 24
Finished Mar 26 03:23:34 PM PDT 24
Peak memory 205016 kb
Host smart-20c7e5af-6bfb-497c-ac75-86581e963d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877856472 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.877856472
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2657819316
Short name T85
Test name
Test status
Simulation time 409398872 ps
CPU time 1.11 seconds
Started Mar 26 01:45:15 PM PDT 24
Finished Mar 26 01:45:16 PM PDT 24
Peak memory 204996 kb
Host smart-df8ad3c2-ea55-468e-b5a6-13cdeb7d13bc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657819316 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.2657819316
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.179587635
Short name T42
Test name
Test status
Simulation time 137829235 ps
CPU time 0.92 seconds
Started Mar 26 03:23:34 PM PDT 24
Finished Mar 26 03:23:35 PM PDT 24
Peak memory 204672 kb
Host smart-078bd269-2a1d-4e70-9728-936b1fc9eee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179587635 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.179587635
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.2997845844
Short name T126
Test name
Test status
Simulation time 267400566 ps
CPU time 8.72 seconds
Started Mar 26 01:45:23 PM PDT 24
Finished Mar 26 01:45:31 PM PDT 24
Peak memory 213260 kb
Host smart-f60a6d29-7278-42e2-acbf-6b85f758c4c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997845844 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.2997845844
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.4065984162
Short name T120
Test name
Test status
Simulation time 10792911869 ps
CPU time 36.12 seconds
Started Mar 26 01:45:47 PM PDT 24
Finished Mar 26 01:46:24 PM PDT 24
Peak memory 229564 kb
Host smart-b59e9960-aa86-4a46-9398-d0acb1070be4
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065984162 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.4065984162
Directory /workspace/1.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.578670492
Short name T131
Test name
Test status
Simulation time 1346737152 ps
CPU time 16.46 seconds
Started Mar 26 01:48:10 PM PDT 24
Finished Mar 26 01:48:26 PM PDT 24
Peak memory 215072 kb
Host smart-8014c40d-f830-4253-9f3b-9ced8bcc9d1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578670492 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.578670492
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.687029777
Short name T36
Test name
Test status
Simulation time 23840766 ps
CPU time 0.7 seconds
Started Mar 26 03:24:11 PM PDT 24
Finished Mar 26 03:24:12 PM PDT 24
Peak memory 204784 kb
Host smart-20fe36a3-7bb4-4b2b-89b6-e4a40a198517
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687029777 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.687029777
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3154889042
Short name T109
Test name
Test status
Simulation time 567480388 ps
CPU time 27.36 seconds
Started Mar 26 01:45:11 PM PDT 24
Finished Mar 26 01:45:39 PM PDT 24
Peak memory 205028 kb
Host smart-acac6675-4f5a-426d-90c5-43b22bd029dc
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154889042 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.3154889042
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.386865203
Short name T335
Test name
Test status
Simulation time 848924298 ps
CPU time 27.24 seconds
Started Mar 26 01:45:29 PM PDT 24
Finished Mar 26 01:45:56 PM PDT 24
Peak memory 205200 kb
Host smart-17cda575-ea76-4d46-99c9-e35fe4fc4f72
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386865203 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.386865203
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.2835233853
Short name T105
Test name
Test status
Simulation time 66593012 ps
CPU time 1.65 seconds
Started Mar 26 01:45:24 PM PDT 24
Finished Mar 26 01:45:25 PM PDT 24
Peak memory 213164 kb
Host smart-b96c0b3b-1385-4d19-b50b-6ff3ab565ff5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835233853 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.2835233853
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.2978112486
Short name T318
Test name
Test status
Simulation time 1221035693 ps
CPU time 4.16 seconds
Started Mar 26 01:45:31 PM PDT 24
Finished Mar 26 01:45:35 PM PDT 24
Peak memory 216664 kb
Host smart-a266ff61-90c9-4e87-a5f5-7d7cad78e45f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978112486 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.2978112486
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.1780343995
Short name T293
Test name
Test status
Simulation time 51651738 ps
CPU time 1.55 seconds
Started Mar 26 01:45:22 PM PDT 24
Finished Mar 26 01:45:24 PM PDT 24
Peak memory 213056 kb
Host smart-9ce0c313-ed64-488f-930e-a1e41baf012c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780343995 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.1780343995
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.2263570408
Short name T278
Test name
Test status
Simulation time 30139839508 ps
CPU time 91.69 seconds
Started Mar 26 01:45:13 PM PDT 24
Finished Mar 26 01:46:46 PM PDT 24
Peak memory 204908 kb
Host smart-32ac8a86-e64b-4d7f-bcf7-08962a8f1f42
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263570408 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.2263570408
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.3482319645
Short name T259
Test name
Test status
Simulation time 29359527499 ps
CPU time 26.83 seconds
Started Mar 26 01:46:31 PM PDT 24
Finished Mar 26 01:46:59 PM PDT 24
Peak memory 203880 kb
Host smart-3f1faccd-fdf5-45eb-bc0a-9a8c7fbd15df
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482319645 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_bit_bash.3482319645
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.245845870
Short name T324
Test name
Test status
Simulation time 346135178 ps
CPU time 1.02 seconds
Started Mar 26 01:45:15 PM PDT 24
Finished Mar 26 01:45:16 PM PDT 24
Peak memory 204744 kb
Host smart-881db92c-6a0a-46c1-aa2f-80a8cf39daa8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245845870 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.245845870
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.314846081
Short name T274
Test name
Test status
Simulation time 73710308 ps
CPU time 0.74 seconds
Started Mar 26 01:45:09 PM PDT 24
Finished Mar 26 01:45:10 PM PDT 24
Peak memory 204564 kb
Host smart-73cfc043-7feb-42fa-805f-4979e4963204
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314846081 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr
_aliasing.314846081
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.726075801
Short name T298
Test name
Test status
Simulation time 1420863017 ps
CPU time 3.22 seconds
Started Mar 26 01:45:12 PM PDT 24
Finished Mar 26 01:45:16 PM PDT 24
Peak memory 204760 kb
Host smart-93228adf-4080-491b-812f-593fdfcb93b7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726075801 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr
_bit_bash.726075801
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.1694523543
Short name T348
Test name
Test status
Simulation time 60249935 ps
CPU time 0.85 seconds
Started Mar 26 01:45:10 PM PDT 24
Finished Mar 26 01:45:11 PM PDT 24
Peak memory 204692 kb
Host smart-12376a73-bfdb-47b5-b14a-399ff2cc5301
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694523543 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.1694523543
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.2828940337
Short name T374
Test name
Test status
Simulation time 15709022 ps
CPU time 0.67 seconds
Started Mar 26 01:45:24 PM PDT 24
Finished Mar 26 01:45:25 PM PDT 24
Peak memory 204660 kb
Host smart-dfa1ecdc-f8b9-4b32-a82a-e15833953a01
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828940337 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.2828940337
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.2113883720
Short name T266
Test name
Test status
Simulation time 25563432 ps
CPU time 0.65 seconds
Started Mar 26 01:45:22 PM PDT 24
Finished Mar 26 01:45:23 PM PDT 24
Peak memory 204536 kb
Host smart-f88af16a-4b0f-4699-aa85-0e4c13ea72c2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113883720 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.2113883720
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2369486498
Short name T96
Test name
Test status
Simulation time 379173497 ps
CPU time 3.87 seconds
Started Mar 26 01:45:31 PM PDT 24
Finished Mar 26 01:45:35 PM PDT 24
Peak memory 204868 kb
Host smart-90406d10-9646-4285-ae62-1bd8b5426af6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369486498 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.2369486498
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.1549289167
Short name T67
Test name
Test status
Simulation time 193361400 ps
CPU time 2.85 seconds
Started Mar 26 01:45:15 PM PDT 24
Finished Mar 26 01:45:18 PM PDT 24
Peak memory 213204 kb
Host smart-2acb57e7-321b-4ccb-88d6-e8d67e3cfce8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549289167 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.1549289167
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3418589329
Short name T89
Test name
Test status
Simulation time 15387448129 ps
CPU time 72.07 seconds
Started Mar 26 01:47:01 PM PDT 24
Finished Mar 26 01:48:13 PM PDT 24
Peak memory 217308 kb
Host smart-0c090127-3083-49c7-901c-1762cd8d1876
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418589329 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.3418589329
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.247164349
Short name T340
Test name
Test status
Simulation time 12750458481 ps
CPU time 53.04 seconds
Started Mar 26 01:45:54 PM PDT 24
Finished Mar 26 01:46:47 PM PDT 24
Peak memory 213224 kb
Host smart-bd0d4e8e-951b-4b73-be34-2033978483f6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247164349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.247164349
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.1730549345
Short name T95
Test name
Test status
Simulation time 1054435562 ps
CPU time 2.44 seconds
Started Mar 26 01:45:54 PM PDT 24
Finished Mar 26 01:45:57 PM PDT 24
Peak memory 214152 kb
Host smart-60fa3d1e-17a0-4901-b3c3-0b6efafde676
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730549345 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.1730549345
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.170923779
Short name T68
Test name
Test status
Simulation time 4069714640 ps
CPU time 3.83 seconds
Started Mar 26 01:45:54 PM PDT 24
Finished Mar 26 01:45:58 PM PDT 24
Peak memory 215284 kb
Host smart-890a516b-eb69-422d-90d4-0623b1b45431
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170923779 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.170923779
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.365424355
Short name T267
Test name
Test status
Simulation time 22855024827 ps
CPU time 22.89 seconds
Started Mar 26 01:45:47 PM PDT 24
Finished Mar 26 01:46:10 PM PDT 24
Peak memory 204908 kb
Host smart-84ea18bc-57b6-44c3-afa6-15688c2d3f3b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365424355 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr
_aliasing.365424355
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.4135628657
Short name T319
Test name
Test status
Simulation time 11816444828 ps
CPU time 49.87 seconds
Started Mar 26 01:45:48 PM PDT 24
Finished Mar 26 01:46:38 PM PDT 24
Peak memory 204844 kb
Host smart-2ab1fcb6-6dc1-4d84-a708-d1721968a1f3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135628657 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_bit_bash.4135628657
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.3896391161
Short name T87
Test name
Test status
Simulation time 2316125820 ps
CPU time 7.27 seconds
Started Mar 26 01:45:39 PM PDT 24
Finished Mar 26 01:45:47 PM PDT 24
Peak memory 204960 kb
Host smart-527069aa-ee52-4d8d-b27d-847c021baf18
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896391161 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.3896391161
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1158061684
Short name T303
Test name
Test status
Simulation time 446242770 ps
CPU time 1.99 seconds
Started Mar 26 01:45:45 PM PDT 24
Finished Mar 26 01:45:47 PM PDT 24
Peak memory 204840 kb
Host smart-4cb2db25-8e37-4f47-ba19-fa98f4f2034d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158061684 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.1
158061684
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.1749309675
Short name T346
Test name
Test status
Simulation time 2897159774 ps
CPU time 5.92 seconds
Started Mar 26 01:45:38 PM PDT 24
Finished Mar 26 01:45:44 PM PDT 24
Peak memory 204796 kb
Host smart-27124027-e79e-4622-b83a-0c320bcd645d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749309675 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.1749309675
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2160865409
Short name T377
Test name
Test status
Simulation time 72049610 ps
CPU time 0.84 seconds
Started Mar 26 01:47:01 PM PDT 24
Finished Mar 26 01:47:02 PM PDT 24
Peak memory 204564 kb
Host smart-345ae401-7bd9-4751-9f4c-da19376a8114
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160865409 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.2160865409
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3959874756
Short name T362
Test name
Test status
Simulation time 113738472 ps
CPU time 0.78 seconds
Started Mar 26 01:45:38 PM PDT 24
Finished Mar 26 01:45:39 PM PDT 24
Peak memory 204624 kb
Host smart-6858f1a9-5c4c-4b34-acf0-1011c6248954
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959874756 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.3
959874756
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.951323086
Short name T296
Test name
Test status
Simulation time 55122697 ps
CPU time 0.67 seconds
Started Mar 26 01:45:54 PM PDT 24
Finished Mar 26 01:45:55 PM PDT 24
Peak memory 204656 kb
Host smart-b322479b-020b-4c38-b858-dc6e30381a9c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951323086 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_part
ial_access.951323086
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.1381450423
Short name T249
Test name
Test status
Simulation time 49662780 ps
CPU time 0.66 seconds
Started Mar 26 01:45:54 PM PDT 24
Finished Mar 26 01:45:55 PM PDT 24
Peak memory 204616 kb
Host smart-4fe7e1ac-8a9f-4424-bdc0-a8bb6a51b14d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381450423 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.1381450423
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.4145172649
Short name T93
Test name
Test status
Simulation time 791359693 ps
CPU time 7.32 seconds
Started Mar 26 01:45:56 PM PDT 24
Finished Mar 26 01:46:03 PM PDT 24
Peak memory 204880 kb
Host smart-8f9573be-9ec2-4d81-9c78-fb8ff39d6edf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145172649 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_
csr_outstanding.4145172649
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.2866563950
Short name T118
Test name
Test status
Simulation time 162380780 ps
CPU time 4.29 seconds
Started Mar 26 01:45:47 PM PDT 24
Finished Mar 26 01:45:51 PM PDT 24
Peak memory 213316 kb
Host smart-747f55a4-95ab-4c53-ba0c-2034cf65aaaf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866563950 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.2866563950
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.3098310877
Short name T80
Test name
Test status
Simulation time 2464917596 ps
CPU time 20.74 seconds
Started Mar 26 01:45:54 PM PDT 24
Finished Mar 26 01:46:15 PM PDT 24
Peak memory 221320 kb
Host smart-87d80efd-0d86-4408-b7eb-8a7abb8a32aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098310877 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.3098310877
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.539437095
Short name T378
Test name
Test status
Simulation time 158123828 ps
CPU time 2.23 seconds
Started Mar 26 01:47:52 PM PDT 24
Finished Mar 26 01:47:54 PM PDT 24
Peak memory 215516 kb
Host smart-422b77c5-e06a-42d9-9b5b-b58fba94db89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539437095 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.539437095
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.798892675
Short name T339
Test name
Test status
Simulation time 112058666 ps
CPU time 1.44 seconds
Started Mar 26 01:47:52 PM PDT 24
Finished Mar 26 01:47:54 PM PDT 24
Peak memory 218628 kb
Host smart-2fda7af8-72df-494f-b999-4da7caad3f71
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798892675 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.798892675
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2713587568
Short name T343
Test name
Test status
Simulation time 458433049 ps
CPU time 1.32 seconds
Started Mar 26 01:47:37 PM PDT 24
Finished Mar 26 01:47:38 PM PDT 24
Peak memory 204816 kb
Host smart-8f743d1d-9d57-4d50-ac9b-a91f9cca9864
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713587568 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
2713587568
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.320706440
Short name T300
Test name
Test status
Simulation time 54861078 ps
CPU time 0.74 seconds
Started Mar 26 01:47:36 PM PDT 24
Finished Mar 26 01:47:37 PM PDT 24
Peak memory 204560 kb
Host smart-5474d143-dff1-4dcc-aeba-5dbb35c5faf1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320706440 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.320706440
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2536974579
Short name T134
Test name
Test status
Simulation time 1818588224 ps
CPU time 10.19 seconds
Started Mar 26 01:47:44 PM PDT 24
Finished Mar 26 01:47:54 PM PDT 24
Peak memory 216036 kb
Host smart-b9ea9a53-7b44-4a2a-ac1b-a9544c35ea68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536974579 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.2
536974579
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3416500161
Short name T81
Test name
Test status
Simulation time 608030246 ps
CPU time 4.32 seconds
Started Mar 26 01:47:53 PM PDT 24
Finished Mar 26 01:47:59 PM PDT 24
Peak memory 218592 kb
Host smart-54d45a87-7a04-4aea-840c-bab8d1735440
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416500161 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.3416500161
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.763897507
Short name T104
Test name
Test status
Simulation time 358164723 ps
CPU time 2.33 seconds
Started Mar 26 01:47:58 PM PDT 24
Finished Mar 26 01:48:01 PM PDT 24
Peak memory 213104 kb
Host smart-abebc8bc-66f7-48e2-8a73-ffeb033fe6bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763897507 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.763897507
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.4220720681
Short name T367
Test name
Test status
Simulation time 293629592 ps
CPU time 1.55 seconds
Started Mar 26 01:47:54 PM PDT 24
Finished Mar 26 01:47:56 PM PDT 24
Peak memory 204764 kb
Host smart-b91e55c9-3d1a-4cc5-8e23-8bc5eec02903
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220720681 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
4220720681
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.1754657189
Short name T276
Test name
Test status
Simulation time 60650208 ps
CPU time 0.72 seconds
Started Mar 26 01:47:44 PM PDT 24
Finished Mar 26 01:47:45 PM PDT 24
Peak memory 204548 kb
Host smart-3cfdf777-09d4-4ffe-834f-f4963d09bcda
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754657189 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.
1754657189
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.2945259848
Short name T369
Test name
Test status
Simulation time 833333710 ps
CPU time 4 seconds
Started Mar 26 01:47:57 PM PDT 24
Finished Mar 26 01:48:02 PM PDT 24
Peak memory 204892 kb
Host smart-ee95d880-07b6-4992-a527-c7a1c239fce7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945259848 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same
_csr_outstanding.2945259848
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.2255810271
Short name T270
Test name
Test status
Simulation time 1520667835 ps
CPU time 5.08 seconds
Started Mar 26 01:47:58 PM PDT 24
Finished Mar 26 01:48:03 PM PDT 24
Peak memory 215544 kb
Host smart-4e951a47-b637-48b9-8460-2a243e768b63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255810271 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.2255810271
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.558583929
Short name T334
Test name
Test status
Simulation time 1638849046 ps
CPU time 10.64 seconds
Started Mar 26 01:47:55 PM PDT 24
Finished Mar 26 01:48:06 PM PDT 24
Peak memory 213216 kb
Host smart-62bc878c-c9f2-48e6-8529-e1087de1d546
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558583929 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.558583929
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.3249305098
Short name T69
Test name
Test status
Simulation time 4787696168 ps
CPU time 4.12 seconds
Started Mar 26 01:48:02 PM PDT 24
Finished Mar 26 01:48:06 PM PDT 24
Peak memory 218404 kb
Host smart-7142d29a-04a2-4f3b-a6e2-1f04b07ddd91
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249305098 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.3249305098
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.2460119658
Short name T370
Test name
Test status
Simulation time 30372640 ps
CPU time 1.52 seconds
Started Mar 26 01:48:01 PM PDT 24
Finished Mar 26 01:48:03 PM PDT 24
Peak memory 213128 kb
Host smart-15cfa746-c2db-4236-8377-d4532e88d1ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460119658 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.2460119658
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.644763286
Short name T250
Test name
Test status
Simulation time 208009326 ps
CPU time 0.96 seconds
Started Mar 26 01:48:02 PM PDT 24
Finished Mar 26 01:48:03 PM PDT 24
Peak memory 204856 kb
Host smart-cb45a815-6f0b-42d8-8f4a-65986c8379d7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644763286 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.644763286
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1195694682
Short name T341
Test name
Test status
Simulation time 101105749 ps
CPU time 0.7 seconds
Started Mar 26 01:47:59 PM PDT 24
Finished Mar 26 01:48:00 PM PDT 24
Peak memory 204584 kb
Host smart-2c4a3742-69ef-4300-9b70-5aada496d8e1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195694682 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
1195694682
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.2539404213
Short name T77
Test name
Test status
Simulation time 986441957 ps
CPU time 4.46 seconds
Started Mar 26 01:48:09 PM PDT 24
Finished Mar 26 01:48:13 PM PDT 24
Peak memory 205032 kb
Host smart-c3fb351f-c9b9-4f2f-964b-cea3dce1225f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539404213 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.2539404213
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.3690771178
Short name T312
Test name
Test status
Simulation time 412069686 ps
CPU time 3.47 seconds
Started Mar 26 01:48:08 PM PDT 24
Finished Mar 26 01:48:12 PM PDT 24
Peak memory 213224 kb
Host smart-938064b0-ad61-427c-b089-0aa0235d5d3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690771178 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.3690771178
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2490697566
Short name T114
Test name
Test status
Simulation time 761854763 ps
CPU time 15.71 seconds
Started Mar 26 01:48:02 PM PDT 24
Finished Mar 26 01:48:18 PM PDT 24
Peak memory 213124 kb
Host smart-5ad6076a-9d72-4980-abea-4ec50ff3815f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490697566 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.2
490697566
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.2882621000
Short name T357
Test name
Test status
Simulation time 710444354 ps
CPU time 4.67 seconds
Started Mar 26 01:48:10 PM PDT 24
Finished Mar 26 01:48:15 PM PDT 24
Peak memory 219780 kb
Host smart-c77acbeb-1598-4c1d-a26a-aa4161d9da4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882621000 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.2882621000
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.225201370
Short name T79
Test name
Test status
Simulation time 38229293 ps
CPU time 2.21 seconds
Started Mar 26 01:48:04 PM PDT 24
Finished Mar 26 01:48:06 PM PDT 24
Peak memory 213104 kb
Host smart-3bce8fab-e0a1-4cb6-9d37-b193c4abaea0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225201370 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.225201370
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.688080155
Short name T333
Test name
Test status
Simulation time 138023137 ps
CPU time 1.22 seconds
Started Mar 26 01:48:09 PM PDT 24
Finished Mar 26 01:48:10 PM PDT 24
Peak memory 204876 kb
Host smart-fadcc7be-ed30-4c64-a910-90210810544a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688080155 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.688080155
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1070112580
Short name T336
Test name
Test status
Simulation time 51313477 ps
CPU time 0.84 seconds
Started Mar 26 01:48:00 PM PDT 24
Finished Mar 26 01:48:01 PM PDT 24
Peak memory 204656 kb
Host smart-82566035-e092-4bf3-903b-f90a1763f7ea
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070112580 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
1070112580
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.3620566065
Short name T75
Test name
Test status
Simulation time 159023525 ps
CPU time 3.73 seconds
Started Mar 26 01:48:08 PM PDT 24
Finished Mar 26 01:48:13 PM PDT 24
Peak memory 204952 kb
Host smart-51744dfd-2ae5-4643-aa64-481c060947ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620566065 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.3620566065
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tap_fsm_rand_reset.2746645188
Short name T329
Test name
Test status
Simulation time 16836027324 ps
CPU time 32.01 seconds
Started Mar 26 01:48:04 PM PDT 24
Finished Mar 26 01:48:36 PM PDT 24
Peak memory 220964 kb
Host smart-4ff9ce3c-f766-44f5-93a4-f360f479a889
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746645188 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rv_dm_tap_fsm_rand_reset.2746645188
Directory /workspace/13.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2422068172
Short name T66
Test name
Test status
Simulation time 120495897 ps
CPU time 2.19 seconds
Started Mar 26 01:48:08 PM PDT 24
Finished Mar 26 01:48:11 PM PDT 24
Peak memory 213172 kb
Host smart-153b4d07-fcdd-4200-8cb8-570ae7f0405f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422068172 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.2422068172
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3296958891
Short name T275
Test name
Test status
Simulation time 273624530 ps
CPU time 2.29 seconds
Started Mar 26 01:48:13 PM PDT 24
Finished Mar 26 01:48:15 PM PDT 24
Peak memory 216268 kb
Host smart-5535cb5d-10c5-4f1f-a189-2b266f6b1707
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296958891 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.3296958891
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.4127065022
Short name T344
Test name
Test status
Simulation time 199837378 ps
CPU time 2.38 seconds
Started Mar 26 01:48:10 PM PDT 24
Finished Mar 26 01:48:12 PM PDT 24
Peak memory 218700 kb
Host smart-5ffa7c23-119b-480b-92bc-3c6aa4132c0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127065022 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.4127065022
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.564246553
Short name T256
Test name
Test status
Simulation time 382834143 ps
CPU time 2.07 seconds
Started Mar 26 01:48:09 PM PDT 24
Finished Mar 26 01:48:12 PM PDT 24
Peak memory 204892 kb
Host smart-01e69bdf-69e9-4cd3-a349-75ca23c6133d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564246553 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.564246553
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2781094638
Short name T317
Test name
Test status
Simulation time 38519240 ps
CPU time 0.69 seconds
Started Mar 26 01:48:10 PM PDT 24
Finished Mar 26 01:48:11 PM PDT 24
Peak memory 204580 kb
Host smart-004cf3d0-f6ee-48a4-b392-cdbbd6b0dbb6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781094638 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
2781094638
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2198658647
Short name T315
Test name
Test status
Simulation time 1164040206 ps
CPU time 4.49 seconds
Started Mar 26 01:48:09 PM PDT 24
Finished Mar 26 01:48:14 PM PDT 24
Peak memory 204964 kb
Host smart-5abd2e5e-955c-4b88-acfd-0699fc9e8caa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198658647 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.2198658647
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.3933654928
Short name T281
Test name
Test status
Simulation time 48238013 ps
CPU time 3.53 seconds
Started Mar 26 01:48:11 PM PDT 24
Finished Mar 26 01:48:15 PM PDT 24
Peak memory 213128 kb
Host smart-304171ef-320f-4732-a65d-88db9aa39714
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933654928 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.3933654928
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.3424906654
Short name T294
Test name
Test status
Simulation time 74162771 ps
CPU time 4.29 seconds
Started Mar 26 01:48:19 PM PDT 24
Finished Mar 26 01:48:25 PM PDT 24
Peak memory 220308 kb
Host smart-6b060f61-a0bb-4051-81a7-a04727ddcef6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424906654 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.3424906654
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.1561589047
Short name T78
Test name
Test status
Simulation time 95466920 ps
CPU time 1.46 seconds
Started Mar 26 01:48:21 PM PDT 24
Finished Mar 26 01:48:23 PM PDT 24
Peak memory 221204 kb
Host smart-a1a89584-da16-424e-9915-6bd40367dbcf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561589047 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.1561589047
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.2245757481
Short name T283
Test name
Test status
Simulation time 338776102 ps
CPU time 1.22 seconds
Started Mar 26 01:48:09 PM PDT 24
Finished Mar 26 01:48:10 PM PDT 24
Peak memory 204832 kb
Host smart-797026b5-b19e-4dac-8236-c5134b1104ef
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245757481 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
2245757481
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3558941343
Short name T57
Test name
Test status
Simulation time 33747214 ps
CPU time 0.74 seconds
Started Mar 26 01:48:11 PM PDT 24
Finished Mar 26 01:48:12 PM PDT 24
Peak memory 204628 kb
Host smart-d3871ea0-c129-4e15-93fd-a24c5d9ddc49
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558941343 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
3558941343
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.2222934915
Short name T373
Test name
Test status
Simulation time 2139917556 ps
CPU time 7.55 seconds
Started Mar 26 01:48:20 PM PDT 24
Finished Mar 26 01:48:29 PM PDT 24
Peak memory 205028 kb
Host smart-76e842e4-0da1-4cff-83b5-6d2a42430010
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222934915 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.2222934915
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.1295068411
Short name T376
Test name
Test status
Simulation time 2478474694 ps
CPU time 4.75 seconds
Started Mar 26 01:48:10 PM PDT 24
Finished Mar 26 01:48:15 PM PDT 24
Peak memory 213144 kb
Host smart-d8b29bb1-46bd-41a6-b5db-a57aa983ca79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295068411 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.1295068411
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2175350329
Short name T132
Test name
Test status
Simulation time 1341903536 ps
CPU time 16.03 seconds
Started Mar 26 01:48:10 PM PDT 24
Finished Mar 26 01:48:26 PM PDT 24
Peak memory 221328 kb
Host smart-9e836565-8c61-443d-8027-b2241464c547
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175350329 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.2
175350329
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2147871492
Short name T309
Test name
Test status
Simulation time 4330120317 ps
CPU time 10.84 seconds
Started Mar 26 01:48:19 PM PDT 24
Finished Mar 26 01:48:31 PM PDT 24
Peak memory 220124 kb
Host smart-87010e40-618d-4564-91aa-55be1571961e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147871492 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.2147871492
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2336065251
Short name T102
Test name
Test status
Simulation time 94011019 ps
CPU time 1.64 seconds
Started Mar 26 01:48:19 PM PDT 24
Finished Mar 26 01:48:22 PM PDT 24
Peak memory 213112 kb
Host smart-6a8f2ac7-81a5-4e06-b9ed-6dbaf5bf664d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336065251 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.2336065251
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2049055519
Short name T306
Test name
Test status
Simulation time 828861124 ps
CPU time 2.23 seconds
Started Mar 26 01:48:18 PM PDT 24
Finished Mar 26 01:48:23 PM PDT 24
Peak memory 204876 kb
Host smart-43122f50-0c9c-4cb8-877b-dd26589456e0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049055519 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
2049055519
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.1746128941
Short name T368
Test name
Test status
Simulation time 74220270 ps
CPU time 0.85 seconds
Started Mar 26 01:48:19 PM PDT 24
Finished Mar 26 01:48:21 PM PDT 24
Peak memory 204684 kb
Host smart-f97cd989-9311-4d11-b7c9-f513e39b313a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746128941 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
1746128941
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.4091430428
Short name T97
Test name
Test status
Simulation time 555915601 ps
CPU time 6.7 seconds
Started Mar 26 01:48:17 PM PDT 24
Finished Mar 26 01:48:24 PM PDT 24
Peak memory 204972 kb
Host smart-566e25e9-ae76-4ea5-b6d2-d168c962cda8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091430428 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.4091430428
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.2565357380
Short name T299
Test name
Test status
Simulation time 95696213 ps
CPU time 2.9 seconds
Started Mar 26 01:48:19 PM PDT 24
Finished Mar 26 01:48:23 PM PDT 24
Peak memory 213144 kb
Host smart-b8e4ff0d-0302-48a9-be57-ea247c5ffa40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565357380 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.2565357380
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.1863123395
Short name T121
Test name
Test status
Simulation time 1401081188 ps
CPU time 16.16 seconds
Started Mar 26 01:48:24 PM PDT 24
Finished Mar 26 01:48:41 PM PDT 24
Peak memory 221364 kb
Host smart-463be169-606a-49c8-b6ce-d64d758298f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863123395 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.1
863123395
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.279409758
Short name T321
Test name
Test status
Simulation time 298033541 ps
CPU time 2.31 seconds
Started Mar 26 01:48:29 PM PDT 24
Finished Mar 26 01:48:33 PM PDT 24
Peak memory 215708 kb
Host smart-7a3714b2-1430-43af-99a9-51abc266a723
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279409758 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.279409758
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.47860279
Short name T330
Test name
Test status
Simulation time 71954035 ps
CPU time 1.51 seconds
Started Mar 26 01:48:17 PM PDT 24
Finished Mar 26 01:48:19 PM PDT 24
Peak memory 218140 kb
Host smart-90b8ac32-01ed-4474-8452-893daad11326
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47860279 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.47860279
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2926759867
Short name T248
Test name
Test status
Simulation time 350400312 ps
CPU time 1.86 seconds
Started Mar 26 01:48:19 PM PDT 24
Finished Mar 26 01:48:22 PM PDT 24
Peak memory 204872 kb
Host smart-85c37204-fa6a-4f79-bce6-69c1c608832f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926759867 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
2926759867
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.3457393666
Short name T277
Test name
Test status
Simulation time 91639354 ps
CPU time 0.71 seconds
Started Mar 26 01:48:19 PM PDT 24
Finished Mar 26 01:48:21 PM PDT 24
Peak memory 204604 kb
Host smart-66307876-7d4e-49db-891d-068426dc8590
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457393666 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
3457393666
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3721917250
Short name T108
Test name
Test status
Simulation time 1090197875 ps
CPU time 4.25 seconds
Started Mar 26 01:48:30 PM PDT 24
Finished Mar 26 01:48:35 PM PDT 24
Peak memory 204928 kb
Host smart-4bc004c5-1d3a-45ff-a0a3-71ddc387c8f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721917250 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.3721917250
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.1068206528
Short name T65
Test name
Test status
Simulation time 3112018090 ps
CPU time 6.42 seconds
Started Mar 26 01:48:18 PM PDT 24
Finished Mar 26 01:48:25 PM PDT 24
Peak memory 213216 kb
Host smart-b5a2795f-b1c6-459b-a92e-80eff919a162
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068206528 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.1068206528
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.838298950
Short name T310
Test name
Test status
Simulation time 232679350 ps
CPU time 8.38 seconds
Started Mar 26 01:48:23 PM PDT 24
Finished Mar 26 01:48:32 PM PDT 24
Peak memory 221236 kb
Host smart-6d5c66dc-3d0c-4ce4-9612-5cb5eaae31d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838298950 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.838298950
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2585814893
Short name T361
Test name
Test status
Simulation time 1456180641 ps
CPU time 5.8 seconds
Started Mar 26 01:48:35 PM PDT 24
Finished Mar 26 01:48:41 PM PDT 24
Peak memory 218480 kb
Host smart-bef828d3-85e2-4c1d-abc3-dec472558ffd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585814893 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.2585814893
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.4140747352
Short name T101
Test name
Test status
Simulation time 205584480 ps
CPU time 2.47 seconds
Started Mar 26 01:48:29 PM PDT 24
Finished Mar 26 01:48:33 PM PDT 24
Peak memory 213192 kb
Host smart-01ba8340-3e71-41f5-b247-89352130bd39
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140747352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.4140747352
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2894130920
Short name T375
Test name
Test status
Simulation time 612816109 ps
CPU time 2.63 seconds
Started Mar 26 01:48:27 PM PDT 24
Finished Mar 26 01:48:31 PM PDT 24
Peak memory 204820 kb
Host smart-2171c7e5-96b2-4061-9b42-14bf54e95e6f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894130920 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
2894130920
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2514224586
Short name T269
Test name
Test status
Simulation time 27780325 ps
CPU time 0.77 seconds
Started Mar 26 01:48:28 PM PDT 24
Finished Mar 26 01:48:30 PM PDT 24
Peak memory 204568 kb
Host smart-5a560c41-51b8-43ff-ad00-5b167e673ea9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514224586 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
2514224586
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1978203054
Short name T92
Test name
Test status
Simulation time 1327202494 ps
CPU time 8.31 seconds
Started Mar 26 01:48:29 PM PDT 24
Finished Mar 26 01:48:39 PM PDT 24
Peak memory 204964 kb
Host smart-af0fb93e-2caf-4e7e-9447-472cb419c992
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978203054 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.1978203054
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tap_fsm_rand_reset.2321448878
Short name T350
Test name
Test status
Simulation time 11195906036 ps
CPU time 36.18 seconds
Started Mar 26 01:48:29 PM PDT 24
Finished Mar 26 01:49:05 PM PDT 24
Peak memory 220792 kb
Host smart-35743ae2-86fd-4b8a-90db-ce4e9e208ce2
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321448878 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rv_dm_tap_fsm_rand_reset.2321448878
Directory /workspace/18.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.3401054970
Short name T111
Test name
Test status
Simulation time 627002950 ps
CPU time 3.09 seconds
Started Mar 26 01:48:29 PM PDT 24
Finished Mar 26 01:48:34 PM PDT 24
Peak memory 213140 kb
Host smart-65cce7ac-fd68-45d9-818b-cdfb67bdafa7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401054970 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.3401054970
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.142472389
Short name T133
Test name
Test status
Simulation time 506249296 ps
CPU time 9.83 seconds
Started Mar 26 01:48:28 PM PDT 24
Finished Mar 26 01:48:39 PM PDT 24
Peak memory 221228 kb
Host smart-7735bf6b-48b4-4ebf-8681-31060cf1d8d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142472389 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.142472389
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2500749639
Short name T301
Test name
Test status
Simulation time 1709806824 ps
CPU time 6.17 seconds
Started Mar 26 01:48:35 PM PDT 24
Finished Mar 26 01:48:41 PM PDT 24
Peak memory 218676 kb
Host smart-da4e9b39-e77f-466f-aafd-60f62dcb78ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500749639 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.2500749639
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.1221041160
Short name T99
Test name
Test status
Simulation time 103393020 ps
CPU time 2.4 seconds
Started Mar 26 01:48:35 PM PDT 24
Finished Mar 26 01:48:38 PM PDT 24
Peak memory 213144 kb
Host smart-247c394e-6b93-409e-a6ee-ddcd98b58a62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221041160 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.1221041160
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.1250675793
Short name T325
Test name
Test status
Simulation time 343018660 ps
CPU time 1.9 seconds
Started Mar 26 01:48:37 PM PDT 24
Finished Mar 26 01:48:39 PM PDT 24
Peak memory 204872 kb
Host smart-be8e1fc4-20db-4718-84db-76e04b343767
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250675793 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
1250675793
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.1892211932
Short name T56
Test name
Test status
Simulation time 31441615 ps
CPU time 0.71 seconds
Started Mar 26 01:48:36 PM PDT 24
Finished Mar 26 01:48:37 PM PDT 24
Peak memory 204600 kb
Host smart-81ecddaf-fdc4-408c-a8e4-4858217a59cf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892211932 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
1892211932
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.3168885017
Short name T355
Test name
Test status
Simulation time 205887618 ps
CPU time 4.24 seconds
Started Mar 26 01:48:38 PM PDT 24
Finished Mar 26 01:48:42 PM PDT 24
Peak memory 204984 kb
Host smart-2eb79a79-4b76-4362-b892-c68cb6da4b9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168885017 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.3168885017
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3178564176
Short name T366
Test name
Test status
Simulation time 127183148 ps
CPU time 5.79 seconds
Started Mar 26 01:48:35 PM PDT 24
Finished Mar 26 01:48:41 PM PDT 24
Peak memory 213332 kb
Host smart-ca15e715-59fc-4acb-a281-bfe114c6c379
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178564176 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.3178564176
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1403024343
Short name T100
Test name
Test status
Simulation time 1848039318 ps
CPU time 32.15 seconds
Started Mar 26 01:45:55 PM PDT 24
Finished Mar 26 01:46:27 PM PDT 24
Peak memory 213168 kb
Host smart-dcaafb30-9836-4d67-aaa3-2cd483cc2305
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403024343 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.1403024343
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.3720582279
Short name T360
Test name
Test status
Simulation time 24568284088 ps
CPU time 37.14 seconds
Started Mar 26 01:46:21 PM PDT 24
Finished Mar 26 01:46:59 PM PDT 24
Peak memory 205072 kb
Host smart-1f5fed9d-c3f2-421e-9c9c-b4fadb899055
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720582279 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.3720582279
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.2632949756
Short name T30
Test name
Test status
Simulation time 183643654 ps
CPU time 2.43 seconds
Started Mar 26 01:46:11 PM PDT 24
Finished Mar 26 01:46:14 PM PDT 24
Peak memory 213116 kb
Host smart-ea11b4c6-1969-4dbd-9b69-57f103570fb4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632949756 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.2632949756
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.2784320336
Short name T279
Test name
Test status
Simulation time 178502406 ps
CPU time 2.27 seconds
Started Mar 26 01:46:22 PM PDT 24
Finished Mar 26 01:46:24 PM PDT 24
Peak memory 221240 kb
Host smart-6617cba2-e216-4657-acd2-d4e256f90157
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784320336 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.2784320336
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.776834754
Short name T322
Test name
Test status
Simulation time 323964679 ps
CPU time 2.43 seconds
Started Mar 26 01:46:21 PM PDT 24
Finished Mar 26 01:46:24 PM PDT 24
Peak memory 221252 kb
Host smart-8470bd40-8261-4947-a248-ea6ae024acf8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776834754 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.776834754
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2653206448
Short name T251
Test name
Test status
Simulation time 16960240886 ps
CPU time 21.29 seconds
Started Mar 26 01:46:04 PM PDT 24
Finished Mar 26 01:46:25 PM PDT 24
Peak memory 204744 kb
Host smart-57483fba-c44e-4672-8684-792505818d40
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653206448 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.2653206448
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.3740713815
Short name T254
Test name
Test status
Simulation time 20627531953 ps
CPU time 54.3 seconds
Started Mar 26 01:46:04 PM PDT 24
Finished Mar 26 01:46:58 PM PDT 24
Peak memory 204904 kb
Host smart-7e4ff160-279e-428e-8253-3adf5dff2046
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740713815 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_bit_bash.3740713815
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.3588901751
Short name T326
Test name
Test status
Simulation time 621344829 ps
CPU time 2.05 seconds
Started Mar 26 01:46:05 PM PDT 24
Finished Mar 26 01:46:08 PM PDT 24
Peak memory 204928 kb
Host smart-772f80d7-aa1a-4887-ae82-4045167b57a4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588901751 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.3588901751
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.148607582
Short name T328
Test name
Test status
Simulation time 423509026 ps
CPU time 1.99 seconds
Started Mar 26 01:46:03 PM PDT 24
Finished Mar 26 01:46:05 PM PDT 24
Peak memory 204716 kb
Host smart-2ce3de2b-6b1b-4f20-8723-55bf824c5494
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148607582 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.148607582
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.1826570762
Short name T359
Test name
Test status
Simulation time 103082960 ps
CPU time 0.81 seconds
Started Mar 26 01:46:05 PM PDT 24
Finished Mar 26 01:46:06 PM PDT 24
Peak memory 204568 kb
Host smart-7a0473c4-edd8-4890-b707-181c1954eb3e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826570762 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_aliasing.1826570762
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1905863588
Short name T268
Test name
Test status
Simulation time 2078364770 ps
CPU time 8.13 seconds
Started Mar 26 01:45:54 PM PDT 24
Finished Mar 26 01:46:03 PM PDT 24
Peak memory 204872 kb
Host smart-f37c610e-0b32-40cc-a7f1-a3eb77af23f0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905863588 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.1905863588
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3265308729
Short name T323
Test name
Test status
Simulation time 121150493 ps
CPU time 0.75 seconds
Started Mar 26 01:45:57 PM PDT 24
Finished Mar 26 01:45:58 PM PDT 24
Peak memory 204736 kb
Host smart-c1f300e3-b44c-4159-85cb-ddccd1679ed8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265308729 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.3265308729
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2516198120
Short name T297
Test name
Test status
Simulation time 28724321 ps
CPU time 0.72 seconds
Started Mar 26 01:45:55 PM PDT 24
Finished Mar 26 01:45:56 PM PDT 24
Peak memory 204648 kb
Host smart-9c57c738-0d98-48b3-9aa6-9637a9a489ba
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516198120 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.2
516198120
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.733367500
Short name T290
Test name
Test status
Simulation time 64136535 ps
CPU time 0.65 seconds
Started Mar 26 01:46:12 PM PDT 24
Finished Mar 26 01:46:13 PM PDT 24
Peak memory 204620 kb
Host smart-58d34275-706e-46f3-83ef-08632b1f9c76
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733367500 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_part
ial_access.733367500
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.1361990732
Short name T307
Test name
Test status
Simulation time 52192099 ps
CPU time 0.65 seconds
Started Mar 26 01:46:12 PM PDT 24
Finished Mar 26 01:46:12 PM PDT 24
Peak memory 204588 kb
Host smart-fd29e22f-4553-4998-80ad-f427682e7015
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361990732 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.1361990732
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3473916273
Short name T372
Test name
Test status
Simulation time 229903705 ps
CPU time 3.64 seconds
Started Mar 26 01:46:23 PM PDT 24
Finished Mar 26 01:46:27 PM PDT 24
Peak memory 204984 kb
Host smart-96dd6ea0-b73f-41d6-b84e-1a42d55504b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473916273 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.3473916273
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.291395275
Short name T26
Test name
Test status
Simulation time 9407482537 ps
CPU time 16.63 seconds
Started Mar 26 01:46:03 PM PDT 24
Finished Mar 26 01:46:20 PM PDT 24
Peak memory 218596 kb
Host smart-2f372fda-6b26-448f-bf6c-1c50aa369299
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291395275 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.291395275
Directory /workspace/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.924645601
Short name T272
Test name
Test status
Simulation time 787947178 ps
CPU time 2.98 seconds
Started Mar 26 01:46:13 PM PDT 24
Finished Mar 26 01:46:16 PM PDT 24
Peak memory 213248 kb
Host smart-d8adb14f-c220-4253-b0f6-e49e9f05efaa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924645601 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.924645601
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.1056531484
Short name T123
Test name
Test status
Simulation time 2174639083 ps
CPU time 19.62 seconds
Started Mar 26 01:46:14 PM PDT 24
Finished Mar 26 01:46:34 PM PDT 24
Peak memory 213244 kb
Host smart-06f37744-119a-46a4-bc70-2fe5a0a66b41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056531484 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.1056531484
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/21.rv_dm_tap_fsm_rand_reset.3051003013
Short name T282
Test name
Test status
Simulation time 15037573355 ps
CPU time 15.24 seconds
Started Mar 26 01:48:36 PM PDT 24
Finished Mar 26 01:48:51 PM PDT 24
Peak memory 215064 kb
Host smart-4a5f90d0-5a6f-45e5-9c13-3fc6ac449da4
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051003013 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 21.rv_dm_tap_fsm_rand_reset.3051003013
Directory /workspace/21.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/26.rv_dm_tap_fsm_rand_reset.1273971746
Short name T135
Test name
Test status
Simulation time 23297478534 ps
CPU time 23.32 seconds
Started Mar 26 01:48:47 PM PDT 24
Finished Mar 26 01:49:10 PM PDT 24
Peak memory 221476 kb
Host smart-e8159a88-4cd9-4474-a882-7cb3a086b25f
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273971746 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 26.rv_dm_tap_fsm_rand_reset.1273971746
Directory /workspace/26.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/27.rv_dm_tap_fsm_rand_reset.1717265453
Short name T338
Test name
Test status
Simulation time 14090199399 ps
CPU time 13.28 seconds
Started Mar 26 01:48:45 PM PDT 24
Finished Mar 26 01:48:58 PM PDT 24
Peak memory 215860 kb
Host smart-d107b89c-8084-4c4f-8b42-fcd1e3e9575e
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717265453 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 27.rv_dm_tap_fsm_rand_reset.1717265453
Directory /workspace/27.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/29.rv_dm_tap_fsm_rand_reset.269227413
Short name T342
Test name
Test status
Simulation time 7020750598 ps
CPU time 19.67 seconds
Started Mar 26 01:48:46 PM PDT 24
Finished Mar 26 01:49:06 PM PDT 24
Peak memory 214136 kb
Host smart-e6108ca8-583e-424c-a4e1-e24824d09047
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269227413 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 29.rv_dm_tap_fsm_rand_reset.269227413
Directory /workspace/29.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1335401552
Short name T345
Test name
Test status
Simulation time 3806196718 ps
CPU time 28.44 seconds
Started Mar 26 01:46:21 PM PDT 24
Finished Mar 26 01:46:50 PM PDT 24
Peak memory 205024 kb
Host smart-46af8642-60b0-4167-b87b-bbba52ff52b9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335401552 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.1335401552
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.3386787634
Short name T76
Test name
Test status
Simulation time 11348121866 ps
CPU time 68.2 seconds
Started Mar 26 01:46:44 PM PDT 24
Finished Mar 26 01:47:53 PM PDT 24
Peak memory 213308 kb
Host smart-93230d04-2252-4efa-b5b0-98070280c90b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386787634 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.3386787634
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1174801354
Short name T90
Test name
Test status
Simulation time 78582882 ps
CPU time 1.6 seconds
Started Mar 26 01:46:44 PM PDT 24
Finished Mar 26 01:46:47 PM PDT 24
Peak memory 213076 kb
Host smart-b383ab90-406c-49a1-8482-c7d96aacb2ae
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174801354 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.1174801354
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1481180535
Short name T265
Test name
Test status
Simulation time 150832709 ps
CPU time 3.55 seconds
Started Mar 26 01:46:44 PM PDT 24
Finished Mar 26 01:46:48 PM PDT 24
Peak memory 218544 kb
Host smart-535667b4-b317-4be4-8596-36e7072179e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481180535 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.1481180535
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2591326946
Short name T106
Test name
Test status
Simulation time 308634435 ps
CPU time 2.29 seconds
Started Mar 26 01:46:43 PM PDT 24
Finished Mar 26 01:46:45 PM PDT 24
Peak memory 218524 kb
Host smart-0334c5c9-b553-475e-87c9-885ffdd88a5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591326946 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.2591326946
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.2450675896
Short name T257
Test name
Test status
Simulation time 3060219765 ps
CPU time 7.22 seconds
Started Mar 26 01:46:43 PM PDT 24
Finished Mar 26 01:46:50 PM PDT 24
Peak memory 204884 kb
Host smart-19b8e560-c88a-4154-b978-ad375566ad94
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450675896 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.2450675896
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1858365554
Short name T349
Test name
Test status
Simulation time 12380085548 ps
CPU time 21.67 seconds
Started Mar 26 01:46:43 PM PDT 24
Finished Mar 26 01:47:05 PM PDT 24
Peak memory 204904 kb
Host smart-ed209c49-76ce-4475-868e-b2d1007b1bf7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858365554 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_bit_bash.1858365554
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2216154107
Short name T88
Test name
Test status
Simulation time 191696795 ps
CPU time 1.19 seconds
Started Mar 26 01:46:43 PM PDT 24
Finished Mar 26 01:46:44 PM PDT 24
Peak memory 204992 kb
Host smart-c835d323-c60f-48b6-860f-9f188c525c97
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216154107 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.2216154107
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1778931016
Short name T263
Test name
Test status
Simulation time 153405431 ps
CPU time 1.15 seconds
Started Mar 26 01:46:43 PM PDT 24
Finished Mar 26 01:46:44 PM PDT 24
Peak memory 204816 kb
Host smart-56fe58c4-0f21-4c5a-b02f-5736ac9bb015
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778931016 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.1
778931016
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1491908884
Short name T379
Test name
Test status
Simulation time 355802225 ps
CPU time 1.35 seconds
Started Mar 26 01:46:34 PM PDT 24
Finished Mar 26 01:46:36 PM PDT 24
Peak memory 204660 kb
Host smart-e0c3c2ea-988f-4520-b14a-c77e96ab2b6e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491908884 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.1491908884
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.3162813885
Short name T287
Test name
Test status
Simulation time 2929844751 ps
CPU time 10.37 seconds
Started Mar 26 01:46:35 PM PDT 24
Finished Mar 26 01:46:46 PM PDT 24
Peak memory 204888 kb
Host smart-348238ea-eaf9-4d5a-8085-44bff116ef3f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162813885 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.3162813885
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1570896915
Short name T311
Test name
Test status
Simulation time 59190412 ps
CPU time 0.82 seconds
Started Mar 26 01:46:22 PM PDT 24
Finished Mar 26 01:46:23 PM PDT 24
Peak memory 204612 kb
Host smart-24df8e49-c94c-4691-ae48-9aba4376f82e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570896915 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.1570896915
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.140563575
Short name T280
Test name
Test status
Simulation time 61139375 ps
CPU time 0.68 seconds
Started Mar 26 01:46:34 PM PDT 24
Finished Mar 26 01:46:35 PM PDT 24
Peak memory 204648 kb
Host smart-dd3508e6-52ab-4077-8eb6-9eeabb765308
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140563575 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.140563575
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.3475403895
Short name T261
Test name
Test status
Simulation time 54195503 ps
CPU time 0.69 seconds
Started Mar 26 01:46:43 PM PDT 24
Finished Mar 26 01:46:44 PM PDT 24
Peak memory 204620 kb
Host smart-71cbd79f-47b6-4e3e-b017-25e0d165cdb9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475403895 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.3475403895
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1117843557
Short name T356
Test name
Test status
Simulation time 35878240 ps
CPU time 0.68 seconds
Started Mar 26 01:46:43 PM PDT 24
Finished Mar 26 01:46:44 PM PDT 24
Peak memory 204648 kb
Host smart-c9428927-6b6e-4e4c-83dd-78fd1d7e9e46
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117843557 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.1117843557
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.3318911636
Short name T107
Test name
Test status
Simulation time 148353258 ps
CPU time 6.61 seconds
Started Mar 26 01:46:43 PM PDT 24
Finished Mar 26 01:46:51 PM PDT 24
Peak memory 204944 kb
Host smart-2851701c-de2c-4ccc-b8cf-8590b9f92eba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318911636 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.3318911636
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.3466585287
Short name T314
Test name
Test status
Simulation time 14593806503 ps
CPU time 29.38 seconds
Started Mar 26 01:46:43 PM PDT 24
Finished Mar 26 01:47:13 PM PDT 24
Peak memory 229444 kb
Host smart-6a4531a5-edca-41ef-8f18-e9fb9d535cfc
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466585287 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.3466585287
Directory /workspace/3.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.3360570242
Short name T358
Test name
Test status
Simulation time 205463262 ps
CPU time 4.21 seconds
Started Mar 26 01:46:43 PM PDT 24
Finished Mar 26 01:46:47 PM PDT 24
Peak memory 213156 kb
Host smart-24dd476a-0dd6-4d8b-9efa-cfd22e6d676f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360570242 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.3360570242
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.1392907457
Short name T127
Test name
Test status
Simulation time 1273617691 ps
CPU time 22.97 seconds
Started Mar 26 01:46:44 PM PDT 24
Finished Mar 26 01:47:08 PM PDT 24
Peak memory 213356 kb
Host smart-2fd49095-de7f-43e2-b196-5e164e8b9ef1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392907457 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.1392907457
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/38.rv_dm_tap_fsm_rand_reset.3576790898
Short name T380
Test name
Test status
Simulation time 7092912160 ps
CPU time 13.56 seconds
Started Mar 26 01:48:55 PM PDT 24
Finished Mar 26 01:49:09 PM PDT 24
Peak memory 213312 kb
Host smart-c1892634-4a5a-43f0-81cf-dcdaea34e5af
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576790898 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 38.rv_dm_tap_fsm_rand_reset.3576790898
Directory /workspace/38.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1484727172
Short name T94
Test name
Test status
Simulation time 8317541672 ps
CPU time 77.23 seconds
Started Mar 26 01:46:44 PM PDT 24
Finished Mar 26 01:48:02 PM PDT 24
Peak memory 217600 kb
Host smart-2b978cbe-ccf0-4b35-96be-f86cfdd90a96
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484727172 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.1484727172
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.3466795891
Short name T103
Test name
Test status
Simulation time 4896994831 ps
CPU time 68.7 seconds
Started Mar 26 01:47:13 PM PDT 24
Finished Mar 26 01:48:21 PM PDT 24
Peak memory 205048 kb
Host smart-a545dd73-768a-4e65-8435-dba38d923b70
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466795891 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.3466795891
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.1861877776
Short name T295
Test name
Test status
Simulation time 309238708 ps
CPU time 1.64 seconds
Started Mar 26 01:47:23 PM PDT 24
Finished Mar 26 01:47:24 PM PDT 24
Peak memory 213200 kb
Host smart-c3bfa776-31a8-4e5e-8c2e-f26b936b910c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861877776 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.1861877776
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2157641989
Short name T313
Test name
Test status
Simulation time 836431812 ps
CPU time 2.72 seconds
Started Mar 26 01:47:22 PM PDT 24
Finished Mar 26 01:47:25 PM PDT 24
Peak memory 217120 kb
Host smart-66b5e546-097f-4763-a08a-7f7368e571af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157641989 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.2157641989
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.698389713
Short name T320
Test name
Test status
Simulation time 86003857 ps
CPU time 2.47 seconds
Started Mar 26 01:47:11 PM PDT 24
Finished Mar 26 01:47:14 PM PDT 24
Peak memory 213112 kb
Host smart-8c7102a6-68c8-400c-b8fb-ceb6dda8d243
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698389713 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.698389713
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.4214778763
Short name T260
Test name
Test status
Simulation time 3835353064 ps
CPU time 7.05 seconds
Started Mar 26 01:47:04 PM PDT 24
Finished Mar 26 01:47:12 PM PDT 24
Peak memory 204820 kb
Host smart-e8120d1c-fc3a-48b8-a357-b88a953ee80a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214778763 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.4214778763
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3852051347
Short name T308
Test name
Test status
Simulation time 22874649564 ps
CPU time 41.78 seconds
Started Mar 26 01:46:49 PM PDT 24
Finished Mar 26 01:47:32 PM PDT 24
Peak memory 204912 kb
Host smart-505f5189-bdc2-4f74-834c-d2c918524960
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852051347 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_bit_bash.3852051347
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.122624084
Short name T86
Test name
Test status
Simulation time 654112825 ps
CPU time 2.74 seconds
Started Mar 26 01:46:51 PM PDT 24
Finished Mar 26 01:46:54 PM PDT 24
Peak memory 204936 kb
Host smart-727e2e07-4472-419c-b888-83cc66d092d0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122624084 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr
_hw_reset.122624084
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3932534364
Short name T304
Test name
Test status
Simulation time 936484906 ps
CPU time 1.95 seconds
Started Mar 26 01:46:54 PM PDT 24
Finished Mar 26 01:46:56 PM PDT 24
Peak memory 204840 kb
Host smart-a9e9d81a-faaa-4602-b408-c7361ecd8443
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932534364 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.3
932534364
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.2765657760
Short name T347
Test name
Test status
Simulation time 288413621 ps
CPU time 1.43 seconds
Started Mar 26 01:46:51 PM PDT 24
Finished Mar 26 01:46:53 PM PDT 24
Peak memory 204672 kb
Host smart-b01ad6f1-badf-4345-bd0d-d3e168036a55
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765657760 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.2765657760
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.3100104412
Short name T302
Test name
Test status
Simulation time 3983079492 ps
CPU time 13.12 seconds
Started Mar 26 01:47:03 PM PDT 24
Finished Mar 26 01:47:16 PM PDT 24
Peak memory 204744 kb
Host smart-c808fd25-c139-4209-99c7-d49a3ad64ef0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100104412 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.3100104412
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.410073506
Short name T262
Test name
Test status
Simulation time 119977375 ps
CPU time 1.02 seconds
Started Mar 26 01:47:02 PM PDT 24
Finished Mar 26 01:47:03 PM PDT 24
Peak memory 204612 kb
Host smart-307846fe-ddfa-4cd3-9ab1-12284892d5c3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410073506 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr
_hw_reset.410073506
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.1619500449
Short name T337
Test name
Test status
Simulation time 49123555 ps
CPU time 0.73 seconds
Started Mar 26 01:46:58 PM PDT 24
Finished Mar 26 01:46:59 PM PDT 24
Peak memory 204552 kb
Host smart-b0129395-f001-435e-8326-ec18071b0dcc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619500449 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.1
619500449
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.4119208988
Short name T353
Test name
Test status
Simulation time 56761811 ps
CPU time 0.67 seconds
Started Mar 26 01:47:13 PM PDT 24
Finished Mar 26 01:47:14 PM PDT 24
Peak memory 204652 kb
Host smart-3f389dc3-ec1c-4f4d-bb3b-d4f7bca735b9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119208988 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.4119208988
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.2854318240
Short name T271
Test name
Test status
Simulation time 45804931 ps
CPU time 0.67 seconds
Started Mar 26 01:47:05 PM PDT 24
Finished Mar 26 01:47:05 PM PDT 24
Peak memory 204628 kb
Host smart-8e025ba0-b500-4fed-b3c1-5ccaff2a303c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854318240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.2854318240
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1034236493
Short name T371
Test name
Test status
Simulation time 5072765903 ps
CPU time 5.65 seconds
Started Mar 26 01:47:14 PM PDT 24
Finished Mar 26 01:47:19 PM PDT 24
Peak memory 205044 kb
Host smart-da40cb26-dd92-4754-9558-855b52257b06
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034236493 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.1034236493
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.4212280205
Short name T25
Test name
Test status
Simulation time 6564587281 ps
CPU time 22.46 seconds
Started Mar 26 01:47:05 PM PDT 24
Finished Mar 26 01:47:28 PM PDT 24
Peak memory 214200 kb
Host smart-7cc82bd2-2f1f-4545-b59f-3a4fcbf78426
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212280205 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.4212280205
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.3335118138
Short name T363
Test name
Test status
Simulation time 122222136 ps
CPU time 5.37 seconds
Started Mar 26 01:47:06 PM PDT 24
Finished Mar 26 01:47:12 PM PDT 24
Peak memory 213124 kb
Host smart-bd01e10c-b2c3-4cfb-a25f-48f0bf7e799b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335118138 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.3335118138
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.1194371180
Short name T24
Test name
Test status
Simulation time 118171152 ps
CPU time 2.21 seconds
Started Mar 26 01:47:21 PM PDT 24
Finished Mar 26 01:47:23 PM PDT 24
Peak memory 217148 kb
Host smart-35171d77-cbb1-4828-8d25-ff730797d2f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194371180 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.1194371180
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.4112511896
Short name T286
Test name
Test status
Simulation time 85157882 ps
CPU time 1.4 seconds
Started Mar 26 01:47:22 PM PDT 24
Finished Mar 26 01:47:24 PM PDT 24
Peak memory 213156 kb
Host smart-60d5c9f8-39ec-492c-b692-938bced4d675
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112511896 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.4112511896
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3920804371
Short name T364
Test name
Test status
Simulation time 285865707 ps
CPU time 1.2 seconds
Started Mar 26 01:47:23 PM PDT 24
Finished Mar 26 01:47:24 PM PDT 24
Peak memory 204800 kb
Host smart-aa7b17f2-63b3-4b8d-99c9-214d9bad86e5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920804371 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.3
920804371
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3562183381
Short name T58
Test name
Test status
Simulation time 51169909 ps
CPU time 0.71 seconds
Started Mar 26 01:47:12 PM PDT 24
Finished Mar 26 01:47:13 PM PDT 24
Peak memory 204652 kb
Host smart-16b57c09-401a-4e6d-80fd-5f00947c75a1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562183381 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.3
562183381
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1074178763
Short name T332
Test name
Test status
Simulation time 283533298 ps
CPU time 4.29 seconds
Started Mar 26 01:47:24 PM PDT 24
Finished Mar 26 01:47:29 PM PDT 24
Peak memory 204912 kb
Host smart-40d17418-b444-4583-83da-7953dd681da7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074178763 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.1074178763
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.1303350447
Short name T119
Test name
Test status
Simulation time 852180928 ps
CPU time 5.05 seconds
Started Mar 26 01:47:17 PM PDT 24
Finished Mar 26 01:47:22 PM PDT 24
Peak memory 213168 kb
Host smart-b0080fcd-3f2e-4ca0-b515-29111c8787e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303350447 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.1303350447
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2759373696
Short name T113
Test name
Test status
Simulation time 1898936645 ps
CPU time 10.06 seconds
Started Mar 26 01:47:13 PM PDT 24
Finished Mar 26 01:47:23 PM PDT 24
Peak memory 213260 kb
Host smart-54dece70-18b3-4e28-86c2-8ea19ac37aa0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759373696 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.2759373696
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2792873173
Short name T292
Test name
Test status
Simulation time 189373348 ps
CPU time 3.54 seconds
Started Mar 26 01:47:32 PM PDT 24
Finished Mar 26 01:47:36 PM PDT 24
Peak memory 218488 kb
Host smart-dc8751f3-c6ee-4ca1-8792-92ebdb1f30c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792873173 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.2792873173
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.4235689507
Short name T327
Test name
Test status
Simulation time 1001226427 ps
CPU time 2.69 seconds
Started Mar 26 01:47:29 PM PDT 24
Finished Mar 26 01:47:32 PM PDT 24
Peak memory 213112 kb
Host smart-f4bdaed8-1849-43fb-83a7-58a7340772f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235689507 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.4235689507
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.3223050919
Short name T252
Test name
Test status
Simulation time 414149561 ps
CPU time 1.3 seconds
Started Mar 26 01:47:20 PM PDT 24
Finished Mar 26 01:47:22 PM PDT 24
Peak memory 204840 kb
Host smart-717a9cde-40b4-4670-aa24-7651827117a1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223050919 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.3
223050919
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.3037889390
Short name T273
Test name
Test status
Simulation time 23317000 ps
CPU time 0.71 seconds
Started Mar 26 01:47:21 PM PDT 24
Finished Mar 26 01:47:21 PM PDT 24
Peak memory 204644 kb
Host smart-a68f735e-aef8-4339-8dd4-e922ab95e39d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037889390 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.3
037889390
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.219555939
Short name T29
Test name
Test status
Simulation time 549751445 ps
CPU time 8.14 seconds
Started Mar 26 01:47:27 PM PDT 24
Finished Mar 26 01:47:36 PM PDT 24
Peak memory 204960 kb
Host smart-17999d51-db0c-4aca-ab46-00844858c10d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219555939 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_c
sr_outstanding.219555939
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.576072701
Short name T352
Test name
Test status
Simulation time 225732490 ps
CPU time 3.96 seconds
Started Mar 26 01:47:19 PM PDT 24
Finished Mar 26 01:47:23 PM PDT 24
Peak memory 213152 kb
Host smart-0589b024-b1f1-41bd-816c-3ecad1c4796b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576072701 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.576072701
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.1360736102
Short name T285
Test name
Test status
Simulation time 570978980 ps
CPU time 3.71 seconds
Started Mar 26 01:47:30 PM PDT 24
Finished Mar 26 01:47:33 PM PDT 24
Peak memory 217912 kb
Host smart-e77a74dd-6d64-45b0-96bd-861d786e411d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360736102 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.1360736102
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.1753362176
Short name T354
Test name
Test status
Simulation time 96994419 ps
CPU time 1.57 seconds
Started Mar 26 01:47:29 PM PDT 24
Finished Mar 26 01:47:31 PM PDT 24
Peak memory 213152 kb
Host smart-e47cf512-b86d-4cff-b6a9-a4ef13e21e55
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753362176 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.1753362176
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.1949734142
Short name T255
Test name
Test status
Simulation time 351519527 ps
CPU time 1.81 seconds
Started Mar 26 01:47:27 PM PDT 24
Finished Mar 26 01:47:29 PM PDT 24
Peak memory 204828 kb
Host smart-f86480a5-995e-4430-84eb-cdbc408ec97d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949734142 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.1
949734142
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.4163142224
Short name T258
Test name
Test status
Simulation time 67246770 ps
CPU time 0.81 seconds
Started Mar 26 01:47:28 PM PDT 24
Finished Mar 26 01:47:29 PM PDT 24
Peak memory 204872 kb
Host smart-7abaae5c-4dcb-434c-9354-4bf97f89d034
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163142224 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.4
163142224
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.4068119946
Short name T91
Test name
Test status
Simulation time 115897190 ps
CPU time 3.71 seconds
Started Mar 26 01:47:27 PM PDT 24
Finished Mar 26 01:47:30 PM PDT 24
Peak memory 204952 kb
Host smart-4409e77a-e943-4964-8206-69967c0ecd14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068119946 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.4068119946
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.2043375441
Short name T173
Test name
Test status
Simulation time 263832999 ps
CPU time 6.33 seconds
Started Mar 26 01:47:29 PM PDT 24
Finished Mar 26 01:47:35 PM PDT 24
Peak memory 213192 kb
Host smart-d654a5f6-f7ca-4de5-b3a9-a8ffcb624183
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043375441 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.2043375441
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2298059935
Short name T122
Test name
Test status
Simulation time 419759406 ps
CPU time 16.15 seconds
Started Mar 26 01:47:28 PM PDT 24
Finished Mar 26 01:47:44 PM PDT 24
Peak memory 214964 kb
Host smart-0e593ca1-397f-42ab-9d2d-d91735cc955d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298059935 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.2298059935
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2777114522
Short name T284
Test name
Test status
Simulation time 6482775509 ps
CPU time 10.14 seconds
Started Mar 26 01:47:35 PM PDT 24
Finished Mar 26 01:47:46 PM PDT 24
Peak memory 220232 kb
Host smart-ae872973-499b-4774-a4b7-6d393bc85d7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777114522 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.2777114522
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.3448196267
Short name T74
Test name
Test status
Simulation time 204036520 ps
CPU time 1.57 seconds
Started Mar 26 01:47:30 PM PDT 24
Finished Mar 26 01:47:32 PM PDT 24
Peak memory 218376 kb
Host smart-9063576d-75d1-49dc-a723-b28c29777cca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448196267 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.3448196267
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3009621360
Short name T289
Test name
Test status
Simulation time 313521878 ps
CPU time 1.52 seconds
Started Mar 26 01:47:28 PM PDT 24
Finished Mar 26 01:47:29 PM PDT 24
Peak memory 204804 kb
Host smart-8b9db97f-432b-4048-8f74-1ea0f51312ce
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009621360 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.3
009621360
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.926090117
Short name T253
Test name
Test status
Simulation time 88027039 ps
CPU time 0.77 seconds
Started Mar 26 01:47:30 PM PDT 24
Finished Mar 26 01:47:31 PM PDT 24
Peak memory 204524 kb
Host smart-89d3fcf6-18d9-403c-882e-58836e693d7e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926090117 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.926090117
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2954229046
Short name T365
Test name
Test status
Simulation time 986741967 ps
CPU time 8.02 seconds
Started Mar 26 01:47:36 PM PDT 24
Finished Mar 26 01:47:44 PM PDT 24
Peak memory 204976 kb
Host smart-38a4db30-2a3e-4580-85d9-71215c2eab61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954229046 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_
csr_outstanding.2954229046
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.3538925113
Short name T351
Test name
Test status
Simulation time 220538572 ps
CPU time 3.5 seconds
Started Mar 26 01:47:30 PM PDT 24
Finished Mar 26 01:47:34 PM PDT 24
Peak memory 213152 kb
Host smart-40d1a2da-da99-4635-951a-0d47ebe2e45f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538925113 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.3538925113
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.66599648
Short name T128
Test name
Test status
Simulation time 1015116580 ps
CPU time 17.54 seconds
Started Mar 26 01:47:31 PM PDT 24
Finished Mar 26 01:47:48 PM PDT 24
Peak memory 213060 kb
Host smart-2047d266-8d41-47f6-8fba-f15f76cbfe53
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66599648 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.66599648
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.2522105216
Short name T288
Test name
Test status
Simulation time 3311295107 ps
CPU time 7.24 seconds
Started Mar 26 01:47:34 PM PDT 24
Finished Mar 26 01:47:41 PM PDT 24
Peak memory 221460 kb
Host smart-89e2d6ee-aba8-4707-a991-b06500bd102a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522105216 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.2522105216
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1425685742
Short name T316
Test name
Test status
Simulation time 52398782 ps
CPU time 1.52 seconds
Started Mar 26 01:47:35 PM PDT 24
Finished Mar 26 01:47:37 PM PDT 24
Peak memory 213136 kb
Host smart-7d5db0ae-eafd-4b37-97ba-c9e356b73315
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425685742 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.1425685742
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.658633630
Short name T305
Test name
Test status
Simulation time 791183598 ps
CPU time 2.93 seconds
Started Mar 26 01:47:36 PM PDT 24
Finished Mar 26 01:47:39 PM PDT 24
Peak memory 204732 kb
Host smart-ec3692ab-bd0c-47ff-9b82-bb7a8535805c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658633630 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.658633630
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1303794752
Short name T291
Test name
Test status
Simulation time 55698150 ps
CPU time 0.69 seconds
Started Mar 26 01:47:40 PM PDT 24
Finished Mar 26 01:47:41 PM PDT 24
Peak memory 204564 kb
Host smart-5767a6e2-2c70-4288-8dc0-25cd0fe88341
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303794752 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.1
303794752
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.2074751506
Short name T73
Test name
Test status
Simulation time 352696834 ps
CPU time 3.42 seconds
Started Mar 26 01:47:35 PM PDT 24
Finished Mar 26 01:47:39 PM PDT 24
Peak memory 205032 kb
Host smart-6a654f48-c9f2-4fc7-8c5f-8636388ff1d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074751506 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.2074751506
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.1087548617
Short name T331
Test name
Test status
Simulation time 152426290 ps
CPU time 2.79 seconds
Started Mar 26 01:47:36 PM PDT 24
Finished Mar 26 01:47:39 PM PDT 24
Peak memory 213164 kb
Host smart-21481251-6dfe-471e-9ac9-f71024e87202
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087548617 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.1087548617
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2221428326
Short name T125
Test name
Test status
Simulation time 815602542 ps
CPU time 8.48 seconds
Started Mar 26 01:47:37 PM PDT 24
Finished Mar 26 01:47:46 PM PDT 24
Peak memory 213100 kb
Host smart-704eded4-4322-4c9d-8642-bd6e2ae58f11
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221428326 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.2221428326
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.4053395660
Short name T216
Test name
Test status
Simulation time 51806067 ps
CPU time 0.71 seconds
Started Mar 26 03:23:33 PM PDT 24
Finished Mar 26 03:23:34 PM PDT 24
Peak memory 204800 kb
Host smart-02e5d74e-c6ee-41f1-9b76-8a671941ab43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053395660 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.4053395660
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.1412478300
Short name T220
Test name
Test status
Simulation time 2564159868 ps
CPU time 12.22 seconds
Started Mar 26 03:23:32 PM PDT 24
Finished Mar 26 03:23:44 PM PDT 24
Peak memory 215080 kb
Host smart-046ab3a5-c56f-46e0-9370-056dc991294a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412478300 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.1412478300
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.4058710936
Short name T9
Test name
Test status
Simulation time 4234173132 ps
CPU time 4.44 seconds
Started Mar 26 03:23:16 PM PDT 24
Finished Mar 26 03:23:20 PM PDT 24
Peak memory 205084 kb
Host smart-af492424-6a13-4bf0-9bf9-a23c48d196e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058710936 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.4058710936
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.2860084680
Short name T141
Test name
Test status
Simulation time 1768858052 ps
CPU time 3.33 seconds
Started Mar 26 03:23:36 PM PDT 24
Finished Mar 26 03:23:39 PM PDT 24
Peak memory 205032 kb
Host smart-cbf55fac-81e7-4c54-9085-eccf7e52dcf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860084680 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.2860084680
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.341573571
Short name T188
Test name
Test status
Simulation time 106363679 ps
CPU time 0.79 seconds
Started Mar 26 03:23:30 PM PDT 24
Finished Mar 26 03:23:31 PM PDT 24
Peak memory 204780 kb
Host smart-b069a003-9d61-4c50-9c54-c7953c894e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341573571 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.341573571
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.949477392
Short name T201
Test name
Test status
Simulation time 1294573440 ps
CPU time 2.41 seconds
Started Mar 26 03:23:37 PM PDT 24
Finished Mar 26 03:23:40 PM PDT 24
Peak memory 205140 kb
Host smart-c580d74d-9ea4-4fc9-83f0-daea584efcbd
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=949477392 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_tl
_access.949477392
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.1354910521
Short name T203
Test name
Test status
Simulation time 29453126 ps
CPU time 0.72 seconds
Started Mar 26 03:23:39 PM PDT 24
Finished Mar 26 03:23:40 PM PDT 24
Peak memory 204684 kb
Host smart-bc4907d7-717e-48b9-ab9f-2e674caba51c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354910521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.1354910521
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.2605536726
Short name T64
Test name
Test status
Simulation time 419677338 ps
CPU time 1.03 seconds
Started Mar 26 03:23:28 PM PDT 24
Finished Mar 26 03:23:29 PM PDT 24
Peak memory 204684 kb
Host smart-bbcba39b-dbe5-48a1-b410-590ae6413cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605536726 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.2605536726
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.2342034198
Short name T205
Test name
Test status
Simulation time 218821162 ps
CPU time 0.84 seconds
Started Mar 26 03:23:35 PM PDT 24
Finished Mar 26 03:23:36 PM PDT 24
Peak memory 204548 kb
Host smart-861c8f51-2f73-4327-ad4c-8ed8342eab64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342034198 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.2342034198
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.2427555987
Short name T33
Test name
Test status
Simulation time 589118653 ps
CPU time 2.38 seconds
Started Mar 26 03:23:39 PM PDT 24
Finished Mar 26 03:23:43 PM PDT 24
Peak memory 204708 kb
Host smart-29caae4c-3811-42b9-9b37-a4bf70a63cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427555987 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.2427555987
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.4015833176
Short name T53
Test name
Test status
Simulation time 27741001 ps
CPU time 0.7 seconds
Started Mar 26 03:23:28 PM PDT 24
Finished Mar 26 03:23:29 PM PDT 24
Peak memory 204660 kb
Host smart-961788d4-3fef-4413-b8f8-e9155e5a445a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015833176 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.4015833176
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.766356735
Short name T60
Test name
Test status
Simulation time 321483224 ps
CPU time 0.83 seconds
Started Mar 26 03:23:38 PM PDT 24
Finished Mar 26 03:23:39 PM PDT 24
Peak memory 204788 kb
Host smart-e65b6ba8-66b1-4a22-b99e-776b20c9b480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766356735 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.766356735
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.1531944704
Short name T139
Test name
Test status
Simulation time 235650510 ps
CPU time 0.83 seconds
Started Mar 26 03:23:36 PM PDT 24
Finished Mar 26 03:23:37 PM PDT 24
Peak memory 204832 kb
Host smart-6b640b18-a361-4893-9f70-1d88c20b1312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531944704 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.1531944704
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.1214577663
Short name T71
Test name
Test status
Simulation time 709245703 ps
CPU time 3.13 seconds
Started Mar 26 03:23:39 PM PDT 24
Finished Mar 26 03:23:43 PM PDT 24
Peak memory 205056 kb
Host smart-0f08f317-6183-4100-be06-e009cb9a8596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214577663 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.1214577663
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.1646765812
Short name T51
Test name
Test status
Simulation time 129241854 ps
CPU time 1.06 seconds
Started Mar 26 03:23:31 PM PDT 24
Finished Mar 26 03:23:32 PM PDT 24
Peak memory 204804 kb
Host smart-893ab5d1-a1a1-4598-8392-e32dcc90d69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646765812 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.1646765812
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.1299871348
Short name T246
Test name
Test status
Simulation time 1122163421 ps
CPU time 3.7 seconds
Started Mar 26 03:23:41 PM PDT 24
Finished Mar 26 03:23:45 PM PDT 24
Peak memory 205076 kb
Host smart-abe348c6-57f3-4107-9556-48413c6ad393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299871348 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.1299871348
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.3087172823
Short name T191
Test name
Test status
Simulation time 693846135 ps
CPU time 1.02 seconds
Started Mar 26 03:23:35 PM PDT 24
Finished Mar 26 03:23:36 PM PDT 24
Peak memory 204680 kb
Host smart-b4df1f97-f999-4603-a4e1-0c52c1ea13dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087172823 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.3087172823
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.3035600273
Short name T157
Test name
Test status
Simulation time 43704133 ps
CPU time 0.7 seconds
Started Mar 26 03:23:39 PM PDT 24
Finished Mar 26 03:23:40 PM PDT 24
Peak memory 204820 kb
Host smart-f4dcf09f-d4e1-454b-bfb3-441eb937eae4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035600273 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.3035600273
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.3636241450
Short name T208
Test name
Test status
Simulation time 32698879228 ps
CPU time 41.63 seconds
Started Mar 26 03:23:45 PM PDT 24
Finished Mar 26 03:24:27 PM PDT 24
Peak memory 213468 kb
Host smart-eb6dd905-083d-481f-8fc6-7c90a88a3ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636241450 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.3636241450
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.2159987776
Short name T8
Test name
Test status
Simulation time 3053669289 ps
CPU time 3.54 seconds
Started Mar 26 03:23:45 PM PDT 24
Finished Mar 26 03:23:49 PM PDT 24
Peak memory 205068 kb
Host smart-222add31-a4aa-4800-98a4-be074f5a3806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159987776 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.2159987776
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.2122950319
Short name T47
Test name
Test status
Simulation time 150505818 ps
CPU time 0.9 seconds
Started Mar 26 03:23:42 PM PDT 24
Finished Mar 26 03:23:43 PM PDT 24
Peak memory 204832 kb
Host smart-e47d3064-2805-4e25-9e01-d09eefcb9223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122950319 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.2122950319
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.1115867670
Short name T43
Test name
Test status
Simulation time 362879220 ps
CPU time 0.83 seconds
Started Mar 26 03:23:42 PM PDT 24
Finished Mar 26 03:23:43 PM PDT 24
Peak memory 204716 kb
Host smart-090912a0-ad28-42f5-aaba-6a61c41ad251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115867670 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.1115867670
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.1835312280
Short name T142
Test name
Test status
Simulation time 1273269478 ps
CPU time 3.24 seconds
Started Mar 26 03:23:42 PM PDT 24
Finished Mar 26 03:23:45 PM PDT 24
Peak memory 205036 kb
Host smart-93138cee-61a5-40f6-babd-1691b9dd9d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835312280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.1835312280
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.289369798
Short name T138
Test name
Test status
Simulation time 121633099 ps
CPU time 0.83 seconds
Started Mar 26 03:23:41 PM PDT 24
Finished Mar 26 03:23:42 PM PDT 24
Peak memory 204796 kb
Host smart-3b0e6d3c-164c-4160-8606-687d7fdd8c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289369798 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.289369798
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.2188652528
Short name T40
Test name
Test status
Simulation time 321921759 ps
CPU time 1.44 seconds
Started Mar 26 03:23:29 PM PDT 24
Finished Mar 26 03:23:31 PM PDT 24
Peak memory 205104 kb
Host smart-789bc22e-0a4c-4f7e-9c9d-9fdb1fd3557d
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2188652528 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.2188652528
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.439580040
Short name T221
Test name
Test status
Simulation time 332199381 ps
CPU time 1.92 seconds
Started Mar 26 03:23:42 PM PDT 24
Finished Mar 26 03:23:44 PM PDT 24
Peak memory 205044 kb
Host smart-134321ab-6449-4139-a4de-251ed6185472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439580040 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.439580040
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.2376705740
Short name T193
Test name
Test status
Simulation time 42776059 ps
CPU time 0.72 seconds
Started Mar 26 03:23:39 PM PDT 24
Finished Mar 26 03:23:41 PM PDT 24
Peak memory 204684 kb
Host smart-c8a91b37-3db6-463b-a8a5-bc8d5fd7321c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376705740 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.2376705740
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.2144805122
Short name T14
Test name
Test status
Simulation time 118553110 ps
CPU time 0.95 seconds
Started Mar 26 03:23:42 PM PDT 24
Finished Mar 26 03:23:43 PM PDT 24
Peak memory 204660 kb
Host smart-e6bb122b-230c-41c0-9bc2-1f38b6e1cea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144805122 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.2144805122
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.858675447
Short name T230
Test name
Test status
Simulation time 71961861 ps
CPU time 0.91 seconds
Started Mar 26 03:23:32 PM PDT 24
Finished Mar 26 03:23:34 PM PDT 24
Peak memory 204640 kb
Host smart-8d98313d-a9b9-4040-a07a-22d95a2284b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858675447 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.858675447
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.3055766578
Short name T55
Test name
Test status
Simulation time 50200094 ps
CPU time 0.72 seconds
Started Mar 26 03:23:36 PM PDT 24
Finished Mar 26 03:23:37 PM PDT 24
Peak memory 204640 kb
Host smart-1763545e-1a2b-4dbd-9c66-c612c7847496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055766578 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.3055766578
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.2346119684
Short name T242
Test name
Test status
Simulation time 54575919 ps
CPU time 0.79 seconds
Started Mar 26 03:23:46 PM PDT 24
Finished Mar 26 03:23:47 PM PDT 24
Peak memory 204828 kb
Host smart-ac92e3bc-6c0b-4c03-8e11-e393d2a82b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346119684 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.2346119684
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.1946711850
Short name T13
Test name
Test status
Simulation time 588157831 ps
CPU time 1.02 seconds
Started Mar 26 03:23:36 PM PDT 24
Finished Mar 26 03:23:37 PM PDT 24
Peak memory 204808 kb
Host smart-154a785c-6311-43be-b1f7-a0d4426211ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946711850 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.1946711850
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.1072490342
Short name T140
Test name
Test status
Simulation time 1219128862 ps
CPU time 1.87 seconds
Started Mar 26 03:23:39 PM PDT 24
Finished Mar 26 03:23:42 PM PDT 24
Peak memory 205056 kb
Host smart-d3ae4632-e11f-453b-bfe5-a760a8c7637f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072490342 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.1072490342
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.4116601935
Short name T46
Test name
Test status
Simulation time 166188407 ps
CPU time 1.23 seconds
Started Mar 26 03:23:39 PM PDT 24
Finished Mar 26 03:23:40 PM PDT 24
Peak memory 205008 kb
Host smart-3f4385c4-9d8d-4108-9c08-6a62743558f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116601935 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.4116601935
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.3840309895
Short name T44
Test name
Test status
Simulation time 40684730 ps
CPU time 0.83 seconds
Started Mar 26 03:23:41 PM PDT 24
Finished Mar 26 03:23:42 PM PDT 24
Peak memory 213096 kb
Host smart-d9dd7b36-c7f7-462f-a78d-36dda84c18b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840309895 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.3840309895
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.1966227799
Short name T206
Test name
Test status
Simulation time 1619071174 ps
CPU time 6.64 seconds
Started Mar 26 03:23:31 PM PDT 24
Finished Mar 26 03:23:37 PM PDT 24
Peak memory 205152 kb
Host smart-d65fdb9f-4c30-47b8-8efd-8dc298937726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966227799 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.1966227799
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.1444334395
Short name T35
Test name
Test status
Simulation time 373672765 ps
CPU time 1.69 seconds
Started Mar 26 03:23:30 PM PDT 24
Finished Mar 26 03:23:32 PM PDT 24
Peak memory 229236 kb
Host smart-a92120f6-78d7-499d-8e5f-9654002ff113
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444334395 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.1444334395
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.1952997679
Short name T210
Test name
Test status
Simulation time 423798915 ps
CPU time 1.84 seconds
Started Mar 26 03:23:39 PM PDT 24
Finished Mar 26 03:23:41 PM PDT 24
Peak memory 204656 kb
Host smart-ca901b08-0bfe-420c-a49f-8a968cb1530a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952997679 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.1952997679
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.1716121481
Short name T110
Test name
Test status
Simulation time 92600045 ps
CPU time 0.72 seconds
Started Mar 26 03:23:51 PM PDT 24
Finished Mar 26 03:23:52 PM PDT 24
Peak memory 204816 kb
Host smart-0fa26eae-8e3c-4b7b-acac-7481fb5bb3c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716121481 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.1716121481
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.1773986197
Short name T16
Test name
Test status
Simulation time 7626998855 ps
CPU time 15.19 seconds
Started Mar 26 03:23:45 PM PDT 24
Finished Mar 26 03:24:00 PM PDT 24
Peak memory 213384 kb
Host smart-2408ca2a-f7dc-43f5-81a3-8870a018f683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773986197 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.1773986197
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.3133068070
Short name T244
Test name
Test status
Simulation time 14424462643 ps
CPU time 16.39 seconds
Started Mar 26 03:23:46 PM PDT 24
Finished Mar 26 03:24:02 PM PDT 24
Peak memory 213340 kb
Host smart-9a353d3f-ebb6-429f-89ab-34608219e4b1
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3133068070 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.3133068070
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.337250918
Short name T195
Test name
Test status
Simulation time 1834884742 ps
CPU time 4.34 seconds
Started Mar 26 03:23:45 PM PDT 24
Finished Mar 26 03:23:49 PM PDT 24
Peak memory 205152 kb
Host smart-15228cf8-e338-471d-a3a3-d1d24c5f18e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337250918 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.337250918
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.2351835822
Short name T166
Test name
Test status
Simulation time 88535301 ps
CPU time 0.69 seconds
Started Mar 26 03:23:41 PM PDT 24
Finished Mar 26 03:23:42 PM PDT 24
Peak memory 204840 kb
Host smart-96c550f1-d65f-4ffd-88e6-3f3259b90c6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351835822 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.2351835822
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.3851491441
Short name T115
Test name
Test status
Simulation time 18732622669 ps
CPU time 83.18 seconds
Started Mar 26 03:23:44 PM PDT 24
Finished Mar 26 03:25:07 PM PDT 24
Peak memory 213444 kb
Host smart-1d7fe096-9265-48a9-aa01-04d7a3fa4bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851491441 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.3851491441
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.3599810978
Short name T235
Test name
Test status
Simulation time 1118424446 ps
CPU time 3.49 seconds
Started Mar 26 03:23:48 PM PDT 24
Finished Mar 26 03:23:52 PM PDT 24
Peak memory 205100 kb
Host smart-88362ab6-d02b-4eef-bc07-cf25ec89fd98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599810978 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.3599810978
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.4063153434
Short name T234
Test name
Test status
Simulation time 15045333038 ps
CPU time 50.1 seconds
Started Mar 26 03:23:46 PM PDT 24
Finished Mar 26 03:24:36 PM PDT 24
Peak memory 214896 kb
Host smart-63524ea8-94ab-4f2b-86a3-5953add978f0
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4063153434 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_
tl_access.4063153434
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.264718108
Short name T241
Test name
Test status
Simulation time 9741472194 ps
CPU time 31.18 seconds
Started Mar 26 03:23:47 PM PDT 24
Finished Mar 26 03:24:18 PM PDT 24
Peak memory 205232 kb
Host smart-8353ee35-bc8d-4bb4-875c-4855b223bad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264718108 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.264718108
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_stress_all.1302978999
Short name T23
Test name
Test status
Simulation time 5888435595 ps
CPU time 5.77 seconds
Started Mar 26 03:23:45 PM PDT 24
Finished Mar 26 03:23:51 PM PDT 24
Peak memory 213336 kb
Host smart-393bf3bc-35cc-4471-8171-7dc7836058c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302978999 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.1302978999
Directory /workspace/11.rv_dm_stress_all/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.3268965598
Short name T38
Test name
Test status
Simulation time 20657941 ps
CPU time 0.74 seconds
Started Mar 26 03:23:45 PM PDT 24
Finished Mar 26 03:23:46 PM PDT 24
Peak memory 204820 kb
Host smart-28dd6a9c-7bec-4933-b303-d1a339bb70a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268965598 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.3268965598
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.1341476462
Short name T177
Test name
Test status
Simulation time 2029185810 ps
CPU time 6.18 seconds
Started Mar 26 03:23:48 PM PDT 24
Finished Mar 26 03:23:54 PM PDT 24
Peak memory 213324 kb
Host smart-cc9920ac-821b-48f8-9252-4b0b50c40561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341476462 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.1341476462
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.4243225868
Short name T215
Test name
Test status
Simulation time 4264689939 ps
CPU time 6.43 seconds
Started Mar 26 03:23:47 PM PDT 24
Finished Mar 26 03:23:53 PM PDT 24
Peak memory 213316 kb
Host smart-771d46fd-8a6e-44d9-9339-8708507b4868
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4243225868 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.4243225868
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.3384174374
Short name T184
Test name
Test status
Simulation time 3885279564 ps
CPU time 14.57 seconds
Started Mar 26 03:23:52 PM PDT 24
Finished Mar 26 03:24:07 PM PDT 24
Peak memory 205164 kb
Host smart-e7dbf956-6cc4-4e97-b6a1-d010c8db5fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384174374 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.3384174374
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.1409647335
Short name T200
Test name
Test status
Simulation time 18370800 ps
CPU time 0.75 seconds
Started Mar 26 03:23:45 PM PDT 24
Finished Mar 26 03:23:46 PM PDT 24
Peak memory 204680 kb
Host smart-ccfed3f7-ebc6-4d97-bcb9-ac0d17e33631
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409647335 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.1409647335
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.1579111225
Short name T237
Test name
Test status
Simulation time 1936786565 ps
CPU time 5.15 seconds
Started Mar 26 03:23:40 PM PDT 24
Finished Mar 26 03:23:46 PM PDT 24
Peak memory 205120 kb
Host smart-b7960e65-415e-4604-a24a-3aec31bc2bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579111225 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.1579111225
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.691847499
Short name T204
Test name
Test status
Simulation time 9983812714 ps
CPU time 12.18 seconds
Started Mar 26 03:23:46 PM PDT 24
Finished Mar 26 03:23:59 PM PDT 24
Peak memory 205216 kb
Host smart-e714d4b8-f80d-4b34-8ed2-c2f010cc8c02
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=691847499 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_t
l_access.691847499
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.1266489231
Short name T199
Test name
Test status
Simulation time 4727606169 ps
CPU time 19.1 seconds
Started Mar 26 03:23:40 PM PDT 24
Finished Mar 26 03:24:00 PM PDT 24
Peak memory 213484 kb
Host smart-1da0bf74-caca-4940-9440-b19f12867e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266489231 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.1266489231
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_stress_all.3690619559
Short name T22
Test name
Test status
Simulation time 2108595922 ps
CPU time 3.7 seconds
Started Mar 26 03:23:47 PM PDT 24
Finished Mar 26 03:23:51 PM PDT 24
Peak memory 205012 kb
Host smart-be43f81b-6dc1-44bc-81a7-fcef566be33b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690619559 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.3690619559
Directory /workspace/13.rv_dm_stress_all/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.2609212706
Short name T175
Test name
Test status
Simulation time 49001745 ps
CPU time 0.7 seconds
Started Mar 26 03:23:45 PM PDT 24
Finished Mar 26 03:23:46 PM PDT 24
Peak memory 204776 kb
Host smart-22de2836-bf8b-4567-bfe8-87211f057e7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609212706 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.2609212706
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.1398654512
Short name T213
Test name
Test status
Simulation time 755600593 ps
CPU time 3.78 seconds
Started Mar 26 03:23:47 PM PDT 24
Finished Mar 26 03:23:51 PM PDT 24
Peak memory 205072 kb
Host smart-dba513c5-d68c-4132-b046-7222767a92a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398654512 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.1398654512
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.2256848793
Short name T217
Test name
Test status
Simulation time 6848472119 ps
CPU time 26.75 seconds
Started Mar 26 03:23:45 PM PDT 24
Finished Mar 26 03:24:12 PM PDT 24
Peak memory 213332 kb
Host smart-3dedc3c1-ab05-487b-adea-bd3b6ae0f5a0
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2256848793 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.2256848793
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.2207478358
Short name T222
Test name
Test status
Simulation time 4398942580 ps
CPU time 17.56 seconds
Started Mar 26 03:23:39 PM PDT 24
Finished Mar 26 03:23:58 PM PDT 24
Peak memory 205320 kb
Host smart-577ea9a1-394c-4e04-9dfa-d6fcd171cceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207478358 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.2207478358
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.3279584558
Short name T62
Test name
Test status
Simulation time 60161845 ps
CPU time 0.7 seconds
Started Mar 26 03:23:50 PM PDT 24
Finished Mar 26 03:23:56 PM PDT 24
Peak memory 204816 kb
Host smart-1fd5b7ca-fb6b-49f2-b05b-056290856f10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279584558 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.3279584558
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.4245852837
Short name T1
Test name
Test status
Simulation time 5457371835 ps
CPU time 18.68 seconds
Started Mar 26 03:23:44 PM PDT 24
Finished Mar 26 03:24:03 PM PDT 24
Peak memory 214824 kb
Host smart-76044809-db2b-4394-80ea-58a1a6615171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245852837 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.4245852837
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.2383725020
Short name T190
Test name
Test status
Simulation time 1186852867 ps
CPU time 2.29 seconds
Started Mar 26 03:23:40 PM PDT 24
Finished Mar 26 03:23:43 PM PDT 24
Peak memory 205148 kb
Host smart-c14e919b-d041-4426-af1d-644a309b42bd
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2383725020 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_
tl_access.2383725020
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.1437284041
Short name T240
Test name
Test status
Simulation time 5089150192 ps
CPU time 9.92 seconds
Started Mar 26 03:23:35 PM PDT 24
Finished Mar 26 03:23:45 PM PDT 24
Peak memory 205236 kb
Host smart-baf9a2bd-7a52-41d8-b872-42ec69b7f700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437284041 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.1437284041
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.646152528
Short name T147
Test name
Test status
Simulation time 41979944 ps
CPU time 0.73 seconds
Started Mar 26 03:23:53 PM PDT 24
Finished Mar 26 03:23:59 PM PDT 24
Peak memory 204804 kb
Host smart-90eea374-484b-433e-8032-a49cec2154ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646152528 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.646152528
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.3460071532
Short name T180
Test name
Test status
Simulation time 21059900145 ps
CPU time 25.29 seconds
Started Mar 26 03:24:07 PM PDT 24
Finished Mar 26 03:24:32 PM PDT 24
Peak memory 213492 kb
Host smart-66ccdf55-eefc-44f0-a796-9eca3c008cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460071532 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.3460071532
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.3401702814
Short name T189
Test name
Test status
Simulation time 4195402323 ps
CPU time 5.64 seconds
Started Mar 26 03:23:52 PM PDT 24
Finished Mar 26 03:24:02 PM PDT 24
Peak memory 205352 kb
Host smart-d6eb4b7e-074a-4ea6-9893-28355733c785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401702814 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.3401702814
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.3789947961
Short name T247
Test name
Test status
Simulation time 3243271384 ps
CPU time 6.85 seconds
Started Mar 26 03:23:48 PM PDT 24
Finished Mar 26 03:23:55 PM PDT 24
Peak memory 213372 kb
Host smart-2c5d710f-d65b-4cc6-9381-de64c1d97063
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3789947961 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_
tl_access.3789947961
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.125873986
Short name T7
Test name
Test status
Simulation time 3070292811 ps
CPU time 10.81 seconds
Started Mar 26 03:24:17 PM PDT 24
Finished Mar 26 03:24:28 PM PDT 24
Peak memory 205228 kb
Host smart-bcaa7081-99cc-4a38-85f2-2f8348f28964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125873986 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.125873986
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.10473071
Short name T143
Test name
Test status
Simulation time 25999727 ps
CPU time 0.7 seconds
Started Mar 26 03:23:53 PM PDT 24
Finished Mar 26 03:23:54 PM PDT 24
Peak memory 204688 kb
Host smart-0f952b24-34d6-4100-bf0b-cdae654078d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10473071 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.10473071
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.2141297428
Short name T219
Test name
Test status
Simulation time 10714046431 ps
CPU time 19.32 seconds
Started Mar 26 03:23:48 PM PDT 24
Finished Mar 26 03:24:08 PM PDT 24
Peak memory 205188 kb
Host smart-1a017808-e52a-4d60-a656-0fb9fd689c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141297428 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.2141297428
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.2352136347
Short name T238
Test name
Test status
Simulation time 3026309854 ps
CPU time 4.42 seconds
Started Mar 26 03:24:14 PM PDT 24
Finished Mar 26 03:24:18 PM PDT 24
Peak memory 205240 kb
Host smart-8844b8d3-365f-4987-9d06-7f72c36c2e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352136347 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.2352136347
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.2831517921
Short name T179
Test name
Test status
Simulation time 751384259 ps
CPU time 3.81 seconds
Started Mar 26 03:24:08 PM PDT 24
Finished Mar 26 03:24:13 PM PDT 24
Peak memory 205164 kb
Host smart-39d5325d-c81f-4125-b608-cbcf18374733
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2831517921 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_
tl_access.2831517921
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.168232728
Short name T194
Test name
Test status
Simulation time 3518873169 ps
CPU time 5.89 seconds
Started Mar 26 03:23:49 PM PDT 24
Finished Mar 26 03:23:56 PM PDT 24
Peak memory 205136 kb
Host smart-76b8bdb8-232c-4c67-9f51-bef2d242f897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168232728 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.168232728
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.3449604749
Short name T172
Test name
Test status
Simulation time 15834942 ps
CPU time 0.69 seconds
Started Mar 26 03:23:53 PM PDT 24
Finished Mar 26 03:23:54 PM PDT 24
Peak memory 204812 kb
Host smart-03cc1343-348d-4dc9-92a4-fcce0b42243b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449604749 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.3449604749
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.407726472
Short name T211
Test name
Test status
Simulation time 3505038258 ps
CPU time 10.7 seconds
Started Mar 26 03:23:53 PM PDT 24
Finished Mar 26 03:24:04 PM PDT 24
Peak memory 213452 kb
Host smart-1b85ac92-acd7-4cd5-badb-27d594050e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407726472 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.407726472
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.1571758679
Short name T41
Test name
Test status
Simulation time 450011419 ps
CPU time 1.69 seconds
Started Mar 26 03:23:52 PM PDT 24
Finished Mar 26 03:23:55 PM PDT 24
Peak memory 205160 kb
Host smart-fb093916-5866-4ac2-8393-c0ceed0603a5
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1571758679 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_
tl_access.1571758679
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.3593047015
Short name T231
Test name
Test status
Simulation time 466635633 ps
CPU time 2.33 seconds
Started Mar 26 03:23:50 PM PDT 24
Finished Mar 26 03:23:53 PM PDT 24
Peak memory 205112 kb
Host smart-4fd35f33-9d5d-474f-b874-de57e3ba19e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593047015 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.3593047015
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_stress_all.1566112806
Short name T117
Test name
Test status
Simulation time 2502124887 ps
CPU time 4.96 seconds
Started Mar 26 03:23:46 PM PDT 24
Finished Mar 26 03:23:51 PM PDT 24
Peak memory 205012 kb
Host smart-c33a826c-c6b9-492c-abb5-1ea192aa25bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566112806 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.1566112806
Directory /workspace/18.rv_dm_stress_all/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.3019389725
Short name T167
Test name
Test status
Simulation time 35632983 ps
CPU time 0.73 seconds
Started Mar 26 03:23:51 PM PDT 24
Finished Mar 26 03:23:52 PM PDT 24
Peak memory 204792 kb
Host smart-ee473f76-cd75-473a-a39a-2818e4e71c5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019389725 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.3019389725
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.1069788657
Short name T245
Test name
Test status
Simulation time 24166627592 ps
CPU time 61.6 seconds
Started Mar 26 03:23:45 PM PDT 24
Finished Mar 26 03:24:47 PM PDT 24
Peak memory 213412 kb
Host smart-ab8c7cd8-04f6-4399-9336-1b96224769d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069788657 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.1069788657
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.3328500017
Short name T197
Test name
Test status
Simulation time 10756002017 ps
CPU time 34.12 seconds
Started Mar 26 03:23:44 PM PDT 24
Finished Mar 26 03:24:18 PM PDT 24
Peak memory 214832 kb
Host smart-52ef12b1-fb93-402c-aef9-9866c3ec0aaa
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3328500017 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_
tl_access.3328500017
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.1798612262
Short name T226
Test name
Test status
Simulation time 2806593715 ps
CPU time 8.02 seconds
Started Mar 26 03:23:55 PM PDT 24
Finished Mar 26 03:24:04 PM PDT 24
Peak memory 205248 kb
Host smart-a0411cbe-ea49-4f6b-9b0e-b3aa96d549eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798612262 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.1798612262
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.1327313428
Short name T174
Test name
Test status
Simulation time 18386756 ps
CPU time 0.68 seconds
Started Mar 26 03:23:43 PM PDT 24
Finished Mar 26 03:23:44 PM PDT 24
Peak memory 204824 kb
Host smart-39b0dd51-0ed2-49ac-a2f1-62ae8e0bb1d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327313428 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.1327313428
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.2946636540
Short name T11
Test name
Test status
Simulation time 1573342213 ps
CPU time 6.65 seconds
Started Mar 26 03:23:34 PM PDT 24
Finished Mar 26 03:23:41 PM PDT 24
Peak memory 205116 kb
Host smart-590cb671-7328-4386-8ea0-1eb3f275f1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946636540 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.2946636540
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.4212901194
Short name T236
Test name
Test status
Simulation time 924116029 ps
CPU time 3.27 seconds
Started Mar 26 03:23:39 PM PDT 24
Finished Mar 26 03:23:44 PM PDT 24
Peak memory 205068 kb
Host smart-6b28523c-ae10-4648-a0a8-fdb9309f6683
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4212901194 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.4212901194
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.3488430684
Short name T243
Test name
Test status
Simulation time 42611152 ps
CPU time 0.76 seconds
Started Mar 26 03:24:00 PM PDT 24
Finished Mar 26 03:24:01 PM PDT 24
Peak memory 204696 kb
Host smart-39c91447-8235-4525-9540-44d5d92a00e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488430684 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.3488430684
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.1671932726
Short name T176
Test name
Test status
Simulation time 2836162369 ps
CPU time 4.66 seconds
Started Mar 26 03:23:41 PM PDT 24
Finished Mar 26 03:23:46 PM PDT 24
Peak memory 205160 kb
Host smart-c8c733c2-5c23-42cc-8377-f2d6d5d83108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671932726 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.1671932726
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.1513273274
Short name T34
Test name
Test status
Simulation time 406957428 ps
CPU time 1.21 seconds
Started Mar 26 03:23:31 PM PDT 24
Finished Mar 26 03:23:32 PM PDT 24
Peak memory 229184 kb
Host smart-d9c408b2-86eb-4c96-8231-d7f9a9e711ae
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513273274 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.1513273274
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.1664461792
Short name T171
Test name
Test status
Simulation time 54582215 ps
CPU time 0.7 seconds
Started Mar 26 03:23:52 PM PDT 24
Finished Mar 26 03:23:53 PM PDT 24
Peak memory 204796 kb
Host smart-3934ef2f-179f-4905-aaf4-d1fee6e1a53c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664461792 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.1664461792
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.1317198886
Short name T150
Test name
Test status
Simulation time 52315840 ps
CPU time 0.68 seconds
Started Mar 26 03:23:45 PM PDT 24
Finished Mar 26 03:23:46 PM PDT 24
Peak memory 204788 kb
Host smart-f3a66be8-0d62-4dfb-9f9f-aeb1a61bf264
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317198886 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.1317198886
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_stress_all.3905578995
Short name T72
Test name
Test status
Simulation time 2746647853 ps
CPU time 3.34 seconds
Started Mar 26 03:23:47 PM PDT 24
Finished Mar 26 03:23:50 PM PDT 24
Peak memory 205024 kb
Host smart-88c2ed5a-b001-4610-8f4d-1f94ac7990d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905578995 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.3905578995
Directory /workspace/22.rv_dm_stress_all/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.2287195257
Short name T212
Test name
Test status
Simulation time 21919172 ps
CPU time 0.71 seconds
Started Mar 26 03:23:43 PM PDT 24
Finished Mar 26 03:23:44 PM PDT 24
Peak memory 204804 kb
Host smart-1bf4a689-3da3-4fa0-b754-579c5bac34c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287195257 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.2287195257
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.3479113167
Short name T164
Test name
Test status
Simulation time 46095104 ps
CPU time 0.7 seconds
Started Mar 26 03:24:11 PM PDT 24
Finished Mar 26 03:24:13 PM PDT 24
Peak memory 204796 kb
Host smart-fafcabfe-5a34-4e65-9b64-b45f775f0479
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479113167 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.3479113167
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.3537032867
Short name T159
Test name
Test status
Simulation time 51242114 ps
CPU time 0.7 seconds
Started Mar 26 03:23:50 PM PDT 24
Finished Mar 26 03:23:51 PM PDT 24
Peak memory 204812 kb
Host smart-0ae76c53-a8eb-4f37-acbe-e538094ee627
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537032867 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.3537032867
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.667137986
Short name T160
Test name
Test status
Simulation time 41663019 ps
CPU time 0.71 seconds
Started Mar 26 03:23:48 PM PDT 24
Finished Mar 26 03:23:48 PM PDT 24
Peak memory 204820 kb
Host smart-29f08980-7972-4100-b9cf-08c10714b449
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667137986 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.667137986
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_stress_all.2934778270
Short name T70
Test name
Test status
Simulation time 489433221 ps
CPU time 2.39 seconds
Started Mar 26 03:23:54 PM PDT 24
Finished Mar 26 03:23:57 PM PDT 24
Peak memory 205040 kb
Host smart-09ddeed0-03f0-45aa-b7e3-99962b1fbc4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934778270 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.2934778270
Directory /workspace/26.rv_dm_stress_all/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.1639011684
Short name T218
Test name
Test status
Simulation time 25327208 ps
CPU time 0.74 seconds
Started Mar 26 03:23:49 PM PDT 24
Finished Mar 26 03:23:51 PM PDT 24
Peak memory 204796 kb
Host smart-98028895-07b2-4151-ad5b-322b1890b36e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639011684 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.1639011684
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.2702485146
Short name T145
Test name
Test status
Simulation time 25129032 ps
CPU time 0.75 seconds
Started Mar 26 03:24:14 PM PDT 24
Finished Mar 26 03:24:15 PM PDT 24
Peak memory 204764 kb
Host smart-201fdfc1-f484-446e-848c-296db8328e50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702485146 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.2702485146
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.3212913815
Short name T61
Test name
Test status
Simulation time 47949987 ps
CPU time 0.69 seconds
Started Mar 26 03:23:52 PM PDT 24
Finished Mar 26 03:23:53 PM PDT 24
Peak memory 204796 kb
Host smart-fdffc232-fb6d-4eda-9741-bb0bea8b81f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212913815 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.3212913815
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.462679640
Short name T161
Test name
Test status
Simulation time 31929089 ps
CPU time 0.77 seconds
Started Mar 26 03:23:31 PM PDT 24
Finished Mar 26 03:23:32 PM PDT 24
Peak memory 204792 kb
Host smart-df37dbc4-c620-4069-8516-352142119e71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462679640 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.462679640
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.769204304
Short name T183
Test name
Test status
Simulation time 11628025689 ps
CPU time 59.42 seconds
Started Mar 26 03:23:45 PM PDT 24
Finished Mar 26 03:24:45 PM PDT 24
Peak memory 205240 kb
Host smart-0a243049-6747-40c3-8bfe-05a619856d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769204304 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.769204304
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.51674599
Short name T116
Test name
Test status
Simulation time 10350900413 ps
CPU time 12.74 seconds
Started Mar 26 03:23:34 PM PDT 24
Finished Mar 26 03:23:47 PM PDT 24
Peak memory 215560 kb
Host smart-b8081df9-e418-4d0c-8949-694e3d1bb29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51674599 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.51674599
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.1349370562
Short name T83
Test name
Test status
Simulation time 3674779899 ps
CPU time 9.13 seconds
Started Mar 26 03:23:41 PM PDT 24
Finished Mar 26 03:23:51 PM PDT 24
Peak memory 213408 kb
Host smart-da93d476-ba87-4d16-92ec-a5f0b33897f2
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1349370562 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.1349370562
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.233507326
Short name T209
Test name
Test status
Simulation time 50521161 ps
CPU time 0.87 seconds
Started Mar 26 03:23:34 PM PDT 24
Finished Mar 26 03:23:35 PM PDT 24
Peak memory 204708 kb
Host smart-17ae90d7-9721-425d-8aa8-6e4eb341295b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233507326 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.233507326
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.2702505106
Short name T196
Test name
Test status
Simulation time 561349529 ps
CPU time 3.37 seconds
Started Mar 26 03:23:37 PM PDT 24
Finished Mar 26 03:23:41 PM PDT 24
Peak memory 205140 kb
Host smart-1800d37e-dfaf-4f21-8c77-d104cf5bf944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702505106 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.2702505106
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.3904324791
Short name T18
Test name
Test status
Simulation time 189126151 ps
CPU time 1.46 seconds
Started Mar 26 03:23:39 PM PDT 24
Finished Mar 26 03:23:42 PM PDT 24
Peak memory 229176 kb
Host smart-44d1ecb8-1160-4857-9863-32ffc8889525
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904324791 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.3904324791
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.2171667928
Short name T169
Test name
Test status
Simulation time 24474280 ps
CPU time 0.81 seconds
Started Mar 26 03:23:49 PM PDT 24
Finished Mar 26 03:23:51 PM PDT 24
Peak memory 204796 kb
Host smart-890e4325-7dde-41aa-b7f2-d14c0bc08558
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171667928 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.2171667928
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/30.rv_dm_stress_all.1798698233
Short name T2
Test name
Test status
Simulation time 1804577965 ps
CPU time 6.41 seconds
Started Mar 26 03:23:49 PM PDT 24
Finished Mar 26 03:23:55 PM PDT 24
Peak memory 205036 kb
Host smart-e888030c-b3d6-490c-8364-f08f1becfa8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798698233 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.1798698233
Directory /workspace/30.rv_dm_stress_all/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.3114052241
Short name T155
Test name
Test status
Simulation time 29746286 ps
CPU time 0.69 seconds
Started Mar 26 03:23:49 PM PDT 24
Finished Mar 26 03:23:50 PM PDT 24
Peak memory 204820 kb
Host smart-3743e248-f932-454a-be65-c6faf4f7dda5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114052241 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.3114052241
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.371048104
Short name T146
Test name
Test status
Simulation time 39245014 ps
CPU time 0.72 seconds
Started Mar 26 03:23:57 PM PDT 24
Finished Mar 26 03:23:58 PM PDT 24
Peak memory 204844 kb
Host smart-2f61815d-a592-42b5-8502-2077f138cf7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371048104 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.371048104
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.2264142950
Short name T151
Test name
Test status
Simulation time 16526416 ps
CPU time 0.67 seconds
Started Mar 26 03:23:53 PM PDT 24
Finished Mar 26 03:23:54 PM PDT 24
Peak memory 204672 kb
Host smart-434c95b7-e145-4a1a-81cc-d2f1d0010451
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264142950 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.2264142950
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.3513523271
Short name T63
Test name
Test status
Simulation time 17797863 ps
CPU time 0.71 seconds
Started Mar 26 03:23:46 PM PDT 24
Finished Mar 26 03:23:46 PM PDT 24
Peak memory 204812 kb
Host smart-db6aea02-5c19-43e4-8cdd-a0ab24ceb5c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513523271 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.3513523271
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_stress_all.4109312708
Short name T39
Test name
Test status
Simulation time 1978590502 ps
CPU time 6.7 seconds
Started Mar 26 03:23:53 PM PDT 24
Finished Mar 26 03:24:00 PM PDT 24
Peak memory 205072 kb
Host smart-2b33f0c4-b0d1-4de6-90e4-fd3dff8cc879
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109312708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.4109312708
Directory /workspace/35.rv_dm_stress_all/latest

Test location /workspace/coverage/default/36.rv_dm_stress_all.2550039831
Short name T49
Test name
Test status
Simulation time 2755327449 ps
CPU time 5.29 seconds
Started Mar 26 03:23:48 PM PDT 24
Finished Mar 26 03:23:54 PM PDT 24
Peak memory 205028 kb
Host smart-9951c772-f25e-4748-b411-6a534ab55a9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550039831 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.2550039831
Directory /workspace/36.rv_dm_stress_all/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.2330226212
Short name T144
Test name
Test status
Simulation time 40025178 ps
CPU time 0.7 seconds
Started Mar 26 03:24:04 PM PDT 24
Finished Mar 26 03:24:06 PM PDT 24
Peak memory 204804 kb
Host smart-2e862df9-988a-4e9a-8569-f34eb73fcee0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330226212 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.2330226212
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.3154213151
Short name T154
Test name
Test status
Simulation time 30367347 ps
CPU time 0.72 seconds
Started Mar 26 03:23:56 PM PDT 24
Finished Mar 26 03:23:57 PM PDT 24
Peak memory 204788 kb
Host smart-2f6c80d4-4d57-4674-9207-b460bfb51bb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154213151 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.3154213151
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.700898591
Short name T162
Test name
Test status
Simulation time 33439142 ps
CPU time 0.72 seconds
Started Mar 26 03:23:48 PM PDT 24
Finished Mar 26 03:23:48 PM PDT 24
Peak memory 204816 kb
Host smart-774758ec-717c-4f58-a3e1-666092418091
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700898591 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.700898591
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_stress_all.2900537973
Short name T6
Test name
Test status
Simulation time 1783109333 ps
CPU time 6.07 seconds
Started Mar 26 03:23:53 PM PDT 24
Finished Mar 26 03:23:59 PM PDT 24
Peak memory 205044 kb
Host smart-96d82746-c872-4f8a-adc8-422ace134ffb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900537973 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.2900537973
Directory /workspace/39.rv_dm_stress_all/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.3817065943
Short name T4
Test name
Test status
Simulation time 38936331 ps
CPU time 0.74 seconds
Started Mar 26 03:23:43 PM PDT 24
Finished Mar 26 03:23:44 PM PDT 24
Peak memory 204816 kb
Host smart-28b7df28-f6b2-4697-91f1-f31d23bd4d64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817065943 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.3817065943
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.2473990099
Short name T186
Test name
Test status
Simulation time 735948082 ps
CPU time 1.4 seconds
Started Mar 26 03:23:39 PM PDT 24
Finished Mar 26 03:23:42 PM PDT 24
Peak memory 205136 kb
Host smart-b6c3a583-8ff5-480d-bd31-a1a96361459c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473990099 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.2473990099
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.163366927
Short name T239
Test name
Test status
Simulation time 1973610391 ps
CPU time 7.54 seconds
Started Mar 26 03:23:39 PM PDT 24
Finished Mar 26 03:23:47 PM PDT 24
Peak memory 205168 kb
Host smart-542887d2-1d84-4d89-989c-6e04e78cfd71
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=163366927 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_tl
_access.163366927
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.465244718
Short name T37
Test name
Test status
Simulation time 78041655 ps
CPU time 0.75 seconds
Started Mar 26 03:23:41 PM PDT 24
Finished Mar 26 03:23:42 PM PDT 24
Peak memory 204668 kb
Host smart-78fc3c2b-1190-49ce-b017-99be1a430ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465244718 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.465244718
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.1906122169
Short name T82
Test name
Test status
Simulation time 15451745246 ps
CPU time 34.89 seconds
Started Mar 26 03:23:40 PM PDT 24
Finished Mar 26 03:24:15 PM PDT 24
Peak memory 205208 kb
Host smart-5fe1cbb5-8173-4aba-b1f7-41c98dc6be95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906122169 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.1906122169
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.3153297139
Short name T19
Test name
Test status
Simulation time 115871812 ps
CPU time 1.3 seconds
Started Mar 26 03:23:44 PM PDT 24
Finished Mar 26 03:23:46 PM PDT 24
Peak memory 229188 kb
Host smart-40dcbe3e-fa1b-4e8d-8085-c77973245d94
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153297139 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.3153297139
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.2274749616
Short name T158
Test name
Test status
Simulation time 15796289 ps
CPU time 0.76 seconds
Started Mar 26 03:24:02 PM PDT 24
Finished Mar 26 03:24:02 PM PDT 24
Peak memory 204824 kb
Host smart-87058e8b-54a6-4761-849c-16d9bc4aaae6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274749616 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.2274749616
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.615219983
Short name T168
Test name
Test status
Simulation time 25195139 ps
CPU time 0.68 seconds
Started Mar 26 03:23:51 PM PDT 24
Finished Mar 26 03:23:52 PM PDT 24
Peak memory 204812 kb
Host smart-527ad203-91ae-4221-8d74-895c0b091ddc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615219983 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.615219983
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.1361800695
Short name T163
Test name
Test status
Simulation time 24750133 ps
CPU time 0.67 seconds
Started Mar 26 03:23:54 PM PDT 24
Finished Mar 26 03:23:54 PM PDT 24
Peak memory 204796 kb
Host smart-11b85f11-955f-4636-8f61-d31a7d5aec0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361800695 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.1361800695
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.471101024
Short name T165
Test name
Test status
Simulation time 25890726 ps
CPU time 0.72 seconds
Started Mar 26 03:23:57 PM PDT 24
Finished Mar 26 03:23:58 PM PDT 24
Peak memory 204828 kb
Host smart-f629e188-63d7-4428-ae3b-e0f3f518397e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471101024 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.471101024
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.4239431359
Short name T229
Test name
Test status
Simulation time 23801418 ps
CPU time 0.72 seconds
Started Mar 26 03:23:55 PM PDT 24
Finished Mar 26 03:23:56 PM PDT 24
Peak memory 204804 kb
Host smart-2ccf3ce5-5908-4215-ab09-fa92ee169dcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239431359 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.4239431359
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_stress_all.4287597767
Short name T136
Test name
Test status
Simulation time 1910268760 ps
CPU time 6.44 seconds
Started Mar 26 03:23:50 PM PDT 24
Finished Mar 26 03:23:57 PM PDT 24
Peak memory 204988 kb
Host smart-83d63822-23eb-472d-b8a4-698c6d44f269
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287597767 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.4287597767
Directory /workspace/44.rv_dm_stress_all/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.45956719
Short name T31
Test name
Test status
Simulation time 23501360 ps
CPU time 0.74 seconds
Started Mar 26 03:24:12 PM PDT 24
Finished Mar 26 03:24:13 PM PDT 24
Peak memory 204844 kb
Host smart-35762fce-f62b-410a-b2ac-ba99e6174a85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45956719 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.45956719
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.3634964267
Short name T148
Test name
Test status
Simulation time 78524952 ps
CPU time 0.69 seconds
Started Mar 26 03:24:08 PM PDT 24
Finished Mar 26 03:24:10 PM PDT 24
Peak memory 204820 kb
Host smart-bc3bf5ac-f7db-4446-bcaa-cf9fe8cbc567
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634964267 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.3634964267
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.1126640602
Short name T170
Test name
Test status
Simulation time 39258359 ps
CPU time 0.77 seconds
Started Mar 26 03:24:23 PM PDT 24
Finished Mar 26 03:24:24 PM PDT 24
Peak memory 204800 kb
Host smart-cf19da5f-440a-4d65-8497-23c2eb361c84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126640602 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.1126640602
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.4210326436
Short name T32
Test name
Test status
Simulation time 20517858 ps
CPU time 0.74 seconds
Started Mar 26 03:24:16 PM PDT 24
Finished Mar 26 03:24:17 PM PDT 24
Peak memory 204804 kb
Host smart-30ce4c6f-edf9-462a-928e-e23fa7e0af72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210326436 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.4210326436
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.139287442
Short name T152
Test name
Test status
Simulation time 58252278 ps
CPU time 0.7 seconds
Started Mar 26 03:23:38 PM PDT 24
Finished Mar 26 03:23:40 PM PDT 24
Peak memory 204788 kb
Host smart-ca496279-104d-4b7e-b92e-49ef0b6002f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139287442 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.139287442
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.2331041604
Short name T228
Test name
Test status
Simulation time 11059964013 ps
CPU time 46.56 seconds
Started Mar 26 03:23:33 PM PDT 24
Finished Mar 26 03:24:20 PM PDT 24
Peak memory 213392 kb
Host smart-fa1c68c4-c6dc-490b-9b46-1b132c505ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331041604 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.2331041604
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.2354264790
Short name T178
Test name
Test status
Simulation time 4612531270 ps
CPU time 11.63 seconds
Started Mar 26 03:23:41 PM PDT 24
Finished Mar 26 03:23:54 PM PDT 24
Peak memory 213436 kb
Host smart-5f2297e5-5e1e-44b7-a65f-0c5684af1b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354264790 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.2354264790
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.3146206243
Short name T224
Test name
Test status
Simulation time 380104793 ps
CPU time 1.19 seconds
Started Mar 26 03:23:46 PM PDT 24
Finished Mar 26 03:23:47 PM PDT 24
Peak memory 205120 kb
Host smart-43d02b15-0956-4b5c-95a2-5a3f9d99a393
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3146206243 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t
l_access.3146206243
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.213502515
Short name T233
Test name
Test status
Simulation time 11820200245 ps
CPU time 11.8 seconds
Started Mar 26 03:23:39 PM PDT 24
Finished Mar 26 03:23:52 PM PDT 24
Peak memory 213448 kb
Host smart-542af82d-7683-4fbf-8637-abf6809003bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213502515 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.213502515
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.92103589
Short name T149
Test name
Test status
Simulation time 44803418 ps
CPU time 0.7 seconds
Started Mar 26 03:23:42 PM PDT 24
Finished Mar 26 03:23:43 PM PDT 24
Peak memory 204788 kb
Host smart-5b25f109-9216-4faf-9f86-9c15380f5865
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92103589 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.92103589
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.4242168915
Short name T232
Test name
Test status
Simulation time 3769914971 ps
CPU time 5.2 seconds
Started Mar 26 03:23:45 PM PDT 24
Finished Mar 26 03:23:50 PM PDT 24
Peak memory 215188 kb
Host smart-9e8c61a0-6f89-403a-b6ce-f0f81ebb3fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242168915 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.4242168915
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.113560232
Short name T223
Test name
Test status
Simulation time 5315210743 ps
CPU time 5.04 seconds
Started Mar 26 03:23:43 PM PDT 24
Finished Mar 26 03:23:49 PM PDT 24
Peak memory 205228 kb
Host smart-9f0f359c-e03b-4023-b880-29620cde9400
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=113560232 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_tl
_access.113560232
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.1071283031
Short name T214
Test name
Test status
Simulation time 2375948226 ps
CPU time 5.76 seconds
Started Mar 26 03:23:47 PM PDT 24
Finished Mar 26 03:23:53 PM PDT 24
Peak memory 205212 kb
Host smart-d79efb0d-fa27-4b3d-a164-48003cc44892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071283031 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.1071283031
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.5234030
Short name T153
Test name
Test status
Simulation time 35628176 ps
CPU time 0.71 seconds
Started Mar 26 03:23:43 PM PDT 24
Finished Mar 26 03:23:44 PM PDT 24
Peak memory 204748 kb
Host smart-fbca7bbb-c9e7-4d38-bd71-89b60c94a9de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5234030 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.5234030
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.3665897113
Short name T198
Test name
Test status
Simulation time 27085745888 ps
CPU time 59.23 seconds
Started Mar 26 03:23:43 PM PDT 24
Finished Mar 26 03:24:42 PM PDT 24
Peak memory 213368 kb
Host smart-9d20e616-0cdd-4e1d-bd56-5f2ce7850016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665897113 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.3665897113
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.3736092683
Short name T202
Test name
Test status
Simulation time 534699018 ps
CPU time 3.09 seconds
Started Mar 26 03:23:45 PM PDT 24
Finished Mar 26 03:23:48 PM PDT 24
Peak memory 205048 kb
Host smart-22b5a70e-149a-4702-a9df-ea10fc265264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736092683 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.3736092683
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.4072276280
Short name T187
Test name
Test status
Simulation time 1317087322 ps
CPU time 5.27 seconds
Started Mar 26 03:23:58 PM PDT 24
Finished Mar 26 03:24:03 PM PDT 24
Peak memory 205016 kb
Host smart-cbf16a0c-d812-4265-b7a5-5fd43bdb0f9b
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4072276280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.4072276280
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.2863371789
Short name T225
Test name
Test status
Simulation time 3378760273 ps
CPU time 4.9 seconds
Started Mar 26 03:23:41 PM PDT 24
Finished Mar 26 03:23:46 PM PDT 24
Peak memory 205176 kb
Host smart-c9dae7c2-5198-4fd1-a3a5-84680f481f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863371789 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.2863371789
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.2713531425
Short name T227
Test name
Test status
Simulation time 37747905 ps
CPU time 0.7 seconds
Started Mar 26 03:23:45 PM PDT 24
Finished Mar 26 03:23:46 PM PDT 24
Peak memory 204840 kb
Host smart-3e889d5e-0f26-4c77-9083-702e79f1906b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713531425 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.2713531425
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.3181735644
Short name T207
Test name
Test status
Simulation time 18694052658 ps
CPU time 36.85 seconds
Started Mar 26 03:23:44 PM PDT 24
Finished Mar 26 03:24:22 PM PDT 24
Peak memory 213404 kb
Host smart-76e01ae6-4f44-4e2c-971b-09a992ac1b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181735644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.3181735644
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.523464030
Short name T84
Test name
Test status
Simulation time 875987631 ps
CPU time 4.5 seconds
Started Mar 26 03:23:46 PM PDT 24
Finished Mar 26 03:23:51 PM PDT 24
Peak memory 205052 kb
Host smart-b753f922-baf6-4ce5-b1e4-b59e44b27276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523464030 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.523464030
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.109449282
Short name T181
Test name
Test status
Simulation time 2855568699 ps
CPU time 5.41 seconds
Started Mar 26 03:23:38 PM PDT 24
Finished Mar 26 03:23:44 PM PDT 24
Peak memory 205156 kb
Host smart-0ea715e1-2860-4ced-890d-c51c88da432c
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=109449282 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_tl
_access.109449282
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.3569562470
Short name T182
Test name
Test status
Simulation time 3008170215 ps
CPU time 9.12 seconds
Started Mar 26 03:23:53 PM PDT 24
Finished Mar 26 03:24:02 PM PDT 24
Peak memory 213332 kb
Host smart-138ef3ba-fd4d-4388-87f6-1a808bbd0315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569562470 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.3569562470
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.939014526
Short name T156
Test name
Test status
Simulation time 130526555 ps
CPU time 0.71 seconds
Started Mar 26 03:23:43 PM PDT 24
Finished Mar 26 03:23:44 PM PDT 24
Peak memory 204800 kb
Host smart-19b591ce-d5de-4268-a43d-64aa3692489c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939014526 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.939014526
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.1648864025
Short name T192
Test name
Test status
Simulation time 4148915407 ps
CPU time 15.12 seconds
Started Mar 26 03:23:40 PM PDT 24
Finished Mar 26 03:23:56 PM PDT 24
Peak memory 205164 kb
Host smart-e3411581-e451-4201-9204-0568aabbe703
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1648864025 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t
l_access.1648864025
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.1389342234
Short name T185
Test name
Test status
Simulation time 6542726435 ps
CPU time 12.02 seconds
Started Mar 26 03:23:43 PM PDT 24
Finished Mar 26 03:23:55 PM PDT 24
Peak memory 205220 kb
Host smart-745bbb83-1f5f-45cb-bd4c-cccd81db95ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389342234 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.1389342234
Directory /workspace/9.rv_dm_sba_tl_access/latest
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