Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
80.90 94.59 80.85 87.69 78.21 83.99 98.52 42.46


Total test records in report: 368
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html
T275 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3118670675 Mar 28 12:39:18 PM PDT 24 Mar 28 12:39:20 PM PDT 24 43894776 ps
T276 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1522502875 Mar 28 12:38:49 PM PDT 24 Mar 28 12:38:52 PM PDT 24 668474425 ps
T277 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.108275357 Mar 28 12:39:19 PM PDT 24 Mar 28 12:39:24 PM PDT 24 292891539 ps
T278 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.3540194152 Mar 28 12:38:16 PM PDT 24 Mar 28 12:39:42 PM PDT 24 28867305539 ps
T279 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.770689977 Mar 28 12:39:19 PM PDT 24 Mar 28 12:39:26 PM PDT 24 200005180 ps
T280 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.2718241937 Mar 28 12:38:49 PM PDT 24 Mar 28 12:39:39 PM PDT 24 22557563952 ps
T281 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.3925757088 Mar 28 12:38:42 PM PDT 24 Mar 28 12:38:43 PM PDT 24 17217839 ps
T282 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.1009009350 Mar 28 12:39:09 PM PDT 24 Mar 28 12:39:13 PM PDT 24 586063694 ps
T283 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.2033511230 Mar 28 12:39:14 PM PDT 24 Mar 28 12:39:18 PM PDT 24 419742854 ps
T284 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3061427442 Mar 28 12:38:34 PM PDT 24 Mar 28 12:38:57 PM PDT 24 11377488433 ps
T130 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2105488104 Mar 28 12:39:17 PM PDT 24 Mar 28 12:39:26 PM PDT 24 1768488273 ps
T285 /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.4179612000 Mar 28 12:38:44 PM PDT 24 Mar 28 12:38:58 PM PDT 24 5855428969 ps
T114 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.38139463 Mar 28 12:39:13 PM PDT 24 Mar 28 12:39:17 PM PDT 24 324236618 ps
T286 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2712197143 Mar 28 12:39:20 PM PDT 24 Mar 28 12:39:22 PM PDT 24 76529084 ps
T115 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.1776669824 Mar 28 12:38:44 PM PDT 24 Mar 28 12:39:18 PM PDT 24 2579493021 ps
T135 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3971006789 Mar 28 12:39:10 PM PDT 24 Mar 28 12:39:21 PM PDT 24 1644592233 ps
T287 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.2769462363 Mar 28 12:38:48 PM PDT 24 Mar 28 12:38:54 PM PDT 24 451687721 ps
T288 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.1813959420 Mar 28 12:39:09 PM PDT 24 Mar 28 12:39:18 PM PDT 24 908208422 ps
T289 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3728628653 Mar 28 12:39:19 PM PDT 24 Mar 28 12:39:21 PM PDT 24 90477909 ps
T290 /workspace/coverage/cover_reg_top/31.rv_dm_tap_fsm_rand_reset.2902914465 Mar 28 12:39:12 PM PDT 24 Mar 28 12:39:26 PM PDT 24 6732221825 ps
T116 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1649651690 Mar 28 12:39:15 PM PDT 24 Mar 28 12:39:18 PM PDT 24 193452693 ps
T136 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.456039865 Mar 28 12:39:18 PM PDT 24 Mar 28 12:39:30 PM PDT 24 524095569 ps
T291 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.3922142019 Mar 28 12:38:43 PM PDT 24 Mar 28 12:40:01 PM PDT 24 3334634226 ps
T292 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.3868072583 Mar 28 12:38:48 PM PDT 24 Mar 28 12:38:50 PM PDT 24 133847572 ps
T120 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.2682895708 Mar 28 12:39:18 PM PDT 24 Mar 28 12:39:23 PM PDT 24 78651734 ps
T293 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.3452739050 Mar 28 12:38:52 PM PDT 24 Mar 28 12:38:53 PM PDT 24 92573829 ps
T294 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.194012823 Mar 28 12:38:42 PM PDT 24 Mar 28 12:38:45 PM PDT 24 1408764955 ps
T103 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.101466705 Mar 28 12:38:47 PM PDT 24 Mar 28 12:40:09 PM PDT 24 24138591449 ps
T295 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2856067390 Mar 28 12:39:17 PM PDT 24 Mar 28 12:39:21 PM PDT 24 179699297 ps
T296 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2902837495 Mar 28 12:39:17 PM PDT 24 Mar 28 12:39:24 PM PDT 24 2277456303 ps
T137 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.474713223 Mar 28 12:38:42 PM PDT 24 Mar 28 12:39:03 PM PDT 24 1447227424 ps
T104 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.4102562664 Mar 28 12:39:20 PM PDT 24 Mar 28 12:39:23 PM PDT 24 70770274 ps
T297 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.4183938284 Mar 28 12:39:16 PM PDT 24 Mar 28 12:39:18 PM PDT 24 153749403 ps
T298 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.942669496 Mar 28 12:39:10 PM PDT 24 Mar 28 12:39:11 PM PDT 24 26859859 ps
T299 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3724652874 Mar 28 12:38:42 PM PDT 24 Mar 28 12:40:02 PM PDT 24 7800365613 ps
T300 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.3532793725 Mar 28 12:38:31 PM PDT 24 Mar 28 12:38:46 PM PDT 24 5177236315 ps
T301 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.1774076445 Mar 28 12:39:18 PM PDT 24 Mar 28 12:39:39 PM PDT 24 12956658182 ps
T302 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.4197875951 Mar 28 12:39:18 PM PDT 24 Mar 28 12:39:21 PM PDT 24 240652307 ps
T303 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.478215102 Mar 28 12:38:50 PM PDT 24 Mar 28 12:38:56 PM PDT 24 464547399 ps
T304 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.3750955736 Mar 28 12:38:48 PM PDT 24 Mar 28 12:38:53 PM PDT 24 297691311 ps
T305 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.2344478082 Mar 28 12:39:17 PM PDT 24 Mar 28 12:39:22 PM PDT 24 1778875064 ps
T306 /workspace/coverage/cover_reg_top/15.rv_dm_tap_fsm_rand_reset.4069236333 Mar 28 12:39:18 PM PDT 24 Mar 28 12:39:35 PM PDT 24 3901772821 ps
T307 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.2122731155 Mar 28 12:38:41 PM PDT 24 Mar 28 12:38:43 PM PDT 24 1072756197 ps
T132 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.210748400 Mar 28 12:39:17 PM PDT 24 Mar 28 12:39:38 PM PDT 24 2312228782 ps
T308 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2342982277 Mar 28 12:39:18 PM PDT 24 Mar 28 12:39:25 PM PDT 24 351795494 ps
T309 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.4287169759 Mar 28 12:38:55 PM PDT 24 Mar 28 12:39:15 PM PDT 24 5279142397 ps
T310 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.50476457 Mar 28 12:38:43 PM PDT 24 Mar 28 12:38:44 PM PDT 24 121202652 ps
T311 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.966370416 Mar 28 12:39:17 PM PDT 24 Mar 28 12:39:20 PM PDT 24 50841486 ps
T105 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.1806385317 Mar 28 12:38:48 PM PDT 24 Mar 28 12:38:51 PM PDT 24 437338932 ps
T312 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.3033370078 Mar 28 12:38:27 PM PDT 24 Mar 28 12:38:31 PM PDT 24 140650420 ps
T61 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2136999311 Mar 28 12:39:17 PM PDT 24 Mar 28 12:39:18 PM PDT 24 220411168 ps
T313 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2687913275 Mar 28 12:39:19 PM PDT 24 Mar 28 12:39:21 PM PDT 24 181727104 ps
T314 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.2929934160 Mar 28 12:38:51 PM PDT 24 Mar 28 12:38:56 PM PDT 24 699611599 ps
T315 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1301582581 Mar 28 12:38:48 PM PDT 24 Mar 28 12:38:49 PM PDT 24 87899029 ps
T316 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.426726811 Mar 28 12:39:13 PM PDT 24 Mar 28 12:39:18 PM PDT 24 80361387 ps
T317 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.4194056591 Mar 28 12:39:10 PM PDT 24 Mar 28 12:39:13 PM PDT 24 111017544 ps
T318 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.4047917472 Mar 28 12:39:15 PM PDT 24 Mar 28 12:39:20 PM PDT 24 151459697 ps
T319 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3864468547 Mar 28 12:39:10 PM PDT 24 Mar 28 12:39:12 PM PDT 24 266349442 ps
T320 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.3346927750 Mar 28 12:39:11 PM PDT 24 Mar 28 12:39:15 PM PDT 24 226339402 ps
T321 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2289373537 Mar 28 12:39:10 PM PDT 24 Mar 28 12:39:12 PM PDT 24 208576077 ps
T322 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.1643878591 Mar 28 12:39:13 PM PDT 24 Mar 28 12:39:24 PM PDT 24 2212587347 ps
T133 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1436225331 Mar 28 12:39:16 PM PDT 24 Mar 28 12:39:32 PM PDT 24 428432347 ps
T127 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.2382469223 Mar 28 12:39:14 PM PDT 24 Mar 28 12:39:21 PM PDT 24 905114489 ps
T323 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2496302609 Mar 28 12:39:14 PM PDT 24 Mar 28 12:39:18 PM PDT 24 685344459 ps
T106 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3900184790 Mar 28 12:39:01 PM PDT 24 Mar 28 12:39:05 PM PDT 24 163460599 ps
T107 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.1486734307 Mar 28 12:39:14 PM PDT 24 Mar 28 12:39:20 PM PDT 24 330157870 ps
T324 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3455452590 Mar 28 12:38:55 PM PDT 24 Mar 28 12:38:57 PM PDT 24 502078184 ps
T325 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.2465538050 Mar 28 12:39:14 PM PDT 24 Mar 28 12:39:21 PM PDT 24 1323418779 ps
T326 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3962650468 Mar 28 12:39:13 PM PDT 24 Mar 28 12:39:18 PM PDT 24 46005101 ps
T327 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1501848806 Mar 28 12:39:17 PM PDT 24 Mar 28 12:39:21 PM PDT 24 62528386 ps
T328 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.2495529747 Mar 28 12:39:17 PM PDT 24 Mar 28 12:39:20 PM PDT 24 202910857 ps
T329 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.2686005488 Mar 28 12:38:40 PM PDT 24 Mar 28 12:38:41 PM PDT 24 21873607 ps
T330 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1655575841 Mar 28 12:38:44 PM PDT 24 Mar 28 12:39:11 PM PDT 24 3719946170 ps
T331 /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.2676994749 Mar 28 12:38:41 PM PDT 24 Mar 28 12:39:09 PM PDT 24 18000794013 ps
T332 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.2849204197 Mar 28 12:39:15 PM PDT 24 Mar 28 12:39:21 PM PDT 24 3756011349 ps
T333 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1768842601 Mar 28 12:39:12 PM PDT 24 Mar 28 12:39:14 PM PDT 24 29244041 ps
T334 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2813064732 Mar 28 12:39:16 PM PDT 24 Mar 28 12:39:18 PM PDT 24 487290114 ps
T335 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3250574318 Mar 28 12:38:49 PM PDT 24 Mar 28 12:38:51 PM PDT 24 161901400 ps
T336 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.2438144155 Mar 28 12:39:09 PM PDT 24 Mar 28 12:39:16 PM PDT 24 2269740809 ps
T337 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.3170729457 Mar 28 12:39:13 PM PDT 24 Mar 28 12:39:19 PM PDT 24 485124013 ps
T138 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.4202572150 Mar 28 12:39:18 PM PDT 24 Mar 28 12:39:39 PM PDT 24 1384512310 ps
T338 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.4106997307 Mar 28 12:39:18 PM PDT 24 Mar 28 12:39:36 PM PDT 24 1460680694 ps
T339 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1622792748 Mar 28 12:39:17 PM PDT 24 Mar 28 12:39:26 PM PDT 24 482673319 ps
T340 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1280578817 Mar 28 12:39:17 PM PDT 24 Mar 28 12:39:19 PM PDT 24 301555321 ps
T341 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.3175541481 Mar 28 12:38:47 PM PDT 24 Mar 28 12:38:49 PM PDT 24 76995046 ps
T342 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.3468046694 Mar 28 12:38:46 PM PDT 24 Mar 28 12:38:51 PM PDT 24 837026161 ps
T343 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.316227748 Mar 28 12:39:13 PM PDT 24 Mar 28 12:39:20 PM PDT 24 3597172831 ps
T344 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.2525231525 Mar 28 12:39:17 PM PDT 24 Mar 28 12:39:21 PM PDT 24 1356970195 ps
T129 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.1537522915 Mar 28 12:38:16 PM PDT 24 Mar 28 12:38:35 PM PDT 24 1631348720 ps
T111 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.3087599776 Mar 28 12:39:18 PM PDT 24 Mar 28 12:39:22 PM PDT 24 335088585 ps
T345 /workspace/coverage/cover_reg_top/33.rv_dm_tap_fsm_rand_reset.1334239317 Mar 28 12:39:28 PM PDT 24 Mar 28 12:39:49 PM PDT 24 6182642486 ps
T346 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.4169884167 Mar 28 12:39:18 PM PDT 24 Mar 28 12:39:27 PM PDT 24 413927267 ps
T347 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.3029592246 Mar 28 12:39:10 PM PDT 24 Mar 28 12:39:16 PM PDT 24 256369758 ps
T348 /workspace/coverage/cover_reg_top/35.rv_dm_tap_fsm_rand_reset.1660885815 Mar 28 12:39:19 PM PDT 24 Mar 28 12:39:36 PM PDT 24 17191770546 ps
T349 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1849382001 Mar 28 12:39:15 PM PDT 24 Mar 28 12:39:26 PM PDT 24 2785712846 ps
T350 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1607913253 Mar 28 12:38:43 PM PDT 24 Mar 28 12:39:28 PM PDT 24 37673699887 ps
T351 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2709124262 Mar 28 12:39:17 PM PDT 24 Mar 28 12:39:25 PM PDT 24 3876443094 ps
T352 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.558675409 Mar 28 12:39:15 PM PDT 24 Mar 28 12:39:25 PM PDT 24 1008686079 ps
T353 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.1067418083 Mar 28 12:38:42 PM PDT 24 Mar 28 12:39:39 PM PDT 24 1467227989 ps
T112 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.582341341 Mar 28 12:39:09 PM PDT 24 Mar 28 12:39:12 PM PDT 24 787098058 ps
T354 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.3094024667 Mar 28 12:39:14 PM PDT 24 Mar 28 12:39:19 PM PDT 24 296997372 ps
T96 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.1518217346 Mar 28 12:38:43 PM PDT 24 Mar 28 12:38:46 PM PDT 24 701617586 ps
T355 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.2103946898 Mar 28 12:39:13 PM PDT 24 Mar 28 12:39:15 PM PDT 24 32524608 ps
T356 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.4009217233 Mar 28 12:39:10 PM PDT 24 Mar 28 12:39:13 PM PDT 24 369118839 ps
T357 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3047514904 Mar 28 12:38:55 PM PDT 24 Mar 28 12:38:57 PM PDT 24 1785660487 ps
T358 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.108437966 Mar 28 12:39:10 PM PDT 24 Mar 28 12:39:11 PM PDT 24 165303671 ps
T97 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.115395667 Mar 28 12:38:36 PM PDT 24 Mar 28 12:38:38 PM PDT 24 717720347 ps
T113 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3549900757 Mar 28 12:38:35 PM PDT 24 Mar 28 12:39:43 PM PDT 24 2534336963 ps
T359 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.437694501 Mar 28 12:38:49 PM PDT 24 Mar 28 12:38:53 PM PDT 24 117583661 ps
T360 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.1052402257 Mar 28 12:38:41 PM PDT 24 Mar 28 12:38:46 PM PDT 24 2023396064 ps
T361 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.3580196272 Mar 28 12:38:48 PM PDT 24 Mar 28 12:38:49 PM PDT 24 92715666 ps
T362 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2424337137 Mar 28 12:38:41 PM PDT 24 Mar 28 12:39:03 PM PDT 24 12201325479 ps
T363 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3461299721 Mar 28 12:39:17 PM PDT 24 Mar 28 12:39:30 PM PDT 24 5869818311 ps
T364 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.208929558 Mar 28 12:38:43 PM PDT 24 Mar 28 12:38:45 PM PDT 24 812563283 ps
T365 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.1435750263 Mar 28 12:39:16 PM PDT 24 Mar 28 12:40:12 PM PDT 24 2660569654 ps
T366 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.4270750958 Mar 28 12:38:43 PM PDT 24 Mar 28 12:39:39 PM PDT 24 2932439610 ps
T367 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.854370599 Mar 28 12:38:49 PM PDT 24 Mar 28 12:38:51 PM PDT 24 150234730 ps
T368 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.652931583 Mar 28 12:39:13 PM PDT 24 Mar 28 12:39:16 PM PDT 24 170223856 ps

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.1381038179
Short name T10
Test name
Test status
Simulation time 11211813391 ps
CPU time 35.83 seconds
Started Mar 28 12:32:51 PM PDT 24
Finished Mar 28 12:33:27 PM PDT 24
Peak memory 213240 kb
Host smart-463090c0-f407-4d7c-a519-c9bc07638707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381038179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.1381038179
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tap_fsm_rand_reset.3220414208
Short name T40
Test name
Test status
Simulation time 14604295301 ps
CPU time 25.93 seconds
Started Mar 28 12:39:18 PM PDT 24
Finished Mar 28 12:39:46 PM PDT 24
Peak memory 221232 kb
Host smart-d5a9eab5-40a5-46f8-a5db-221a368c0835
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220414208 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rv_dm_tap_fsm_rand_reset.3220414208
Directory /workspace/18.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/39.rv_dm_stress_all.3614824178
Short name T4
Test name
Test status
Simulation time 4436417470 ps
CPU time 2.59 seconds
Started Mar 28 12:32:54 PM PDT 24
Finished Mar 28 12:32:57 PM PDT 24
Peak memory 204800 kb
Host smart-d652fcc9-349a-4468-82aa-30ae39691f1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614824178 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.3614824178
Directory /workspace/39.rv_dm_stress_all/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.637025730
Short name T31
Test name
Test status
Simulation time 40011281 ps
CPU time 0.72 seconds
Started Mar 28 12:32:54 PM PDT 24
Finished Mar 28 12:32:54 PM PDT 24
Peak memory 204536 kb
Host smart-766fc029-96a2-4aad-8610-818c2b986419
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637025730 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.637025730
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_stress_all.1944242697
Short name T27
Test name
Test status
Simulation time 3345578604 ps
CPU time 11.52 seconds
Started Mar 28 12:32:59 PM PDT 24
Finished Mar 28 12:33:11 PM PDT 24
Peak memory 204948 kb
Host smart-2fb20f7e-28c2-4cf5-bfa6-4a86635339ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944242697 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.1944242697
Directory /workspace/19.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2613665197
Short name T41
Test name
Test status
Simulation time 2963907639 ps
CPU time 10.45 seconds
Started Mar 28 12:39:09 PM PDT 24
Finished Mar 28 12:39:19 PM PDT 24
Peak memory 213176 kb
Host smart-71cad888-7d55-42a9-80a7-61350b7f6942
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613665197 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.2613665197
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/28.rv_dm_stress_all.2175447351
Short name T11
Test name
Test status
Simulation time 7373447154 ps
CPU time 5.54 seconds
Started Mar 28 12:33:12 PM PDT 24
Finished Mar 28 12:33:19 PM PDT 24
Peak memory 204824 kb
Host smart-16eec4bd-656d-41ac-9821-de4c276cf9bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175447351 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.2175447351
Directory /workspace/28.rv_dm_stress_all/latest

Test location /workspace/coverage/default/10.rv_dm_stress_all.797636413
Short name T22
Test name
Test status
Simulation time 4579020202 ps
CPU time 6.09 seconds
Started Mar 28 12:32:56 PM PDT 24
Finished Mar 28 12:33:02 PM PDT 24
Peak memory 204980 kb
Host smart-8b33142d-5c1d-4731-881d-053539bc7e41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797636413 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.797636413
Directory /workspace/10.rv_dm_stress_all/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.1075465866
Short name T176
Test name
Test status
Simulation time 5888152365 ps
CPU time 27.13 seconds
Started Mar 28 12:33:11 PM PDT 24
Finished Mar 28 12:33:40 PM PDT 24
Peak memory 215476 kb
Host smart-34daa344-dd21-4a54-b111-954d7b6a6fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075465866 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.1075465866
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.738648088
Short name T88
Test name
Test status
Simulation time 1466021600 ps
CPU time 68.09 seconds
Started Mar 28 12:39:04 PM PDT 24
Finished Mar 28 12:40:13 PM PDT 24
Peak memory 213172 kb
Host smart-ae0e16e1-bdf1-47c3-8150-644664745376
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738648088 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.rv_dm_csr_aliasing.738648088
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.2719829336
Short name T8
Test name
Test status
Simulation time 1801332658 ps
CPU time 3.26 seconds
Started Mar 28 12:32:25 PM PDT 24
Finished Mar 28 12:32:30 PM PDT 24
Peak memory 204680 kb
Host smart-5582dcc3-89dd-4efa-98bb-39192d4b1a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719829336 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.2719829336
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.3133177757
Short name T3
Test name
Test status
Simulation time 276220819 ps
CPU time 1.1 seconds
Started Mar 28 12:32:28 PM PDT 24
Finished Mar 28 12:32:29 PM PDT 24
Peak memory 236652 kb
Host smart-cd474ca8-40d2-43c4-8872-0176f125e6ab
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133177757 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.3133177757
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.474713223
Short name T137
Test name
Test status
Simulation time 1447227424 ps
CPU time 20.86 seconds
Started Mar 28 12:38:42 PM PDT 24
Finished Mar 28 12:39:03 PM PDT 24
Peak memory 213112 kb
Host smart-b8278768-f491-4eef-9213-ae4ed1e05a29
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474713223 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.474713223
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.3325281896
Short name T53
Test name
Test status
Simulation time 43347565 ps
CPU time 0.77 seconds
Started Mar 28 12:32:27 PM PDT 24
Finished Mar 28 12:32:28 PM PDT 24
Peak memory 212960 kb
Host smart-cdd77ac9-ddb8-4ecc-8eb0-756c3433635c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325281896 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.3325281896
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.1417091959
Short name T56
Test name
Test status
Simulation time 299013024 ps
CPU time 1.58 seconds
Started Mar 28 12:32:27 PM PDT 24
Finished Mar 28 12:32:29 PM PDT 24
Peak memory 204908 kb
Host smart-d03b30c2-9fcc-4e88-aa1b-7e35c41743e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417091959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.1417091959
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.2139549229
Short name T46
Test name
Test status
Simulation time 3038347267 ps
CPU time 6.07 seconds
Started Mar 28 12:32:24 PM PDT 24
Finished Mar 28 12:32:31 PM PDT 24
Peak memory 205060 kb
Host smart-823c86ae-edb8-45db-847e-0f946e947da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139549229 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.2139549229
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2136999311
Short name T61
Test name
Test status
Simulation time 220411168 ps
CPU time 0.88 seconds
Started Mar 28 12:39:17 PM PDT 24
Finished Mar 28 12:39:18 PM PDT 24
Peak memory 204728 kb
Host smart-2589bd93-7233-49a9-9236-2ca34d9f8e8e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136999311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
2136999311
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.3702079286
Short name T55
Test name
Test status
Simulation time 43628512 ps
CPU time 0.73 seconds
Started Mar 28 12:32:20 PM PDT 24
Finished Mar 28 12:32:23 PM PDT 24
Peak memory 204648 kb
Host smart-ad35824a-244f-442e-8df4-f07c28421ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702079286 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.3702079286
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.645988887
Short name T6
Test name
Test status
Simulation time 90988369 ps
CPU time 0.74 seconds
Started Mar 28 12:32:26 PM PDT 24
Finished Mar 28 12:32:28 PM PDT 24
Peak memory 204640 kb
Host smart-ec223d6c-8649-4f59-b831-0649955e4827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645988887 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.645988887
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.2723976708
Short name T89
Test name
Test status
Simulation time 280816294 ps
CPU time 6.86 seconds
Started Mar 28 12:39:16 PM PDT 24
Finished Mar 28 12:39:24 PM PDT 24
Peak memory 204972 kb
Host smart-58c87377-5b30-43ce-aa80-a8319f19e964
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723976708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.2723976708
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1436225331
Short name T133
Test name
Test status
Simulation time 428432347 ps
CPU time 15.33 seconds
Started Mar 28 12:39:16 PM PDT 24
Finished Mar 28 12:39:32 PM PDT 24
Peak memory 212868 kb
Host smart-5dcec853-6396-4d11-81ba-0bc86257a4e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436225331 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.1436225331
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3236893755
Short name T236
Test name
Test status
Simulation time 63552771 ps
CPU time 0.7 seconds
Started Mar 28 12:38:25 PM PDT 24
Finished Mar 28 12:38:26 PM PDT 24
Peak memory 204568 kb
Host smart-1a0186cd-b1d6-4dbf-aef5-a0fea0859309
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236893755 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.3236893755
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.115395667
Short name T97
Test name
Test status
Simulation time 717720347 ps
CPU time 1.45 seconds
Started Mar 28 12:38:36 PM PDT 24
Finished Mar 28 12:38:38 PM PDT 24
Peak memory 204968 kb
Host smart-e3296ae9-c4af-459d-84e7-acb89a28489c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115395667 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr
_hw_reset.115395667
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.1292149954
Short name T77
Test name
Test status
Simulation time 3352596048 ps
CPU time 3.44 seconds
Started Mar 28 12:39:09 PM PDT 24
Finished Mar 28 12:39:13 PM PDT 24
Peak memory 215784 kb
Host smart-18456fd4-23ff-4fbd-ba81-5c195001a875
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292149954 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.1292149954
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.2401575292
Short name T58
Test name
Test status
Simulation time 838919087 ps
CPU time 1.27 seconds
Started Mar 28 12:32:28 PM PDT 24
Finished Mar 28 12:32:29 PM PDT 24
Peak memory 204328 kb
Host smart-049592ae-4808-4f2a-a9df-0f627aeb40c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401575292 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.2401575292
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.4102562664
Short name T104
Test name
Test status
Simulation time 70770274 ps
CPU time 2.22 seconds
Started Mar 28 12:39:20 PM PDT 24
Finished Mar 28 12:39:23 PM PDT 24
Peak memory 213060 kb
Host smart-f88b81fc-9fdf-433f-bb62-7cc877e42e71
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102562664 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.4102562664
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.1537522915
Short name T129
Test name
Test status
Simulation time 1631348720 ps
CPU time 18.53 seconds
Started Mar 28 12:38:16 PM PDT 24
Finished Mar 28 12:38:35 PM PDT 24
Peak memory 213052 kb
Host smart-2b18675d-c73b-43e6-ac18-ad71ce7f305e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537522915 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.1537522915
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.306656666
Short name T134
Test name
Test status
Simulation time 4183186423 ps
CPU time 17.44 seconds
Started Mar 28 12:38:42 PM PDT 24
Finished Mar 28 12:39:00 PM PDT 24
Peak memory 213184 kb
Host smart-509051f8-b800-4861-a60b-1a6005bf338a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306656666 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.306656666
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3549900757
Short name T113
Test name
Test status
Simulation time 2534336963 ps
CPU time 68.11 seconds
Started Mar 28 12:38:35 PM PDT 24
Finished Mar 28 12:39:43 PM PDT 24
Peak memory 204968 kb
Host smart-f8e8331b-2b9c-4eac-ae44-d7e8f2258259
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549900757 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.3549900757
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.1067418083
Short name T353
Test name
Test status
Simulation time 1467227989 ps
CPU time 56.21 seconds
Started Mar 28 12:38:42 PM PDT 24
Finished Mar 28 12:39:39 PM PDT 24
Peak memory 204860 kb
Host smart-b316e061-23bb-411b-b8ab-74588ca76875
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067418083 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.1067418083
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3455452590
Short name T324
Test name
Test status
Simulation time 502078184 ps
CPU time 1.65 seconds
Started Mar 28 12:38:55 PM PDT 24
Finished Mar 28 12:38:57 PM PDT 24
Peak memory 213080 kb
Host smart-4b8c7f93-caaf-4c37-9f02-7ebb5a3d5b07
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455452590 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.3455452590
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.467225979
Short name T75
Test name
Test status
Simulation time 2570235178 ps
CPU time 5.16 seconds
Started Mar 28 12:38:49 PM PDT 24
Finished Mar 28 12:38:54 PM PDT 24
Peak memory 216972 kb
Host smart-d4406486-a5c4-48f5-bfe1-9068847ee52c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467225979 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.467225979
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2813136109
Short name T86
Test name
Test status
Simulation time 46848535 ps
CPU time 2.14 seconds
Started Mar 28 12:38:48 PM PDT 24
Finished Mar 28 12:38:51 PM PDT 24
Peak memory 213208 kb
Host smart-0be00b29-fbfc-4eec-b106-b33063f4135f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813136109 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.2813136109
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3061427442
Short name T284
Test name
Test status
Simulation time 11377488433 ps
CPU time 23.07 seconds
Started Mar 28 12:38:34 PM PDT 24
Finished Mar 28 12:38:57 PM PDT 24
Peak memory 204872 kb
Host smart-a195dd84-7516-45ca-bf04-89be3ac2bb02
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061427442 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.3061427442
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.3540194152
Short name T278
Test name
Test status
Simulation time 28867305539 ps
CPU time 86.12 seconds
Started Mar 28 12:38:16 PM PDT 24
Finished Mar 28 12:39:42 PM PDT 24
Peak memory 204784 kb
Host smart-585daa1e-eb9e-4fd5-b6f6-4bd5270accd4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540194152 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_bit_bash.3540194152
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3878459306
Short name T260
Test name
Test status
Simulation time 257339762 ps
CPU time 1.55 seconds
Started Mar 28 12:38:18 PM PDT 24
Finished Mar 28 12:38:20 PM PDT 24
Peak memory 204744 kb
Host smart-2f46f485-c561-46d5-a7fa-017340c52066
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878459306 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.3
878459306
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.3532793725
Short name T300
Test name
Test status
Simulation time 5177236315 ps
CPU time 14.57 seconds
Started Mar 28 12:38:31 PM PDT 24
Finished Mar 28 12:38:46 PM PDT 24
Peak memory 204852 kb
Host smart-6b409d59-e214-4362-8d20-aa17b94e3cfb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532793725 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.3532793725
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.244507727
Short name T244
Test name
Test status
Simulation time 106272358 ps
CPU time 0.72 seconds
Started Mar 28 12:38:27 PM PDT 24
Finished Mar 28 12:38:28 PM PDT 24
Peak memory 204596 kb
Host smart-80db6184-8ec2-4ae3-a595-cc867c5e6253
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244507727 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr
_hw_reset.244507727
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3847207975
Short name T252
Test name
Test status
Simulation time 93540330 ps
CPU time 0.73 seconds
Started Mar 28 12:38:31 PM PDT 24
Finished Mar 28 12:38:32 PM PDT 24
Peak memory 204564 kb
Host smart-38f4908b-6ec6-453d-9f86-03ac0e969bae
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847207975 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.3
847207975
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.2686005488
Short name T329
Test name
Test status
Simulation time 21873607 ps
CPU time 0.66 seconds
Started Mar 28 12:38:40 PM PDT 24
Finished Mar 28 12:38:41 PM PDT 24
Peak memory 204532 kb
Host smart-10ec9e28-8d50-4dd4-b754-b78c2ab30780
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686005488 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.2686005488
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.3925757088
Short name T281
Test name
Test status
Simulation time 17217839 ps
CPU time 0.68 seconds
Started Mar 28 12:38:42 PM PDT 24
Finished Mar 28 12:38:43 PM PDT 24
Peak memory 204548 kb
Host smart-cadcc293-d231-4413-9402-c0a1d0cb12a8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925757088 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.3925757088
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.3750955736
Short name T304
Test name
Test status
Simulation time 297691311 ps
CPU time 4.35 seconds
Started Mar 28 12:38:48 PM PDT 24
Finished Mar 28 12:38:53 PM PDT 24
Peak memory 204924 kb
Host smart-0a4e6d4c-7bc3-4d64-9df3-72e2a4ef7be0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750955736 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.3750955736
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.3033370078
Short name T312
Test name
Test status
Simulation time 140650420 ps
CPU time 3.84 seconds
Started Mar 28 12:38:27 PM PDT 24
Finished Mar 28 12:38:31 PM PDT 24
Peak memory 213052 kb
Host smart-5c369668-5b1c-4e7c-a47f-169cc4cc1264
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033370078 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.3033370078
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3724652874
Short name T299
Test name
Test status
Simulation time 7800365613 ps
CPU time 80.27 seconds
Started Mar 28 12:38:42 PM PDT 24
Finished Mar 28 12:40:02 PM PDT 24
Peak memory 213144 kb
Host smart-55a63161-5bd1-4d36-9d0d-54ea9dadac7a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724652874 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.3724652874
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.4270750958
Short name T366
Test name
Test status
Simulation time 2932439610 ps
CPU time 56.4 seconds
Started Mar 28 12:38:43 PM PDT 24
Finished Mar 28 12:39:39 PM PDT 24
Peak memory 204904 kb
Host smart-04fc60ac-61b5-4017-92b4-793ebe687c8b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270750958 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.4270750958
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.1806385317
Short name T105
Test name
Test status
Simulation time 437338932 ps
CPU time 2.53 seconds
Started Mar 28 12:38:48 PM PDT 24
Finished Mar 28 12:38:51 PM PDT 24
Peak memory 213096 kb
Host smart-d281d089-7421-495a-bfd4-da49ca99cf37
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806385317 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.1806385317
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.103692782
Short name T74
Test name
Test status
Simulation time 146700911 ps
CPU time 2.11 seconds
Started Mar 28 12:38:41 PM PDT 24
Finished Mar 28 12:38:44 PM PDT 24
Peak memory 216016 kb
Host smart-2ebfada7-ab9c-4e9f-806b-21bbd56171b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103692782 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.103692782
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2749727904
Short name T84
Test name
Test status
Simulation time 61723592 ps
CPU time 1.58 seconds
Started Mar 28 12:38:45 PM PDT 24
Finished Mar 28 12:38:47 PM PDT 24
Peak memory 213128 kb
Host smart-844b188e-e1b1-4223-8264-44d7f470b136
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749727904 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.2749727904
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2830172385
Short name T273
Test name
Test status
Simulation time 3156396276 ps
CPU time 6.34 seconds
Started Mar 28 12:38:50 PM PDT 24
Finished Mar 28 12:38:57 PM PDT 24
Peak memory 204896 kb
Host smart-a3d5b3b6-5690-46da-936f-f56f4d870f15
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830172385 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.2830172385
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1607913253
Short name T350
Test name
Test status
Simulation time 37673699887 ps
CPU time 45.08 seconds
Started Mar 28 12:38:43 PM PDT 24
Finished Mar 28 12:39:28 PM PDT 24
Peak memory 204832 kb
Host smart-b130b1fe-75b2-4988-9389-bd36591ed15b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607913253 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_bit_bash.1607913253
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2558096047
Short name T95
Test name
Test status
Simulation time 1150488949 ps
CPU time 2.29 seconds
Started Mar 28 12:38:45 PM PDT 24
Finished Mar 28 12:38:48 PM PDT 24
Peak memory 204860 kb
Host smart-8d90fa0c-ceaa-4eba-b4b9-5a46d77cc142
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558096047 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.2558096047
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1522502875
Short name T276
Test name
Test status
Simulation time 668474425 ps
CPU time 1.51 seconds
Started Mar 28 12:38:49 PM PDT 24
Finished Mar 28 12:38:52 PM PDT 24
Peak memory 204524 kb
Host smart-f2314171-a97a-4dfd-bb7d-64335b73edcd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522502875 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.1
522502875
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.50476457
Short name T310
Test name
Test status
Simulation time 121202652 ps
CPU time 0.82 seconds
Started Mar 28 12:38:43 PM PDT 24
Finished Mar 28 12:38:44 PM PDT 24
Peak memory 204536 kb
Host smart-3bf12b46-3e3a-4915-affd-d6b2e9ac4527
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50476457 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_
aliasing.50476457
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.1052402257
Short name T360
Test name
Test status
Simulation time 2023396064 ps
CPU time 4.7 seconds
Started Mar 28 12:38:41 PM PDT 24
Finished Mar 28 12:38:46 PM PDT 24
Peak memory 204676 kb
Host smart-0e63bb22-fdf9-4e8b-b4cc-e29786a5f61a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052402257 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.1052402257
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.310569005
Short name T241
Test name
Test status
Simulation time 65432855 ps
CPU time 0.78 seconds
Started Mar 28 12:38:48 PM PDT 24
Finished Mar 28 12:38:49 PM PDT 24
Peak memory 204584 kb
Host smart-d2edc336-8345-4c85-bfcb-c10888296663
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310569005 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_hw_reset.310569005
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.1793823249
Short name T249
Test name
Test status
Simulation time 27730326 ps
CPU time 0.78 seconds
Started Mar 28 12:38:42 PM PDT 24
Finished Mar 28 12:38:43 PM PDT 24
Peak memory 204548 kb
Host smart-51b95b03-4c91-4103-aa6c-859e141028d5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793823249 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.1
793823249
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.44150853
Short name T239
Test name
Test status
Simulation time 27165324 ps
CPU time 0.7 seconds
Started Mar 28 12:38:50 PM PDT 24
Finished Mar 28 12:38:51 PM PDT 24
Peak memory 204612 kb
Host smart-fed291bc-14af-47be-998b-e0fc6051b66d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44150853 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_parti
al_access.44150853
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.3933619670
Short name T245
Test name
Test status
Simulation time 98852988 ps
CPU time 0.66 seconds
Started Mar 28 12:38:48 PM PDT 24
Finished Mar 28 12:38:49 PM PDT 24
Peak memory 204636 kb
Host smart-a5313766-ee7b-430e-9ed8-9416c3b7932e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933619670 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.3933619670
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.137610533
Short name T100
Test name
Test status
Simulation time 1620939866 ps
CPU time 8.21 seconds
Started Mar 28 12:38:55 PM PDT 24
Finished Mar 28 12:39:04 PM PDT 24
Peak memory 204960 kb
Host smart-ea889ead-aa10-4ea0-a570-7c217f78598b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137610533 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_c
sr_outstanding.137610533
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.2769462363
Short name T287
Test name
Test status
Simulation time 451687721 ps
CPU time 5.64 seconds
Started Mar 28 12:38:48 PM PDT 24
Finished Mar 28 12:38:54 PM PDT 24
Peak memory 213192 kb
Host smart-8f6afbe0-047e-43b5-9c67-d1918be89cfe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769462363 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.2769462363
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.1112974657
Short name T76
Test name
Test status
Simulation time 610501287 ps
CPU time 4.18 seconds
Started Mar 28 12:39:19 PM PDT 24
Finished Mar 28 12:39:24 PM PDT 24
Peak memory 216580 kb
Host smart-1fc66f47-c50f-4a7c-879f-26c8a81c394c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112974657 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.1112974657
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.3087599776
Short name T111
Test name
Test status
Simulation time 335088585 ps
CPU time 2.22 seconds
Started Mar 28 12:39:18 PM PDT 24
Finished Mar 28 12:39:22 PM PDT 24
Peak memory 212856 kb
Host smart-9972c478-4d7f-41db-8adc-dbb820744dd5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087599776 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.3087599776
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3058411907
Short name T265
Test name
Test status
Simulation time 235915652 ps
CPU time 0.98 seconds
Started Mar 28 12:39:19 PM PDT 24
Finished Mar 28 12:39:22 PM PDT 24
Peak memory 204776 kb
Host smart-caa2fc75-03ee-44f7-9b04-da2461d9830d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058411907 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
3058411907
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.2103946898
Short name T355
Test name
Test status
Simulation time 32524608 ps
CPU time 0.71 seconds
Started Mar 28 12:39:13 PM PDT 24
Finished Mar 28 12:39:15 PM PDT 24
Peak memory 204560 kb
Host smart-7383ca76-1d6d-4359-9e74-103e503d30b7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103946898 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
2103946898
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.558675409
Short name T352
Test name
Test status
Simulation time 1008686079 ps
CPU time 8.46 seconds
Started Mar 28 12:39:15 PM PDT 24
Finished Mar 28 12:39:25 PM PDT 24
Peak memory 204888 kb
Host smart-6f5afddd-f9f3-4a4a-b5a5-18c68760efc8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558675409 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same_
csr_outstanding.558675409
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.2382469223
Short name T127
Test name
Test status
Simulation time 905114489 ps
CPU time 4.91 seconds
Started Mar 28 12:39:14 PM PDT 24
Finished Mar 28 12:39:21 PM PDT 24
Peak memory 212976 kb
Host smart-c850475f-24c7-4bb5-ad41-19950a322f9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382469223 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.2382469223
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1849382001
Short name T349
Test name
Test status
Simulation time 2785712846 ps
CPU time 9.79 seconds
Started Mar 28 12:39:15 PM PDT 24
Finished Mar 28 12:39:26 PM PDT 24
Peak memory 221276 kb
Host smart-70bd34bd-a56d-471a-82e8-6ce1b8b089f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849382001 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.1
849382001
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3962650468
Short name T326
Test name
Test status
Simulation time 46005101 ps
CPU time 2.28 seconds
Started Mar 28 12:39:13 PM PDT 24
Finished Mar 28 12:39:18 PM PDT 24
Peak memory 220340 kb
Host smart-7c6e385b-1131-4918-be7c-17909eac32ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962650468 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.3962650468
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.2509492086
Short name T99
Test name
Test status
Simulation time 79941914 ps
CPU time 2.21 seconds
Started Mar 28 12:39:17 PM PDT 24
Finished Mar 28 12:39:21 PM PDT 24
Peak memory 213200 kb
Host smart-08b05400-7ceb-489f-b742-749b28ef369a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509492086 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.2509492086
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3864468547
Short name T319
Test name
Test status
Simulation time 266349442 ps
CPU time 1.45 seconds
Started Mar 28 12:39:10 PM PDT 24
Finished Mar 28 12:39:12 PM PDT 24
Peak memory 204720 kb
Host smart-eb2f8c77-2abf-4fc7-94ba-97f583ce93ea
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864468547 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
3864468547
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3118670675
Short name T275
Test name
Test status
Simulation time 43894776 ps
CPU time 0.89 seconds
Started Mar 28 12:39:18 PM PDT 24
Finished Mar 28 12:39:20 PM PDT 24
Peak memory 204556 kb
Host smart-0cd267bb-c8bd-496d-aa3a-537dacb1d066
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118670675 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.
3118670675
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.943355074
Short name T82
Test name
Test status
Simulation time 1384755415 ps
CPU time 4.22 seconds
Started Mar 28 12:39:13 PM PDT 24
Finished Mar 28 12:39:18 PM PDT 24
Peak memory 204940 kb
Host smart-564492b4-97c6-443f-97f8-7cd3674f766e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943355074 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same_
csr_outstanding.943355074
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1501848806
Short name T327
Test name
Test status
Simulation time 62528386 ps
CPU time 3.32 seconds
Started Mar 28 12:39:17 PM PDT 24
Finished Mar 28 12:39:21 PM PDT 24
Peak memory 213088 kb
Host smart-f9fdf16a-57b7-4a55-8815-bca987a4179e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501848806 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.1501848806
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.1774076445
Short name T301
Test name
Test status
Simulation time 12956658182 ps
CPU time 19.03 seconds
Started Mar 28 12:39:18 PM PDT 24
Finished Mar 28 12:39:39 PM PDT 24
Peak memory 219616 kb
Host smart-011742f3-2027-4792-a714-5653c3fca2f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774076445 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.1
774076445
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.2344478082
Short name T305
Test name
Test status
Simulation time 1778875064 ps
CPU time 4.86 seconds
Started Mar 28 12:39:17 PM PDT 24
Finished Mar 28 12:39:22 PM PDT 24
Peak memory 218588 kb
Host smart-b1abbb4c-4a04-4c3c-a4f1-ea078f86b73a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344478082 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.2344478082
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.2344230918
Short name T81
Test name
Test status
Simulation time 202291077 ps
CPU time 1.52 seconds
Started Mar 28 12:39:10 PM PDT 24
Finished Mar 28 12:39:12 PM PDT 24
Peak memory 213148 kb
Host smart-6a5983df-58f9-45a6-bf79-57385a0d2a19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344230918 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.2344230918
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.2071476744
Short name T262
Test name
Test status
Simulation time 538844675 ps
CPU time 1.61 seconds
Started Mar 28 12:39:13 PM PDT 24
Finished Mar 28 12:39:17 PM PDT 24
Peak memory 204612 kb
Host smart-87f0c5c7-281e-4dbd-95a9-9ec432c95e47
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071476744 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
2071476744
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.652931583
Short name T368
Test name
Test status
Simulation time 170223856 ps
CPU time 0.78 seconds
Started Mar 28 12:39:13 PM PDT 24
Finished Mar 28 12:39:16 PM PDT 24
Peak memory 204464 kb
Host smart-265cc641-01c6-4403-8788-a030fff87ab6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652931583 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.652931583
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.2682895708
Short name T120
Test name
Test status
Simulation time 78651734 ps
CPU time 3.68 seconds
Started Mar 28 12:39:18 PM PDT 24
Finished Mar 28 12:39:23 PM PDT 24
Peak memory 204884 kb
Host smart-09076097-90ab-4596-86b8-952a43fa9d95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682895708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.2682895708
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.3170729457
Short name T337
Test name
Test status
Simulation time 485124013 ps
CPU time 3.13 seconds
Started Mar 28 12:39:13 PM PDT 24
Finished Mar 28 12:39:19 PM PDT 24
Peak memory 213024 kb
Host smart-aff228c9-f20d-4fe4-ad32-95a402148356
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170729457 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.3170729457
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.210748400
Short name T132
Test name
Test status
Simulation time 2312228782 ps
CPU time 19.83 seconds
Started Mar 28 12:39:17 PM PDT 24
Finished Mar 28 12:39:38 PM PDT 24
Peak memory 213172 kb
Host smart-0f4cc432-6ad6-4adb-afe9-aa2a254b9791
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210748400 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.210748400
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3461299721
Short name T363
Test name
Test status
Simulation time 5869818311 ps
CPU time 12.72 seconds
Started Mar 28 12:39:17 PM PDT 24
Finished Mar 28 12:39:30 PM PDT 24
Peak memory 219388 kb
Host smart-57cbc1dd-c78f-4f30-8aa5-3be70de0fcc8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461299721 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.3461299721
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.1185502621
Short name T101
Test name
Test status
Simulation time 323495360 ps
CPU time 2.24 seconds
Started Mar 28 12:39:17 PM PDT 24
Finished Mar 28 12:39:19 PM PDT 24
Peak memory 213072 kb
Host smart-0730fb06-3032-4edf-84fb-a052b509f04f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185502621 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.1185502621
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.2465538050
Short name T325
Test name
Test status
Simulation time 1323418779 ps
CPU time 4.95 seconds
Started Mar 28 12:39:14 PM PDT 24
Finished Mar 28 12:39:21 PM PDT 24
Peak memory 204820 kb
Host smart-d86b135f-2918-43d0-96e7-f04456054f01
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465538050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
2465538050
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1274295412
Short name T263
Test name
Test status
Simulation time 59565454 ps
CPU time 0.73 seconds
Started Mar 28 12:39:16 PM PDT 24
Finished Mar 28 12:39:18 PM PDT 24
Peak memory 204580 kb
Host smart-0643c5ce-94fc-4ab3-88ef-44606ccf9c8f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274295412 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
1274295412
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.1643878591
Short name T322
Test name
Test status
Simulation time 2212587347 ps
CPU time 8.55 seconds
Started Mar 28 12:39:13 PM PDT 24
Finished Mar 28 12:39:24 PM PDT 24
Peak memory 204940 kb
Host smart-746fe3f4-c975-4090-ba61-449cffc3799e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643878591 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.1643878591
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tap_fsm_rand_reset.3079405292
Short name T139
Test name
Test status
Simulation time 28547657748 ps
CPU time 29.66 seconds
Started Mar 28 12:39:12 PM PDT 24
Finished Mar 28 12:39:43 PM PDT 24
Peak memory 221380 kb
Host smart-cf05533c-2fda-4398-8fa7-70f3495252c5
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079405292 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rv_dm_tap_fsm_rand_reset.3079405292
Directory /workspace/13.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.3961423013
Short name T92
Test name
Test status
Simulation time 158056606 ps
CPU time 5.77 seconds
Started Mar 28 12:39:17 PM PDT 24
Finished Mar 28 12:39:23 PM PDT 24
Peak memory 212960 kb
Host smart-803e09c9-e08c-404d-9a6f-4a58c698a06f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961423013 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.3961423013
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2105488104
Short name T130
Test name
Test status
Simulation time 1768488273 ps
CPU time 8.44 seconds
Started Mar 28 12:39:17 PM PDT 24
Finished Mar 28 12:39:26 PM PDT 24
Peak memory 213476 kb
Host smart-9c895e37-e600-45b5-baae-c094e1e4899f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105488104 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.2
105488104
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.2849204197
Short name T332
Test name
Test status
Simulation time 3756011349 ps
CPU time 4.95 seconds
Started Mar 28 12:39:15 PM PDT 24
Finished Mar 28 12:39:21 PM PDT 24
Peak memory 213168 kb
Host smart-c37b9648-6dab-4d2a-ba16-5d8bcaa37691
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849204197 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.2849204197
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3579835385
Short name T258
Test name
Test status
Simulation time 173259800 ps
CPU time 0.96 seconds
Started Mar 28 12:39:17 PM PDT 24
Finished Mar 28 12:39:19 PM PDT 24
Peak memory 204708 kb
Host smart-01cdf4f4-7f13-4f5b-b211-05b4a5440466
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579835385 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
3579835385
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2712197143
Short name T286
Test name
Test status
Simulation time 76529084 ps
CPU time 0.92 seconds
Started Mar 28 12:39:20 PM PDT 24
Finished Mar 28 12:39:22 PM PDT 24
Peak memory 204524 kb
Host smart-07183beb-7e55-442f-b397-73f584db147a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712197143 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
2712197143
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.4047917472
Short name T318
Test name
Test status
Simulation time 151459697 ps
CPU time 3.6 seconds
Started Mar 28 12:39:15 PM PDT 24
Finished Mar 28 12:39:20 PM PDT 24
Peak memory 204864 kb
Host smart-68f821ff-3c71-49ea-a04c-f4b39e8be73d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047917472 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.4047917472
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.770689977
Short name T279
Test name
Test status
Simulation time 200005180 ps
CPU time 5.73 seconds
Started Mar 28 12:39:19 PM PDT 24
Finished Mar 28 12:39:26 PM PDT 24
Peak memory 213108 kb
Host smart-85f86e8c-4f47-43e3-b2b7-8ebb87914a3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770689977 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.770689977
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1622792748
Short name T339
Test name
Test status
Simulation time 482673319 ps
CPU time 8.83 seconds
Started Mar 28 12:39:17 PM PDT 24
Finished Mar 28 12:39:26 PM PDT 24
Peak memory 213332 kb
Host smart-ee49818e-a474-4c2b-b89e-6f235fa5a42a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622792748 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.1
622792748
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.3337859392
Short name T261
Test name
Test status
Simulation time 3322725391 ps
CPU time 8.76 seconds
Started Mar 28 12:39:18 PM PDT 24
Finished Mar 28 12:39:29 PM PDT 24
Peak memory 221100 kb
Host smart-8f259587-2313-4e3a-a4b5-1ea61adb47e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337859392 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.3337859392
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.3175486129
Short name T110
Test name
Test status
Simulation time 115792917 ps
CPU time 2.51 seconds
Started Mar 28 12:39:17 PM PDT 24
Finished Mar 28 12:39:22 PM PDT 24
Peak memory 212976 kb
Host smart-e48c8783-14f2-4cb6-b28e-1487c6b54391
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175486129 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.3175486129
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1700679942
Short name T235
Test name
Test status
Simulation time 884248116 ps
CPU time 2.45 seconds
Started Mar 28 12:39:20 PM PDT 24
Finished Mar 28 12:39:23 PM PDT 24
Peak memory 204712 kb
Host smart-c7d17110-ceb1-41ae-b8fd-4728d4b68c08
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700679942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
1700679942
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3398127372
Short name T272
Test name
Test status
Simulation time 78990789 ps
CPU time 0.86 seconds
Started Mar 28 12:39:19 PM PDT 24
Finished Mar 28 12:39:21 PM PDT 24
Peak memory 204560 kb
Host smart-3fd9f355-d2f7-45f4-bb25-130ba478af10
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398127372 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
3398127372
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.4169884167
Short name T346
Test name
Test status
Simulation time 413927267 ps
CPU time 7.63 seconds
Started Mar 28 12:39:18 PM PDT 24
Finished Mar 28 12:39:27 PM PDT 24
Peak memory 204860 kb
Host smart-52714063-37ee-4599-94f3-15de1a11cd0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169884167 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.4169884167
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tap_fsm_rand_reset.4069236333
Short name T306
Test name
Test status
Simulation time 3901772821 ps
CPU time 15.28 seconds
Started Mar 28 12:39:18 PM PDT 24
Finished Mar 28 12:39:35 PM PDT 24
Peak memory 219580 kb
Host smart-311bcae2-2915-4f3e-b3a1-bee5d7700cda
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069236333 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rv_dm_tap_fsm_rand_reset.4069236333
Directory /workspace/15.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.3540302486
Short name T42
Test name
Test status
Simulation time 37153748 ps
CPU time 2.22 seconds
Started Mar 28 12:39:12 PM PDT 24
Finished Mar 28 12:39:15 PM PDT 24
Peak memory 213072 kb
Host smart-f16a2708-52cc-49b6-b365-c4b3fb76540f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540302486 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.3540302486
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.4115426589
Short name T131
Test name
Test status
Simulation time 309368680 ps
CPU time 8.64 seconds
Started Mar 28 12:39:19 PM PDT 24
Finished Mar 28 12:39:29 PM PDT 24
Peak memory 221248 kb
Host smart-aaf07cf9-39ab-4dfd-8076-a8a690519eb5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115426589 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.4
115426589
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.546462506
Short name T78
Test name
Test status
Simulation time 2837925999 ps
CPU time 7.73 seconds
Started Mar 28 12:39:15 PM PDT 24
Finished Mar 28 12:39:23 PM PDT 24
Peak memory 218748 kb
Host smart-9bb76b02-0253-4913-86b8-4de0a5b85882
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546462506 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.546462506
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.1202889354
Short name T85
Test name
Test status
Simulation time 288261432 ps
CPU time 2.3 seconds
Started Mar 28 12:39:18 PM PDT 24
Finished Mar 28 12:39:22 PM PDT 24
Peak memory 213140 kb
Host smart-b75b168e-afe4-43eb-b6c3-6c95d618e730
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202889354 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.1202889354
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.1370228282
Short name T255
Test name
Test status
Simulation time 328871771 ps
CPU time 1.2 seconds
Started Mar 28 12:39:14 PM PDT 24
Finished Mar 28 12:39:17 PM PDT 24
Peak memory 204616 kb
Host smart-1e8769d4-fd54-4735-b2e2-d1950405aab1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370228282 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
1370228282
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.412090392
Short name T250
Test name
Test status
Simulation time 97586414 ps
CPU time 0.79 seconds
Started Mar 28 12:39:18 PM PDT 24
Finished Mar 28 12:39:20 PM PDT 24
Peak memory 204552 kb
Host smart-17b71bd6-f5d8-4778-a30b-b419d1fbdf6a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412090392 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.412090392
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1808814312
Short name T119
Test name
Test status
Simulation time 444260505 ps
CPU time 7.96 seconds
Started Mar 28 12:39:15 PM PDT 24
Finished Mar 28 12:39:24 PM PDT 24
Peak memory 204820 kb
Host smart-6035e967-34e4-4850-9b85-633653c4130c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808814312 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.1808814312
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.1329100338
Short name T247
Test name
Test status
Simulation time 190104221 ps
CPU time 4.6 seconds
Started Mar 28 12:39:18 PM PDT 24
Finished Mar 28 12:39:25 PM PDT 24
Peak memory 213048 kb
Host smart-885b5ca6-eae9-41f4-9bf8-b4b3e3519a35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329100338 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.1329100338
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.456039865
Short name T136
Test name
Test status
Simulation time 524095569 ps
CPU time 9.74 seconds
Started Mar 28 12:39:18 PM PDT 24
Finished Mar 28 12:39:30 PM PDT 24
Peak memory 213080 kb
Host smart-d13d5175-72f4-4673-aa68-b0e4b93a22d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456039865 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.456039865
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2856067390
Short name T295
Test name
Test status
Simulation time 179699297 ps
CPU time 2.47 seconds
Started Mar 28 12:39:17 PM PDT 24
Finished Mar 28 12:39:21 PM PDT 24
Peak memory 217496 kb
Host smart-4c9d3c3c-dd6c-485a-bc1c-9d9e9fbf3dc1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856067390 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.2856067390
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.2495529747
Short name T328
Test name
Test status
Simulation time 202910857 ps
CPU time 1.6 seconds
Started Mar 28 12:39:17 PM PDT 24
Finished Mar 28 12:39:20 PM PDT 24
Peak memory 213208 kb
Host smart-a911d4f5-fdbf-40ab-89c5-be1c70a44276
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495529747 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.2495529747
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2856692212
Short name T268
Test name
Test status
Simulation time 693147235 ps
CPU time 1.58 seconds
Started Mar 28 12:39:15 PM PDT 24
Finished Mar 28 12:39:18 PM PDT 24
Peak memory 204664 kb
Host smart-4c3bbed6-d7e5-44ea-a7e3-7c26b16ba0e2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856692212 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
2856692212
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.966370416
Short name T311
Test name
Test status
Simulation time 50841486 ps
CPU time 0.72 seconds
Started Mar 28 12:39:17 PM PDT 24
Finished Mar 28 12:39:20 PM PDT 24
Peak memory 204616 kb
Host smart-14c8058d-5256-4f93-be5d-f510a361b6be
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966370416 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.966370416
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2541582245
Short name T98
Test name
Test status
Simulation time 741189979 ps
CPU time 6.49 seconds
Started Mar 28 12:39:18 PM PDT 24
Finished Mar 28 12:39:26 PM PDT 24
Peak memory 204876 kb
Host smart-29b46702-0a16-4e76-86d9-9545f4e8f613
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541582245 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.2541582245
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2257227523
Short name T79
Test name
Test status
Simulation time 453024647 ps
CPU time 5.1 seconds
Started Mar 28 12:39:15 PM PDT 24
Finished Mar 28 12:39:22 PM PDT 24
Peak memory 213084 kb
Host smart-c1e144b6-78e6-4e4a-863d-840c275a97bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257227523 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.2257227523
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.4106997307
Short name T338
Test name
Test status
Simulation time 1460680694 ps
CPU time 15.95 seconds
Started Mar 28 12:39:18 PM PDT 24
Finished Mar 28 12:39:36 PM PDT 24
Peak memory 212648 kb
Host smart-788f00e2-fd37-4983-bd8a-27198865c6bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106997307 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.4
106997307
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2709124262
Short name T351
Test name
Test status
Simulation time 3876443094 ps
CPU time 6.59 seconds
Started Mar 28 12:39:17 PM PDT 24
Finished Mar 28 12:39:25 PM PDT 24
Peak memory 218888 kb
Host smart-df749990-211e-4787-8de5-359b006015db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709124262 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.2709124262
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.4197875951
Short name T302
Test name
Test status
Simulation time 240652307 ps
CPU time 1.57 seconds
Started Mar 28 12:39:18 PM PDT 24
Finished Mar 28 12:39:21 PM PDT 24
Peak memory 217684 kb
Host smart-7e291b0d-38b9-4092-92bc-8d0d8150e94a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197875951 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.4197875951
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.3018880850
Short name T259
Test name
Test status
Simulation time 337653705 ps
CPU time 1.14 seconds
Started Mar 28 12:39:09 PM PDT 24
Finished Mar 28 12:39:11 PM PDT 24
Peak memory 204576 kb
Host smart-76d73c2e-a627-4421-a4c4-68280c1ad75a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018880850 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
3018880850
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.4096969396
Short name T65
Test name
Test status
Simulation time 52260774 ps
CPU time 0.81 seconds
Started Mar 28 12:39:17 PM PDT 24
Finished Mar 28 12:39:18 PM PDT 24
Peak memory 204560 kb
Host smart-db876f00-f164-4d72-a8bf-f2bffb30b45e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096969396 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
4096969396
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2342982277
Short name T308
Test name
Test status
Simulation time 351795494 ps
CPU time 4.97 seconds
Started Mar 28 12:39:18 PM PDT 24
Finished Mar 28 12:39:25 PM PDT 24
Peak memory 213076 kb
Host smart-18edfeb7-ab7b-4778-9e86-17285c732f7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342982277 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.2342982277
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.1813959420
Short name T288
Test name
Test status
Simulation time 908208422 ps
CPU time 8.58 seconds
Started Mar 28 12:39:09 PM PDT 24
Finished Mar 28 12:39:18 PM PDT 24
Peak memory 221140 kb
Host smart-cf8cd33c-0991-4b3f-bafa-a983d7ff314a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813959420 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.1
813959420
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3241558172
Short name T39
Test name
Test status
Simulation time 4488731471 ps
CPU time 5.82 seconds
Started Mar 28 12:39:17 PM PDT 24
Finished Mar 28 12:39:23 PM PDT 24
Peak memory 218648 kb
Host smart-a254947f-d205-4e9b-92a1-f5845c452a6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241558172 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.3241558172
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.2033511230
Short name T283
Test name
Test status
Simulation time 419742854 ps
CPU time 2.62 seconds
Started Mar 28 12:39:14 PM PDT 24
Finished Mar 28 12:39:18 PM PDT 24
Peak memory 221152 kb
Host smart-a1d72b64-8420-4254-8652-00e8577d6189
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033511230 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.2033511230
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.720088120
Short name T271
Test name
Test status
Simulation time 113986860 ps
CPU time 0.7 seconds
Started Mar 28 12:39:16 PM PDT 24
Finished Mar 28 12:39:18 PM PDT 24
Peak memory 204536 kb
Host smart-ea6e7698-2495-4403-8542-eac5b77f3f9b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720088120 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.720088120
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1868948170
Short name T117
Test name
Test status
Simulation time 889010522 ps
CPU time 4.11 seconds
Started Mar 28 12:39:17 PM PDT 24
Finished Mar 28 12:39:21 PM PDT 24
Peak memory 204896 kb
Host smart-afb20ea7-5634-43f0-85bd-14188904397a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868948170 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.1868948170
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.2525231525
Short name T344
Test name
Test status
Simulation time 1356970195 ps
CPU time 3.96 seconds
Started Mar 28 12:39:17 PM PDT 24
Finished Mar 28 12:39:21 PM PDT 24
Peak memory 213052 kb
Host smart-caf77a6e-422b-4342-aec7-4c1dbe2f0466
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525231525 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.2525231525
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.4202572150
Short name T138
Test name
Test status
Simulation time 1384512310 ps
CPU time 19.36 seconds
Started Mar 28 12:39:18 PM PDT 24
Finished Mar 28 12:39:39 PM PDT 24
Peak memory 221296 kb
Host smart-6297f473-23ec-4ea3-bf65-6c66ea4f5b6a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202572150 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.4
202572150
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.101466705
Short name T103
Test name
Test status
Simulation time 24138591449 ps
CPU time 80.75 seconds
Started Mar 28 12:38:47 PM PDT 24
Finished Mar 28 12:40:09 PM PDT 24
Peak memory 213204 kb
Host smart-5a45868b-320e-4ffc-bfc8-b3a7799cde2e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101466705 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.rv_dm_csr_aliasing.101466705
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.1776669824
Short name T115
Test name
Test status
Simulation time 2579493021 ps
CPU time 33.16 seconds
Started Mar 28 12:38:44 PM PDT 24
Finished Mar 28 12:39:18 PM PDT 24
Peak memory 204960 kb
Host smart-d39eb7b8-2cd7-4367-8a4f-f4d3ed6c1475
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776669824 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.1776669824
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3047514904
Short name T357
Test name
Test status
Simulation time 1785660487 ps
CPU time 2.6 seconds
Started Mar 28 12:38:55 PM PDT 24
Finished Mar 28 12:38:57 PM PDT 24
Peak memory 213144 kb
Host smart-a445e6df-e858-4183-b6b2-877a3f25e83a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047514904 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.3047514904
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.1036609855
Short name T248
Test name
Test status
Simulation time 459579356 ps
CPU time 2.51 seconds
Started Mar 28 12:38:40 PM PDT 24
Finished Mar 28 12:38:43 PM PDT 24
Peak memory 217132 kb
Host smart-0b5d0b61-dd08-42b2-b9e1-28c9905ee79f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036609855 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.1036609855
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3420620464
Short name T269
Test name
Test status
Simulation time 87537077 ps
CPU time 1.47 seconds
Started Mar 28 12:38:42 PM PDT 24
Finished Mar 28 12:38:44 PM PDT 24
Peak memory 218224 kb
Host smart-4b4ec30d-01bd-46bb-bc50-22e67b569640
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420620464 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.3420620464
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2424337137
Short name T362
Test name
Test status
Simulation time 12201325479 ps
CPU time 21.28 seconds
Started Mar 28 12:38:41 PM PDT 24
Finished Mar 28 12:39:03 PM PDT 24
Peak memory 204892 kb
Host smart-be46aa91-4920-4d98-a70d-d030d7cefb73
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424337137 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.2424337137
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.2718241937
Short name T280
Test name
Test status
Simulation time 22557563952 ps
CPU time 48.95 seconds
Started Mar 28 12:38:49 PM PDT 24
Finished Mar 28 12:39:39 PM PDT 24
Peak memory 204848 kb
Host smart-ec479bd6-0bd1-4877-9f1f-4b9bd792739f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718241937 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_bit_bash.2718241937
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.3589311795
Short name T93
Test name
Test status
Simulation time 739463474 ps
CPU time 2.13 seconds
Started Mar 28 12:38:41 PM PDT 24
Finished Mar 28 12:38:43 PM PDT 24
Peak memory 204872 kb
Host smart-1c8dcf0d-4c58-41b6-b90d-b890c7ea7a74
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589311795 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.3589311795
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.3868072583
Short name T292
Test name
Test status
Simulation time 133847572 ps
CPU time 1.31 seconds
Started Mar 28 12:38:48 PM PDT 24
Finished Mar 28 12:38:50 PM PDT 24
Peak memory 204712 kb
Host smart-9b172f73-e2a2-4317-b5cd-5b74c7f96091
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868072583 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.3
868072583
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.854370599
Short name T367
Test name
Test status
Simulation time 150234730 ps
CPU time 1.13 seconds
Started Mar 28 12:38:49 PM PDT 24
Finished Mar 28 12:38:51 PM PDT 24
Peak memory 204580 kb
Host smart-40dd3d5e-e125-4379-8aa0-83cfc7a686f8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854370599 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_aliasing.854370599
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.2122731155
Short name T307
Test name
Test status
Simulation time 1072756197 ps
CPU time 1.76 seconds
Started Mar 28 12:38:41 PM PDT 24
Finished Mar 28 12:38:43 PM PDT 24
Peak memory 204780 kb
Host smart-bf8fc06f-5eb7-4e07-b3eb-8d488ec3bfb8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122731155 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.2122731155
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1355928309
Short name T238
Test name
Test status
Simulation time 53633302 ps
CPU time 0.78 seconds
Started Mar 28 12:38:48 PM PDT 24
Finished Mar 28 12:38:49 PM PDT 24
Peak memory 204596 kb
Host smart-a47c7b1b-ce59-4d8d-94a5-187445635658
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355928309 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.1355928309
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.3580196272
Short name T361
Test name
Test status
Simulation time 92715666 ps
CPU time 0.9 seconds
Started Mar 28 12:38:48 PM PDT 24
Finished Mar 28 12:38:49 PM PDT 24
Peak memory 204524 kb
Host smart-09c7d2a4-03b6-4063-9c47-628b704bef7b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580196272 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.3
580196272
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1301582581
Short name T315
Test name
Test status
Simulation time 87899029 ps
CPU time 0.68 seconds
Started Mar 28 12:38:48 PM PDT 24
Finished Mar 28 12:38:49 PM PDT 24
Peak memory 204564 kb
Host smart-91df0ca7-08d5-469d-98a2-b1c1e2e12615
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301582581 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.1301582581
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.2241944898
Short name T264
Test name
Test status
Simulation time 42215897 ps
CPU time 0.65 seconds
Started Mar 28 12:38:49 PM PDT 24
Finished Mar 28 12:38:50 PM PDT 24
Peak memory 204600 kb
Host smart-a1821e90-bb7a-452d-9cab-9de31d5ed708
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241944898 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.2241944898
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3900184790
Short name T106
Test name
Test status
Simulation time 163460599 ps
CPU time 3.5 seconds
Started Mar 28 12:39:01 PM PDT 24
Finished Mar 28 12:39:05 PM PDT 24
Peak memory 204964 kb
Host smart-fac38c86-ea40-4f72-9798-f03c378a8918
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900184790 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.3900184790
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.2676994749
Short name T331
Test name
Test status
Simulation time 18000794013 ps
CPU time 26.82 seconds
Started Mar 28 12:38:41 PM PDT 24
Finished Mar 28 12:39:09 PM PDT 24
Peak memory 229528 kb
Host smart-f0d0ac62-c474-4836-b8c3-02c4e61d8982
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676994749 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.2676994749
Directory /workspace/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.194012823
Short name T294
Test name
Test status
Simulation time 1408764955 ps
CPU time 2.88 seconds
Started Mar 28 12:38:42 PM PDT 24
Finished Mar 28 12:38:45 PM PDT 24
Peak memory 213188 kb
Host smart-93408bb9-6d22-41e0-b0ce-62fddef7aeeb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194012823 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.194012823
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.3922142019
Short name T291
Test name
Test status
Simulation time 3334634226 ps
CPU time 76.27 seconds
Started Mar 28 12:38:43 PM PDT 24
Finished Mar 28 12:40:01 PM PDT 24
Peak memory 204916 kb
Host smart-69082aad-44d0-461f-967b-7fc079516275
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922142019 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.3922142019
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1655575841
Short name T330
Test name
Test status
Simulation time 3719946170 ps
CPU time 27.01 seconds
Started Mar 28 12:38:44 PM PDT 24
Finished Mar 28 12:39:11 PM PDT 24
Peak memory 204892 kb
Host smart-15c50ab8-587a-4fa6-b435-256250a9791c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655575841 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.1655575841
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.437694501
Short name T359
Test name
Test status
Simulation time 117583661 ps
CPU time 2.52 seconds
Started Mar 28 12:38:49 PM PDT 24
Finished Mar 28 12:38:53 PM PDT 24
Peak memory 212820 kb
Host smart-6e00f0f2-8fb6-4a4e-912b-3f36e06a4704
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437694501 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.437694501
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.2929934160
Short name T314
Test name
Test status
Simulation time 699611599 ps
CPU time 4.41 seconds
Started Mar 28 12:38:51 PM PDT 24
Finished Mar 28 12:38:56 PM PDT 24
Peak memory 218256 kb
Host smart-7f972a64-b036-4750-a4ab-d984b44b57a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929934160 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.2929934160
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.427397442
Short name T270
Test name
Test status
Simulation time 127093719 ps
CPU time 2.09 seconds
Started Mar 28 12:38:48 PM PDT 24
Finished Mar 28 12:38:51 PM PDT 24
Peak memory 213036 kb
Host smart-e48840ff-c0da-4e1d-a34d-45f3489f759c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427397442 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.427397442
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.4287169759
Short name T309
Test name
Test status
Simulation time 5279142397 ps
CPU time 20.67 seconds
Started Mar 28 12:38:55 PM PDT 24
Finished Mar 28 12:39:15 PM PDT 24
Peak memory 204756 kb
Host smart-ba72dd66-c52f-4b62-a6af-00120cfc7682
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287169759 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.4287169759
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1888017555
Short name T257
Test name
Test status
Simulation time 33731508092 ps
CPU time 53.44 seconds
Started Mar 28 12:38:41 PM PDT 24
Finished Mar 28 12:39:35 PM PDT 24
Peak memory 204708 kb
Host smart-aeec1fb0-0705-41e8-816d-8296df677f06
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888017555 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_bit_bash.1888017555
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.1518217346
Short name T96
Test name
Test status
Simulation time 701617586 ps
CPU time 2.08 seconds
Started Mar 28 12:38:43 PM PDT 24
Finished Mar 28 12:38:46 PM PDT 24
Peak memory 204832 kb
Host smart-0f74b414-034e-4c62-b42f-d851713c40f8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518217346 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.1518217346
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.2930283837
Short name T240
Test name
Test status
Simulation time 486420024 ps
CPU time 2.29 seconds
Started Mar 28 12:38:52 PM PDT 24
Finished Mar 28 12:38:54 PM PDT 24
Peak memory 204768 kb
Host smart-a6b75bc5-8d24-4f40-a993-40055bed1673
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930283837 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.2
930283837
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3250574318
Short name T335
Test name
Test status
Simulation time 161901400 ps
CPU time 0.76 seconds
Started Mar 28 12:38:49 PM PDT 24
Finished Mar 28 12:38:51 PM PDT 24
Peak memory 204548 kb
Host smart-653dc3cb-0683-46f6-be3b-71d10d6879ad
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250574318 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.3250574318
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.208929558
Short name T364
Test name
Test status
Simulation time 812563283 ps
CPU time 2.43 seconds
Started Mar 28 12:38:43 PM PDT 24
Finished Mar 28 12:38:45 PM PDT 24
Peak memory 204720 kb
Host smart-163b3b96-2e9c-4691-99fb-5e861b545fad
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208929558 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr
_bit_bash.208929558
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.747080147
Short name T246
Test name
Test status
Simulation time 68406520 ps
CPU time 0.89 seconds
Started Mar 28 12:38:51 PM PDT 24
Finished Mar 28 12:38:52 PM PDT 24
Peak memory 204636 kb
Host smart-a715d7b4-6655-4ddc-ac7a-f94ae579e38d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747080147 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr
_hw_reset.747080147
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.3452739050
Short name T293
Test name
Test status
Simulation time 92573829 ps
CPU time 0.77 seconds
Started Mar 28 12:38:52 PM PDT 24
Finished Mar 28 12:38:53 PM PDT 24
Peak memory 204488 kb
Host smart-4a2ee45e-7bcd-477e-a23b-1e567115c494
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452739050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.3
452739050
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.899836072
Short name T234
Test name
Test status
Simulation time 53122242 ps
CPU time 0.65 seconds
Started Mar 28 12:38:55 PM PDT 24
Finished Mar 28 12:38:56 PM PDT 24
Peak memory 204584 kb
Host smart-a976e6bf-53d2-45ff-9152-51d475dee713
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899836072 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_part
ial_access.899836072
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.3175541481
Short name T341
Test name
Test status
Simulation time 76995046 ps
CPU time 0.67 seconds
Started Mar 28 12:38:47 PM PDT 24
Finished Mar 28 12:38:49 PM PDT 24
Peak memory 204592 kb
Host smart-2bd5c2d3-9462-4e8e-9935-f321efcabb74
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175541481 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.3175541481
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.3468046694
Short name T342
Test name
Test status
Simulation time 837026161 ps
CPU time 4.02 seconds
Started Mar 28 12:38:46 PM PDT 24
Finished Mar 28 12:38:51 PM PDT 24
Peak memory 204896 kb
Host smart-88fe1349-b47b-47e2-8f44-33eb82696e35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468046694 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.3468046694
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.4179612000
Short name T285
Test name
Test status
Simulation time 5855428969 ps
CPU time 13.58 seconds
Started Mar 28 12:38:44 PM PDT 24
Finished Mar 28 12:38:58 PM PDT 24
Peak memory 217884 kb
Host smart-62c9ecd8-7813-4709-8c99-d1dec36a0560
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179612000 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.4179612000
Directory /workspace/3.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.478215102
Short name T303
Test name
Test status
Simulation time 464547399 ps
CPU time 5.41 seconds
Started Mar 28 12:38:50 PM PDT 24
Finished Mar 28 12:38:56 PM PDT 24
Peak memory 213120 kb
Host smart-ceb771dd-965a-4e60-9c13-e662e3e93c0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478215102 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.478215102
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.575112779
Short name T73
Test name
Test status
Simulation time 1145301972 ps
CPU time 9.47 seconds
Started Mar 28 12:38:48 PM PDT 24
Finished Mar 28 12:38:58 PM PDT 24
Peak memory 213092 kb
Host smart-a5a8c181-3f35-46c6-93f4-0deb852477e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575112779 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.575112779
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/31.rv_dm_tap_fsm_rand_reset.2902914465
Short name T290
Test name
Test status
Simulation time 6732221825 ps
CPU time 12.51 seconds
Started Mar 28 12:39:12 PM PDT 24
Finished Mar 28 12:39:26 PM PDT 24
Peak memory 219536 kb
Host smart-58cc5e94-b865-499b-b227-4b894500f494
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902914465 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 31.rv_dm_tap_fsm_rand_reset.2902914465
Directory /workspace/31.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/32.rv_dm_tap_fsm_rand_reset.1736365873
Short name T274
Test name
Test status
Simulation time 9605368949 ps
CPU time 17.95 seconds
Started Mar 28 12:39:19 PM PDT 24
Finished Mar 28 12:39:38 PM PDT 24
Peak memory 214748 kb
Host smart-466c1a29-939e-4cc6-b9bf-46af22400ea6
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736365873 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 32.rv_dm_tap_fsm_rand_reset.1736365873
Directory /workspace/32.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/33.rv_dm_tap_fsm_rand_reset.1334239317
Short name T345
Test name
Test status
Simulation time 6182642486 ps
CPU time 21.47 seconds
Started Mar 28 12:39:28 PM PDT 24
Finished Mar 28 12:39:49 PM PDT 24
Peak memory 213960 kb
Host smart-41d0f296-1be5-49a6-a8be-6c321350575f
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334239317 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 33.rv_dm_tap_fsm_rand_reset.1334239317
Directory /workspace/33.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/35.rv_dm_tap_fsm_rand_reset.1660885815
Short name T348
Test name
Test status
Simulation time 17191770546 ps
CPU time 15.51 seconds
Started Mar 28 12:39:19 PM PDT 24
Finished Mar 28 12:39:36 PM PDT 24
Peak memory 218252 kb
Host smart-ebf7e986-0c46-47b3-950c-871340510f45
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660885815 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 35.rv_dm_tap_fsm_rand_reset.1660885815
Directory /workspace/35.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.1435750263
Short name T365
Test name
Test status
Simulation time 2660569654 ps
CPU time 54.58 seconds
Started Mar 28 12:39:16 PM PDT 24
Finished Mar 28 12:40:12 PM PDT 24
Peak memory 204916 kb
Host smart-e329e5ac-bf0b-4f60-b8e2-774b08302304
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435750263 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.1435750263
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.1143999163
Short name T102
Test name
Test status
Simulation time 890662543 ps
CPU time 2.49 seconds
Started Mar 28 12:39:11 PM PDT 24
Finished Mar 28 12:39:14 PM PDT 24
Peak memory 212960 kb
Host smart-0af4bdc6-8427-43f1-89ac-4cd05e270980
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143999163 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.1143999163
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2289373537
Short name T321
Test name
Test status
Simulation time 208576077 ps
CPU time 2.25 seconds
Started Mar 28 12:39:10 PM PDT 24
Finished Mar 28 12:39:12 PM PDT 24
Peak memory 216888 kb
Host smart-751cac75-48a2-4d4d-a260-a51c106bf98d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289373537 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.2289373537
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.948351322
Short name T108
Test name
Test status
Simulation time 216945812 ps
CPU time 1.54 seconds
Started Mar 28 12:39:16 PM PDT 24
Finished Mar 28 12:39:18 PM PDT 24
Peak memory 218112 kb
Host smart-251bd516-0c99-46cb-9f3c-6cecfbec0384
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948351322 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.948351322
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.316227748
Short name T343
Test name
Test status
Simulation time 3597172831 ps
CPU time 6.74 seconds
Started Mar 28 12:39:13 PM PDT 24
Finished Mar 28 12:39:20 PM PDT 24
Peak memory 204824 kb
Host smart-9f4c9173-12be-43bf-bda9-2e6d806fae69
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316227748 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr
_aliasing.316227748
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.1961560039
Short name T237
Test name
Test status
Simulation time 9721990663 ps
CPU time 22.23 seconds
Started Mar 28 12:39:09 PM PDT 24
Finished Mar 28 12:39:32 PM PDT 24
Peak memory 204788 kb
Host smart-9952e814-8e76-4ccb-bae5-8680c6623372
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961560039 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_bit_bash.1961560039
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.3950644650
Short name T94
Test name
Test status
Simulation time 494110974 ps
CPU time 2.75 seconds
Started Mar 28 12:39:04 PM PDT 24
Finished Mar 28 12:39:07 PM PDT 24
Peak memory 204928 kb
Host smart-3c770152-5b47-42df-b331-8024cd403d1a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950644650 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.3950644650
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.1091794830
Short name T242
Test name
Test status
Simulation time 663287019 ps
CPU time 2.8 seconds
Started Mar 28 12:39:19 PM PDT 24
Finished Mar 28 12:39:23 PM PDT 24
Peak memory 204752 kb
Host smart-c7832add-872f-4173-a096-d851b428708d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091794830 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.1
091794830
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.256203415
Short name T254
Test name
Test status
Simulation time 423834118 ps
CPU time 1.11 seconds
Started Mar 28 12:39:14 PM PDT 24
Finished Mar 28 12:39:17 PM PDT 24
Peak memory 204504 kb
Host smart-30c4ff4e-2d70-42a4-8ee8-330483a2c8f8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256203415 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr
_aliasing.256203415
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2045653778
Short name T266
Test name
Test status
Simulation time 1063893529 ps
CPU time 3.5 seconds
Started Mar 28 12:39:11 PM PDT 24
Finished Mar 28 12:39:15 PM PDT 24
Peak memory 204708 kb
Host smart-ebe69b18-cabe-4e8a-b8ce-e09f43135dfe
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045653778 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.2045653778
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2506434472
Short name T253
Test name
Test status
Simulation time 32327398 ps
CPU time 0.73 seconds
Started Mar 28 12:39:16 PM PDT 24
Finished Mar 28 12:39:18 PM PDT 24
Peak memory 204648 kb
Host smart-cbcee3a1-fb3e-439c-a1cb-6241523391c3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506434472 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.2506434472
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.4183938284
Short name T297
Test name
Test status
Simulation time 153749403 ps
CPU time 0.89 seconds
Started Mar 28 12:39:16 PM PDT 24
Finished Mar 28 12:39:18 PM PDT 24
Peak memory 204588 kb
Host smart-594f0b80-376c-4ed7-be7d-a5b6d7ed768f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183938284 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.4
183938284
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1768842601
Short name T333
Test name
Test status
Simulation time 29244041 ps
CPU time 0.67 seconds
Started Mar 28 12:39:12 PM PDT 24
Finished Mar 28 12:39:14 PM PDT 24
Peak memory 204604 kb
Host smart-4af461ac-d7d3-4f0e-a266-2a3b4d11eb99
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768842601 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.1768842601
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.942669496
Short name T298
Test name
Test status
Simulation time 26859859 ps
CPU time 0.72 seconds
Started Mar 28 12:39:10 PM PDT 24
Finished Mar 28 12:39:11 PM PDT 24
Peak memory 204556 kb
Host smart-4e0b7b25-c02b-4eac-9e6c-56d5428ca01c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942669496 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.942669496
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.2448553867
Short name T87
Test name
Test status
Simulation time 76652779 ps
CPU time 3.38 seconds
Started Mar 28 12:39:11 PM PDT 24
Finished Mar 28 12:39:15 PM PDT 24
Peak memory 204916 kb
Host smart-6405951a-92a1-424e-8139-52bca90d160e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448553867 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.2448553867
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.3346927750
Short name T320
Test name
Test status
Simulation time 226339402 ps
CPU time 3.61 seconds
Started Mar 28 12:39:11 PM PDT 24
Finished Mar 28 12:39:15 PM PDT 24
Peak memory 213004 kb
Host smart-296a4652-c62b-408c-8c18-e2b56dbc6c36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346927750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.3346927750
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.2215955057
Short name T128
Test name
Test status
Simulation time 1245850587 ps
CPU time 9.77 seconds
Started Mar 28 12:39:15 PM PDT 24
Finished Mar 28 12:39:26 PM PDT 24
Peak memory 221276 kb
Host smart-6d819b13-aa4d-446c-be3c-ec39aac335f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215955057 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.2215955057
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.582341341
Short name T112
Test name
Test status
Simulation time 787098058 ps
CPU time 2.38 seconds
Started Mar 28 12:39:09 PM PDT 24
Finished Mar 28 12:39:12 PM PDT 24
Peak memory 213104 kb
Host smart-7c1bffbc-f78f-4fdc-aded-8f90599e6316
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582341341 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.582341341
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3144217642
Short name T243
Test name
Test status
Simulation time 1109807340 ps
CPU time 2.27 seconds
Started Mar 28 12:39:13 PM PDT 24
Finished Mar 28 12:39:17 PM PDT 24
Peak memory 204740 kb
Host smart-60203d0d-df2f-4813-976d-da033e2199e5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144217642 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.3
144217642
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.108437966
Short name T358
Test name
Test status
Simulation time 165303671 ps
CPU time 0.82 seconds
Started Mar 28 12:39:10 PM PDT 24
Finished Mar 28 12:39:11 PM PDT 24
Peak memory 204632 kb
Host smart-e7fab146-2acb-491a-bf98-39676ed73b68
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108437966 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.108437966
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.4085991284
Short name T118
Test name
Test status
Simulation time 2038266849 ps
CPU time 8.16 seconds
Started Mar 28 12:39:10 PM PDT 24
Finished Mar 28 12:39:19 PM PDT 24
Peak memory 204880 kb
Host smart-9e841df7-d0b9-402c-bf98-0961bba6da52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085991284 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.4085991284
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.1009009350
Short name T282
Test name
Test status
Simulation time 586063694 ps
CPU time 3.26 seconds
Started Mar 28 12:39:09 PM PDT 24
Finished Mar 28 12:39:13 PM PDT 24
Peak memory 213044 kb
Host smart-795a8c7b-938d-4210-985d-c2b6e548d19f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009009350 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.1009009350
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3971006789
Short name T135
Test name
Test status
Simulation time 1644592233 ps
CPU time 10.72 seconds
Started Mar 28 12:39:10 PM PDT 24
Finished Mar 28 12:39:21 PM PDT 24
Peak memory 213172 kb
Host smart-1104edd5-1fca-408d-8d97-46feade67af6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971006789 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.3971006789
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.108275357
Short name T277
Test name
Test status
Simulation time 292891539 ps
CPU time 3.83 seconds
Started Mar 28 12:39:19 PM PDT 24
Finished Mar 28 12:39:24 PM PDT 24
Peak memory 213140 kb
Host smart-e78be32a-b432-4e61-ad0e-46783145069f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108275357 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.108275357
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.2275828454
Short name T90
Test name
Test status
Simulation time 356962963 ps
CPU time 1.69 seconds
Started Mar 28 12:39:11 PM PDT 24
Finished Mar 28 12:39:13 PM PDT 24
Peak memory 213072 kb
Host smart-bc245e94-bf64-4c8d-895c-8e4ba194e195
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275828454 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.2275828454
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2496302609
Short name T323
Test name
Test status
Simulation time 685344459 ps
CPU time 2.16 seconds
Started Mar 28 12:39:14 PM PDT 24
Finished Mar 28 12:39:18 PM PDT 24
Peak memory 204640 kb
Host smart-40781f18-86fa-4e25-a4ad-5bbe06835cef
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496302609 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.2
496302609
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2687913275
Short name T313
Test name
Test status
Simulation time 181727104 ps
CPU time 0.73 seconds
Started Mar 28 12:39:19 PM PDT 24
Finished Mar 28 12:39:21 PM PDT 24
Peak memory 204372 kb
Host smart-bd047544-8dea-4edd-ac56-50a308519f1d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687913275 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.2
687913275
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.1486734307
Short name T107
Test name
Test status
Simulation time 330157870 ps
CPU time 4.23 seconds
Started Mar 28 12:39:14 PM PDT 24
Finished Mar 28 12:39:20 PM PDT 24
Peak memory 204952 kb
Host smart-a410b8fd-7bd4-4803-8263-e76fd82c9336
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486734307 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.1486734307
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.2862042687
Short name T267
Test name
Test status
Simulation time 508735805 ps
CPU time 4.05 seconds
Started Mar 28 12:39:17 PM PDT 24
Finished Mar 28 12:39:21 PM PDT 24
Peak memory 212868 kb
Host smart-edd50269-053a-4503-8570-c098384f2483
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862042687 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.2862042687
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.426726811
Short name T316
Test name
Test status
Simulation time 80361387 ps
CPU time 2.28 seconds
Started Mar 28 12:39:13 PM PDT 24
Finished Mar 28 12:39:18 PM PDT 24
Peak memory 220904 kb
Host smart-680b5a1b-e5b3-442c-b8b2-70b844da6809
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426726811 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.426726811
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.38139463
Short name T114
Test name
Test status
Simulation time 324236618 ps
CPU time 2.42 seconds
Started Mar 28 12:39:13 PM PDT 24
Finished Mar 28 12:39:17 PM PDT 24
Peak memory 213092 kb
Host smart-b4bce57a-c219-4400-a985-3965d100eff1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38139463 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.38139463
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2813064732
Short name T334
Test name
Test status
Simulation time 487290114 ps
CPU time 1.37 seconds
Started Mar 28 12:39:16 PM PDT 24
Finished Mar 28 12:39:18 PM PDT 24
Peak memory 204604 kb
Host smart-86964e90-b758-473f-a85e-9dd0f6ba4772
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813064732 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.2
813064732
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.2310212441
Short name T63
Test name
Test status
Simulation time 177235163 ps
CPU time 0.68 seconds
Started Mar 28 12:39:10 PM PDT 24
Finished Mar 28 12:39:11 PM PDT 24
Peak memory 204552 kb
Host smart-4da8b33f-c072-470d-9818-c85736ce8306
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310212441 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.2
310212441
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.4009217233
Short name T356
Test name
Test status
Simulation time 369118839 ps
CPU time 3.54 seconds
Started Mar 28 12:39:10 PM PDT 24
Finished Mar 28 12:39:13 PM PDT 24
Peak memory 204720 kb
Host smart-3c828c78-abcd-473b-88e5-d834e34a01fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009217233 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.4009217233
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.638700548
Short name T256
Test name
Test status
Simulation time 958281137 ps
CPU time 5.24 seconds
Started Mar 28 12:39:15 PM PDT 24
Finished Mar 28 12:39:21 PM PDT 24
Peak memory 213076 kb
Host smart-92eb7cda-89e4-4c1b-8421-7a8e69a1aaa1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638700548 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.638700548
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2902837495
Short name T296
Test name
Test status
Simulation time 2277456303 ps
CPU time 7.17 seconds
Started Mar 28 12:39:17 PM PDT 24
Finished Mar 28 12:39:24 PM PDT 24
Peak memory 217904 kb
Host smart-1e35a061-3769-46c5-b6a6-93551964d19d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902837495 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.2902837495
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.3298625053
Short name T109
Test name
Test status
Simulation time 110319268 ps
CPU time 1.49 seconds
Started Mar 28 12:39:13 PM PDT 24
Finished Mar 28 12:39:16 PM PDT 24
Peak memory 213032 kb
Host smart-c6d6f27c-6126-4c7b-a357-63a9e6c96af0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298625053 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.3298625053
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1280578817
Short name T340
Test name
Test status
Simulation time 301555321 ps
CPU time 1.55 seconds
Started Mar 28 12:39:17 PM PDT 24
Finished Mar 28 12:39:19 PM PDT 24
Peak memory 204740 kb
Host smart-12e3c60f-b843-47ce-be25-cd0e22f31494
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280578817 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.1
280578817
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3728628653
Short name T289
Test name
Test status
Simulation time 90477909 ps
CPU time 0.78 seconds
Started Mar 28 12:39:19 PM PDT 24
Finished Mar 28 12:39:21 PM PDT 24
Peak memory 204568 kb
Host smart-3296bb69-1aad-41d2-a0d4-de7ccbfcab1f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728628653 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.3
728628653
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.3094024667
Short name T354
Test name
Test status
Simulation time 296997372 ps
CPU time 3.72 seconds
Started Mar 28 12:39:14 PM PDT 24
Finished Mar 28 12:39:19 PM PDT 24
Peak memory 204912 kb
Host smart-8246e62a-8bec-4ce6-8de1-e9cc7bdc3d6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094024667 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_
csr_outstanding.3094024667
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.414446197
Short name T60
Test name
Test status
Simulation time 29941647613 ps
CPU time 26.55 seconds
Started Mar 28 12:39:12 PM PDT 24
Finished Mar 28 12:39:39 PM PDT 24
Peak memory 229416 kb
Host smart-0110d1be-774b-46a5-b0b3-d91eb27e8011
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414446197 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.414446197
Directory /workspace/8.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.3029592246
Short name T347
Test name
Test status
Simulation time 256369758 ps
CPU time 4.94 seconds
Started Mar 28 12:39:10 PM PDT 24
Finished Mar 28 12:39:16 PM PDT 24
Peak memory 213072 kb
Host smart-3825f359-a688-436a-8866-0030de573bc3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029592246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.3029592246
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.4005086450
Short name T91
Test name
Test status
Simulation time 3106713722 ps
CPU time 18.69 seconds
Started Mar 28 12:39:16 PM PDT 24
Finished Mar 28 12:39:36 PM PDT 24
Peak memory 213196 kb
Host smart-cee2baf3-395f-44a3-91bd-054e0a4b7346
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005086450 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.4005086450
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.2438144155
Short name T336
Test name
Test status
Simulation time 2269740809 ps
CPU time 5.99 seconds
Started Mar 28 12:39:09 PM PDT 24
Finished Mar 28 12:39:16 PM PDT 24
Peak memory 219196 kb
Host smart-bbeceb0b-d530-405d-bea2-d7e909b7afc4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438144155 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.2438144155
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1649651690
Short name T116
Test name
Test status
Simulation time 193452693 ps
CPU time 1.6 seconds
Started Mar 28 12:39:15 PM PDT 24
Finished Mar 28 12:39:18 PM PDT 24
Peak memory 213020 kb
Host smart-cb37444e-e060-42b8-9a45-1949cdd8b436
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649651690 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.1649651690
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.2480594498
Short name T251
Test name
Test status
Simulation time 1213965488 ps
CPU time 2.96 seconds
Started Mar 28 12:39:19 PM PDT 24
Finished Mar 28 12:39:23 PM PDT 24
Peak memory 204800 kb
Host smart-1d4fb3f0-9335-40c2-aa67-9870468506c3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480594498 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.2
480594498
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1148936792
Short name T64
Test name
Test status
Simulation time 132000398 ps
CPU time 0.86 seconds
Started Mar 28 12:39:14 PM PDT 24
Finished Mar 28 12:39:17 PM PDT 24
Peak memory 204564 kb
Host smart-92304473-0456-4839-bca2-06e236141df5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148936792 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.1
148936792
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.438652533
Short name T83
Test name
Test status
Simulation time 274839456 ps
CPU time 4.04 seconds
Started Mar 28 12:39:14 PM PDT 24
Finished Mar 28 12:39:19 PM PDT 24
Peak memory 204852 kb
Host smart-5c332f56-c8da-46fb-a8c6-533f0373fa36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438652533 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_c
sr_outstanding.438652533
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.4194056591
Short name T317
Test name
Test status
Simulation time 111017544 ps
CPU time 3.07 seconds
Started Mar 28 12:39:10 PM PDT 24
Finished Mar 28 12:39:13 PM PDT 24
Peak memory 213180 kb
Host smart-54667b31-5114-4fa1-a3f3-e3fe19685d39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194056591 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.4194056591
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2541648533
Short name T122
Test name
Test status
Simulation time 547822606 ps
CPU time 10.45 seconds
Started Mar 28 12:39:15 PM PDT 24
Finished Mar 28 12:39:27 PM PDT 24
Peak memory 213072 kb
Host smart-3c72eb33-39d8-44db-9765-19d41d0d0b4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541648533 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.2541648533
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.1481410781
Short name T32
Test name
Test status
Simulation time 47128862 ps
CPU time 0.67 seconds
Started Mar 28 12:32:23 PM PDT 24
Finished Mar 28 12:32:25 PM PDT 24
Peak memory 204664 kb
Host smart-db036c4e-041c-4550-9017-db5a0f23270c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481410781 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.1481410781
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.1213495626
Short name T187
Test name
Test status
Simulation time 17734778378 ps
CPU time 44.14 seconds
Started Mar 28 12:32:37 PM PDT 24
Finished Mar 28 12:33:22 PM PDT 24
Peak memory 213276 kb
Host smart-9553d3ea-0722-481c-a433-2bbd0e4a30c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213495626 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.1213495626
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.490560466
Short name T224
Test name
Test status
Simulation time 4471425937 ps
CPU time 6.56 seconds
Started Mar 28 12:32:25 PM PDT 24
Finished Mar 28 12:32:33 PM PDT 24
Peak memory 205232 kb
Host smart-b846fe34-c62d-4adb-91c0-eab1f17a212d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490560466 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.490560466
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.657528659
Short name T12
Test name
Test status
Simulation time 2657008020 ps
CPU time 8.09 seconds
Started Mar 28 12:32:17 PM PDT 24
Finished Mar 28 12:32:29 PM PDT 24
Peak memory 204896 kb
Host smart-190aeba5-6ee7-4a27-a695-b5d50b7fcd10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657528659 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.657528659
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.3432806196
Short name T51
Test name
Test status
Simulation time 172961420 ps
CPU time 0.97 seconds
Started Mar 28 12:32:28 PM PDT 24
Finished Mar 28 12:32:29 PM PDT 24
Peak memory 204536 kb
Host smart-3ce24807-8389-47bf-aaa5-9c19cb8317f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432806196 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.3432806196
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.1433309615
Short name T26
Test name
Test status
Simulation time 2445065477 ps
CPU time 2.58 seconds
Started Mar 28 12:32:26 PM PDT 24
Finished Mar 28 12:32:30 PM PDT 24
Peak memory 204916 kb
Host smart-9101b313-20c6-4779-8e10-5ead72e518c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433309615 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.1433309615
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.445304559
Short name T28
Test name
Test status
Simulation time 37406069 ps
CPU time 0.72 seconds
Started Mar 28 12:32:25 PM PDT 24
Finished Mar 28 12:32:28 PM PDT 24
Peak memory 204648 kb
Host smart-acfa3ddd-41c6-429c-9209-64646391ce71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445304559 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.445304559
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.789108064
Short name T216
Test name
Test status
Simulation time 4094594589 ps
CPU time 7.7 seconds
Started Mar 28 12:32:27 PM PDT 24
Finished Mar 28 12:32:35 PM PDT 24
Peak memory 213272 kb
Host smart-ca9aa231-9cf4-4bd5-b212-63a1079dde71
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=789108064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_tl
_access.789108064
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.1727588097
Short name T182
Test name
Test status
Simulation time 165597855 ps
CPU time 0.9 seconds
Started Mar 28 12:32:24 PM PDT 24
Finished Mar 28 12:32:26 PM PDT 24
Peak memory 204520 kb
Host smart-4f32eca5-905b-4371-90dd-a02fde1f18ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727588097 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.1727588097
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.3577065049
Short name T18
Test name
Test status
Simulation time 276842669 ps
CPU time 1.17 seconds
Started Mar 28 12:32:29 PM PDT 24
Finished Mar 28 12:32:31 PM PDT 24
Peak memory 204768 kb
Host smart-1f96de0a-755e-4b90-bccb-c7493a8c785c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577065049 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.3577065049
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.1817560902
Short name T206
Test name
Test status
Simulation time 161091313 ps
CPU time 0.9 seconds
Started Mar 28 12:32:24 PM PDT 24
Finished Mar 28 12:32:27 PM PDT 24
Peak memory 204512 kb
Host smart-a9388da3-deae-438c-bdf6-d1b1403ef992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817560902 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.1817560902
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.3652527708
Short name T59
Test name
Test status
Simulation time 290906837 ps
CPU time 1.15 seconds
Started Mar 28 12:32:24 PM PDT 24
Finished Mar 28 12:32:26 PM PDT 24
Peak memory 204524 kb
Host smart-14f478c1-916e-481f-8beb-fdea8779d431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652527708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.3652527708
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.330934290
Short name T62
Test name
Test status
Simulation time 68801900 ps
CPU time 0.72 seconds
Started Mar 28 12:32:26 PM PDT 24
Finished Mar 28 12:32:28 PM PDT 24
Peak memory 204516 kb
Host smart-7577fb98-1c16-4883-acf9-6c8c513d1576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330934290 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.330934290
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.180191742
Short name T225
Test name
Test status
Simulation time 61860450 ps
CPU time 0.84 seconds
Started Mar 28 12:32:27 PM PDT 24
Finished Mar 28 12:32:28 PM PDT 24
Peak memory 204652 kb
Host smart-36ac8a21-35f0-4802-b9b5-651608af1dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180191742 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.180191742
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.1872317486
Short name T142
Test name
Test status
Simulation time 79686169 ps
CPU time 0.74 seconds
Started Mar 28 12:32:48 PM PDT 24
Finished Mar 28 12:32:49 PM PDT 24
Peak memory 204688 kb
Host smart-1dd234f8-8b29-4b66-8a1c-1043eb4569c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872317486 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.1872317486
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.2024520772
Short name T20
Test name
Test status
Simulation time 1733723728 ps
CPU time 1.82 seconds
Started Mar 28 12:32:28 PM PDT 24
Finished Mar 28 12:32:30 PM PDT 24
Peak memory 204988 kb
Host smart-fbb9e8bc-3df4-4f9e-bdbf-3f93ce5ca329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024520772 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.2024520772
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.2874950152
Short name T50
Test name
Test status
Simulation time 145726784 ps
CPU time 1.06 seconds
Started Mar 28 12:32:33 PM PDT 24
Finished Mar 28 12:32:35 PM PDT 24
Peak memory 229092 kb
Host smart-f4907e51-6672-4379-a82d-7be35610b9bd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874950152 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.2874950152
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.3483886563
Short name T9
Test name
Test status
Simulation time 739420117 ps
CPU time 1.33 seconds
Started Mar 28 12:32:26 PM PDT 24
Finished Mar 28 12:32:28 PM PDT 24
Peak memory 204404 kb
Host smart-bc87160f-b569-4108-bb98-dd8d656d9eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483886563 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.3483886563
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.3895412392
Short name T151
Test name
Test status
Simulation time 20577945 ps
CPU time 0.73 seconds
Started Mar 28 12:32:26 PM PDT 24
Finished Mar 28 12:32:28 PM PDT 24
Peak memory 204656 kb
Host smart-67b99383-88e9-49e4-889f-114f2832a635
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895412392 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.3895412392
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.524271550
Short name T180
Test name
Test status
Simulation time 808308731 ps
CPU time 2.1 seconds
Started Mar 28 12:32:26 PM PDT 24
Finished Mar 28 12:32:29 PM PDT 24
Peak memory 204944 kb
Host smart-cb047401-3f9d-4dcf-9a65-d1668af4ceae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524271550 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.524271550
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.2173304623
Short name T7
Test name
Test status
Simulation time 343930612 ps
CPU time 1.37 seconds
Started Mar 28 12:32:23 PM PDT 24
Finished Mar 28 12:32:26 PM PDT 24
Peak memory 204664 kb
Host smart-96486227-a4e4-4baa-90c9-bfae6f4b0102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173304623 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.2173304623
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.4259555335
Short name T141
Test name
Test status
Simulation time 32322982 ps
CPU time 0.74 seconds
Started Mar 28 12:32:28 PM PDT 24
Finished Mar 28 12:32:29 PM PDT 24
Peak memory 204664 kb
Host smart-eb13d4da-c5b8-4ff0-a9d4-43fb01a348bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259555335 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.4259555335
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.2797711732
Short name T193
Test name
Test status
Simulation time 8895019090 ps
CPU time 26.02 seconds
Started Mar 28 12:32:35 PM PDT 24
Finished Mar 28 12:33:01 PM PDT 24
Peak memory 205060 kb
Host smart-5112d1f1-1565-4610-b084-ff658b25d8e8
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2797711732 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.2797711732
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.399023183
Short name T17
Test name
Test status
Simulation time 516973409 ps
CPU time 1.54 seconds
Started Mar 28 12:32:29 PM PDT 24
Finished Mar 28 12:32:30 PM PDT 24
Peak memory 204908 kb
Host smart-2c78d294-3581-410a-8d4a-ee91eef686b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399023183 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.399023183
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.667470871
Short name T220
Test name
Test status
Simulation time 36148822 ps
CPU time 0.72 seconds
Started Mar 28 12:32:24 PM PDT 24
Finished Mar 28 12:32:26 PM PDT 24
Peak memory 204540 kb
Host smart-e6e32506-174b-40fb-8e11-95b2a806bb29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667470871 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.667470871
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.3615095679
Short name T36
Test name
Test status
Simulation time 548513479 ps
CPU time 1.71 seconds
Started Mar 28 12:32:25 PM PDT 24
Finished Mar 28 12:32:29 PM PDT 24
Peak memory 204536 kb
Host smart-a9ae6b67-148e-421d-8f48-531e3c4ecac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615095679 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.3615095679
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.455033514
Short name T195
Test name
Test status
Simulation time 147522168 ps
CPU time 1.07 seconds
Started Mar 28 12:32:32 PM PDT 24
Finished Mar 28 12:32:33 PM PDT 24
Peak memory 204464 kb
Host smart-53db4b58-0cc1-4bbe-a252-b35df46b1f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455033514 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.455033514
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.4165833358
Short name T19
Test name
Test status
Simulation time 292296443 ps
CPU time 1.26 seconds
Started Mar 28 12:32:25 PM PDT 24
Finished Mar 28 12:32:28 PM PDT 24
Peak memory 204392 kb
Host smart-df7f4529-2104-4695-ba34-49b8cde02a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165833358 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.4165833358
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.2220849911
Short name T1
Test name
Test status
Simulation time 54284523 ps
CPU time 0.69 seconds
Started Mar 28 12:32:39 PM PDT 24
Finished Mar 28 12:32:39 PM PDT 24
Peak memory 204488 kb
Host smart-eab516d3-abbc-4007-a4ec-d0011526744c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220849911 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.2220849911
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.2501822842
Short name T71
Test name
Test status
Simulation time 38723746 ps
CPU time 0.78 seconds
Started Mar 28 12:32:25 PM PDT 24
Finished Mar 28 12:32:31 PM PDT 24
Peak memory 204648 kb
Host smart-0d2045a0-b5ff-4152-8e02-3521ff3206b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501822842 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.2501822842
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.1301270689
Short name T52
Test name
Test status
Simulation time 583422458 ps
CPU time 2.08 seconds
Started Mar 28 12:32:28 PM PDT 24
Finished Mar 28 12:32:30 PM PDT 24
Peak memory 204852 kb
Host smart-a44cb11e-ddb8-4af1-845a-f7713d8e486f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301270689 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.1301270689
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.2269919734
Short name T21
Test name
Test status
Simulation time 220922444 ps
CPU time 1.48 seconds
Started Mar 28 12:32:27 PM PDT 24
Finished Mar 28 12:32:29 PM PDT 24
Peak memory 204868 kb
Host smart-017e935c-ec4a-45c1-8d07-b56a02f7fb0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269919734 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.2269919734
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.2039000252
Short name T14
Test name
Test status
Simulation time 444560650 ps
CPU time 1.95 seconds
Started Mar 28 12:32:23 PM PDT 24
Finished Mar 28 12:32:27 PM PDT 24
Peak memory 204648 kb
Host smart-e28e8f38-64f4-4a56-b676-b2abeb8506ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039000252 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.2039000252
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.2603952717
Short name T57
Test name
Test status
Simulation time 33781125 ps
CPU time 0.83 seconds
Started Mar 28 12:32:26 PM PDT 24
Finished Mar 28 12:32:28 PM PDT 24
Peak memory 204172 kb
Host smart-9cad2454-91ce-4341-bc5d-c77e51141c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603952717 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.2603952717
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.4173293353
Short name T37
Test name
Test status
Simulation time 74974961 ps
CPU time 0.8 seconds
Started Mar 28 12:32:26 PM PDT 24
Finished Mar 28 12:32:28 PM PDT 24
Peak memory 212952 kb
Host smart-56a84b98-b191-4255-b35d-c1946fbfe311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173293353 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.4173293353
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.3048772285
Short name T49
Test name
Test status
Simulation time 98457472 ps
CPU time 1.18 seconds
Started Mar 28 12:32:27 PM PDT 24
Finished Mar 28 12:32:29 PM PDT 24
Peak memory 229352 kb
Host smart-e37a3dfc-f808-4d72-a32f-f27b59250481
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048772285 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.3048772285
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.1705642077
Short name T178
Test name
Test status
Simulation time 126144908 ps
CPU time 1.04 seconds
Started Mar 28 12:32:25 PM PDT 24
Finished Mar 28 12:32:28 PM PDT 24
Peak memory 204548 kb
Host smart-c6c27a04-2646-4104-9a53-3826053f84dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705642077 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.1705642077
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.2723954676
Short name T158
Test name
Test status
Simulation time 35709952 ps
CPU time 0.71 seconds
Started Mar 28 12:33:05 PM PDT 24
Finished Mar 28 12:33:05 PM PDT 24
Peak memory 204644 kb
Host smart-4e2b122d-e9a5-4463-b0af-f14b435000eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723954676 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.2723954676
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.1949934791
Short name T23
Test name
Test status
Simulation time 2689552283 ps
CPU time 2.84 seconds
Started Mar 28 12:32:48 PM PDT 24
Finished Mar 28 12:32:56 PM PDT 24
Peak memory 205032 kb
Host smart-d8a0527d-7e4c-4fcd-9478-f8cf997c2b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949934791 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.1949934791
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.359331845
Short name T204
Test name
Test status
Simulation time 5638370607 ps
CPU time 11.85 seconds
Started Mar 28 12:32:58 PM PDT 24
Finished Mar 28 12:33:10 PM PDT 24
Peak memory 205068 kb
Host smart-cabcfb4a-a203-425f-8c78-d93d19ec8ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359331845 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.359331845
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.2422224785
Short name T197
Test name
Test status
Simulation time 1015188383 ps
CPU time 3.23 seconds
Started Mar 28 12:32:59 PM PDT 24
Finished Mar 28 12:33:03 PM PDT 24
Peak memory 204984 kb
Host smart-006dc1ac-d188-4c9f-8f44-02c52dde2330
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2422224785 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.2422224785
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.3157238219
Short name T230
Test name
Test status
Simulation time 3667718046 ps
CPU time 4.91 seconds
Started Mar 28 12:33:03 PM PDT 24
Finished Mar 28 12:33:09 PM PDT 24
Peak memory 205028 kb
Host smart-d775f4e4-2287-4f9c-a28f-9b659739c3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157238219 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.3157238219
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.1568743320
Short name T153
Test name
Test status
Simulation time 30893249 ps
CPU time 0.77 seconds
Started Mar 28 12:32:53 PM PDT 24
Finished Mar 28 12:32:54 PM PDT 24
Peak memory 204668 kb
Host smart-633f54c1-d365-4919-abcd-2ce5d7fd636b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568743320 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.1568743320
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.2792687528
Short name T189
Test name
Test status
Simulation time 4038386628 ps
CPU time 5.57 seconds
Started Mar 28 12:33:03 PM PDT 24
Finished Mar 28 12:33:09 PM PDT 24
Peak memory 204996 kb
Host smart-08c6d9d0-3241-44b2-88a2-dbefad97d7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792687528 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.2792687528
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.4246293014
Short name T45
Test name
Test status
Simulation time 842674734 ps
CPU time 2.84 seconds
Started Mar 28 12:32:54 PM PDT 24
Finished Mar 28 12:32:57 PM PDT 24
Peak memory 204984 kb
Host smart-0d5ba9f7-4456-45ff-8165-9bf69d9afa8f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4246293014 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_
tl_access.4246293014
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.1887839971
Short name T181
Test name
Test status
Simulation time 6278910967 ps
CPU time 19.75 seconds
Started Mar 28 12:32:56 PM PDT 24
Finished Mar 28 12:33:16 PM PDT 24
Peak memory 213288 kb
Host smart-6471ffe9-5d9b-4847-96e7-871cc9743580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887839971 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.1887839971
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.2822816836
Short name T35
Test name
Test status
Simulation time 21813735 ps
CPU time 0.7 seconds
Started Mar 28 12:33:01 PM PDT 24
Finished Mar 28 12:33:02 PM PDT 24
Peak memory 204648 kb
Host smart-72f34257-4ed6-42c3-b0e3-7b1634d29085
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822816836 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.2822816836
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.25855150
Short name T15
Test name
Test status
Simulation time 804866705 ps
CPU time 4.7 seconds
Started Mar 28 12:32:49 PM PDT 24
Finished Mar 28 12:32:58 PM PDT 24
Peak memory 204996 kb
Host smart-c43b03ce-66ec-43ad-8e30-2ab384054e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25855150 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.25855150
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.1223704624
Short name T2
Test name
Test status
Simulation time 5161772064 ps
CPU time 11.34 seconds
Started Mar 28 12:33:04 PM PDT 24
Finished Mar 28 12:33:15 PM PDT 24
Peak memory 214412 kb
Host smart-75de219e-d2b6-47dd-8d13-c4b36ec6f22b
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1223704624 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.1223704624
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.782850160
Short name T185
Test name
Test status
Simulation time 2635964800 ps
CPU time 7.73 seconds
Started Mar 28 12:32:58 PM PDT 24
Finished Mar 28 12:33:06 PM PDT 24
Peak memory 213228 kb
Host smart-938625df-da6e-4283-9787-825c1c1df9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782850160 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.782850160
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.3309407066
Short name T69
Test name
Test status
Simulation time 93872157 ps
CPU time 0.72 seconds
Started Mar 28 12:33:07 PM PDT 24
Finished Mar 28 12:33:08 PM PDT 24
Peak memory 204640 kb
Host smart-5df5a1d2-01cb-4bdb-b429-e34ba739d018
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309407066 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.3309407066
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.1041590509
Short name T186
Test name
Test status
Simulation time 2201970910 ps
CPU time 5.09 seconds
Started Mar 28 12:32:53 PM PDT 24
Finished Mar 28 12:32:59 PM PDT 24
Peak memory 205068 kb
Host smart-1a785ad3-d031-4ae6-9833-6faf1c001d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041590509 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.1041590509
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.2722889353
Short name T232
Test name
Test status
Simulation time 2615723698 ps
CPU time 7.04 seconds
Started Mar 28 12:33:09 PM PDT 24
Finished Mar 28 12:33:16 PM PDT 24
Peak memory 213232 kb
Host smart-7deb2721-8a9b-4b1e-b61e-3b6826a502ca
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2722889353 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_
tl_access.2722889353
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.1737104064
Short name T174
Test name
Test status
Simulation time 7075940752 ps
CPU time 25.3 seconds
Started Mar 28 12:33:13 PM PDT 24
Finished Mar 28 12:33:39 PM PDT 24
Peak memory 213312 kb
Host smart-6a7e167b-ff7d-4f80-996b-ea566439691c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737104064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.1737104064
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.4029958020
Short name T219
Test name
Test status
Simulation time 65432352 ps
CPU time 0.69 seconds
Started Mar 28 12:33:12 PM PDT 24
Finished Mar 28 12:33:14 PM PDT 24
Peak memory 204660 kb
Host smart-0c256851-3cc0-4501-9f18-56357eb390b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029958020 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.4029958020
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.3581014700
Short name T213
Test name
Test status
Simulation time 10790088549 ps
CPU time 26.74 seconds
Started Mar 28 12:33:05 PM PDT 24
Finished Mar 28 12:33:31 PM PDT 24
Peak memory 213220 kb
Host smart-20cbf932-8f83-4738-9583-3b463fa3f18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581014700 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.3581014700
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.3794715767
Short name T202
Test name
Test status
Simulation time 5907048691 ps
CPU time 20.81 seconds
Started Mar 28 12:33:09 PM PDT 24
Finished Mar 28 12:33:34 PM PDT 24
Peak memory 215372 kb
Host smart-1a0a2187-b607-475e-8410-5eb94f233964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794715767 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.3794715767
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.1018929678
Short name T184
Test name
Test status
Simulation time 6985306362 ps
CPU time 16.1 seconds
Started Mar 28 12:32:59 PM PDT 24
Finished Mar 28 12:33:15 PM PDT 24
Peak memory 213276 kb
Host smart-76e2393d-5b3a-46d2-a4be-5b8c2fb30b2f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1018929678 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.1018929678
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.3218224163
Short name T173
Test name
Test status
Simulation time 1503548154 ps
CPU time 3.82 seconds
Started Mar 28 12:33:09 PM PDT 24
Finished Mar 28 12:33:17 PM PDT 24
Peak memory 205008 kb
Host smart-5f1381f8-5010-4e2f-95cc-1c68f510d261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218224163 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.3218224163
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.3382814003
Short name T166
Test name
Test status
Simulation time 56529126 ps
CPU time 0.7 seconds
Started Mar 28 12:33:03 PM PDT 24
Finished Mar 28 12:33:04 PM PDT 24
Peak memory 204648 kb
Host smart-48b9154b-dae3-4a5b-87a5-6d90f349944c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382814003 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.3382814003
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.545349408
Short name T209
Test name
Test status
Simulation time 1214542783 ps
CPU time 2.81 seconds
Started Mar 28 12:33:08 PM PDT 24
Finished Mar 28 12:33:11 PM PDT 24
Peak memory 204956 kb
Host smart-e898f5c9-c777-4c87-9929-5014be235fe9
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=545349408 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_t
l_access.545349408
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.3236515378
Short name T218
Test name
Test status
Simulation time 50211692 ps
CPU time 0.68 seconds
Started Mar 28 12:32:52 PM PDT 24
Finished Mar 28 12:32:52 PM PDT 24
Peak memory 204604 kb
Host smart-e66eb38e-a7bb-4a2e-b179-384c5ed013e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236515378 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.3236515378
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.2150497858
Short name T25
Test name
Test status
Simulation time 14773954216 ps
CPU time 21.59 seconds
Started Mar 28 12:33:01 PM PDT 24
Finished Mar 28 12:33:23 PM PDT 24
Peak memory 213360 kb
Host smart-30fc1703-4555-4985-b1a6-b375ed772add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150497858 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.2150497858
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.1290916624
Short name T66
Test name
Test status
Simulation time 3637790837 ps
CPU time 6.5 seconds
Started Mar 28 12:32:55 PM PDT 24
Finished Mar 28 12:33:02 PM PDT 24
Peak memory 204920 kb
Host smart-42dd55e1-283c-4251-a842-082afc910835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290916624 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.1290916624
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.2916379748
Short name T226
Test name
Test status
Simulation time 882528640 ps
CPU time 2.47 seconds
Started Mar 28 12:33:03 PM PDT 24
Finished Mar 28 12:33:05 PM PDT 24
Peak memory 204964 kb
Host smart-86caa26d-3061-49c6-99f2-f3441c47700e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2916379748 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_
tl_access.2916379748
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.2845509520
Short name T38
Test name
Test status
Simulation time 6395367957 ps
CPU time 13.59 seconds
Started Mar 28 12:33:09 PM PDT 24
Finished Mar 28 12:33:26 PM PDT 24
Peak memory 205004 kb
Host smart-127afdad-d695-4b5e-ac65-cad3d7b145c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845509520 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.2845509520
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.1696949013
Short name T150
Test name
Test status
Simulation time 58134844 ps
CPU time 0.67 seconds
Started Mar 28 12:33:00 PM PDT 24
Finished Mar 28 12:33:01 PM PDT 24
Peak memory 204672 kb
Host smart-64464937-3149-45e4-8e2e-7b20b7bc8ccd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696949013 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.1696949013
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.3979126938
Short name T188
Test name
Test status
Simulation time 2284653446 ps
CPU time 6.66 seconds
Started Mar 28 12:32:59 PM PDT 24
Finished Mar 28 12:33:06 PM PDT 24
Peak memory 205096 kb
Host smart-93e80c19-1f24-4e76-ae2e-7334000f0d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979126938 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.3979126938
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.4100272034
Short name T183
Test name
Test status
Simulation time 2118267006 ps
CPU time 3.93 seconds
Started Mar 28 12:32:58 PM PDT 24
Finished Mar 28 12:33:02 PM PDT 24
Peak memory 204996 kb
Host smart-b4c21ccc-fdb1-4a00-9f4c-10ed9c0ca0e7
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4100272034 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_
tl_access.4100272034
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.2841408
Short name T34
Test name
Test status
Simulation time 4409452200 ps
CPU time 4.15 seconds
Started Mar 28 12:33:05 PM PDT 24
Finished Mar 28 12:33:09 PM PDT 24
Peak memory 205072 kb
Host smart-7c4988c8-0a8c-4e1c-b896-7626a2465fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841408 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.2841408
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.1796557467
Short name T145
Test name
Test status
Simulation time 32937189 ps
CPU time 0.73 seconds
Started Mar 28 12:32:57 PM PDT 24
Finished Mar 28 12:32:57 PM PDT 24
Peak memory 204668 kb
Host smart-16848757-e877-4d5b-a136-87514ddbebad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796557467 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.1796557467
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.1219340798
Short name T211
Test name
Test status
Simulation time 18873979858 ps
CPU time 34.26 seconds
Started Mar 28 12:32:58 PM PDT 24
Finished Mar 28 12:33:33 PM PDT 24
Peak memory 213276 kb
Host smart-57de3d10-1638-48fa-a6e8-68210a77a051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219340798 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.1219340798
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.1625847539
Short name T222
Test name
Test status
Simulation time 677123735 ps
CPU time 2.84 seconds
Started Mar 28 12:32:51 PM PDT 24
Finished Mar 28 12:32:54 PM PDT 24
Peak memory 204948 kb
Host smart-a4464f79-2b66-4764-9bfb-1919975c12ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625847539 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.1625847539
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.18258251
Short name T205
Test name
Test status
Simulation time 4798043465 ps
CPU time 16.54 seconds
Started Mar 28 12:32:53 PM PDT 24
Finished Mar 28 12:33:09 PM PDT 24
Peak memory 213288 kb
Host smart-381b7a81-9110-4951-9614-d4884462dc05
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=18258251 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_tl
_access.18258251
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.1560095137
Short name T196
Test name
Test status
Simulation time 803024633 ps
CPU time 2.39 seconds
Started Mar 28 12:33:14 PM PDT 24
Finished Mar 28 12:33:22 PM PDT 24
Peak memory 205004 kb
Host smart-f8672332-fc16-4992-b64c-19c1abf901c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560095137 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.1560095137
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.3668601355
Short name T208
Test name
Test status
Simulation time 20266207 ps
CPU time 0.7 seconds
Started Mar 28 12:32:59 PM PDT 24
Finished Mar 28 12:33:00 PM PDT 24
Peak memory 204656 kb
Host smart-1d906b58-e148-463c-9c32-0277b4a505ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668601355 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.3668601355
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.3104448984
Short name T16
Test name
Test status
Simulation time 1130649009 ps
CPU time 2.94 seconds
Started Mar 28 12:32:44 PM PDT 24
Finished Mar 28 12:32:47 PM PDT 24
Peak memory 204968 kb
Host smart-78957f66-eb80-4d10-af6f-97acfb966e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104448984 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.3104448984
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.2674697734
Short name T48
Test name
Test status
Simulation time 2355858114 ps
CPU time 5.77 seconds
Started Mar 28 12:32:55 PM PDT 24
Finished Mar 28 12:33:01 PM PDT 24
Peak memory 204964 kb
Host smart-9bd59b2b-d03a-4f95-a8d5-b5aa0e561a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674697734 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.2674697734
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.294032298
Short name T159
Test name
Test status
Simulation time 17944554 ps
CPU time 0.72 seconds
Started Mar 28 12:32:28 PM PDT 24
Finished Mar 28 12:32:29 PM PDT 24
Peak memory 204768 kb
Host smart-2280f8e6-146f-4728-8f42-a3d3a938a155
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294032298 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.294032298
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.3114454772
Short name T221
Test name
Test status
Simulation time 7277925699 ps
CPU time 8.94 seconds
Started Mar 28 12:32:28 PM PDT 24
Finished Mar 28 12:32:37 PM PDT 24
Peak memory 213324 kb
Host smart-28af903e-1923-4312-9784-769be4ec1984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114454772 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.3114454772
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.511238708
Short name T203
Test name
Test status
Simulation time 1265078031 ps
CPU time 4.54 seconds
Started Mar 28 12:32:28 PM PDT 24
Finished Mar 28 12:32:32 PM PDT 24
Peak memory 204988 kb
Host smart-6b5b0e1e-2247-43d2-9c36-4bc1a74e3f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511238708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.511238708
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.1676362910
Short name T198
Test name
Test status
Simulation time 7587150717 ps
CPU time 14.28 seconds
Started Mar 28 12:32:26 PM PDT 24
Finished Mar 28 12:32:41 PM PDT 24
Peak memory 213260 kb
Host smart-0f27b6dd-8abe-4cbe-a657-d8ac0f73d394
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1676362910 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.1676362910
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.851971174
Short name T47
Test name
Test status
Simulation time 136858452 ps
CPU time 0.74 seconds
Started Mar 28 12:32:28 PM PDT 24
Finished Mar 28 12:32:29 PM PDT 24
Peak memory 204632 kb
Host smart-0b1bac4c-1288-4279-819d-2b1abb5e9819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851971174 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.851971174
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.3662647192
Short name T191
Test name
Test status
Simulation time 1407834888 ps
CPU time 3.9 seconds
Started Mar 28 12:32:24 PM PDT 24
Finished Mar 28 12:32:29 PM PDT 24
Peak memory 204852 kb
Host smart-e1e6b8d1-32b0-454f-9061-1d14e3e5295e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662647192 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.3662647192
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.722971694
Short name T170
Test name
Test status
Simulation time 20055067 ps
CPU time 0.72 seconds
Started Mar 28 12:32:47 PM PDT 24
Finished Mar 28 12:32:47 PM PDT 24
Peak memory 204664 kb
Host smart-4452c022-2415-4b57-9ce8-1ff7be343756
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722971694 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.722971694
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.136236024
Short name T152
Test name
Test status
Simulation time 49083882 ps
CPU time 0.73 seconds
Started Mar 28 12:32:54 PM PDT 24
Finished Mar 28 12:32:55 PM PDT 24
Peak memory 204664 kb
Host smart-b3005999-bece-49ca-9175-3d090ea62d6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136236024 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.136236024
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.348994710
Short name T149
Test name
Test status
Simulation time 52171589 ps
CPU time 0.69 seconds
Started Mar 28 12:33:03 PM PDT 24
Finished Mar 28 12:33:04 PM PDT 24
Peak memory 204612 kb
Host smart-3c35438a-4c62-4e8a-b2f8-64f53eae7a98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348994710 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.348994710
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_stress_all.2797479661
Short name T54
Test name
Test status
Simulation time 1958051100 ps
CPU time 5.84 seconds
Started Mar 28 12:32:58 PM PDT 24
Finished Mar 28 12:33:04 PM PDT 24
Peak memory 204832 kb
Host smart-5824f9aa-e0cf-457a-9c2e-7dcb7b675de2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797479661 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.2797479661
Directory /workspace/22.rv_dm_stress_all/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.3115536361
Short name T157
Test name
Test status
Simulation time 87948723 ps
CPU time 0.69 seconds
Started Mar 28 12:32:57 PM PDT 24
Finished Mar 28 12:32:58 PM PDT 24
Peak memory 204612 kb
Host smart-ff653e26-52ad-4859-89d2-b3c2e00c4a9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115536361 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.3115536361
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.2702861397
Short name T168
Test name
Test status
Simulation time 37756244 ps
CPU time 0.75 seconds
Started Mar 28 12:33:03 PM PDT 24
Finished Mar 28 12:33:04 PM PDT 24
Peak memory 204664 kb
Host smart-63876059-4581-447d-a716-14cad55c3196
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702861397 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.2702861397
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.3204488444
Short name T223
Test name
Test status
Simulation time 21692095 ps
CPU time 0.72 seconds
Started Mar 28 12:33:06 PM PDT 24
Finished Mar 28 12:33:08 PM PDT 24
Peak memory 204648 kb
Host smart-6aed0837-54ab-4c80-9041-50148edc0433
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204488444 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.3204488444
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.2093238965
Short name T146
Test name
Test status
Simulation time 27285338 ps
CPU time 0.69 seconds
Started Mar 28 12:32:56 PM PDT 24
Finished Mar 28 12:32:56 PM PDT 24
Peak memory 204644 kb
Host smart-227a40bf-0c66-4b12-bc62-f144e899f51d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093238965 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.2093238965
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.3467202243
Short name T126
Test name
Test status
Simulation time 47662852 ps
CPU time 0.77 seconds
Started Mar 28 12:33:09 PM PDT 24
Finished Mar 28 12:33:14 PM PDT 24
Peak memory 204660 kb
Host smart-4a3cbafc-31c4-47d8-8bba-4d30008c467d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467202243 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.3467202243
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.57013998
Short name T215
Test name
Test status
Simulation time 32536080 ps
CPU time 0.72 seconds
Started Mar 28 12:33:06 PM PDT 24
Finished Mar 28 12:33:08 PM PDT 24
Peak memory 204632 kb
Host smart-ac6f50d0-fc3b-40e6-809f-16ecccfb44a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57013998 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.57013998
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.2636404612
Short name T80
Test name
Test status
Simulation time 19371792 ps
CPU time 0.74 seconds
Started Mar 28 12:32:59 PM PDT 24
Finished Mar 28 12:33:00 PM PDT 24
Peak memory 204672 kb
Host smart-f72e1e5f-51d0-4b5b-be88-8988de98ff16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636404612 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.2636404612
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.122160232
Short name T43
Test name
Test status
Simulation time 53785199 ps
CPU time 0.66 seconds
Started Mar 28 12:33:02 PM PDT 24
Finished Mar 28 12:33:03 PM PDT 24
Peak memory 204664 kb
Host smart-8d8bc49d-3333-4779-877c-7f8b972f0be2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122160232 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.122160232
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.739423036
Short name T217
Test name
Test status
Simulation time 2788029114 ps
CPU time 7.79 seconds
Started Mar 28 12:32:26 PM PDT 24
Finished Mar 28 12:32:35 PM PDT 24
Peak memory 205032 kb
Host smart-14ea6b00-2724-4aea-9fa3-49d83bdf22c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739423036 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.739423036
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.4172110678
Short name T207
Test name
Test status
Simulation time 8890851721 ps
CPU time 12.99 seconds
Started Mar 28 12:32:25 PM PDT 24
Finished Mar 28 12:32:40 PM PDT 24
Peak memory 214328 kb
Host smart-bc5d2fd2-ffbc-4c71-aea4-dba9c681de3f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4172110678 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.4172110678
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.2529708709
Short name T199
Test name
Test status
Simulation time 33828824 ps
CPU time 0.74 seconds
Started Mar 28 12:32:49 PM PDT 24
Finished Mar 28 12:32:50 PM PDT 24
Peak memory 204492 kb
Host smart-6a69c1f8-c27c-4e3c-8e55-5a47660595ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529708709 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.2529708709
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.4252422969
Short name T227
Test name
Test status
Simulation time 15470012604 ps
CPU time 52.5 seconds
Started Mar 28 12:32:27 PM PDT 24
Finished Mar 28 12:33:20 PM PDT 24
Peak memory 213380 kb
Host smart-4ad03724-91ab-4e9b-9ae4-52994e816f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252422969 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.4252422969
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.3607995045
Short name T30
Test name
Test status
Simulation time 376708324 ps
CPU time 1.28 seconds
Started Mar 28 12:32:52 PM PDT 24
Finished Mar 28 12:32:54 PM PDT 24
Peak memory 229064 kb
Host smart-8d46e1e5-a8a9-45ed-86d8-bfc8f658b588
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607995045 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.3607995045
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.3637664582
Short name T147
Test name
Test status
Simulation time 18726354 ps
CPU time 0.71 seconds
Started Mar 28 12:32:58 PM PDT 24
Finished Mar 28 12:32:58 PM PDT 24
Peak memory 204604 kb
Host smart-91beec65-830e-4c8e-abad-483ed3c69391
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637664582 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.3637664582
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.1242710373
Short name T233
Test name
Test status
Simulation time 47159057 ps
CPU time 0.71 seconds
Started Mar 28 12:32:57 PM PDT 24
Finished Mar 28 12:32:58 PM PDT 24
Peak memory 204616 kb
Host smart-4b86e0e8-7f92-42b6-879d-4e316f80f3d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242710373 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.1242710373
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.1479437629
Short name T70
Test name
Test status
Simulation time 57658048 ps
CPU time 0.7 seconds
Started Mar 28 12:32:53 PM PDT 24
Finished Mar 28 12:32:54 PM PDT 24
Peak memory 204668 kb
Host smart-c41d1369-8192-43de-acaf-4503411a0a99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479437629 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.1479437629
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.1498972781
Short name T172
Test name
Test status
Simulation time 15829577 ps
CPU time 0.68 seconds
Started Mar 28 12:32:56 PM PDT 24
Finished Mar 28 12:32:57 PM PDT 24
Peak memory 204660 kb
Host smart-884b8a95-6bda-489d-bb2d-5731ca503555
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498972781 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.1498972781
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.170630358
Short name T165
Test name
Test status
Simulation time 19497502 ps
CPU time 0.72 seconds
Started Mar 28 12:33:09 PM PDT 24
Finished Mar 28 12:33:14 PM PDT 24
Peak memory 204672 kb
Host smart-b9c32a22-93f8-4e3a-9024-84d43eb7bc08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170630358 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.170630358
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_stress_all.1802540956
Short name T140
Test name
Test status
Simulation time 1102511204 ps
CPU time 4.6 seconds
Started Mar 28 12:33:14 PM PDT 24
Finished Mar 28 12:33:24 PM PDT 24
Peak memory 204896 kb
Host smart-de62671f-e7ea-4254-93c5-c25cbf1e6050
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802540956 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.1802540956
Directory /workspace/34.rv_dm_stress_all/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.3612063261
Short name T68
Test name
Test status
Simulation time 27499721 ps
CPU time 0.71 seconds
Started Mar 28 12:33:04 PM PDT 24
Finished Mar 28 12:33:05 PM PDT 24
Peak memory 204684 kb
Host smart-e66396ed-0860-46f7-ac96-b8dad6173ffc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612063261 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.3612063261
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.485136470
Short name T162
Test name
Test status
Simulation time 30143494 ps
CPU time 0.67 seconds
Started Mar 28 12:33:01 PM PDT 24
Finished Mar 28 12:33:02 PM PDT 24
Peak memory 204744 kb
Host smart-2b2452af-209d-4cee-a345-210e4009c13a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485136470 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.485136470
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.2192116357
Short name T160
Test name
Test status
Simulation time 49882988 ps
CPU time 0.75 seconds
Started Mar 28 12:32:48 PM PDT 24
Finished Mar 28 12:32:49 PM PDT 24
Peak memory 204628 kb
Host smart-04830a0d-e4d0-44bd-b741-75a44a424f03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192116357 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.2192116357
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.1497138722
Short name T163
Test name
Test status
Simulation time 32751219 ps
CPU time 0.73 seconds
Started Mar 28 12:32:50 PM PDT 24
Finished Mar 28 12:32:51 PM PDT 24
Peak memory 204748 kb
Host smart-a1006864-7cc7-402c-8e14-51d1b5c63c9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497138722 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.1497138722
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_stress_all.2025060358
Short name T5
Test name
Test status
Simulation time 2655721711 ps
CPU time 9.73 seconds
Started Mar 28 12:33:03 PM PDT 24
Finished Mar 28 12:33:13 PM PDT 24
Peak memory 205004 kb
Host smart-901b9357-7386-42e3-b193-6f7fd2a84b37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025060358 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.2025060358
Directory /workspace/38.rv_dm_stress_all/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.2894175408
Short name T212
Test name
Test status
Simulation time 27469735 ps
CPU time 0.76 seconds
Started Mar 28 12:32:54 PM PDT 24
Finished Mar 28 12:32:55 PM PDT 24
Peak memory 204648 kb
Host smart-c5b7c680-1974-494e-9316-5d3dd2e0e5d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894175408 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.2894175408
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.3589561698
Short name T148
Test name
Test status
Simulation time 29641843 ps
CPU time 0.68 seconds
Started Mar 28 12:32:40 PM PDT 24
Finished Mar 28 12:32:41 PM PDT 24
Peak memory 204768 kb
Host smart-1b221e8d-a062-4321-b8bd-2906a8a36a45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589561698 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.3589561698
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.1168166919
Short name T124
Test name
Test status
Simulation time 25922131362 ps
CPU time 50.8 seconds
Started Mar 28 12:33:02 PM PDT 24
Finished Mar 28 12:33:53 PM PDT 24
Peak memory 213328 kb
Host smart-4064f932-f914-42fa-86d0-684715f23708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168166919 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.1168166919
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.1973186909
Short name T125
Test name
Test status
Simulation time 4027927756 ps
CPU time 6.87 seconds
Started Mar 28 12:32:57 PM PDT 24
Finished Mar 28 12:33:04 PM PDT 24
Peak memory 213208 kb
Host smart-32cfe6c6-9df9-4445-9ea9-48566175d1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973186909 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.1973186909
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.2821577164
Short name T214
Test name
Test status
Simulation time 4476804854 ps
CPU time 10.34 seconds
Started Mar 28 12:32:45 PM PDT 24
Finished Mar 28 12:32:55 PM PDT 24
Peak memory 205196 kb
Host smart-1c2e5ba6-b2f7-43bb-b5b1-cc145cfc3632
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2821577164 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.2821577164
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.1268523345
Short name T175
Test name
Test status
Simulation time 30099883 ps
CPU time 0.73 seconds
Started Mar 28 12:32:52 PM PDT 24
Finished Mar 28 12:32:53 PM PDT 24
Peak memory 204496 kb
Host smart-19d2456c-d291-4dad-bb9e-6a4ab772345b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268523345 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.1268523345
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.579734354
Short name T190
Test name
Test status
Simulation time 1916152058 ps
CPU time 6.62 seconds
Started Mar 28 12:32:39 PM PDT 24
Finished Mar 28 12:32:45 PM PDT 24
Peak memory 204952 kb
Host smart-3781ae57-459c-42b5-944f-a0f64cb68f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579734354 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.579734354
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.757893421
Short name T29
Test name
Test status
Simulation time 89131052 ps
CPU time 1.01 seconds
Started Mar 28 12:33:13 PM PDT 24
Finished Mar 28 12:33:14 PM PDT 24
Peak memory 229080 kb
Host smart-8843edf7-fbb9-416f-bd0c-4e283cefc45e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757893421 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.757893421
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.2327724962
Short name T164
Test name
Test status
Simulation time 28300973 ps
CPU time 0.7 seconds
Started Mar 28 12:33:00 PM PDT 24
Finished Mar 28 12:33:02 PM PDT 24
Peak memory 204776 kb
Host smart-df490c8b-d361-4a78-9ee4-aadf98b8d23b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327724962 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.2327724962
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.2338196190
Short name T143
Test name
Test status
Simulation time 30720732 ps
CPU time 0.71 seconds
Started Mar 28 12:33:03 PM PDT 24
Finished Mar 28 12:33:04 PM PDT 24
Peak memory 204644 kb
Host smart-61013ed1-d712-450b-b479-0fe232c96ecf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338196190 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.2338196190
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.915949422
Short name T44
Test name
Test status
Simulation time 41839788 ps
CPU time 0.72 seconds
Started Mar 28 12:33:08 PM PDT 24
Finished Mar 28 12:33:09 PM PDT 24
Peak memory 204660 kb
Host smart-01308abb-2018-4a88-be50-cc9214c72927
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915949422 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.915949422
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.2567099998
Short name T67
Test name
Test status
Simulation time 49141061 ps
CPU time 0.69 seconds
Started Mar 28 12:33:06 PM PDT 24
Finished Mar 28 12:33:07 PM PDT 24
Peak memory 204660 kb
Host smart-98fd167f-95f4-42ec-98c3-40ec07525a52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567099998 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.2567099998
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.437874812
Short name T161
Test name
Test status
Simulation time 32358519 ps
CPU time 0.72 seconds
Started Mar 28 12:33:05 PM PDT 24
Finished Mar 28 12:33:06 PM PDT 24
Peak memory 204660 kb
Host smart-14dec094-5cfc-48c5-bc7f-15abb5ecbcde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437874812 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.437874812
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.3639971495
Short name T155
Test name
Test status
Simulation time 26975867 ps
CPU time 0.73 seconds
Started Mar 28 12:33:13 PM PDT 24
Finished Mar 28 12:33:14 PM PDT 24
Peak memory 204464 kb
Host smart-8a11aaf3-c8d7-42df-96d3-9064329383d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639971495 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.3639971495
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.3366793111
Short name T169
Test name
Test status
Simulation time 35983249 ps
CPU time 0.73 seconds
Started Mar 28 12:33:22 PM PDT 24
Finished Mar 28 12:33:23 PM PDT 24
Peak memory 204684 kb
Host smart-32ce786e-54d9-460c-9218-228a5c5bc80d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366793111 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.3366793111
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.351019140
Short name T144
Test name
Test status
Simulation time 113419185 ps
CPU time 0.76 seconds
Started Mar 28 12:33:10 PM PDT 24
Finished Mar 28 12:33:14 PM PDT 24
Peak memory 204608 kb
Host smart-ac0442b9-277f-4133-9dfc-4b9a23f1b4ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351019140 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.351019140
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.342272361
Short name T167
Test name
Test status
Simulation time 28924608 ps
CPU time 0.67 seconds
Started Mar 28 12:33:07 PM PDT 24
Finished Mar 28 12:33:08 PM PDT 24
Peak memory 204636 kb
Host smart-832ee611-c725-4c8c-a78a-320b53a24cd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342272361 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.342272361
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.3157248427
Short name T121
Test name
Test status
Simulation time 39572918 ps
CPU time 0.65 seconds
Started Mar 28 12:33:05 PM PDT 24
Finished Mar 28 12:33:05 PM PDT 24
Peak memory 204704 kb
Host smart-37603f7a-4227-47e4-9cf2-f801975181e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157248427 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.3157248427
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.852079107
Short name T33
Test name
Test status
Simulation time 46247809 ps
CPU time 0.71 seconds
Started Mar 28 12:32:43 PM PDT 24
Finished Mar 28 12:32:44 PM PDT 24
Peak memory 204656 kb
Host smart-bfa88687-9b6f-4baf-9b45-90bd37bff30c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852079107 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.852079107
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.2080520622
Short name T210
Test name
Test status
Simulation time 29071091721 ps
CPU time 92.52 seconds
Started Mar 28 12:32:59 PM PDT 24
Finished Mar 28 12:34:32 PM PDT 24
Peak memory 221504 kb
Host smart-c6c50ede-64c8-4082-85ad-1edc38aa013c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080520622 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.2080520622
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.625658983
Short name T201
Test name
Test status
Simulation time 7802077404 ps
CPU time 18.88 seconds
Started Mar 28 12:32:43 PM PDT 24
Finished Mar 28 12:33:02 PM PDT 24
Peak memory 205072 kb
Host smart-3507ce6d-3f99-4c39-a889-5be0bd43866f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625658983 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.625658983
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.3153517992
Short name T154
Test name
Test status
Simulation time 23547238 ps
CPU time 0.7 seconds
Started Mar 28 12:33:06 PM PDT 24
Finished Mar 28 12:33:07 PM PDT 24
Peak memory 204668 kb
Host smart-52014c4f-574f-40ed-a83b-f82389229c98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153517992 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.3153517992
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.430166085
Short name T24
Test name
Test status
Simulation time 32169812011 ps
CPU time 53.63 seconds
Started Mar 28 12:33:02 PM PDT 24
Finished Mar 28 12:33:56 PM PDT 24
Peak memory 213288 kb
Host smart-977e048a-be41-4650-a952-a7b6c9e2c294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430166085 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.430166085
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.1047264486
Short name T179
Test name
Test status
Simulation time 4065507474 ps
CPU time 15.47 seconds
Started Mar 28 12:33:00 PM PDT 24
Finished Mar 28 12:33:15 PM PDT 24
Peak memory 205196 kb
Host smart-5a1956f9-1cc4-462d-8ff5-fd55050472cb
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1047264486 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t
l_access.1047264486
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.2635483984
Short name T231
Test name
Test status
Simulation time 1571992760 ps
CPU time 4.85 seconds
Started Mar 28 12:32:52 PM PDT 24
Finished Mar 28 12:32:57 PM PDT 24
Peak memory 205008 kb
Host smart-d4544fe9-fa0a-4adc-bc6f-c40b61d10b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635483984 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.2635483984
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.1186369823
Short name T200
Test name
Test status
Simulation time 7307793626 ps
CPU time 12.14 seconds
Started Mar 28 12:32:58 PM PDT 24
Finished Mar 28 12:33:10 PM PDT 24
Peak memory 205088 kb
Host smart-d0ea4238-4fc2-417d-8b8c-8a64da0b2904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186369823 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.1186369823
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.3241578010
Short name T13
Test name
Test status
Simulation time 8104561412 ps
CPU time 28.09 seconds
Started Mar 28 12:32:53 PM PDT 24
Finished Mar 28 12:33:21 PM PDT 24
Peak memory 205152 kb
Host smart-e208d17c-b54c-49e4-b495-a3a2a0ac27bb
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3241578010 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.3241578010
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.2696024434
Short name T228
Test name
Test status
Simulation time 15677901259 ps
CPU time 50.16 seconds
Started Mar 28 12:32:51 PM PDT 24
Finished Mar 28 12:33:42 PM PDT 24
Peak memory 213280 kb
Host smart-f4bf2185-9d3b-4610-b522-1f5a8487f2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696024434 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.2696024434
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.3876378768
Short name T156
Test name
Test status
Simulation time 19910393 ps
CPU time 0.71 seconds
Started Mar 28 12:33:03 PM PDT 24
Finished Mar 28 12:33:05 PM PDT 24
Peak memory 204580 kb
Host smart-0934c764-0f9f-457b-ad5c-b2c19b7de70a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876378768 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.3876378768
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.1310040042
Short name T123
Test name
Test status
Simulation time 6932944156 ps
CPU time 11.01 seconds
Started Mar 28 12:33:06 PM PDT 24
Finished Mar 28 12:33:18 PM PDT 24
Peak memory 213312 kb
Host smart-7bb89846-f2a1-4ed6-9abb-5ba3b01feaac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310040042 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.1310040042
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.3728719076
Short name T72
Test name
Test status
Simulation time 421545644 ps
CPU time 2.45 seconds
Started Mar 28 12:32:49 PM PDT 24
Finished Mar 28 12:32:51 PM PDT 24
Peak memory 204924 kb
Host smart-0f00871a-3e76-4148-9f28-eb88d91696f7
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3728719076 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t
l_access.3728719076
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.30154814
Short name T177
Test name
Test status
Simulation time 1139900674 ps
CPU time 1.08 seconds
Started Mar 28 12:32:59 PM PDT 24
Finished Mar 28 12:33:00 PM PDT 24
Peak memory 204948 kb
Host smart-a9e81075-a30a-4714-bf4f-7b52f1c046e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30154814 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.30154814
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.2867459756
Short name T171
Test name
Test status
Simulation time 19888450 ps
CPU time 0.69 seconds
Started Mar 28 12:33:07 PM PDT 24
Finished Mar 28 12:33:08 PM PDT 24
Peak memory 204580 kb
Host smart-5486e26c-2a57-4e84-b399-0bf29ad66ae4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867459756 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.2867459756
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.2001286302
Short name T229
Test name
Test status
Simulation time 49686757766 ps
CPU time 117.08 seconds
Started Mar 28 12:32:41 PM PDT 24
Finished Mar 28 12:34:38 PM PDT 24
Peak memory 213280 kb
Host smart-f30bd963-d02d-4ffe-9d72-a07a920741eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001286302 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.2001286302
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.3640932216
Short name T194
Test name
Test status
Simulation time 2864926614 ps
CPU time 9.34 seconds
Started Mar 28 12:32:35 PM PDT 24
Finished Mar 28 12:32:44 PM PDT 24
Peak memory 205024 kb
Host smart-6572aa64-2d39-46db-b2b4-53da92634796
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3640932216 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t
l_access.3640932216
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.2539795982
Short name T192
Test name
Test status
Simulation time 892665702 ps
CPU time 2.51 seconds
Started Mar 28 12:33:01 PM PDT 24
Finished Mar 28 12:33:04 PM PDT 24
Peak memory 204804 kb
Host smart-9e0a26ec-8e80-4180-9c23-f4914b30936f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539795982 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.2539795982
Directory /workspace/9.rv_dm_sba_tl_access/latest
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