Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
80.20 94.49 80.05 87.69 75.64 83.83 98.52 41.15


Total test records in report: 384
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T276 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.254308538 Mar 31 03:52:35 PM PDT 24 Mar 31 03:52:37 PM PDT 24 230137455 ps
T277 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2744380746 Mar 31 03:52:37 PM PDT 24 Mar 31 03:52:40 PM PDT 24 1524948846 ps
T278 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.3722206919 Mar 31 03:52:51 PM PDT 24 Mar 31 03:52:52 PM PDT 24 17880533 ps
T279 /workspace/coverage/cover_reg_top/23.rv_dm_tap_fsm_rand_reset.399136617 Mar 31 03:53:00 PM PDT 24 Mar 31 03:53:23 PM PDT 24 8000131651 ps
T280 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.2384687995 Mar 31 03:52:48 PM PDT 24 Mar 31 03:52:50 PM PDT 24 99535340 ps
T111 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.2796957484 Mar 31 03:52:55 PM PDT 24 Mar 31 03:52:57 PM PDT 24 140072300 ps
T135 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1166726559 Mar 31 03:53:02 PM PDT 24 Mar 31 03:53:19 PM PDT 24 663349100 ps
T281 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.202932789 Mar 31 03:53:07 PM PDT 24 Mar 31 03:53:07 PM PDT 24 78828512 ps
T282 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1233437155 Mar 31 03:52:55 PM PDT 24 Mar 31 03:53:03 PM PDT 24 3370058565 ps
T283 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.1519841826 Mar 31 03:52:59 PM PDT 24 Mar 31 03:53:02 PM PDT 24 66277028 ps
T284 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.789775939 Mar 31 03:53:01 PM PDT 24 Mar 31 03:53:03 PM PDT 24 278170984 ps
T285 /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.1448618789 Mar 31 03:52:37 PM PDT 24 Mar 31 03:52:47 PM PDT 24 5791021399 ps
T286 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.1502781264 Mar 31 03:52:44 PM PDT 24 Mar 31 03:52:46 PM PDT 24 545762807 ps
T287 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2553702677 Mar 31 03:53:09 PM PDT 24 Mar 31 03:53:11 PM PDT 24 69883777 ps
T112 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.97584751 Mar 31 03:52:35 PM PDT 24 Mar 31 03:53:42 PM PDT 24 5087849877 ps
T288 /workspace/coverage/cover_reg_top/17.rv_dm_tap_fsm_rand_reset.2045138298 Mar 31 03:52:55 PM PDT 24 Mar 31 03:53:18 PM PDT 24 6535203622 ps
T100 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.638030448 Mar 31 03:52:54 PM PDT 24 Mar 31 03:52:57 PM PDT 24 2600319451 ps
T289 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2929689317 Mar 31 03:52:32 PM PDT 24 Mar 31 03:52:32 PM PDT 24 18079141 ps
T290 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.4177752959 Mar 31 03:52:34 PM PDT 24 Mar 31 03:52:35 PM PDT 24 136595893 ps
T130 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2818702568 Mar 31 03:52:43 PM PDT 24 Mar 31 03:53:03 PM PDT 24 2079712034 ps
T291 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3821264529 Mar 31 03:53:24 PM PDT 24 Mar 31 03:53:27 PM PDT 24 492716622 ps
T131 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2970802013 Mar 31 03:52:53 PM PDT 24 Mar 31 03:53:08 PM PDT 24 1331915966 ps
T292 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.3471208008 Mar 31 03:52:48 PM PDT 24 Mar 31 03:52:53 PM PDT 24 1368358919 ps
T293 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.3180869144 Mar 31 03:52:58 PM PDT 24 Mar 31 03:53:06 PM PDT 24 389089192 ps
T115 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2184748138 Mar 31 03:52:51 PM PDT 24 Mar 31 03:53:47 PM PDT 24 14042078928 ps
T294 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.2861869564 Mar 31 03:53:08 PM PDT 24 Mar 31 03:53:09 PM PDT 24 119551038 ps
T295 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.4182054093 Mar 31 03:52:49 PM PDT 24 Mar 31 03:52:58 PM PDT 24 7366671994 ps
T296 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.3848824340 Mar 31 03:53:17 PM PDT 24 Mar 31 03:53:19 PM PDT 24 143600755 ps
T297 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2036635746 Mar 31 03:52:50 PM PDT 24 Mar 31 03:52:51 PM PDT 24 231764357 ps
T129 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.1905842402 Mar 31 03:52:37 PM PDT 24 Mar 31 03:52:42 PM PDT 24 209407670 ps
T298 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1306042724 Mar 31 03:52:38 PM PDT 24 Mar 31 03:52:43 PM PDT 24 3569338606 ps
T299 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2514040434 Mar 31 03:52:58 PM PDT 24 Mar 31 03:53:02 PM PDT 24 142214639 ps
T300 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.568455457 Mar 31 03:53:00 PM PDT 24 Mar 31 03:53:03 PM PDT 24 117453694 ps
T301 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2800872389 Mar 31 03:52:38 PM PDT 24 Mar 31 03:52:39 PM PDT 24 291072520 ps
T302 /workspace/coverage/cover_reg_top/20.rv_dm_tap_fsm_rand_reset.1565560067 Mar 31 03:53:06 PM PDT 24 Mar 31 03:53:19 PM PDT 24 7380537362 ps
T303 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1058812743 Mar 31 03:52:39 PM PDT 24 Mar 31 03:52:40 PM PDT 24 47638423 ps
T304 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.1382239008 Mar 31 03:52:46 PM PDT 24 Mar 31 03:52:47 PM PDT 24 32570133 ps
T305 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2739104082 Mar 31 03:52:49 PM PDT 24 Mar 31 03:52:53 PM PDT 24 1397582526 ps
T306 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.4201399439 Mar 31 03:53:11 PM PDT 24 Mar 31 03:53:13 PM PDT 24 36755173 ps
T307 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.2330062376 Mar 31 03:53:00 PM PDT 24 Mar 31 03:53:08 PM PDT 24 1457601328 ps
T308 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.2658244112 Mar 31 03:52:25 PM PDT 24 Mar 31 03:52:32 PM PDT 24 1953876808 ps
T136 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3213569051 Mar 31 03:52:32 PM PDT 24 Mar 31 03:52:52 PM PDT 24 2082898969 ps
T309 /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.2832111759 Mar 31 03:52:38 PM PDT 24 Mar 31 03:52:51 PM PDT 24 12950145307 ps
T134 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2045215813 Mar 31 03:52:51 PM PDT 24 Mar 31 03:52:59 PM PDT 24 772698682 ps
T310 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3671649131 Mar 31 03:52:27 PM PDT 24 Mar 31 03:52:55 PM PDT 24 700151577 ps
T311 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2064234736 Mar 31 03:52:30 PM PDT 24 Mar 31 03:52:31 PM PDT 24 76303826 ps
T312 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2179619693 Mar 31 03:53:06 PM PDT 24 Mar 31 03:53:07 PM PDT 24 45618726 ps
T313 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3836090118 Mar 31 03:52:37 PM PDT 24 Mar 31 03:52:40 PM PDT 24 110744758 ps
T314 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2697343728 Mar 31 03:52:43 PM PDT 24 Mar 31 03:52:46 PM PDT 24 1487391664 ps
T315 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.1586627586 Mar 31 03:53:02 PM PDT 24 Mar 31 03:53:07 PM PDT 24 579914776 ps
T316 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.685947368 Mar 31 03:52:52 PM PDT 24 Mar 31 03:52:54 PM PDT 24 64669589 ps
T116 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.2775018541 Mar 31 03:53:22 PM PDT 24 Mar 31 03:53:24 PM PDT 24 380047938 ps
T317 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.2729378214 Mar 31 03:52:36 PM PDT 24 Mar 31 03:52:37 PM PDT 24 69902955 ps
T318 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.4084049904 Mar 31 03:53:11 PM PDT 24 Mar 31 03:53:13 PM PDT 24 90893419 ps
T319 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.555508960 Mar 31 03:52:44 PM PDT 24 Mar 31 03:52:45 PM PDT 24 23433782 ps
T320 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.3641416008 Mar 31 03:52:44 PM PDT 24 Mar 31 03:52:47 PM PDT 24 165051093 ps
T321 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.1423003729 Mar 31 03:52:43 PM PDT 24 Mar 31 03:52:44 PM PDT 24 521099477 ps
T322 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2366077209 Mar 31 03:52:48 PM PDT 24 Mar 31 03:52:56 PM PDT 24 1089696326 ps
T323 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3401456934 Mar 31 03:52:57 PM PDT 24 Mar 31 03:52:58 PM PDT 24 28127891 ps
T132 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.1554944184 Mar 31 03:52:31 PM PDT 24 Mar 31 03:52:41 PM PDT 24 1012608908 ps
T324 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3830813389 Mar 31 03:52:38 PM PDT 24 Mar 31 03:52:39 PM PDT 24 294950189 ps
T325 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.280012796 Mar 31 03:52:28 PM PDT 24 Mar 31 03:52:45 PM PDT 24 4604050113 ps
T326 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.3919777305 Mar 31 03:52:38 PM PDT 24 Mar 31 03:53:04 PM PDT 24 7367624611 ps
T327 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.2427006498 Mar 31 03:52:38 PM PDT 24 Mar 31 03:52:58 PM PDT 24 9695427405 ps
T328 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1978840009 Mar 31 03:52:35 PM PDT 24 Mar 31 03:52:50 PM PDT 24 18178056015 ps
T101 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.680292944 Mar 31 03:52:30 PM PDT 24 Mar 31 03:52:32 PM PDT 24 1467854777 ps
T117 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.3845001218 Mar 31 03:52:37 PM PDT 24 Mar 31 03:53:33 PM PDT 24 2867525437 ps
T329 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.3639928947 Mar 31 03:52:30 PM PDT 24 Mar 31 03:52:48 PM PDT 24 11492287926 ps
T330 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.644198994 Mar 31 03:52:53 PM PDT 24 Mar 31 03:52:56 PM PDT 24 85613834 ps
T331 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.526124491 Mar 31 03:52:59 PM PDT 24 Mar 31 03:53:02 PM PDT 24 148644338 ps
T332 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.2961193869 Mar 31 03:53:04 PM PDT 24 Mar 31 03:53:07 PM PDT 24 348057206 ps
T333 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2713860767 Mar 31 03:52:28 PM PDT 24 Mar 31 03:52:29 PM PDT 24 95073497 ps
T334 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.658691729 Mar 31 03:53:08 PM PDT 24 Mar 31 03:53:10 PM PDT 24 729582926 ps
T335 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2044442607 Mar 31 03:53:04 PM PDT 24 Mar 31 03:53:06 PM PDT 24 132909460 ps
T336 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.380246274 Mar 31 03:52:37 PM PDT 24 Mar 31 03:53:49 PM PDT 24 12797526945 ps
T337 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.1681637459 Mar 31 03:52:44 PM PDT 24 Mar 31 03:52:47 PM PDT 24 1062921396 ps
T338 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.646492005 Mar 31 03:52:53 PM PDT 24 Mar 31 03:52:53 PM PDT 24 46945341 ps
T339 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.3967255041 Mar 31 03:52:51 PM PDT 24 Mar 31 03:52:54 PM PDT 24 113224011 ps
T340 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2565019147 Mar 31 03:53:00 PM PDT 24 Mar 31 03:53:01 PM PDT 24 93270798 ps
T341 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.1143665522 Mar 31 03:52:52 PM PDT 24 Mar 31 03:52:59 PM PDT 24 553511375 ps
T342 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1684657398 Mar 31 03:53:04 PM PDT 24 Mar 31 03:53:06 PM PDT 24 153565275 ps
T133 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.346542002 Mar 31 03:53:16 PM PDT 24 Mar 31 03:53:34 PM PDT 24 3402272537 ps
T140 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.88656827 Mar 31 03:52:35 PM PDT 24 Mar 31 03:52:55 PM PDT 24 1453250865 ps
T343 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3246745573 Mar 31 03:52:36 PM PDT 24 Mar 31 03:52:49 PM PDT 24 3223999701 ps
T344 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.2844928044 Mar 31 03:52:57 PM PDT 24 Mar 31 03:52:59 PM PDT 24 28653026 ps
T118 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.683266060 Mar 31 03:53:11 PM PDT 24 Mar 31 03:53:13 PM PDT 24 221791134 ps
T345 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.202014391 Mar 31 03:52:36 PM PDT 24 Mar 31 03:52:44 PM PDT 24 5582303324 ps
T138 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.2986710726 Mar 31 03:52:40 PM PDT 24 Mar 31 03:52:51 PM PDT 24 4699561997 ps
T346 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3731147303 Mar 31 03:53:01 PM PDT 24 Mar 31 03:53:05 PM PDT 24 80097419 ps
T347 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3511538092 Mar 31 03:52:39 PM PDT 24 Mar 31 03:52:40 PM PDT 24 59448588 ps
T348 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2759198760 Mar 31 03:52:59 PM PDT 24 Mar 31 03:53:01 PM PDT 24 270122940 ps
T137 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3825859783 Mar 31 03:52:53 PM PDT 24 Mar 31 03:53:03 PM PDT 24 2767348319 ps
T349 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.729243026 Mar 31 03:52:52 PM PDT 24 Mar 31 03:53:08 PM PDT 24 417638096 ps
T102 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.3008860600 Mar 31 03:52:34 PM PDT 24 Mar 31 03:52:39 PM PDT 24 1364677265 ps
T350 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.354655956 Mar 31 03:52:58 PM PDT 24 Mar 31 03:53:06 PM PDT 24 1027695793 ps
T351 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2401479400 Mar 31 03:52:39 PM PDT 24 Mar 31 03:52:41 PM PDT 24 133384163 ps
T352 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.3580079994 Mar 31 03:52:35 PM PDT 24 Mar 31 03:52:36 PM PDT 24 78567642 ps
T353 /workspace/coverage/cover_reg_top/26.rv_dm_tap_fsm_rand_reset.1361125767 Mar 31 03:52:56 PM PDT 24 Mar 31 03:53:11 PM PDT 24 8243718532 ps
T354 /workspace/coverage/cover_reg_top/14.rv_dm_tap_fsm_rand_reset.4060989362 Mar 31 03:53:03 PM PDT 24 Mar 31 03:53:19 PM PDT 24 8263895324 ps
T355 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.313666655 Mar 31 03:52:51 PM PDT 24 Mar 31 03:52:52 PM PDT 24 47208074 ps
T356 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3888059073 Mar 31 03:53:10 PM PDT 24 Mar 31 03:53:12 PM PDT 24 147253341 ps
T357 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.226396508 Mar 31 03:52:57 PM PDT 24 Mar 31 03:52:58 PM PDT 24 54084158 ps
T358 /workspace/coverage/cover_reg_top/13.rv_dm_tap_fsm_rand_reset.185371124 Mar 31 03:53:05 PM PDT 24 Mar 31 03:53:21 PM PDT 24 8561543401 ps
T359 /workspace/coverage/cover_reg_top/19.rv_dm_tap_fsm_rand_reset.2144119043 Mar 31 03:53:04 PM PDT 24 Mar 31 03:53:27 PM PDT 24 23508824025 ps
T139 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2919532988 Mar 31 03:52:42 PM PDT 24 Mar 31 03:53:01 PM PDT 24 2108899279 ps
T360 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.3735975309 Mar 31 03:52:34 PM PDT 24 Mar 31 03:52:38 PM PDT 24 69264570 ps
T361 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1502130708 Mar 31 03:52:33 PM PDT 24 Mar 31 03:52:34 PM PDT 24 479355354 ps
T362 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.3455520282 Mar 31 03:52:50 PM PDT 24 Mar 31 03:52:55 PM PDT 24 254626299 ps
T363 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.2072268807 Mar 31 03:53:07 PM PDT 24 Mar 31 03:53:08 PM PDT 24 69180693 ps
T364 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.3455404664 Mar 31 03:52:37 PM PDT 24 Mar 31 03:52:53 PM PDT 24 733015306 ps
T113 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.3335637520 Mar 31 03:53:03 PM PDT 24 Mar 31 03:53:06 PM PDT 24 366572452 ps
T365 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.1347527058 Mar 31 03:52:56 PM PDT 24 Mar 31 03:53:04 PM PDT 24 349158848 ps
T366 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.3702653037 Mar 31 03:52:55 PM PDT 24 Mar 31 03:52:58 PM PDT 24 86938795 ps
T71 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3565891137 Mar 31 03:52:35 PM PDT 24 Mar 31 03:52:40 PM PDT 24 4751035752 ps
T367 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1509436246 Mar 31 03:52:53 PM PDT 24 Mar 31 03:52:53 PM PDT 24 88388923 ps
T119 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.2364785351 Mar 31 03:52:54 PM PDT 24 Mar 31 03:53:01 PM PDT 24 178006865 ps
T368 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.1376376438 Mar 31 03:52:37 PM PDT 24 Mar 31 03:52:56 PM PDT 24 2509294066 ps
T369 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.4025160033 Mar 31 03:52:45 PM PDT 24 Mar 31 03:52:48 PM PDT 24 114621333 ps
T370 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1424038010 Mar 31 03:52:36 PM PDT 24 Mar 31 03:52:55 PM PDT 24 16629624777 ps
T371 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.3126326667 Mar 31 03:52:41 PM PDT 24 Mar 31 03:52:43 PM PDT 24 85678429 ps
T372 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.2018824829 Mar 31 03:52:35 PM PDT 24 Mar 31 03:52:36 PM PDT 24 81534077 ps
T373 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2549322297 Mar 31 03:53:16 PM PDT 24 Mar 31 03:53:22 PM PDT 24 158602111 ps
T374 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.1584084123 Mar 31 03:52:49 PM PDT 24 Mar 31 03:52:50 PM PDT 24 102425820 ps
T375 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.4025897960 Mar 31 03:52:55 PM PDT 24 Mar 31 03:52:55 PM PDT 24 36322797 ps
T376 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2799329808 Mar 31 03:53:06 PM PDT 24 Mar 31 03:53:10 PM PDT 24 274611119 ps
T377 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.3171171829 Mar 31 03:52:37 PM PDT 24 Mar 31 03:52:38 PM PDT 24 76861218 ps
T114 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2451873436 Mar 31 03:52:35 PM PDT 24 Mar 31 03:52:37 PM PDT 24 109599011 ps
T378 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.789533984 Mar 31 03:52:39 PM PDT 24 Mar 31 03:52:41 PM PDT 24 35222385 ps
T379 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.1814912570 Mar 31 03:53:01 PM PDT 24 Mar 31 03:53:02 PM PDT 24 44090650 ps
T380 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.4145883116 Mar 31 03:52:44 PM PDT 24 Mar 31 03:53:11 PM PDT 24 2952655951 ps
T381 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.2315746495 Mar 31 03:52:47 PM PDT 24 Mar 31 03:52:48 PM PDT 24 379118545 ps
T382 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3132838210 Mar 31 03:53:21 PM PDT 24 Mar 31 03:53:24 PM PDT 24 710981412 ps
T383 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.3350287472 Mar 31 03:53:08 PM PDT 24 Mar 31 03:53:38 PM PDT 24 11114483415 ps
T384 /workspace/coverage/cover_reg_top/33.rv_dm_tap_fsm_rand_reset.3753260883 Mar 31 03:53:06 PM PDT 24 Mar 31 03:53:22 PM PDT 24 12759197624 ps

Test location /workspace/coverage/default/4.rv_dm_stress_all.1258800885
Short name T2
Test name
Test status
Simulation time 1482902436 ps
CPU time 5.09 seconds
Started Mar 31 12:59:48 PM PDT 24
Finished Mar 31 12:59:53 PM PDT 24
Peak memory 204932 kb
Host smart-4ba26f50-3707-4250-8a3a-cdf0e6b46f73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258800885 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.1258800885
Directory /workspace/4.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.2403485085
Short name T49
Test name
Test status
Simulation time 20083890384 ps
CPU time 49.78 seconds
Started Mar 31 12:59:23 PM PDT 24
Finished Mar 31 01:00:13 PM PDT 24
Peak memory 215768 kb
Host smart-427bfde3-2d1f-4c5a-bbd1-4a33810b4e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403485085 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.2403485085
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3692172908
Short name T88
Test name
Test status
Simulation time 2485073594 ps
CPU time 63.46 seconds
Started Mar 31 03:52:29 PM PDT 24
Finished Mar 31 03:53:34 PM PDT 24
Peak memory 217604 kb
Host smart-86459ad9-af81-4104-b096-2c3254ae3799
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692172908 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.3692172908
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.3038941713
Short name T77
Test name
Test status
Simulation time 24545775 ps
CPU time 0.78 seconds
Started Mar 31 01:00:04 PM PDT 24
Finished Mar 31 01:00:05 PM PDT 24
Peak memory 204732 kb
Host smart-517148f0-52ee-423b-bf73-7eed5817369f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038941713 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.3038941713
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tap_fsm_rand_reset.1816642533
Short name T52
Test name
Test status
Simulation time 10473160470 ps
CPU time 39.56 seconds
Started Mar 31 03:52:48 PM PDT 24
Finished Mar 31 03:53:28 PM PDT 24
Peak memory 221424 kb
Host smart-5c539d93-1a1f-4a8a-8697-45a7e4059fc9
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816642533 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rv_dm_tap_fsm_rand_reset.1816642533
Directory /workspace/11.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/37.rv_dm_stress_all.3823462152
Short name T15
Test name
Test status
Simulation time 392811448 ps
CPU time 1.91 seconds
Started Mar 31 01:00:15 PM PDT 24
Finished Mar 31 01:00:17 PM PDT 24
Peak memory 204980 kb
Host smart-d5b16b28-c828-4a8d-9713-6e044c01461f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823462152 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.3823462152
Directory /workspace/37.rv_dm_stress_all/latest

Test location /workspace/coverage/default/6.rv_dm_stress_all.3348124665
Short name T45
Test name
Test status
Simulation time 4508060749 ps
CPU time 15.33 seconds
Started Mar 31 12:59:49 PM PDT 24
Finished Mar 31 01:00:05 PM PDT 24
Peak memory 205072 kb
Host smart-1372cab0-8816-4b0b-83cc-a6b6ce7a4317
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348124665 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.3348124665
Directory /workspace/6.rv_dm_stress_all/latest

Test location /workspace/coverage/default/26.rv_dm_stress_all.1721236600
Short name T141
Test name
Test status
Simulation time 5979719571 ps
CPU time 21.5 seconds
Started Mar 31 01:00:10 PM PDT 24
Finished Mar 31 01:00:32 PM PDT 24
Peak memory 205100 kb
Host smart-2c33cdf9-c1c6-40cd-b7e8-5708dbdb15a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721236600 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.1721236600
Directory /workspace/26.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.1560864572
Short name T84
Test name
Test status
Simulation time 1239516935 ps
CPU time 18.33 seconds
Started Mar 31 03:53:09 PM PDT 24
Finished Mar 31 03:53:28 PM PDT 24
Peak memory 213156 kb
Host smart-0f48a6d9-e22a-466b-9f88-006cdd03b4d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560864572 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.1
560864572
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.263739883
Short name T97
Test name
Test status
Simulation time 6442710010 ps
CPU time 15.73 seconds
Started Mar 31 12:59:22 PM PDT 24
Finished Mar 31 12:59:39 PM PDT 24
Peak memory 213472 kb
Host smart-da9d94d4-f9fc-49bf-90e5-11d1d5e3b233
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=263739883 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_tl
_access.263739883
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.910293999
Short name T44
Test name
Test status
Simulation time 413736303 ps
CPU time 1.08 seconds
Started Mar 31 12:59:39 PM PDT 24
Finished Mar 31 12:59:40 PM PDT 24
Peak memory 204612 kb
Host smart-95a2c2e4-8e20-4dab-a655-7ae41396a27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910293999 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.910293999
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.842610069
Short name T106
Test name
Test status
Simulation time 1903710534 ps
CPU time 30.88 seconds
Started Mar 31 03:52:38 PM PDT 24
Finished Mar 31 03:53:10 PM PDT 24
Peak memory 204960 kb
Host smart-0a1bf64d-8cde-4036-8505-aa50433f37ce
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842610069 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.rv_dm_csr_aliasing.842610069
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.2844865743
Short name T40
Test name
Test status
Simulation time 392310031 ps
CPU time 1.11 seconds
Started Mar 31 12:59:52 PM PDT 24
Finished Mar 31 12:59:54 PM PDT 24
Peak memory 236300 kb
Host smart-d6996119-c7c9-4115-a47a-f2a85a4321f7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844865743 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.2844865743
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.3194566580
Short name T11
Test name
Test status
Simulation time 603579801 ps
CPU time 1.32 seconds
Started Mar 31 12:59:30 PM PDT 24
Finished Mar 31 12:59:31 PM PDT 24
Peak memory 204804 kb
Host smart-08f9d990-a673-45f3-8921-cd409e3c5903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194566580 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.3194566580
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.2608453443
Short name T30
Test name
Test status
Simulation time 52819843 ps
CPU time 0.76 seconds
Started Mar 31 12:59:37 PM PDT 24
Finished Mar 31 12:59:38 PM PDT 24
Peak memory 213092 kb
Host smart-4542bddb-7db8-41d9-8088-5617f4bf80d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608453443 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.2608453443
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.346542002
Short name T133
Test name
Test status
Simulation time 3402272537 ps
CPU time 18.83 seconds
Started Mar 31 03:53:16 PM PDT 24
Finished Mar 31 03:53:34 PM PDT 24
Peak memory 221464 kb
Host smart-3f8ca63a-b70b-45e1-8576-0d6affa28d56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346542002 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.346542002
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.58574049
Short name T212
Test name
Test status
Simulation time 13319979251 ps
CPU time 49.81 seconds
Started Mar 31 12:59:58 PM PDT 24
Finished Mar 31 01:00:48 PM PDT 24
Peak memory 213372 kb
Host smart-8d39d004-2a21-4968-848f-c04ee2bb9b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58574049 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.58574049
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.1257109349
Short name T33
Test name
Test status
Simulation time 78118120 ps
CPU time 0.89 seconds
Started Mar 31 12:59:37 PM PDT 24
Finished Mar 31 12:59:38 PM PDT 24
Peak memory 204832 kb
Host smart-4b9a4fe9-b775-47c2-a06c-b4e0b053368e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257109349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.1257109349
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.2459619670
Short name T37
Test name
Test status
Simulation time 87033317 ps
CPU time 0.79 seconds
Started Mar 31 12:59:24 PM PDT 24
Finished Mar 31 12:59:25 PM PDT 24
Peak memory 204776 kb
Host smart-72745d7e-f6cd-4970-a040-102ab41a187e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459619670 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.2459619670
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3565891137
Short name T71
Test name
Test status
Simulation time 4751035752 ps
CPU time 4.23 seconds
Started Mar 31 03:52:35 PM PDT 24
Finished Mar 31 03:52:40 PM PDT 24
Peak memory 205048 kb
Host smart-4c9fb58c-1d50-46d4-b937-3d5d933ad6c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565891137 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.3565891137
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.1628588314
Short name T90
Test name
Test status
Simulation time 1079716361 ps
CPU time 7.82 seconds
Started Mar 31 03:53:02 PM PDT 24
Finished Mar 31 03:53:10 PM PDT 24
Peak memory 205032 kb
Host smart-c9d99c5d-57fb-44b1-916c-849265c92a09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628588314 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.1628588314
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.2070782649
Short name T81
Test name
Test status
Simulation time 1689991490 ps
CPU time 18.12 seconds
Started Mar 31 03:52:52 PM PDT 24
Finished Mar 31 03:53:10 PM PDT 24
Peak memory 213256 kb
Host smart-c25f0b42-b369-4e3b-8680-850f8ce9b154
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070782649 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.2
070782649
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.3068696144
Short name T73
Test name
Test status
Simulation time 3039599310 ps
CPU time 2.3 seconds
Started Mar 31 03:52:32 PM PDT 24
Finished Mar 31 03:52:34 PM PDT 24
Peak memory 204916 kb
Host smart-c229c74f-908b-4602-ae59-054674736e44
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068696144 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.3068696144
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.680292944
Short name T101
Test name
Test status
Simulation time 1467854777 ps
CPU time 2.23 seconds
Started Mar 31 03:52:30 PM PDT 24
Finished Mar 31 03:52:32 PM PDT 24
Peak memory 204936 kb
Host smart-5f4e2016-efca-4ca2-b982-9d71a0fffba7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680292944 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr
_hw_reset.680292944
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.2375736678
Short name T28
Test name
Test status
Simulation time 202330318 ps
CPU time 1.04 seconds
Started Mar 31 12:59:23 PM PDT 24
Finished Mar 31 12:59:24 PM PDT 24
Peak memory 204696 kb
Host smart-72cd16e6-6b33-439e-996d-622290189001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375736678 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.2375736678
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.3335637520
Short name T113
Test name
Test status
Simulation time 366572452 ps
CPU time 2.1 seconds
Started Mar 31 03:53:03 PM PDT 24
Finished Mar 31 03:53:06 PM PDT 24
Peak memory 213248 kb
Host smart-7cfdd2ec-0ea1-4cd9-815c-db838f59ab99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335637520 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.3335637520
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.1478488189
Short name T60
Test name
Test status
Simulation time 25218025 ps
CPU time 0.73 seconds
Started Mar 31 12:59:57 PM PDT 24
Finished Mar 31 12:59:58 PM PDT 24
Peak memory 204820 kb
Host smart-bc45e7ac-d9d3-4b3d-a86a-fc34f7321a2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478488189 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.1478488189
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.3368368446
Short name T94
Test name
Test status
Simulation time 240984403 ps
CPU time 6.21 seconds
Started Mar 31 03:52:32 PM PDT 24
Finished Mar 31 03:52:38 PM PDT 24
Peak memory 213204 kb
Host smart-294c86b5-0703-4a1f-a0eb-7199c3b42a35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368368446 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.3368368446
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2970802013
Short name T131
Test name
Test status
Simulation time 1331915966 ps
CPU time 15.17 seconds
Started Mar 31 03:52:53 PM PDT 24
Finished Mar 31 03:53:08 PM PDT 24
Peak memory 212980 kb
Host smart-b85e7c02-aa24-417e-bfe4-85b4816932e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970802013 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.2970802013
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3671649131
Short name T310
Test name
Test status
Simulation time 700151577 ps
CPU time 27.55 seconds
Started Mar 31 03:52:27 PM PDT 24
Finished Mar 31 03:52:55 PM PDT 24
Peak memory 204948 kb
Host smart-c360d2fb-bc9a-41b4-a9aa-b8200367687a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671649131 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.3671649131
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.97584751
Short name T112
Test name
Test status
Simulation time 5087849877 ps
CPU time 66.56 seconds
Started Mar 31 03:52:35 PM PDT 24
Finished Mar 31 03:53:42 PM PDT 24
Peak memory 205112 kb
Host smart-b1dbd5dd-861d-4f25-a268-6931be17a5d4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97584751 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.97584751
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.1777886018
Short name T87
Test name
Test status
Simulation time 117485142 ps
CPU time 2.55 seconds
Started Mar 31 03:52:46 PM PDT 24
Finished Mar 31 03:52:49 PM PDT 24
Peak memory 213244 kb
Host smart-b4ce8b5e-4297-4a5a-98b0-283303748314
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777886018 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.1777886018
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.2652075310
Short name T269
Test name
Test status
Simulation time 3688267825 ps
CPU time 8.35 seconds
Started Mar 31 03:52:30 PM PDT 24
Finished Mar 31 03:52:39 PM PDT 24
Peak memory 217892 kb
Host smart-ccd495c9-6396-4665-adb4-b64aae9c81a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652075310 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.2652075310
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2861255990
Short name T270
Test name
Test status
Simulation time 97545723 ps
CPU time 2.17 seconds
Started Mar 31 03:52:30 PM PDT 24
Finished Mar 31 03:52:37 PM PDT 24
Peak memory 213188 kb
Host smart-2b29516a-cf73-4f5a-beb8-8464bcbdd53e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861255990 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.2861255990
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3246745573
Short name T343
Test name
Test status
Simulation time 3223999701 ps
CPU time 12.4 seconds
Started Mar 31 03:52:36 PM PDT 24
Finished Mar 31 03:52:49 PM PDT 24
Peak memory 204864 kb
Host smart-eb663bf7-f26c-4788-8dd0-c9e02ebff562
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246745573 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.3246745573
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.3639928947
Short name T329
Test name
Test status
Simulation time 11492287926 ps
CPU time 17.63 seconds
Started Mar 31 03:52:30 PM PDT 24
Finished Mar 31 03:52:48 PM PDT 24
Peak memory 204932 kb
Host smart-c294a589-1563-4fc0-bb64-0a546b55da04
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639928947 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_bit_bash.3639928947
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.4045143202
Short name T275
Test name
Test status
Simulation time 274561817 ps
CPU time 0.99 seconds
Started Mar 31 03:52:24 PM PDT 24
Finished Mar 31 03:52:25 PM PDT 24
Peak memory 204748 kb
Host smart-caa912dc-d796-49b1-8941-fb7c0107d1a8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045143202 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.4
045143202
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2713860767
Short name T333
Test name
Test status
Simulation time 95073497 ps
CPU time 0.77 seconds
Started Mar 31 03:52:28 PM PDT 24
Finished Mar 31 03:52:29 PM PDT 24
Peak memory 204780 kb
Host smart-fe2d2f38-0a92-4a16-9e06-9b6f765ac217
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713860767 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.2713860767
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.2658244112
Short name T308
Test name
Test status
Simulation time 1953876808 ps
CPU time 6.2 seconds
Started Mar 31 03:52:25 PM PDT 24
Finished Mar 31 03:52:32 PM PDT 24
Peak memory 204840 kb
Host smart-afcf6f21-ec11-480e-b47c-8ead7684bef9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658244112 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.2658244112
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3975568684
Short name T264
Test name
Test status
Simulation time 33663300 ps
CPU time 0.81 seconds
Started Mar 31 03:52:23 PM PDT 24
Finished Mar 31 03:52:24 PM PDT 24
Peak memory 204744 kb
Host smart-3ca6c68c-1267-4d3e-98d0-dd24b2edd494
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975568684 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.3975568684
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.2729378214
Short name T317
Test name
Test status
Simulation time 69902955 ps
CPU time 0.7 seconds
Started Mar 31 03:52:36 PM PDT 24
Finished Mar 31 03:52:37 PM PDT 24
Peak memory 204624 kb
Host smart-fe19bfee-e834-4c19-94fd-40de36358fda
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729378214 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.2
729378214
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.2563835421
Short name T239
Test name
Test status
Simulation time 32799547 ps
CPU time 0.67 seconds
Started Mar 31 03:52:36 PM PDT 24
Finished Mar 31 03:52:37 PM PDT 24
Peak memory 204624 kb
Host smart-701a7822-c989-4373-a81a-c33e81b99341
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563835421 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.2563835421
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.555508960
Short name T319
Test name
Test status
Simulation time 23433782 ps
CPU time 0.63 seconds
Started Mar 31 03:52:44 PM PDT 24
Finished Mar 31 03:52:45 PM PDT 24
Peak memory 204624 kb
Host smart-b0791961-b0d7-4237-8381-7bed625b05d9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555508960 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.555508960
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2214442905
Short name T105
Test name
Test status
Simulation time 567527450 ps
CPU time 6.82 seconds
Started Mar 31 03:52:32 PM PDT 24
Finished Mar 31 03:52:39 PM PDT 24
Peak memory 205036 kb
Host smart-485c7a2b-8a77-47dc-9140-f83c01808e55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214442905 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.2214442905
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.1696507471
Short name T273
Test name
Test status
Simulation time 8649412060 ps
CPU time 15.46 seconds
Started Mar 31 03:52:33 PM PDT 24
Finished Mar 31 03:52:49 PM PDT 24
Peak memory 218088 kb
Host smart-946ffff7-c85b-468e-9fd3-5f6cf4039ea7
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696507471 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.1696507471
Directory /workspace/0.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3213569051
Short name T136
Test name
Test status
Simulation time 2082898969 ps
CPU time 20.06 seconds
Started Mar 31 03:52:32 PM PDT 24
Finished Mar 31 03:52:52 PM PDT 24
Peak memory 221300 kb
Host smart-484a63ac-3cc0-48e9-bfe6-3e546ee5548b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213569051 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.3213569051
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2184748138
Short name T115
Test name
Test status
Simulation time 14042078928 ps
CPU time 55.62 seconds
Started Mar 31 03:52:51 PM PDT 24
Finished Mar 31 03:53:47 PM PDT 24
Peak memory 205044 kb
Host smart-625c8124-18fc-4c73-ae3a-88daceb67cf6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184748138 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.2184748138
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2451873436
Short name T114
Test name
Test status
Simulation time 109599011 ps
CPU time 2.41 seconds
Started Mar 31 03:52:35 PM PDT 24
Finished Mar 31 03:52:37 PM PDT 24
Peak memory 213144 kb
Host smart-877e8de3-00ff-4070-b9fb-e24be2ed3d0c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451873436 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.2451873436
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2744380746
Short name T277
Test name
Test status
Simulation time 1524948846 ps
CPU time 3.73 seconds
Started Mar 31 03:52:37 PM PDT 24
Finished Mar 31 03:52:40 PM PDT 24
Peak memory 218780 kb
Host smart-8822983e-4243-42a8-a658-122d3c7fabae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744380746 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.2744380746
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1978840009
Short name T328
Test name
Test status
Simulation time 18178056015 ps
CPU time 15.36 seconds
Started Mar 31 03:52:35 PM PDT 24
Finished Mar 31 03:52:50 PM PDT 24
Peak memory 204920 kb
Host smart-f31a0dd8-2193-4014-a50e-238305df4a61
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978840009 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.1978840009
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1424038010
Short name T370
Test name
Test status
Simulation time 16629624777 ps
CPU time 19.26 seconds
Started Mar 31 03:52:36 PM PDT 24
Finished Mar 31 03:52:55 PM PDT 24
Peak memory 204884 kb
Host smart-12038e33-d990-4cc9-a4df-be4009bf211f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424038010 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_bit_bash.1424038010
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2850786470
Short name T243
Test name
Test status
Simulation time 1171872669 ps
CPU time 1.66 seconds
Started Mar 31 03:52:35 PM PDT 24
Finished Mar 31 03:52:37 PM PDT 24
Peak memory 204920 kb
Host smart-cd1ccdc4-c6a4-4db0-a15a-1005b362895a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850786470 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.2850786470
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2800872389
Short name T301
Test name
Test status
Simulation time 291072520 ps
CPU time 1.14 seconds
Started Mar 31 03:52:38 PM PDT 24
Finished Mar 31 03:52:39 PM PDT 24
Peak memory 204916 kb
Host smart-26fdf9b3-030b-48b0-b1a8-ec7ecef87d25
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800872389 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.2
800872389
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.4177752959
Short name T290
Test name
Test status
Simulation time 136595893 ps
CPU time 0.93 seconds
Started Mar 31 03:52:34 PM PDT 24
Finished Mar 31 03:52:35 PM PDT 24
Peak memory 204656 kb
Host smart-0545bb56-c023-46ab-983f-3b88ecad123d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177752959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.4177752959
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2630762724
Short name T244
Test name
Test status
Simulation time 85378870 ps
CPU time 0.76 seconds
Started Mar 31 03:52:32 PM PDT 24
Finished Mar 31 03:52:33 PM PDT 24
Peak memory 204664 kb
Host smart-7fe93f78-eaca-46e2-aad9-8f5ba0c38a23
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630762724 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.2630762724
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.313666655
Short name T355
Test name
Test status
Simulation time 47208074 ps
CPU time 0.67 seconds
Started Mar 31 03:52:51 PM PDT 24
Finished Mar 31 03:52:52 PM PDT 24
Peak memory 204608 kb
Host smart-11bd6663-def3-4b8d-aebc-30e1eba6d984
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313666655 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.313666655
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3407919751
Short name T246
Test name
Test status
Simulation time 54747760 ps
CPU time 0.67 seconds
Started Mar 31 03:52:35 PM PDT 24
Finished Mar 31 03:52:41 PM PDT 24
Peak memory 204644 kb
Host smart-8cffdd61-638c-4c20-9141-6ddfaf0b1b8f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407919751 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.3407919751
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.3722206919
Short name T278
Test name
Test status
Simulation time 17880533 ps
CPU time 0.68 seconds
Started Mar 31 03:52:51 PM PDT 24
Finished Mar 31 03:52:52 PM PDT 24
Peak memory 204672 kb
Host smart-24ca3161-2e4d-4bed-8947-fd0fce622ef7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722206919 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.3722206919
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3420778321
Short name T89
Test name
Test status
Simulation time 158695359 ps
CPU time 3.62 seconds
Started Mar 31 03:52:48 PM PDT 24
Finished Mar 31 03:52:52 PM PDT 24
Peak memory 204952 kb
Host smart-89c63776-3ccb-454d-993a-53cf937ce395
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420778321 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_
csr_outstanding.3420778321
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.3117754609
Short name T76
Test name
Test status
Simulation time 234378237 ps
CPU time 5.46 seconds
Started Mar 31 03:52:47 PM PDT 24
Finished Mar 31 03:52:53 PM PDT 24
Peak memory 213196 kb
Host smart-ebca5b82-266f-46f7-8028-8773a8addb3a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117754609 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.3117754609
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.3455404664
Short name T364
Test name
Test status
Simulation time 733015306 ps
CPU time 15.74 seconds
Started Mar 31 03:52:37 PM PDT 24
Finished Mar 31 03:52:53 PM PDT 24
Peak memory 213096 kb
Host smart-3dc6286d-4bad-4b7d-94d3-9b2830f4a793
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455404664 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.3455404664
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.532661574
Short name T83
Test name
Test status
Simulation time 84736440 ps
CPU time 3.59 seconds
Started Mar 31 03:52:51 PM PDT 24
Finished Mar 31 03:52:54 PM PDT 24
Peak memory 219316 kb
Host smart-735d9b0f-7697-4e2b-9af0-b431edb3b68f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532661574 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.532661574
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.2844928044
Short name T344
Test name
Test status
Simulation time 28653026 ps
CPU time 1.5 seconds
Started Mar 31 03:52:57 PM PDT 24
Finished Mar 31 03:52:59 PM PDT 24
Peak memory 221392 kb
Host smart-df9231b5-d098-41e2-9ee4-8e8c859ebd0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844928044 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.2844928044
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2759198760
Short name T348
Test name
Test status
Simulation time 270122940 ps
CPU time 1.81 seconds
Started Mar 31 03:52:59 PM PDT 24
Finished Mar 31 03:53:01 PM PDT 24
Peak memory 204828 kb
Host smart-1bfe7207-757e-4889-abeb-fd87babf9e06
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759198760 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
2759198760
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1145770320
Short name T75
Test name
Test status
Simulation time 150811385 ps
CPU time 0.91 seconds
Started Mar 31 03:52:53 PM PDT 24
Finished Mar 31 03:52:54 PM PDT 24
Peak memory 204604 kb
Host smart-2563b848-b177-4b6f-bdb0-13b1a9f6c553
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145770320 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
1145770320
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.1519841826
Short name T283
Test name
Test status
Simulation time 66277028 ps
CPU time 2.82 seconds
Started Mar 31 03:52:59 PM PDT 24
Finished Mar 31 03:53:02 PM PDT 24
Peak memory 213208 kb
Host smart-43a37187-07d3-46b3-a5a2-8471cc1d1f06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519841826 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.1519841826
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2818702568
Short name T130
Test name
Test status
Simulation time 2079712034 ps
CPU time 19.96 seconds
Started Mar 31 03:52:43 PM PDT 24
Finished Mar 31 03:53:03 PM PDT 24
Peak memory 221344 kb
Host smart-4bdf810e-6894-496e-b58d-163a8db0b3fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818702568 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.2
818702568
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3888059073
Short name T356
Test name
Test status
Simulation time 147253341 ps
CPU time 2.19 seconds
Started Mar 31 03:53:10 PM PDT 24
Finished Mar 31 03:53:12 PM PDT 24
Peak memory 215288 kb
Host smart-4a29dca7-630e-46be-aa41-ef4bc30bd8b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888059073 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.3888059073
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.2384687995
Short name T280
Test name
Test status
Simulation time 99535340 ps
CPU time 1.49 seconds
Started Mar 31 03:52:48 PM PDT 24
Finished Mar 31 03:52:50 PM PDT 24
Peak memory 213176 kb
Host smart-776ce1cc-5752-4724-a5b5-87ac9277b79a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384687995 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.2384687995
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3821264529
Short name T291
Test name
Test status
Simulation time 492716622 ps
CPU time 2.56 seconds
Started Mar 31 03:53:24 PM PDT 24
Finished Mar 31 03:53:27 PM PDT 24
Peak memory 204908 kb
Host smart-72c1ac45-a2ec-4cb5-a9a9-63bc856044c5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821264529 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
3821264529
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3511538092
Short name T347
Test name
Test status
Simulation time 59448588 ps
CPU time 0.68 seconds
Started Mar 31 03:52:39 PM PDT 24
Finished Mar 31 03:52:40 PM PDT 24
Peak memory 204672 kb
Host smart-ade982c4-38eb-4a2c-ae1c-162df4c74348
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511538092 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.
3511538092
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.1143665522
Short name T341
Test name
Test status
Simulation time 553511375 ps
CPU time 6.62 seconds
Started Mar 31 03:52:52 PM PDT 24
Finished Mar 31 03:52:59 PM PDT 24
Peak memory 204968 kb
Host smart-8c925712-f36d-4337-bbcf-18d70698df18
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143665522 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same
_csr_outstanding.1143665522
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.568455457
Short name T300
Test name
Test status
Simulation time 117453694 ps
CPU time 3.2 seconds
Started Mar 31 03:53:00 PM PDT 24
Finished Mar 31 03:53:03 PM PDT 24
Peak memory 213164 kb
Host smart-8e23b2dd-756b-4181-a573-d9f0f58a759a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568455457 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.568455457
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.729243026
Short name T349
Test name
Test status
Simulation time 417638096 ps
CPU time 16.01 seconds
Started Mar 31 03:52:52 PM PDT 24
Finished Mar 31 03:53:08 PM PDT 24
Peak memory 213184 kb
Host smart-37aa93cc-0521-4b14-9f46-d79a778c6386
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729243026 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.729243026
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.917772585
Short name T51
Test name
Test status
Simulation time 380697649 ps
CPU time 2.7 seconds
Started Mar 31 03:52:54 PM PDT 24
Finished Mar 31 03:52:57 PM PDT 24
Peak memory 218252 kb
Host smart-21bc3852-ee9a-49dd-8dab-86654a478ce3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917772585 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.917772585
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.3892677956
Short name T93
Test name
Test status
Simulation time 1715943835 ps
CPU time 2.6 seconds
Started Mar 31 03:52:52 PM PDT 24
Finished Mar 31 03:52:55 PM PDT 24
Peak memory 213120 kb
Host smart-93523d46-a33a-456e-96af-48544c39c245
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892677956 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.3892677956
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1986881979
Short name T250
Test name
Test status
Simulation time 236344137 ps
CPU time 1.31 seconds
Started Mar 31 03:52:48 PM PDT 24
Finished Mar 31 03:52:49 PM PDT 24
Peak memory 204960 kb
Host smart-ba58192e-7755-4045-924e-b1822a572e02
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986881979 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
1986881979
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.160797170
Short name T248
Test name
Test status
Simulation time 26788261 ps
CPU time 0.7 seconds
Started Mar 31 03:52:38 PM PDT 24
Finished Mar 31 03:52:39 PM PDT 24
Peak memory 204560 kb
Host smart-0d0bdabf-fe7f-4cfc-b815-acd92a47c2b2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160797170 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.160797170
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.354655956
Short name T350
Test name
Test status
Simulation time 1027695793 ps
CPU time 7.7 seconds
Started Mar 31 03:52:58 PM PDT 24
Finished Mar 31 03:53:06 PM PDT 24
Peak memory 204960 kb
Host smart-88f1b645-8a70-4ce4-8084-6994cd29eb48
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354655956 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same_
csr_outstanding.354655956
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tap_fsm_rand_reset.1318129461
Short name T259
Test name
Test status
Simulation time 13108192174 ps
CPU time 11.87 seconds
Started Mar 31 03:53:03 PM PDT 24
Finished Mar 31 03:53:15 PM PDT 24
Peak memory 213264 kb
Host smart-cd289dc7-e232-4ba5-bf33-ab8373eaf7fd
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318129461 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rv_dm_tap_fsm_rand_reset.1318129461
Directory /workspace/12.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.2961193869
Short name T332
Test name
Test status
Simulation time 348057206 ps
CPU time 3.43 seconds
Started Mar 31 03:53:04 PM PDT 24
Finished Mar 31 03:53:07 PM PDT 24
Peak memory 213140 kb
Host smart-0a13e50b-edf5-45e0-80e2-533b485132f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961193869 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.2961193869
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3825859783
Short name T137
Test name
Test status
Simulation time 2767348319 ps
CPU time 10.12 seconds
Started Mar 31 03:52:53 PM PDT 24
Finished Mar 31 03:53:03 PM PDT 24
Peak memory 213312 kb
Host smart-287ab4a6-5405-4a07-8504-c62e7b32dc17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825859783 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.3
825859783
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.1438942042
Short name T267
Test name
Test status
Simulation time 466339165 ps
CPU time 2.38 seconds
Started Mar 31 03:53:00 PM PDT 24
Finished Mar 31 03:53:02 PM PDT 24
Peak memory 217180 kb
Host smart-18e74db8-a7c5-435a-a633-966a70441244
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438942042 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.1438942042
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.2775018541
Short name T116
Test name
Test status
Simulation time 380047938 ps
CPU time 2.6 seconds
Started Mar 31 03:53:22 PM PDT 24
Finished Mar 31 03:53:24 PM PDT 24
Peak memory 213104 kb
Host smart-510a3166-8ed7-4409-b3f3-f1070cff4482
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775018541 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.2775018541
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.1423003729
Short name T321
Test name
Test status
Simulation time 521099477 ps
CPU time 1.25 seconds
Started Mar 31 03:52:43 PM PDT 24
Finished Mar 31 03:52:44 PM PDT 24
Peak memory 204904 kb
Host smart-41566b5c-b8fc-4b0e-9d49-fbae6cdfb0c8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423003729 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
1423003729
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1684657398
Short name T342
Test name
Test status
Simulation time 153565275 ps
CPU time 1.13 seconds
Started Mar 31 03:53:04 PM PDT 24
Finished Mar 31 03:53:06 PM PDT 24
Peak memory 204636 kb
Host smart-a2eab123-868f-4475-99ff-2164e0e82558
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684657398 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
1684657398
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2739104082
Short name T305
Test name
Test status
Simulation time 1397582526 ps
CPU time 4.41 seconds
Started Mar 31 03:52:49 PM PDT 24
Finished Mar 31 03:52:53 PM PDT 24
Peak memory 204904 kb
Host smart-d73d41f3-5b46-4230-94d0-226987fd8f9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739104082 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.2739104082
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tap_fsm_rand_reset.185371124
Short name T358
Test name
Test status
Simulation time 8561543401 ps
CPU time 16.6 seconds
Started Mar 31 03:53:05 PM PDT 24
Finished Mar 31 03:53:21 PM PDT 24
Peak memory 214652 kb
Host smart-ac5fa1ee-99a3-4cfe-8cc0-197215e41d9d
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185371124 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.rv_dm_tap_fsm_rand_reset.185371124
Directory /workspace/13.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2553702677
Short name T287
Test name
Test status
Simulation time 69883777 ps
CPU time 2.09 seconds
Started Mar 31 03:53:09 PM PDT 24
Finished Mar 31 03:53:11 PM PDT 24
Peak memory 213204 kb
Host smart-1ab041a1-378e-4590-b00c-7197834e0b89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553702677 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.2553702677
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2045215813
Short name T134
Test name
Test status
Simulation time 772698682 ps
CPU time 8.12 seconds
Started Mar 31 03:52:51 PM PDT 24
Finished Mar 31 03:52:59 PM PDT 24
Peak memory 221368 kb
Host smart-a0a9d8b1-f8f3-4a12-8e27-3f576730c84e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045215813 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.2
045215813
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.1335372651
Short name T268
Test name
Test status
Simulation time 369691427 ps
CPU time 2.18 seconds
Started Mar 31 03:53:09 PM PDT 24
Finished Mar 31 03:53:12 PM PDT 24
Peak memory 216460 kb
Host smart-5a440c53-cf2d-41c1-b61a-2d003ccefd70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335372651 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.1335372651
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.644198994
Short name T330
Test name
Test status
Simulation time 85613834 ps
CPU time 2.17 seconds
Started Mar 31 03:52:53 PM PDT 24
Finished Mar 31 03:52:56 PM PDT 24
Peak memory 218784 kb
Host smart-33ea86fb-748d-492e-af3f-118f8bf2ac8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644198994 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.644198994
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2036635746
Short name T297
Test name
Test status
Simulation time 231764357 ps
CPU time 0.99 seconds
Started Mar 31 03:52:50 PM PDT 24
Finished Mar 31 03:52:51 PM PDT 24
Peak memory 204860 kb
Host smart-9fd03c50-ff5f-42e7-9904-cbe5855eda0e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036635746 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
2036635746
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.1814912570
Short name T379
Test name
Test status
Simulation time 44090650 ps
CPU time 0.81 seconds
Started Mar 31 03:53:01 PM PDT 24
Finished Mar 31 03:53:02 PM PDT 24
Peak memory 204640 kb
Host smart-014f0dce-6f60-41f4-a913-fa0d74b61c8a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814912570 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
1814912570
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3803497004
Short name T91
Test name
Test status
Simulation time 3847791274 ps
CPU time 8.3 seconds
Started Mar 31 03:53:17 PM PDT 24
Finished Mar 31 03:53:25 PM PDT 24
Peak memory 205056 kb
Host smart-e6074445-6cbc-45a4-a1ec-3acf84f045bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803497004 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.3803497004
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tap_fsm_rand_reset.4060989362
Short name T354
Test name
Test status
Simulation time 8263895324 ps
CPU time 15.35 seconds
Started Mar 31 03:53:03 PM PDT 24
Finished Mar 31 03:53:19 PM PDT 24
Peak memory 221472 kb
Host smart-fce7a1aa-44dc-4edf-90fa-8202bdcb7bfc
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060989362 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rv_dm_tap_fsm_rand_reset.4060989362
Directory /workspace/14.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.2242987715
Short name T262
Test name
Test status
Simulation time 180395408 ps
CPU time 5.11 seconds
Started Mar 31 03:52:59 PM PDT 24
Finished Mar 31 03:53:04 PM PDT 24
Peak memory 213212 kb
Host smart-151b1181-64d1-4382-b478-825b3b69f76b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242987715 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.2242987715
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1233437155
Short name T282
Test name
Test status
Simulation time 3370058565 ps
CPU time 7.84 seconds
Started Mar 31 03:52:55 PM PDT 24
Finished Mar 31 03:53:03 PM PDT 24
Peak memory 217324 kb
Host smart-706c81a2-ce3e-45ce-afac-15ce7420dcce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233437155 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.1233437155
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2179619693
Short name T312
Test name
Test status
Simulation time 45618726 ps
CPU time 1.46 seconds
Started Mar 31 03:53:06 PM PDT 24
Finished Mar 31 03:53:07 PM PDT 24
Peak memory 213172 kb
Host smart-8908e9bb-0f9d-4804-8de7-7c970ffcdc47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179619693 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.2179619693
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.706351793
Short name T257
Test name
Test status
Simulation time 348542917 ps
CPU time 1.38 seconds
Started Mar 31 03:53:00 PM PDT 24
Finished Mar 31 03:53:02 PM PDT 24
Peak memory 204832 kb
Host smart-27c7c493-1d4b-41a9-8d10-5d4801be6284
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706351793 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.706351793
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3401456934
Short name T323
Test name
Test status
Simulation time 28127891 ps
CPU time 0.69 seconds
Started Mar 31 03:52:57 PM PDT 24
Finished Mar 31 03:52:58 PM PDT 24
Peak memory 204644 kb
Host smart-0c6ef855-bceb-48dc-86b8-68d05760e9c0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401456934 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
3401456934
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.2713985140
Short name T103
Test name
Test status
Simulation time 509065573 ps
CPU time 7.31 seconds
Started Mar 31 03:52:48 PM PDT 24
Finished Mar 31 03:52:56 PM PDT 24
Peak memory 204992 kb
Host smart-67307282-03ed-4a76-9b0a-14231540aef4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713985140 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.2713985140
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.778136334
Short name T271
Test name
Test status
Simulation time 255234185 ps
CPU time 4.92 seconds
Started Mar 31 03:52:52 PM PDT 24
Finished Mar 31 03:52:57 PM PDT 24
Peak memory 213196 kb
Host smart-a3630361-9bc2-40bc-890a-6b98629f9628
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778136334 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.778136334
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2877434363
Short name T53
Test name
Test status
Simulation time 1741539687 ps
CPU time 9.25 seconds
Started Mar 31 03:53:06 PM PDT 24
Finished Mar 31 03:53:15 PM PDT 24
Peak memory 213172 kb
Host smart-706ad472-7fd5-4ec9-a733-4fcc4a02644a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877434363 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.2
877434363
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.3143910300
Short name T272
Test name
Test status
Simulation time 2745646088 ps
CPU time 5.73 seconds
Started Mar 31 03:53:09 PM PDT 24
Finished Mar 31 03:53:15 PM PDT 24
Peak memory 214844 kb
Host smart-814349af-15b5-4ed0-8016-9b6c0af59843
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143910300 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.3143910300
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.1634166861
Short name T57
Test name
Test status
Simulation time 63908571 ps
CPU time 1.55 seconds
Started Mar 31 03:53:15 PM PDT 24
Finished Mar 31 03:53:16 PM PDT 24
Peak memory 221344 kb
Host smart-25e77dbf-f814-48f1-9e98-d5fba79ea820
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634166861 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.1634166861
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.3310559328
Short name T242
Test name
Test status
Simulation time 369419642 ps
CPU time 1.79 seconds
Started Mar 31 03:52:51 PM PDT 24
Finished Mar 31 03:52:54 PM PDT 24
Peak memory 204812 kb
Host smart-3cafea90-6396-4c7e-b7a5-fbaee365cec0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310559328 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
3310559328
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2565019147
Short name T340
Test name
Test status
Simulation time 93270798 ps
CPU time 0.9 seconds
Started Mar 31 03:53:00 PM PDT 24
Finished Mar 31 03:53:01 PM PDT 24
Peak memory 204660 kb
Host smart-3ce6854f-cbc0-400e-8960-232777371ecd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565019147 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
2565019147
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3731147303
Short name T346
Test name
Test status
Simulation time 80097419 ps
CPU time 3.55 seconds
Started Mar 31 03:53:01 PM PDT 24
Finished Mar 31 03:53:05 PM PDT 24
Peak memory 204988 kb
Host smart-bbb28925-63f2-4333-9b02-4630cc30895b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731147303 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.3731147303
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.526124491
Short name T331
Test name
Test status
Simulation time 148644338 ps
CPU time 2.16 seconds
Started Mar 31 03:52:59 PM PDT 24
Finished Mar 31 03:53:02 PM PDT 24
Peak memory 213176 kb
Host smart-272c7f26-5aa8-4c8b-9b9b-54b1f643f8e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526124491 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.526124491
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.2986710726
Short name T138
Test name
Test status
Simulation time 4699561997 ps
CPU time 10.19 seconds
Started Mar 31 03:52:40 PM PDT 24
Finished Mar 31 03:52:51 PM PDT 24
Peak memory 221360 kb
Host smart-ccb0fe7d-e837-4291-8139-eed8b8b9b0cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986710726 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.2
986710726
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2044442607
Short name T335
Test name
Test status
Simulation time 132909460 ps
CPU time 2.4 seconds
Started Mar 31 03:53:04 PM PDT 24
Finished Mar 31 03:53:06 PM PDT 24
Peak memory 217516 kb
Host smart-e5f49e14-cc90-4b14-b9e6-d5a82833635b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044442607 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.2044442607
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.2364785351
Short name T119
Test name
Test status
Simulation time 178006865 ps
CPU time 2.37 seconds
Started Mar 31 03:52:54 PM PDT 24
Finished Mar 31 03:53:01 PM PDT 24
Peak memory 213264 kb
Host smart-fb5b674a-5454-42b9-a439-479b47e7103b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364785351 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.2364785351
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.1045004817
Short name T240
Test name
Test status
Simulation time 285674268 ps
CPU time 1.47 seconds
Started Mar 31 03:53:09 PM PDT 24
Finished Mar 31 03:53:11 PM PDT 24
Peak memory 204808 kb
Host smart-39b6b9ca-d8e9-4c84-8d65-85d63cb39c86
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045004817 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
1045004817
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.3953128992
Short name T251
Test name
Test status
Simulation time 56158869 ps
CPU time 0.72 seconds
Started Mar 31 03:53:07 PM PDT 24
Finished Mar 31 03:53:08 PM PDT 24
Peak memory 204664 kb
Host smart-dce5393f-9e0c-4987-b9c0-4de7bf618d14
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953128992 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
3953128992
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2549322297
Short name T373
Test name
Test status
Simulation time 158602111 ps
CPU time 6.48 seconds
Started Mar 31 03:53:16 PM PDT 24
Finished Mar 31 03:53:22 PM PDT 24
Peak memory 204940 kb
Host smart-3e301ea3-d302-4257-85ce-31fcf1a6a059
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549322297 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.2549322297
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tap_fsm_rand_reset.2045138298
Short name T288
Test name
Test status
Simulation time 6535203622 ps
CPU time 23.22 seconds
Started Mar 31 03:52:55 PM PDT 24
Finished Mar 31 03:53:18 PM PDT 24
Peak memory 213724 kb
Host smart-edbf2f41-a960-42c2-b776-879c6c84a8cc
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045138298 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rv_dm_tap_fsm_rand_reset.2045138298
Directory /workspace/17.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.3455520282
Short name T362
Test name
Test status
Simulation time 254626299 ps
CPU time 5.35 seconds
Started Mar 31 03:52:50 PM PDT 24
Finished Mar 31 03:52:55 PM PDT 24
Peak memory 213328 kb
Host smart-4ab3b831-78c2-4a27-a44e-18d2b461db35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455520282 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.3455520282
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2111616838
Short name T150
Test name
Test status
Simulation time 2291666838 ps
CPU time 4.08 seconds
Started Mar 31 03:52:51 PM PDT 24
Finished Mar 31 03:52:56 PM PDT 24
Peak memory 221136 kb
Host smart-a8463658-c262-47de-a653-7c9a512aabda
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111616838 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.2111616838
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.1629154613
Short name T108
Test name
Test status
Simulation time 414248299 ps
CPU time 2.47 seconds
Started Mar 31 03:52:59 PM PDT 24
Finished Mar 31 03:53:02 PM PDT 24
Peak memory 213072 kb
Host smart-018a0c2f-619d-4955-a004-096f2e5056cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629154613 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.1629154613
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.789775939
Short name T284
Test name
Test status
Simulation time 278170984 ps
CPU time 1.89 seconds
Started Mar 31 03:53:01 PM PDT 24
Finished Mar 31 03:53:03 PM PDT 24
Peak memory 204860 kb
Host smart-80e0d229-4ac6-4ac7-afba-39623befd334
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789775939 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.789775939
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.3848824340
Short name T296
Test name
Test status
Simulation time 143600755 ps
CPU time 0.84 seconds
Started Mar 31 03:53:17 PM PDT 24
Finished Mar 31 03:53:19 PM PDT 24
Peak memory 204672 kb
Host smart-0279ac88-ecd3-4789-9a3b-e76016e850a5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848824340 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
3848824340
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.2330062376
Short name T307
Test name
Test status
Simulation time 1457601328 ps
CPU time 8.11 seconds
Started Mar 31 03:53:00 PM PDT 24
Finished Mar 31 03:53:08 PM PDT 24
Peak memory 205044 kb
Host smart-82ed12da-e841-4648-88f8-5f9b42d4d5e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330062376 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.2330062376
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.3264844949
Short name T54
Test name
Test status
Simulation time 119906227 ps
CPU time 3.45 seconds
Started Mar 31 03:53:12 PM PDT 24
Finished Mar 31 03:53:16 PM PDT 24
Peak memory 213180 kb
Host smart-4272f022-b718-4ce6-956b-10bb4d42e6df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264844949 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.3264844949
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.259489011
Short name T86
Test name
Test status
Simulation time 185564036 ps
CPU time 2.29 seconds
Started Mar 31 03:53:16 PM PDT 24
Finished Mar 31 03:53:18 PM PDT 24
Peak memory 213220 kb
Host smart-605d9b4f-4763-4270-a127-b5f9ac6c5327
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259489011 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.259489011
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.1553879260
Short name T260
Test name
Test status
Simulation time 365080116 ps
CPU time 2.34 seconds
Started Mar 31 03:53:07 PM PDT 24
Finished Mar 31 03:53:09 PM PDT 24
Peak memory 213192 kb
Host smart-c9375d78-1b7a-48cd-82f9-56d2f287c341
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553879260 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.1553879260
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.658691729
Short name T334
Test name
Test status
Simulation time 729582926 ps
CPU time 1.26 seconds
Started Mar 31 03:53:08 PM PDT 24
Finished Mar 31 03:53:10 PM PDT 24
Peak memory 204856 kb
Host smart-fcbfade1-3e13-4d8c-9c55-d0a1e8ef466d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658691729 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.658691729
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.202932789
Short name T281
Test name
Test status
Simulation time 78828512 ps
CPU time 0.79 seconds
Started Mar 31 03:53:07 PM PDT 24
Finished Mar 31 03:53:07 PM PDT 24
Peak memory 204632 kb
Host smart-26c4dc33-02c7-4dc9-a6c6-feea8a3ffee7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202932789 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.202932789
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.216104130
Short name T92
Test name
Test status
Simulation time 292426759 ps
CPU time 3.61 seconds
Started Mar 31 03:53:00 PM PDT 24
Finished Mar 31 03:53:04 PM PDT 24
Peak memory 205024 kb
Host smart-89e641ca-70cb-4cfa-95bb-c58d7e90c762
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216104130 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same_
csr_outstanding.216104130
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tap_fsm_rand_reset.2144119043
Short name T359
Test name
Test status
Simulation time 23508824025 ps
CPU time 23.49 seconds
Started Mar 31 03:53:04 PM PDT 24
Finished Mar 31 03:53:27 PM PDT 24
Peak memory 236632 kb
Host smart-1c686620-94cc-40bb-880c-5274b2c7955c
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144119043 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rv_dm_tap_fsm_rand_reset.2144119043
Directory /workspace/19.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.4201399439
Short name T306
Test name
Test status
Simulation time 36755173 ps
CPU time 1.96 seconds
Started Mar 31 03:53:11 PM PDT 24
Finished Mar 31 03:53:13 PM PDT 24
Peak memory 213148 kb
Host smart-2b336191-e07a-44b4-9dc7-5261cb97a3ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201399439 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.4201399439
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2815947046
Short name T95
Test name
Test status
Simulation time 1145381322 ps
CPU time 8.47 seconds
Started Mar 31 03:53:09 PM PDT 24
Finished Mar 31 03:53:18 PM PDT 24
Peak memory 213200 kb
Host smart-3e54b98c-7389-45c7-92df-6d1fb745e344
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815947046 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.2
815947046
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.3845001218
Short name T117
Test name
Test status
Simulation time 2867525437 ps
CPU time 55.45 seconds
Started Mar 31 03:52:37 PM PDT 24
Finished Mar 31 03:53:33 PM PDT 24
Peak memory 205012 kb
Host smart-a200bbf4-afb6-45bc-aac8-dadb6df9d2d2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845001218 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.3845001218
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.254308538
Short name T276
Test name
Test status
Simulation time 230137455 ps
CPU time 1.61 seconds
Started Mar 31 03:52:35 PM PDT 24
Finished Mar 31 03:52:37 PM PDT 24
Peak memory 213168 kb
Host smart-78bbe9ac-a36c-414e-b478-6117413c42e9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254308538 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.254308538
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3836090118
Short name T313
Test name
Test status
Simulation time 110744758 ps
CPU time 2.46 seconds
Started Mar 31 03:52:37 PM PDT 24
Finished Mar 31 03:52:40 PM PDT 24
Peak memory 218012 kb
Host smart-e1890acc-ab8c-4dc4-9932-4d390b68bafe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836090118 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.3836090118
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.2744910188
Short name T274
Test name
Test status
Simulation time 125227518 ps
CPU time 1.55 seconds
Started Mar 31 03:52:38 PM PDT 24
Finished Mar 31 03:52:39 PM PDT 24
Peak memory 213252 kb
Host smart-7fc248dc-ec0e-406e-b9b2-1a7246ea9817
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744910188 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.2744910188
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.3919777305
Short name T326
Test name
Test status
Simulation time 7367624611 ps
CPU time 25.06 seconds
Started Mar 31 03:52:38 PM PDT 24
Finished Mar 31 03:53:04 PM PDT 24
Peak memory 204892 kb
Host smart-4e1a819a-e674-4e9b-a35d-d789895090e9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919777305 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.3919777305
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.280012796
Short name T325
Test name
Test status
Simulation time 4604050113 ps
CPU time 16.52 seconds
Started Mar 31 03:52:28 PM PDT 24
Finished Mar 31 03:52:45 PM PDT 24
Peak memory 204900 kb
Host smart-2c4e89dd-ffb3-4340-a15e-8657fc9f93b1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280012796 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr
_bit_bash.280012796
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.3008860600
Short name T102
Test name
Test status
Simulation time 1364677265 ps
CPU time 4.74 seconds
Started Mar 31 03:52:34 PM PDT 24
Finished Mar 31 03:52:39 PM PDT 24
Peak memory 204904 kb
Host smart-3171d866-1cad-4415-a497-bbb063d8d884
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008860600 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.3008860600
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1502130708
Short name T361
Test name
Test status
Simulation time 479355354 ps
CPU time 1.23 seconds
Started Mar 31 03:52:33 PM PDT 24
Finished Mar 31 03:52:34 PM PDT 24
Peak memory 204924 kb
Host smart-1ec49ee7-26cb-4ea6-8fef-e485fc83dea6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502130708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.1
502130708
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.649642226
Short name T256
Test name
Test status
Simulation time 331088249 ps
CPU time 0.78 seconds
Started Mar 31 03:52:33 PM PDT 24
Finished Mar 31 03:52:35 PM PDT 24
Peak memory 204640 kb
Host smart-7f6af13f-043d-4527-8903-5e02a8a303e4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649642226 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_aliasing.649642226
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1551500928
Short name T252
Test name
Test status
Simulation time 2199281954 ps
CPU time 7.84 seconds
Started Mar 31 03:52:35 PM PDT 24
Finished Mar 31 03:52:44 PM PDT 24
Peak memory 204932 kb
Host smart-a08057f0-3da6-45d9-9293-974833398bd2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551500928 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.1551500928
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1058812743
Short name T303
Test name
Test status
Simulation time 47638423 ps
CPU time 0.7 seconds
Started Mar 31 03:52:39 PM PDT 24
Finished Mar 31 03:52:40 PM PDT 24
Peak memory 204724 kb
Host smart-031bac29-d979-4187-bbba-fa356456cca4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058812743 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.1058812743
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2064234736
Short name T311
Test name
Test status
Simulation time 76303826 ps
CPU time 0.71 seconds
Started Mar 31 03:52:30 PM PDT 24
Finished Mar 31 03:52:31 PM PDT 24
Peak memory 204676 kb
Host smart-d7d9dc4c-d0f5-4fe2-a45a-23d937482527
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064234736 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.2
064234736
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2929689317
Short name T289
Test name
Test status
Simulation time 18079141 ps
CPU time 0.68 seconds
Started Mar 31 03:52:32 PM PDT 24
Finished Mar 31 03:52:32 PM PDT 24
Peak memory 204624 kb
Host smart-007d2309-66d3-4d17-840e-fbb309ec318d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929689317 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.2929689317
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.3580079994
Short name T352
Test name
Test status
Simulation time 78567642 ps
CPU time 0.65 seconds
Started Mar 31 03:52:35 PM PDT 24
Finished Mar 31 03:52:36 PM PDT 24
Peak memory 204664 kb
Host smart-869e8ad2-89b9-4a45-b3a5-b75d6d16abed
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580079994 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.3580079994
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.1586627586
Short name T315
Test name
Test status
Simulation time 579914776 ps
CPU time 4.65 seconds
Started Mar 31 03:53:02 PM PDT 24
Finished Mar 31 03:53:07 PM PDT 24
Peak memory 204960 kb
Host smart-3a6b4ab1-95cc-4a07-b4f5-ee7f7d2162ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586627586 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.1586627586
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.2832111759
Short name T309
Test name
Test status
Simulation time 12950145307 ps
CPU time 12.07 seconds
Started Mar 31 03:52:38 PM PDT 24
Finished Mar 31 03:52:51 PM PDT 24
Peak memory 213900 kb
Host smart-08f7e891-ceb9-41cb-a377-f8369d8dbcf5
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832111759 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.2832111759
Directory /workspace/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.3735975309
Short name T360
Test name
Test status
Simulation time 69264570 ps
CPU time 4 seconds
Started Mar 31 03:52:34 PM PDT 24
Finished Mar 31 03:52:38 PM PDT 24
Peak memory 213180 kb
Host smart-3533449b-915d-4363-a82e-4676f94cbccf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735975309 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.3735975309
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.88656827
Short name T140
Test name
Test status
Simulation time 1453250865 ps
CPU time 19.82 seconds
Started Mar 31 03:52:35 PM PDT 24
Finished Mar 31 03:52:55 PM PDT 24
Peak memory 213216 kb
Host smart-6d33c9cd-8f37-495f-9ecb-ed2050b1ec37
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88656827 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.88656827
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_dm_tap_fsm_rand_reset.1565560067
Short name T302
Test name
Test status
Simulation time 7380537362 ps
CPU time 13.42 seconds
Started Mar 31 03:53:06 PM PDT 24
Finished Mar 31 03:53:19 PM PDT 24
Peak memory 220516 kb
Host smart-e45896d5-582b-4d13-90a6-bf5370d985c8
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565560067 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 20.rv_dm_tap_fsm_rand_reset.1565560067
Directory /workspace/20.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/21.rv_dm_tap_fsm_rand_reset.3750551274
Short name T265
Test name
Test status
Simulation time 19354608645 ps
CPU time 11.99 seconds
Started Mar 31 03:53:12 PM PDT 24
Finished Mar 31 03:53:24 PM PDT 24
Peak memory 220688 kb
Host smart-5adf83c4-859c-42d0-9a87-838afbc43ab7
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750551274 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 21.rv_dm_tap_fsm_rand_reset.3750551274
Directory /workspace/21.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/23.rv_dm_tap_fsm_rand_reset.399136617
Short name T279
Test name
Test status
Simulation time 8000131651 ps
CPU time 22.93 seconds
Started Mar 31 03:53:00 PM PDT 24
Finished Mar 31 03:53:23 PM PDT 24
Peak memory 219800 kb
Host smart-6ce35624-1606-4442-8fcf-f9a845785a4f
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399136617 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 23.rv_dm_tap_fsm_rand_reset.399136617
Directory /workspace/23.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/26.rv_dm_tap_fsm_rand_reset.1361125767
Short name T353
Test name
Test status
Simulation time 8243718532 ps
CPU time 15.39 seconds
Started Mar 31 03:52:56 PM PDT 24
Finished Mar 31 03:53:11 PM PDT 24
Peak memory 215204 kb
Host smart-537ea762-d9f8-4812-947b-77f881626538
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361125767 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 26.rv_dm_tap_fsm_rand_reset.1361125767
Directory /workspace/26.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2531832406
Short name T109
Test name
Test status
Simulation time 9548729896 ps
CPU time 81.71 seconds
Started Mar 31 03:52:37 PM PDT 24
Finished Mar 31 03:53:59 PM PDT 24
Peak memory 218600 kb
Host smart-1271f277-53fb-46d4-9060-74f8b8a6ea03
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531832406 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.2531832406
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.4145883116
Short name T380
Test name
Test status
Simulation time 2952655951 ps
CPU time 26.91 seconds
Started Mar 31 03:52:44 PM PDT 24
Finished Mar 31 03:53:11 PM PDT 24
Peak memory 205036 kb
Host smart-8cc81e3f-0111-4fa6-a624-5ecd134b0314
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145883116 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.4145883116
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.3641416008
Short name T320
Test name
Test status
Simulation time 165051093 ps
CPU time 2.19 seconds
Started Mar 31 03:52:44 PM PDT 24
Finished Mar 31 03:52:47 PM PDT 24
Peak memory 213196 kb
Host smart-cb36557f-08bb-4f71-bf46-59b58a494023
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641416008 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.3641416008
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.2393116989
Short name T85
Test name
Test status
Simulation time 2355601733 ps
CPU time 3.56 seconds
Started Mar 31 03:53:00 PM PDT 24
Finished Mar 31 03:53:03 PM PDT 24
Peak memory 216988 kb
Host smart-6b239189-5f8f-4d8f-acd8-fd94434ad60a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393116989 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.2393116989
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.3126326667
Short name T371
Test name
Test status
Simulation time 85678429 ps
CPU time 2.23 seconds
Started Mar 31 03:52:41 PM PDT 24
Finished Mar 31 03:52:43 PM PDT 24
Peak memory 213180 kb
Host smart-1054e667-0c16-48b7-b39d-844ec6ab7fd5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126326667 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.3126326667
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.4182054093
Short name T295
Test name
Test status
Simulation time 7366671994 ps
CPU time 9.58 seconds
Started Mar 31 03:52:49 PM PDT 24
Finished Mar 31 03:52:58 PM PDT 24
Peak memory 204932 kb
Host smart-f6eb04cc-c019-4f8e-b4d6-b7fb740288e6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182054093 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.4182054093
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.3350287472
Short name T383
Test name
Test status
Simulation time 11114483415 ps
CPU time 30.13 seconds
Started Mar 31 03:53:08 PM PDT 24
Finished Mar 31 03:53:38 PM PDT 24
Peak memory 204944 kb
Host smart-92216e5a-0428-4acd-a225-5d3072a43bee
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350287472 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_bit_bash.3350287472
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.638030448
Short name T100
Test name
Test status
Simulation time 2600319451 ps
CPU time 3.14 seconds
Started Mar 31 03:52:54 PM PDT 24
Finished Mar 31 03:52:57 PM PDT 24
Peak memory 205040 kb
Host smart-40c6557b-d16f-4a2d-abf4-5669be9bc800
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638030448 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr
_hw_reset.638030448
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.2315746495
Short name T381
Test name
Test status
Simulation time 379118545 ps
CPU time 1.43 seconds
Started Mar 31 03:52:47 PM PDT 24
Finished Mar 31 03:52:48 PM PDT 24
Peak memory 204852 kb
Host smart-7c2ba76f-3ef3-4867-8716-4ad594daedb9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315746495 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.2
315746495
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3916272502
Short name T74
Test name
Test status
Simulation time 61488833 ps
CPU time 0.81 seconds
Started Mar 31 03:52:52 PM PDT 24
Finished Mar 31 03:52:53 PM PDT 24
Peak memory 204652 kb
Host smart-97776c62-718a-4024-93ef-67bd163ba8ec
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916272502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.3916272502
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.3471208008
Short name T292
Test name
Test status
Simulation time 1368358919 ps
CPU time 5.53 seconds
Started Mar 31 03:52:48 PM PDT 24
Finished Mar 31 03:52:53 PM PDT 24
Peak memory 204884 kb
Host smart-7ba7eaca-5f8e-4d09-96fc-cc1bf5e16761
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471208008 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.3471208008
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.2018824829
Short name T372
Test name
Test status
Simulation time 81534077 ps
CPU time 0.93 seconds
Started Mar 31 03:52:35 PM PDT 24
Finished Mar 31 03:52:36 PM PDT 24
Peak memory 204648 kb
Host smart-bfff4f39-4c2f-486c-92aa-032449fcceeb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018824829 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.2018824829
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.3171171829
Short name T377
Test name
Test status
Simulation time 76861218 ps
CPU time 0.72 seconds
Started Mar 31 03:52:37 PM PDT 24
Finished Mar 31 03:52:38 PM PDT 24
Peak memory 204640 kb
Host smart-60af8193-760e-4b5f-9ade-14e6a4f1851b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171171829 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.3
171171829
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.3341187647
Short name T249
Test name
Test status
Simulation time 60984795 ps
CPU time 0.76 seconds
Started Mar 31 03:52:54 PM PDT 24
Finished Mar 31 03:52:55 PM PDT 24
Peak memory 204688 kb
Host smart-e46104a7-24f3-4380-a958-f54aaac70351
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341187647 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.3341187647
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.271284813
Short name T247
Test name
Test status
Simulation time 111927322 ps
CPU time 0.65 seconds
Started Mar 31 03:52:36 PM PDT 24
Finished Mar 31 03:52:37 PM PDT 24
Peak memory 204664 kb
Host smart-434e91c5-1f34-4f41-9693-842679ffd5ba
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271284813 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.271284813
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.3180869144
Short name T293
Test name
Test status
Simulation time 389089192 ps
CPU time 7.52 seconds
Started Mar 31 03:52:58 PM PDT 24
Finished Mar 31 03:53:06 PM PDT 24
Peak memory 205048 kb
Host smart-77000f48-7710-4346-b531-fbf413cf2b7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180869144 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.3180869144
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.3967255041
Short name T339
Test name
Test status
Simulation time 113224011 ps
CPU time 3.54 seconds
Started Mar 31 03:52:51 PM PDT 24
Finished Mar 31 03:52:54 PM PDT 24
Peak memory 213096 kb
Host smart-d95f4109-2cf2-4cdb-994e-6353866b7bf0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967255041 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.3967255041
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.1554944184
Short name T132
Test name
Test status
Simulation time 1012608908 ps
CPU time 9.52 seconds
Started Mar 31 03:52:31 PM PDT 24
Finished Mar 31 03:52:41 PM PDT 24
Peak memory 213212 kb
Host smart-0d70d8d2-c12e-4500-ad08-ebaf4e0592c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554944184 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.1554944184
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/33.rv_dm_tap_fsm_rand_reset.3753260883
Short name T384
Test name
Test status
Simulation time 12759197624 ps
CPU time 16.47 seconds
Started Mar 31 03:53:06 PM PDT 24
Finished Mar 31 03:53:22 PM PDT 24
Peak memory 213188 kb
Host smart-42cedcdc-f66e-4c19-8c0d-560810245bd2
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753260883 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 33.rv_dm_tap_fsm_rand_reset.3753260883
Directory /workspace/33.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/34.rv_dm_tap_fsm_rand_reset.3776787632
Short name T70
Test name
Test status
Simulation time 8382662857 ps
CPU time 14.46 seconds
Started Mar 31 03:53:10 PM PDT 24
Finished Mar 31 03:53:25 PM PDT 24
Peak memory 214428 kb
Host smart-65a4555c-006f-4f2e-825f-a4b03759e8c6
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776787632 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 34.rv_dm_tap_fsm_rand_reset.3776787632
Directory /workspace/34.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/37.rv_dm_tap_fsm_rand_reset.2482252568
Short name T258
Test name
Test status
Simulation time 7733836222 ps
CPU time 10.03 seconds
Started Mar 31 03:53:07 PM PDT 24
Finished Mar 31 03:53:17 PM PDT 24
Peak memory 219664 kb
Host smart-cf99bf6b-bc57-40c4-88cb-bd28133697f7
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482252568 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 37.rv_dm_tap_fsm_rand_reset.2482252568
Directory /workspace/37.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/38.rv_dm_tap_fsm_rand_reset.3617549451
Short name T82
Test name
Test status
Simulation time 16211492700 ps
CPU time 12.02 seconds
Started Mar 31 03:53:10 PM PDT 24
Finished Mar 31 03:53:23 PM PDT 24
Peak memory 215368 kb
Host smart-3115b631-c8fb-4afa-8a81-479a8b1b53d2
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617549451 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 38.rv_dm_tap_fsm_rand_reset.3617549451
Directory /workspace/38.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.3345002740
Short name T104
Test name
Test status
Simulation time 4087531610 ps
CPU time 69.51 seconds
Started Mar 31 03:52:41 PM PDT 24
Finished Mar 31 03:53:51 PM PDT 24
Peak memory 213260 kb
Host smart-34f7aee2-1a73-4ef0-8c63-eb1a94a9788a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345002740 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.3345002740
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.380246274
Short name T336
Test name
Test status
Simulation time 12797526945 ps
CPU time 71.71 seconds
Started Mar 31 03:52:37 PM PDT 24
Finished Mar 31 03:53:49 PM PDT 24
Peak memory 213284 kb
Host smart-0d076000-7264-495c-b9e7-3a3aa9053121
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380246274 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.380246274
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.997330384
Short name T55
Test name
Test status
Simulation time 104346886 ps
CPU time 2.25 seconds
Started Mar 31 03:52:52 PM PDT 24
Finished Mar 31 03:52:54 PM PDT 24
Peak memory 213260 kb
Host smart-027462cf-b8ba-4bff-b096-b50bc067e9c0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997330384 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.997330384
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.3702653037
Short name T366
Test name
Test status
Simulation time 86938795 ps
CPU time 2.29 seconds
Started Mar 31 03:52:55 PM PDT 24
Finished Mar 31 03:52:58 PM PDT 24
Peak memory 221292 kb
Host smart-41589812-6505-435b-b9e5-5677a59ba0a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702653037 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.3702653037
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.1502781264
Short name T286
Test name
Test status
Simulation time 545762807 ps
CPU time 2.46 seconds
Started Mar 31 03:52:44 PM PDT 24
Finished Mar 31 03:52:46 PM PDT 24
Peak memory 213156 kb
Host smart-1d536a3d-1879-4131-a8cf-b6cbf8409f03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502781264 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.1502781264
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.202014391
Short name T345
Test name
Test status
Simulation time 5582303324 ps
CPU time 8.04 seconds
Started Mar 31 03:52:36 PM PDT 24
Finished Mar 31 03:52:44 PM PDT 24
Peak memory 204912 kb
Host smart-87856c85-09db-4272-aae2-bd566fb20344
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202014391 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr
_aliasing.202014391
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.2427006498
Short name T327
Test name
Test status
Simulation time 9695427405 ps
CPU time 15.54 seconds
Started Mar 31 03:52:38 PM PDT 24
Finished Mar 31 03:52:58 PM PDT 24
Peak memory 204836 kb
Host smart-a1dae802-5e87-480e-9125-28cb78545fcf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427006498 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_bit_bash.2427006498
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2828772228
Short name T99
Test name
Test status
Simulation time 333191495 ps
CPU time 1.13 seconds
Started Mar 31 03:53:06 PM PDT 24
Finished Mar 31 03:53:07 PM PDT 24
Peak memory 204964 kb
Host smart-847c1f67-09fc-4d88-8536-36f0161e7c55
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828772228 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.2828772228
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.189193923
Short name T245
Test name
Test status
Simulation time 741702853 ps
CPU time 1.5 seconds
Started Mar 31 03:52:36 PM PDT 24
Finished Mar 31 03:52:38 PM PDT 24
Peak memory 205072 kb
Host smart-a90a98e8-5b3c-42c3-8ee7-29b4ffd4c8ab
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189193923 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.189193923
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.1584084123
Short name T374
Test name
Test status
Simulation time 102425820 ps
CPU time 0.79 seconds
Started Mar 31 03:52:49 PM PDT 24
Finished Mar 31 03:52:50 PM PDT 24
Peak memory 204688 kb
Host smart-0b19eeeb-c6bb-4f2b-bb68-e339e2f71bbc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584084123 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.1584084123
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.1175316409
Short name T241
Test name
Test status
Simulation time 2208372987 ps
CPU time 7.58 seconds
Started Mar 31 03:52:37 PM PDT 24
Finished Mar 31 03:52:44 PM PDT 24
Peak memory 204368 kb
Host smart-8bb2b0a6-6dac-4db4-8c2e-bfac0cfbf94f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175316409 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.1175316409
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.169925257
Short name T255
Test name
Test status
Simulation time 40548779 ps
CPU time 0.67 seconds
Started Mar 31 03:52:34 PM PDT 24
Finished Mar 31 03:52:35 PM PDT 24
Peak memory 204736 kb
Host smart-ea56f9af-fe4d-4795-9028-355c3df1d2ed
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169925257 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr
_hw_reset.169925257
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.4201036448
Short name T263
Test name
Test status
Simulation time 43606561 ps
CPU time 0.69 seconds
Started Mar 31 03:52:50 PM PDT 24
Finished Mar 31 03:52:50 PM PDT 24
Peak memory 204632 kb
Host smart-f10d456f-8060-487c-8832-01f172e35e1a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201036448 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.4
201036448
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1509436246
Short name T367
Test name
Test status
Simulation time 88388923 ps
CPU time 0.71 seconds
Started Mar 31 03:52:53 PM PDT 24
Finished Mar 31 03:52:53 PM PDT 24
Peak memory 204480 kb
Host smart-aad10432-1388-47e2-83e6-faee8dbd7475
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509436246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.1509436246
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.646492005
Short name T338
Test name
Test status
Simulation time 46945341 ps
CPU time 0.75 seconds
Started Mar 31 03:52:53 PM PDT 24
Finished Mar 31 03:52:53 PM PDT 24
Peak memory 204488 kb
Host smart-6cdf608e-1d99-46b0-a55a-1311bebae46c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646492005 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.646492005
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3106506822
Short name T56
Test name
Test status
Simulation time 1634678598 ps
CPU time 7.23 seconds
Started Mar 31 03:52:52 PM PDT 24
Finished Mar 31 03:53:00 PM PDT 24
Peak memory 204912 kb
Host smart-8d1925f1-efbf-4e21-a53f-5cedc802d504
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106506822 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.3106506822
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.1448618789
Short name T285
Test name
Test status
Simulation time 5791021399 ps
CPU time 10.42 seconds
Started Mar 31 03:52:37 PM PDT 24
Finished Mar 31 03:52:47 PM PDT 24
Peak memory 217740 kb
Host smart-ccb8266e-9500-4234-96dc-827b659d73b3
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448618789 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.1448618789
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.1337034193
Short name T159
Test name
Test status
Simulation time 157855761 ps
CPU time 2.55 seconds
Started Mar 31 03:52:40 PM PDT 24
Finished Mar 31 03:52:43 PM PDT 24
Peak memory 213188 kb
Host smart-e6263ce9-28bf-4eb7-ac02-62435e6ae4ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337034193 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.1337034193
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1166726559
Short name T135
Test name
Test status
Simulation time 663349100 ps
CPU time 16.37 seconds
Started Mar 31 03:53:02 PM PDT 24
Finished Mar 31 03:53:19 PM PDT 24
Peak memory 212992 kb
Host smart-a9e13b00-f6d7-456c-8a16-d1387ed1f67d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166726559 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.1166726559
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.4084049904
Short name T318
Test name
Test status
Simulation time 90893419 ps
CPU time 2.3 seconds
Started Mar 31 03:53:11 PM PDT 24
Finished Mar 31 03:53:13 PM PDT 24
Peak memory 217440 kb
Host smart-1f02889a-4790-43ca-84f8-598550b3aab9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084049904 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.4084049904
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.4129668889
Short name T110
Test name
Test status
Simulation time 70676839 ps
CPU time 2.09 seconds
Started Mar 31 03:52:49 PM PDT 24
Finished Mar 31 03:52:56 PM PDT 24
Peak memory 213360 kb
Host smart-91aa0ecb-7f27-4c4c-9fc8-1a1de4a172e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129668889 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.4129668889
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.1681637459
Short name T337
Test name
Test status
Simulation time 1062921396 ps
CPU time 2.58 seconds
Started Mar 31 03:52:44 PM PDT 24
Finished Mar 31 03:52:47 PM PDT 24
Peak memory 204748 kb
Host smart-667f90dc-9082-47f2-ac14-48613d42091a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681637459 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.1
681637459
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.1382239008
Short name T304
Test name
Test status
Simulation time 32570133 ps
CPU time 0.66 seconds
Started Mar 31 03:52:46 PM PDT 24
Finished Mar 31 03:52:47 PM PDT 24
Peak memory 204580 kb
Host smart-fcd0eb4b-2448-4baf-9a85-b969f03d0029
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382239008 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.1
382239008
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1243744992
Short name T121
Test name
Test status
Simulation time 576441915 ps
CPU time 7.94 seconds
Started Mar 31 03:52:56 PM PDT 24
Finished Mar 31 03:53:04 PM PDT 24
Peak memory 205040 kb
Host smart-0462a5ea-0b6d-40ea-83be-688d723160a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243744992 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.1243744992
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.789533984
Short name T378
Test name
Test status
Simulation time 35222385 ps
CPU time 1.69 seconds
Started Mar 31 03:52:39 PM PDT 24
Finished Mar 31 03:52:41 PM PDT 24
Peak memory 213100 kb
Host smart-8d2c7d5d-7efc-4aec-991b-0a9e5a324c37
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789533984 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.789533984
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2514040434
Short name T299
Test name
Test status
Simulation time 142214639 ps
CPU time 3.7 seconds
Started Mar 31 03:52:58 PM PDT 24
Finished Mar 31 03:53:02 PM PDT 24
Peak memory 221192 kb
Host smart-62164abf-fbfd-4021-b9b9-78095651e96b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514040434 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.2514040434
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.2796957484
Short name T111
Test name
Test status
Simulation time 140072300 ps
CPU time 2.07 seconds
Started Mar 31 03:52:55 PM PDT 24
Finished Mar 31 03:52:57 PM PDT 24
Peak memory 213000 kb
Host smart-a2317554-a68c-4e81-8019-666a61e71749
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796957484 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.2796957484
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.4029454530
Short name T253
Test name
Test status
Simulation time 743776671 ps
CPU time 1.56 seconds
Started Mar 31 03:52:49 PM PDT 24
Finished Mar 31 03:52:51 PM PDT 24
Peak memory 204848 kb
Host smart-4bc7de72-5543-4d0e-b74a-0c27cfd68f54
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029454530 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.4
029454530
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.4025897960
Short name T375
Test name
Test status
Simulation time 36322797 ps
CPU time 0.76 seconds
Started Mar 31 03:52:55 PM PDT 24
Finished Mar 31 03:52:55 PM PDT 24
Peak memory 204468 kb
Host smart-d75b23c5-b0e8-468d-b299-500de574488f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025897960 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.4
025897960
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2799329808
Short name T376
Test name
Test status
Simulation time 274611119 ps
CPU time 4.23 seconds
Started Mar 31 03:53:06 PM PDT 24
Finished Mar 31 03:53:10 PM PDT 24
Peak memory 204980 kb
Host smart-ee48b5ec-96dc-4d38-826b-b41812771fd6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799329808 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.2799329808
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.952097858
Short name T128
Test name
Test status
Simulation time 25574733133 ps
CPU time 23.79 seconds
Started Mar 31 03:52:38 PM PDT 24
Finished Mar 31 03:53:02 PM PDT 24
Peak memory 237564 kb
Host smart-8d57f28d-91e8-4b00-8421-e3c0f2647e9f
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952097858 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.952097858
Directory /workspace/6.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.1905842402
Short name T129
Test name
Test status
Simulation time 209407670 ps
CPU time 4.12 seconds
Started Mar 31 03:52:37 PM PDT 24
Finished Mar 31 03:52:42 PM PDT 24
Peak memory 213156 kb
Host smart-6a068e51-a0a1-4f87-87be-ade4d45f341e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905842402 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.1905842402
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2919532988
Short name T139
Test name
Test status
Simulation time 2108899279 ps
CPU time 18.39 seconds
Started Mar 31 03:52:42 PM PDT 24
Finished Mar 31 03:53:01 PM PDT 24
Peak memory 221292 kb
Host smart-de92540a-2b5a-4abe-ba63-68999fa17906
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919532988 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.2919532988
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.1110509673
Short name T261
Test name
Test status
Simulation time 7194125320 ps
CPU time 6.21 seconds
Started Mar 31 03:52:51 PM PDT 24
Finished Mar 31 03:52:58 PM PDT 24
Peak memory 219548 kb
Host smart-2691a929-a315-4fbb-8099-244d0ba4c0f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110509673 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.1110509673
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.683266060
Short name T118
Test name
Test status
Simulation time 221791134 ps
CPU time 2.3 seconds
Started Mar 31 03:53:11 PM PDT 24
Finished Mar 31 03:53:13 PM PDT 24
Peak memory 219076 kb
Host smart-919f99ea-14a4-421d-a60d-a2aabb9ad170
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683266060 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.683266060
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2401479400
Short name T351
Test name
Test status
Simulation time 133384163 ps
CPU time 1.21 seconds
Started Mar 31 03:52:39 PM PDT 24
Finished Mar 31 03:52:41 PM PDT 24
Peak memory 204908 kb
Host smart-73ce0c63-12da-47f8-b9fb-2b925f3ee09f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401479400 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.2
401479400
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.2861869564
Short name T294
Test name
Test status
Simulation time 119551038 ps
CPU time 0.89 seconds
Started Mar 31 03:53:08 PM PDT 24
Finished Mar 31 03:53:09 PM PDT 24
Peak memory 204704 kb
Host smart-75255683-2468-4e77-b067-f8ac684490ad
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861869564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.2
861869564
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.4025160033
Short name T369
Test name
Test status
Simulation time 114621333 ps
CPU time 3.04 seconds
Started Mar 31 03:52:45 PM PDT 24
Finished Mar 31 03:52:48 PM PDT 24
Peak memory 213176 kb
Host smart-9ba2d7f4-d0ca-4d34-a21f-4d3efd8a529e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025160033 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.4025160033
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.1376376438
Short name T368
Test name
Test status
Simulation time 2509294066 ps
CPU time 19.05 seconds
Started Mar 31 03:52:37 PM PDT 24
Finished Mar 31 03:52:56 PM PDT 24
Peak memory 213232 kb
Host smart-75eb18c9-482c-40bf-a500-443161e69a0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376376438 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.1376376438
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1306042724
Short name T298
Test name
Test status
Simulation time 3569338606 ps
CPU time 4.56 seconds
Started Mar 31 03:52:38 PM PDT 24
Finished Mar 31 03:52:43 PM PDT 24
Peak memory 220004 kb
Host smart-433e5e43-75b0-4ec3-8c64-aa46e564f3cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306042724 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.1306042724
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1953248887
Short name T107
Test name
Test status
Simulation time 71707470 ps
CPU time 1.51 seconds
Started Mar 31 03:52:56 PM PDT 24
Finished Mar 31 03:52:57 PM PDT 24
Peak memory 213200 kb
Host smart-20489053-8521-451e-82bc-7c9e341f579b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953248887 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.1953248887
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3830813389
Short name T324
Test name
Test status
Simulation time 294950189 ps
CPU time 0.99 seconds
Started Mar 31 03:52:38 PM PDT 24
Finished Mar 31 03:52:39 PM PDT 24
Peak memory 204824 kb
Host smart-e7ba2525-0b5b-45ef-93e4-756a059a26af
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830813389 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.3
830813389
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.226396508
Short name T357
Test name
Test status
Simulation time 54084158 ps
CPU time 0.84 seconds
Started Mar 31 03:52:57 PM PDT 24
Finished Mar 31 03:52:58 PM PDT 24
Peak memory 204616 kb
Host smart-de503d84-0423-48ec-a455-f0c79ed1fdf7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226396508 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.226396508
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.591848219
Short name T122
Test name
Test status
Simulation time 788471034 ps
CPU time 7.6 seconds
Started Mar 31 03:52:53 PM PDT 24
Finished Mar 31 03:53:00 PM PDT 24
Peak memory 205064 kb
Host smart-dcec5de2-f814-4580-ab73-e72bbfbc239d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591848219 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_c
sr_outstanding.591848219
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2697343728
Short name T314
Test name
Test status
Simulation time 1487391664 ps
CPU time 3.46 seconds
Started Mar 31 03:52:43 PM PDT 24
Finished Mar 31 03:52:46 PM PDT 24
Peak memory 213176 kb
Host smart-b7578499-e51a-4989-b53d-37dc21d2ea58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697343728 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.2697343728
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.1347527058
Short name T365
Test name
Test status
Simulation time 349158848 ps
CPU time 8.53 seconds
Started Mar 31 03:52:56 PM PDT 24
Finished Mar 31 03:53:04 PM PDT 24
Peak memory 221344 kb
Host smart-9fa87179-a556-4c8e-a32c-f1fe3650c811
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347527058 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.1347527058
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3132838210
Short name T382
Test name
Test status
Simulation time 710981412 ps
CPU time 3.65 seconds
Started Mar 31 03:53:21 PM PDT 24
Finished Mar 31 03:53:24 PM PDT 24
Peak memory 217512 kb
Host smart-9a724792-907b-4599-bf74-40bbb5de7ca0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132838210 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.3132838210
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.685947368
Short name T316
Test name
Test status
Simulation time 64669589 ps
CPU time 1.96 seconds
Started Mar 31 03:52:52 PM PDT 24
Finished Mar 31 03:52:54 PM PDT 24
Peak memory 213268 kb
Host smart-98311b16-bc3c-4941-a802-9629108a02b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685947368 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.685947368
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.2621725606
Short name T254
Test name
Test status
Simulation time 287488300 ps
CPU time 1.42 seconds
Started Mar 31 03:52:35 PM PDT 24
Finished Mar 31 03:52:36 PM PDT 24
Peak memory 204840 kb
Host smart-a4bd5a5c-b36d-4ec9-957a-789ffe755cc2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621725606 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.2
621725606
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.2072268807
Short name T363
Test name
Test status
Simulation time 69180693 ps
CPU time 0.68 seconds
Started Mar 31 03:53:07 PM PDT 24
Finished Mar 31 03:53:08 PM PDT 24
Peak memory 204672 kb
Host smart-b84ea366-5301-4fd9-8b9e-55ad3fd6b1a3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072268807 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.2
072268807
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.2534111945
Short name T120
Test name
Test status
Simulation time 797448904 ps
CPU time 7.48 seconds
Started Mar 31 03:52:54 PM PDT 24
Finished Mar 31 03:53:01 PM PDT 24
Peak memory 205000 kb
Host smart-7330abf0-7bb0-4758-9400-9a5e0c7287dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534111945 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.2534111945
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.3859388625
Short name T266
Test name
Test status
Simulation time 308872056 ps
CPU time 2.8 seconds
Started Mar 31 03:52:36 PM PDT 24
Finished Mar 31 03:52:39 PM PDT 24
Peak memory 213244 kb
Host smart-ff48865d-50f9-4d88-adba-1919e4fab38a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859388625 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.3859388625
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2366077209
Short name T322
Test name
Test status
Simulation time 1089696326 ps
CPU time 8.07 seconds
Started Mar 31 03:52:48 PM PDT 24
Finished Mar 31 03:52:56 PM PDT 24
Peak memory 220560 kb
Host smart-2c872169-44ad-4ce2-b4dc-05d77862046c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366077209 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.2366077209
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.1413223010
Short name T42
Test name
Test status
Simulation time 15807642 ps
CPU time 0.71 seconds
Started Mar 31 12:59:32 PM PDT 24
Finished Mar 31 12:59:33 PM PDT 24
Peak memory 204352 kb
Host smart-c4d3f343-d452-40b2-b3b2-d42ea26d9e0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413223010 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.1413223010
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.4235788221
Short name T195
Test name
Test status
Simulation time 25407567471 ps
CPU time 101.48 seconds
Started Mar 31 12:59:23 PM PDT 24
Finished Mar 31 01:01:05 PM PDT 24
Peak memory 213400 kb
Host smart-2075debd-e7db-46cd-9809-561d5a732c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235788221 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.4235788221
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.1343825484
Short name T5
Test name
Test status
Simulation time 1382970699 ps
CPU time 5.27 seconds
Started Mar 31 12:59:23 PM PDT 24
Finished Mar 31 12:59:29 PM PDT 24
Peak memory 205024 kb
Host smart-b2f17bfc-0a8e-44ff-aa1e-fcf802e1f3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343825484 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.1343825484
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.3105189242
Short name T34
Test name
Test status
Simulation time 186845362 ps
CPU time 1.29 seconds
Started Mar 31 12:59:23 PM PDT 24
Finished Mar 31 12:59:25 PM PDT 24
Peak memory 204772 kb
Host smart-4943cca1-9303-4373-9693-cb1fa37dd79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105189242 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.3105189242
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.2394022138
Short name T4
Test name
Test status
Simulation time 652736859 ps
CPU time 2.62 seconds
Started Mar 31 12:59:22 PM PDT 24
Finished Mar 31 12:59:25 PM PDT 24
Peak memory 204832 kb
Host smart-3b23843f-8fa7-4dd7-a8f8-be8d2f6a9153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394022138 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.2394022138
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.1970892668
Short name T16
Test name
Test status
Simulation time 71085201 ps
CPU time 0.73 seconds
Started Mar 31 12:59:25 PM PDT 24
Finished Mar 31 12:59:26 PM PDT 24
Peak memory 204768 kb
Host smart-c0f54cac-5fee-4547-ac2b-7d10728876e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970892668 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.1970892668
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.93227011
Short name T32
Test name
Test status
Simulation time 743882820 ps
CPU time 1.96 seconds
Started Mar 31 12:59:23 PM PDT 24
Finished Mar 31 12:59:26 PM PDT 24
Peak memory 204808 kb
Host smart-afc7d638-b5ae-48d1-8b7b-6b7eb05d3deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93227011 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.93227011
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.980862330
Short name T46
Test name
Test status
Simulation time 159838102 ps
CPU time 0.78 seconds
Started Mar 31 12:59:23 PM PDT 24
Finished Mar 31 12:59:24 PM PDT 24
Peak memory 204648 kb
Host smart-49b42b02-992b-4707-b02c-d4d5b15b0827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980862330 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.980862330
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.2537459079
Short name T43
Test name
Test status
Simulation time 328039088 ps
CPU time 1 seconds
Started Mar 31 12:59:27 PM PDT 24
Finished Mar 31 12:59:28 PM PDT 24
Peak memory 204540 kb
Host smart-deb52237-c301-478a-9f09-430a2ae703a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537459079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.2537459079
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.2940372676
Short name T173
Test name
Test status
Simulation time 252852960 ps
CPU time 0.8 seconds
Started Mar 31 12:59:21 PM PDT 24
Finished Mar 31 12:59:22 PM PDT 24
Peak memory 204660 kb
Host smart-1112dda3-f9e9-4433-8349-99cbdca0bdd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940372676 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.2940372676
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.4197047198
Short name T21
Test name
Test status
Simulation time 196899212 ps
CPU time 1.26 seconds
Started Mar 31 12:59:27 PM PDT 24
Finished Mar 31 12:59:28 PM PDT 24
Peak memory 204860 kb
Host smart-4c147c61-0369-4d59-b296-4e5328f242e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197047198 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.4197047198
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.2933155629
Short name T72
Test name
Test status
Simulation time 45176402 ps
CPU time 0.73 seconds
Started Mar 31 12:59:22 PM PDT 24
Finished Mar 31 12:59:23 PM PDT 24
Peak memory 204644 kb
Host smart-e3063668-f7d8-4f19-9d22-d6f443c87777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933155629 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.2933155629
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.1009960624
Short name T181
Test name
Test status
Simulation time 136035630 ps
CPU time 1.08 seconds
Started Mar 31 12:59:21 PM PDT 24
Finished Mar 31 12:59:23 PM PDT 24
Peak memory 204824 kb
Host smart-d0235eb3-5809-472d-8d3e-411564beab1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009960624 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.1009960624
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.3928541614
Short name T228
Test name
Test status
Simulation time 104329886 ps
CPU time 0.97 seconds
Started Mar 31 12:59:24 PM PDT 24
Finished Mar 31 12:59:26 PM PDT 24
Peak memory 204780 kb
Host smart-8bb05f39-13e8-486a-a311-5557544902b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928541614 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.3928541614
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.1469460196
Short name T17
Test name
Test status
Simulation time 242173651 ps
CPU time 1.42 seconds
Started Mar 31 12:59:23 PM PDT 24
Finished Mar 31 12:59:25 PM PDT 24
Peak memory 204712 kb
Host smart-b12203db-c419-4d8f-872e-56ed96c4df04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469460196 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.1469460196
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.580863903
Short name T29
Test name
Test status
Simulation time 30488038 ps
CPU time 0.78 seconds
Started Mar 31 12:59:22 PM PDT 24
Finished Mar 31 12:59:23 PM PDT 24
Peak memory 213072 kb
Host smart-1f2935d2-76da-4f13-9e8a-721a3d62f37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580863903 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.580863903
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.2508424835
Short name T219
Test name
Test status
Simulation time 9975279185 ps
CPU time 14.8 seconds
Started Mar 31 12:59:24 PM PDT 24
Finished Mar 31 12:59:39 PM PDT 24
Peak memory 205252 kb
Host smart-9eb1dc48-2fbe-4ff6-92a2-5295c0c4e0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508424835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.2508424835
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.3916533452
Short name T62
Test name
Test status
Simulation time 271228295 ps
CPU time 1.23 seconds
Started Mar 31 12:59:33 PM PDT 24
Finished Mar 31 12:59:35 PM PDT 24
Peak memory 229168 kb
Host smart-a3e0fde4-e110-45cc-9e92-a7a1b43e3ded
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916533452 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.3916533452
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.1768296889
Short name T35
Test name
Test status
Simulation time 217350641 ps
CPU time 1.46 seconds
Started Mar 31 12:59:21 PM PDT 24
Finished Mar 31 12:59:23 PM PDT 24
Peak memory 204924 kb
Host smart-5d243c74-ea32-482e-8334-309c1d4fc601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768296889 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.1768296889
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.4184989217
Short name T69
Test name
Test status
Simulation time 1212633282 ps
CPU time 3.99 seconds
Started Mar 31 12:59:22 PM PDT 24
Finished Mar 31 12:59:27 PM PDT 24
Peak memory 204816 kb
Host smart-c53d6935-9d0e-41ed-9221-53c031b536e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184989217 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.4184989217
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.3520853649
Short name T193
Test name
Test status
Simulation time 26054664 ps
CPU time 0.69 seconds
Started Mar 31 12:59:44 PM PDT 24
Finished Mar 31 12:59:45 PM PDT 24
Peak memory 204808 kb
Host smart-1994a5c8-3c31-49dd-874b-dadd909817f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520853649 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.3520853649
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.1727018937
Short name T210
Test name
Test status
Simulation time 10437447177 ps
CPU time 28.28 seconds
Started Mar 31 12:59:30 PM PDT 24
Finished Mar 31 12:59:59 PM PDT 24
Peak memory 205172 kb
Host smart-3dd4dec5-20ee-4fc5-a091-091ff531b6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727018937 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.1727018937
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.2846949756
Short name T174
Test name
Test status
Simulation time 13802439908 ps
CPU time 44.45 seconds
Started Mar 31 12:59:30 PM PDT 24
Finished Mar 31 01:00:14 PM PDT 24
Peak memory 215984 kb
Host smart-e3222b65-24ca-405f-ad19-5977d37633c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846949756 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.2846949756
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.2715034126
Short name T8
Test name
Test status
Simulation time 1488482544 ps
CPU time 5.34 seconds
Started Mar 31 12:59:29 PM PDT 24
Finished Mar 31 12:59:35 PM PDT 24
Peak memory 205008 kb
Host smart-b3b50c5d-33de-4dd6-939f-65e9e6ccc40b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715034126 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.2715034126
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.4014885493
Short name T27
Test name
Test status
Simulation time 367997967 ps
CPU time 1.41 seconds
Started Mar 31 12:59:32 PM PDT 24
Finished Mar 31 12:59:33 PM PDT 24
Peak memory 204684 kb
Host smart-5aa239de-92d5-486d-b7d1-d2e5be2acb78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014885493 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.4014885493
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.977943511
Short name T142
Test name
Test status
Simulation time 1078223393 ps
CPU time 3.88 seconds
Started Mar 31 12:59:32 PM PDT 24
Finished Mar 31 12:59:36 PM PDT 24
Peak memory 205076 kb
Host smart-1789e2dc-36e9-485b-b026-8a86dffcf895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977943511 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.977943511
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.847961796
Short name T26
Test name
Test status
Simulation time 53300459 ps
CPU time 0.73 seconds
Started Mar 31 12:59:29 PM PDT 24
Finished Mar 31 12:59:30 PM PDT 24
Peak memory 204816 kb
Host smart-a8601e10-8fc3-4ca9-b1c4-85aa6d3c9590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847961796 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.847961796
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.1444821137
Short name T225
Test name
Test status
Simulation time 1648455125 ps
CPU time 3.48 seconds
Started Mar 31 12:59:30 PM PDT 24
Finished Mar 31 12:59:34 PM PDT 24
Peak memory 205124 kb
Host smart-653e881f-d662-41b5-adfe-c151bb503b5e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1444821137 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.1444821137
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.2084108772
Short name T14
Test name
Test status
Simulation time 349760744 ps
CPU time 2.01 seconds
Started Mar 31 12:59:33 PM PDT 24
Finished Mar 31 12:59:35 PM PDT 24
Peak memory 205004 kb
Host smart-baa486f5-9344-4a15-8119-4e315402dfbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084108772 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.2084108772
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.1507937350
Short name T171
Test name
Test status
Simulation time 16667878 ps
CPU time 0.67 seconds
Started Mar 31 12:59:31 PM PDT 24
Finished Mar 31 12:59:32 PM PDT 24
Peak memory 204596 kb
Host smart-14b4591d-7b74-4a3e-bce2-6df85d62a7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507937350 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.1507937350
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.2280762835
Short name T198
Test name
Test status
Simulation time 110241647 ps
CPU time 0.97 seconds
Started Mar 31 12:59:42 PM PDT 24
Finished Mar 31 12:59:43 PM PDT 24
Peak memory 204580 kb
Host smart-464bd258-41e1-40ca-a750-f827e8a5c0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280762835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.2280762835
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.3179851439
Short name T221
Test name
Test status
Simulation time 209761689 ps
CPU time 1.06 seconds
Started Mar 31 12:59:44 PM PDT 24
Finished Mar 31 12:59:46 PM PDT 24
Peak memory 204664 kb
Host smart-1b78373f-d281-40ff-95f8-e3c0e569c4b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179851439 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.3179851439
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.643244645
Short name T6
Test name
Test status
Simulation time 112232075 ps
CPU time 0.74 seconds
Started Mar 31 12:59:40 PM PDT 24
Finished Mar 31 12:59:41 PM PDT 24
Peak memory 204696 kb
Host smart-0772ae23-8167-4aaa-a7cc-c7afe80a66ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643244645 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.643244645
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.3511704766
Short name T20
Test name
Test status
Simulation time 74583525 ps
CPU time 0.72 seconds
Started Mar 31 12:59:31 PM PDT 24
Finished Mar 31 12:59:32 PM PDT 24
Peak memory 204708 kb
Host smart-2f951760-4d66-4f94-9490-1668bd27c66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511704766 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.3511704766
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.919203136
Short name T143
Test name
Test status
Simulation time 229993647 ps
CPU time 1.5 seconds
Started Mar 31 12:59:31 PM PDT 24
Finished Mar 31 12:59:33 PM PDT 24
Peak memory 204884 kb
Host smart-6f3699e4-eacc-4ca0-8ff5-b9bd424662ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919203136 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.919203136
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.2572130979
Short name T18
Test name
Test status
Simulation time 538759995 ps
CPU time 1.75 seconds
Started Mar 31 12:59:32 PM PDT 24
Finished Mar 31 12:59:34 PM PDT 24
Peak memory 204516 kb
Host smart-3f880dc7-9746-41f3-9f2a-dfb127f32cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572130979 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.2572130979
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.1708930144
Short name T36
Test name
Test status
Simulation time 147771726 ps
CPU time 0.83 seconds
Started Mar 31 12:59:39 PM PDT 24
Finished Mar 31 12:59:40 PM PDT 24
Peak memory 204728 kb
Host smart-632f2d38-4e75-4919-9492-cc9f18b5b618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708930144 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.1708930144
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.25061406
Short name T213
Test name
Test status
Simulation time 416668159 ps
CPU time 2.61 seconds
Started Mar 31 12:59:31 PM PDT 24
Finished Mar 31 12:59:34 PM PDT 24
Peak memory 205064 kb
Host smart-33764a68-1004-43b7-8eef-277e117ab1d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25061406 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.25061406
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.118287389
Short name T61
Test name
Test status
Simulation time 67193557 ps
CPU time 1.08 seconds
Started Mar 31 12:59:39 PM PDT 24
Finished Mar 31 12:59:41 PM PDT 24
Peak memory 228484 kb
Host smart-488a787b-1d51-4669-a163-cdaa6e41bdfa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118287389 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.118287389
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.433037537
Short name T209
Test name
Test status
Simulation time 899922817 ps
CPU time 1.26 seconds
Started Mar 31 12:59:30 PM PDT 24
Finished Mar 31 12:59:32 PM PDT 24
Peak memory 204652 kb
Host smart-e65e2c1e-d441-4be7-9680-6b9e41ec1acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433037537 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.433037537
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.240282739
Short name T216
Test name
Test status
Simulation time 17324556 ps
CPU time 0.7 seconds
Started Mar 31 12:59:51 PM PDT 24
Finished Mar 31 12:59:52 PM PDT 24
Peak memory 204784 kb
Host smart-64e970d7-41e4-4da1-a095-46c9ea3c5953
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240282739 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.240282739
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.2535845016
Short name T186
Test name
Test status
Simulation time 2607411715 ps
CPU time 6.76 seconds
Started Mar 31 12:59:57 PM PDT 24
Finished Mar 31 01:00:04 PM PDT 24
Peak memory 205124 kb
Host smart-1b78b672-8c2f-4c6a-9ec2-20ef64449180
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2535845016 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.2535845016
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.1707822063
Short name T188
Test name
Test status
Simulation time 3477683827 ps
CPU time 6.05 seconds
Started Mar 31 12:59:52 PM PDT 24
Finished Mar 31 12:59:59 PM PDT 24
Peak memory 205092 kb
Host smart-17a65c6d-011e-4c0b-8199-5017a9f36694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707822063 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.1707822063
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.2811355469
Short name T175
Test name
Test status
Simulation time 21417261 ps
CPU time 0.71 seconds
Started Mar 31 12:59:52 PM PDT 24
Finished Mar 31 12:59:53 PM PDT 24
Peak memory 204784 kb
Host smart-2b90fc13-4925-4957-85c0-48c0f33778dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811355469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.2811355469
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.4214421293
Short name T12
Test name
Test status
Simulation time 1899582538 ps
CPU time 8.67 seconds
Started Mar 31 12:59:51 PM PDT 24
Finished Mar 31 01:00:00 PM PDT 24
Peak memory 205116 kb
Host smart-20c757ce-626d-44e9-a8c8-0290e5a5854b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214421293 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.4214421293
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.1107771638
Short name T222
Test name
Test status
Simulation time 1533764123 ps
CPU time 6.26 seconds
Started Mar 31 12:59:53 PM PDT 24
Finished Mar 31 01:00:00 PM PDT 24
Peak memory 205164 kb
Host smart-55c02770-257a-43a9-86a9-c712f390127a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107771638 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.1107771638
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.484051098
Short name T179
Test name
Test status
Simulation time 8753562772 ps
CPU time 12.33 seconds
Started Mar 31 12:59:55 PM PDT 24
Finished Mar 31 01:00:07 PM PDT 24
Peak memory 213408 kb
Host smart-bd0fee0e-7ea0-4604-a53f-2272c59c693d
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=484051098 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_t
l_access.484051098
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.3001509260
Short name T187
Test name
Test status
Simulation time 1559401027 ps
CPU time 7.97 seconds
Started Mar 31 12:59:51 PM PDT 24
Finished Mar 31 12:59:59 PM PDT 24
Peak memory 205052 kb
Host smart-85bbf052-3de0-4b0b-bdbd-4b539d338f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001509260 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.3001509260
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.2968782994
Short name T185
Test name
Test status
Simulation time 779494974 ps
CPU time 4.05 seconds
Started Mar 31 12:59:52 PM PDT 24
Finished Mar 31 12:59:57 PM PDT 24
Peak memory 205124 kb
Host smart-94aec15f-bc19-4374-8acf-da4ccd0e7518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968782994 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.2968782994
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.1271124384
Short name T176
Test name
Test status
Simulation time 2090119301 ps
CPU time 4.96 seconds
Started Mar 31 12:59:51 PM PDT 24
Finished Mar 31 12:59:56 PM PDT 24
Peak memory 205044 kb
Host smart-950cc2f2-a738-491f-8873-da0399086e16
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1271124384 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.1271124384
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.1446156342
Short name T180
Test name
Test status
Simulation time 2713304167 ps
CPU time 5.95 seconds
Started Mar 31 12:59:52 PM PDT 24
Finished Mar 31 12:59:59 PM PDT 24
Peak memory 205212 kb
Host smart-4961735a-7833-4fc4-bd54-ae34ea299217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446156342 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.1446156342
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_stress_all.3023405201
Short name T24
Test name
Test status
Simulation time 3167018248 ps
CPU time 9.57 seconds
Started Mar 31 12:59:57 PM PDT 24
Finished Mar 31 01:00:06 PM PDT 24
Peak memory 205032 kb
Host smart-e6115c60-470b-4199-ae77-d08d96dded8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023405201 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.3023405201
Directory /workspace/12.rv_dm_stress_all/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.656219859
Short name T126
Test name
Test status
Simulation time 28980200 ps
CPU time 0.75 seconds
Started Mar 31 01:00:03 PM PDT 24
Finished Mar 31 01:00:04 PM PDT 24
Peak memory 204724 kb
Host smart-a879774d-f322-4042-bc04-e5d658e8f1f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656219859 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.656219859
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.3627636293
Short name T236
Test name
Test status
Simulation time 13904920881 ps
CPU time 42.59 seconds
Started Mar 31 01:00:06 PM PDT 24
Finished Mar 31 01:00:49 PM PDT 24
Peak memory 213472 kb
Host smart-ef2e3f27-d2cb-414d-97dd-afeb6a6fac39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627636293 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.3627636293
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.4260401270
Short name T238
Test name
Test status
Simulation time 4460431139 ps
CPU time 7.08 seconds
Started Mar 31 12:59:57 PM PDT 24
Finished Mar 31 01:00:04 PM PDT 24
Peak memory 205420 kb
Host smart-77bc5dec-8f25-4197-8d88-6536910bb5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260401270 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.4260401270
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.4280557393
Short name T165
Test name
Test status
Simulation time 5583955965 ps
CPU time 19.28 seconds
Started Mar 31 01:00:01 PM PDT 24
Finished Mar 31 01:00:20 PM PDT 24
Peak memory 205372 kb
Host smart-785d8494-8725-4ea9-a1de-e8428aec32c1
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4280557393 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_
tl_access.4280557393
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.3268885984
Short name T68
Test name
Test status
Simulation time 6376584597 ps
CPU time 16.68 seconds
Started Mar 31 01:00:04 PM PDT 24
Finished Mar 31 01:00:20 PM PDT 24
Peak memory 213380 kb
Host smart-e9929d92-c705-4a4d-a784-9a45a0fda905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268885984 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.3268885984
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.345214205
Short name T149
Test name
Test status
Simulation time 14584914 ps
CPU time 0.69 seconds
Started Mar 31 01:00:03 PM PDT 24
Finished Mar 31 01:00:04 PM PDT 24
Peak memory 204800 kb
Host smart-e6d51ae6-3640-4b59-9146-77514df14f43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345214205 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.345214205
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.3562286723
Short name T7
Test name
Test status
Simulation time 1308089390 ps
CPU time 2.93 seconds
Started Mar 31 12:59:57 PM PDT 24
Finished Mar 31 01:00:00 PM PDT 24
Peak memory 205112 kb
Host smart-28fe2a81-e293-4acd-9f88-b6b08a6de31e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3562286723 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.3562286723
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.1869908168
Short name T202
Test name
Test status
Simulation time 802455468 ps
CPU time 3.2 seconds
Started Mar 31 01:00:05 PM PDT 24
Finished Mar 31 01:00:08 PM PDT 24
Peak memory 205104 kb
Host smart-d7f59564-64f4-423e-92cc-5130dc975d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869908168 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.1869908168
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.3969631628
Short name T80
Test name
Test status
Simulation time 28074929 ps
CPU time 0.69 seconds
Started Mar 31 01:00:04 PM PDT 24
Finished Mar 31 01:00:05 PM PDT 24
Peak memory 204788 kb
Host smart-6cc61975-a6ab-430c-a067-5c3196420cb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969631628 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.3969631628
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.1579771585
Short name T207
Test name
Test status
Simulation time 17745950015 ps
CPU time 15.9 seconds
Started Mar 31 01:00:03 PM PDT 24
Finished Mar 31 01:00:19 PM PDT 24
Peak memory 215680 kb
Host smart-7410502d-f0f7-4082-92b9-c9831eeadd65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579771585 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.1579771585
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.497090189
Short name T227
Test name
Test status
Simulation time 806946511 ps
CPU time 1.83 seconds
Started Mar 31 12:59:58 PM PDT 24
Finished Mar 31 01:00:00 PM PDT 24
Peak memory 205156 kb
Host smart-40de4596-6499-406e-b538-78cea817a704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497090189 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.497090189
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.2617621481
Short name T211
Test name
Test status
Simulation time 3253013317 ps
CPU time 11 seconds
Started Mar 31 12:59:57 PM PDT 24
Finished Mar 31 01:00:08 PM PDT 24
Peak memory 213328 kb
Host smart-de5d1e97-6d77-46cd-a6f8-09edd4e5ad3c
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2617621481 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_
tl_access.2617621481
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.2792972836
Short name T200
Test name
Test status
Simulation time 11623595945 ps
CPU time 20.47 seconds
Started Mar 31 01:00:04 PM PDT 24
Finished Mar 31 01:00:24 PM PDT 24
Peak memory 205220 kb
Host smart-afc21305-7c80-4a3f-accc-0004b54b73c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792972836 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.2792972836
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.3517762905
Short name T3
Test name
Test status
Simulation time 18574684 ps
CPU time 0.73 seconds
Started Mar 31 01:00:05 PM PDT 24
Finished Mar 31 01:00:06 PM PDT 24
Peak memory 204768 kb
Host smart-f5d61920-095c-42ac-8be0-e918cb4d36e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517762905 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.3517762905
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.1401563675
Short name T189
Test name
Test status
Simulation time 9224163725 ps
CPU time 49.61 seconds
Started Mar 31 01:00:03 PM PDT 24
Finished Mar 31 01:00:52 PM PDT 24
Peak memory 213460 kb
Host smart-86d89e29-46e0-4853-88ca-eecdf8d52fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401563675 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.1401563675
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.348777777
Short name T229
Test name
Test status
Simulation time 791200858 ps
CPU time 2.8 seconds
Started Mar 31 01:00:01 PM PDT 24
Finished Mar 31 01:00:04 PM PDT 24
Peak memory 205140 kb
Host smart-dd334e5e-83e9-40f5-a819-69ce2d390d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348777777 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.348777777
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.3190611516
Short name T204
Test name
Test status
Simulation time 1333275139 ps
CPU time 5.7 seconds
Started Mar 31 01:00:03 PM PDT 24
Finished Mar 31 01:00:09 PM PDT 24
Peak memory 205104 kb
Host smart-1e7e92a1-fe82-4a76-b3f5-192d165e4c5b
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3190611516 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_
tl_access.3190611516
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.2978042781
Short name T205
Test name
Test status
Simulation time 14236758066 ps
CPU time 48.07 seconds
Started Mar 31 01:00:03 PM PDT 24
Finished Mar 31 01:00:51 PM PDT 24
Peak memory 213392 kb
Host smart-78a1731d-51c5-4b39-9577-bc774ff75e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978042781 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.2978042781
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.1507541699
Short name T162
Test name
Test status
Simulation time 15387708 ps
CPU time 0.71 seconds
Started Mar 31 01:00:11 PM PDT 24
Finished Mar 31 01:00:11 PM PDT 24
Peak memory 204804 kb
Host smart-3146dd68-4e9e-416a-bb6a-81942b554a26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507541699 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.1507541699
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.1276063531
Short name T199
Test name
Test status
Simulation time 17282757139 ps
CPU time 21.88 seconds
Started Mar 31 01:00:05 PM PDT 24
Finished Mar 31 01:00:27 PM PDT 24
Peak memory 213452 kb
Host smart-8898053c-92ae-4327-8a3d-19debab7f479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276063531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.1276063531
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.3704488812
Short name T177
Test name
Test status
Simulation time 674494807 ps
CPU time 2.19 seconds
Started Mar 31 01:00:04 PM PDT 24
Finished Mar 31 01:00:06 PM PDT 24
Peak memory 205120 kb
Host smart-ba2b6435-4929-4cb2-9132-595e8ebb1528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704488812 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.3704488812
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.1517165651
Short name T232
Test name
Test status
Simulation time 3078594394 ps
CPU time 7.72 seconds
Started Mar 31 01:00:05 PM PDT 24
Finished Mar 31 01:00:13 PM PDT 24
Peak memory 213380 kb
Host smart-8599e1d7-56d9-4f7c-90ef-76d1cfa6e86c
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1517165651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_
tl_access.1517165651
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.3077363096
Short name T182
Test name
Test status
Simulation time 3228733597 ps
CPU time 5.54 seconds
Started Mar 31 01:00:05 PM PDT 24
Finished Mar 31 01:00:10 PM PDT 24
Peak memory 213380 kb
Host smart-e150f75b-38b2-436a-b018-8dbd02433dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077363096 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.3077363096
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.1803271789
Short name T79
Test name
Test status
Simulation time 17247031 ps
CPU time 0.72 seconds
Started Mar 31 01:00:05 PM PDT 24
Finished Mar 31 01:00:05 PM PDT 24
Peak memory 204764 kb
Host smart-2be13d5b-5575-4f3c-bf1d-ed73c8e93852
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803271789 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.1803271789
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.2526179725
Short name T224
Test name
Test status
Simulation time 2025813913 ps
CPU time 9.38 seconds
Started Mar 31 01:00:04 PM PDT 24
Finished Mar 31 01:00:14 PM PDT 24
Peak memory 205140 kb
Host smart-34c2c402-b032-4661-baa2-f661513e5e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526179725 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.2526179725
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.1157181715
Short name T98
Test name
Test status
Simulation time 6648204618 ps
CPU time 12.11 seconds
Started Mar 31 01:00:04 PM PDT 24
Finished Mar 31 01:00:16 PM PDT 24
Peak memory 213304 kb
Host smart-9eb9e3c9-a61f-469b-a1a3-7d248787fdf0
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1157181715 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_
tl_access.1157181715
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.1365456847
Short name T167
Test name
Test status
Simulation time 1047194491 ps
CPU time 3.11 seconds
Started Mar 31 01:00:05 PM PDT 24
Finished Mar 31 01:00:09 PM PDT 24
Peak memory 205100 kb
Host smart-a08d2b17-0e18-42ea-9e3d-b93b4a975a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365456847 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.1365456847
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.2306214517
Short name T168
Test name
Test status
Simulation time 35608559 ps
CPU time 0.71 seconds
Started Mar 31 01:00:11 PM PDT 24
Finished Mar 31 01:00:12 PM PDT 24
Peak memory 204772 kb
Host smart-ad841f5a-4083-4b0a-bac7-b066ecff0774
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306214517 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.2306214517
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.2807423867
Short name T194
Test name
Test status
Simulation time 7744979061 ps
CPU time 9.86 seconds
Started Mar 31 01:00:10 PM PDT 24
Finished Mar 31 01:00:20 PM PDT 24
Peak memory 215088 kb
Host smart-2d479879-1e76-4a95-ac5e-b4c4e3182525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807423867 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.2807423867
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.2627131019
Short name T170
Test name
Test status
Simulation time 2527320949 ps
CPU time 8.63 seconds
Started Mar 31 01:00:11 PM PDT 24
Finished Mar 31 01:00:20 PM PDT 24
Peak memory 213380 kb
Host smart-c044ca63-ddd9-463c-89a9-1a304f7d618c
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2627131019 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_
tl_access.2627131019
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.3492666767
Short name T197
Test name
Test status
Simulation time 654506071 ps
CPU time 2.81 seconds
Started Mar 31 01:00:05 PM PDT 24
Finished Mar 31 01:00:08 PM PDT 24
Peak memory 205104 kb
Host smart-b79674a3-dffb-4375-880b-c3edc44cd8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492666767 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.3492666767
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.1141681918
Short name T192
Test name
Test status
Simulation time 22856485 ps
CPU time 0.74 seconds
Started Mar 31 12:59:39 PM PDT 24
Finished Mar 31 12:59:40 PM PDT 24
Peak memory 204812 kb
Host smart-e2c98eee-b7d9-438a-8adb-c9d7814f50c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141681918 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.1141681918
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.3454925917
Short name T178
Test name
Test status
Simulation time 9093097859 ps
CPU time 19.25 seconds
Started Mar 31 12:59:41 PM PDT 24
Finished Mar 31 01:00:00 PM PDT 24
Peak memory 205216 kb
Host smart-730fa73f-a0ff-4d2e-a16a-ce7303e9f5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454925917 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.3454925917
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.563548076
Short name T191
Test name
Test status
Simulation time 2311693304 ps
CPU time 10.23 seconds
Started Mar 31 12:59:39 PM PDT 24
Finished Mar 31 12:59:49 PM PDT 24
Peak memory 205128 kb
Host smart-5b1740e3-1bc8-49a3-bfb9-80ca197606d9
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=563548076 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_tl
_access.563548076
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.468845379
Short name T163
Test name
Test status
Simulation time 182087033 ps
CPU time 0.84 seconds
Started Mar 31 12:59:42 PM PDT 24
Finished Mar 31 12:59:43 PM PDT 24
Peak memory 204664 kb
Host smart-132a9d7c-066a-4ff4-b42b-ded0746020cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468845379 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.468845379
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.4115169720
Short name T9
Test name
Test status
Simulation time 3647578987 ps
CPU time 9.75 seconds
Started Mar 31 12:59:43 PM PDT 24
Finished Mar 31 12:59:52 PM PDT 24
Peak memory 213296 kb
Host smart-945a9e5c-03fe-49c2-983e-3db081311ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115169720 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.4115169720
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.3439597113
Short name T38
Test name
Test status
Simulation time 388953972 ps
CPU time 1.42 seconds
Started Mar 31 12:59:40 PM PDT 24
Finished Mar 31 12:59:42 PM PDT 24
Peak memory 229160 kb
Host smart-798f9638-334d-4552-a494-5e36ff6722b4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439597113 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.3439597113
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all.4224973099
Short name T19
Test name
Test status
Simulation time 1558348435 ps
CPU time 3.27 seconds
Started Mar 31 12:59:43 PM PDT 24
Finished Mar 31 12:59:46 PM PDT 24
Peak memory 204952 kb
Host smart-9bb610d8-fc97-4959-8aa1-dfdfc0e8f180
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224973099 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.4224973099
Directory /workspace/2.rv_dm_stress_all/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.566883463
Short name T63
Test name
Test status
Simulation time 37943320 ps
CPU time 0.69 seconds
Started Mar 31 01:00:11 PM PDT 24
Finished Mar 31 01:00:12 PM PDT 24
Peak memory 204772 kb
Host smart-8f60aed8-b49f-4a47-b819-9011a6a73e40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566883463 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.566883463
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.647088998
Short name T66
Test name
Test status
Simulation time 20084115 ps
CPU time 0.72 seconds
Started Mar 31 01:00:11 PM PDT 24
Finished Mar 31 01:00:12 PM PDT 24
Peak memory 204772 kb
Host smart-801e929f-7cc8-4137-aee1-1e7637e6afc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647088998 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.647088998
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.2615126477
Short name T155
Test name
Test status
Simulation time 53539028 ps
CPU time 0.7 seconds
Started Mar 31 01:00:16 PM PDT 24
Finished Mar 31 01:00:17 PM PDT 24
Peak memory 204676 kb
Host smart-08b76274-8b6d-45b3-9410-ed2a8aa94e24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615126477 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.2615126477
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.2307227786
Short name T152
Test name
Test status
Simulation time 24005132 ps
CPU time 0.73 seconds
Started Mar 31 01:00:14 PM PDT 24
Finished Mar 31 01:00:15 PM PDT 24
Peak memory 204964 kb
Host smart-964a2c78-f537-456f-b5b5-018be04ae60b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307227786 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.2307227786
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.3170859784
Short name T147
Test name
Test status
Simulation time 53708493 ps
CPU time 0.75 seconds
Started Mar 31 01:00:10 PM PDT 24
Finished Mar 31 01:00:11 PM PDT 24
Peak memory 204760 kb
Host smart-f8e81c1e-6c3a-487f-8316-44164dc3733e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170859784 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.3170859784
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.488924304
Short name T145
Test name
Test status
Simulation time 17296197 ps
CPU time 0.7 seconds
Started Mar 31 01:00:10 PM PDT 24
Finished Mar 31 01:00:11 PM PDT 24
Peak memory 204792 kb
Host smart-06043783-e08e-4d8c-93ae-3e7e6a5f6f8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488924304 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.488924304
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.3442391175
Short name T50
Test name
Test status
Simulation time 64112901 ps
CPU time 0.74 seconds
Started Mar 31 01:00:16 PM PDT 24
Finished Mar 31 01:00:17 PM PDT 24
Peak memory 204580 kb
Host smart-f6e8f922-4a19-423a-b6ac-f3514f2c3784
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442391175 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.3442391175
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.1453962607
Short name T124
Test name
Test status
Simulation time 18793925 ps
CPU time 0.72 seconds
Started Mar 31 01:00:16 PM PDT 24
Finished Mar 31 01:00:16 PM PDT 24
Peak memory 204784 kb
Host smart-b2513cc0-801b-4dad-a198-179dac29be6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453962607 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.1453962607
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.4154151844
Short name T208
Test name
Test status
Simulation time 17878881 ps
CPU time 0.73 seconds
Started Mar 31 01:00:14 PM PDT 24
Finished Mar 31 01:00:15 PM PDT 24
Peak memory 204964 kb
Host smart-31c57dd8-ed26-4573-90cf-aecd714b93b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154151844 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.4154151844
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.2844034582
Short name T125
Test name
Test status
Simulation time 90354730 ps
CPU time 0.73 seconds
Started Mar 31 12:59:41 PM PDT 24
Finished Mar 31 12:59:42 PM PDT 24
Peak memory 204740 kb
Host smart-cef9218a-3694-4111-8148-831a05241a78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844034582 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.2844034582
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.823700958
Short name T10
Test name
Test status
Simulation time 928033166 ps
CPU time 5.45 seconds
Started Mar 31 12:59:42 PM PDT 24
Finished Mar 31 12:59:48 PM PDT 24
Peak memory 205096 kb
Host smart-180c4b98-c8f8-40b3-a421-3976a961a7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823700958 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.823700958
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.789511448
Short name T223
Test name
Test status
Simulation time 818989906 ps
CPU time 2.16 seconds
Started Mar 31 12:59:40 PM PDT 24
Finished Mar 31 12:59:42 PM PDT 24
Peak memory 205076 kb
Host smart-3958823b-90bd-45ca-9085-0c432d86806f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=789511448 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_tl
_access.789511448
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.842002116
Short name T233
Test name
Test status
Simulation time 83522374 ps
CPU time 0.79 seconds
Started Mar 31 12:59:44 PM PDT 24
Finished Mar 31 12:59:46 PM PDT 24
Peak memory 204660 kb
Host smart-788d3560-20b4-4ad5-98c3-281e1643afc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842002116 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.842002116
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.835871609
Short name T206
Test name
Test status
Simulation time 10948287887 ps
CPU time 17.62 seconds
Started Mar 31 12:59:42 PM PDT 24
Finished Mar 31 12:59:59 PM PDT 24
Peak memory 213356 kb
Host smart-86353782-94e8-4cd3-824a-a28e3892fdf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835871609 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.835871609
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.18729304
Short name T39
Test name
Test status
Simulation time 120856995 ps
CPU time 1.07 seconds
Started Mar 31 12:59:39 PM PDT 24
Finished Mar 31 12:59:40 PM PDT 24
Peak memory 229392 kb
Host smart-000a1a19-473f-4069-917d-935a88e582e8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18729304 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.18729304
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.4220583618
Short name T65
Test name
Test status
Simulation time 46692206 ps
CPU time 0.71 seconds
Started Mar 31 01:00:11 PM PDT 24
Finished Mar 31 01:00:12 PM PDT 24
Peak memory 204780 kb
Host smart-fcf02ca9-9d57-4368-8484-f0e1d95c28be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220583618 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.4220583618
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.2085523451
Short name T127
Test name
Test status
Simulation time 214459913 ps
CPU time 0.73 seconds
Started Mar 31 01:00:10 PM PDT 24
Finished Mar 31 01:00:11 PM PDT 24
Peak memory 204792 kb
Host smart-2fe0fddc-7f4d-438a-96da-d6cec67fe93a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085523451 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.2085523451
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.3208402285
Short name T41
Test name
Test status
Simulation time 68441243 ps
CPU time 0.71 seconds
Started Mar 31 01:00:16 PM PDT 24
Finished Mar 31 01:00:16 PM PDT 24
Peak memory 204784 kb
Host smart-5a38115d-ebdf-4bb3-b04d-33abb0462851
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208402285 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.3208402285
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.2069700873
Short name T231
Test name
Test status
Simulation time 179414166 ps
CPU time 0.69 seconds
Started Mar 31 01:00:14 PM PDT 24
Finished Mar 31 01:00:15 PM PDT 24
Peak memory 204740 kb
Host smart-196b5976-90e2-4f20-8c49-6c5cd24befaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069700873 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.2069700873
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.1065688004
Short name T59
Test name
Test status
Simulation time 42412491 ps
CPU time 0.7 seconds
Started Mar 31 01:00:17 PM PDT 24
Finished Mar 31 01:00:17 PM PDT 24
Peak memory 204780 kb
Host smart-a7f23281-8360-4229-b0c3-6b10f0405213
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065688004 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.1065688004
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.259643883
Short name T144
Test name
Test status
Simulation time 39086318 ps
CPU time 0.73 seconds
Started Mar 31 01:00:17 PM PDT 24
Finished Mar 31 01:00:18 PM PDT 24
Peak memory 204800 kb
Host smart-540c0ba0-b9d6-410d-af18-308dfec0ad92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259643883 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.259643883
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.2162007258
Short name T48
Test name
Test status
Simulation time 15808262 ps
CPU time 0.71 seconds
Started Mar 31 01:00:17 PM PDT 24
Finished Mar 31 01:00:18 PM PDT 24
Peak memory 204816 kb
Host smart-795aaf9f-b6a5-4363-852c-8166e79f098f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162007258 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.2162007258
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.1988509624
Short name T201
Test name
Test status
Simulation time 54093851 ps
CPU time 0.69 seconds
Started Mar 31 01:00:15 PM PDT 24
Finished Mar 31 01:00:16 PM PDT 24
Peak memory 204740 kb
Host smart-861245f7-6554-408d-bb3f-40376b345b34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988509624 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.1988509624
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.4019912252
Short name T158
Test name
Test status
Simulation time 29308383 ps
CPU time 0.69 seconds
Started Mar 31 01:00:20 PM PDT 24
Finished Mar 31 01:00:21 PM PDT 24
Peak memory 204804 kb
Host smart-b846549e-9897-4e46-997a-3990582ff184
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019912252 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.4019912252
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.2855758032
Short name T160
Test name
Test status
Simulation time 16864381 ps
CPU time 0.7 seconds
Started Mar 31 01:00:15 PM PDT 24
Finished Mar 31 01:00:16 PM PDT 24
Peak memory 204692 kb
Host smart-20c6cd9c-355d-41f8-851b-aa56d78be1a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855758032 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.2855758032
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.480314319
Short name T153
Test name
Test status
Simulation time 15818544 ps
CPU time 0.71 seconds
Started Mar 31 12:59:47 PM PDT 24
Finished Mar 31 12:59:49 PM PDT 24
Peak memory 204808 kb
Host smart-a30bed52-3d4f-44a1-8137-11aad822f980
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480314319 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.480314319
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.3848553918
Short name T196
Test name
Test status
Simulation time 6694477501 ps
CPU time 27.62 seconds
Started Mar 31 12:59:46 PM PDT 24
Finished Mar 31 01:00:14 PM PDT 24
Peak memory 213404 kb
Host smart-a9969f94-407a-45f8-932f-25386ca15e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848553918 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.3848553918
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.2304374850
Short name T190
Test name
Test status
Simulation time 534772206 ps
CPU time 2.25 seconds
Started Mar 31 12:59:46 PM PDT 24
Finished Mar 31 12:59:49 PM PDT 24
Peak memory 205120 kb
Host smart-f1b43126-9ab5-4b6a-b06e-895340036f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304374850 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.2304374850
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.2458773589
Short name T164
Test name
Test status
Simulation time 3809090490 ps
CPU time 11.07 seconds
Started Mar 31 12:59:46 PM PDT 24
Finished Mar 31 12:59:58 PM PDT 24
Peak memory 214500 kb
Host smart-6e861da9-d02a-4687-8f5a-c52093cfe3cd
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2458773589 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.2458773589
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.4252938880
Short name T214
Test name
Test status
Simulation time 57762765 ps
CPU time 0.85 seconds
Started Mar 31 12:59:47 PM PDT 24
Finished Mar 31 12:59:48 PM PDT 24
Peak memory 204672 kb
Host smart-2894a3f8-8f1f-4e9e-a3fd-5b3c360ba382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252938880 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.4252938880
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.2986075502
Short name T169
Test name
Test status
Simulation time 1989480152 ps
CPU time 7.22 seconds
Started Mar 31 12:59:47 PM PDT 24
Finished Mar 31 12:59:54 PM PDT 24
Peak memory 205076 kb
Host smart-1bc8fd30-abfa-4588-8d4f-2957546156ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986075502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.2986075502
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.103885841
Short name T151
Test name
Test status
Simulation time 23882245 ps
CPU time 0.72 seconds
Started Mar 31 01:00:15 PM PDT 24
Finished Mar 31 01:00:16 PM PDT 24
Peak memory 204724 kb
Host smart-db52664a-ba37-4999-97f9-093815c4d217
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103885841 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.103885841
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.3125511123
Short name T148
Test name
Test status
Simulation time 20588072 ps
CPU time 0.73 seconds
Started Mar 31 01:00:23 PM PDT 24
Finished Mar 31 01:00:24 PM PDT 24
Peak memory 204776 kb
Host smart-21590ca5-ce8d-4e60-b39f-4f550dd69239
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125511123 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.3125511123
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.2099826966
Short name T31
Test name
Test status
Simulation time 21851991 ps
CPU time 0.75 seconds
Started Mar 31 01:00:21 PM PDT 24
Finished Mar 31 01:00:22 PM PDT 24
Peak memory 204792 kb
Host smart-7fd0f38b-419e-4246-a4aa-ef3f5f8bb78a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099826966 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.2099826966
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.1312490448
Short name T157
Test name
Test status
Simulation time 24730797 ps
CPU time 0.66 seconds
Started Mar 31 01:00:21 PM PDT 24
Finished Mar 31 01:00:22 PM PDT 24
Peak memory 204760 kb
Host smart-54db2881-9f96-417b-91b7-abc56c4ace8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312490448 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.1312490448
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.159030343
Short name T146
Test name
Test status
Simulation time 42478641 ps
CPU time 0.73 seconds
Started Mar 31 01:00:22 PM PDT 24
Finished Mar 31 01:00:22 PM PDT 24
Peak memory 204800 kb
Host smart-0e0e5e04-d857-4531-a5f3-a542f913385a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159030343 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.159030343
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.3611901991
Short name T78
Test name
Test status
Simulation time 43007080 ps
CPU time 0.69 seconds
Started Mar 31 01:00:22 PM PDT 24
Finished Mar 31 01:00:23 PM PDT 24
Peak memory 204724 kb
Host smart-8fddc46b-877e-4d11-9b2f-18dcba1d194c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611901991 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.3611901991
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.443455430
Short name T184
Test name
Test status
Simulation time 20367132 ps
CPU time 0.72 seconds
Started Mar 31 01:00:22 PM PDT 24
Finished Mar 31 01:00:23 PM PDT 24
Peak memory 204740 kb
Host smart-04f74042-40fc-4399-9580-ace55fb41487
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443455430 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.443455430
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.603184983
Short name T156
Test name
Test status
Simulation time 19555952 ps
CPU time 0.7 seconds
Started Mar 31 01:00:20 PM PDT 24
Finished Mar 31 01:00:21 PM PDT 24
Peak memory 204800 kb
Host smart-609b24ed-dce3-440a-99bc-b318516f7b4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603184983 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.603184983
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.39974425
Short name T47
Test name
Test status
Simulation time 61490136 ps
CPU time 0.7 seconds
Started Mar 31 01:00:30 PM PDT 24
Finished Mar 31 01:00:32 PM PDT 24
Peak memory 204676 kb
Host smart-931b7a3b-6903-4a56-a325-9baff3454c51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39974425 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.39974425
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.2798242639
Short name T166
Test name
Test status
Simulation time 26791121 ps
CPU time 0.69 seconds
Started Mar 31 01:00:26 PM PDT 24
Finished Mar 31 01:00:27 PM PDT 24
Peak memory 204808 kb
Host smart-7fec8e7d-6ddf-4939-af08-06ab18504882
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798242639 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.2798242639
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_stress_all.1899562026
Short name T1
Test name
Test status
Simulation time 1423488444 ps
CPU time 5.49 seconds
Started Mar 31 01:00:27 PM PDT 24
Finished Mar 31 01:00:32 PM PDT 24
Peak memory 205060 kb
Host smart-21f94426-0e4a-441e-897d-92c3a6f9b053
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899562026 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.1899562026
Directory /workspace/49.rv_dm_stress_all/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.1169358056
Short name T154
Test name
Test status
Simulation time 24083996 ps
CPU time 0.7 seconds
Started Mar 31 12:59:45 PM PDT 24
Finished Mar 31 12:59:46 PM PDT 24
Peak memory 204788 kb
Host smart-d7374091-8c82-45d0-9915-0eb0d6a64c8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169358056 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.1169358056
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.3366939313
Short name T22
Test name
Test status
Simulation time 18023258459 ps
CPU time 66.19 seconds
Started Mar 31 12:59:46 PM PDT 24
Finished Mar 31 01:00:52 PM PDT 24
Peak memory 213452 kb
Host smart-2ed2e642-5259-41a6-b151-a55ff613d9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366939313 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.3366939313
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.3625923192
Short name T172
Test name
Test status
Simulation time 1715529265 ps
CPU time 7.72 seconds
Started Mar 31 12:59:48 PM PDT 24
Finished Mar 31 12:59:57 PM PDT 24
Peak memory 205112 kb
Host smart-3255af57-d2f2-4da5-98ce-921f851c461a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625923192 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.3625923192
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.789099751
Short name T217
Test name
Test status
Simulation time 1942968350 ps
CPU time 7.29 seconds
Started Mar 31 12:59:46 PM PDT 24
Finished Mar 31 12:59:53 PM PDT 24
Peak memory 205068 kb
Host smart-099d1197-26b0-420c-8985-2051489350f6
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=789099751 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_tl
_access.789099751
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.989172473
Short name T96
Test name
Test status
Simulation time 447722060 ps
CPU time 2.82 seconds
Started Mar 31 12:59:47 PM PDT 24
Finished Mar 31 12:59:50 PM PDT 24
Peak memory 205148 kb
Host smart-7f8f2116-e804-403a-8f8c-3067b5c5ea19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989172473 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.989172473
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.112018202
Short name T215
Test name
Test status
Simulation time 57828937 ps
CPU time 0.71 seconds
Started Mar 31 12:59:53 PM PDT 24
Finished Mar 31 12:59:54 PM PDT 24
Peak memory 204800 kb
Host smart-cadd6085-3a55-4c42-aaaf-e0738fd66c79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112018202 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.112018202
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.2165567843
Short name T23
Test name
Test status
Simulation time 25362599656 ps
CPU time 80.55 seconds
Started Mar 31 12:59:53 PM PDT 24
Finished Mar 31 01:01:14 PM PDT 24
Peak memory 213404 kb
Host smart-078bbfd1-d709-481b-b783-ad4235c32ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165567843 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.2165567843
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.3409083525
Short name T230
Test name
Test status
Simulation time 9574163211 ps
CPU time 29.9 seconds
Started Mar 31 12:59:46 PM PDT 24
Finished Mar 31 01:00:16 PM PDT 24
Peak memory 215028 kb
Host smart-32042fe9-34bd-4ce6-b137-9dcc1190109d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409083525 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.3409083525
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.1019404763
Short name T237
Test name
Test status
Simulation time 6482536842 ps
CPU time 23.85 seconds
Started Mar 31 12:59:46 PM PDT 24
Finished Mar 31 01:00:10 PM PDT 24
Peak memory 214588 kb
Host smart-778c3606-1257-43a1-81ae-9549bafd5b08
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1019404763 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t
l_access.1019404763
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.1075950573
Short name T58
Test name
Test status
Simulation time 711840776 ps
CPU time 1.6 seconds
Started Mar 31 12:59:44 PM PDT 24
Finished Mar 31 12:59:45 PM PDT 24
Peak memory 205136 kb
Host smart-acf257c5-ce3e-4bf8-b055-5008a591f807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075950573 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.1075950573
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.3806850579
Short name T161
Test name
Test status
Simulation time 55418958 ps
CPU time 0.69 seconds
Started Mar 31 12:59:47 PM PDT 24
Finished Mar 31 12:59:48 PM PDT 24
Peak memory 204744 kb
Host smart-e9ac6c9e-721f-40d3-bc8a-54561a995b02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806850579 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.3806850579
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.955190964
Short name T226
Test name
Test status
Simulation time 25472133847 ps
CPU time 105.9 seconds
Started Mar 31 12:59:46 PM PDT 24
Finished Mar 31 01:01:32 PM PDT 24
Peak memory 213348 kb
Host smart-663a4f0a-531c-49da-a363-d59170df05ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955190964 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.955190964
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.1265167125
Short name T13
Test name
Test status
Simulation time 940187736 ps
CPU time 3.44 seconds
Started Mar 31 12:59:46 PM PDT 24
Finished Mar 31 12:59:50 PM PDT 24
Peak memory 205112 kb
Host smart-93bb09e6-8ee1-4100-b743-127730faa7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265167125 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.1265167125
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.3685261689
Short name T64
Test name
Test status
Simulation time 3721988629 ps
CPU time 9.05 seconds
Started Mar 31 12:59:49 PM PDT 24
Finished Mar 31 12:59:59 PM PDT 24
Peak memory 213360 kb
Host smart-3436b959-970a-4008-bf60-a030810830ed
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3685261689 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.3685261689
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.105983993
Short name T218
Test name
Test status
Simulation time 4400152805 ps
CPU time 3.66 seconds
Started Mar 31 12:59:46 PM PDT 24
Finished Mar 31 12:59:50 PM PDT 24
Peak memory 205068 kb
Host smart-9a132dd4-7a6a-43e0-bb5f-31a8938959f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105983993 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.105983993
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.628444867
Short name T183
Test name
Test status
Simulation time 19673610 ps
CPU time 0.69 seconds
Started Mar 31 12:59:46 PM PDT 24
Finished Mar 31 12:59:47 PM PDT 24
Peak memory 204828 kb
Host smart-08f225ba-3a8c-4b07-9731-d9360564bb54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628444867 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.628444867
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.4220573474
Short name T234
Test name
Test status
Simulation time 10849679910 ps
CPU time 21.42 seconds
Started Mar 31 12:59:52 PM PDT 24
Finished Mar 31 01:00:14 PM PDT 24
Peak memory 213460 kb
Host smart-01ced541-16b5-41ee-bd31-bcc345a96bba
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4220573474 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t
l_access.4220573474
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.4049408546
Short name T67
Test name
Test status
Simulation time 2795810258 ps
CPU time 5.45 seconds
Started Mar 31 12:59:47 PM PDT 24
Finished Mar 31 12:59:53 PM PDT 24
Peak memory 205188 kb
Host smart-b8d4ce2f-9189-4450-8ca6-1fb4584846b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049408546 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.4049408546
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_stress_all.646475967
Short name T25
Test name
Test status
Simulation time 3560616393 ps
CPU time 6.8 seconds
Started Mar 31 12:59:47 PM PDT 24
Finished Mar 31 12:59:55 PM PDT 24
Peak memory 205068 kb
Host smart-6865e33c-2c41-450c-9f27-93a1a76855db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646475967 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.646475967
Directory /workspace/8.rv_dm_stress_all/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.305772564
Short name T123
Test name
Test status
Simulation time 33783462 ps
CPU time 0.7 seconds
Started Mar 31 12:59:57 PM PDT 24
Finished Mar 31 12:59:57 PM PDT 24
Peak memory 204768 kb
Host smart-d2c297ad-fc2a-47e2-a8b6-aa519cd45c8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305772564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.305772564
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.3283301436
Short name T203
Test name
Test status
Simulation time 4941693872 ps
CPU time 11.76 seconds
Started Mar 31 12:59:54 PM PDT 24
Finished Mar 31 01:00:06 PM PDT 24
Peak memory 215356 kb
Host smart-c16a1e29-1419-4c8e-9846-907b5970d3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283301436 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.3283301436
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.794191115
Short name T235
Test name
Test status
Simulation time 880438368 ps
CPU time 4.99 seconds
Started Mar 31 12:59:53 PM PDT 24
Finished Mar 31 12:59:58 PM PDT 24
Peak memory 205064 kb
Host smart-6845f884-8f6f-4ad5-ae9d-27ab88259187
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=794191115 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_tl
_access.794191115
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.1528553703
Short name T220
Test name
Test status
Simulation time 3456141511 ps
CPU time 5.14 seconds
Started Mar 31 12:59:52 PM PDT 24
Finished Mar 31 12:59:57 PM PDT 24
Peak memory 205172 kb
Host smart-e670cc45-0413-48f8-904c-b7ac7c032ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528553703 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.1528553703
Directory /workspace/9.rv_dm_sba_tl_access/latest
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