Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
79.90 94.34 80.32 87.21 73.08 83.50 98.42 42.46


Total test records in report: 378
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html
T269 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.3814503850 Apr 02 12:28:52 PM PDT 24 Apr 02 12:28:55 PM PDT 24 494227779 ps
T270 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1056525797 Apr 02 12:28:51 PM PDT 24 Apr 02 12:28:56 PM PDT 24 2271105026 ps
T271 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1151832538 Apr 02 12:28:48 PM PDT 24 Apr 02 12:29:01 PM PDT 24 8905644911 ps
T272 /workspace/coverage/cover_reg_top/15.rv_dm_tap_fsm_rand_reset.779547329 Apr 02 12:28:58 PM PDT 24 Apr 02 12:29:11 PM PDT 24 7352491720 ps
T104 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3960916171 Apr 02 12:28:51 PM PDT 24 Apr 02 12:28:53 PM PDT 24 403126884 ps
T273 /workspace/coverage/cover_reg_top/24.rv_dm_tap_fsm_rand_reset.1853362676 Apr 02 12:29:25 PM PDT 24 Apr 02 12:30:06 PM PDT 24 11825684181 ps
T274 /workspace/coverage/cover_reg_top/23.rv_dm_tap_fsm_rand_reset.402049669 Apr 02 12:29:25 PM PDT 24 Apr 02 12:29:38 PM PDT 24 13814897242 ps
T275 /workspace/coverage/cover_reg_top/12.rv_dm_tap_fsm_rand_reset.2485531698 Apr 02 12:29:18 PM PDT 24 Apr 02 12:29:34 PM PDT 24 7281182236 ps
T133 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.814000426 Apr 02 12:29:34 PM PDT 24 Apr 02 12:29:44 PM PDT 24 2133955763 ps
T276 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.204768135 Apr 02 12:28:45 PM PDT 24 Apr 02 12:28:50 PM PDT 24 54147437 ps
T277 /workspace/coverage/cover_reg_top/32.rv_dm_tap_fsm_rand_reset.1450401494 Apr 02 12:29:24 PM PDT 24 Apr 02 12:29:39 PM PDT 24 5112187286 ps
T98 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.3000586816 Apr 02 12:28:51 PM PDT 24 Apr 02 12:29:20 PM PDT 24 3613126852 ps
T278 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.1739184656 Apr 02 12:28:58 PM PDT 24 Apr 02 12:29:07 PM PDT 24 1577501218 ps
T279 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.4064454801 Apr 02 12:28:45 PM PDT 24 Apr 02 12:28:47 PM PDT 24 48502849 ps
T280 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.3703626990 Apr 02 12:29:01 PM PDT 24 Apr 02 12:29:05 PM PDT 24 170829525 ps
T128 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.4149143015 Apr 02 12:28:50 PM PDT 24 Apr 02 12:29:08 PM PDT 24 3228769531 ps
T281 /workspace/coverage/cover_reg_top/21.rv_dm_tap_fsm_rand_reset.3416077131 Apr 02 12:29:15 PM PDT 24 Apr 02 12:29:33 PM PDT 24 4536342447 ps
T282 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.607239962 Apr 02 12:29:20 PM PDT 24 Apr 02 12:29:52 PM PDT 24 12154453140 ps
T126 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2247230727 Apr 02 12:28:53 PM PDT 24 Apr 02 12:29:02 PM PDT 24 1716379827 ps
T283 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.2878128804 Apr 02 12:29:24 PM PDT 24 Apr 02 12:29:25 PM PDT 24 97841110 ps
T284 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.899003892 Apr 02 12:28:51 PM PDT 24 Apr 02 12:28:53 PM PDT 24 194848766 ps
T285 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.134175137 Apr 02 12:28:51 PM PDT 24 Apr 02 12:28:52 PM PDT 24 33323069 ps
T286 /workspace/coverage/cover_reg_top/33.rv_dm_tap_fsm_rand_reset.3842405318 Apr 02 12:28:54 PM PDT 24 Apr 02 12:29:20 PM PDT 24 28382888231 ps
T287 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.1527697840 Apr 02 12:28:55 PM PDT 24 Apr 02 12:28:57 PM PDT 24 90624256 ps
T288 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2713633231 Apr 02 12:28:51 PM PDT 24 Apr 02 12:28:53 PM PDT 24 130175097 ps
T289 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.2909288814 Apr 02 12:28:53 PM PDT 24 Apr 02 12:29:00 PM PDT 24 270145619 ps
T290 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.930238950 Apr 02 12:28:51 PM PDT 24 Apr 02 12:29:03 PM PDT 24 643649767 ps
T291 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.3774475623 Apr 02 12:28:45 PM PDT 24 Apr 02 12:28:49 PM PDT 24 1474200072 ps
T292 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.603219505 Apr 02 12:28:52 PM PDT 24 Apr 02 12:28:54 PM PDT 24 1217785503 ps
T99 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1214218762 Apr 02 12:28:49 PM PDT 24 Apr 02 12:30:03 PM PDT 24 16606508574 ps
T293 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3286512973 Apr 02 12:29:59 PM PDT 24 Apr 02 12:30:06 PM PDT 24 34435210 ps
T100 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.713375512 Apr 02 12:30:00 PM PDT 24 Apr 02 12:30:03 PM PDT 24 46874311 ps
T132 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.4052528994 Apr 02 12:28:53 PM PDT 24 Apr 02 12:29:11 PM PDT 24 3077155988 ps
T294 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.313210029 Apr 02 12:28:43 PM PDT 24 Apr 02 12:28:45 PM PDT 24 16676635 ps
T295 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.4214814565 Apr 02 12:28:52 PM PDT 24 Apr 02 12:28:55 PM PDT 24 205035643 ps
T296 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3294200304 Apr 02 12:28:49 PM PDT 24 Apr 02 12:29:43 PM PDT 24 12681226953 ps
T101 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.4193401699 Apr 02 12:28:49 PM PDT 24 Apr 02 12:28:51 PM PDT 24 62202670 ps
T297 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.991988226 Apr 02 12:29:23 PM PDT 24 Apr 02 12:29:31 PM PDT 24 1833896499 ps
T298 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.3876908177 Apr 02 12:28:51 PM PDT 24 Apr 02 12:28:52 PM PDT 24 101396836 ps
T299 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.3482409573 Apr 02 12:29:17 PM PDT 24 Apr 02 12:29:20 PM PDT 24 654984167 ps
T130 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.3544212471 Apr 02 12:29:35 PM PDT 24 Apr 02 12:29:44 PM PDT 24 442837861 ps
T300 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.2482943356 Apr 02 12:29:10 PM PDT 24 Apr 02 12:29:15 PM PDT 24 352274646 ps
T123 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.3212514386 Apr 02 12:29:24 PM PDT 24 Apr 02 12:29:39 PM PDT 24 650386680 ps
T301 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.4198257074 Apr 02 12:28:49 PM PDT 24 Apr 02 12:28:55 PM PDT 24 246500062 ps
T302 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.182938529 Apr 02 12:30:00 PM PDT 24 Apr 02 12:30:03 PM PDT 24 492375661 ps
T303 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.4116427987 Apr 02 12:28:47 PM PDT 24 Apr 02 12:28:49 PM PDT 24 42600250 ps
T304 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.2740020896 Apr 02 12:28:50 PM PDT 24 Apr 02 12:29:56 PM PDT 24 5096792965 ps
T305 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.3613010779 Apr 02 12:28:57 PM PDT 24 Apr 02 12:28:58 PM PDT 24 156707112 ps
T306 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.4211103355 Apr 02 12:28:52 PM PDT 24 Apr 02 12:29:00 PM PDT 24 536734153 ps
T307 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1248185275 Apr 02 12:29:12 PM PDT 24 Apr 02 12:29:31 PM PDT 24 13253575695 ps
T308 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.1303568141 Apr 02 12:29:15 PM PDT 24 Apr 02 12:29:22 PM PDT 24 147269377 ps
T309 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2714413524 Apr 02 12:28:46 PM PDT 24 Apr 02 12:28:48 PM PDT 24 305150807 ps
T310 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1242241061 Apr 02 12:28:51 PM PDT 24 Apr 02 12:29:01 PM PDT 24 165116873 ps
T311 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.2812844743 Apr 02 12:29:15 PM PDT 24 Apr 02 12:29:44 PM PDT 24 7041298617 ps
T87 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.3960987903 Apr 02 12:29:02 PM PDT 24 Apr 02 12:29:04 PM PDT 24 341950336 ps
T312 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.1237590076 Apr 02 12:28:50 PM PDT 24 Apr 02 12:28:53 PM PDT 24 59954539 ps
T313 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3863811489 Apr 02 12:28:52 PM PDT 24 Apr 02 12:28:55 PM PDT 24 151894976 ps
T314 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.5554202 Apr 02 12:28:51 PM PDT 24 Apr 02 12:28:53 PM PDT 24 1157088959 ps
T105 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.796199956 Apr 02 12:28:52 PM PDT 24 Apr 02 12:28:54 PM PDT 24 96798816 ps
T315 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.2015066753 Apr 02 12:28:46 PM PDT 24 Apr 02 12:28:48 PM PDT 24 66164998 ps
T316 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.3992803767 Apr 02 12:28:52 PM PDT 24 Apr 02 12:28:53 PM PDT 24 155655260 ps
T129 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2209560949 Apr 02 12:29:18 PM PDT 24 Apr 02 12:29:35 PM PDT 24 1104246198 ps
T106 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.3415157340 Apr 02 12:29:25 PM PDT 24 Apr 02 12:29:27 PM PDT 24 103442493 ps
T317 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.4085013882 Apr 02 12:28:50 PM PDT 24 Apr 02 12:28:58 PM PDT 24 80892041 ps
T318 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.647675257 Apr 02 12:28:48 PM PDT 24 Apr 02 12:28:52 PM PDT 24 550096651 ps
T88 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1111499692 Apr 02 12:29:18 PM PDT 24 Apr 02 12:29:19 PM PDT 24 738420222 ps
T319 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.2840926350 Apr 02 12:28:51 PM PDT 24 Apr 02 12:28:55 PM PDT 24 120390236 ps
T320 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.2801854880 Apr 02 12:29:59 PM PDT 24 Apr 02 12:30:12 PM PDT 24 1472166934 ps
T321 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2232580398 Apr 02 12:28:47 PM PDT 24 Apr 02 12:28:53 PM PDT 24 211253211 ps
T127 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.1679160143 Apr 02 12:29:25 PM PDT 24 Apr 02 12:29:35 PM PDT 24 1040331359 ps
T322 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.180588594 Apr 02 12:28:47 PM PDT 24 Apr 02 12:29:10 PM PDT 24 6472826655 ps
T323 /workspace/coverage/cover_reg_top/36.rv_dm_tap_fsm_rand_reset.1403990533 Apr 02 12:28:53 PM PDT 24 Apr 02 12:29:17 PM PDT 24 23902858860 ps
T324 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3906377665 Apr 02 12:28:57 PM PDT 24 Apr 02 12:29:11 PM PDT 24 420196066 ps
T325 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.1584674183 Apr 02 12:29:59 PM PDT 24 Apr 02 12:30:02 PM PDT 24 638138883 ps
T326 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.403953763 Apr 02 12:29:30 PM PDT 24 Apr 02 12:29:32 PM PDT 24 554372674 ps
T327 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2917732577 Apr 02 12:30:00 PM PDT 24 Apr 02 12:30:04 PM PDT 24 85916107 ps
T328 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.735811302 Apr 02 12:29:21 PM PDT 24 Apr 02 12:29:21 PM PDT 24 50945801 ps
T329 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.972517925 Apr 02 12:29:17 PM PDT 24 Apr 02 12:29:19 PM PDT 24 558678114 ps
T330 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.2374315618 Apr 02 12:29:02 PM PDT 24 Apr 02 12:29:12 PM PDT 24 527571634 ps
T331 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2328678745 Apr 02 12:28:47 PM PDT 24 Apr 02 12:28:54 PM PDT 24 3508461226 ps
T332 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.15434948 Apr 02 12:28:50 PM PDT 24 Apr 02 12:28:51 PM PDT 24 134031195 ps
T333 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.403975808 Apr 02 12:28:53 PM PDT 24 Apr 02 12:28:55 PM PDT 24 120944886 ps
T334 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.4182988631 Apr 02 12:29:38 PM PDT 24 Apr 02 12:29:39 PM PDT 24 55192499 ps
T335 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.4125077348 Apr 02 12:29:17 PM PDT 24 Apr 02 12:29:21 PM PDT 24 752876351 ps
T336 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.2531528707 Apr 02 12:28:55 PM PDT 24 Apr 02 12:30:08 PM PDT 24 30403590169 ps
T337 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.458747641 Apr 02 12:29:20 PM PDT 24 Apr 02 12:29:28 PM PDT 24 3685574505 ps
T338 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1386475560 Apr 02 12:28:51 PM PDT 24 Apr 02 12:28:52 PM PDT 24 162767387 ps
T339 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.375719649 Apr 02 12:28:49 PM PDT 24 Apr 02 12:30:11 PM PDT 24 38771729170 ps
T340 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.328022387 Apr 02 12:29:59 PM PDT 24 Apr 02 12:30:02 PM PDT 24 144087909 ps
T341 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2460161662 Apr 02 12:28:50 PM PDT 24 Apr 02 12:28:51 PM PDT 24 363543316 ps
T342 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.3619074327 Apr 02 12:28:49 PM PDT 24 Apr 02 12:28:55 PM PDT 24 111060393 ps
T343 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3962703852 Apr 02 12:29:25 PM PDT 24 Apr 02 12:29:28 PM PDT 24 89053838 ps
T344 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1105010468 Apr 02 12:28:46 PM PDT 24 Apr 02 12:28:50 PM PDT 24 189408768 ps
T345 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.4167151815 Apr 02 12:29:59 PM PDT 24 Apr 02 12:30:03 PM PDT 24 804313678 ps
T124 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3207682039 Apr 02 12:28:50 PM PDT 24 Apr 02 12:29:09 PM PDT 24 986198966 ps
T346 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.3924598479 Apr 02 12:28:52 PM PDT 24 Apr 02 12:30:02 PM PDT 24 26351200854 ps
T347 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.2047775249 Apr 02 12:28:47 PM PDT 24 Apr 02 12:28:50 PM PDT 24 47066445 ps
T348 /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.1465444187 Apr 02 12:28:53 PM PDT 24 Apr 02 12:29:22 PM PDT 24 13662097326 ps
T349 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.787886028 Apr 02 12:28:50 PM PDT 24 Apr 02 12:28:51 PM PDT 24 92335395 ps
T350 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.483852517 Apr 02 12:30:00 PM PDT 24 Apr 02 12:30:03 PM PDT 24 829618175 ps
T351 /workspace/coverage/cover_reg_top/38.rv_dm_tap_fsm_rand_reset.3613614606 Apr 02 12:29:27 PM PDT 24 Apr 02 12:29:53 PM PDT 24 25324874889 ps
T352 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.2467575264 Apr 02 12:28:51 PM PDT 24 Apr 02 12:28:52 PM PDT 24 96596441 ps
T353 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2341385547 Apr 02 12:28:48 PM PDT 24 Apr 02 12:28:49 PM PDT 24 72846635 ps
T354 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.2663283371 Apr 02 12:28:47 PM PDT 24 Apr 02 12:28:50 PM PDT 24 379569563 ps
T355 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2578527699 Apr 02 12:28:53 PM PDT 24 Apr 02 12:28:56 PM PDT 24 2604232439 ps
T356 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.1326882120 Apr 02 12:28:48 PM PDT 24 Apr 02 12:28:49 PM PDT 24 71388885 ps
T357 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.3663182281 Apr 02 12:29:18 PM PDT 24 Apr 02 12:29:19 PM PDT 24 52077930 ps
T358 /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.3321642462 Apr 02 12:29:20 PM PDT 24 Apr 02 12:29:42 PM PDT 24 35232281579 ps
T359 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.3179074019 Apr 02 12:29:21 PM PDT 24 Apr 02 12:29:22 PM PDT 24 16129235 ps
T360 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.3245430465 Apr 02 12:29:24 PM PDT 24 Apr 02 12:29:28 PM PDT 24 739207546 ps
T361 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.3838905930 Apr 02 12:28:48 PM PDT 24 Apr 02 12:28:51 PM PDT 24 1189690724 ps
T362 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2399798382 Apr 02 12:28:55 PM PDT 24 Apr 02 12:29:02 PM PDT 24 511636874 ps
T363 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1486834382 Apr 02 12:30:00 PM PDT 24 Apr 02 12:30:06 PM PDT 24 270693814 ps
T364 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.1044128202 Apr 02 12:28:50 PM PDT 24 Apr 02 12:28:52 PM PDT 24 70407661 ps
T365 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.3108328809 Apr 02 12:28:51 PM PDT 24 Apr 02 12:28:54 PM PDT 24 84714704 ps
T366 /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.630435870 Apr 02 12:29:17 PM PDT 24 Apr 02 12:29:45 PM PDT 24 17593012040 ps
T367 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.519606659 Apr 02 12:28:45 PM PDT 24 Apr 02 12:28:52 PM PDT 24 2471240350 ps
T368 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.485750099 Apr 02 12:28:51 PM PDT 24 Apr 02 12:28:52 PM PDT 24 23455719 ps
T369 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.2900219236 Apr 02 12:28:47 PM PDT 24 Apr 02 12:28:51 PM PDT 24 118775478 ps
T370 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.4225560070 Apr 02 12:29:26 PM PDT 24 Apr 02 12:29:32 PM PDT 24 3623317240 ps
T371 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1584726301 Apr 02 12:28:48 PM PDT 24 Apr 02 12:28:49 PM PDT 24 40417682 ps
T372 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3519209733 Apr 02 12:28:48 PM PDT 24 Apr 02 12:28:49 PM PDT 24 267570634 ps
T373 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2077341968 Apr 02 12:28:49 PM PDT 24 Apr 02 12:28:52 PM PDT 24 618442795 ps
T374 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.2273560605 Apr 02 12:29:23 PM PDT 24 Apr 02 12:29:35 PM PDT 24 1852771528 ps
T375 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2227851281 Apr 02 12:28:49 PM PDT 24 Apr 02 12:28:53 PM PDT 24 92962834 ps
T376 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.625539873 Apr 02 12:28:48 PM PDT 24 Apr 02 12:28:50 PM PDT 24 546780389 ps
T377 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.3774119408 Apr 02 12:29:23 PM PDT 24 Apr 02 12:29:31 PM PDT 24 3648334439 ps
T378 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3306826705 Apr 02 12:28:51 PM PDT 24 Apr 02 12:28:51 PM PDT 24 24168921 ps

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.1340404905
Short name T1
Test name
Test status
Simulation time 933756130 ps
CPU time 1.78 seconds
Started Apr 02 12:31:23 PM PDT 24
Finished Apr 02 12:31:25 PM PDT 24
Peak memory 204896 kb
Host smart-5f74cdeb-ad0a-4231-9464-05155c34bf26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340404905 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.1340404905
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/20.rv_dm_stress_all.3305437672
Short name T12
Test name
Test status
Simulation time 4714249809 ps
CPU time 15.46 seconds
Started Apr 02 12:31:25 PM PDT 24
Finished Apr 02 12:31:40 PM PDT 24
Peak memory 204988 kb
Host smart-82f68897-e8d4-410b-985c-ef0c33a248e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305437672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.3305437672
Directory /workspace/20.rv_dm_stress_all/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.291592948
Short name T36
Test name
Test status
Simulation time 48826243 ps
CPU time 0.71 seconds
Started Apr 02 12:31:26 PM PDT 24
Finished Apr 02 12:31:26 PM PDT 24
Peak memory 205020 kb
Host smart-b777d506-abda-4ff2-a107-6c84acece3e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291592948 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.291592948
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.2058998357
Short name T40
Test name
Test status
Simulation time 6775105868 ps
CPU time 21.88 seconds
Started Apr 02 12:29:38 PM PDT 24
Finished Apr 02 12:30:00 PM PDT 24
Peak memory 213912 kb
Host smart-54d0a6c4-3022-4650-b274-db63faced9ff
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058998357 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.2058998357
Directory /workspace/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2812790708
Short name T43
Test name
Test status
Simulation time 3442939200 ps
CPU time 73.77 seconds
Started Apr 02 12:28:46 PM PDT 24
Finished Apr 02 12:30:00 PM PDT 24
Peak memory 204964 kb
Host smart-b0ba9cae-18a5-418f-8b75-0d3e95f5113d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812790708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.2812790708
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.2561768563
Short name T23
Test name
Test status
Simulation time 11476005163 ps
CPU time 40.24 seconds
Started Apr 02 12:31:29 PM PDT 24
Finished Apr 02 12:32:09 PM PDT 24
Peak memory 205152 kb
Host smart-4e2e50bf-889e-4f35-865b-abcdb6f4463c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561768563 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.2561768563
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_stress_all.2577466146
Short name T54
Test name
Test status
Simulation time 9090271493 ps
CPU time 7.61 seconds
Started Apr 02 12:31:28 PM PDT 24
Finished Apr 02 12:31:36 PM PDT 24
Peak memory 205016 kb
Host smart-1503b7b7-3e1a-43b7-9ade-ad91b59152fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577466146 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.2577466146
Directory /workspace/6.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.1588040639
Short name T115
Test name
Test status
Simulation time 833005360 ps
CPU time 15.37 seconds
Started Apr 02 12:28:51 PM PDT 24
Finished Apr 02 12:29:06 PM PDT 24
Peak memory 213072 kb
Host smart-b842d157-e296-4e79-b453-1b2e633d598d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588040639 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.1
588040639
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.1557932630
Short name T16
Test name
Test status
Simulation time 8883745114 ps
CPU time 15.76 seconds
Started Apr 02 12:31:29 PM PDT 24
Finished Apr 02 12:31:45 PM PDT 24
Peak memory 215384 kb
Host smart-52bd6c6d-5fa2-4b79-abe0-4672ec157647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557932630 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.1557932630
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.3619760812
Short name T65
Test name
Test status
Simulation time 2004865075 ps
CPU time 5.61 seconds
Started Apr 02 12:29:19 PM PDT 24
Finished Apr 02 12:29:25 PM PDT 24
Peak memory 220884 kb
Host smart-8c87a71e-3cab-47a8-80ff-790370ce37d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619760812 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.3619760812
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/37.rv_dm_stress_all.2652969705
Short name T18
Test name
Test status
Simulation time 10353196717 ps
CPU time 8.64 seconds
Started Apr 02 12:32:12 PM PDT 24
Finished Apr 02 12:32:21 PM PDT 24
Peak memory 213120 kb
Host smart-7a3d97e5-ea47-484e-bad0-d03426c7f8c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652969705 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.2652969705
Directory /workspace/37.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.1802958471
Short name T31
Test name
Test status
Simulation time 173417320 ps
CPU time 1.09 seconds
Started Apr 02 12:31:14 PM PDT 24
Finished Apr 02 12:31:15 PM PDT 24
Peak memory 229356 kb
Host smart-245e4017-2a75-46e5-9c6e-2558af90370d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802958471 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.1802958471
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.3419420242
Short name T55
Test name
Test status
Simulation time 94493182 ps
CPU time 0.93 seconds
Started Apr 02 12:30:58 PM PDT 24
Finished Apr 02 12:30:59 PM PDT 24
Peak memory 204744 kb
Host smart-8ace041c-1ea0-44e4-abcb-fd35ff9b2d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419420242 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.3419420242
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.2088817235
Short name T52
Test name
Test status
Simulation time 29019623 ps
CPU time 0.8 seconds
Started Apr 02 12:31:18 PM PDT 24
Finished Apr 02 12:31:19 PM PDT 24
Peak memory 212960 kb
Host smart-cc857d62-600a-4596-90c2-052182b2f2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088817235 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.2088817235
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1214218762
Short name T99
Test name
Test status
Simulation time 16606508574 ps
CPU time 73.96 seconds
Started Apr 02 12:28:49 PM PDT 24
Finished Apr 02 12:30:03 PM PDT 24
Peak memory 218420 kb
Host smart-3513cbea-f4ee-425a-8450-aa8290813be0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214218762 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.1214218762
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.3212514386
Short name T123
Test name
Test status
Simulation time 650386680 ps
CPU time 15.33 seconds
Started Apr 02 12:29:24 PM PDT 24
Finished Apr 02 12:29:39 PM PDT 24
Peak memory 221308 kb
Host smart-b747ec38-06b1-455a-913a-223789cac988
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212514386 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.3212514386
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.2183064843
Short name T4
Test name
Test status
Simulation time 52345865 ps
CPU time 0.86 seconds
Started Apr 02 12:31:01 PM PDT 24
Finished Apr 02 12:31:02 PM PDT 24
Peak memory 204616 kb
Host smart-af03bf9f-f557-4d72-a449-6dd04c4c3dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183064843 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.2183064843
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.2377462324
Short name T7
Test name
Test status
Simulation time 123231523 ps
CPU time 0.75 seconds
Started Apr 02 12:31:07 PM PDT 24
Finished Apr 02 12:31:08 PM PDT 24
Peak memory 204736 kb
Host smart-4439ad59-5e4d-4afa-a8e1-c923667ec8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377462324 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.2377462324
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2773399060
Short name T107
Test name
Test status
Simulation time 518505631 ps
CPU time 4.26 seconds
Started Apr 02 12:29:10 PM PDT 24
Finished Apr 02 12:29:15 PM PDT 24
Peak memory 204924 kb
Host smart-c6274906-c193-40ca-8da8-713d88478e1d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773399060 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.2773399060
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.1697140569
Short name T2
Test name
Test status
Simulation time 87069407 ps
CPU time 0.69 seconds
Started Apr 02 12:31:29 PM PDT 24
Finished Apr 02 12:31:30 PM PDT 24
Peak memory 204640 kb
Host smart-e320a900-b684-4bd9-a08d-331e1648003f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697140569 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.1697140569
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.4116788475
Short name T60
Test name
Test status
Simulation time 98857626 ps
CPU time 0.74 seconds
Started Apr 02 12:28:50 PM PDT 24
Finished Apr 02 12:28:51 PM PDT 24
Peak memory 204628 kb
Host smart-68397338-d833-4778-9328-1baf93cc21c5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116788475 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.4116788475
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1111499692
Short name T88
Test name
Test status
Simulation time 738420222 ps
CPU time 1.61 seconds
Started Apr 02 12:29:18 PM PDT 24
Finished Apr 02 12:29:19 PM PDT 24
Peak memory 204776 kb
Host smart-fe60ddd5-956f-4bf8-9e24-80f6af31719a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111499692 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.1111499692
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.4136574726
Short name T42
Test name
Test status
Simulation time 2180704459 ps
CPU time 32.54 seconds
Started Apr 02 12:28:52 PM PDT 24
Finished Apr 02 12:29:25 PM PDT 24
Peak memory 214228 kb
Host smart-b583a064-7e4f-467b-af58-381131d3cddf
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136574726 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.4136574726
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.3544212471
Short name T130
Test name
Test status
Simulation time 442837861 ps
CPU time 8.23 seconds
Started Apr 02 12:29:35 PM PDT 24
Finished Apr 02 12:29:44 PM PDT 24
Peak memory 213124 kb
Host smart-4c62fe73-b8b0-4d2a-8d07-3efe67c3813b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544212471 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.3
544212471
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.253432891
Short name T156
Test name
Test status
Simulation time 52028497 ps
CPU time 0.79 seconds
Started Apr 02 12:31:29 PM PDT 24
Finished Apr 02 12:31:30 PM PDT 24
Peak memory 204740 kb
Host smart-db2316fb-b350-4165-aeb9-5ad57b9e3747
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253432891 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.253432891
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.4105498651
Short name T35
Test name
Test status
Simulation time 311149612 ps
CPU time 1.18 seconds
Started Apr 02 12:31:06 PM PDT 24
Finished Apr 02 12:31:07 PM PDT 24
Peak memory 204580 kb
Host smart-e75e31ca-b7a5-4bf8-b914-ca5deff68875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105498651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.4105498651
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.3415157340
Short name T106
Test name
Test status
Simulation time 103442493 ps
CPU time 2.43 seconds
Started Apr 02 12:29:25 PM PDT 24
Finished Apr 02 12:29:27 PM PDT 24
Peak memory 213144 kb
Host smart-af98bc4a-ced3-4224-a894-ae5d63b93ed5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415157340 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.3415157340
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2209560949
Short name T129
Test name
Test status
Simulation time 1104246198 ps
CPU time 16.66 seconds
Started Apr 02 12:29:18 PM PDT 24
Finished Apr 02 12:29:35 PM PDT 24
Peak memory 221232 kb
Host smart-17f07b88-60e5-4b4a-b52c-b79830aea22a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209560949 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.2209560949
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.4224982188
Short name T90
Test name
Test status
Simulation time 17523412839 ps
CPU time 65.6 seconds
Started Apr 02 12:29:17 PM PDT 24
Finished Apr 02 12:30:22 PM PDT 24
Peak memory 205208 kb
Host smart-a2a35e18-1090-4892-a9ae-4bf3f968474d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224982188 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.4224982188
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.852902658
Short name T96
Test name
Test status
Simulation time 107337242 ps
CPU time 2.43 seconds
Started Apr 02 12:28:47 PM PDT 24
Finished Apr 02 12:28:50 PM PDT 24
Peak memory 213128 kb
Host smart-9a6f19dd-9f16-4537-9c79-0e763fe909c8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852902658 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.852902658
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.458747641
Short name T337
Test name
Test status
Simulation time 3685574505 ps
CPU time 7.75 seconds
Started Apr 02 12:29:20 PM PDT 24
Finished Apr 02 12:29:28 PM PDT 24
Peak memory 213148 kb
Host smart-395046c8-74a3-4b65-b1a3-effc9a7154a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458747641 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.458747641
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.3818750967
Short name T92
Test name
Test status
Simulation time 137084544 ps
CPU time 2.19 seconds
Started Apr 02 12:28:46 PM PDT 24
Finished Apr 02 12:28:50 PM PDT 24
Peak memory 213140 kb
Host smart-882e579a-e5a4-4b65-9438-a9172812acc1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818750967 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.3818750967
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.2812844743
Short name T311
Test name
Test status
Simulation time 7041298617 ps
CPU time 29.03 seconds
Started Apr 02 12:29:15 PM PDT 24
Finished Apr 02 12:29:44 PM PDT 24
Peak memory 204812 kb
Host smart-9ce2e357-fcf6-4dde-a4bc-177efe435e64
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812844743 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.2812844743
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.375719649
Short name T339
Test name
Test status
Simulation time 38771729170 ps
CPU time 81.92 seconds
Started Apr 02 12:28:49 PM PDT 24
Finished Apr 02 12:30:11 PM PDT 24
Peak memory 204820 kb
Host smart-c643ea3b-9ea5-4e50-801b-1b60afb6cd55
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375719649 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr
_bit_bash.375719649
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.1892575673
Short name T250
Test name
Test status
Simulation time 704664481 ps
CPU time 1.62 seconds
Started Apr 02 12:28:50 PM PDT 24
Finished Apr 02 12:28:52 PM PDT 24
Peak memory 204792 kb
Host smart-00501597-a9b7-48ec-9626-ae3290172446
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892575673 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.1892575673
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.1029018653
Short name T230
Test name
Test status
Simulation time 255950671 ps
CPU time 1.64 seconds
Started Apr 02 12:28:51 PM PDT 24
Finished Apr 02 12:28:53 PM PDT 24
Peak memory 204676 kb
Host smart-1a6f9156-dd2a-4bca-bce3-8af5bc17af27
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029018653 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.1
029018653
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3019297363
Short name T266
Test name
Test status
Simulation time 314486348 ps
CPU time 1.23 seconds
Started Apr 02 12:28:52 PM PDT 24
Finished Apr 02 12:28:53 PM PDT 24
Peak memory 204516 kb
Host smart-d1f16abb-d9d7-4f46-899e-0f0c1279b56e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019297363 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.3019297363
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.403953763
Short name T326
Test name
Test status
Simulation time 554372674 ps
CPU time 1.26 seconds
Started Apr 02 12:29:30 PM PDT 24
Finished Apr 02 12:29:32 PM PDT 24
Peak memory 204816 kb
Host smart-314a0137-71c4-41cc-9a1c-5df68ee1235d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403953763 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr
_bit_bash.403953763
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.735811302
Short name T328
Test name
Test status
Simulation time 50945801 ps
CPU time 0.71 seconds
Started Apr 02 12:29:21 PM PDT 24
Finished Apr 02 12:29:21 PM PDT 24
Peak memory 204552 kb
Host smart-1aec9a8a-30cc-485b-8247-edc8a309d263
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735811302 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.735811302
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.4064454801
Short name T279
Test name
Test status
Simulation time 48502849 ps
CPU time 0.69 seconds
Started Apr 02 12:28:45 PM PDT 24
Finished Apr 02 12:28:47 PM PDT 24
Peak memory 204552 kb
Host smart-4022a4a2-5bb5-4b6e-92df-9566c32937dd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064454801 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.4064454801
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.2050293985
Short name T262
Test name
Test status
Simulation time 23393158 ps
CPU time 0.67 seconds
Started Apr 02 12:28:50 PM PDT 24
Finished Apr 02 12:28:52 PM PDT 24
Peak memory 204560 kb
Host smart-6211c527-8e88-4801-8afc-10281e63c25b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050293985 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.2050293985
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.2900219236
Short name T369
Test name
Test status
Simulation time 118775478 ps
CPU time 3.12 seconds
Started Apr 02 12:28:47 PM PDT 24
Finished Apr 02 12:28:51 PM PDT 24
Peak memory 213016 kb
Host smart-8be99a26-fe03-4823-948b-a8846f900b40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900219236 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.2900219236
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.4149143015
Short name T128
Test name
Test status
Simulation time 3228769531 ps
CPU time 18.02 seconds
Started Apr 02 12:28:50 PM PDT 24
Finished Apr 02 12:29:08 PM PDT 24
Peak memory 221284 kb
Host smart-5d7ecfe3-5fe0-448d-b37e-421a0165a9d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149143015 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.4149143015
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.607239962
Short name T282
Test name
Test status
Simulation time 12154453140 ps
CPU time 32.44 seconds
Started Apr 02 12:29:20 PM PDT 24
Finished Apr 02 12:29:52 PM PDT 24
Peak memory 204960 kb
Host smart-090cbc32-8362-4fbf-b579-36469fdeb9ce
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607239962 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.rv_dm_csr_aliasing.607239962
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.3927892173
Short name T264
Test name
Test status
Simulation time 3648982001 ps
CPU time 37.41 seconds
Started Apr 02 12:28:59 PM PDT 24
Finished Apr 02 12:29:36 PM PDT 24
Peak memory 204992 kb
Host smart-5082c30a-c178-4734-aefd-1f2d0eb65ab4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927892173 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.3927892173
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.3838905930
Short name T361
Test name
Test status
Simulation time 1189690724 ps
CPU time 2.59 seconds
Started Apr 02 12:28:48 PM PDT 24
Finished Apr 02 12:28:51 PM PDT 24
Peak memory 213128 kb
Host smart-0ed32113-0639-4aaf-bcd1-330ca437876c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838905930 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.3838905930
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.1237590076
Short name T312
Test name
Test status
Simulation time 59954539 ps
CPU time 3.72 seconds
Started Apr 02 12:28:50 PM PDT 24
Finished Apr 02 12:28:53 PM PDT 24
Peak memory 218828 kb
Host smart-aaedb4dd-0243-4e11-8d97-a73a9807c2d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237590076 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.1237590076
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.403975808
Short name T333
Test name
Test status
Simulation time 120944886 ps
CPU time 1.51 seconds
Started Apr 02 12:28:53 PM PDT 24
Finished Apr 02 12:28:55 PM PDT 24
Peak memory 213080 kb
Host smart-5e72e351-546a-4a6d-8a48-7ac0297994d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403975808 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.403975808
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2328678745
Short name T331
Test name
Test status
Simulation time 3508461226 ps
CPU time 6.54 seconds
Started Apr 02 12:28:47 PM PDT 24
Finished Apr 02 12:28:54 PM PDT 24
Peak memory 204748 kb
Host smart-fc0ea074-99b8-4762-be15-c7c6c54746b1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328678745 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.2328678745
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1151832538
Short name T271
Test name
Test status
Simulation time 8905644911 ps
CPU time 12.37 seconds
Started Apr 02 12:28:48 PM PDT 24
Finished Apr 02 12:29:01 PM PDT 24
Peak memory 204784 kb
Host smart-69f5e73e-224e-4192-b602-686f7ed499f6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151832538 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_bit_bash.1151832538
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2369156290
Short name T244
Test name
Test status
Simulation time 292627376 ps
CPU time 1.57 seconds
Started Apr 02 12:28:52 PM PDT 24
Finished Apr 02 12:28:53 PM PDT 24
Peak memory 204664 kb
Host smart-0ef56b2e-c248-4bdf-88ee-1f9e891e8a8c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369156290 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.2
369156290
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2713633231
Short name T288
Test name
Test status
Simulation time 130175097 ps
CPU time 1.07 seconds
Started Apr 02 12:28:51 PM PDT 24
Finished Apr 02 12:28:53 PM PDT 24
Peak memory 204500 kb
Host smart-5e204b94-749e-4067-9a4d-2c600a2d6ac3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713633231 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.2713633231
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2077341968
Short name T373
Test name
Test status
Simulation time 618442795 ps
CPU time 3.06 seconds
Started Apr 02 12:28:49 PM PDT 24
Finished Apr 02 12:28:52 PM PDT 24
Peak memory 204752 kb
Host smart-70a05104-8e53-47b4-9650-3efa068f801f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077341968 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.2077341968
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.3992803767
Short name T316
Test name
Test status
Simulation time 155655260 ps
CPU time 0.9 seconds
Started Apr 02 12:28:52 PM PDT 24
Finished Apr 02 12:28:53 PM PDT 24
Peak memory 204576 kb
Host smart-0bdf408c-e6b6-4b2f-a87c-f0b91948285f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992803767 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.3992803767
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.1689720795
Short name T249
Test name
Test status
Simulation time 130470125 ps
CPU time 0.7 seconds
Started Apr 02 12:28:50 PM PDT 24
Finished Apr 02 12:28:52 PM PDT 24
Peak memory 204548 kb
Host smart-1cfadb70-4d14-4703-9dbf-77533f753664
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689720795 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.1
689720795
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3306826705
Short name T378
Test name
Test status
Simulation time 24168921 ps
CPU time 0.69 seconds
Started Apr 02 12:28:51 PM PDT 24
Finished Apr 02 12:28:51 PM PDT 24
Peak memory 204500 kb
Host smart-13c29f72-d2a8-4ecc-8383-cac5751a9f79
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306826705 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.3306826705
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.485750099
Short name T368
Test name
Test status
Simulation time 23455719 ps
CPU time 0.64 seconds
Started Apr 02 12:28:51 PM PDT 24
Finished Apr 02 12:28:52 PM PDT 24
Peak memory 204516 kb
Host smart-44fe9338-1092-4996-bfee-da3338eadac5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485750099 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.485750099
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.991988226
Short name T297
Test name
Test status
Simulation time 1833896499 ps
CPU time 8.4 seconds
Started Apr 02 12:29:23 PM PDT 24
Finished Apr 02 12:29:31 PM PDT 24
Peak memory 204824 kb
Host smart-0e0890c2-9a1a-4a02-af19-926139d964ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991988226 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_c
sr_outstanding.991988226
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1242241061
Short name T310
Test name
Test status
Simulation time 165116873 ps
CPU time 4.57 seconds
Started Apr 02 12:28:51 PM PDT 24
Finished Apr 02 12:29:01 PM PDT 24
Peak memory 213068 kb
Host smart-3bbc13fe-794f-4801-8ccc-d789825ed6b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242241061 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.1242241061
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.1739184656
Short name T278
Test name
Test status
Simulation time 1577501218 ps
CPU time 9.58 seconds
Started Apr 02 12:28:58 PM PDT 24
Finished Apr 02 12:29:07 PM PDT 24
Peak memory 213092 kb
Host smart-17079720-1bfa-40a8-bf3c-1f15c30e7838
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739184656 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.1739184656
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.2640926681
Short name T73
Test name
Test status
Simulation time 264806688 ps
CPU time 2.34 seconds
Started Apr 02 12:28:50 PM PDT 24
Finished Apr 02 12:28:53 PM PDT 24
Peak memory 216680 kb
Host smart-9bbaf981-c640-4fe1-a1dc-a81c8d28a3f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640926681 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.2640926681
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.61493975
Short name T85
Test name
Test status
Simulation time 1890349080 ps
CPU time 2.69 seconds
Started Apr 02 12:28:48 PM PDT 24
Finished Apr 02 12:28:51 PM PDT 24
Peak memory 212976 kb
Host smart-13505153-dcd7-49a8-a4df-762ca21a012a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61493975 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.61493975
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.1584674183
Short name T325
Test name
Test status
Simulation time 638138883 ps
CPU time 2.87 seconds
Started Apr 02 12:29:59 PM PDT 24
Finished Apr 02 12:30:02 PM PDT 24
Peak memory 202264 kb
Host smart-3278891a-a30d-462a-95ac-82efa357ec20
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584674183 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
1584674183
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.4182988631
Short name T334
Test name
Test status
Simulation time 55192499 ps
CPU time 0.74 seconds
Started Apr 02 12:29:38 PM PDT 24
Finished Apr 02 12:29:39 PM PDT 24
Peak memory 204564 kb
Host smart-31768fb8-330d-47fc-ac90-d552eb82318a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182988631 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
4182988631
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.1927510765
Short name T44
Test name
Test status
Simulation time 749896671 ps
CPU time 7.95 seconds
Started Apr 02 12:28:48 PM PDT 24
Finished Apr 02 12:28:56 PM PDT 24
Peak memory 204940 kb
Host smart-0e42cf9c-f925-4751-8a9f-cc789166d288
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927510765 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.1927510765
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.2840926350
Short name T319
Test name
Test status
Simulation time 120390236 ps
CPU time 3.78 seconds
Started Apr 02 12:28:51 PM PDT 24
Finished Apr 02 12:28:55 PM PDT 24
Peak memory 213156 kb
Host smart-f17a807f-5d84-4c37-a73b-6fe50e8509f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840926350 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.2840926350
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2435882806
Short name T117
Test name
Test status
Simulation time 2055636383 ps
CPU time 9.04 seconds
Started Apr 02 12:28:52 PM PDT 24
Finished Apr 02 12:29:01 PM PDT 24
Peak memory 221272 kb
Host smart-94a41249-8f5a-4aff-9504-6912cd82a145
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435882806 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.2
435882806
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.4054990653
Short name T256
Test name
Test status
Simulation time 1544272514 ps
CPU time 5.42 seconds
Started Apr 02 12:29:11 PM PDT 24
Finished Apr 02 12:29:17 PM PDT 24
Peak memory 219944 kb
Host smart-886c003f-5a59-44b1-acf1-52c558f0e0cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054990653 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.4054990653
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.1044128202
Short name T364
Test name
Test status
Simulation time 70407661 ps
CPU time 2.17 seconds
Started Apr 02 12:28:50 PM PDT 24
Finished Apr 02 12:28:52 PM PDT 24
Peak memory 213076 kb
Host smart-9968c86f-23c9-4feb-bf7e-0413bd74fac6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044128202 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.1044128202
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.603219505
Short name T292
Test name
Test status
Simulation time 1217785503 ps
CPU time 1.89 seconds
Started Apr 02 12:28:52 PM PDT 24
Finished Apr 02 12:28:54 PM PDT 24
Peak memory 204688 kb
Host smart-934ef2cf-5335-42ec-8e50-a1f244c5edbe
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603219505 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.603219505
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.1677320114
Short name T255
Test name
Test status
Simulation time 40862141 ps
CPU time 0.76 seconds
Started Apr 02 12:28:44 PM PDT 24
Finished Apr 02 12:28:50 PM PDT 24
Peak memory 204512 kb
Host smart-c85f88d7-f836-4400-abf0-0b11318d5398
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677320114 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.
1677320114
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.4198257074
Short name T301
Test name
Test status
Simulation time 246500062 ps
CPU time 3.64 seconds
Started Apr 02 12:28:49 PM PDT 24
Finished Apr 02 12:28:55 PM PDT 24
Peak memory 204948 kb
Host smart-c93c602c-314f-4908-a64d-a3ea1a38a6b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198257074 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same
_csr_outstanding.4198257074
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tap_fsm_rand_reset.4184655622
Short name T74
Test name
Test status
Simulation time 15859246011 ps
CPU time 27.77 seconds
Started Apr 02 12:29:59 PM PDT 24
Finished Apr 02 12:30:27 PM PDT 24
Peak memory 218288 kb
Host smart-38ac9c12-5243-4d0b-9f88-76aa5b974b4e
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184655622 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rv_dm_tap_fsm_rand_reset.4184655622
Directory /workspace/11.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.2801854880
Short name T320
Test name
Test status
Simulation time 1472166934 ps
CPU time 7.55 seconds
Started Apr 02 12:29:59 PM PDT 24
Finished Apr 02 12:30:12 PM PDT 24
Peak memory 212616 kb
Host smart-618fab62-ae7a-4fb1-91a1-ac4cc3c0620d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801854880 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.2801854880
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.182938529
Short name T302
Test name
Test status
Simulation time 492375661 ps
CPU time 2.81 seconds
Started Apr 02 12:30:00 PM PDT 24
Finished Apr 02 12:30:03 PM PDT 24
Peak memory 217088 kb
Host smart-6cc7adc9-55c1-4295-9527-3ea17bf23d2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182938529 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.182938529
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.2015066753
Short name T315
Test name
Test status
Simulation time 66164998 ps
CPU time 1.41 seconds
Started Apr 02 12:28:46 PM PDT 24
Finished Apr 02 12:28:48 PM PDT 24
Peak memory 213024 kb
Host smart-84f1d8db-65f6-42c4-9c94-23ae6d4cfe15
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015066753 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.2015066753
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.5554202
Short name T314
Test name
Test status
Simulation time 1157088959 ps
CPU time 2.22 seconds
Started Apr 02 12:28:51 PM PDT 24
Finished Apr 02 12:28:53 PM PDT 24
Peak memory 204664 kb
Host smart-c301f300-af7d-4efb-b8e0-334f07a30904
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5554202 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.5554202
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3519209733
Short name T372
Test name
Test status
Simulation time 267570634 ps
CPU time 0.62 seconds
Started Apr 02 12:28:48 PM PDT 24
Finished Apr 02 12:28:49 PM PDT 24
Peak memory 204528 kb
Host smart-2fddeecf-f4c2-49b5-a9be-9e2d111e6bba
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519209733 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
3519209733
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.4125077348
Short name T335
Test name
Test status
Simulation time 752876351 ps
CPU time 3.83 seconds
Started Apr 02 12:29:17 PM PDT 24
Finished Apr 02 12:29:21 PM PDT 24
Peak memory 204796 kb
Host smart-9c042e9b-031f-4ca8-94b3-d7cef4ca3ac4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125077348 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.4125077348
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tap_fsm_rand_reset.2485531698
Short name T275
Test name
Test status
Simulation time 7281182236 ps
CPU time 15.53 seconds
Started Apr 02 12:29:18 PM PDT 24
Finished Apr 02 12:29:34 PM PDT 24
Peak memory 217368 kb
Host smart-67667511-52c7-45f8-8641-65cd78d9b968
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485531698 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rv_dm_tap_fsm_rand_reset.2485531698
Directory /workspace/12.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.3619074327
Short name T342
Test name
Test status
Simulation time 111060393 ps
CPU time 3.52 seconds
Started Apr 02 12:28:49 PM PDT 24
Finished Apr 02 12:28:55 PM PDT 24
Peak memory 213048 kb
Host smart-a49a1217-2d90-4498-a989-78685767ad47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619074327 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.3619074327
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3906377665
Short name T324
Test name
Test status
Simulation time 420196066 ps
CPU time 14.36 seconds
Started Apr 02 12:28:57 PM PDT 24
Finished Apr 02 12:29:11 PM PDT 24
Peak memory 213120 kb
Host smart-efbb1612-16a9-4a8b-92d1-15a66061f35c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906377665 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.3
906377665
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3286512973
Short name T293
Test name
Test status
Simulation time 34435210 ps
CPU time 2.11 seconds
Started Apr 02 12:29:59 PM PDT 24
Finished Apr 02 12:30:06 PM PDT 24
Peak memory 212164 kb
Host smart-a7829379-1946-4772-8033-4b24b54b2001
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286512973 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.3286512973
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.2179577429
Short name T103
Test name
Test status
Simulation time 59342536 ps
CPU time 1.54 seconds
Started Apr 02 12:28:48 PM PDT 24
Finished Apr 02 12:28:50 PM PDT 24
Peak memory 218084 kb
Host smart-43289fab-5ef1-4f7a-9263-aa0f6308a606
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179577429 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.2179577429
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.4167151815
Short name T345
Test name
Test status
Simulation time 804313678 ps
CPU time 3.27 seconds
Started Apr 02 12:29:59 PM PDT 24
Finished Apr 02 12:30:03 PM PDT 24
Peak memory 202208 kb
Host smart-f072ffe1-3371-4250-ad49-b6710973e1e0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167151815 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
4167151815
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2438967403
Short name T240
Test name
Test status
Simulation time 29303858 ps
CPU time 0.69 seconds
Started Apr 02 12:28:50 PM PDT 24
Finished Apr 02 12:28:51 PM PDT 24
Peak memory 204552 kb
Host smart-7445d790-10c3-449c-b337-41baf2095f59
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438967403 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
2438967403
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.4214814565
Short name T295
Test name
Test status
Simulation time 205035643 ps
CPU time 3.5 seconds
Started Apr 02 12:28:52 PM PDT 24
Finished Apr 02 12:28:55 PM PDT 24
Peak memory 204864 kb
Host smart-9311a28c-4a5d-4eb0-a0b3-e337ada117e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214814565 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.4214814565
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2232580398
Short name T321
Test name
Test status
Simulation time 211253211 ps
CPU time 5.32 seconds
Started Apr 02 12:28:47 PM PDT 24
Finished Apr 02 12:28:53 PM PDT 24
Peak memory 213124 kb
Host smart-6bb57629-ffbe-4b15-b46a-acb949b06c2e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232580398 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.2232580398
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.381171948
Short name T116
Test name
Test status
Simulation time 387988218 ps
CPU time 8.04 seconds
Started Apr 02 12:30:21 PM PDT 24
Finished Apr 02 12:30:29 PM PDT 24
Peak memory 212900 kb
Host smart-d0e390df-dffe-4531-b8b9-f00c9da39502
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381171948 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.381171948
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.4225560070
Short name T370
Test name
Test status
Simulation time 3623317240 ps
CPU time 6.48 seconds
Started Apr 02 12:29:26 PM PDT 24
Finished Apr 02 12:29:32 PM PDT 24
Peak memory 217824 kb
Host smart-785b0737-bc80-48e8-9658-5f0aeb0f01e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225560070 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.4225560070
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.3018857863
Short name T81
Test name
Test status
Simulation time 37080877 ps
CPU time 2.09 seconds
Started Apr 02 12:29:27 PM PDT 24
Finished Apr 02 12:29:29 PM PDT 24
Peak memory 213084 kb
Host smart-dcb35689-928e-4fa4-ab99-6c1b326d06e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018857863 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.3018857863
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3648849736
Short name T258
Test name
Test status
Simulation time 801140448 ps
CPU time 1.31 seconds
Started Apr 02 12:29:59 PM PDT 24
Finished Apr 02 12:30:01 PM PDT 24
Peak memory 202096 kb
Host smart-d131a0c4-51d0-4982-9885-b8af56574c33
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648849736 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
3648849736
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.1685965912
Short name T59
Test name
Test status
Simulation time 50435933 ps
CPU time 0.79 seconds
Started Apr 02 12:28:48 PM PDT 24
Finished Apr 02 12:28:49 PM PDT 24
Peak memory 204564 kb
Host smart-083f6977-f30d-4665-a235-d1e958ccd784
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685965912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
1685965912
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.446259604
Short name T97
Test name
Test status
Simulation time 2279663611 ps
CPU time 4.85 seconds
Started Apr 02 12:28:49 PM PDT 24
Finished Apr 02 12:28:54 PM PDT 24
Peak memory 205016 kb
Host smart-64f564b6-9148-4c75-be9d-2e873752d74a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446259604 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same_
csr_outstanding.446259604
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.647675257
Short name T318
Test name
Test status
Simulation time 550096651 ps
CPU time 3.84 seconds
Started Apr 02 12:28:48 PM PDT 24
Finished Apr 02 12:28:52 PM PDT 24
Peak memory 213120 kb
Host smart-06d97fc5-8135-4f94-be44-0d1d9662275a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647675257 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.647675257
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.4211103355
Short name T306
Test name
Test status
Simulation time 536734153 ps
CPU time 8.11 seconds
Started Apr 02 12:28:52 PM PDT 24
Finished Apr 02 12:29:00 PM PDT 24
Peak memory 213124 kb
Host smart-8d5a981e-f50c-4218-8db9-80e2f94f9b18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211103355 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.4
211103355
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1056525797
Short name T270
Test name
Test status
Simulation time 2271105026 ps
CPU time 4.38 seconds
Started Apr 02 12:28:51 PM PDT 24
Finished Apr 02 12:28:56 PM PDT 24
Peak memory 216560 kb
Host smart-e4125153-d69a-4045-b023-3cd376388889
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056525797 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.1056525797
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1948358022
Short name T265
Test name
Test status
Simulation time 848278369 ps
CPU time 1.2 seconds
Started Apr 02 12:29:16 PM PDT 24
Finished Apr 02 12:29:17 PM PDT 24
Peak memory 204764 kb
Host smart-54506189-4f71-4aed-a7e7-4be589f27ce8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948358022 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
1948358022
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3065994903
Short name T234
Test name
Test status
Simulation time 65240720 ps
CPU time 0.81 seconds
Started Apr 02 12:28:55 PM PDT 24
Finished Apr 02 12:28:58 PM PDT 24
Peak memory 204560 kb
Host smart-ac6286b6-3e47-41a0-8678-781b72420b2b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065994903 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
3065994903
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.3542928466
Short name T93
Test name
Test status
Simulation time 422596680 ps
CPU time 4.1 seconds
Started Apr 02 12:28:50 PM PDT 24
Finished Apr 02 12:28:54 PM PDT 24
Peak memory 204868 kb
Host smart-6d95152c-bb71-4b23-8142-b9102b3eb737
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542928466 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.3542928466
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tap_fsm_rand_reset.779547329
Short name T272
Test name
Test status
Simulation time 7352491720 ps
CPU time 13.42 seconds
Started Apr 02 12:28:58 PM PDT 24
Finished Apr 02 12:29:11 PM PDT 24
Peak memory 218656 kb
Host smart-541eeaa7-1d79-475c-9864-ee2ff4eeea17
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779547329 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.rv_dm_tap_fsm_rand_reset.779547329
Directory /workspace/15.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.3814503850
Short name T269
Test name
Test status
Simulation time 494227779 ps
CPU time 2.97 seconds
Started Apr 02 12:28:52 PM PDT 24
Finished Apr 02 12:28:55 PM PDT 24
Peak memory 213080 kb
Host smart-f5f7cfe8-ebb3-4fde-a360-81192746d59e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814503850 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.3814503850
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.814000426
Short name T133
Test name
Test status
Simulation time 2133955763 ps
CPU time 9.5 seconds
Started Apr 02 12:29:34 PM PDT 24
Finished Apr 02 12:29:44 PM PDT 24
Peak memory 213124 kb
Host smart-785e7f2f-5892-44ce-8718-380668040c4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814000426 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.814000426
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.1527697840
Short name T287
Test name
Test status
Simulation time 90624256 ps
CPU time 2.21 seconds
Started Apr 02 12:28:55 PM PDT 24
Finished Apr 02 12:28:57 PM PDT 24
Peak memory 213188 kb
Host smart-1fcf607b-6398-4856-9b72-c00ef33ba989
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527697840 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.1527697840
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2917732577
Short name T327
Test name
Test status
Simulation time 85916107 ps
CPU time 2.27 seconds
Started Apr 02 12:30:00 PM PDT 24
Finished Apr 02 12:30:04 PM PDT 24
Peak memory 210824 kb
Host smart-6e65ef3a-2560-468c-841b-d14c32c24a9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917732577 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.2917732577
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.3371137522
Short name T263
Test name
Test status
Simulation time 1369404251 ps
CPU time 2.42 seconds
Started Apr 02 12:30:03 PM PDT 24
Finished Apr 02 12:30:06 PM PDT 24
Peak memory 204388 kb
Host smart-cd91dfa9-2b79-45fe-bc4f-1df2a982ab2c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371137522 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
3371137522
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2600771612
Short name T257
Test name
Test status
Simulation time 54589357 ps
CPU time 0.7 seconds
Started Apr 02 12:28:51 PM PDT 24
Finished Apr 02 12:28:52 PM PDT 24
Peak memory 204568 kb
Host smart-63cd0390-c96c-4d1e-8511-f10e4e21ba82
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600771612 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
2600771612
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3863811489
Short name T313
Test name
Test status
Simulation time 151894976 ps
CPU time 3.56 seconds
Started Apr 02 12:28:52 PM PDT 24
Finished Apr 02 12:28:55 PM PDT 24
Peak memory 204988 kb
Host smart-7d50b09b-a931-4332-b4db-05d10b89806b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863811489 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.3863811489
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.2482943356
Short name T300
Test name
Test status
Simulation time 352274646 ps
CPU time 4.23 seconds
Started Apr 02 12:29:10 PM PDT 24
Finished Apr 02 12:29:15 PM PDT 24
Peak memory 213408 kb
Host smart-96dfc2e9-2fc0-484e-880d-b3cd1fb0df5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482943356 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.2482943356
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.3245430465
Short name T360
Test name
Test status
Simulation time 739207546 ps
CPU time 3.23 seconds
Started Apr 02 12:29:24 PM PDT 24
Finished Apr 02 12:29:28 PM PDT 24
Peak memory 217916 kb
Host smart-1e27a586-5b8a-4e82-978e-b42280f44015
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245430465 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.3245430465
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.972517925
Short name T329
Test name
Test status
Simulation time 558678114 ps
CPU time 2.21 seconds
Started Apr 02 12:29:17 PM PDT 24
Finished Apr 02 12:29:19 PM PDT 24
Peak memory 213364 kb
Host smart-06396efc-8044-416a-8f39-affe23824ed6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972517925 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.972517925
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.553696700
Short name T238
Test name
Test status
Simulation time 333852142 ps
CPU time 1.05 seconds
Started Apr 02 12:28:48 PM PDT 24
Finished Apr 02 12:28:50 PM PDT 24
Peak memory 204744 kb
Host smart-7d62bd23-44b9-4d2b-ae7b-46b65e9b8d53
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553696700 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.553696700
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.3613010779
Short name T305
Test name
Test status
Simulation time 156707112 ps
CPU time 0.7 seconds
Started Apr 02 12:28:57 PM PDT 24
Finished Apr 02 12:28:58 PM PDT 24
Peak memory 204540 kb
Host smart-221815bb-33f9-4e33-ba2a-41c3f5c22253
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613010779 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
3613010779
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2399798382
Short name T362
Test name
Test status
Simulation time 511636874 ps
CPU time 7.42 seconds
Started Apr 02 12:28:55 PM PDT 24
Finished Apr 02 12:29:02 PM PDT 24
Peak memory 204884 kb
Host smart-85f58368-d024-4df0-8ef0-422ad7106040
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399798382 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.2399798382
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.1582531030
Short name T63
Test name
Test status
Simulation time 89444314 ps
CPU time 2.78 seconds
Started Apr 02 12:28:48 PM PDT 24
Finished Apr 02 12:28:54 PM PDT 24
Peak memory 213076 kb
Host smart-1ae730bf-f740-4017-b4cc-5d636f407051
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582531030 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.1582531030
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.3262247531
Short name T125
Test name
Test status
Simulation time 483586050 ps
CPU time 14.76 seconds
Started Apr 02 12:28:52 PM PDT 24
Finished Apr 02 12:29:07 PM PDT 24
Peak memory 213064 kb
Host smart-a2ed2f6d-4750-4e28-a89e-1ebcf2fe499b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262247531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.3
262247531
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1105010468
Short name T344
Test name
Test status
Simulation time 189408768 ps
CPU time 3.87 seconds
Started Apr 02 12:28:46 PM PDT 24
Finished Apr 02 12:28:50 PM PDT 24
Peak memory 219276 kb
Host smart-fa0e577f-ac60-48d0-90e4-4ecc26e03d56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105010468 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.1105010468
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.713375512
Short name T100
Test name
Test status
Simulation time 46874311 ps
CPU time 2.1 seconds
Started Apr 02 12:30:00 PM PDT 24
Finished Apr 02 12:30:03 PM PDT 24
Peak memory 210872 kb
Host smart-50068938-f05c-4f25-a4ea-0041b7438a38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713375512 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.713375512
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.483852517
Short name T350
Test name
Test status
Simulation time 829618175 ps
CPU time 2.07 seconds
Started Apr 02 12:30:00 PM PDT 24
Finished Apr 02 12:30:03 PM PDT 24
Peak memory 201672 kb
Host smart-1a3435f1-39be-4caf-bca2-f9709e3ac007
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483852517 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.483852517
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.1161605686
Short name T239
Test name
Test status
Simulation time 189238600 ps
CPU time 0.76 seconds
Started Apr 02 12:28:51 PM PDT 24
Finished Apr 02 12:28:52 PM PDT 24
Peak memory 204508 kb
Host smart-b17a1147-1c19-4852-a0e1-8b99f723d1ed
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161605686 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
1161605686
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1486834382
Short name T363
Test name
Test status
Simulation time 270693814 ps
CPU time 4.22 seconds
Started Apr 02 12:30:00 PM PDT 24
Finished Apr 02 12:30:06 PM PDT 24
Peak memory 202584 kb
Host smart-5b1a3e9c-9baf-4343-a1ae-f4e4a88a0ff3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486834382 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.1486834382
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.4065617504
Short name T64
Test name
Test status
Simulation time 687447740 ps
CPU time 4.7 seconds
Started Apr 02 12:30:21 PM PDT 24
Finished Apr 02 12:30:25 PM PDT 24
Peak memory 212840 kb
Host smart-9edbd445-c043-490c-a94b-5919fa07b5cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065617504 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.4065617504
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.2273560605
Short name T374
Test name
Test status
Simulation time 1852771528 ps
CPU time 12.58 seconds
Started Apr 02 12:29:23 PM PDT 24
Finished Apr 02 12:29:35 PM PDT 24
Peak memory 220700 kb
Host smart-99c7fd20-570d-4e10-8993-92d1c9c7a5f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273560605 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.2
273560605
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3962703852
Short name T343
Test name
Test status
Simulation time 89053838 ps
CPU time 2.32 seconds
Started Apr 02 12:29:25 PM PDT 24
Finished Apr 02 12:29:28 PM PDT 24
Peak memory 216732 kb
Host smart-e65c0ff9-d296-428c-936e-b897aa34363b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962703852 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.3962703852
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3960916171
Short name T104
Test name
Test status
Simulation time 403126884 ps
CPU time 2.25 seconds
Started Apr 02 12:28:51 PM PDT 24
Finished Apr 02 12:28:53 PM PDT 24
Peak memory 213044 kb
Host smart-3cfb040e-6d5c-4890-9faf-3909a97a2042
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960916171 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.3960916171
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2896657264
Short name T232
Test name
Test status
Simulation time 369839826 ps
CPU time 1.16 seconds
Started Apr 02 12:29:59 PM PDT 24
Finished Apr 02 12:30:01 PM PDT 24
Peak memory 204184 kb
Host smart-7b3ae705-8505-4bb2-b742-70091eaadf01
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896657264 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
2896657264
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.1326882120
Short name T356
Test name
Test status
Simulation time 71388885 ps
CPU time 0.71 seconds
Started Apr 02 12:28:48 PM PDT 24
Finished Apr 02 12:28:49 PM PDT 24
Peak memory 204520 kb
Host smart-376b3c73-14d6-417f-a04d-f24d6fc89d33
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326882120 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
1326882120
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1025665130
Short name T83
Test name
Test status
Simulation time 1133285345 ps
CPU time 4.11 seconds
Started Apr 02 12:30:01 PM PDT 24
Finished Apr 02 12:30:06 PM PDT 24
Peak memory 203876 kb
Host smart-49df74c5-041a-4f3c-bcba-821874ed2cbd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025665130 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.1025665130
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tap_fsm_rand_reset.3465209102
Short name T267
Test name
Test status
Simulation time 6571629604 ps
CPU time 16.15 seconds
Started Apr 02 12:30:01 PM PDT 24
Finished Apr 02 12:30:18 PM PDT 24
Peak memory 216608 kb
Host smart-9694ba40-0167-4ae0-b8ac-44d387681a0a
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465209102 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rv_dm_tap_fsm_rand_reset.3465209102
Directory /workspace/19.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.1472788227
Short name T252
Test name
Test status
Simulation time 814291299 ps
CPU time 4.94 seconds
Started Apr 02 12:28:48 PM PDT 24
Finished Apr 02 12:28:56 PM PDT 24
Peak memory 213060 kb
Host smart-82a3448f-d6f7-4817-8cbb-9e83a64fef4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472788227 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.1472788227
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.338091638
Short name T122
Test name
Test status
Simulation time 1064476094 ps
CPU time 15.43 seconds
Started Apr 02 12:30:01 PM PDT 24
Finished Apr 02 12:30:17 PM PDT 24
Peak memory 220608 kb
Host smart-fe3a6d00-d1fd-4880-93fe-9296acfe63d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338091638 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.338091638
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.3924598479
Short name T346
Test name
Test status
Simulation time 26351200854 ps
CPU time 69.94 seconds
Started Apr 02 12:28:52 PM PDT 24
Finished Apr 02 12:30:02 PM PDT 24
Peak memory 204928 kb
Host smart-eb8b961f-246a-48e7-abca-7630f876f300
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924598479 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.3924598479
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.2663283371
Short name T354
Test name
Test status
Simulation time 379569563 ps
CPU time 2.52 seconds
Started Apr 02 12:28:47 PM PDT 24
Finished Apr 02 12:28:50 PM PDT 24
Peak memory 213120 kb
Host smart-a7ceba8a-9760-41aa-8e78-53225173d989
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663283371 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.2663283371
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.930238950
Short name T290
Test name
Test status
Simulation time 643649767 ps
CPU time 2.08 seconds
Started Apr 02 12:28:51 PM PDT 24
Finished Apr 02 12:29:03 PM PDT 24
Peak memory 214828 kb
Host smart-82cc7a01-90c3-4f61-9995-8df6c07fc0f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930238950 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.930238950
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.796199956
Short name T105
Test name
Test status
Simulation time 96798816 ps
CPU time 2.25 seconds
Started Apr 02 12:28:52 PM PDT 24
Finished Apr 02 12:28:54 PM PDT 24
Peak memory 213092 kb
Host smart-53d0b59e-42ce-406a-9b05-04f9bcfb8769
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796199956 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.796199956
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.3774119408
Short name T377
Test name
Test status
Simulation time 3648334439 ps
CPU time 7.81 seconds
Started Apr 02 12:29:23 PM PDT 24
Finished Apr 02 12:29:31 PM PDT 24
Peak memory 204744 kb
Host smart-5016b115-c4ab-4791-8006-15e8789bdf55
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774119408 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.3774119408
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.3774475623
Short name T291
Test name
Test status
Simulation time 1474200072 ps
CPU time 2.11 seconds
Started Apr 02 12:28:45 PM PDT 24
Finished Apr 02 12:28:49 PM PDT 24
Peak memory 204804 kb
Host smart-d7b9a6bd-0a68-45ec-91bb-cc95727c1514
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774475623 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.3774475623
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.475530883
Short name T259
Test name
Test status
Simulation time 175025053 ps
CPU time 1.15 seconds
Started Apr 02 12:28:53 PM PDT 24
Finished Apr 02 12:28:54 PM PDT 24
Peak memory 204864 kb
Host smart-bd4d2561-1a33-4ddb-80f2-c1856d83e41b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475530883 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.475530883
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3027657168
Short name T268
Test name
Test status
Simulation time 159433645 ps
CPU time 1.12 seconds
Started Apr 02 12:28:50 PM PDT 24
Finished Apr 02 12:28:52 PM PDT 24
Peak memory 204436 kb
Host smart-3fe3ebfd-11c9-4399-9e60-2ed1c9effd52
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027657168 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_aliasing.3027657168
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.355831919
Short name T235
Test name
Test status
Simulation time 1456767149 ps
CPU time 3.07 seconds
Started Apr 02 12:29:09 PM PDT 24
Finished Apr 02 12:29:12 PM PDT 24
Peak memory 204764 kb
Host smart-c583d9b4-6325-4997-8ef5-e8d3e4a12072
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355831919 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_bit_bash.355831919
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1584726301
Short name T371
Test name
Test status
Simulation time 40417682 ps
CPU time 0.76 seconds
Started Apr 02 12:28:48 PM PDT 24
Finished Apr 02 12:28:49 PM PDT 24
Peak memory 204648 kb
Host smart-6ae9fe68-2c98-45cf-bf1e-3223136bfac2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584726301 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.1584726301
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.3663182281
Short name T357
Test name
Test status
Simulation time 52077930 ps
CPU time 0.69 seconds
Started Apr 02 12:29:18 PM PDT 24
Finished Apr 02 12:29:19 PM PDT 24
Peak memory 204560 kb
Host smart-ecc2934d-6525-44d6-b7d4-bec301df0f2e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663182281 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.3
663182281
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.3179074019
Short name T359
Test name
Test status
Simulation time 16129235 ps
CPU time 0.66 seconds
Started Apr 02 12:29:21 PM PDT 24
Finished Apr 02 12:29:22 PM PDT 24
Peak memory 204568 kb
Host smart-a31486ce-7a8a-4273-b568-016c191f91d6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179074019 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.3179074019
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.315491717
Short name T242
Test name
Test status
Simulation time 67950278 ps
CPU time 0.66 seconds
Started Apr 02 12:28:50 PM PDT 24
Finished Apr 02 12:28:51 PM PDT 24
Peak memory 204540 kb
Host smart-0efb4691-a0c8-4014-90e1-8dd873179d45
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315491717 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.315491717
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.2343156145
Short name T91
Test name
Test status
Simulation time 278738023 ps
CPU time 4.21 seconds
Started Apr 02 12:28:51 PM PDT 24
Finished Apr 02 12:28:55 PM PDT 24
Peak memory 204892 kb
Host smart-0c6050ed-932c-47d6-a467-1f94934f1cbc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343156145 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.2343156145
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.630435870
Short name T366
Test name
Test status
Simulation time 17593012040 ps
CPU time 27.65 seconds
Started Apr 02 12:29:17 PM PDT 24
Finished Apr 02 12:29:45 PM PDT 24
Peak memory 221432 kb
Host smart-bf9f1aca-1d9b-4447-b088-e29b814fc85f
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630435870 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.630435870
Directory /workspace/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.2097091382
Short name T112
Test name
Test status
Simulation time 181576747 ps
CPU time 2.81 seconds
Started Apr 02 12:28:45 PM PDT 24
Finished Apr 02 12:28:49 PM PDT 24
Peak memory 213032 kb
Host smart-083c9906-952f-4db3-acaf-de12156c8bb7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097091382 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.2097091382
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/21.rv_dm_tap_fsm_rand_reset.3416077131
Short name T281
Test name
Test status
Simulation time 4536342447 ps
CPU time 17.5 seconds
Started Apr 02 12:29:15 PM PDT 24
Finished Apr 02 12:29:33 PM PDT 24
Peak memory 220284 kb
Host smart-a265526b-ba78-4a70-be6d-5f4460f26dd9
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416077131 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 21.rv_dm_tap_fsm_rand_reset.3416077131
Directory /workspace/21.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/23.rv_dm_tap_fsm_rand_reset.402049669
Short name T274
Test name
Test status
Simulation time 13814897242 ps
CPU time 13.17 seconds
Started Apr 02 12:29:25 PM PDT 24
Finished Apr 02 12:29:38 PM PDT 24
Peak memory 214552 kb
Host smart-6da7935e-eabd-4572-b376-d6dc6b2621ea
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402049669 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 23.rv_dm_tap_fsm_rand_reset.402049669
Directory /workspace/23.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/24.rv_dm_tap_fsm_rand_reset.1853362676
Short name T273
Test name
Test status
Simulation time 11825684181 ps
CPU time 41.46 seconds
Started Apr 02 12:29:25 PM PDT 24
Finished Apr 02 12:30:06 PM PDT 24
Peak memory 221292 kb
Host smart-3d1b571d-497f-4623-b0cf-a9f8b511d1b4
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853362676 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 24.rv_dm_tap_fsm_rand_reset.1853362676
Directory /workspace/24.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/26.rv_dm_tap_fsm_rand_reset.3569602114
Short name T76
Test name
Test status
Simulation time 9230710209 ps
CPU time 14.41 seconds
Started Apr 02 12:28:51 PM PDT 24
Finished Apr 02 12:29:10 PM PDT 24
Peak memory 213748 kb
Host smart-89680200-689d-49b5-8e7c-b3552eb22f5f
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569602114 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 26.rv_dm_tap_fsm_rand_reset.3569602114
Directory /workspace/26.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/29.rv_dm_tap_fsm_rand_reset.3721711361
Short name T77
Test name
Test status
Simulation time 13513066278 ps
CPU time 11.85 seconds
Started Apr 02 12:28:49 PM PDT 24
Finished Apr 02 12:29:01 PM PDT 24
Peak memory 215192 kb
Host smart-4ae4b59f-6986-4913-9e3b-098719d631d8
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721711361 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 29.rv_dm_tap_fsm_rand_reset.3721711361
Directory /workspace/29.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.3000586816
Short name T98
Test name
Test status
Simulation time 3613126852 ps
CPU time 29.64 seconds
Started Apr 02 12:28:51 PM PDT 24
Finished Apr 02 12:29:20 PM PDT 24
Peak memory 213176 kb
Host smart-8675a985-8e9b-4bc7-be32-0d1752246d7c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000586816 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.3000586816
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.2531528707
Short name T336
Test name
Test status
Simulation time 30403590169 ps
CPU time 73.35 seconds
Started Apr 02 12:28:55 PM PDT 24
Finished Apr 02 12:30:08 PM PDT 24
Peak memory 204984 kb
Host smart-1f4932f5-bfde-46ee-ad8e-5a1c25a05ff4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531528707 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.2531528707
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.192261377
Short name T102
Test name
Test status
Simulation time 373549772 ps
CPU time 2.45 seconds
Started Apr 02 12:28:55 PM PDT 24
Finished Apr 02 12:28:58 PM PDT 24
Peak memory 213208 kb
Host smart-d4c1d554-78a4-4688-bf00-f39056d0b1f6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192261377 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.192261377
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.3108328809
Short name T365
Test name
Test status
Simulation time 84714704 ps
CPU time 2.1 seconds
Started Apr 02 12:28:51 PM PDT 24
Finished Apr 02 12:28:54 PM PDT 24
Peak memory 215012 kb
Host smart-a80c65e2-0609-4d7a-9345-ea555890cfee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108328809 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.3108328809
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.3842526541
Short name T261
Test name
Test status
Simulation time 52405167 ps
CPU time 1.45 seconds
Started Apr 02 12:28:52 PM PDT 24
Finished Apr 02 12:28:54 PM PDT 24
Peak memory 213184 kb
Host smart-c0dc6eca-12fb-46ba-9d1b-6aee9051e9d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842526541 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.3842526541
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1248185275
Short name T307
Test name
Test status
Simulation time 13253575695 ps
CPU time 18.69 seconds
Started Apr 02 12:29:12 PM PDT 24
Finished Apr 02 12:29:31 PM PDT 24
Peak memory 204764 kb
Host smart-88ecc78c-1259-46ec-8233-c1a775787776
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248185275 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.1248185275
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.871423791
Short name T236
Test name
Test status
Simulation time 9574134111 ps
CPU time 30.37 seconds
Started Apr 02 12:28:50 PM PDT 24
Finished Apr 02 12:29:20 PM PDT 24
Peak memory 204808 kb
Host smart-f38942c4-4b23-4bec-ab6c-7085835c13d4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871423791 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr
_bit_bash.871423791
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2923726726
Short name T246
Test name
Test status
Simulation time 677134424 ps
CPU time 1.3 seconds
Started Apr 02 12:28:50 PM PDT 24
Finished Apr 02 12:28:51 PM PDT 24
Peak memory 204792 kb
Host smart-c7a50bd3-1539-495d-905f-a49d638aaf0e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923726726 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.2923726726
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.2796637240
Short name T233
Test name
Test status
Simulation time 555615465 ps
CPU time 1.64 seconds
Started Apr 02 12:28:50 PM PDT 24
Finished Apr 02 12:28:52 PM PDT 24
Peak memory 204736 kb
Host smart-6419ccd3-25a3-4880-b3bd-ccf1be34e9da
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796637240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.2
796637240
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.15434948
Short name T332
Test name
Test status
Simulation time 134031195 ps
CPU time 0.89 seconds
Started Apr 02 12:28:50 PM PDT 24
Finished Apr 02 12:28:51 PM PDT 24
Peak memory 204556 kb
Host smart-56ca2d8b-155e-41dd-9c54-673d13429732
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15434948 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_
aliasing.15434948
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.846784746
Short name T58
Test name
Test status
Simulation time 1402284669 ps
CPU time 6.51 seconds
Started Apr 02 12:29:28 PM PDT 24
Finished Apr 02 12:29:35 PM PDT 24
Peak memory 204684 kb
Host smart-64600cf0-526f-4fe2-9ca1-704331542d7e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846784746 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr
_bit_bash.846784746
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.787886028
Short name T349
Test name
Test status
Simulation time 92335395 ps
CPU time 0.83 seconds
Started Apr 02 12:28:50 PM PDT 24
Finished Apr 02 12:28:51 PM PDT 24
Peak memory 204628 kb
Host smart-d7e25a8c-430e-4418-ba37-8efe1fa46265
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787886028 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr
_hw_reset.787886028
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.134175137
Short name T285
Test name
Test status
Simulation time 33323069 ps
CPU time 0.68 seconds
Started Apr 02 12:28:51 PM PDT 24
Finished Apr 02 12:28:52 PM PDT 24
Peak memory 204492 kb
Host smart-c8dd307e-1934-410b-8e4a-180cc65332dd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134175137 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.134175137
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.1858964282
Short name T231
Test name
Test status
Simulation time 16309740 ps
CPU time 0.67 seconds
Started Apr 02 12:28:46 PM PDT 24
Finished Apr 02 12:28:47 PM PDT 24
Peak memory 204508 kb
Host smart-bf6ad7db-986f-44c3-9fa2-4a611deafe44
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858964282 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.1858964282
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1197617916
Short name T260
Test name
Test status
Simulation time 48399199 ps
CPU time 0.66 seconds
Started Apr 02 12:29:23 PM PDT 24
Finished Apr 02 12:29:24 PM PDT 24
Peak memory 204632 kb
Host smart-5b299e7b-6a50-49a3-adb8-1a566de77990
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197617916 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.1197617916
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.237766904
Short name T94
Test name
Test status
Simulation time 782557703 ps
CPU time 7.02 seconds
Started Apr 02 12:28:50 PM PDT 24
Finished Apr 02 12:28:57 PM PDT 24
Peak memory 204932 kb
Host smart-c5ffd8ef-9b01-45cc-a01a-5879bb4b8053
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237766904 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_c
sr_outstanding.237766904
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.4085013882
Short name T317
Test name
Test status
Simulation time 80892041 ps
CPU time 2.27 seconds
Started Apr 02 12:28:50 PM PDT 24
Finished Apr 02 12:28:58 PM PDT 24
Peak memory 213104 kb
Host smart-69e551ea-2aad-43bc-942e-8b3c9ce05c7e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085013882 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.4085013882
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3207682039
Short name T124
Test name
Test status
Simulation time 986198966 ps
CPU time 19.01 seconds
Started Apr 02 12:28:50 PM PDT 24
Finished Apr 02 12:29:09 PM PDT 24
Peak memory 221280 kb
Host smart-9aa29585-b2fa-4766-85a0-ee9afe5d1abc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207682039 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.3207682039
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/32.rv_dm_tap_fsm_rand_reset.1450401494
Short name T277
Test name
Test status
Simulation time 5112187286 ps
CPU time 14.52 seconds
Started Apr 02 12:29:24 PM PDT 24
Finished Apr 02 12:29:39 PM PDT 24
Peak memory 219888 kb
Host smart-cda4ea97-2cef-4fff-9bfd-e756259cc213
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450401494 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 32.rv_dm_tap_fsm_rand_reset.1450401494
Directory /workspace/32.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/33.rv_dm_tap_fsm_rand_reset.3842405318
Short name T286
Test name
Test status
Simulation time 28382888231 ps
CPU time 25.68 seconds
Started Apr 02 12:28:54 PM PDT 24
Finished Apr 02 12:29:20 PM PDT 24
Peak memory 229504 kb
Host smart-c699b1b0-3ced-40bb-9d91-c2108c67f5f3
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842405318 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 33.rv_dm_tap_fsm_rand_reset.3842405318
Directory /workspace/33.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/34.rv_dm_tap_fsm_rand_reset.2658588026
Short name T75
Test name
Test status
Simulation time 12237164639 ps
CPU time 41.74 seconds
Started Apr 02 12:28:51 PM PDT 24
Finished Apr 02 12:29:33 PM PDT 24
Peak memory 220472 kb
Host smart-9f0f2b20-b57b-4ab8-b0a0-e15ae7c03399
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658588026 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 34.rv_dm_tap_fsm_rand_reset.2658588026
Directory /workspace/34.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/36.rv_dm_tap_fsm_rand_reset.1403990533
Short name T323
Test name
Test status
Simulation time 23902858860 ps
CPU time 24.17 seconds
Started Apr 02 12:28:53 PM PDT 24
Finished Apr 02 12:29:17 PM PDT 24
Peak memory 229820 kb
Host smart-ba27c29f-ff7f-4cc3-8ee6-c24bc3876811
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403990533 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 36.rv_dm_tap_fsm_rand_reset.1403990533
Directory /workspace/36.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/37.rv_dm_tap_fsm_rand_reset.377082627
Short name T39
Test name
Test status
Simulation time 5054038172 ps
CPU time 16.92 seconds
Started Apr 02 12:28:56 PM PDT 24
Finished Apr 02 12:29:13 PM PDT 24
Peak memory 213052 kb
Host smart-3912ecc7-0752-4862-918c-0e6af0c863dc
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377082627 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 37.rv_dm_tap_fsm_rand_reset.377082627
Directory /workspace/37.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/38.rv_dm_tap_fsm_rand_reset.3613614606
Short name T351
Test name
Test status
Simulation time 25324874889 ps
CPU time 25.42 seconds
Started Apr 02 12:29:27 PM PDT 24
Finished Apr 02 12:29:53 PM PDT 24
Peak memory 231892 kb
Host smart-37361abe-6660-4728-8e85-2d2876919aff
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613614606 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 38.rv_dm_tap_fsm_rand_reset.3613614606
Directory /workspace/38.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.2740020896
Short name T304
Test name
Test status
Simulation time 5096792965 ps
CPU time 64.31 seconds
Started Apr 02 12:28:50 PM PDT 24
Finished Apr 02 12:29:56 PM PDT 24
Peak memory 204936 kb
Host smart-486789de-0393-48a9-ac19-91e59a1a841f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740020896 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.2740020896
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.88560558
Short name T79
Test name
Test status
Simulation time 54015599 ps
CPU time 2.32 seconds
Started Apr 02 12:29:23 PM PDT 24
Finished Apr 02 12:29:25 PM PDT 24
Peak memory 213172 kb
Host smart-78e6b13a-9bc7-4224-b08b-6bcb33e3c068
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88560558 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.88560558
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.519606659
Short name T367
Test name
Test status
Simulation time 2471240350 ps
CPU time 5.09 seconds
Started Apr 02 12:28:45 PM PDT 24
Finished Apr 02 12:28:52 PM PDT 24
Peak memory 220268 kb
Host smart-b9f60a43-e897-46b0-945e-9ff0fd41f506
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519606659 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.519606659
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.2047775249
Short name T347
Test name
Test status
Simulation time 47066445 ps
CPU time 2.04 seconds
Started Apr 02 12:28:47 PM PDT 24
Finished Apr 02 12:28:50 PM PDT 24
Peak memory 218576 kb
Host smart-ac0cfeeb-a893-4e41-a693-a4cb05342932
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047775249 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.2047775249
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.180588594
Short name T322
Test name
Test status
Simulation time 6472826655 ps
CPU time 21.84 seconds
Started Apr 02 12:28:47 PM PDT 24
Finished Apr 02 12:29:10 PM PDT 24
Peak memory 204796 kb
Host smart-c594f0e0-cd25-4da9-ba37-1e7fb0ac0b71
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180588594 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr
_aliasing.180588594
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3294200304
Short name T296
Test name
Test status
Simulation time 12681226953 ps
CPU time 46.24 seconds
Started Apr 02 12:28:49 PM PDT 24
Finished Apr 02 12:29:43 PM PDT 24
Peak memory 204824 kb
Host smart-291026f8-c303-49bc-b1d9-e0a83ac8446f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294200304 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_bit_bash.3294200304
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.3960987903
Short name T87
Test name
Test status
Simulation time 341950336 ps
CPU time 1.76 seconds
Started Apr 02 12:29:02 PM PDT 24
Finished Apr 02 12:29:04 PM PDT 24
Peak memory 204880 kb
Host smart-4093dfcd-e568-4814-9797-c540e840cc67
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960987903 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.3960987903
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.553930269
Short name T237
Test name
Test status
Simulation time 766007637 ps
CPU time 1.14 seconds
Started Apr 02 12:28:48 PM PDT 24
Finished Apr 02 12:28:49 PM PDT 24
Peak memory 204752 kb
Host smart-3c3837c0-0741-43b8-bb77-fb6c6b56f039
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553930269 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.553930269
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.2634129704
Short name T243
Test name
Test status
Simulation time 214598334 ps
CPU time 0.73 seconds
Started Apr 02 12:28:51 PM PDT 24
Finished Apr 02 12:28:52 PM PDT 24
Peak memory 204496 kb
Host smart-091e806c-51d4-4200-85c9-d3b3e585d3cb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634129704 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.2634129704
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.3482409573
Short name T299
Test name
Test status
Simulation time 654984167 ps
CPU time 2.87 seconds
Started Apr 02 12:29:17 PM PDT 24
Finished Apr 02 12:29:20 PM PDT 24
Peak memory 204872 kb
Host smart-5b25a8ca-8c85-4f89-a756-1ed60ea04e6a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482409573 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.3482409573
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2227851281
Short name T375
Test name
Test status
Simulation time 92962834 ps
CPU time 0.96 seconds
Started Apr 02 12:28:49 PM PDT 24
Finished Apr 02 12:28:53 PM PDT 24
Peak memory 204624 kb
Host smart-2ee9ace6-cd46-4f55-97a3-279913600eba
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227851281 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.2227851281
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.1441951847
Short name T241
Test name
Test status
Simulation time 64037207 ps
CPU time 0.82 seconds
Started Apr 02 12:28:49 PM PDT 24
Finished Apr 02 12:28:50 PM PDT 24
Peak memory 204536 kb
Host smart-ebb1c60a-dad2-46b6-a609-4f43059e1b0a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441951847 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.1
441951847
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.313210029
Short name T294
Test name
Test status
Simulation time 16676635 ps
CPU time 0.66 seconds
Started Apr 02 12:28:43 PM PDT 24
Finished Apr 02 12:28:45 PM PDT 24
Peak memory 204496 kb
Host smart-8490d30a-02da-42e1-a6f1-426d75b09388
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313210029 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_part
ial_access.313210029
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.2467575264
Short name T352
Test name
Test status
Simulation time 96596441 ps
CPU time 0.68 seconds
Started Apr 02 12:28:51 PM PDT 24
Finished Apr 02 12:28:52 PM PDT 24
Peak memory 204584 kb
Host smart-297c9d1f-45d6-4020-9550-9da964b789e7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467575264 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.2467575264
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3908885379
Short name T89
Test name
Test status
Simulation time 280040340 ps
CPU time 3.35 seconds
Started Apr 02 12:28:50 PM PDT 24
Finished Apr 02 12:28:54 PM PDT 24
Peak memory 205028 kb
Host smart-ca7fe019-9eb5-46f8-ab33-65925e04456e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908885379 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.3908885379
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.3321642462
Short name T358
Test name
Test status
Simulation time 35232281579 ps
CPU time 21.46 seconds
Started Apr 02 12:29:20 PM PDT 24
Finished Apr 02 12:29:42 PM PDT 24
Peak memory 229432 kb
Host smart-9b3ec7c1-1f64-47ec-bae6-c97d5e1b18ed
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321642462 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.3321642462
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.182020273
Short name T247
Test name
Test status
Simulation time 131277546 ps
CPU time 2.41 seconds
Started Apr 02 12:28:51 PM PDT 24
Finished Apr 02 12:28:54 PM PDT 24
Peak memory 213084 kb
Host smart-91f1a045-45eb-482d-825b-bc54c3a0cc4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182020273 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.182020273
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.2374315618
Short name T330
Test name
Test status
Simulation time 527571634 ps
CPU time 9.97 seconds
Started Apr 02 12:29:02 PM PDT 24
Finished Apr 02 12:29:12 PM PDT 24
Peak memory 213076 kb
Host smart-90f668eb-13a2-4665-b702-c119edae6d9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374315618 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.2374315618
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.1964673104
Short name T251
Test name
Test status
Simulation time 2208311872 ps
CPU time 2.87 seconds
Started Apr 02 12:28:53 PM PDT 24
Finished Apr 02 12:28:56 PM PDT 24
Peak memory 214992 kb
Host smart-0555e804-8e68-4fe7-b4ac-7606e2da5d8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964673104 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.1964673104
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.3876908177
Short name T298
Test name
Test status
Simulation time 101396836 ps
CPU time 1.41 seconds
Started Apr 02 12:28:51 PM PDT 24
Finished Apr 02 12:28:52 PM PDT 24
Peak memory 212992 kb
Host smart-63d9d3b0-af09-479f-8c3c-afcc4bdc90e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876908177 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.3876908177
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3266669934
Short name T254
Test name
Test status
Simulation time 192619657 ps
CPU time 0.96 seconds
Started Apr 02 12:29:11 PM PDT 24
Finished Apr 02 12:29:12 PM PDT 24
Peak memory 204700 kb
Host smart-9d3db4d2-ba49-454c-93fb-313dd39b0b5f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266669934 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.3
266669934
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.4116427987
Short name T303
Test name
Test status
Simulation time 42600250 ps
CPU time 0.75 seconds
Started Apr 02 12:28:47 PM PDT 24
Finished Apr 02 12:28:49 PM PDT 24
Peak memory 204520 kb
Host smart-e702b4b0-fbd5-4ae2-a9ac-0c37a184fab0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116427987 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.4
116427987
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.2457391192
Short name T82
Test name
Test status
Simulation time 300424748 ps
CPU time 6.58 seconds
Started Apr 02 12:28:47 PM PDT 24
Finished Apr 02 12:28:54 PM PDT 24
Peak memory 204944 kb
Host smart-9332b1c4-4a1f-449d-943c-a0dd88fa0945
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457391192 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.2457391192
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.1465444187
Short name T348
Test name
Test status
Simulation time 13662097326 ps
CPU time 29.67 seconds
Started Apr 02 12:28:53 PM PDT 24
Finished Apr 02 12:29:22 PM PDT 24
Peak memory 229432 kb
Host smart-21414f92-7f7e-4e0d-94e9-377066e2eb98
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465444187 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.1465444187
Directory /workspace/5.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.204768135
Short name T276
Test name
Test status
Simulation time 54147437 ps
CPU time 3.31 seconds
Started Apr 02 12:28:45 PM PDT 24
Finished Apr 02 12:28:50 PM PDT 24
Peak memory 213040 kb
Host smart-97e59c2d-012f-4a7b-9a2f-0a1c6e022bd5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204768135 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.204768135
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2247230727
Short name T126
Test name
Test status
Simulation time 1716379827 ps
CPU time 9.14 seconds
Started Apr 02 12:28:53 PM PDT 24
Finished Apr 02 12:29:02 PM PDT 24
Peak memory 213080 kb
Host smart-f2f4000c-f028-498f-acbd-5c9ab3e47df4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247230727 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.2247230727
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.2774281797
Short name T84
Test name
Test status
Simulation time 209818983 ps
CPU time 1.47 seconds
Started Apr 02 12:28:54 PM PDT 24
Finished Apr 02 12:28:55 PM PDT 24
Peak memory 213008 kb
Host smart-d732e6cc-9709-4e41-99d9-25cb573e2b53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774281797 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.2774281797
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2714413524
Short name T309
Test name
Test status
Simulation time 305150807 ps
CPU time 1.84 seconds
Started Apr 02 12:28:46 PM PDT 24
Finished Apr 02 12:28:48 PM PDT 24
Peak memory 204728 kb
Host smart-fb65a3d9-5d80-4a5d-bfe9-39c4ad3958f8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714413524 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.2
714413524
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2564600215
Short name T245
Test name
Test status
Simulation time 75263860 ps
CPU time 0.75 seconds
Started Apr 02 12:29:37 PM PDT 24
Finished Apr 02 12:29:38 PM PDT 24
Peak memory 204568 kb
Host smart-feac3507-86fa-4d2c-9ffe-f04720be244e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564600215 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.2
564600215
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2901764740
Short name T80
Test name
Test status
Simulation time 144662639 ps
CPU time 3.37 seconds
Started Apr 02 12:28:56 PM PDT 24
Finished Apr 02 12:28:59 PM PDT 24
Peak memory 204832 kb
Host smart-d1bfeb50-1027-4e23-9910-37bfa533589b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901764740 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.2901764740
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.2226086464
Short name T38
Test name
Test status
Simulation time 10322357867 ps
CPU time 12.4 seconds
Started Apr 02 12:29:23 PM PDT 24
Finished Apr 02 12:29:35 PM PDT 24
Peak memory 221284 kb
Host smart-01a75462-9463-48ba-acb8-35cdd9ba2d64
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226086464 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.2226086464
Directory /workspace/6.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.3640977337
Short name T253
Test name
Test status
Simulation time 256093692 ps
CPU time 5.49 seconds
Started Apr 02 12:29:39 PM PDT 24
Finished Apr 02 12:29:45 PM PDT 24
Peak memory 213080 kb
Host smart-1f20b582-a39e-4f8d-baa2-1790f9432298
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640977337 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.3640977337
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.4052528994
Short name T132
Test name
Test status
Simulation time 3077155988 ps
CPU time 18.55 seconds
Started Apr 02 12:28:53 PM PDT 24
Finished Apr 02 12:29:11 PM PDT 24
Peak memory 221240 kb
Host smart-5a785878-5a40-4d13-923a-64137e0aabf9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052528994 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.4052528994
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3387338066
Short name T248
Test name
Test status
Simulation time 103361152 ps
CPU time 2.25 seconds
Started Apr 02 12:29:29 PM PDT 24
Finished Apr 02 12:29:32 PM PDT 24
Peak memory 213144 kb
Host smart-900e52e3-c321-438c-a08f-ec42d78a6e84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387338066 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.3387338066
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.4193401699
Short name T101
Test name
Test status
Simulation time 62202670 ps
CPU time 1.65 seconds
Started Apr 02 12:28:49 PM PDT 24
Finished Apr 02 12:28:51 PM PDT 24
Peak memory 218200 kb
Host smart-0dfffdec-262d-4580-9d5d-a79c0f47565d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193401699 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.4193401699
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2460161662
Short name T341
Test name
Test status
Simulation time 363543316 ps
CPU time 1.34 seconds
Started Apr 02 12:28:50 PM PDT 24
Finished Apr 02 12:28:51 PM PDT 24
Peak memory 204748 kb
Host smart-04a8ba2a-9fd2-426c-b63c-92754e12e4a1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460161662 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.2
460161662
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.2878128804
Short name T283
Test name
Test status
Simulation time 97841110 ps
CPU time 0.75 seconds
Started Apr 02 12:29:24 PM PDT 24
Finished Apr 02 12:29:25 PM PDT 24
Peak memory 204476 kb
Host smart-caf335ef-9cce-4fc1-9141-0e0614fb8dfe
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878128804 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.2
878128804
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.1303568141
Short name T308
Test name
Test status
Simulation time 147269377 ps
CPU time 6.46 seconds
Started Apr 02 12:29:15 PM PDT 24
Finished Apr 02 12:29:22 PM PDT 24
Peak memory 204884 kb
Host smart-2eb297bf-0be1-4226-af06-46a37225e785
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303568141 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.1303568141
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.2585063329
Short name T121
Test name
Test status
Simulation time 955745496 ps
CPU time 6.76 seconds
Started Apr 02 12:29:13 PM PDT 24
Finished Apr 02 12:29:20 PM PDT 24
Peak memory 213008 kb
Host smart-cd84c31b-90a9-4d27-8eed-05da0fb38f09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585063329 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.2585063329
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2578527699
Short name T355
Test name
Test status
Simulation time 2604232439 ps
CPU time 3.11 seconds
Started Apr 02 12:28:53 PM PDT 24
Finished Apr 02 12:28:56 PM PDT 24
Peak memory 218792 kb
Host smart-763abea1-e4d7-4188-a661-ee6a7a888b3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578527699 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.2578527699
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.4093120894
Short name T95
Test name
Test status
Simulation time 884426468 ps
CPU time 1.66 seconds
Started Apr 02 12:28:47 PM PDT 24
Finished Apr 02 12:28:50 PM PDT 24
Peak memory 213076 kb
Host smart-6677cd62-dae7-4832-81de-1309a08af3f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093120894 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.4093120894
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.625539873
Short name T376
Test name
Test status
Simulation time 546780389 ps
CPU time 1.34 seconds
Started Apr 02 12:28:48 PM PDT 24
Finished Apr 02 12:28:50 PM PDT 24
Peak memory 204732 kb
Host smart-63f6e3a4-03fa-4c94-9a84-0ec0ce01a7fb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625539873 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.625539873
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2341385547
Short name T353
Test name
Test status
Simulation time 72846635 ps
CPU time 0.76 seconds
Started Apr 02 12:28:48 PM PDT 24
Finished Apr 02 12:28:49 PM PDT 24
Peak memory 204544 kb
Host smart-a63d0ce9-a05d-43d4-86be-1ffa2dd269d6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341385547 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.2
341385547
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.3381516871
Short name T108
Test name
Test status
Simulation time 204352678 ps
CPU time 3.8 seconds
Started Apr 02 12:28:52 PM PDT 24
Finished Apr 02 12:28:56 PM PDT 24
Peak memory 204864 kb
Host smart-bf0b295c-8b07-47bb-ae05-17c03281435e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381516871 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_
csr_outstanding.3381516871
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.796387969
Short name T41
Test name
Test status
Simulation time 52502726 ps
CPU time 2.87 seconds
Started Apr 02 12:28:46 PM PDT 24
Finished Apr 02 12:28:49 PM PDT 24
Peak memory 213072 kb
Host smart-f1afded7-089c-47e8-be7c-4359e4ef1b46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796387969 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.796387969
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.1679160143
Short name T127
Test name
Test status
Simulation time 1040331359 ps
CPU time 9.56 seconds
Started Apr 02 12:29:25 PM PDT 24
Finished Apr 02 12:29:35 PM PDT 24
Peak memory 221128 kb
Host smart-50023d49-ac1e-44fb-a028-13bd25004f13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679160143 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.1679160143
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.328022387
Short name T340
Test name
Test status
Simulation time 144087909 ps
CPU time 2.06 seconds
Started Apr 02 12:29:59 PM PDT 24
Finished Apr 02 12:30:02 PM PDT 24
Peak memory 213256 kb
Host smart-cfc59f8f-fe19-4e23-be84-e34327af7a49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328022387 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.328022387
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.2310750148
Short name T109
Test name
Test status
Simulation time 73258348 ps
CPU time 2.07 seconds
Started Apr 02 12:28:44 PM PDT 24
Finished Apr 02 12:28:46 PM PDT 24
Peak memory 218416 kb
Host smart-9af2734a-014e-4e5e-89ab-e10da537e570
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310750148 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.2310750148
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.899003892
Short name T284
Test name
Test status
Simulation time 194848766 ps
CPU time 1.05 seconds
Started Apr 02 12:28:51 PM PDT 24
Finished Apr 02 12:28:53 PM PDT 24
Peak memory 204764 kb
Host smart-d60713b2-20e6-4e84-95d9-7d0d60a44a98
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899003892 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.899003892
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1386475560
Short name T338
Test name
Test status
Simulation time 162767387 ps
CPU time 0.7 seconds
Started Apr 02 12:28:51 PM PDT 24
Finished Apr 02 12:28:52 PM PDT 24
Peak memory 204588 kb
Host smart-5c356095-9aa8-4feb-9902-250904e721cf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386475560 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.1
386475560
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.2909288814
Short name T289
Test name
Test status
Simulation time 270145619 ps
CPU time 6.15 seconds
Started Apr 02 12:28:53 PM PDT 24
Finished Apr 02 12:29:00 PM PDT 24
Peak memory 204932 kb
Host smart-45b3f304-8cbb-40e6-992d-586c67bbf11e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909288814 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.2909288814
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.3703626990
Short name T280
Test name
Test status
Simulation time 170829525 ps
CPU time 3.53 seconds
Started Apr 02 12:29:01 PM PDT 24
Finished Apr 02 12:29:05 PM PDT 24
Peak memory 213080 kb
Host smart-318ef81c-ccd5-4d48-8459-62317b76fc3a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703626990 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.3703626990
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.1018486136
Short name T131
Test name
Test status
Simulation time 3892783482 ps
CPU time 9.16 seconds
Started Apr 02 12:28:59 PM PDT 24
Finished Apr 02 12:29:08 PM PDT 24
Peak memory 215812 kb
Host smart-eb0fbf3a-3f04-455b-ba23-6ab0b23e2a6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018486136 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.1018486136
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.2055925211
Short name T211
Test name
Test status
Simulation time 67249722 ps
CPU time 0.67 seconds
Started Apr 02 12:31:05 PM PDT 24
Finished Apr 02 12:31:06 PM PDT 24
Peak memory 204692 kb
Host smart-8be6e4f5-c9d8-446c-8353-820a39416962
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055925211 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.2055925211
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.191821355
Short name T179
Test name
Test status
Simulation time 9011774807 ps
CPU time 20.81 seconds
Started Apr 02 12:30:57 PM PDT 24
Finished Apr 02 12:31:18 PM PDT 24
Peak memory 205156 kb
Host smart-e275b668-e80c-4674-a9c3-3c47cbe7536f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191821355 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.191821355
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.259107925
Short name T182
Test name
Test status
Simulation time 2809121796 ps
CPU time 5.38 seconds
Started Apr 02 12:31:05 PM PDT 24
Finished Apr 02 12:31:11 PM PDT 24
Peak memory 213228 kb
Host smart-f93755c3-5e85-4f33-9783-962537584a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259107925 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.259107925
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.1068547877
Short name T111
Test name
Test status
Simulation time 2272941025 ps
CPU time 3.75 seconds
Started Apr 02 12:31:02 PM PDT 24
Finished Apr 02 12:31:06 PM PDT 24
Peak memory 204920 kb
Host smart-705d8650-34d6-4e60-be2b-ce917e1ccc5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068547877 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.1068547877
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.896694362
Short name T25
Test name
Test status
Simulation time 4008205783 ps
CPU time 3.2 seconds
Started Apr 02 12:31:23 PM PDT 24
Finished Apr 02 12:31:26 PM PDT 24
Peak memory 205024 kb
Host smart-670843d0-f99a-4395-b501-27d409f5de54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896694362 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.896694362
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.4071942337
Short name T135
Test name
Test status
Simulation time 36492491 ps
CPU time 0.72 seconds
Started Apr 02 12:31:08 PM PDT 24
Finished Apr 02 12:31:09 PM PDT 24
Peak memory 204700 kb
Host smart-55ce65ba-26f3-4906-b35a-11d2b34f39d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071942337 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.4071942337
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.87108212
Short name T5
Test name
Test status
Simulation time 797281661 ps
CPU time 3.16 seconds
Started Apr 02 12:31:10 PM PDT 24
Finished Apr 02 12:31:13 PM PDT 24
Peak memory 204912 kb
Host smart-5606d0ca-729b-4d51-b6e7-cd1e2ae7ef7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87108212 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.87108212
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.3004670038
Short name T228
Test name
Test status
Simulation time 60682196 ps
CPU time 0.82 seconds
Started Apr 02 12:31:04 PM PDT 24
Finished Apr 02 12:31:05 PM PDT 24
Peak memory 204512 kb
Host smart-0b9374da-6ba7-4704-84eb-dda7ead30cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004670038 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.3004670038
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.2942919586
Short name T19
Test name
Test status
Simulation time 127157470 ps
CPU time 0.85 seconds
Started Apr 02 12:31:08 PM PDT 24
Finished Apr 02 12:31:09 PM PDT 24
Peak memory 204496 kb
Host smart-677385c0-29f0-475f-bfe7-6d19379fafe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942919586 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.2942919586
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.3860339845
Short name T227
Test name
Test status
Simulation time 676992666 ps
CPU time 1.98 seconds
Started Apr 02 12:30:55 PM PDT 24
Finished Apr 02 12:30:57 PM PDT 24
Peak memory 204756 kb
Host smart-56f598a7-5677-4b7c-b2d6-a766a7cfa04d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860339845 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.3860339845
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.826573708
Short name T10
Test name
Test status
Simulation time 56115969 ps
CPU time 0.8 seconds
Started Apr 02 12:31:12 PM PDT 24
Finished Apr 02 12:31:13 PM PDT 24
Peak memory 204572 kb
Host smart-73f70ef4-6e20-4815-801c-cce13deda117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826573708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.826573708
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.1694795668
Short name T137
Test name
Test status
Simulation time 84836503 ps
CPU time 0.75 seconds
Started Apr 02 12:30:55 PM PDT 24
Finished Apr 02 12:30:56 PM PDT 24
Peak memory 204688 kb
Host smart-0b2e5a87-7135-44dc-970e-499b1d31ddc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694795668 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.1694795668
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.3676130629
Short name T134
Test name
Test status
Simulation time 329570792 ps
CPU time 1.33 seconds
Started Apr 02 12:31:05 PM PDT 24
Finished Apr 02 12:31:07 PM PDT 24
Peak memory 204904 kb
Host smart-db6f0f88-cbb0-4729-a232-2bc537869e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676130629 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.3676130629
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.769809298
Short name T136
Test name
Test status
Simulation time 172086463 ps
CPU time 1.02 seconds
Started Apr 02 12:30:54 PM PDT 24
Finished Apr 02 12:30:55 PM PDT 24
Peak memory 204708 kb
Host smart-f7e9a916-3a49-4474-ad18-49b3a38b7890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769809298 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.769809298
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.2141523976
Short name T167
Test name
Test status
Simulation time 4715096183 ps
CPU time 7.48 seconds
Started Apr 02 12:30:57 PM PDT 24
Finished Apr 02 12:31:05 PM PDT 24
Peak memory 205004 kb
Host smart-4d0f5a0f-bdae-4038-8891-28dc2793b704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141523976 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.2141523976
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.2886314241
Short name T213
Test name
Test status
Simulation time 225345343 ps
CPU time 1.33 seconds
Started Apr 02 12:31:08 PM PDT 24
Finished Apr 02 12:31:09 PM PDT 24
Peak memory 204776 kb
Host smart-aefe73d0-72aa-473e-b05b-0945a2e46ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886314241 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.2886314241
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.3386795744
Short name T57
Test name
Test status
Simulation time 1134700904 ps
CPU time 3.96 seconds
Started Apr 02 12:31:11 PM PDT 24
Finished Apr 02 12:31:15 PM PDT 24
Peak memory 204896 kb
Host smart-5b4dff15-0d60-43b4-b55a-26f0a99b8692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386795744 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.3386795744
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.3965838373
Short name T148
Test name
Test status
Simulation time 47934078 ps
CPU time 0.69 seconds
Started Apr 02 12:31:13 PM PDT 24
Finished Apr 02 12:31:14 PM PDT 24
Peak memory 204684 kb
Host smart-aae236ad-9b81-48c6-8db6-ada6b0171c71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965838373 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.3965838373
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.1010125220
Short name T224
Test name
Test status
Simulation time 4548528341 ps
CPU time 9.15 seconds
Started Apr 02 12:31:06 PM PDT 24
Finished Apr 02 12:31:15 PM PDT 24
Peak memory 213360 kb
Host smart-116ba35b-6924-497a-a820-f691e1277e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010125220 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.1010125220
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.4190526527
Short name T13
Test name
Test status
Simulation time 1695150884 ps
CPU time 3.34 seconds
Started Apr 02 12:31:17 PM PDT 24
Finished Apr 02 12:31:21 PM PDT 24
Peak memory 204912 kb
Host smart-ec056529-3602-4dc7-bac1-6f22e7377344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190526527 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.4190526527
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.3260430982
Short name T15
Test name
Test status
Simulation time 289922523 ps
CPU time 1.18 seconds
Started Apr 02 12:31:09 PM PDT 24
Finished Apr 02 12:31:10 PM PDT 24
Peak memory 204652 kb
Host smart-fef4a55a-d326-4120-8746-d182fb378126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260430982 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.3260430982
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.1719535005
Short name T50
Test name
Test status
Simulation time 335765516 ps
CPU time 0.99 seconds
Started Apr 02 12:31:12 PM PDT 24
Finished Apr 02 12:31:13 PM PDT 24
Peak memory 204584 kb
Host smart-dea0ee6d-2a0a-4335-9fac-9f46d6ef39c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719535005 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.1719535005
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.3497077718
Short name T6
Test name
Test status
Simulation time 6201555192 ps
CPU time 3.21 seconds
Started Apr 02 12:31:09 PM PDT 24
Finished Apr 02 12:31:13 PM PDT 24
Peak memory 205060 kb
Host smart-74f69e91-3ca7-417c-87bd-7c01d29ab525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497077718 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.3497077718
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.1734284414
Short name T226
Test name
Test status
Simulation time 97484472 ps
CPU time 0.8 seconds
Started Apr 02 12:31:15 PM PDT 24
Finished Apr 02 12:31:16 PM PDT 24
Peak memory 204648 kb
Host smart-2007a9af-e7d1-4ae9-86b2-a55c57de7470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734284414 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.1734284414
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.3515062602
Short name T8
Test name
Test status
Simulation time 1247641209 ps
CPU time 1.87 seconds
Started Apr 02 12:31:11 PM PDT 24
Finished Apr 02 12:31:13 PM PDT 24
Peak memory 204960 kb
Host smart-8ba5f57c-6373-4645-881c-99ec777b2f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515062602 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.3515062602
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.635134866
Short name T174
Test name
Test status
Simulation time 65192728 ps
CPU time 0.85 seconds
Started Apr 02 12:31:02 PM PDT 24
Finished Apr 02 12:31:03 PM PDT 24
Peak memory 204476 kb
Host smart-3d2864e0-e726-4e31-b509-e0f55aed0314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635134866 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.635134866
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.4154280766
Short name T17
Test name
Test status
Simulation time 132305842 ps
CPU time 1.09 seconds
Started Apr 02 12:31:14 PM PDT 24
Finished Apr 02 12:31:15 PM PDT 24
Peak memory 204512 kb
Host smart-10fd2015-3b02-4c93-be74-50372f998e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154280766 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.4154280766
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.3785509445
Short name T56
Test name
Test status
Simulation time 377417831 ps
CPU time 1.38 seconds
Started Apr 02 12:31:15 PM PDT 24
Finished Apr 02 12:31:16 PM PDT 24
Peak memory 204668 kb
Host smart-270694e5-bf09-4a72-891e-d14d1bdb7546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785509445 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.3785509445
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.677969896
Short name T24
Test name
Test status
Simulation time 45308289 ps
CPU time 0.8 seconds
Started Apr 02 12:31:12 PM PDT 24
Finished Apr 02 12:31:13 PM PDT 24
Peak memory 204620 kb
Host smart-65c6604d-2b2f-467d-b91d-e747dad04dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677969896 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.677969896
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.4033368791
Short name T205
Test name
Test status
Simulation time 104873729 ps
CPU time 0.82 seconds
Started Apr 02 12:31:15 PM PDT 24
Finished Apr 02 12:31:16 PM PDT 24
Peak memory 204588 kb
Host smart-28d154bc-68ef-4f8c-814e-b8488895b2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033368791 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.4033368791
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.1374846949
Short name T51
Test name
Test status
Simulation time 404939390 ps
CPU time 1.05 seconds
Started Apr 02 12:31:10 PM PDT 24
Finished Apr 02 12:31:11 PM PDT 24
Peak memory 204764 kb
Host smart-44224dc4-986c-4277-be84-4a97b7d2175a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374846949 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.1374846949
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.2581631606
Short name T20
Test name
Test status
Simulation time 169960183 ps
CPU time 1.32 seconds
Started Apr 02 12:31:05 PM PDT 24
Finished Apr 02 12:31:07 PM PDT 24
Peak memory 204928 kb
Host smart-705b851a-2ca5-48bb-949d-1c8d416770cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581631606 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.2581631606
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.1771453467
Short name T9
Test name
Test status
Simulation time 29076475 ps
CPU time 0.76 seconds
Started Apr 02 12:31:11 PM PDT 24
Finished Apr 02 12:31:12 PM PDT 24
Peak memory 204728 kb
Host smart-7851d249-af21-452a-a699-49b4bd565b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771453467 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.1771453467
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.3804066704
Short name T53
Test name
Test status
Simulation time 23319393 ps
CPU time 0.77 seconds
Started Apr 02 12:31:12 PM PDT 24
Finished Apr 02 12:31:12 PM PDT 24
Peak memory 212928 kb
Host smart-7af32efc-3848-4158-a97a-3136c021c035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804066704 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.3804066704
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.631695881
Short name T194
Test name
Test status
Simulation time 2557044780 ps
CPU time 7.79 seconds
Started Apr 02 12:31:12 PM PDT 24
Finished Apr 02 12:31:20 PM PDT 24
Peak memory 205056 kb
Host smart-7c324603-7fdc-4d18-9567-0fcbb9233ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631695881 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.631695881
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.3708825907
Short name T48
Test name
Test status
Simulation time 123312288 ps
CPU time 1.18 seconds
Started Apr 02 12:31:23 PM PDT 24
Finished Apr 02 12:31:24 PM PDT 24
Peak memory 228200 kb
Host smart-655fa79c-1373-4f40-9990-17b84fc5cda3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708825907 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.3708825907
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.2176758957
Short name T21
Test name
Test status
Simulation time 190551844 ps
CPU time 1.35 seconds
Started Apr 02 12:31:25 PM PDT 24
Finished Apr 02 12:31:27 PM PDT 24
Peak memory 204512 kb
Host smart-73057500-b11e-4cd0-865e-0eccc75580a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176758957 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.2176758957
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.1555154837
Short name T68
Test name
Test status
Simulation time 14604196 ps
CPU time 0.74 seconds
Started Apr 02 12:31:29 PM PDT 24
Finished Apr 02 12:31:30 PM PDT 24
Peak memory 204716 kb
Host smart-875fe6de-4bac-4bcc-8b6b-e6ace15bd9c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555154837 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.1555154837
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.1940153229
Short name T204
Test name
Test status
Simulation time 6523537545 ps
CPU time 7.17 seconds
Started Apr 02 12:31:24 PM PDT 24
Finished Apr 02 12:31:32 PM PDT 24
Peak memory 215020 kb
Host smart-47ee77b2-c70b-4850-b84c-1377b0c3395b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940153229 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.1940153229
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.3050402567
Short name T86
Test name
Test status
Simulation time 350181274 ps
CPU time 1.97 seconds
Started Apr 02 12:31:23 PM PDT 24
Finished Apr 02 12:31:25 PM PDT 24
Peak memory 205048 kb
Host smart-506c2a51-b44c-449c-aab3-22cb6781a8e7
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3050402567 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.3050402567
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.2887193204
Short name T225
Test name
Test status
Simulation time 3022015219 ps
CPU time 12.21 seconds
Started Apr 02 12:31:27 PM PDT 24
Finished Apr 02 12:31:40 PM PDT 24
Peak memory 205072 kb
Host smart-7511d897-a0f7-4daa-aa91-afd413746fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887193204 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.2887193204
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.4168766223
Short name T120
Test name
Test status
Simulation time 49344330 ps
CPU time 0.68 seconds
Started Apr 02 12:31:28 PM PDT 24
Finished Apr 02 12:31:30 PM PDT 24
Peak memory 204700 kb
Host smart-d89d2cad-9c65-4919-9365-d3dfa0673b65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168766223 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.4168766223
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.3159195369
Short name T187
Test name
Test status
Simulation time 676999107 ps
CPU time 2.96 seconds
Started Apr 02 12:31:30 PM PDT 24
Finished Apr 02 12:31:33 PM PDT 24
Peak memory 205036 kb
Host smart-c551ce29-7676-4ee4-ba36-14b25fc5d67c
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3159195369 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_
tl_access.3159195369
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.2778421734
Short name T3
Test name
Test status
Simulation time 1749996435 ps
CPU time 8.16 seconds
Started Apr 02 12:31:29 PM PDT 24
Finished Apr 02 12:31:37 PM PDT 24
Peak memory 205032 kb
Host smart-6c08dc3c-190e-4b3c-aa89-af83251b0b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778421734 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.2778421734
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.4049260201
Short name T138
Test name
Test status
Simulation time 52468258 ps
CPU time 0.73 seconds
Started Apr 02 12:31:26 PM PDT 24
Finished Apr 02 12:31:27 PM PDT 24
Peak memory 204656 kb
Host smart-acdbacad-31f0-4bfa-a668-680df36804bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049260201 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.4049260201
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.867023004
Short name T118
Test name
Test status
Simulation time 3119432998 ps
CPU time 6.91 seconds
Started Apr 02 12:31:21 PM PDT 24
Finished Apr 02 12:31:28 PM PDT 24
Peak memory 205120 kb
Host smart-0c9adbee-a98e-4573-ae3b-22bead986c48
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=867023004 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_t
l_access.867023004
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.64922818
Short name T49
Test name
Test status
Simulation time 1977585170 ps
CPU time 9.69 seconds
Started Apr 02 12:31:27 PM PDT 24
Finished Apr 02 12:31:38 PM PDT 24
Peak memory 205016 kb
Host smart-6e4a27c0-766c-4938-be35-3f75a2fc618d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64922818 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.64922818
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.3114767658
Short name T163
Test name
Test status
Simulation time 32145438 ps
CPU time 0.71 seconds
Started Apr 02 12:31:26 PM PDT 24
Finished Apr 02 12:31:27 PM PDT 24
Peak memory 204700 kb
Host smart-fafc0113-9c9e-4cdd-85bc-b9197cc4ff1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114767658 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.3114767658
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.3651260880
Short name T183
Test name
Test status
Simulation time 6544230403 ps
CPU time 20.2 seconds
Started Apr 02 12:31:30 PM PDT 24
Finished Apr 02 12:31:50 PM PDT 24
Peak memory 205036 kb
Host smart-c7e20063-e4c8-4369-80f4-b7f1348d1a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651260880 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.3651260880
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.809188107
Short name T218
Test name
Test status
Simulation time 2660549090 ps
CPU time 5.85 seconds
Started Apr 02 12:31:28 PM PDT 24
Finished Apr 02 12:31:34 PM PDT 24
Peak memory 214864 kb
Host smart-c9a3289c-ea6d-4101-82bf-79807c4c4bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809188107 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.809188107
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.3917007064
Short name T206
Test name
Test status
Simulation time 837352769 ps
CPU time 1.79 seconds
Started Apr 02 12:31:26 PM PDT 24
Finished Apr 02 12:31:28 PM PDT 24
Peak memory 205060 kb
Host smart-4f75abf5-7a96-46a7-97a1-4cc6a186360b
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3917007064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_
tl_access.3917007064
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.3753070912
Short name T184
Test name
Test status
Simulation time 10928494399 ps
CPU time 33.66 seconds
Started Apr 02 12:31:32 PM PDT 24
Finished Apr 02 12:32:06 PM PDT 24
Peak memory 213212 kb
Host smart-30750e8a-b395-4907-a78c-fdee142e5651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753070912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.3753070912
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.1891812158
Short name T151
Test name
Test status
Simulation time 73882962 ps
CPU time 0.72 seconds
Started Apr 02 12:31:35 PM PDT 24
Finished Apr 02 12:31:36 PM PDT 24
Peak memory 204536 kb
Host smart-d9084fa9-45a0-4acb-bdfc-bae748d0e1fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891812158 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.1891812158
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.889019283
Short name T11
Test name
Test status
Simulation time 3062840559 ps
CPU time 9.05 seconds
Started Apr 02 12:31:28 PM PDT 24
Finished Apr 02 12:31:37 PM PDT 24
Peak memory 213220 kb
Host smart-2d58576c-037d-4566-b428-82c315dc1bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889019283 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.889019283
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.3884952179
Short name T171
Test name
Test status
Simulation time 5210233320 ps
CPU time 6 seconds
Started Apr 02 12:31:27 PM PDT 24
Finished Apr 02 12:31:34 PM PDT 24
Peak memory 205072 kb
Host smart-7ffed81d-bf90-4655-a7bd-c98b37627826
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3884952179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.3884952179
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.4184204194
Short name T212
Test name
Test status
Simulation time 12489690422 ps
CPU time 19.93 seconds
Started Apr 02 12:31:31 PM PDT 24
Finished Apr 02 12:31:51 PM PDT 24
Peak memory 205096 kb
Host smart-57526650-2855-46f5-adfc-7a5ef5895923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184204194 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.4184204194
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.3863515453
Short name T155
Test name
Test status
Simulation time 26227539 ps
CPU time 0.73 seconds
Started Apr 02 12:31:28 PM PDT 24
Finished Apr 02 12:31:29 PM PDT 24
Peak memory 204556 kb
Host smart-d9073f4e-07f7-47f7-a56e-b587b0d6087a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863515453 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.3863515453
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.1045103157
Short name T22
Test name
Test status
Simulation time 7314329219 ps
CPU time 21.39 seconds
Started Apr 02 12:31:26 PM PDT 24
Finished Apr 02 12:31:48 PM PDT 24
Peak memory 205100 kb
Host smart-d8ce6c4d-e613-4baa-aaf9-7f89bcfe1ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045103157 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.1045103157
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.2717266532
Short name T201
Test name
Test status
Simulation time 1609007384 ps
CPU time 5.76 seconds
Started Apr 02 12:31:30 PM PDT 24
Finished Apr 02 12:31:36 PM PDT 24
Peak memory 205004 kb
Host smart-d5a487c5-04a9-466d-b006-09af483bbffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717266532 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.2717266532
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.3185629017
Short name T169
Test name
Test status
Simulation time 2358336427 ps
CPU time 8.73 seconds
Started Apr 02 12:31:35 PM PDT 24
Finished Apr 02 12:31:49 PM PDT 24
Peak memory 205052 kb
Host smart-82d8bee0-d0ca-440a-880b-bd06a6c6b4c7
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3185629017 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_
tl_access.3185629017
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.4113719387
Short name T196
Test name
Test status
Simulation time 1700563534 ps
CPU time 8.18 seconds
Started Apr 02 12:31:29 PM PDT 24
Finished Apr 02 12:31:37 PM PDT 24
Peak memory 204984 kb
Host smart-b1cfbcd5-b511-4cfd-a900-3eb3b49ada80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113719387 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.4113719387
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.1950415311
Short name T200
Test name
Test status
Simulation time 20028689719 ps
CPU time 35.78 seconds
Started Apr 02 12:31:31 PM PDT 24
Finished Apr 02 12:32:07 PM PDT 24
Peak memory 213232 kb
Host smart-ecadc845-ebd3-41b8-96a6-ebe6c9deed17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950415311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.1950415311
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.2711678543
Short name T191
Test name
Test status
Simulation time 10785392390 ps
CPU time 33.7 seconds
Started Apr 02 12:31:30 PM PDT 24
Finished Apr 02 12:32:04 PM PDT 24
Peak memory 205028 kb
Host smart-74a8b039-fc23-4867-9d69-3eaa00affb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711678543 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.2711678543
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.64103451
Short name T214
Test name
Test status
Simulation time 2435502069 ps
CPU time 7.66 seconds
Started Apr 02 12:31:30 PM PDT 24
Finished Apr 02 12:31:37 PM PDT 24
Peak memory 204992 kb
Host smart-00865066-6b64-4c8c-8abb-73c2f3404a26
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=64103451 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_tl
_access.64103451
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.55613974
Short name T177
Test name
Test status
Simulation time 2174185673 ps
CPU time 3.73 seconds
Started Apr 02 12:31:28 PM PDT 24
Finished Apr 02 12:31:32 PM PDT 24
Peak memory 204908 kb
Host smart-7945143a-d901-4307-9d52-6fc1e15c7ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55613974 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.55613974
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.1709270054
Short name T139
Test name
Test status
Simulation time 33154915 ps
CPU time 0.69 seconds
Started Apr 02 12:31:29 PM PDT 24
Finished Apr 02 12:31:30 PM PDT 24
Peak memory 204640 kb
Host smart-f058cf0a-689a-46a8-859d-5fc64c4ff37a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709270054 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.1709270054
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.2247186410
Short name T216
Test name
Test status
Simulation time 8874869072 ps
CPU time 28.12 seconds
Started Apr 02 12:31:25 PM PDT 24
Finished Apr 02 12:31:54 PM PDT 24
Peak memory 215620 kb
Host smart-8cd4f8ff-c5a6-4920-97c5-14e197fb8ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247186410 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.2247186410
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.1486520861
Short name T193
Test name
Test status
Simulation time 1073279751 ps
CPU time 2.51 seconds
Started Apr 02 12:31:29 PM PDT 24
Finished Apr 02 12:31:32 PM PDT 24
Peak memory 204888 kb
Host smart-d6c9737c-3e8b-4bf2-8fe3-0d5c512da75f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1486520861 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_
tl_access.1486520861
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.2933181001
Short name T198
Test name
Test status
Simulation time 4869821471 ps
CPU time 8.1 seconds
Started Apr 02 12:31:27 PM PDT 24
Finished Apr 02 12:31:36 PM PDT 24
Peak memory 205040 kb
Host smart-f83113ec-5c64-4f38-bc9a-af845902c37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933181001 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.2933181001
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_stress_all.4030107090
Short name T33
Test name
Test status
Simulation time 7814033867 ps
CPU time 4.72 seconds
Started Apr 02 12:31:24 PM PDT 24
Finished Apr 02 12:31:30 PM PDT 24
Peak memory 204984 kb
Host smart-68639efe-cf20-4b48-9498-528b93037300
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030107090 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.4030107090
Directory /workspace/17.rv_dm_stress_all/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.2034334332
Short name T162
Test name
Test status
Simulation time 118739697 ps
CPU time 0.66 seconds
Started Apr 02 12:31:37 PM PDT 24
Finished Apr 02 12:31:38 PM PDT 24
Peak memory 204736 kb
Host smart-9fe37506-c6c0-4cbc-80d7-a9cdae3c8cee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034334332 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.2034334332
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.1667741677
Short name T223
Test name
Test status
Simulation time 4030325382 ps
CPU time 9.57 seconds
Started Apr 02 12:31:30 PM PDT 24
Finished Apr 02 12:31:40 PM PDT 24
Peak memory 205032 kb
Host smart-ef03df63-a3af-4e9b-b675-b007f5f45961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667741677 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.1667741677
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.1881413797
Short name T189
Test name
Test status
Simulation time 1986241262 ps
CPU time 6.88 seconds
Started Apr 02 12:31:29 PM PDT 24
Finished Apr 02 12:31:36 PM PDT 24
Peak memory 213220 kb
Host smart-d0d534a7-498b-4c02-baf3-576e7f063524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881413797 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.1881413797
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.730254605
Short name T168
Test name
Test status
Simulation time 4255499482 ps
CPU time 6.66 seconds
Started Apr 02 12:31:29 PM PDT 24
Finished Apr 02 12:31:36 PM PDT 24
Peak memory 213372 kb
Host smart-11b0d1ed-b506-493f-8374-1a584a40f7dc
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=730254605 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_t
l_access.730254605
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.1289777288
Short name T165
Test name
Test status
Simulation time 1171690655 ps
CPU time 4.61 seconds
Started Apr 02 12:31:26 PM PDT 24
Finished Apr 02 12:31:33 PM PDT 24
Peak memory 204872 kb
Host smart-3c3bd7e4-c322-44c7-91b6-b78956aa2b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289777288 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.1289777288
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.181264
Short name T219
Test name
Test status
Simulation time 2266534154 ps
CPU time 4.86 seconds
Started Apr 02 12:31:28 PM PDT 24
Finished Apr 02 12:31:33 PM PDT 24
Peak memory 213180 kb
Host smart-c7ed7198-adf7-41ec-b791-45713b60fd4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181264 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.181264
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.3106377812
Short name T173
Test name
Test status
Simulation time 3683529972 ps
CPU time 6.44 seconds
Started Apr 02 12:31:35 PM PDT 24
Finished Apr 02 12:31:42 PM PDT 24
Peak memory 213008 kb
Host smart-ea665188-3210-4dd8-9ca0-fb6cdb6393a4
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3106377812 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_
tl_access.3106377812
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.1123106985
Short name T215
Test name
Test status
Simulation time 1018210873 ps
CPU time 1.8 seconds
Started Apr 02 12:31:27 PM PDT 24
Finished Apr 02 12:31:30 PM PDT 24
Peak memory 205104 kb
Host smart-1af53df3-ae16-4f2c-bae4-ae6594be7fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123106985 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.1123106985
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.3745720880
Short name T149
Test name
Test status
Simulation time 52952601 ps
CPU time 0.71 seconds
Started Apr 02 12:31:13 PM PDT 24
Finished Apr 02 12:31:14 PM PDT 24
Peak memory 204720 kb
Host smart-604172b0-f129-44e3-8595-ebc05ca83e67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745720880 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.3745720880
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.1992878495
Short name T113
Test name
Test status
Simulation time 4695287533 ps
CPU time 8.18 seconds
Started Apr 02 12:31:08 PM PDT 24
Finished Apr 02 12:31:17 PM PDT 24
Peak memory 215480 kb
Host smart-b6ce6935-7fc2-4710-84a2-af476ae00ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992878495 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.1992878495
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.3368518356
Short name T192
Test name
Test status
Simulation time 2768188527 ps
CPU time 6.14 seconds
Started Apr 02 12:31:18 PM PDT 24
Finished Apr 02 12:31:24 PM PDT 24
Peak memory 205060 kb
Host smart-69fb408f-cf02-41ec-a96c-46aef94b3eff
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3368518356 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.3368518356
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.892054246
Short name T175
Test name
Test status
Simulation time 88677884 ps
CPU time 0.8 seconds
Started Apr 02 12:31:19 PM PDT 24
Finished Apr 02 12:31:20 PM PDT 24
Peak memory 204540 kb
Host smart-edd7a64e-2aab-46d9-8170-a7a49077dcce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892054246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.892054246
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.877879352
Short name T37
Test name
Test status
Simulation time 5144426847 ps
CPU time 8.13 seconds
Started Apr 02 12:31:09 PM PDT 24
Finished Apr 02 12:31:17 PM PDT 24
Peak memory 213320 kb
Host smart-e72b45f5-8913-459b-8650-c2ce829157d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877879352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.877879352
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.4117031079
Short name T47
Test name
Test status
Simulation time 99068915 ps
CPU time 1.14 seconds
Started Apr 02 12:31:20 PM PDT 24
Finished Apr 02 12:31:21 PM PDT 24
Peak memory 229144 kb
Host smart-3ac208ed-1cc3-45ae-8e5e-f66a2e33971c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117031079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.4117031079
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all.4278256476
Short name T34
Test name
Test status
Simulation time 6693864791 ps
CPU time 6.06 seconds
Started Apr 02 12:31:08 PM PDT 24
Finished Apr 02 12:31:14 PM PDT 24
Peak memory 205036 kb
Host smart-b7dedcd0-2bb4-45e6-a9a4-41c482e6ded9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278256476 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.4278256476
Directory /workspace/2.rv_dm_stress_all/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.1113923357
Short name T152
Test name
Test status
Simulation time 33860369 ps
CPU time 0.7 seconds
Started Apr 02 12:31:27 PM PDT 24
Finished Apr 02 12:31:29 PM PDT 24
Peak memory 204672 kb
Host smart-b3415ff2-7094-4da1-9059-6f67026492c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113923357 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.1113923357
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.299077398
Short name T72
Test name
Test status
Simulation time 27980931 ps
CPU time 0.67 seconds
Started Apr 02 12:31:33 PM PDT 24
Finished Apr 02 12:31:35 PM PDT 24
Peak memory 204736 kb
Host smart-3ec774c9-6727-4905-8b00-6dc7ded87593
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299077398 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.299077398
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.3785635559
Short name T203
Test name
Test status
Simulation time 23210220 ps
CPU time 0.68 seconds
Started Apr 02 12:31:33 PM PDT 24
Finished Apr 02 12:31:35 PM PDT 24
Peak memory 204700 kb
Host smart-5320cdd4-a91a-4f18-9797-8ccf774eb02f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785635559 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.3785635559
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.2571961554
Short name T78
Test name
Test status
Simulation time 17041072 ps
CPU time 0.68 seconds
Started Apr 02 12:31:31 PM PDT 24
Finished Apr 02 12:31:31 PM PDT 24
Peak memory 204672 kb
Host smart-8a0f641f-5dec-41d0-bc13-e7c4b75d3242
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571961554 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.2571961554
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.3947296244
Short name T199
Test name
Test status
Simulation time 19814731 ps
CPU time 0.72 seconds
Started Apr 02 12:31:25 PM PDT 24
Finished Apr 02 12:31:26 PM PDT 24
Peak memory 204708 kb
Host smart-02e44725-c84a-47c1-87b5-fbafb8068b4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947296244 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.3947296244
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.3525242795
Short name T158
Test name
Test status
Simulation time 49297169 ps
CPU time 0.69 seconds
Started Apr 02 12:31:55 PM PDT 24
Finished Apr 02 12:31:56 PM PDT 24
Peak memory 204308 kb
Host smart-41844456-2edd-413e-a279-6a40ab7868f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525242795 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.3525242795
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.1823123393
Short name T144
Test name
Test status
Simulation time 27928506 ps
CPU time 0.7 seconds
Started Apr 02 12:31:24 PM PDT 24
Finished Apr 02 12:31:25 PM PDT 24
Peak memory 204596 kb
Host smart-f33dae55-4611-4112-bc93-92085e01d0da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823123393 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.1823123393
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.806808859
Short name T145
Test name
Test status
Simulation time 22989981 ps
CPU time 0.76 seconds
Started Apr 02 12:31:30 PM PDT 24
Finished Apr 02 12:31:31 PM PDT 24
Peak memory 204700 kb
Host smart-d2c660b4-6efa-4513-9f54-bba167850482
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806808859 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.806808859
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.3722606333
Short name T62
Test name
Test status
Simulation time 18902975 ps
CPU time 0.73 seconds
Started Apr 02 12:31:29 PM PDT 24
Finished Apr 02 12:31:30 PM PDT 24
Peak memory 204704 kb
Host smart-e8726e6a-d11d-4cb3-a9b3-6f4099745ac2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722606333 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.3722606333
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.792787626
Short name T27
Test name
Test status
Simulation time 29160935 ps
CPU time 0.68 seconds
Started Apr 02 12:31:55 PM PDT 24
Finished Apr 02 12:31:56 PM PDT 24
Peak memory 204724 kb
Host smart-bfc61bc6-c07a-4b62-b56d-c8b5332520c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792787626 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.792787626
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.515967696
Short name T32
Test name
Test status
Simulation time 18606403 ps
CPU time 0.72 seconds
Started Apr 02 12:31:17 PM PDT 24
Finished Apr 02 12:31:17 PM PDT 24
Peak memory 204684 kb
Host smart-73ef79e7-7162-497e-a5e5-f01855b0030c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515967696 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.515967696
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.3016984901
Short name T176
Test name
Test status
Simulation time 2027980889 ps
CPU time 10.1 seconds
Started Apr 02 12:31:12 PM PDT 24
Finished Apr 02 12:31:23 PM PDT 24
Peak memory 214504 kb
Host smart-0d18ff14-067b-492f-95ec-1fdc62bb9b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016984901 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.3016984901
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.1594478829
Short name T178
Test name
Test status
Simulation time 3486829358 ps
CPU time 5.24 seconds
Started Apr 02 12:31:18 PM PDT 24
Finished Apr 02 12:31:24 PM PDT 24
Peak memory 205104 kb
Host smart-f75618ec-f92d-49d6-a417-362f2a17abef
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1594478829 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.1594478829
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.756629035
Short name T208
Test name
Test status
Simulation time 42210549 ps
CPU time 0.76 seconds
Started Apr 02 12:31:15 PM PDT 24
Finished Apr 02 12:31:16 PM PDT 24
Peak memory 204576 kb
Host smart-64d47938-de34-4b34-9324-c6a3ba6ab758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756629035 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.756629035
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.506399733
Short name T207
Test name
Test status
Simulation time 3909495402 ps
CPU time 15.09 seconds
Started Apr 02 12:31:25 PM PDT 24
Finished Apr 02 12:31:41 PM PDT 24
Peak memory 205048 kb
Host smart-d32ea0bd-15c3-4747-8717-b7646da687db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506399733 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.506399733
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.4125375493
Short name T29
Test name
Test status
Simulation time 152028277 ps
CPU time 1.45 seconds
Started Apr 02 12:31:15 PM PDT 24
Finished Apr 02 12:31:17 PM PDT 24
Peak memory 228812 kb
Host smart-708c8dee-b374-40bc-9b39-0f44f13567f7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125375493 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.4125375493
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.2496162580
Short name T69
Test name
Test status
Simulation time 21079375 ps
CPU time 0.69 seconds
Started Apr 02 12:31:33 PM PDT 24
Finished Apr 02 12:31:35 PM PDT 24
Peak memory 204736 kb
Host smart-a4a1a45c-b13e-4eeb-8091-cd4a0de60dbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496162580 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.2496162580
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.258877744
Short name T161
Test name
Test status
Simulation time 43193692 ps
CPU time 0.69 seconds
Started Apr 02 12:31:27 PM PDT 24
Finished Apr 02 12:31:29 PM PDT 24
Peak memory 204704 kb
Host smart-12a35020-245f-4233-805a-85f0c704e551
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258877744 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.258877744
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.3646254048
Short name T61
Test name
Test status
Simulation time 81815948 ps
CPU time 0.68 seconds
Started Apr 02 12:31:33 PM PDT 24
Finished Apr 02 12:31:35 PM PDT 24
Peak memory 204736 kb
Host smart-188a959e-374a-4c3c-a90a-4111764d335c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646254048 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.3646254048
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.3128483858
Short name T164
Test name
Test status
Simulation time 22618787 ps
CPU time 0.67 seconds
Started Apr 02 12:31:33 PM PDT 24
Finished Apr 02 12:31:35 PM PDT 24
Peak memory 204708 kb
Host smart-fa5c6678-2aa4-46d1-9a67-0a900fec9f6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128483858 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.3128483858
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.513360240
Short name T146
Test name
Test status
Simulation time 54310799 ps
CPU time 0.69 seconds
Started Apr 02 12:31:29 PM PDT 24
Finished Apr 02 12:31:30 PM PDT 24
Peak memory 204536 kb
Host smart-431390f4-61b0-4a13-8a12-1f268adafe00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513360240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.513360240
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.1838986471
Short name T186
Test name
Test status
Simulation time 43187545 ps
CPU time 0.71 seconds
Started Apr 02 12:31:28 PM PDT 24
Finished Apr 02 12:31:29 PM PDT 24
Peak memory 204536 kb
Host smart-fdca6880-6ecb-4702-99b0-85cb7442c976
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838986471 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.1838986471
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.1651042988
Short name T67
Test name
Test status
Simulation time 63911986 ps
CPU time 0.69 seconds
Started Apr 02 12:31:28 PM PDT 24
Finished Apr 02 12:31:30 PM PDT 24
Peak memory 204248 kb
Host smart-0d4e1f6e-ce87-4457-a4b0-bede2b808b3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651042988 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.1651042988
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.590162220
Short name T110
Test name
Test status
Simulation time 41940249 ps
CPU time 0.66 seconds
Started Apr 02 12:31:28 PM PDT 24
Finished Apr 02 12:31:29 PM PDT 24
Peak memory 204532 kb
Host smart-ccb817ef-0cf0-414f-acdf-e5dea5b97928
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590162220 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.590162220
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.1133044842
Short name T119
Test name
Test status
Simulation time 35317617 ps
CPU time 0.75 seconds
Started Apr 02 12:31:27 PM PDT 24
Finished Apr 02 12:31:29 PM PDT 24
Peak memory 204656 kb
Host smart-78170d84-53d8-424f-b0ea-fd4cd929cc12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133044842 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.1133044842
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.2732168117
Short name T140
Test name
Test status
Simulation time 24584328 ps
CPU time 0.71 seconds
Started Apr 02 12:31:11 PM PDT 24
Finished Apr 02 12:31:12 PM PDT 24
Peak memory 204684 kb
Host smart-4362c27c-863d-49c3-97d2-fe941cb477ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732168117 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.2732168117
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.3773807766
Short name T209
Test name
Test status
Simulation time 2882948936 ps
CPU time 5.25 seconds
Started Apr 02 12:31:14 PM PDT 24
Finished Apr 02 12:31:19 PM PDT 24
Peak memory 205112 kb
Host smart-a9e96ac2-2913-42fe-ad3d-d5496aace8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773807766 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.3773807766
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.2523819364
Short name T26
Test name
Test status
Simulation time 2817640081 ps
CPU time 4.41 seconds
Started Apr 02 12:31:16 PM PDT 24
Finished Apr 02 12:31:21 PM PDT 24
Peak memory 205188 kb
Host smart-81446d7e-dccf-42cc-a583-657257a7c463
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2523819364 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.2523819364
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.3629375364
Short name T188
Test name
Test status
Simulation time 147868560 ps
CPU time 1.16 seconds
Started Apr 02 12:31:15 PM PDT 24
Finished Apr 02 12:31:16 PM PDT 24
Peak memory 204592 kb
Host smart-d8380799-698a-4481-9db6-d35d689a5c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629375364 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.3629375364
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.1981858373
Short name T185
Test name
Test status
Simulation time 7579642762 ps
CPU time 7.78 seconds
Started Apr 02 12:31:10 PM PDT 24
Finished Apr 02 12:31:18 PM PDT 24
Peak memory 213280 kb
Host smart-f0b934ae-c7a9-46dd-8939-be56f749afe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981858373 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.1981858373
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.103513118
Short name T30
Test name
Test status
Simulation time 102988714 ps
CPU time 0.99 seconds
Started Apr 02 12:31:23 PM PDT 24
Finished Apr 02 12:31:24 PM PDT 24
Peak memory 229320 kb
Host smart-5049b84d-2f85-4e18-9c16-d64a8c6d5434
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103513118 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.103513118
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.4112269655
Short name T154
Test name
Test status
Simulation time 45928776 ps
CPU time 0.71 seconds
Started Apr 02 12:32:55 PM PDT 24
Finished Apr 02 12:32:56 PM PDT 24
Peak memory 204596 kb
Host smart-322ce1d4-4620-4962-9f09-44d4c49670ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112269655 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.4112269655
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.4201554891
Short name T66
Test name
Test status
Simulation time 22013195 ps
CPU time 0.68 seconds
Started Apr 02 12:32:57 PM PDT 24
Finished Apr 02 12:32:58 PM PDT 24
Peak memory 204600 kb
Host smart-a928e678-d6d6-414b-9f16-46f3f8240592
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201554891 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.4201554891
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.2032176118
Short name T70
Test name
Test status
Simulation time 28161678 ps
CPU time 0.69 seconds
Started Apr 02 12:31:37 PM PDT 24
Finished Apr 02 12:31:38 PM PDT 24
Peak memory 204700 kb
Host smart-6fa0751f-d209-4c19-a420-32c1aa66cd12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032176118 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.2032176118
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.2224373136
Short name T142
Test name
Test status
Simulation time 20349956 ps
CPU time 0.71 seconds
Started Apr 02 12:32:56 PM PDT 24
Finished Apr 02 12:32:57 PM PDT 24
Peak memory 204604 kb
Host smart-820660bf-7c73-41cb-83cf-34af616a0e27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224373136 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.2224373136
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.803174955
Short name T150
Test name
Test status
Simulation time 16792018 ps
CPU time 0.69 seconds
Started Apr 02 12:31:31 PM PDT 24
Finished Apr 02 12:31:32 PM PDT 24
Peak memory 204724 kb
Host smart-d3d02c58-2a61-466b-9bd7-42f3ba1b8e05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803174955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.803174955
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.1146178118
Short name T71
Test name
Test status
Simulation time 46856645 ps
CPU time 0.68 seconds
Started Apr 02 12:31:31 PM PDT 24
Finished Apr 02 12:31:32 PM PDT 24
Peak memory 204700 kb
Host smart-d0d2d5d6-4f57-4620-b796-f3cc6b719836
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146178118 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.1146178118
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.1022538338
Short name T160
Test name
Test status
Simulation time 20401724 ps
CPU time 0.71 seconds
Started Apr 02 12:32:57 PM PDT 24
Finished Apr 02 12:32:58 PM PDT 24
Peak memory 204604 kb
Host smart-32eac958-baa1-4310-85b0-ec0cba7527b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022538338 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.1022538338
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.1682029447
Short name T45
Test name
Test status
Simulation time 37383835 ps
CPU time 0.69 seconds
Started Apr 02 12:32:56 PM PDT 24
Finished Apr 02 12:32:57 PM PDT 24
Peak memory 204604 kb
Host smart-7f2f707e-013f-477a-8ec6-1110790c81fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682029447 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.1682029447
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.539231079
Short name T153
Test name
Test status
Simulation time 55944847 ps
CPU time 0.66 seconds
Started Apr 02 12:32:56 PM PDT 24
Finished Apr 02 12:32:57 PM PDT 24
Peak memory 204656 kb
Host smart-49523c03-05c8-4c3b-a326-71d608c252e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539231079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.539231079
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.1335721648
Short name T141
Test name
Test status
Simulation time 27923050 ps
CPU time 0.71 seconds
Started Apr 02 12:32:59 PM PDT 24
Finished Apr 02 12:33:00 PM PDT 24
Peak memory 204664 kb
Host smart-582f444b-f382-41bb-9d93-3140c8b20f3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335721648 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.1335721648
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.2895668688
Short name T147
Test name
Test status
Simulation time 49191957 ps
CPU time 0.71 seconds
Started Apr 02 12:31:21 PM PDT 24
Finished Apr 02 12:31:21 PM PDT 24
Peak memory 204740 kb
Host smart-fe4982df-1248-40ed-95ea-82353b98c42a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895668688 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.2895668688
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.339179393
Short name T202
Test name
Test status
Simulation time 4618322222 ps
CPU time 16.9 seconds
Started Apr 02 12:31:19 PM PDT 24
Finished Apr 02 12:31:36 PM PDT 24
Peak memory 213404 kb
Host smart-84728a22-7e25-4e2a-9816-8a220bc7801e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339179393 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.339179393
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.1568694062
Short name T197
Test name
Test status
Simulation time 2122678126 ps
CPU time 4.86 seconds
Started Apr 02 12:31:21 PM PDT 24
Finished Apr 02 12:31:26 PM PDT 24
Peak memory 205060 kb
Host smart-6ffda41c-500c-464d-888d-86f8254897f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568694062 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.1568694062
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.2964990180
Short name T170
Test name
Test status
Simulation time 2343675471 ps
CPU time 6.93 seconds
Started Apr 02 12:31:22 PM PDT 24
Finished Apr 02 12:31:30 PM PDT 24
Peak memory 204976 kb
Host smart-8c09c4de-476d-4c0d-914f-a2d97b32d16a
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2964990180 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t
l_access.2964990180
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.3829328260
Short name T221
Test name
Test status
Simulation time 3605528653 ps
CPU time 5.14 seconds
Started Apr 02 12:31:21 PM PDT 24
Finished Apr 02 12:31:26 PM PDT 24
Peak memory 205072 kb
Host smart-39a8009a-7c77-420f-817d-8a657fcff0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829328260 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.3829328260
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.1523417145
Short name T143
Test name
Test status
Simulation time 35264305 ps
CPU time 0.72 seconds
Started Apr 02 12:31:20 PM PDT 24
Finished Apr 02 12:31:21 PM PDT 24
Peak memory 204704 kb
Host smart-537adac8-83b8-438e-945f-50899875fdf8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523417145 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.1523417145
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.295176542
Short name T172
Test name
Test status
Simulation time 3575963491 ps
CPU time 3.83 seconds
Started Apr 02 12:31:16 PM PDT 24
Finished Apr 02 12:31:20 PM PDT 24
Peak memory 205100 kb
Host smart-a17dd4c4-be54-48e7-b362-ef1bb23f9a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295176542 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.295176542
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.3029664920
Short name T180
Test name
Test status
Simulation time 4075989929 ps
CPU time 3.77 seconds
Started Apr 02 12:31:25 PM PDT 24
Finished Apr 02 12:31:29 PM PDT 24
Peak memory 205032 kb
Host smart-20465818-ddd9-4d1b-a5dd-b68d627078c4
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3029664920 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t
l_access.3029664920
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.2828509263
Short name T46
Test name
Test status
Simulation time 705076664 ps
CPU time 1.44 seconds
Started Apr 02 12:31:22 PM PDT 24
Finished Apr 02 12:31:29 PM PDT 24
Peak memory 205096 kb
Host smart-eebc142d-a5b8-481a-a9f5-bbcf5b6e3a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828509263 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.2828509263
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.316147170
Short name T217
Test name
Test status
Simulation time 47565521 ps
CPU time 0.7 seconds
Started Apr 02 12:31:25 PM PDT 24
Finished Apr 02 12:31:26 PM PDT 24
Peak memory 204640 kb
Host smart-3987f295-82fa-4976-9d41-b422e726ac8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316147170 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.316147170
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.3810807982
Short name T210
Test name
Test status
Simulation time 33624094330 ps
CPU time 129.43 seconds
Started Apr 02 12:31:19 PM PDT 24
Finished Apr 02 12:33:29 PM PDT 24
Peak memory 213312 kb
Host smart-158215d0-3fd7-411e-9a38-6cc081e1a365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810807982 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.3810807982
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.2187827609
Short name T222
Test name
Test status
Simulation time 5063323388 ps
CPU time 17.62 seconds
Started Apr 02 12:31:22 PM PDT 24
Finished Apr 02 12:31:40 PM PDT 24
Peak memory 214804 kb
Host smart-b2c18577-a6b5-4c18-8b62-e86b6c81279b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187827609 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.2187827609
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.2792488257
Short name T195
Test name
Test status
Simulation time 1395091362 ps
CPU time 6.38 seconds
Started Apr 02 12:31:28 PM PDT 24
Finished Apr 02 12:31:35 PM PDT 24
Peak memory 204976 kb
Host smart-b316d020-6b58-440b-b8e8-17bb4af5253f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2792488257 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.2792488257
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.800913921
Short name T166
Test name
Test status
Simulation time 798563140 ps
CPU time 4.27 seconds
Started Apr 02 12:31:09 PM PDT 24
Finished Apr 02 12:31:14 PM PDT 24
Peak memory 204956 kb
Host smart-6c918015-a440-420b-a1b3-69abc1390117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800913921 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.800913921
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_stress_all.2071476646
Short name T14
Test name
Test status
Simulation time 5718716502 ps
CPU time 13.88 seconds
Started Apr 02 12:31:27 PM PDT 24
Finished Apr 02 12:31:42 PM PDT 24
Peak memory 205104 kb
Host smart-7a86de3e-8f61-424d-8cc4-39c384c100bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071476646 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.2071476646
Directory /workspace/7.rv_dm_stress_all/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.578977151
Short name T157
Test name
Test status
Simulation time 20757758 ps
CPU time 0.72 seconds
Started Apr 02 12:31:24 PM PDT 24
Finished Apr 02 12:31:25 PM PDT 24
Peak memory 204712 kb
Host smart-1fe9d9c9-54c7-4e88-893a-1170eb6d7622
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578977151 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.578977151
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.3434751429
Short name T220
Test name
Test status
Simulation time 4027896195 ps
CPU time 13.17 seconds
Started Apr 02 12:31:22 PM PDT 24
Finished Apr 02 12:31:36 PM PDT 24
Peak memory 213388 kb
Host smart-d8451feb-d597-4027-895f-42421bc9c8cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434751429 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.3434751429
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.2326502769
Short name T181
Test name
Test status
Simulation time 2745466144 ps
CPU time 12.09 seconds
Started Apr 02 12:31:30 PM PDT 24
Finished Apr 02 12:31:42 PM PDT 24
Peak memory 213236 kb
Host smart-f55adf96-bcd3-424c-ba78-5a2ce2d504bc
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2326502769 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t
l_access.2326502769
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.178606723
Short name T114
Test name
Test status
Simulation time 1659048355 ps
CPU time 2.08 seconds
Started Apr 02 12:31:21 PM PDT 24
Finished Apr 02 12:31:23 PM PDT 24
Peak memory 205000 kb
Host smart-a727ad5e-b49a-47c4-9622-2cf12fcb33cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178606723 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.178606723
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.863798369
Short name T159
Test name
Test status
Simulation time 36244620 ps
CPU time 0.68 seconds
Started Apr 02 12:31:25 PM PDT 24
Finished Apr 02 12:31:26 PM PDT 24
Peak memory 204680 kb
Host smart-f87bd4a2-71ea-4b94-bb12-fedb1a51017f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863798369 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.863798369
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.1550525993
Short name T190
Test name
Test status
Simulation time 7375616256 ps
CPU time 12.71 seconds
Started Apr 02 12:31:27 PM PDT 24
Finished Apr 02 12:31:41 PM PDT 24
Peak memory 205140 kb
Host smart-501ce1a0-937c-432f-a110-6c6e07e013ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550525993 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.1550525993
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.1775400782
Short name T229
Test name
Test status
Simulation time 10135420690 ps
CPU time 19.88 seconds
Started Apr 02 12:31:29 PM PDT 24
Finished Apr 02 12:31:49 PM PDT 24
Peak memory 213312 kb
Host smart-9b6d33e1-ccad-4679-bd3d-b1d1aada9b06
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1775400782 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t
l_access.1775400782
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.2147684745
Short name T28
Test name
Test status
Simulation time 2248652889 ps
CPU time 8.51 seconds
Started Apr 02 12:31:25 PM PDT 24
Finished Apr 02 12:31:34 PM PDT 24
Peak memory 205068 kb
Host smart-67e1c71f-0b9d-4c92-80dd-02b4d2eeb333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147684745 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.2147684745
Directory /workspace/9.rv_dm_sba_tl_access/latest
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