Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
81.52 94.44 80.32 87.69 79.49 83.66 98.10 46.93


Total test records in report: 375
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html
T275 /workspace/coverage/cover_reg_top/37.rv_dm_tap_fsm_rand_reset.3801911488 Apr 04 03:36:59 PM PDT 24 Apr 04 03:37:15 PM PDT 24 13005172222 ps
T276 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.1694654660 Apr 04 03:36:23 PM PDT 24 Apr 04 03:36:29 PM PDT 24 182652124 ps
T277 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1601383520 Apr 04 03:35:57 PM PDT 24 Apr 04 03:36:00 PM PDT 24 1337096384 ps
T278 /workspace/coverage/cover_reg_top/24.rv_dm_tap_fsm_rand_reset.1232376422 Apr 04 03:36:58 PM PDT 24 Apr 04 03:37:19 PM PDT 24 5685999931 ps
T279 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.3288780028 Apr 04 03:36:23 PM PDT 24 Apr 04 03:36:27 PM PDT 24 208491087 ps
T280 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.1784209485 Apr 04 03:36:54 PM PDT 24 Apr 04 03:36:56 PM PDT 24 94419337 ps
T124 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.3756735258 Apr 04 03:36:56 PM PDT 24 Apr 04 03:37:05 PM PDT 24 415022613 ps
T114 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.278313108 Apr 04 03:36:53 PM PDT 24 Apr 04 03:36:55 PM PDT 24 44601229 ps
T281 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3410348046 Apr 04 03:36:23 PM PDT 24 Apr 04 03:36:24 PM PDT 24 37385301 ps
T282 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.4139086935 Apr 04 03:36:56 PM PDT 24 Apr 04 03:37:01 PM PDT 24 304013464 ps
T98 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.523310994 Apr 04 03:36:05 PM PDT 24 Apr 04 03:36:07 PM PDT 24 1207656711 ps
T135 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.1743704706 Apr 04 03:36:21 PM PDT 24 Apr 04 03:36:32 PM PDT 24 873675097 ps
T116 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.582853802 Apr 04 03:36:57 PM PDT 24 Apr 04 03:37:01 PM PDT 24 45398763 ps
T283 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2655529450 Apr 04 03:36:54 PM PDT 24 Apr 04 03:36:55 PM PDT 24 73873971 ps
T284 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.1615813432 Apr 04 03:35:59 PM PDT 24 Apr 04 03:36:04 PM PDT 24 78761812 ps
T285 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.664144319 Apr 04 03:36:42 PM PDT 24 Apr 04 03:36:52 PM PDT 24 225591574 ps
T286 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.897830213 Apr 04 03:36:13 PM PDT 24 Apr 04 03:36:18 PM PDT 24 1221641178 ps
T142 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.331786387 Apr 04 03:36:38 PM PDT 24 Apr 04 03:36:58 PM PDT 24 1776228873 ps
T287 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1213546910 Apr 04 03:36:40 PM PDT 24 Apr 04 03:36:43 PM PDT 24 87628115 ps
T106 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.147118663 Apr 04 03:36:57 PM PDT 24 Apr 04 03:36:59 PM PDT 24 353274106 ps
T288 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.726777444 Apr 04 03:36:12 PM PDT 24 Apr 04 03:36:14 PM PDT 24 24720903 ps
T289 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3372081048 Apr 04 03:36:25 PM PDT 24 Apr 04 03:36:32 PM PDT 24 3562716036 ps
T290 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3589686526 Apr 04 03:36:09 PM PDT 24 Apr 04 03:36:12 PM PDT 24 122770320 ps
T291 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.3335324861 Apr 04 03:36:55 PM PDT 24 Apr 04 03:37:01 PM PDT 24 1371436740 ps
T292 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.807297215 Apr 04 03:36:09 PM PDT 24 Apr 04 03:36:11 PM PDT 24 134802227 ps
T293 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1877038453 Apr 04 03:36:08 PM PDT 24 Apr 04 03:36:49 PM PDT 24 19748437696 ps
T294 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.3925090157 Apr 04 03:36:10 PM PDT 24 Apr 04 03:37:03 PM PDT 24 13758972126 ps
T295 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.427003829 Apr 04 03:36:00 PM PDT 24 Apr 04 03:36:01 PM PDT 24 46817056 ps
T296 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3096918756 Apr 04 03:36:55 PM PDT 24 Apr 04 03:36:57 PM PDT 24 368157504 ps
T117 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.787376146 Apr 04 03:36:13 PM PDT 24 Apr 04 03:36:15 PM PDT 24 25660529 ps
T297 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.856840122 Apr 04 03:36:57 PM PDT 24 Apr 04 03:37:05 PM PDT 24 146825588 ps
T118 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1227727061 Apr 04 03:36:27 PM PDT 24 Apr 04 03:36:29 PM PDT 24 107485698 ps
T298 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.1339156699 Apr 04 03:36:22 PM PDT 24 Apr 04 03:36:32 PM PDT 24 635763679 ps
T107 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.510215045 Apr 04 03:36:05 PM PDT 24 Apr 04 03:37:24 PM PDT 24 4431448421 ps
T299 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.2706339422 Apr 04 03:36:23 PM PDT 24 Apr 04 03:36:26 PM PDT 24 649389519 ps
T300 /workspace/coverage/cover_reg_top/18.rv_dm_tap_fsm_rand_reset.2523612030 Apr 04 03:36:55 PM PDT 24 Apr 04 03:37:17 PM PDT 24 5505887698 ps
T138 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1039881698 Apr 04 03:36:22 PM PDT 24 Apr 04 03:36:43 PM PDT 24 7173486164 ps
T301 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.580478280 Apr 04 03:36:56 PM PDT 24 Apr 04 03:37:00 PM PDT 24 601367714 ps
T136 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3316585004 Apr 04 03:36:20 PM PDT 24 Apr 04 03:36:37 PM PDT 24 679924168 ps
T302 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3034787201 Apr 04 03:36:05 PM PDT 24 Apr 04 03:36:06 PM PDT 24 37358919 ps
T119 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.2118028920 Apr 04 03:35:58 PM PDT 24 Apr 04 03:37:04 PM PDT 24 2214889882 ps
T303 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1154881343 Apr 04 03:36:10 PM PDT 24 Apr 04 03:36:12 PM PDT 24 160950262 ps
T304 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3463066200 Apr 04 03:36:55 PM PDT 24 Apr 04 03:37:01 PM PDT 24 1144243748 ps
T305 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.2848181524 Apr 04 03:36:29 PM PDT 24 Apr 04 03:36:30 PM PDT 24 17754328 ps
T306 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.2746942001 Apr 04 03:36:53 PM PDT 24 Apr 04 03:36:59 PM PDT 24 1268295194 ps
T307 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.1577593501 Apr 04 03:36:21 PM PDT 24 Apr 04 03:36:26 PM PDT 24 1239513425 ps
T308 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2167853432 Apr 04 03:36:13 PM PDT 24 Apr 04 03:36:15 PM PDT 24 51719175 ps
T309 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.1293388902 Apr 04 03:36:26 PM PDT 24 Apr 04 03:36:27 PM PDT 24 51032282 ps
T310 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1146146427 Apr 04 03:36:09 PM PDT 24 Apr 04 03:36:12 PM PDT 24 1261435349 ps
T311 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2421517699 Apr 04 03:36:07 PM PDT 24 Apr 04 03:36:08 PM PDT 24 456992668 ps
T312 /workspace/coverage/cover_reg_top/27.rv_dm_tap_fsm_rand_reset.1909177013 Apr 04 03:36:58 PM PDT 24 Apr 04 03:37:31 PM PDT 24 10817714391 ps
T313 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.3726554601 Apr 04 03:36:54 PM PDT 24 Apr 04 03:36:55 PM PDT 24 330902638 ps
T115 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3699643837 Apr 04 03:36:06 PM PDT 24 Apr 04 03:36:08 PM PDT 24 60730470 ps
T314 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.3077376392 Apr 04 03:36:08 PM PDT 24 Apr 04 03:36:46 PM PDT 24 20333122463 ps
T108 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.1594163454 Apr 04 03:36:23 PM PDT 24 Apr 04 03:36:30 PM PDT 24 285951319 ps
T140 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.2738438597 Apr 04 03:36:55 PM PDT 24 Apr 04 03:37:18 PM PDT 24 1234350823 ps
T315 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1093712565 Apr 04 03:36:56 PM PDT 24 Apr 04 03:36:58 PM PDT 24 47714064 ps
T316 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.825890916 Apr 04 03:36:12 PM PDT 24 Apr 04 03:36:14 PM PDT 24 115855914 ps
T109 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1036683051 Apr 04 03:36:55 PM PDT 24 Apr 04 03:37:04 PM PDT 24 139913370 ps
T110 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.1468347293 Apr 04 03:36:56 PM PDT 24 Apr 04 03:37:01 PM PDT 24 804785866 ps
T317 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.972162978 Apr 04 03:36:54 PM PDT 24 Apr 04 03:36:57 PM PDT 24 110896884 ps
T141 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.787022507 Apr 04 03:36:29 PM PDT 24 Apr 04 03:36:50 PM PDT 24 6424815672 ps
T143 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3877503106 Apr 04 03:35:59 PM PDT 24 Apr 04 03:36:15 PM PDT 24 495092175 ps
T318 /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2362269742 Apr 04 03:36:11 PM PDT 24 Apr 04 03:36:26 PM PDT 24 7839692302 ps
T319 /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.399493226 Apr 04 03:36:12 PM PDT 24 Apr 04 03:36:26 PM PDT 24 33763689203 ps
T320 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2429533867 Apr 04 03:36:55 PM PDT 24 Apr 04 03:36:57 PM PDT 24 81680530 ps
T321 /workspace/coverage/cover_reg_top/22.rv_dm_tap_fsm_rand_reset.3813058071 Apr 04 03:36:58 PM PDT 24 Apr 04 03:37:31 PM PDT 24 9888899673 ps
T322 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.4120356506 Apr 04 03:36:10 PM PDT 24 Apr 04 03:36:15 PM PDT 24 2686454734 ps
T99 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2442441892 Apr 04 03:36:10 PM PDT 24 Apr 04 03:36:13 PM PDT 24 821112057 ps
T323 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.373156245 Apr 04 03:36:14 PM PDT 24 Apr 04 03:36:22 PM PDT 24 1135994680 ps
T324 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3998663254 Apr 04 03:36:40 PM PDT 24 Apr 04 03:36:43 PM PDT 24 304624637 ps
T325 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.799867843 Apr 04 03:36:53 PM PDT 24 Apr 04 03:36:58 PM PDT 24 4095227786 ps
T326 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.4271006067 Apr 04 03:36:11 PM PDT 24 Apr 04 03:36:16 PM PDT 24 826939176 ps
T327 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.40792190 Apr 04 03:36:10 PM PDT 24 Apr 04 03:36:14 PM PDT 24 417447821 ps
T328 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3098826315 Apr 04 03:36:56 PM PDT 24 Apr 04 03:36:59 PM PDT 24 143183314 ps
T329 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.3239312138 Apr 04 03:35:59 PM PDT 24 Apr 04 03:36:00 PM PDT 24 27847634 ps
T330 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.1870714978 Apr 04 03:36:54 PM PDT 24 Apr 04 03:36:58 PM PDT 24 696751296 ps
T331 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.359164885 Apr 04 03:36:22 PM PDT 24 Apr 04 03:36:28 PM PDT 24 3337687242 ps
T332 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.1758639641 Apr 04 03:36:14 PM PDT 24 Apr 04 03:36:16 PM PDT 24 704176420 ps
T333 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.450640645 Apr 04 03:36:54 PM PDT 24 Apr 04 03:36:55 PM PDT 24 138745793 ps
T334 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1420325888 Apr 04 03:36:12 PM PDT 24 Apr 04 03:36:14 PM PDT 24 221468965 ps
T335 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.799502645 Apr 04 03:36:13 PM PDT 24 Apr 04 03:36:15 PM PDT 24 55738357 ps
T100 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2960944362 Apr 04 03:36:15 PM PDT 24 Apr 04 03:36:17 PM PDT 24 639154032 ps
T336 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.1618440352 Apr 04 03:36:54 PM PDT 24 Apr 04 03:36:56 PM PDT 24 358957219 ps
T337 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2476475486 Apr 04 03:36:14 PM PDT 24 Apr 04 03:36:43 PM PDT 24 6299629708 ps
T338 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.2318523731 Apr 04 03:36:39 PM PDT 24 Apr 04 03:36:41 PM PDT 24 356307938 ps
T339 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.1474999725 Apr 04 03:36:26 PM PDT 24 Apr 04 03:36:27 PM PDT 24 40988876 ps
T144 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1688560861 Apr 04 03:36:56 PM PDT 24 Apr 04 03:37:05 PM PDT 24 211690541 ps
T340 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.848541702 Apr 04 03:36:09 PM PDT 24 Apr 04 03:36:11 PM PDT 24 341875112 ps
T341 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.4072041723 Apr 04 03:36:14 PM PDT 24 Apr 04 03:36:41 PM PDT 24 10034737547 ps
T342 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.2397828816 Apr 04 03:36:07 PM PDT 24 Apr 04 03:36:11 PM PDT 24 69548225 ps
T343 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.2739344857 Apr 04 03:36:25 PM PDT 24 Apr 04 03:36:27 PM PDT 24 229126329 ps
T344 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1997902900 Apr 04 03:36:26 PM PDT 24 Apr 04 03:36:27 PM PDT 24 126228449 ps
T345 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.1982666658 Apr 04 03:36:57 PM PDT 24 Apr 04 03:37:13 PM PDT 24 1601555858 ps
T346 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.478975438 Apr 04 03:36:54 PM PDT 24 Apr 04 03:36:57 PM PDT 24 115050415 ps
T347 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.373077276 Apr 04 03:36:06 PM PDT 24 Apr 04 03:36:08 PM PDT 24 67871068 ps
T348 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.3454098085 Apr 04 03:36:07 PM PDT 24 Apr 04 03:36:09 PM PDT 24 876417238 ps
T349 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.3673335460 Apr 04 03:36:13 PM PDT 24 Apr 04 03:36:14 PM PDT 24 16365885 ps
T350 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3287467212 Apr 04 03:36:39 PM PDT 24 Apr 04 03:36:42 PM PDT 24 1222004675 ps
T351 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.3571354045 Apr 04 03:36:20 PM PDT 24 Apr 04 03:36:25 PM PDT 24 518270068 ps
T352 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.4126638444 Apr 04 03:36:13 PM PDT 24 Apr 04 03:37:22 PM PDT 24 4884838305 ps
T353 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.42798888 Apr 04 03:36:07 PM PDT 24 Apr 04 03:36:07 PM PDT 24 15884998 ps
T354 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.2260074304 Apr 04 03:36:24 PM PDT 24 Apr 04 03:36:28 PM PDT 24 97590153 ps
T355 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.286954470 Apr 04 03:35:58 PM PDT 24 Apr 04 03:36:23 PM PDT 24 12538383173 ps
T356 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3206567280 Apr 04 03:36:13 PM PDT 24 Apr 04 03:36:30 PM PDT 24 800560751 ps
T357 /workspace/coverage/cover_reg_top/17.rv_dm_tap_fsm_rand_reset.1428006934 Apr 04 03:36:56 PM PDT 24 Apr 04 03:37:09 PM PDT 24 11787231426 ps
T358 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1948841120 Apr 04 03:36:56 PM PDT 24 Apr 04 03:36:58 PM PDT 24 814680361 ps
T359 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2975377914 Apr 04 03:36:55 PM PDT 24 Apr 04 03:37:15 PM PDT 24 3946445896 ps
T360 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.351699138 Apr 04 03:36:13 PM PDT 24 Apr 04 03:36:26 PM PDT 24 3469665464 ps
T361 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.1689886746 Apr 04 03:36:56 PM PDT 24 Apr 04 03:37:01 PM PDT 24 1256008961 ps
T362 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.1563416836 Apr 04 03:36:07 PM PDT 24 Apr 04 03:36:08 PM PDT 24 48771877 ps
T363 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3501043915 Apr 04 03:36:25 PM PDT 24 Apr 04 03:36:26 PM PDT 24 167684030 ps
T364 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3830414261 Apr 04 03:36:10 PM PDT 24 Apr 04 03:36:12 PM PDT 24 47524851 ps
T101 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.1223545899 Apr 04 03:36:14 PM PDT 24 Apr 04 03:36:16 PM PDT 24 203773708 ps
T365 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.490794045 Apr 04 03:36:23 PM PDT 24 Apr 04 03:36:27 PM PDT 24 851934082 ps
T366 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.3757230946 Apr 04 03:36:57 PM PDT 24 Apr 04 03:37:03 PM PDT 24 545297670 ps
T367 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.2780440205 Apr 04 03:36:38 PM PDT 24 Apr 04 03:36:45 PM PDT 24 144287235 ps
T368 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2616060840 Apr 04 03:36:24 PM PDT 24 Apr 04 03:36:26 PM PDT 24 65844565 ps
T369 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.1319038998 Apr 04 03:36:29 PM PDT 24 Apr 04 03:37:22 PM PDT 24 2921713152 ps
T370 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.721765256 Apr 04 03:36:11 PM PDT 24 Apr 04 03:36:12 PM PDT 24 108634735 ps
T371 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1680861562 Apr 04 03:36:22 PM PDT 24 Apr 04 03:36:24 PM PDT 24 86482302 ps
T372 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3603423775 Apr 04 03:36:55 PM PDT 24 Apr 04 03:37:13 PM PDT 24 1450815205 ps
T373 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3523101930 Apr 04 03:36:56 PM PDT 24 Apr 04 03:36:58 PM PDT 24 204488439 ps
T374 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.2666404731 Apr 04 03:36:38 PM PDT 24 Apr 04 03:36:42 PM PDT 24 1911404888 ps
T375 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.503532580 Apr 04 03:36:15 PM PDT 24 Apr 04 03:36:16 PM PDT 24 66012291 ps

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.59099601
Short name T32
Test name
Test status
Simulation time 2236529779 ps
CPU time 8.76 seconds
Started Apr 04 12:32:22 PM PDT 24
Finished Apr 04 12:32:31 PM PDT 24
Peak memory 205580 kb
Host smart-526c8e48-f8fd-454c-9b29-654a212d1804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59099601 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.59099601
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all.1593527331
Short name T5
Test name
Test status
Simulation time 3099707438 ps
CPU time 6.29 seconds
Started Apr 04 12:32:13 PM PDT 24
Finished Apr 04 12:32:19 PM PDT 24
Peak memory 205488 kb
Host smart-1eb67a9a-d6fd-49d8-a9ac-485fc48a6941
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593527331 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.1593527331
Directory /workspace/3.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.1455139176
Short name T42
Test name
Test status
Simulation time 4522095983 ps
CPU time 20 seconds
Started Apr 04 03:36:12 PM PDT 24
Finished Apr 04 03:36:32 PM PDT 24
Peak memory 213008 kb
Host smart-c33d107c-027c-43be-a4ed-d312e4f4f557
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455139176 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.1455139176
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/28.rv_dm_tap_fsm_rand_reset.244741520
Short name T131
Test name
Test status
Simulation time 17057093447 ps
CPU time 24.3 seconds
Started Apr 04 03:36:58 PM PDT 24
Finished Apr 04 03:37:24 PM PDT 24
Peak memory 220512 kb
Host smart-ae41c185-71ee-497a-9d1f-063a8238c8c1
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244741520 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 28.rv_dm_tap_fsm_rand_reset.244741520
Directory /workspace/28.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/16.rv_dm_stress_all.1401473732
Short name T37
Test name
Test status
Simulation time 959212977 ps
CPU time 3.77 seconds
Started Apr 04 12:32:45 PM PDT 24
Finished Apr 04 12:32:49 PM PDT 24
Peak memory 205268 kb
Host smart-d421c82b-d890-448e-ad7a-27cbc52db114
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401473732 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.1401473732
Directory /workspace/16.rv_dm_stress_all/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.1981151820
Short name T31
Test name
Test status
Simulation time 53840943 ps
CPU time 0.87 seconds
Started Apr 04 12:32:59 PM PDT 24
Finished Apr 04 12:33:00 PM PDT 24
Peak memory 205120 kb
Host smart-c7efd167-79f6-44f8-8341-b45ffc478eea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981151820 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.1981151820
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2181987366
Short name T44
Test name
Test status
Simulation time 310053413 ps
CPU time 4.83 seconds
Started Apr 04 03:36:22 PM PDT 24
Finished Apr 04 03:36:27 PM PDT 24
Peak memory 213096 kb
Host smart-89aea0eb-1110-4559-be7e-58d94ceb87b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181987366 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.2181987366
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.836550839
Short name T48
Test name
Test status
Simulation time 1989106922 ps
CPU time 4.26 seconds
Started Apr 04 12:32:13 PM PDT 24
Finished Apr 04 12:32:18 PM PDT 24
Peak memory 205360 kb
Host smart-f64ecea9-2162-464c-a3aa-4f4621bf9954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836550839 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.836550839
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.1568275368
Short name T46
Test name
Test status
Simulation time 2468708563 ps
CPU time 33.88 seconds
Started Apr 04 03:36:11 PM PDT 24
Finished Apr 04 03:36:45 PM PDT 24
Peak memory 204960 kb
Host smart-5e6de2ab-3d82-4e37-a0d6-373d3e089631
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568275368 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.1568275368
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/default/49.rv_dm_stress_all.4248630935
Short name T11
Test name
Test status
Simulation time 2771236650 ps
CPU time 9.12 seconds
Started Apr 04 12:33:14 PM PDT 24
Finished Apr 04 12:33:24 PM PDT 24
Peak memory 205364 kb
Host smart-36d8e74f-d621-40f3-8b34-d4fb14f678f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248630935 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.4248630935
Directory /workspace/49.rv_dm_stress_all/latest

Test location /workspace/coverage/default/45.rv_dm_stress_all.3564438109
Short name T24
Test name
Test status
Simulation time 2142454271 ps
CPU time 7.87 seconds
Started Apr 04 12:33:14 PM PDT 24
Finished Apr 04 12:33:23 PM PDT 24
Peak memory 205320 kb
Host smart-a66fd8d9-1af0-4139-a1a3-a8c052b89376
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564438109 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.3564438109
Directory /workspace/45.rv_dm_stress_all/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.458229122
Short name T199
Test name
Test status
Simulation time 11109308696 ps
CPU time 33.17 seconds
Started Apr 04 12:32:24 PM PDT 24
Finished Apr 04 12:32:57 PM PDT 24
Peak memory 213736 kb
Host smart-59abec33-7a05-4af0-9a66-47b37e443bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458229122 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.458229122
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/31.rv_dm_tap_fsm_rand_reset.2163665666
Short name T72
Test name
Test status
Simulation time 6459863947 ps
CPU time 13.41 seconds
Started Apr 04 03:36:56 PM PDT 24
Finished Apr 04 03:37:10 PM PDT 24
Peak memory 220692 kb
Host smart-cd07e862-6d14-43c6-a7c5-50f4d40a9258
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163665666 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 31.rv_dm_tap_fsm_rand_reset.2163665666
Directory /workspace/31.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.3732986211
Short name T26
Test name
Test status
Simulation time 61152454 ps
CPU time 1.04 seconds
Started Apr 04 12:33:26 PM PDT 24
Finished Apr 04 12:33:27 PM PDT 24
Peak memory 229228 kb
Host smart-0ad755f3-033d-48f1-bab2-39456d7d3a0c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732986211 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.3732986211
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.3081298560
Short name T49
Test name
Test status
Simulation time 29333518 ps
CPU time 0.83 seconds
Started Apr 04 12:33:27 PM PDT 24
Finished Apr 04 12:33:28 PM PDT 24
Peak memory 213184 kb
Host smart-fcf97fb1-660d-4bec-bbfe-fa446a90a894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081298560 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.3081298560
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.1665982450
Short name T67
Test name
Test status
Simulation time 223744663 ps
CPU time 1.39 seconds
Started Apr 04 12:28:53 PM PDT 24
Finished Apr 04 12:28:54 PM PDT 24
Peak memory 204876 kb
Host smart-d9b18806-fc4f-4a56-989a-3de92d4c9ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665982450 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.1665982450
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2811028936
Short name T104
Test name
Test status
Simulation time 241066626 ps
CPU time 6.4 seconds
Started Apr 04 03:36:12 PM PDT 24
Finished Apr 04 03:36:19 PM PDT 24
Peak memory 204856 kb
Host smart-2c4b3304-4bf1-406d-b32c-841e1ca7b9dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811028936 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_
csr_outstanding.2811028936
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.695984461
Short name T133
Test name
Test status
Simulation time 2746935887 ps
CPU time 21.62 seconds
Started Apr 04 03:36:21 PM PDT 24
Finished Apr 04 03:36:43 PM PDT 24
Peak memory 220436 kb
Host smart-6ccf212d-b5cd-4536-87f3-c1539b5da5f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695984461 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.695984461
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.1671500630
Short name T65
Test name
Test status
Simulation time 54660710 ps
CPU time 0.8 seconds
Started Apr 04 12:29:22 PM PDT 24
Finished Apr 04 12:29:23 PM PDT 24
Peak memory 204812 kb
Host smart-8b287631-2ef2-4a64-b49a-780809fbc09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671500630 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.1671500630
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.787022507
Short name T141
Test name
Test status
Simulation time 6424815672 ps
CPU time 20.22 seconds
Started Apr 04 03:36:29 PM PDT 24
Finished Apr 04 03:36:50 PM PDT 24
Peak memory 213508 kb
Host smart-08dc5176-d48f-42b7-af9d-2efe96540c39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787022507 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.787022507
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.506283022
Short name T68
Test name
Test status
Simulation time 87238942 ps
CPU time 0.88 seconds
Started Apr 04 12:28:33 PM PDT 24
Finished Apr 04 12:28:34 PM PDT 24
Peak memory 204980 kb
Host smart-7cb181db-521c-4b90-a640-bd8c421bebcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506283022 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.506283022
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.1776686435
Short name T74
Test name
Test status
Simulation time 346769091 ps
CPU time 0.88 seconds
Started Apr 04 03:35:57 PM PDT 24
Finished Apr 04 03:35:58 PM PDT 24
Peak memory 204488 kb
Host smart-13cdf0f9-4daa-4c59-aa26-0623a69f5597
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776686435 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.1776686435
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.1881587110
Short name T155
Test name
Test status
Simulation time 20246450 ps
CPU time 0.73 seconds
Started Apr 04 12:33:27 PM PDT 24
Finished Apr 04 12:33:28 PM PDT 24
Peak memory 204668 kb
Host smart-9c9acf80-694c-480d-be5e-a387b73ba2d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881587110 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.1881587110
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.1997709501
Short name T3
Test name
Test status
Simulation time 1820300558 ps
CPU time 6.16 seconds
Started Apr 04 12:28:57 PM PDT 24
Finished Apr 04 12:29:03 PM PDT 24
Peak memory 203736 kb
Host smart-4427866c-fb39-4d8c-8e17-913b3cea8fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997709501 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.1997709501
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.523310994
Short name T98
Test name
Test status
Simulation time 1207656711 ps
CPU time 1.64 seconds
Started Apr 04 03:36:05 PM PDT 24
Finished Apr 04 03:36:07 PM PDT 24
Peak memory 204776 kb
Host smart-82e39ca0-f3ea-4f6a-896c-bc7aa793474d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523310994 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr
_hw_reset.523310994
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.510215045
Short name T107
Test name
Test status
Simulation time 4431448421 ps
CPU time 78.96 seconds
Started Apr 04 03:36:05 PM PDT 24
Finished Apr 04 03:37:24 PM PDT 24
Peak memory 204976 kb
Host smart-34478050-12c2-4f73-abfe-af588948efd0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510215045 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.rv_dm_csr_aliasing.510215045
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3051723088
Short name T139
Test name
Test status
Simulation time 1045924220 ps
CPU time 15.55 seconds
Started Apr 04 03:36:55 PM PDT 24
Finished Apr 04 03:37:12 PM PDT 24
Peak memory 213072 kb
Host smart-7bfebd80-80c5-47c8-a637-e65aad06d3b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051723088 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.3
051723088
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.3053156599
Short name T62
Test name
Test status
Simulation time 192095520 ps
CPU time 1.2 seconds
Started Apr 04 12:29:04 PM PDT 24
Finished Apr 04 12:29:05 PM PDT 24
Peak memory 203852 kb
Host smart-b31e9025-5839-43e9-920e-5e23bdc344c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053156599 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.3053156599
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/14.rv_dm_stress_all.2279907492
Short name T14
Test name
Test status
Simulation time 7419922674 ps
CPU time 4.29 seconds
Started Apr 04 12:33:44 PM PDT 24
Finished Apr 04 12:33:49 PM PDT 24
Peak memory 205356 kb
Host smart-dcbef9da-ff5d-4905-9d27-d2652d9fc13f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279907492 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.2279907492
Directory /workspace/14.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.875609635
Short name T92
Test name
Test status
Simulation time 10313346953 ps
CPU time 75.57 seconds
Started Apr 04 03:36:04 PM PDT 24
Finished Apr 04 03:37:21 PM PDT 24
Peak memory 204964 kb
Host smart-0e7dba54-b84f-4d14-a0f1-4550960fdcb6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875609635 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.rv_dm_csr_aliasing.875609635
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.2118028920
Short name T119
Test name
Test status
Simulation time 2214889882 ps
CPU time 65.81 seconds
Started Apr 04 03:35:58 PM PDT 24
Finished Apr 04 03:37:04 PM PDT 24
Peak memory 204964 kb
Host smart-cab77668-c79a-4a23-8eed-4f4587074034
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118028920 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.2118028920
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.3077376392
Short name T314
Test name
Test status
Simulation time 20333122463 ps
CPU time 37.14 seconds
Started Apr 04 03:36:08 PM PDT 24
Finished Apr 04 03:36:46 PM PDT 24
Peak memory 213204 kb
Host smart-caf68be0-b17f-4645-ad95-b65c9184e703
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077376392 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.3077376392
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.373077276
Short name T347
Test name
Test status
Simulation time 67871068 ps
CPU time 1.64 seconds
Started Apr 04 03:36:06 PM PDT 24
Finished Apr 04 03:36:08 PM PDT 24
Peak memory 212996 kb
Host smart-8ce8713d-c462-4b8d-ac6c-ea8f2c7d49a2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373077276 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.373077276
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3589686526
Short name T290
Test name
Test status
Simulation time 122770320 ps
CPU time 1.99 seconds
Started Apr 04 03:36:09 PM PDT 24
Finished Apr 04 03:36:12 PM PDT 24
Peak memory 216656 kb
Host smart-bf443640-81a5-48f4-bab5-8226b1ef82d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589686526 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.3589686526
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2670034035
Short name T263
Test name
Test status
Simulation time 185453288 ps
CPU time 1.45 seconds
Started Apr 04 03:36:11 PM PDT 24
Finished Apr 04 03:36:13 PM PDT 24
Peak memory 218460 kb
Host smart-35f96a2d-a6ad-4d5d-a899-092a349cf52d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670034035 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.2670034035
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.709580238
Short name T240
Test name
Test status
Simulation time 14017314816 ps
CPU time 20.59 seconds
Started Apr 04 03:35:57 PM PDT 24
Finished Apr 04 03:36:18 PM PDT 24
Peak memory 204832 kb
Host smart-2b5b8b89-ee2e-4aa0-9ecf-09080f845bd4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709580238 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr
_aliasing.709580238
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.286954470
Short name T355
Test name
Test status
Simulation time 12538383173 ps
CPU time 25.27 seconds
Started Apr 04 03:35:58 PM PDT 24
Finished Apr 04 03:36:23 PM PDT 24
Peak memory 204836 kb
Host smart-24de3659-0e1c-49d9-8da9-bca90286aa95
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286954470 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr
_bit_bash.286954470
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.375594525
Short name T97
Test name
Test status
Simulation time 344016244 ps
CPU time 1.73 seconds
Started Apr 04 03:35:57 PM PDT 24
Finished Apr 04 03:35:59 PM PDT 24
Peak memory 204796 kb
Host smart-7f258b83-1381-4a73-8541-edd86ec2cf49
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375594525 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr
_hw_reset.375594525
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1601383520
Short name T277
Test name
Test status
Simulation time 1337096384 ps
CPU time 3.42 seconds
Started Apr 04 03:35:57 PM PDT 24
Finished Apr 04 03:36:00 PM PDT 24
Peak memory 204700 kb
Host smart-7a1e7b7c-e45e-4ce6-a108-f72ded25bf66
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601383520 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.1601383520
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.691954187
Short name T75
Test name
Test status
Simulation time 35339590 ps
CPU time 0.73 seconds
Started Apr 04 03:35:57 PM PDT 24
Finished Apr 04 03:35:57 PM PDT 24
Peak memory 204580 kb
Host smart-127c280c-8ac7-4dee-af70-cbb80ebd4710
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691954187 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr
_hw_reset.691954187
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1431195
Short name T262
Test name
Test status
Simulation time 122336456 ps
CPU time 0.96 seconds
Started Apr 04 03:36:00 PM PDT 24
Finished Apr 04 03:36:01 PM PDT 24
Peak memory 204460 kb
Host smart-53fcd450-8d92-4b11-87b9-bf4db3d82aaf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431195 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.1431195
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.427003829
Short name T295
Test name
Test status
Simulation time 46817056 ps
CPU time 0.68 seconds
Started Apr 04 03:36:00 PM PDT 24
Finished Apr 04 03:36:01 PM PDT 24
Peak memory 204520 kb
Host smart-8c0a55a4-19ef-49dd-b60e-2894ad24a667
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427003829 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_part
ial_access.427003829
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.3239312138
Short name T329
Test name
Test status
Simulation time 27847634 ps
CPU time 0.66 seconds
Started Apr 04 03:35:59 PM PDT 24
Finished Apr 04 03:36:00 PM PDT 24
Peak memory 204524 kb
Host smart-23c5b646-9313-4a48-83e4-7359677d351c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239312138 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.3239312138
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.4271006067
Short name T326
Test name
Test status
Simulation time 826939176 ps
CPU time 4.18 seconds
Started Apr 04 03:36:11 PM PDT 24
Finished Apr 04 03:36:16 PM PDT 24
Peak memory 204920 kb
Host smart-cac85acd-b701-4723-9eee-3c07553216f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271006067 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.4271006067
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.1615813432
Short name T284
Test name
Test status
Simulation time 78761812 ps
CPU time 4.93 seconds
Started Apr 04 03:35:59 PM PDT 24
Finished Apr 04 03:36:04 PM PDT 24
Peak memory 213080 kb
Host smart-2e547178-fa97-418e-9eec-1bbd556f264b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615813432 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.1615813432
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3877503106
Short name T143
Test name
Test status
Simulation time 495092175 ps
CPU time 15.82 seconds
Started Apr 04 03:35:59 PM PDT 24
Finished Apr 04 03:36:15 PM PDT 24
Peak memory 221156 kb
Host smart-81ecf112-ef03-40ef-ac2f-c7d6dddc7b18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877503106 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.3877503106
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.3555576726
Short name T94
Test name
Test status
Simulation time 742912539 ps
CPU time 28.14 seconds
Started Apr 04 03:36:10 PM PDT 24
Finished Apr 04 03:36:39 PM PDT 24
Peak memory 204884 kb
Host smart-c935cdd6-c49a-41ba-bb5c-65b1e7f36020
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555576726 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.3555576726
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2421517699
Short name T311
Test name
Test status
Simulation time 456992668 ps
CPU time 1.51 seconds
Started Apr 04 03:36:07 PM PDT 24
Finished Apr 04 03:36:08 PM PDT 24
Peak memory 213000 kb
Host smart-ce11a79b-a328-4327-80a0-7b32ce153d30
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421517699 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.2421517699
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2172758722
Short name T270
Test name
Test status
Simulation time 42731457 ps
CPU time 2.42 seconds
Started Apr 04 03:36:10 PM PDT 24
Finished Apr 04 03:36:13 PM PDT 24
Peak memory 217068 kb
Host smart-b6dc0bd3-3f53-49f1-a4ec-cabe2725c962
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172758722 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.2172758722
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.807297215
Short name T292
Test name
Test status
Simulation time 134802227 ps
CPU time 2.09 seconds
Started Apr 04 03:36:09 PM PDT 24
Finished Apr 04 03:36:11 PM PDT 24
Peak memory 213036 kb
Host smart-0f910827-edc0-4134-9c5b-dd7022ba3ec2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807297215 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.807297215
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.351699138
Short name T360
Test name
Test status
Simulation time 3469665464 ps
CPU time 13.01 seconds
Started Apr 04 03:36:13 PM PDT 24
Finished Apr 04 03:36:26 PM PDT 24
Peak memory 204860 kb
Host smart-090c0437-cfa2-4348-b063-07b8c9ac6038
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351699138 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr
_aliasing.351699138
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1877038453
Short name T293
Test name
Test status
Simulation time 19748437696 ps
CPU time 40.17 seconds
Started Apr 04 03:36:08 PM PDT 24
Finished Apr 04 03:36:49 PM PDT 24
Peak memory 204772 kb
Host smart-762c8a23-b61c-4ee8-89c2-b40d2d2279a9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877038453 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_bit_bash.1877038453
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.3560463846
Short name T243
Test name
Test status
Simulation time 362389976 ps
CPU time 2.27 seconds
Started Apr 04 03:36:10 PM PDT 24
Finished Apr 04 03:36:13 PM PDT 24
Peak memory 204644 kb
Host smart-8bf21318-d064-4982-8b78-4d1f32600952
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560463846 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.3
560463846
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.825890916
Short name T316
Test name
Test status
Simulation time 115855914 ps
CPU time 0.85 seconds
Started Apr 04 03:36:12 PM PDT 24
Finished Apr 04 03:36:14 PM PDT 24
Peak memory 204496 kb
Host smart-92dcb461-ce2e-4a65-938d-5c558aa5458c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825890916 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_aliasing.825890916
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.848541702
Short name T340
Test name
Test status
Simulation time 341875112 ps
CPU time 2.3 seconds
Started Apr 04 03:36:09 PM PDT 24
Finished Apr 04 03:36:11 PM PDT 24
Peak memory 204728 kb
Host smart-db13064f-aa50-47c1-a045-cfd016a6c100
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848541702 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_bit_bash.848541702
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.850899298
Short name T257
Test name
Test status
Simulation time 55439346 ps
CPU time 0.78 seconds
Started Apr 04 03:36:11 PM PDT 24
Finished Apr 04 03:36:13 PM PDT 24
Peak memory 204544 kb
Host smart-452e404c-7dab-4e0f-9dc0-8e63b36cc10e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850899298 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_hw_reset.850899298
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3034787201
Short name T302
Test name
Test status
Simulation time 37358919 ps
CPU time 0.75 seconds
Started Apr 04 03:36:05 PM PDT 24
Finished Apr 04 03:36:06 PM PDT 24
Peak memory 204496 kb
Host smart-f5afc1ae-7d3c-44c0-804c-a077c04dcbe6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034787201 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.3
034787201
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.42798888
Short name T353
Test name
Test status
Simulation time 15884998 ps
CPU time 0.66 seconds
Started Apr 04 03:36:07 PM PDT 24
Finished Apr 04 03:36:07 PM PDT 24
Peak memory 204472 kb
Host smart-48ed8f24-468f-4456-9b50-299cbb16982c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42798888 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_parti
al_access.42798888
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.1563416836
Short name T362
Test name
Test status
Simulation time 48771877 ps
CPU time 0.67 seconds
Started Apr 04 03:36:07 PM PDT 24
Finished Apr 04 03:36:08 PM PDT 24
Peak memory 204552 kb
Host smart-2faad22e-9ee0-47d1-90b4-70c23b5ed9ee
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563416836 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.1563416836
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.2397828816
Short name T342
Test name
Test status
Simulation time 69548225 ps
CPU time 4.08 seconds
Started Apr 04 03:36:07 PM PDT 24
Finished Apr 04 03:36:11 PM PDT 24
Peak memory 213112 kb
Host smart-7994a290-c86a-42de-9598-5cffabeb29f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397828816 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.2397828816
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.2152674336
Short name T41
Test name
Test status
Simulation time 836906340 ps
CPU time 9.08 seconds
Started Apr 04 03:36:09 PM PDT 24
Finished Apr 04 03:36:19 PM PDT 24
Peak memory 221236 kb
Host smart-30e8ee4c-b1e2-4232-b700-057cb92e0c6c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152674336 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.2152674336
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.2666404731
Short name T374
Test name
Test status
Simulation time 1911404888 ps
CPU time 3.83 seconds
Started Apr 04 03:36:38 PM PDT 24
Finished Apr 04 03:36:42 PM PDT 24
Peak memory 220980 kb
Host smart-cc98ccf1-7eca-468d-96d8-ba1eb2755a54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666404731 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.2666404731
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.1770530722
Short name T113
Test name
Test status
Simulation time 462575209 ps
CPU time 1.55 seconds
Started Apr 04 03:36:41 PM PDT 24
Finished Apr 04 03:36:43 PM PDT 24
Peak memory 213036 kb
Host smart-0a2d8cf2-a8e9-41a0-a42f-ef0d43ba2366
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770530722 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.1770530722
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3998663254
Short name T324
Test name
Test status
Simulation time 304624637 ps
CPU time 2.06 seconds
Started Apr 04 03:36:40 PM PDT 24
Finished Apr 04 03:36:43 PM PDT 24
Peak memory 204716 kb
Host smart-175c839b-6863-4dd7-b8df-d2c4f7e02c23
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998663254 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
3998663254
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.2821035014
Short name T254
Test name
Test status
Simulation time 80230039 ps
CPU time 0.86 seconds
Started Apr 04 03:36:39 PM PDT 24
Finished Apr 04 03:36:40 PM PDT 24
Peak memory 204488 kb
Host smart-1893a929-628c-4f8d-845d-22fdf6a98a01
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821035014 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
2821035014
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.2780440205
Short name T367
Test name
Test status
Simulation time 144287235 ps
CPU time 6.44 seconds
Started Apr 04 03:36:38 PM PDT 24
Finished Apr 04 03:36:45 PM PDT 24
Peak memory 204812 kb
Host smart-5e6d9202-cabf-4920-902c-55bdf4d3d2df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780440205 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.2780440205
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3287467212
Short name T350
Test name
Test status
Simulation time 1222004675 ps
CPU time 3 seconds
Started Apr 04 03:36:39 PM PDT 24
Finished Apr 04 03:36:42 PM PDT 24
Peak memory 215424 kb
Host smart-ecd378d9-6fe8-48de-a113-7cd11fe9a3c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287467212 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.3287467212
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.331786387
Short name T142
Test name
Test status
Simulation time 1776228873 ps
CPU time 19.29 seconds
Started Apr 04 03:36:38 PM PDT 24
Finished Apr 04 03:36:58 PM PDT 24
Peak memory 221240 kb
Host smart-ca360107-8c51-4dda-a920-f856b2ec635f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331786387 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.331786387
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3142518847
Short name T255
Test name
Test status
Simulation time 721856600 ps
CPU time 2.54 seconds
Started Apr 04 03:36:52 PM PDT 24
Finished Apr 04 03:36:55 PM PDT 24
Peak memory 216376 kb
Host smart-845de32e-6374-4784-8ab9-9f4343fdf1b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142518847 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.3142518847
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.1692885442
Short name T111
Test name
Test status
Simulation time 35778634 ps
CPU time 2.09 seconds
Started Apr 04 03:36:58 PM PDT 24
Finished Apr 04 03:37:02 PM PDT 24
Peak memory 218840 kb
Host smart-37d7361d-5bc0-44f4-95f9-a17cf8f7c23a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692885442 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.1692885442
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.2318523731
Short name T338
Test name
Test status
Simulation time 356307938 ps
CPU time 1.32 seconds
Started Apr 04 03:36:39 PM PDT 24
Finished Apr 04 03:36:41 PM PDT 24
Peak memory 204676 kb
Host smart-be894952-8cec-44e0-b016-a4da5036fdf3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318523731 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
2318523731
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.2946785916
Short name T245
Test name
Test status
Simulation time 70796973 ps
CPU time 0.77 seconds
Started Apr 04 03:36:41 PM PDT 24
Finished Apr 04 03:36:42 PM PDT 24
Peak memory 204532 kb
Host smart-216c4973-ba8f-4902-8017-de5f594da1eb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946785916 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.
2946785916
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.3756735258
Short name T124
Test name
Test status
Simulation time 415022613 ps
CPU time 8.07 seconds
Started Apr 04 03:36:56 PM PDT 24
Finished Apr 04 03:37:05 PM PDT 24
Peak memory 204804 kb
Host smart-0ba0e9a3-94b0-4d46-b0eb-5f72c65edda7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756735258 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same
_csr_outstanding.3756735258
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1213546910
Short name T287
Test name
Test status
Simulation time 87628115 ps
CPU time 2.54 seconds
Started Apr 04 03:36:40 PM PDT 24
Finished Apr 04 03:36:43 PM PDT 24
Peak memory 213152 kb
Host smart-d18de419-6ad1-49f3-a2a4-1584030645a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213546910 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.1213546910
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.208008796
Short name T134
Test name
Test status
Simulation time 188827892 ps
CPU time 8.32 seconds
Started Apr 04 03:36:38 PM PDT 24
Finished Apr 04 03:36:47 PM PDT 24
Peak memory 213060 kb
Host smart-4295c76f-882a-485d-825d-e6a0dc31eae8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208008796 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.208008796
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.799867843
Short name T325
Test name
Test status
Simulation time 4095227786 ps
CPU time 4.45 seconds
Started Apr 04 03:36:53 PM PDT 24
Finished Apr 04 03:36:58 PM PDT 24
Peak memory 219628 kb
Host smart-c18faf7e-057a-4c65-a1ca-0ada84ca4823
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799867843 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.799867843
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.136060670
Short name T264
Test name
Test status
Simulation time 53136629 ps
CPU time 1.51 seconds
Started Apr 04 03:36:53 PM PDT 24
Finished Apr 04 03:36:55 PM PDT 24
Peak memory 218148 kb
Host smart-8f59c501-82af-4cb4-9fd6-2cbdaa63c043
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136060670 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.136060670
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1676124863
Short name T239
Test name
Test status
Simulation time 720284451 ps
CPU time 1.39 seconds
Started Apr 04 03:36:55 PM PDT 24
Finished Apr 04 03:36:58 PM PDT 24
Peak memory 204656 kb
Host smart-c7b51acf-0241-4c49-aa57-22d54ccbd7e9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676124863 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
1676124863
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2429533867
Short name T320
Test name
Test status
Simulation time 81680530 ps
CPU time 0.69 seconds
Started Apr 04 03:36:55 PM PDT 24
Finished Apr 04 03:36:57 PM PDT 24
Peak memory 204492 kb
Host smart-b2be8ad2-a0c0-44df-92d1-3a40b69f6825
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429533867 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
2429533867
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.2728382426
Short name T121
Test name
Test status
Simulation time 148014000 ps
CPU time 3.48 seconds
Started Apr 04 03:36:53 PM PDT 24
Finished Apr 04 03:36:56 PM PDT 24
Peak memory 204816 kb
Host smart-389497fd-9793-4848-b0d4-6dafa141dc87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728382426 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.2728382426
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.1784209485
Short name T280
Test name
Test status
Simulation time 94419337 ps
CPU time 2.41 seconds
Started Apr 04 03:36:54 PM PDT 24
Finished Apr 04 03:36:56 PM PDT 24
Peak memory 215512 kb
Host smart-9d194bf2-1cd0-47c0-bf8c-66f4c485d343
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784209485 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.1784209485
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.747161209
Short name T43
Test name
Test status
Simulation time 3704704815 ps
CPU time 19.74 seconds
Started Apr 04 03:36:56 PM PDT 24
Finished Apr 04 03:37:17 PM PDT 24
Peak memory 213128 kb
Host smart-dea00662-4b07-49f5-a151-b2f645ddc8b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747161209 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.747161209
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.609697430
Short name T126
Test name
Test status
Simulation time 208714420 ps
CPU time 2.1 seconds
Started Apr 04 03:36:55 PM PDT 24
Finished Apr 04 03:36:59 PM PDT 24
Peak memory 215036 kb
Host smart-babb20c8-3a57-42f8-99cc-2e4ff6f4462e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609697430 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.609697430
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.147118663
Short name T106
Test name
Test status
Simulation time 353274106 ps
CPU time 2.19 seconds
Started Apr 04 03:36:57 PM PDT 24
Finished Apr 04 03:36:59 PM PDT 24
Peak memory 221232 kb
Host smart-e1ca12b9-cba2-46f7-b1ce-96436bb599dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147118663 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.147118663
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.3726554601
Short name T313
Test name
Test status
Simulation time 330902638 ps
CPU time 1.31 seconds
Started Apr 04 03:36:54 PM PDT 24
Finished Apr 04 03:36:55 PM PDT 24
Peak memory 204720 kb
Host smart-f84410b7-babd-4826-a4fb-4964638726d2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726554601 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
3726554601
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1093712565
Short name T315
Test name
Test status
Simulation time 47714064 ps
CPU time 0.75 seconds
Started Apr 04 03:36:56 PM PDT 24
Finished Apr 04 03:36:58 PM PDT 24
Peak memory 204508 kb
Host smart-e52a097a-177a-4e22-9489-a89adcb69b30
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093712565 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
1093712565
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.255095302
Short name T123
Test name
Test status
Simulation time 518376893 ps
CPU time 4.03 seconds
Started Apr 04 03:36:55 PM PDT 24
Finished Apr 04 03:37:01 PM PDT 24
Peak memory 204800 kb
Host smart-4bd9094e-1209-4768-823b-8110e9c797f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255095302 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same_
csr_outstanding.255095302
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tap_fsm_rand_reset.3849247939
Short name T71
Test name
Test status
Simulation time 7362607526 ps
CPU time 24.6 seconds
Started Apr 04 03:36:53 PM PDT 24
Finished Apr 04 03:37:18 PM PDT 24
Peak memory 220340 kb
Host smart-0e9e74c5-e8dd-44e9-a960-be1e755de5d1
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849247939 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rv_dm_tap_fsm_rand_reset.3849247939
Directory /workspace/13.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.4139086935
Short name T282
Test name
Test status
Simulation time 304013464 ps
CPU time 4.06 seconds
Started Apr 04 03:36:56 PM PDT 24
Finished Apr 04 03:37:01 PM PDT 24
Peak memory 212988 kb
Host smart-b9f968a2-cfb4-4f4a-8506-592521a4b17e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139086935 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.4139086935
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1688560861
Short name T144
Test name
Test status
Simulation time 211690541 ps
CPU time 8.41 seconds
Started Apr 04 03:36:56 PM PDT 24
Finished Apr 04 03:37:05 PM PDT 24
Peak memory 213096 kb
Host smart-fa893497-1171-4c01-9b42-6d105474d8ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688560861 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.1
688560861
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3098826315
Short name T328
Test name
Test status
Simulation time 143183314 ps
CPU time 2.61 seconds
Started Apr 04 03:36:56 PM PDT 24
Finished Apr 04 03:36:59 PM PDT 24
Peak memory 221128 kb
Host smart-a60f4cde-b6ce-45a8-a1f6-22c7eae7a72b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098826315 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.3098826315
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.4249805498
Short name T91
Test name
Test status
Simulation time 66311046 ps
CPU time 1.64 seconds
Started Apr 04 03:36:56 PM PDT 24
Finished Apr 04 03:36:58 PM PDT 24
Peak memory 213060 kb
Host smart-e95d1f16-6ead-4a5d-9a92-024fd8e9607a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249805498 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.4249805498
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2918260282
Short name T248
Test name
Test status
Simulation time 733769384 ps
CPU time 3.1 seconds
Started Apr 04 03:36:52 PM PDT 24
Finished Apr 04 03:36:55 PM PDT 24
Peak memory 204668 kb
Host smart-da4d0b93-1723-45e8-ac53-5ccd6f241c08
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918260282 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
2918260282
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.569606988
Short name T250
Test name
Test status
Simulation time 64694817 ps
CPU time 0.74 seconds
Started Apr 04 03:36:54 PM PDT 24
Finished Apr 04 03:36:55 PM PDT 24
Peak memory 204524 kb
Host smart-58c7dedd-3f2e-42ce-b429-25f1c80e954b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569606988 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.569606988
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1036683051
Short name T109
Test name
Test status
Simulation time 139913370 ps
CPU time 6.81 seconds
Started Apr 04 03:36:55 PM PDT 24
Finished Apr 04 03:37:04 PM PDT 24
Peak memory 204864 kb
Host smart-6e948084-85f9-4a9b-9eea-03379bccbb4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036683051 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.1036683051
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.478975438
Short name T346
Test name
Test status
Simulation time 115050415 ps
CPU time 3.27 seconds
Started Apr 04 03:36:54 PM PDT 24
Finished Apr 04 03:36:57 PM PDT 24
Peak memory 213124 kb
Host smart-38538876-72e5-4507-943b-eb2658213eda
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478975438 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.478975438
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3603423775
Short name T372
Test name
Test status
Simulation time 1450815205 ps
CPU time 15.92 seconds
Started Apr 04 03:36:55 PM PDT 24
Finished Apr 04 03:37:13 PM PDT 24
Peak memory 221152 kb
Host smart-1de6c4e7-fea8-47e1-8efb-952836b9428c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603423775 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.3
603423775
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.2746942001
Short name T306
Test name
Test status
Simulation time 1268295194 ps
CPU time 5.41 seconds
Started Apr 04 03:36:53 PM PDT 24
Finished Apr 04 03:36:59 PM PDT 24
Peak memory 218052 kb
Host smart-c9e56a21-3b86-4912-b382-fe442d63ae74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746942001 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.2746942001
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.132722884
Short name T102
Test name
Test status
Simulation time 176264555 ps
CPU time 2.3 seconds
Started Apr 04 03:36:55 PM PDT 24
Finished Apr 04 03:36:59 PM PDT 24
Peak memory 213012 kb
Host smart-67052e82-b572-470f-88e4-b21f509b870f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132722884 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.132722884
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3096918756
Short name T296
Test name
Test status
Simulation time 368157504 ps
CPU time 1.98 seconds
Started Apr 04 03:36:55 PM PDT 24
Finished Apr 04 03:36:57 PM PDT 24
Peak memory 204708 kb
Host smart-f2f37f17-c411-4a93-8703-b3032a394f6d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096918756 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
3096918756
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3418939803
Short name T261
Test name
Test status
Simulation time 26038620 ps
CPU time 0.72 seconds
Started Apr 04 03:36:53 PM PDT 24
Finished Apr 04 03:36:54 PM PDT 24
Peak memory 204524 kb
Host smart-70201f95-848c-4edc-9b01-2a942e7514e1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418939803 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
3418939803
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.1468347293
Short name T110
Test name
Test status
Simulation time 804785866 ps
CPU time 4.05 seconds
Started Apr 04 03:36:56 PM PDT 24
Finished Apr 04 03:37:01 PM PDT 24
Peak memory 204860 kb
Host smart-abee1194-1e75-4188-82a2-a7cdfb6238d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468347293 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.1468347293
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.749699609
Short name T132
Test name
Test status
Simulation time 302435574 ps
CPU time 5.66 seconds
Started Apr 04 03:36:54 PM PDT 24
Finished Apr 04 03:36:59 PM PDT 24
Peak memory 213160 kb
Host smart-0a720589-4182-4624-bc2a-60a2a7a06222
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749699609 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.749699609
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.46031842
Short name T87
Test name
Test status
Simulation time 2014348468 ps
CPU time 5.64 seconds
Started Apr 04 03:36:54 PM PDT 24
Finished Apr 04 03:37:00 PM PDT 24
Peak memory 216144 kb
Host smart-f5eddd84-0776-47c4-8170-abc45592ebf3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46031842 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.46031842
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.582853802
Short name T116
Test name
Test status
Simulation time 45398763 ps
CPU time 2.23 seconds
Started Apr 04 03:36:57 PM PDT 24
Finished Apr 04 03:37:01 PM PDT 24
Peak memory 212724 kb
Host smart-3da24eff-42ad-4a96-a1c4-53ca85c70436
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582853802 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.582853802
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2387887775
Short name T273
Test name
Test status
Simulation time 1722690205 ps
CPU time 2.47 seconds
Started Apr 04 03:36:53 PM PDT 24
Finished Apr 04 03:36:56 PM PDT 24
Peak memory 204760 kb
Host smart-1325f724-42df-4811-8fa1-04088ea152be
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387887775 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
2387887775
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3523101930
Short name T373
Test name
Test status
Simulation time 204488439 ps
CPU time 0.83 seconds
Started Apr 04 03:36:56 PM PDT 24
Finished Apr 04 03:36:58 PM PDT 24
Peak memory 204508 kb
Host smart-15d8fe8e-501d-4278-89b8-bd96f0f04c39
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523101930 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
3523101930
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3463066200
Short name T304
Test name
Test status
Simulation time 1144243748 ps
CPU time 4.67 seconds
Started Apr 04 03:36:55 PM PDT 24
Finished Apr 04 03:37:01 PM PDT 24
Peak memory 204944 kb
Host smart-13b02fbe-9187-4e2e-86d9-cb39e0831ffb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463066200 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.3463066200
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3511198367
Short name T85
Test name
Test status
Simulation time 94285933 ps
CPU time 2.31 seconds
Started Apr 04 03:36:53 PM PDT 24
Finished Apr 04 03:36:55 PM PDT 24
Peak memory 213040 kb
Host smart-473ad06f-11e2-4339-ba65-3cd05b9279be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511198367 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.3511198367
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.2738438597
Short name T140
Test name
Test status
Simulation time 1234350823 ps
CPU time 21.18 seconds
Started Apr 04 03:36:55 PM PDT 24
Finished Apr 04 03:37:18 PM PDT 24
Peak memory 221052 kb
Host smart-bdaf8351-7514-437f-8e43-247f357b3188
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738438597 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.2
738438597
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.580478280
Short name T301
Test name
Test status
Simulation time 601367714 ps
CPU time 2.94 seconds
Started Apr 04 03:36:56 PM PDT 24
Finished Apr 04 03:37:00 PM PDT 24
Peak memory 217052 kb
Host smart-a9c2a0ae-5f4f-44d6-b14b-64316fa78ba7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580478280 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.580478280
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.278313108
Short name T114
Test name
Test status
Simulation time 44601229 ps
CPU time 2.11 seconds
Started Apr 04 03:36:53 PM PDT 24
Finished Apr 04 03:36:55 PM PDT 24
Peak memory 212964 kb
Host smart-b15611a9-53f6-4e9a-a5b1-c69b3671a307
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278313108 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.278313108
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.1689886746
Short name T361
Test name
Test status
Simulation time 1256008961 ps
CPU time 4.26 seconds
Started Apr 04 03:36:56 PM PDT 24
Finished Apr 04 03:37:01 PM PDT 24
Peak memory 204700 kb
Host smart-fdaca86f-aee3-430c-ada1-70317f8f7d6b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689886746 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
1689886746
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.450640645
Short name T333
Test name
Test status
Simulation time 138745793 ps
CPU time 0.76 seconds
Started Apr 04 03:36:54 PM PDT 24
Finished Apr 04 03:36:55 PM PDT 24
Peak memory 204496 kb
Host smart-eee043c6-7c24-43c0-9733-e849bc326be2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450640645 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.450640645
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.856840122
Short name T297
Test name
Test status
Simulation time 146825588 ps
CPU time 6.38 seconds
Started Apr 04 03:36:57 PM PDT 24
Finished Apr 04 03:37:05 PM PDT 24
Peak memory 204800 kb
Host smart-3b4eda91-04a4-4938-80dd-2829cc8d9dc5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856840122 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same_
csr_outstanding.856840122
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tap_fsm_rand_reset.1428006934
Short name T357
Test name
Test status
Simulation time 11787231426 ps
CPU time 12.45 seconds
Started Apr 04 03:36:56 PM PDT 24
Finished Apr 04 03:37:09 PM PDT 24
Peak memory 221072 kb
Host smart-039bc401-b639-4c64-854c-6aed74da4711
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428006934 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rv_dm_tap_fsm_rand_reset.1428006934
Directory /workspace/17.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.1870714978
Short name T330
Test name
Test status
Simulation time 696751296 ps
CPU time 2.78 seconds
Started Apr 04 03:36:54 PM PDT 24
Finished Apr 04 03:36:58 PM PDT 24
Peak memory 213024 kb
Host smart-1e345306-8054-4138-9380-aa4c202989f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870714978 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.1870714978
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2975377914
Short name T359
Test name
Test status
Simulation time 3946445896 ps
CPU time 18.64 seconds
Started Apr 04 03:36:55 PM PDT 24
Finished Apr 04 03:37:15 PM PDT 24
Peak memory 213220 kb
Host smart-31aab8a7-2291-42d2-a06c-fbf67e095045
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975377914 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.2
975377914
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.3335324861
Short name T291
Test name
Test status
Simulation time 1371436740 ps
CPU time 4.48 seconds
Started Apr 04 03:36:55 PM PDT 24
Finished Apr 04 03:37:01 PM PDT 24
Peak memory 219204 kb
Host smart-b445cca3-7b90-4317-ad39-b994c9042874
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335324861 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.3335324861
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.698232454
Short name T89
Test name
Test status
Simulation time 622559997 ps
CPU time 2.26 seconds
Started Apr 04 03:36:55 PM PDT 24
Finished Apr 04 03:36:57 PM PDT 24
Peak memory 213048 kb
Host smart-b4fb7ca9-a94f-4a22-8d8d-52fa44bc2e70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698232454 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.698232454
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1948841120
Short name T358
Test name
Test status
Simulation time 814680361 ps
CPU time 1.25 seconds
Started Apr 04 03:36:56 PM PDT 24
Finished Apr 04 03:36:58 PM PDT 24
Peak memory 204676 kb
Host smart-5bfee1b5-3080-4629-8f0b-befa838b9827
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948841120 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
1948841120
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2655529450
Short name T283
Test name
Test status
Simulation time 73873971 ps
CPU time 0.7 seconds
Started Apr 04 03:36:54 PM PDT 24
Finished Apr 04 03:36:55 PM PDT 24
Peak memory 204528 kb
Host smart-7d7aee35-d73e-410c-8507-e6939c66664c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655529450 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
2655529450
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1835985013
Short name T105
Test name
Test status
Simulation time 82402809 ps
CPU time 3.51 seconds
Started Apr 04 03:36:56 PM PDT 24
Finished Apr 04 03:37:00 PM PDT 24
Peak memory 204756 kb
Host smart-98b872bb-b7f9-4639-b657-e8efb0dc5cbd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835985013 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.1835985013
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tap_fsm_rand_reset.2523612030
Short name T300
Test name
Test status
Simulation time 5505887698 ps
CPU time 21.1 seconds
Started Apr 04 03:36:55 PM PDT 24
Finished Apr 04 03:37:17 PM PDT 24
Peak memory 221260 kb
Host smart-b48029de-1a20-463e-843c-fc6f683a2bbe
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523612030 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rv_dm_tap_fsm_rand_reset.2523612030
Directory /workspace/18.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.3757230946
Short name T366
Test name
Test status
Simulation time 545297670 ps
CPU time 5.86 seconds
Started Apr 04 03:36:57 PM PDT 24
Finished Apr 04 03:37:03 PM PDT 24
Peak memory 213076 kb
Host smart-a0c11fce-04dd-49c7-9a43-f9d55d0f9d8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757230946 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.3757230946
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3014741288
Short name T137
Test name
Test status
Simulation time 4825553310 ps
CPU time 9.71 seconds
Started Apr 04 03:36:56 PM PDT 24
Finished Apr 04 03:37:07 PM PDT 24
Peak memory 221368 kb
Host smart-3bbb20de-be05-48d3-9e47-20e52b0e4bd4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014741288 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.3
014741288
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2269183594
Short name T258
Test name
Test status
Simulation time 345103430 ps
CPU time 4.46 seconds
Started Apr 04 03:36:54 PM PDT 24
Finished Apr 04 03:36:59 PM PDT 24
Peak memory 221084 kb
Host smart-c88fcc6f-30e1-4588-9046-fbe2d6c3d273
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269183594 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.2269183594
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.972162978
Short name T317
Test name
Test status
Simulation time 110896884 ps
CPU time 2.4 seconds
Started Apr 04 03:36:54 PM PDT 24
Finished Apr 04 03:36:57 PM PDT 24
Peak memory 218628 kb
Host smart-43469a79-cb97-4488-ab2a-e3968ed98a50
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972162978 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.972162978
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.1618440352
Short name T336
Test name
Test status
Simulation time 358957219 ps
CPU time 1.53 seconds
Started Apr 04 03:36:54 PM PDT 24
Finished Apr 04 03:36:56 PM PDT 24
Peak memory 204704 kb
Host smart-2651d7f4-7be6-4227-ac6a-4500772f65e8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618440352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
1618440352
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2784750455
Short name T268
Test name
Test status
Simulation time 51046359 ps
CPU time 0.77 seconds
Started Apr 04 03:36:55 PM PDT 24
Finished Apr 04 03:36:58 PM PDT 24
Peak memory 204452 kb
Host smart-2b861c26-0c51-415d-bc55-332e810f1968
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784750455 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
2784750455
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1780873454
Short name T93
Test name
Test status
Simulation time 2273862813 ps
CPU time 8.76 seconds
Started Apr 04 03:36:55 PM PDT 24
Finished Apr 04 03:37:05 PM PDT 24
Peak memory 205068 kb
Host smart-973f6ae6-b2fd-47da-b127-8062b99150e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780873454 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.1780873454
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.2312762473
Short name T265
Test name
Test status
Simulation time 113803399 ps
CPU time 3.24 seconds
Started Apr 04 03:36:55 PM PDT 24
Finished Apr 04 03:37:00 PM PDT 24
Peak memory 213096 kb
Host smart-9d6253d2-33e0-4a77-9965-e277703871ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312762473 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.2312762473
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.1982666658
Short name T345
Test name
Test status
Simulation time 1601555858 ps
CPU time 16.4 seconds
Started Apr 04 03:36:57 PM PDT 24
Finished Apr 04 03:37:13 PM PDT 24
Peak memory 212988 kb
Host smart-9a7d8288-89ed-48fc-8614-5cd6564428a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982666658 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.1
982666658
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3699643837
Short name T115
Test name
Test status
Simulation time 60730470 ps
CPU time 1.53 seconds
Started Apr 04 03:36:06 PM PDT 24
Finished Apr 04 03:36:08 PM PDT 24
Peak memory 213012 kb
Host smart-53dee865-9c48-47d5-89c0-6de3b35ab391
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699643837 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.3699643837
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.4120356506
Short name T322
Test name
Test status
Simulation time 2686454734 ps
CPU time 4.41 seconds
Started Apr 04 03:36:10 PM PDT 24
Finished Apr 04 03:36:15 PM PDT 24
Peak memory 215788 kb
Host smart-ec665b04-cfff-482f-8773-37c678fe190c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120356506 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.4120356506
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.787376146
Short name T117
Test name
Test status
Simulation time 25660529 ps
CPU time 1.44 seconds
Started Apr 04 03:36:13 PM PDT 24
Finished Apr 04 03:36:15 PM PDT 24
Peak memory 213020 kb
Host smart-a9a33163-857b-4166-9577-13aea1d0c498
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787376146 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.787376146
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2633277654
Short name T252
Test name
Test status
Simulation time 14216665760 ps
CPU time 39.16 seconds
Started Apr 04 03:36:05 PM PDT 24
Finished Apr 04 03:36:44 PM PDT 24
Peak memory 204780 kb
Host smart-67b099a1-4c29-4694-a1d7-248e7930d8f9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633277654 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.2633277654
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.3925090157
Short name T294
Test name
Test status
Simulation time 13758972126 ps
CPU time 51.69 seconds
Started Apr 04 03:36:10 PM PDT 24
Finished Apr 04 03:37:03 PM PDT 24
Peak memory 204812 kb
Host smart-1181e692-871e-403c-9baf-55aad19a512c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925090157 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_bit_bash.3925090157
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2442441892
Short name T99
Test name
Test status
Simulation time 821112057 ps
CPU time 1.63 seconds
Started Apr 04 03:36:10 PM PDT 24
Finished Apr 04 03:36:13 PM PDT 24
Peak memory 204756 kb
Host smart-51686730-5cba-4143-a543-9e4da8cb22d5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442441892 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.2442441892
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.3454098085
Short name T348
Test name
Test status
Simulation time 876417238 ps
CPU time 2.2 seconds
Started Apr 04 03:36:07 PM PDT 24
Finished Apr 04 03:36:09 PM PDT 24
Peak memory 204740 kb
Host smart-1ec2115c-39e4-439b-ae6a-1b41f24407bd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454098085 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.3
454098085
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.2520730608
Short name T259
Test name
Test status
Simulation time 54718406 ps
CPU time 0.74 seconds
Started Apr 04 03:36:10 PM PDT 24
Finished Apr 04 03:36:11 PM PDT 24
Peak memory 204532 kb
Host smart-d65a9f3e-58f5-4e25-861e-bc2b5c032bc0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520730608 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_aliasing.2520730608
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1146146427
Short name T310
Test name
Test status
Simulation time 1261435349 ps
CPU time 2.12 seconds
Started Apr 04 03:36:09 PM PDT 24
Finished Apr 04 03:36:12 PM PDT 24
Peak memory 204692 kb
Host smart-e5af1f82-ad07-4b3c-b4dc-54bc854cb665
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146146427 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.1146146427
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3830414261
Short name T364
Test name
Test status
Simulation time 47524851 ps
CPU time 0.81 seconds
Started Apr 04 03:36:10 PM PDT 24
Finished Apr 04 03:36:12 PM PDT 24
Peak memory 204576 kb
Host smart-6b9ce9c4-56a9-4d4b-9953-81aa7ee3e880
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830414261 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.3830414261
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.3204091298
Short name T260
Test name
Test status
Simulation time 35841577 ps
CPU time 0.74 seconds
Started Apr 04 03:36:12 PM PDT 24
Finished Apr 04 03:36:13 PM PDT 24
Peak memory 204452 kb
Host smart-b5fcedb3-e569-4238-9656-2f6ae3619b38
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204091298 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.3
204091298
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.3716970343
Short name T249
Test name
Test status
Simulation time 48031984 ps
CPU time 0.68 seconds
Started Apr 04 03:36:14 PM PDT 24
Finished Apr 04 03:36:15 PM PDT 24
Peak memory 204508 kb
Host smart-7fb6c264-2c11-4b54-aae2-6c54a1a054bf
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716970343 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.3716970343
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.3673335460
Short name T349
Test name
Test status
Simulation time 16365885 ps
CPU time 0.68 seconds
Started Apr 04 03:36:13 PM PDT 24
Finished Apr 04 03:36:14 PM PDT 24
Peak memory 204500 kb
Host smart-9635364e-6b4e-44fc-99b6-acd85823e9fc
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673335460 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.3673335460
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.40792190
Short name T327
Test name
Test status
Simulation time 417447821 ps
CPU time 4.23 seconds
Started Apr 04 03:36:10 PM PDT 24
Finished Apr 04 03:36:14 PM PDT 24
Peak memory 204864 kb
Host smart-423c34c8-e304-420d-a60a-7c8b15153b71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40792190 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_cs
r_outstanding.40792190
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.2313659258
Short name T267
Test name
Test status
Simulation time 437979352 ps
CPU time 5.71 seconds
Started Apr 04 03:36:10 PM PDT 24
Finished Apr 04 03:36:16 PM PDT 24
Peak memory 213136 kb
Host smart-1e029753-8109-45e6-925f-b98cda6b0d8a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313659258 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.2313659258
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/22.rv_dm_tap_fsm_rand_reset.3813058071
Short name T321
Test name
Test status
Simulation time 9888899673 ps
CPU time 31.8 seconds
Started Apr 04 03:36:58 PM PDT 24
Finished Apr 04 03:37:31 PM PDT 24
Peak memory 221316 kb
Host smart-59c347de-6ea6-40f8-b354-85f9db8d760f
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813058071 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 22.rv_dm_tap_fsm_rand_reset.3813058071
Directory /workspace/22.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/24.rv_dm_tap_fsm_rand_reset.1232376422
Short name T278
Test name
Test status
Simulation time 5685999931 ps
CPU time 19.78 seconds
Started Apr 04 03:36:58 PM PDT 24
Finished Apr 04 03:37:19 PM PDT 24
Peak memory 213988 kb
Host smart-5f9e17fa-501b-406b-a1fb-2b07a9fdce28
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232376422 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 24.rv_dm_tap_fsm_rand_reset.1232376422
Directory /workspace/24.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/26.rv_dm_tap_fsm_rand_reset.2907972439
Short name T145
Test name
Test status
Simulation time 10456114410 ps
CPU time 32.02 seconds
Started Apr 04 03:36:56 PM PDT 24
Finished Apr 04 03:37:29 PM PDT 24
Peak memory 229572 kb
Host smart-c9998631-3a62-4106-a021-e9aa5dd6cf72
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907972439 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 26.rv_dm_tap_fsm_rand_reset.2907972439
Directory /workspace/26.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/27.rv_dm_tap_fsm_rand_reset.1909177013
Short name T312
Test name
Test status
Simulation time 10817714391 ps
CPU time 31.75 seconds
Started Apr 04 03:36:58 PM PDT 24
Finished Apr 04 03:37:31 PM PDT 24
Peak memory 221024 kb
Host smart-2cf55589-7fd8-485b-8c34-c257bcd81cb3
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909177013 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 27.rv_dm_tap_fsm_rand_reset.1909177013
Directory /workspace/27.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1022065639
Short name T95
Test name
Test status
Simulation time 1424104045 ps
CPU time 68.05 seconds
Started Apr 04 03:36:11 PM PDT 24
Finished Apr 04 03:37:20 PM PDT 24
Peak memory 218088 kb
Host smart-b6212cbb-d063-4b7a-8a78-af07b7c3acda
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022065639 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.1022065639
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.4126638444
Short name T352
Test name
Test status
Simulation time 4884838305 ps
CPU time 67.82 seconds
Started Apr 04 03:36:13 PM PDT 24
Finished Apr 04 03:37:22 PM PDT 24
Peak memory 204920 kb
Host smart-7b32846a-2e10-4524-a126-9435c8884679
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126638444 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.4126638444
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.2185723234
Short name T112
Test name
Test status
Simulation time 159825546 ps
CPU time 2.1 seconds
Started Apr 04 03:36:13 PM PDT 24
Finished Apr 04 03:36:15 PM PDT 24
Peak memory 213036 kb
Host smart-ed4fe5e1-837f-4a23-8206-f3ccc56dd1e2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185723234 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.2185723234
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.2775247438
Short name T158
Test name
Test status
Simulation time 3354216611 ps
CPU time 6.39 seconds
Started Apr 04 03:36:13 PM PDT 24
Finished Apr 04 03:36:20 PM PDT 24
Peak memory 221388 kb
Host smart-726babe2-ad6d-4b44-9151-2e8d3b63f649
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775247438 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.2775247438
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2167853432
Short name T308
Test name
Test status
Simulation time 51719175 ps
CPU time 1.44 seconds
Started Apr 04 03:36:13 PM PDT 24
Finished Apr 04 03:36:15 PM PDT 24
Peak memory 218116 kb
Host smart-3036dbb0-1882-4a21-8fda-fe0bad441b22
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167853432 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.2167853432
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.2278895371
Short name T241
Test name
Test status
Simulation time 9645214898 ps
CPU time 33.08 seconds
Started Apr 04 03:36:14 PM PDT 24
Finished Apr 04 03:36:48 PM PDT 24
Peak memory 204836 kb
Host smart-5c92ddc6-0912-438f-87ae-28f644a46757
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278895371 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.2278895371
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.937584264
Short name T246
Test name
Test status
Simulation time 20818341449 ps
CPU time 19.98 seconds
Started Apr 04 03:36:12 PM PDT 24
Finished Apr 04 03:36:33 PM PDT 24
Peak memory 204756 kb
Host smart-7e34f231-210b-4bec-a045-ebe8b7fe56fb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937584264 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr
_bit_bash.937584264
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.1223545899
Short name T101
Test name
Test status
Simulation time 203773708 ps
CPU time 1.22 seconds
Started Apr 04 03:36:14 PM PDT 24
Finished Apr 04 03:36:16 PM PDT 24
Peak memory 204696 kb
Host smart-b0f293e7-7e4a-4cbb-894b-b617c5ecfd33
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223545899 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.1223545899
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1154881343
Short name T303
Test name
Test status
Simulation time 160950262 ps
CPU time 1.34 seconds
Started Apr 04 03:36:10 PM PDT 24
Finished Apr 04 03:36:12 PM PDT 24
Peak memory 204752 kb
Host smart-32b1eb3e-d469-4da9-b9c0-0e80f17c6cf4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154881343 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.1
154881343
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1420325888
Short name T334
Test name
Test status
Simulation time 221468965 ps
CPU time 0.75 seconds
Started Apr 04 03:36:12 PM PDT 24
Finished Apr 04 03:36:14 PM PDT 24
Peak memory 204456 kb
Host smart-9275e855-7318-4529-a0a7-6616788244a3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420325888 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.1420325888
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.897830213
Short name T286
Test name
Test status
Simulation time 1221641178 ps
CPU time 5.01 seconds
Started Apr 04 03:36:13 PM PDT 24
Finished Apr 04 03:36:18 PM PDT 24
Peak memory 204680 kb
Host smart-3e7099d8-7736-4ed8-a13d-c35081213b3e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897830213 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr
_bit_bash.897830213
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.2857755442
Short name T274
Test name
Test status
Simulation time 43497098 ps
CPU time 0.78 seconds
Started Apr 04 03:36:12 PM PDT 24
Finished Apr 04 03:36:13 PM PDT 24
Peak memory 204604 kb
Host smart-97ffc577-5a03-4889-9944-b15b47c6bc0c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857755442 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.2857755442
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.721765256
Short name T370
Test name
Test status
Simulation time 108634735 ps
CPU time 0.83 seconds
Started Apr 04 03:36:11 PM PDT 24
Finished Apr 04 03:36:12 PM PDT 24
Peak memory 204464 kb
Host smart-90d7ea32-e5c5-45ae-afd4-ed73dc09c648
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721765256 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.721765256
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.726777444
Short name T288
Test name
Test status
Simulation time 24720903 ps
CPU time 0.66 seconds
Started Apr 04 03:36:12 PM PDT 24
Finished Apr 04 03:36:14 PM PDT 24
Peak memory 204464 kb
Host smart-dfc476be-0a3d-47a0-8757-e249c1365f99
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726777444 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_part
ial_access.726777444
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1359918108
Short name T242
Test name
Test status
Simulation time 58777989 ps
CPU time 0.73 seconds
Started Apr 04 03:36:13 PM PDT 24
Finished Apr 04 03:36:14 PM PDT 24
Peak memory 204556 kb
Host smart-67eb578b-8b30-46b9-956c-46422273aca3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359918108 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.1359918108
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.373156245
Short name T323
Test name
Test status
Simulation time 1135994680 ps
CPU time 8.63 seconds
Started Apr 04 03:36:14 PM PDT 24
Finished Apr 04 03:36:22 PM PDT 24
Peak memory 204864 kb
Host smart-07543b66-bec4-412b-975d-24f0db1926a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373156245 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_c
sr_outstanding.373156245
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.399493226
Short name T319
Test name
Test status
Simulation time 33763689203 ps
CPU time 14.09 seconds
Started Apr 04 03:36:12 PM PDT 24
Finished Apr 04 03:36:26 PM PDT 24
Peak memory 215112 kb
Host smart-1f93e7af-7982-4f5e-8f7e-83c06c23029d
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399493226 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.399493226
Directory /workspace/3.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2642404440
Short name T84
Test name
Test status
Simulation time 56818336 ps
CPU time 2.85 seconds
Started Apr 04 03:36:14 PM PDT 24
Finished Apr 04 03:36:17 PM PDT 24
Peak memory 213036 kb
Host smart-f41841f8-db6d-49f2-807e-cc8926df1fab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642404440 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.2642404440
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3206567280
Short name T356
Test name
Test status
Simulation time 800560751 ps
CPU time 16.45 seconds
Started Apr 04 03:36:13 PM PDT 24
Finished Apr 04 03:36:30 PM PDT 24
Peak memory 213012 kb
Host smart-f440f8be-83bc-418a-a9d1-cf174c120b85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206567280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.3206567280
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/37.rv_dm_tap_fsm_rand_reset.3801911488
Short name T275
Test name
Test status
Simulation time 13005172222 ps
CPU time 15.29 seconds
Started Apr 04 03:36:59 PM PDT 24
Finished Apr 04 03:37:15 PM PDT 24
Peak memory 214236 kb
Host smart-bf03e5d8-0d67-49d3-9e55-b760f471d01c
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801911488 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 37.rv_dm_tap_fsm_rand_reset.3801911488
Directory /workspace/37.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2476475486
Short name T337
Test name
Test status
Simulation time 6299629708 ps
CPU time 28.88 seconds
Started Apr 04 03:36:14 PM PDT 24
Finished Apr 04 03:36:43 PM PDT 24
Peak memory 204872 kb
Host smart-40288e12-59e7-4df2-9343-fe802fb1fc8b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476475486 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.2476475486
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.1319038998
Short name T369
Test name
Test status
Simulation time 2921713152 ps
CPU time 53.7 seconds
Started Apr 04 03:36:29 PM PDT 24
Finished Apr 04 03:37:22 PM PDT 24
Peak memory 204972 kb
Host smart-c920a88e-bcc4-4c4c-947e-23d27dfd7f46
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319038998 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.1319038998
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2616060840
Short name T368
Test name
Test status
Simulation time 65844565 ps
CPU time 1.63 seconds
Started Apr 04 03:36:24 PM PDT 24
Finished Apr 04 03:36:26 PM PDT 24
Peak memory 212988 kb
Host smart-a4a8e1e2-17e2-46ca-bf20-04d6f2c7690d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616060840 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.2616060840
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.1804775161
Short name T253
Test name
Test status
Simulation time 2696369993 ps
CPU time 6.26 seconds
Started Apr 04 03:36:22 PM PDT 24
Finished Apr 04 03:36:29 PM PDT 24
Peak memory 217148 kb
Host smart-b07a1029-c597-4aee-9755-d680db4c9265
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804775161 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.1804775161
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.3257521574
Short name T47
Test name
Test status
Simulation time 61756119 ps
CPU time 1.55 seconds
Started Apr 04 03:36:23 PM PDT 24
Finished Apr 04 03:36:25 PM PDT 24
Peak memory 213024 kb
Host smart-c9878913-70a7-4ed5-bb2d-6e95fe834375
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257521574 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.3257521574
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.413583454
Short name T272
Test name
Test status
Simulation time 11249364739 ps
CPU time 16.82 seconds
Started Apr 04 03:36:15 PM PDT 24
Finished Apr 04 03:36:32 PM PDT 24
Peak memory 204804 kb
Host smart-7c2d1c1d-1763-4beb-947f-478bb9241d43
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413583454 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr
_aliasing.413583454
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.4072041723
Short name T341
Test name
Test status
Simulation time 10034737547 ps
CPU time 26.6 seconds
Started Apr 04 03:36:14 PM PDT 24
Finished Apr 04 03:36:41 PM PDT 24
Peak memory 204776 kb
Host smart-09fbe7e1-3365-4e51-bdb5-ed9d4a3ae4ee
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072041723 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_bit_bash.4072041723
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2960944362
Short name T100
Test name
Test status
Simulation time 639154032 ps
CPU time 1.36 seconds
Started Apr 04 03:36:15 PM PDT 24
Finished Apr 04 03:36:17 PM PDT 24
Peak memory 204828 kb
Host smart-3cc6ce29-f4c3-43f4-987f-45410762482a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960944362 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.2960944362
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.1758639641
Short name T332
Test name
Test status
Simulation time 704176420 ps
CPU time 1.65 seconds
Started Apr 04 03:36:14 PM PDT 24
Finished Apr 04 03:36:16 PM PDT 24
Peak memory 204676 kb
Host smart-4cc0e5e8-e04a-49c8-8a1f-bfda1ac7df1c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758639641 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.1
758639641
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.3553262490
Short name T76
Test name
Test status
Simulation time 45967502 ps
CPU time 0.82 seconds
Started Apr 04 03:36:11 PM PDT 24
Finished Apr 04 03:36:12 PM PDT 24
Peak memory 204520 kb
Host smart-8980044b-69e6-47df-8d2e-3c4c3a0b05e8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553262490 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.3553262490
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2469819071
Short name T256
Test name
Test status
Simulation time 1210296911 ps
CPU time 4.86 seconds
Started Apr 04 03:36:13 PM PDT 24
Finished Apr 04 03:36:18 PM PDT 24
Peak memory 204680 kb
Host smart-1724d790-2a5e-48ac-93ff-6b17daf9c2ee
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469819071 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.2469819071
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.503532580
Short name T375
Test name
Test status
Simulation time 66012291 ps
CPU time 0.78 seconds
Started Apr 04 03:36:15 PM PDT 24
Finished Apr 04 03:36:16 PM PDT 24
Peak memory 204560 kb
Host smart-83d91162-db68-4385-88f0-836d74e29b39
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503532580 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr
_hw_reset.503532580
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.799502645
Short name T335
Test name
Test status
Simulation time 55738357 ps
CPU time 0.75 seconds
Started Apr 04 03:36:13 PM PDT 24
Finished Apr 04 03:36:15 PM PDT 24
Peak memory 204492 kb
Host smart-3e181279-c28f-4d43-9c0d-d96d0c02e3c6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799502645 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.799502645
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.2848181524
Short name T305
Test name
Test status
Simulation time 17754328 ps
CPU time 0.69 seconds
Started Apr 04 03:36:29 PM PDT 24
Finished Apr 04 03:36:30 PM PDT 24
Peak memory 204536 kb
Host smart-5e030bac-8e02-40b4-9bd6-f982a1c044f7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848181524 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.2848181524
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.1474999725
Short name T339
Test name
Test status
Simulation time 40988876 ps
CPU time 0.66 seconds
Started Apr 04 03:36:26 PM PDT 24
Finished Apr 04 03:36:27 PM PDT 24
Peak memory 204504 kb
Host smart-67b91169-4cd6-4d16-b052-55cf189738be
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474999725 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.1474999725
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3671558732
Short name T103
Test name
Test status
Simulation time 704934469 ps
CPU time 4.38 seconds
Started Apr 04 03:36:28 PM PDT 24
Finished Apr 04 03:36:32 PM PDT 24
Peak memory 204824 kb
Host smart-98bcf674-2dfd-4e95-84c1-3bf43cddadda
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671558732 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.3671558732
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2362269742
Short name T318
Test name
Test status
Simulation time 7839692302 ps
CPU time 14.2 seconds
Started Apr 04 03:36:11 PM PDT 24
Finished Apr 04 03:36:26 PM PDT 24
Peak memory 218436 kb
Host smart-a4a20dd6-a29c-4233-bee3-90ba6b873ddd
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362269742 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.2362269742
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1039881698
Short name T138
Test name
Test status
Simulation time 7173486164 ps
CPU time 20.97 seconds
Started Apr 04 03:36:22 PM PDT 24
Finished Apr 04 03:36:43 PM PDT 24
Peak memory 221352 kb
Host smart-f26f50b7-121f-40c0-b01f-e20c78287cca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039881698 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.1039881698
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.490794045
Short name T365
Test name
Test status
Simulation time 851934082 ps
CPU time 3.86 seconds
Started Apr 04 03:36:23 PM PDT 24
Finished Apr 04 03:36:27 PM PDT 24
Peak memory 218060 kb
Host smart-2a7ef031-5996-4a45-a84e-ccf747276ec6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490794045 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.490794045
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.2942973712
Short name T251
Test name
Test status
Simulation time 93877211 ps
CPU time 1.48 seconds
Started Apr 04 03:36:29 PM PDT 24
Finished Apr 04 03:36:30 PM PDT 24
Peak memory 213016 kb
Host smart-df73a79d-ad60-4ec5-9240-6f9d8f36fbd8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942973712 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.2942973712
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.1577593501
Short name T307
Test name
Test status
Simulation time 1239513425 ps
CPU time 4.32 seconds
Started Apr 04 03:36:21 PM PDT 24
Finished Apr 04 03:36:26 PM PDT 24
Peak memory 204688 kb
Host smart-8c443810-ddd9-4da0-9d9c-cd5377fd1b6c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577593501 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.1
577593501
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.1999649903
Short name T266
Test name
Test status
Simulation time 27785435 ps
CPU time 0.71 seconds
Started Apr 04 03:36:21 PM PDT 24
Finished Apr 04 03:36:22 PM PDT 24
Peak memory 204496 kb
Host smart-31c93ffa-8664-4d21-9441-aa3a0ecc7eb8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999649903 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.1
999649903
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.3061403532
Short name T120
Test name
Test status
Simulation time 419694896 ps
CPU time 3.36 seconds
Started Apr 04 03:36:25 PM PDT 24
Finished Apr 04 03:36:28 PM PDT 24
Peak memory 204808 kb
Host smart-8df67c06-3734-420f-b0aa-0d2bc2d425ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061403532 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.3061403532
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.1694654660
Short name T276
Test name
Test status
Simulation time 182652124 ps
CPU time 5.68 seconds
Started Apr 04 03:36:23 PM PDT 24
Finished Apr 04 03:36:29 PM PDT 24
Peak memory 213088 kb
Host smart-e89c0641-f0d3-4a83-8b63-73965e891afc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694654660 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.1694654660
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.1339156699
Short name T298
Test name
Test status
Simulation time 635763679 ps
CPU time 9.75 seconds
Started Apr 04 03:36:22 PM PDT 24
Finished Apr 04 03:36:32 PM PDT 24
Peak memory 221228 kb
Host smart-2feb726f-5549-4b54-a4f5-1c2a571491a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339156699 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.1339156699
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.359164885
Short name T331
Test name
Test status
Simulation time 3337687242 ps
CPU time 5.22 seconds
Started Apr 04 03:36:22 PM PDT 24
Finished Apr 04 03:36:28 PM PDT 24
Peak memory 215476 kb
Host smart-818deeb0-5f7d-4a17-8989-92db92e61cf9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359164885 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.359164885
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1227727061
Short name T118
Test name
Test status
Simulation time 107485698 ps
CPU time 1.65 seconds
Started Apr 04 03:36:27 PM PDT 24
Finished Apr 04 03:36:29 PM PDT 24
Peak memory 213076 kb
Host smart-1720f4f0-19cf-451e-82fd-5d08e6453255
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227727061 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.1227727061
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.668356332
Short name T244
Test name
Test status
Simulation time 722366662 ps
CPU time 2.01 seconds
Started Apr 04 03:36:23 PM PDT 24
Finished Apr 04 03:36:25 PM PDT 24
Peak memory 204604 kb
Host smart-13cdecd2-59d8-48ab-949b-c0eee4cfd4a5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668356332 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.668356332
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.1293388902
Short name T309
Test name
Test status
Simulation time 51032282 ps
CPU time 0.81 seconds
Started Apr 04 03:36:26 PM PDT 24
Finished Apr 04 03:36:27 PM PDT 24
Peak memory 204480 kb
Host smart-a1ed0627-d3d1-4391-9e54-a0843259cd0a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293388902 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.1
293388902
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.3211907561
Short name T122
Test name
Test status
Simulation time 578070131 ps
CPU time 7.9 seconds
Started Apr 04 03:36:22 PM PDT 24
Finished Apr 04 03:36:31 PM PDT 24
Peak memory 204812 kb
Host smart-4324330e-3737-496e-9bcb-b6277a51f8be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211907561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.3211907561
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.2260074304
Short name T354
Test name
Test status
Simulation time 97590153 ps
CPU time 2.86 seconds
Started Apr 04 03:36:24 PM PDT 24
Finished Apr 04 03:36:28 PM PDT 24
Peak memory 213152 kb
Host smart-147e801c-c326-41f8-b9ec-f317cb88067d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260074304 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.2260074304
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3372081048
Short name T289
Test name
Test status
Simulation time 3562716036 ps
CPU time 7.53 seconds
Started Apr 04 03:36:25 PM PDT 24
Finished Apr 04 03:36:32 PM PDT 24
Peak memory 217604 kb
Host smart-095d87e0-904c-4eb7-a504-ad1874a4c2f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372081048 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.3372081048
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.2739344857
Short name T343
Test name
Test status
Simulation time 229126329 ps
CPU time 1.59 seconds
Started Apr 04 03:36:25 PM PDT 24
Finished Apr 04 03:36:27 PM PDT 24
Peak memory 213028 kb
Host smart-9f829188-a23b-4c38-84a4-11d2a61b842c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739344857 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.2739344857
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3501043915
Short name T363
Test name
Test status
Simulation time 167684030 ps
CPU time 0.98 seconds
Started Apr 04 03:36:25 PM PDT 24
Finished Apr 04 03:36:26 PM PDT 24
Peak memory 204768 kb
Host smart-319b1739-225e-4034-954b-3e3c6de4f9a7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501043915 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.3
501043915
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1997902900
Short name T344
Test name
Test status
Simulation time 126228449 ps
CPU time 0.75 seconds
Started Apr 04 03:36:26 PM PDT 24
Finished Apr 04 03:36:27 PM PDT 24
Peak memory 204496 kb
Host smart-40f8a638-fff6-4214-b1ea-3aa7f8801972
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997902900 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.1
997902900
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.664144319
Short name T285
Test name
Test status
Simulation time 225591574 ps
CPU time 6.69 seconds
Started Apr 04 03:36:42 PM PDT 24
Finished Apr 04 03:36:52 PM PDT 24
Peak memory 204836 kb
Host smart-2b81299e-06cf-4602-8b61-1f270201f80f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664144319 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_c
sr_outstanding.664144319
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.4083258524
Short name T271
Test name
Test status
Simulation time 313888931 ps
CPU time 4.66 seconds
Started Apr 04 03:36:25 PM PDT 24
Finished Apr 04 03:36:30 PM PDT 24
Peak memory 213140 kb
Host smart-59aa6dfe-a6c3-4a55-8176-3e111137be4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083258524 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.4083258524
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.1743704706
Short name T135
Test name
Test status
Simulation time 873675097 ps
CPU time 10.34 seconds
Started Apr 04 03:36:21 PM PDT 24
Finished Apr 04 03:36:32 PM PDT 24
Peak memory 213076 kb
Host smart-98425cb4-0b69-4e31-bcf4-5b39e76805e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743704706 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.1743704706
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1938000595
Short name T86
Test name
Test status
Simulation time 560631292 ps
CPU time 2.58 seconds
Started Apr 04 03:36:23 PM PDT 24
Finished Apr 04 03:36:26 PM PDT 24
Peak memory 217376 kb
Host smart-2419b855-ce9e-422a-826f-ba3c5c16ccda
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938000595 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.1938000595
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1680861562
Short name T371
Test name
Test status
Simulation time 86482302 ps
CPU time 2.18 seconds
Started Apr 04 03:36:22 PM PDT 24
Finished Apr 04 03:36:24 PM PDT 24
Peak memory 218352 kb
Host smart-4e692a29-21ec-4538-af48-17ed4ab1351d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680861562 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.1680861562
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.687829658
Short name T247
Test name
Test status
Simulation time 282987696 ps
CPU time 1.14 seconds
Started Apr 04 03:36:23 PM PDT 24
Finished Apr 04 03:36:25 PM PDT 24
Peak memory 204636 kb
Host smart-db722c7d-fdc9-46eb-a2c8-15b6e3c44589
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687829658 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.687829658
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3410348046
Short name T281
Test name
Test status
Simulation time 37385301 ps
CPU time 0.76 seconds
Started Apr 04 03:36:23 PM PDT 24
Finished Apr 04 03:36:24 PM PDT 24
Peak memory 204512 kb
Host smart-57b705f6-0354-4679-a1d3-d43de43784d0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410348046 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.3
410348046
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.1594163454
Short name T108
Test name
Test status
Simulation time 285951319 ps
CPU time 6.72 seconds
Started Apr 04 03:36:23 PM PDT 24
Finished Apr 04 03:36:30 PM PDT 24
Peak memory 204772 kb
Host smart-e18dcafe-ed53-4e00-aa3b-78377c6b294a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594163454 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_
csr_outstanding.1594163454
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.3571354045
Short name T351
Test name
Test status
Simulation time 518270068 ps
CPU time 4.85 seconds
Started Apr 04 03:36:20 PM PDT 24
Finished Apr 04 03:36:25 PM PDT 24
Peak memory 213040 kb
Host smart-f97b4196-7ac2-4471-94b8-5f25f51f0d53
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571354045 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.3571354045
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3316585004
Short name T136
Test name
Test status
Simulation time 679924168 ps
CPU time 16.08 seconds
Started Apr 04 03:36:20 PM PDT 24
Finished Apr 04 03:36:37 PM PDT 24
Peak memory 212968 kb
Host smart-c8e8d5aa-cee4-42ab-9676-084e5a118433
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316585004 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.3316585004
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.2464640020
Short name T88
Test name
Test status
Simulation time 3069070316 ps
CPU time 5.03 seconds
Started Apr 04 03:36:39 PM PDT 24
Finished Apr 04 03:36:44 PM PDT 24
Peak memory 218904 kb
Host smart-2dbfa3d2-d5b2-4898-968d-30138a571a0b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464640020 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.2464640020
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1299653000
Short name T45
Test name
Test status
Simulation time 111844894 ps
CPU time 1.61 seconds
Started Apr 04 03:36:38 PM PDT 24
Finished Apr 04 03:36:39 PM PDT 24
Peak memory 218064 kb
Host smart-913a3618-ad3f-4f8a-ba1f-1441bbef2a7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299653000 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.1299653000
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.2706339422
Short name T299
Test name
Test status
Simulation time 649389519 ps
CPU time 2.95 seconds
Started Apr 04 03:36:23 PM PDT 24
Finished Apr 04 03:36:26 PM PDT 24
Peak memory 204652 kb
Host smart-04817caf-e7b1-4b71-85e8-a8df933ebed1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706339422 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.2
706339422
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.872326214
Short name T269
Test name
Test status
Simulation time 36209094 ps
CPU time 0.66 seconds
Started Apr 04 03:36:22 PM PDT 24
Finished Apr 04 03:36:23 PM PDT 24
Peak memory 204456 kb
Host smart-9d7e788c-786d-47e8-85ea-16e5cb1bb465
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872326214 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.872326214
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.919545043
Short name T90
Test name
Test status
Simulation time 464818143 ps
CPU time 7.74 seconds
Started Apr 04 03:36:38 PM PDT 24
Finished Apr 04 03:36:46 PM PDT 24
Peak memory 204844 kb
Host smart-1362db2b-917a-4d30-9972-729e129f013d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919545043 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_c
sr_outstanding.919545043
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.3288780028
Short name T279
Test name
Test status
Simulation time 208491087 ps
CPU time 3.43 seconds
Started Apr 04 03:36:23 PM PDT 24
Finished Apr 04 03:36:27 PM PDT 24
Peak memory 213080 kb
Host smart-1b0daaba-e0fa-4563-a197-8111a0b134e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288780028 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.3288780028
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.2171906001
Short name T156
Test name
Test status
Simulation time 33001501 ps
CPU time 0.79 seconds
Started Apr 04 12:33:22 PM PDT 24
Finished Apr 04 12:33:23 PM PDT 24
Peak memory 204932 kb
Host smart-5269698e-c5a1-4b87-8675-72cb82c627cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171906001 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.2171906001
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.4180187853
Short name T146
Test name
Test status
Simulation time 4125314890 ps
CPU time 4.91 seconds
Started Apr 04 12:28:57 PM PDT 24
Finished Apr 04 12:29:02 PM PDT 24
Peak memory 203876 kb
Host smart-85513cee-3d57-43a7-8304-2a312ea794dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180187853 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.4180187853
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.957546097
Short name T23
Test name
Test status
Simulation time 807846770 ps
CPU time 3.65 seconds
Started Apr 04 12:29:45 PM PDT 24
Finished Apr 04 12:29:49 PM PDT 24
Peak memory 205180 kb
Host smart-c643cb30-0a91-43e0-a660-f0d8f782c1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957546097 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.957546097
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.1000401349
Short name T17
Test name
Test status
Simulation time 158211658 ps
CPU time 0.73 seconds
Started Apr 04 12:29:04 PM PDT 24
Finished Apr 04 12:29:05 PM PDT 24
Peak memory 204684 kb
Host smart-84bc5f58-4116-4cd6-b09f-c61f6557c5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000401349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.1000401349
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.477036042
Short name T185
Test name
Test status
Simulation time 9654011351 ps
CPU time 33.8 seconds
Started Apr 04 12:28:56 PM PDT 24
Finished Apr 04 12:29:30 PM PDT 24
Peak memory 213328 kb
Host smart-61b9b917-98ef-457b-8142-a379b7582d25
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=477036042 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_tl
_access.477036042
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.3199280878
Short name T8
Test name
Test status
Simulation time 1198419809 ps
CPU time 1.27 seconds
Started Apr 04 12:28:55 PM PDT 24
Finished Apr 04 12:28:56 PM PDT 24
Peak memory 204944 kb
Host smart-6ad4ef99-964f-4d6c-84be-a043ea8eeaf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199280878 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.3199280878
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.518078160
Short name T177
Test name
Test status
Simulation time 31312453 ps
CPU time 0.75 seconds
Started Apr 04 12:29:02 PM PDT 24
Finished Apr 04 12:29:04 PM PDT 24
Peak memory 203124 kb
Host smart-d293bc75-958e-406d-947c-f1f37dc20811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518078160 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.518078160
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.1681753677
Short name T35
Test name
Test status
Simulation time 50207674 ps
CPU time 0.83 seconds
Started Apr 04 12:28:03 PM PDT 24
Finished Apr 04 12:28:04 PM PDT 24
Peak memory 205176 kb
Host smart-d1d141a7-88c0-4000-89bd-7baa8f28edca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681753677 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.1681753677
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.3050692476
Short name T195
Test name
Test status
Simulation time 149181073 ps
CPU time 0.89 seconds
Started Apr 04 12:29:25 PM PDT 24
Finished Apr 04 12:29:26 PM PDT 24
Peak memory 204860 kb
Host smart-34753b58-7f49-44af-be06-6dc7b4e161b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050692476 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.3050692476
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.1241271934
Short name T70
Test name
Test status
Simulation time 318127758 ps
CPU time 1.81 seconds
Started Apr 04 12:27:51 PM PDT 24
Finished Apr 04 12:27:53 PM PDT 24
Peak memory 205000 kb
Host smart-8e68d4ef-6c23-42f0-9989-cb8369095a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241271934 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.1241271934
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.297381456
Short name T22
Test name
Test status
Simulation time 50071237 ps
CPU time 0.7 seconds
Started Apr 04 12:29:47 PM PDT 24
Finished Apr 04 12:29:48 PM PDT 24
Peak memory 204832 kb
Host smart-b3119b90-ce2e-4b3f-adeb-85d625d448d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297381456 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.297381456
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.797070313
Short name T147
Test name
Test status
Simulation time 185471336 ps
CPU time 0.71 seconds
Started Apr 04 12:29:06 PM PDT 24
Finished Apr 04 12:29:07 PM PDT 24
Peak memory 205012 kb
Host smart-683fee19-39b9-42d9-8e37-789ede07c30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797070313 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.797070313
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.2037911006
Short name T148
Test name
Test status
Simulation time 177586546 ps
CPU time 1.31 seconds
Started Apr 04 12:29:02 PM PDT 24
Finished Apr 04 12:29:04 PM PDT 24
Peak memory 203608 kb
Host smart-0f475453-5a3b-458d-a415-4cde6f9a5b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037911006 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.2037911006
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.740917089
Short name T2
Test name
Test status
Simulation time 332932502 ps
CPU time 0.94 seconds
Started Apr 04 12:29:23 PM PDT 24
Finished Apr 04 12:29:24 PM PDT 24
Peak memory 203692 kb
Host smart-de60dec7-ba94-49f4-8b2e-ac8f76cac266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740917089 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.740917089
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.2834026207
Short name T63
Test name
Test status
Simulation time 67552777 ps
CPU time 0.82 seconds
Started Apr 04 12:28:27 PM PDT 24
Finished Apr 04 12:28:28 PM PDT 24
Peak memory 213264 kb
Host smart-29d70975-8e60-459a-a439-a06c90d5eda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834026207 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.2834026207
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.2216632412
Short name T211
Test name
Test status
Simulation time 2483120641 ps
CPU time 4.65 seconds
Started Apr 04 12:28:52 PM PDT 24
Finished Apr 04 12:28:57 PM PDT 24
Peak memory 204376 kb
Host smart-087747ca-3ac2-423a-84d8-790b1c1ad479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216632412 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.2216632412
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.3098557697
Short name T213
Test name
Test status
Simulation time 792980878 ps
CPU time 1.35 seconds
Started Apr 04 12:28:53 PM PDT 24
Finished Apr 04 12:28:54 PM PDT 24
Peak memory 204784 kb
Host smart-9f313bcd-2aa3-463b-ba38-2d19038ad208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098557697 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.3098557697
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.2661791249
Short name T34
Test name
Test status
Simulation time 749195052 ps
CPU time 3.19 seconds
Started Apr 04 12:28:52 PM PDT 24
Finished Apr 04 12:28:55 PM PDT 24
Peak memory 204296 kb
Host smart-bfb5038a-5bcc-49cb-86b1-c953a39b43e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661791249 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.2661791249
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.775317192
Short name T129
Test name
Test status
Simulation time 33425911414 ps
CPU time 112.64 seconds
Started Apr 04 12:32:11 PM PDT 24
Finished Apr 04 12:34:04 PM PDT 24
Peak memory 213748 kb
Host smart-447b15dd-863a-40a8-a955-df9884345303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775317192 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.775317192
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.3777586264
Short name T6
Test name
Test status
Simulation time 2699239218 ps
CPU time 3.71 seconds
Started Apr 04 12:32:11 PM PDT 24
Finished Apr 04 12:32:15 PM PDT 24
Peak memory 205452 kb
Host smart-ed27d9b1-3353-4deb-8056-82a348a6d4a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777586264 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.3777586264
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.1493819553
Short name T66
Test name
Test status
Simulation time 174055036 ps
CPU time 1.02 seconds
Started Apr 04 12:32:10 PM PDT 24
Finished Apr 04 12:32:12 PM PDT 24
Peak memory 205020 kb
Host smart-13a588d8-3b90-4a95-a604-3b52e86de0b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493819553 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.1493819553
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.877387632
Short name T25
Test name
Test status
Simulation time 71328033 ps
CPU time 0.88 seconds
Started Apr 04 12:33:27 PM PDT 24
Finished Apr 04 12:33:28 PM PDT 24
Peak memory 204492 kb
Host smart-4b63a10b-573d-41cf-8c06-0484bc863e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877387632 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.877387632
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.376004277
Short name T9
Test name
Test status
Simulation time 1001912281 ps
CPU time 2.45 seconds
Started Apr 04 12:33:26 PM PDT 24
Finished Apr 04 12:33:29 PM PDT 24
Peak memory 205036 kb
Host smart-730689f6-a361-4598-9c60-2f401c84a84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376004277 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.376004277
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.1366808178
Short name T149
Test name
Test status
Simulation time 52612670 ps
CPU time 0.76 seconds
Started Apr 04 12:33:26 PM PDT 24
Finished Apr 04 12:33:27 PM PDT 24
Peak memory 203080 kb
Host smart-1374d95c-3658-4e1e-b66b-660c893da1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366808178 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.1366808178
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.2518740631
Short name T50
Test name
Test status
Simulation time 826749503 ps
CPU time 1.82 seconds
Started Apr 04 12:33:25 PM PDT 24
Finished Apr 04 12:33:27 PM PDT 24
Peak memory 203692 kb
Host smart-ddf0f897-0ebf-4797-96d5-2cfcf2c27a00
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2518740631 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.2518740631
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.1185101279
Short name T64
Test name
Test status
Simulation time 1238837115 ps
CPU time 1.75 seconds
Started Apr 04 12:33:26 PM PDT 24
Finished Apr 04 12:33:28 PM PDT 24
Peak memory 204872 kb
Host smart-662f1f46-f332-46e6-8525-4a83251de745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185101279 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.1185101279
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.1842316242
Short name T178
Test name
Test status
Simulation time 228355773 ps
CPU time 0.89 seconds
Started Apr 04 12:32:08 PM PDT 24
Finished Apr 04 12:32:09 PM PDT 24
Peak memory 204968 kb
Host smart-bd492a69-fdd0-4505-a5cb-355c70512cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842316242 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.1842316242
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.2318048201
Short name T16
Test name
Test status
Simulation time 134904717 ps
CPU time 0.88 seconds
Started Apr 04 12:32:12 PM PDT 24
Finished Apr 04 12:32:13 PM PDT 24
Peak memory 204964 kb
Host smart-f151a375-3f46-4099-843a-3a0a0e38c3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318048201 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.2318048201
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.1189941826
Short name T226
Test name
Test status
Simulation time 423158842 ps
CPU time 0.8 seconds
Started Apr 04 12:33:26 PM PDT 24
Finished Apr 04 12:33:27 PM PDT 24
Peak memory 204392 kb
Host smart-44bbbbeb-6d4e-4daa-81a7-c409ee7f7f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189941826 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.1189941826
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.3413448956
Short name T73
Test name
Test status
Simulation time 30474139 ps
CPU time 0.72 seconds
Started Apr 04 12:32:11 PM PDT 24
Finished Apr 04 12:32:12 PM PDT 24
Peak memory 204892 kb
Host smart-b1ea3484-15dc-41be-874b-95a89909f0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413448956 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.3413448956
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.3824730012
Short name T83
Test name
Test status
Simulation time 64932664 ps
CPU time 0.76 seconds
Started Apr 04 12:33:27 PM PDT 24
Finished Apr 04 12:33:28 PM PDT 24
Peak memory 204616 kb
Host smart-38bada5b-0a02-488d-b8b8-a2ca3277a6bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824730012 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.3824730012
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.1406439945
Short name T13
Test name
Test status
Simulation time 174074033 ps
CPU time 1.19 seconds
Started Apr 04 12:33:25 PM PDT 24
Finished Apr 04 12:33:27 PM PDT 24
Peak memory 204548 kb
Host smart-8be869ed-93db-45d3-8df5-e296758f310b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406439945 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.1406439945
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.3315477841
Short name T18
Test name
Test status
Simulation time 184124602 ps
CPU time 1.38 seconds
Started Apr 04 12:33:26 PM PDT 24
Finished Apr 04 12:33:28 PM PDT 24
Peak memory 203152 kb
Host smart-aaa4912a-a1a4-4736-a068-d4f23bee1cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315477841 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.3315477841
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.1643988079
Short name T4
Test name
Test status
Simulation time 36581670 ps
CPU time 0.83 seconds
Started Apr 04 12:32:08 PM PDT 24
Finished Apr 04 12:32:09 PM PDT 24
Peak memory 205116 kb
Host smart-7869ca20-5097-485f-b9d5-f3dc1cbee11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643988079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.1643988079
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.3873587749
Short name T7
Test name
Test status
Simulation time 95720184 ps
CPU time 1 seconds
Started Apr 04 12:32:05 PM PDT 24
Finished Apr 04 12:32:06 PM PDT 24
Peak memory 205016 kb
Host smart-da7fc50f-9d3b-481e-b83e-bbcede6981a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873587749 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.3873587749
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.1445690574
Short name T214
Test name
Test status
Simulation time 633287657 ps
CPU time 4.1 seconds
Started Apr 04 12:32:08 PM PDT 24
Finished Apr 04 12:32:12 PM PDT 24
Peak memory 205364 kb
Host smart-31d3bd85-d0d9-47d2-a88d-1c0c4c0df081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445690574 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.1445690574
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.1279423085
Short name T27
Test name
Test status
Simulation time 282743256 ps
CPU time 1.29 seconds
Started Apr 04 12:32:11 PM PDT 24
Finished Apr 04 12:32:13 PM PDT 24
Peak memory 229216 kb
Host smart-1144fe1b-c2c8-4673-822a-547c8820b8ac
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279423085 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.1279423085
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.3701081808
Short name T193
Test name
Test status
Simulation time 216624789 ps
CPU time 1.42 seconds
Started Apr 04 12:32:09 PM PDT 24
Finished Apr 04 12:32:11 PM PDT 24
Peak memory 204940 kb
Host smart-2954fda1-691c-4143-af3f-5655bd67112d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701081808 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.3701081808
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.1400608863
Short name T60
Test name
Test status
Simulation time 51788571 ps
CPU time 0.72 seconds
Started Apr 04 12:32:22 PM PDT 24
Finished Apr 04 12:32:23 PM PDT 24
Peak memory 205052 kb
Host smart-76423a8a-e0a5-4bda-96d9-ea264e638fbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400608863 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.1400608863
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.3918209078
Short name T187
Test name
Test status
Simulation time 2408265227 ps
CPU time 6.4 seconds
Started Apr 04 12:32:35 PM PDT 24
Finished Apr 04 12:32:41 PM PDT 24
Peak memory 215176 kb
Host smart-78e0a1fb-75c2-4432-9866-d5a1b131e76e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918209078 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.3918209078
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.1512218899
Short name T39
Test name
Test status
Simulation time 1359668380 ps
CPU time 5.04 seconds
Started Apr 04 12:32:36 PM PDT 24
Finished Apr 04 12:32:41 PM PDT 24
Peak memory 205376 kb
Host smart-97290ab0-9a54-4233-836f-1c730a1770b4
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1512218899 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.1512218899
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.455511375
Short name T69
Test name
Test status
Simulation time 968279851 ps
CPU time 4.64 seconds
Started Apr 04 12:32:33 PM PDT 24
Finished Apr 04 12:32:38 PM PDT 24
Peak memory 205328 kb
Host smart-5d9d2ea8-f9a1-49b1-b3c9-da6ccbdf4785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455511375 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.455511375
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.2129329021
Short name T221
Test name
Test status
Simulation time 47298572 ps
CPU time 0.73 seconds
Started Apr 04 12:32:23 PM PDT 24
Finished Apr 04 12:32:24 PM PDT 24
Peak memory 205084 kb
Host smart-ea2c9293-bfdc-4634-a26f-dcc7b357a16f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129329021 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.2129329021
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.580824335
Short name T82
Test name
Test status
Simulation time 1215920516 ps
CPU time 3.79 seconds
Started Apr 04 12:32:23 PM PDT 24
Finished Apr 04 12:32:26 PM PDT 24
Peak memory 205400 kb
Host smart-3b61f536-8042-4f60-a620-661c8bca00ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580824335 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.580824335
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.3326919948
Short name T197
Test name
Test status
Simulation time 5337675374 ps
CPU time 5.92 seconds
Started Apr 04 12:32:22 PM PDT 24
Finished Apr 04 12:32:28 PM PDT 24
Peak memory 213700 kb
Host smart-289e9c6b-aa11-4757-91bb-f1e16147565a
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3326919948 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_
tl_access.3326919948
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.3063014865
Short name T232
Test name
Test status
Simulation time 3299878045 ps
CPU time 13.14 seconds
Started Apr 04 12:32:24 PM PDT 24
Finished Apr 04 12:32:37 PM PDT 24
Peak memory 205472 kb
Host smart-eb1ec123-de50-4857-9378-543cb57bf914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063014865 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.3063014865
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.3144439248
Short name T233
Test name
Test status
Simulation time 28883481 ps
CPU time 0.7 seconds
Started Apr 04 12:33:58 PM PDT 24
Finished Apr 04 12:33:59 PM PDT 24
Peak memory 204940 kb
Host smart-24ce9836-3e47-4a56-9e7b-7b0f2abb7811
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144439248 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.3144439248
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.2513324032
Short name T19
Test name
Test status
Simulation time 8097736716 ps
CPU time 14.88 seconds
Started Apr 04 12:32:34 PM PDT 24
Finished Apr 04 12:32:49 PM PDT 24
Peak memory 213712 kb
Host smart-1a7d50ca-0c01-47f4-8243-78dd60dfb357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513324032 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.2513324032
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.3252366883
Short name T127
Test name
Test status
Simulation time 11526212350 ps
CPU time 38.14 seconds
Started Apr 04 12:32:35 PM PDT 24
Finished Apr 04 12:33:13 PM PDT 24
Peak memory 213676 kb
Host smart-9fa09432-accb-4a93-b40e-d2859fd74ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252366883 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.3252366883
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.4151059567
Short name T207
Test name
Test status
Simulation time 9530492100 ps
CPU time 18.3 seconds
Started Apr 04 12:32:34 PM PDT 24
Finished Apr 04 12:32:53 PM PDT 24
Peak memory 214864 kb
Host smart-000374ec-7c6c-43c1-8cae-7d4a2d6d149d
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4151059567 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.4151059567
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.1500671573
Short name T182
Test name
Test status
Simulation time 9703726894 ps
CPU time 11.8 seconds
Started Apr 04 12:34:13 PM PDT 24
Finished Apr 04 12:34:25 PM PDT 24
Peak memory 205400 kb
Host smart-6c229cf4-d1e2-4b70-8f71-05d39c8363f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500671573 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.1500671573
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.2829507672
Short name T204
Test name
Test status
Simulation time 48161030 ps
CPU time 0.74 seconds
Started Apr 04 12:33:53 PM PDT 24
Finished Apr 04 12:33:54 PM PDT 24
Peak memory 204704 kb
Host smart-0f4082f0-3780-4cdc-98d6-bc651ee91d1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829507672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.2829507672
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.2502719900
Short name T20
Test name
Test status
Simulation time 37719723263 ps
CPU time 35.81 seconds
Started Apr 04 12:33:53 PM PDT 24
Finished Apr 04 12:34:29 PM PDT 24
Peak memory 213404 kb
Host smart-7a8a3f9a-4ce0-40f4-80b7-b2d97552efac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502719900 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.2502719900
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.3696341377
Short name T218
Test name
Test status
Simulation time 1797076346 ps
CPU time 4.03 seconds
Started Apr 04 12:32:34 PM PDT 24
Finished Apr 04 12:32:38 PM PDT 24
Peak memory 205396 kb
Host smart-c9e599b3-2a35-4946-87f2-0e681e49460a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696341377 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.3696341377
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.2322813200
Short name T202
Test name
Test status
Simulation time 1170504666 ps
CPU time 3.08 seconds
Started Apr 04 12:32:41 PM PDT 24
Finished Apr 04 12:32:46 PM PDT 24
Peak memory 205460 kb
Host smart-7a1890e0-0a76-41b7-b005-eb84b950da8e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2322813200 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_
tl_access.2322813200
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.2091483473
Short name T183
Test name
Test status
Simulation time 8122345531 ps
CPU time 9.95 seconds
Started Apr 04 12:33:43 PM PDT 24
Finished Apr 04 12:33:55 PM PDT 24
Peak memory 204632 kb
Host smart-4f0192ef-cd71-47ed-a797-374d58743f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091483473 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.2091483473
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.3176181986
Short name T174
Test name
Test status
Simulation time 60527943 ps
CPU time 0.73 seconds
Started Apr 04 12:32:33 PM PDT 24
Finished Apr 04 12:32:33 PM PDT 24
Peak memory 205032 kb
Host smart-525f5a58-b028-4b0a-81d0-d9fd58f1deea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176181986 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.3176181986
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.4195665872
Short name T200
Test name
Test status
Simulation time 10274482660 ps
CPU time 11.61 seconds
Started Apr 04 12:33:55 PM PDT 24
Finished Apr 04 12:34:07 PM PDT 24
Peak memory 213564 kb
Host smart-17daa79b-6a8f-4d4a-a60f-fc7d4a07717a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195665872 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.4195665872
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.3307931534
Short name T236
Test name
Test status
Simulation time 3950051685 ps
CPU time 8.68 seconds
Started Apr 04 12:32:41 PM PDT 24
Finished Apr 04 12:32:51 PM PDT 24
Peak memory 205484 kb
Host smart-ad7dc834-fcd4-4eff-9c74-43000ae5892f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307931534 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.3307931534
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.3745117033
Short name T179
Test name
Test status
Simulation time 1102575018 ps
CPU time 2.74 seconds
Started Apr 04 12:32:38 PM PDT 24
Finished Apr 04 12:32:41 PM PDT 24
Peak memory 205344 kb
Host smart-ba00c468-3719-4613-9b00-ae1430724a2d
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3745117033 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.3745117033
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.3817845978
Short name T227
Test name
Test status
Simulation time 4521169738 ps
CPU time 4.91 seconds
Started Apr 04 12:33:44 PM PDT 24
Finished Apr 04 12:33:49 PM PDT 24
Peak memory 205396 kb
Host smart-74f33a27-6dbf-4033-b231-8f1b52eb46a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817845978 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.3817845978
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.2526064778
Short name T165
Test name
Test status
Simulation time 52355714 ps
CPU time 0.74 seconds
Started Apr 04 12:32:44 PM PDT 24
Finished Apr 04 12:32:45 PM PDT 24
Peak memory 205108 kb
Host smart-7bddd4fc-dba9-4ff8-b487-cfcacbeeec04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526064778 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.2526064778
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.2326919756
Short name T188
Test name
Test status
Simulation time 578772868 ps
CPU time 3.13 seconds
Started Apr 04 12:32:38 PM PDT 24
Finished Apr 04 12:32:42 PM PDT 24
Peak memory 205392 kb
Host smart-3123dc83-7325-4b33-b77e-d5ba4ce1b0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326919756 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.2326919756
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.2145979370
Short name T186
Test name
Test status
Simulation time 3862000225 ps
CPU time 16.22 seconds
Started Apr 04 12:32:38 PM PDT 24
Finished Apr 04 12:32:54 PM PDT 24
Peak memory 205540 kb
Host smart-7e7b63be-f6bc-4cad-9e6c-f20ab68527da
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2145979370 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_
tl_access.2145979370
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.2624297209
Short name T209
Test name
Test status
Simulation time 1634679605 ps
CPU time 9.17 seconds
Started Apr 04 12:32:36 PM PDT 24
Finished Apr 04 12:32:45 PM PDT 24
Peak memory 205276 kb
Host smart-951b7a1a-10d2-4b62-ba72-f457683c0905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624297209 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.2624297209
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.2281965352
Short name T164
Test name
Test status
Simulation time 50340123 ps
CPU time 0.72 seconds
Started Apr 04 12:32:45 PM PDT 24
Finished Apr 04 12:32:47 PM PDT 24
Peak memory 205000 kb
Host smart-15d9dedc-396a-4d6e-b234-fe6f7251a6eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281965352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.2281965352
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.2632096639
Short name T234
Test name
Test status
Simulation time 11019625106 ps
CPU time 31.48 seconds
Started Apr 04 12:32:48 PM PDT 24
Finished Apr 04 12:33:19 PM PDT 24
Peak memory 213660 kb
Host smart-3ef23380-be83-44bd-a6c7-5926f59474e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632096639 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.2632096639
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.1546540717
Short name T235
Test name
Test status
Simulation time 4250605309 ps
CPU time 12.08 seconds
Started Apr 04 12:32:44 PM PDT 24
Finished Apr 04 12:32:57 PM PDT 24
Peak memory 213744 kb
Host smart-9654f02d-d76b-46da-a25e-70f1d48aeccf
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1546540717 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_
tl_access.1546540717
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.2913117684
Short name T198
Test name
Test status
Simulation time 6012974174 ps
CPU time 13.69 seconds
Started Apr 04 12:32:48 PM PDT 24
Finished Apr 04 12:33:01 PM PDT 24
Peak memory 205540 kb
Host smart-2cc244af-bac2-4ef9-aa30-a83653cf3ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913117684 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.2913117684
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.2743405963
Short name T224
Test name
Test status
Simulation time 29457432 ps
CPU time 0.75 seconds
Started Apr 04 12:32:45 PM PDT 24
Finished Apr 04 12:32:46 PM PDT 24
Peak memory 205064 kb
Host smart-ab3f7583-5ee4-4833-a9a4-4008f852a4dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743405963 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.2743405963
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.4291557256
Short name T96
Test name
Test status
Simulation time 2586751344 ps
CPU time 6.33 seconds
Started Apr 04 12:32:45 PM PDT 24
Finished Apr 04 12:32:52 PM PDT 24
Peak memory 205436 kb
Host smart-236636a1-1e43-4cf5-9b37-46e17e8a61bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291557256 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.4291557256
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.2543850951
Short name T216
Test name
Test status
Simulation time 1463397736 ps
CPU time 5.4 seconds
Started Apr 04 12:32:45 PM PDT 24
Finished Apr 04 12:32:50 PM PDT 24
Peak memory 205308 kb
Host smart-6b5c3bd1-66c9-4050-9229-cdc8451bacdb
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2543850951 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_
tl_access.2543850951
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.1714914706
Short name T40
Test name
Test status
Simulation time 3881335291 ps
CPU time 13.25 seconds
Started Apr 04 12:32:45 PM PDT 24
Finished Apr 04 12:32:58 PM PDT 24
Peak memory 205500 kb
Host smart-340d02d7-6c12-4929-9fbd-3ee36240c61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714914706 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.1714914706
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.3654458847
Short name T166
Test name
Test status
Simulation time 23359117 ps
CPU time 0.74 seconds
Started Apr 04 12:33:55 PM PDT 24
Finished Apr 04 12:33:57 PM PDT 24
Peak memory 204112 kb
Host smart-e0103f28-0ad2-4bb8-a415-3c57a6b15a52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654458847 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.3654458847
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.2338680591
Short name T1
Test name
Test status
Simulation time 2031104574 ps
CPU time 6.87 seconds
Started Apr 04 12:32:47 PM PDT 24
Finished Apr 04 12:32:54 PM PDT 24
Peak memory 205308 kb
Host smart-0af82e41-3261-487b-8aad-8fedc2c612a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338680591 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.2338680591
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.1422278810
Short name T181
Test name
Test status
Simulation time 829246489 ps
CPU time 3.34 seconds
Started Apr 04 12:32:46 PM PDT 24
Finished Apr 04 12:32:50 PM PDT 24
Peak memory 205400 kb
Host smart-b72251fb-557c-4796-a9bd-490343d08429
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1422278810 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_
tl_access.1422278810
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.1446799386
Short name T128
Test name
Test status
Simulation time 5291114288 ps
CPU time 9.46 seconds
Started Apr 04 12:32:48 PM PDT 24
Finished Apr 04 12:32:57 PM PDT 24
Peak memory 205540 kb
Host smart-3f19ceb3-e7a4-48bf-8dd8-e0c4b739702b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446799386 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.1446799386
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.218646722
Short name T225
Test name
Test status
Simulation time 45357972 ps
CPU time 0.71 seconds
Started Apr 04 12:32:56 PM PDT 24
Finished Apr 04 12:32:57 PM PDT 24
Peak memory 205076 kb
Host smart-db6e0588-19e1-40ad-a125-43de6c53e8a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218646722 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.218646722
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.3046058029
Short name T56
Test name
Test status
Simulation time 3892959065 ps
CPU time 3.96 seconds
Started Apr 04 12:32:46 PM PDT 24
Finished Apr 04 12:32:51 PM PDT 24
Peak memory 205540 kb
Host smart-998ed875-7592-499d-87cd-f708d012fdf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046058029 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.3046058029
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.1863167816
Short name T59
Test name
Test status
Simulation time 2144074011 ps
CPU time 3.08 seconds
Started Apr 04 12:32:49 PM PDT 24
Finished Apr 04 12:32:52 PM PDT 24
Peak memory 205416 kb
Host smart-7e700df5-a8af-44eb-8d91-b74cb2cf1f9c
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1863167816 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_
tl_access.1863167816
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.2984778543
Short name T189
Test name
Test status
Simulation time 9926073862 ps
CPU time 13.35 seconds
Started Apr 04 12:32:46 PM PDT 24
Finished Apr 04 12:33:00 PM PDT 24
Peak memory 213792 kb
Host smart-a2f8c833-9404-4951-b40b-562735727cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984778543 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.2984778543
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.1654157098
Short name T33
Test name
Test status
Simulation time 38646714 ps
CPU time 0.7 seconds
Started Apr 04 12:32:14 PM PDT 24
Finished Apr 04 12:32:15 PM PDT 24
Peak memory 205100 kb
Host smart-81a9436c-e082-4e24-9390-c41f52317b1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654157098 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.1654157098
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.1611673370
Short name T231
Test name
Test status
Simulation time 1181151403 ps
CPU time 3.53 seconds
Started Apr 04 12:32:35 PM PDT 24
Finished Apr 04 12:32:38 PM PDT 24
Peak memory 205392 kb
Host smart-8991083e-198b-4423-aa68-d56415cbffaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611673370 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.1611673370
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.561221237
Short name T201
Test name
Test status
Simulation time 582699586 ps
CPU time 2.88 seconds
Started Apr 04 12:32:21 PM PDT 24
Finished Apr 04 12:32:24 PM PDT 24
Peak memory 205376 kb
Host smart-a822db72-5101-46f8-b33a-540e414acd4d
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=561221237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_tl
_access.561221237
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.1528690148
Short name T10
Test name
Test status
Simulation time 38828039 ps
CPU time 0.78 seconds
Started Apr 04 12:32:13 PM PDT 24
Finished Apr 04 12:32:14 PM PDT 24
Peak memory 204992 kb
Host smart-4b5888a1-9283-4925-aaa9-e3d3a1e21017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528690148 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.1528690148
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.15920251
Short name T208
Test name
Test status
Simulation time 1125067890 ps
CPU time 4.62 seconds
Started Apr 04 12:32:21 PM PDT 24
Finished Apr 04 12:32:25 PM PDT 24
Peak memory 205376 kb
Host smart-0859e12f-0a4c-42e6-b058-d4735429f965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15920251 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.15920251
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.2018856534
Short name T52
Test name
Test status
Simulation time 176971328 ps
CPU time 1.23 seconds
Started Apr 04 12:32:19 PM PDT 24
Finished Apr 04 12:32:20 PM PDT 24
Peak memory 229292 kb
Host smart-6af5eaf1-9917-424a-89ef-75648a990935
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018856534 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.2018856534
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.358912995
Short name T170
Test name
Test status
Simulation time 43749387 ps
CPU time 0.76 seconds
Started Apr 04 12:32:57 PM PDT 24
Finished Apr 04 12:32:59 PM PDT 24
Peak memory 205060 kb
Host smart-b04ba86b-c468-4dd3-b089-03ce290078fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358912995 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.358912995
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.4094823536
Short name T159
Test name
Test status
Simulation time 18967895 ps
CPU time 0.73 seconds
Started Apr 04 12:32:56 PM PDT 24
Finished Apr 04 12:32:57 PM PDT 24
Peak memory 205108 kb
Host smart-c2f2d4d1-b62d-4de1-81f3-4c52e20a0ee7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094823536 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.4094823536
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.1504011822
Short name T161
Test name
Test status
Simulation time 58111219 ps
CPU time 0.82 seconds
Started Apr 04 12:32:56 PM PDT 24
Finished Apr 04 12:32:57 PM PDT 24
Peak memory 205064 kb
Host smart-a6b81fa2-dd8c-4852-bbf0-61c3b059985b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504011822 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.1504011822
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.2665132742
Short name T29
Test name
Test status
Simulation time 44268400 ps
CPU time 0.67 seconds
Started Apr 04 12:34:13 PM PDT 24
Finished Apr 04 12:34:14 PM PDT 24
Peak memory 204940 kb
Host smart-3a8a23f3-1c2c-4ca5-9778-47cd80d81873
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665132742 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.2665132742
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.1749260209
Short name T80
Test name
Test status
Simulation time 18077450 ps
CPU time 0.72 seconds
Started Apr 04 12:32:54 PM PDT 24
Finished Apr 04 12:32:55 PM PDT 24
Peak memory 205112 kb
Host smart-9353b833-85d4-42f0-8f81-3d9cc8e043d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749260209 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.1749260209
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.1341310673
Short name T77
Test name
Test status
Simulation time 57217581 ps
CPU time 0.72 seconds
Started Apr 04 12:32:54 PM PDT 24
Finished Apr 04 12:32:55 PM PDT 24
Peak memory 205116 kb
Host smart-530bd08a-abe1-4fbe-bce3-99eae7c61758
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341310673 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.1341310673
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.415456482
Short name T215
Test name
Test status
Simulation time 45663768 ps
CPU time 0.68 seconds
Started Apr 04 12:32:55 PM PDT 24
Finished Apr 04 12:32:56 PM PDT 24
Peak memory 205028 kb
Host smart-7b46f48f-1085-4925-aa40-5950bab11acb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415456482 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.415456482
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.1419806702
Short name T151
Test name
Test status
Simulation time 48356167 ps
CPU time 0.73 seconds
Started Apr 04 12:32:57 PM PDT 24
Finished Apr 04 12:32:59 PM PDT 24
Peak memory 205088 kb
Host smart-dbfe3a07-0d16-4411-af31-8c7699d64cf3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419806702 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.1419806702
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.3795267240
Short name T79
Test name
Test status
Simulation time 44744275 ps
CPU time 0.7 seconds
Started Apr 04 12:32:55 PM PDT 24
Finished Apr 04 12:32:56 PM PDT 24
Peak memory 205092 kb
Host smart-c544615a-0b09-44f1-a093-c98b3a301d58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795267240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.3795267240
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.3797478817
Short name T150
Test name
Test status
Simulation time 66114448 ps
CPU time 0.71 seconds
Started Apr 04 12:32:16 PM PDT 24
Finished Apr 04 12:32:17 PM PDT 24
Peak memory 205056 kb
Host smart-f06df764-853b-4eae-aa1c-ab79fbb19751
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797478817 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.3797478817
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.3036262945
Short name T54
Test name
Test status
Simulation time 48785170024 ps
CPU time 80.71 seconds
Started Apr 04 12:32:30 PM PDT 24
Finished Apr 04 12:33:51 PM PDT 24
Peak memory 205452 kb
Host smart-359e23fc-1112-4fa2-a164-445b4f8f7fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036262945 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.3036262945
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.1732377118
Short name T237
Test name
Test status
Simulation time 4378283576 ps
CPU time 11.53 seconds
Started Apr 04 12:32:13 PM PDT 24
Finished Apr 04 12:32:25 PM PDT 24
Peak memory 221932 kb
Host smart-cd9712cd-5bd0-4a6c-9967-7405240a3cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732377118 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.1732377118
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.2894666991
Short name T55
Test name
Test status
Simulation time 11277101739 ps
CPU time 11.18 seconds
Started Apr 04 12:32:15 PM PDT 24
Finished Apr 04 12:32:26 PM PDT 24
Peak memory 214688 kb
Host smart-27e6fa01-d363-45eb-b8c9-af1e569fd024
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2894666991 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.2894666991
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.1134711825
Short name T205
Test name
Test status
Simulation time 106203208 ps
CPU time 0.74 seconds
Started Apr 04 12:32:14 PM PDT 24
Finished Apr 04 12:32:16 PM PDT 24
Peak memory 204952 kb
Host smart-fb0be69c-1225-4de6-9db2-ec7a00987e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134711825 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.1134711825
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.2959826502
Short name T194
Test name
Test status
Simulation time 2412832764 ps
CPU time 6.72 seconds
Started Apr 04 12:32:14 PM PDT 24
Finished Apr 04 12:32:21 PM PDT 24
Peak memory 205508 kb
Host smart-5ee07b87-ad1c-43ad-b24a-878756100b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959826502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.2959826502
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.3605521780
Short name T53
Test name
Test status
Simulation time 83104432 ps
CPU time 1.16 seconds
Started Apr 04 12:32:28 PM PDT 24
Finished Apr 04 12:32:30 PM PDT 24
Peak memory 228608 kb
Host smart-b8ed7b1b-e430-494f-abb6-56c4ed017523
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605521780 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.3605521780
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.92000896
Short name T157
Test name
Test status
Simulation time 55085786 ps
CPU time 0.68 seconds
Started Apr 04 12:32:54 PM PDT 24
Finished Apr 04 12:32:55 PM PDT 24
Peak memory 205108 kb
Host smart-952d6db2-15da-4aa4-9826-37eac57f18b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92000896 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.92000896
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.3410743793
Short name T163
Test name
Test status
Simulation time 68483433 ps
CPU time 0.81 seconds
Started Apr 04 12:32:55 PM PDT 24
Finished Apr 04 12:32:56 PM PDT 24
Peak memory 205096 kb
Host smart-c94bb7e9-006a-4e36-87ab-c36b954d98b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410743793 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.3410743793
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.2083040749
Short name T81
Test name
Test status
Simulation time 49193569 ps
CPU time 0.71 seconds
Started Apr 04 12:32:53 PM PDT 24
Finished Apr 04 12:32:54 PM PDT 24
Peak memory 205104 kb
Host smart-2f915817-794d-4472-91a8-ec2f1db74128
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083040749 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.2083040749
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.1076032935
Short name T78
Test name
Test status
Simulation time 50559855 ps
CPU time 0.74 seconds
Started Apr 04 12:33:03 PM PDT 24
Finished Apr 04 12:33:04 PM PDT 24
Peak memory 205176 kb
Host smart-bfa8238d-8979-4328-a692-7c68570bf20b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076032935 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.1076032935
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.837235730
Short name T219
Test name
Test status
Simulation time 47337792 ps
CPU time 0.74 seconds
Started Apr 04 12:33:14 PM PDT 24
Finished Apr 04 12:33:15 PM PDT 24
Peak memory 205140 kb
Host smart-cc514d32-7df2-4c56-92bc-c99e51e6e2b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837235730 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.837235730
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.3635991718
Short name T172
Test name
Test status
Simulation time 35442121 ps
CPU time 0.8 seconds
Started Apr 04 12:33:04 PM PDT 24
Finished Apr 04 12:33:05 PM PDT 24
Peak memory 205096 kb
Host smart-3e9dd864-e13a-4f40-8aa4-c63ee07a60f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635991718 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.3635991718
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.3860503357
Short name T154
Test name
Test status
Simulation time 30884087 ps
CPU time 0.74 seconds
Started Apr 04 12:33:03 PM PDT 24
Finished Apr 04 12:33:04 PM PDT 24
Peak memory 205092 kb
Host smart-d14a0426-35e0-4ecf-9de1-5ad53404e8bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860503357 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.3860503357
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.1550056994
Short name T30
Test name
Test status
Simulation time 17111278 ps
CPU time 0.76 seconds
Started Apr 04 12:33:12 PM PDT 24
Finished Apr 04 12:33:13 PM PDT 24
Peak memory 205048 kb
Host smart-8edeff45-2a76-43aa-9bda-f5563fad653e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550056994 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.1550056994
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.594903306
Short name T57
Test name
Test status
Simulation time 37129897 ps
CPU time 0.76 seconds
Started Apr 04 12:33:03 PM PDT 24
Finished Apr 04 12:33:04 PM PDT 24
Peak memory 205096 kb
Host smart-1b6d5e91-1b0a-4cca-ba1d-28fd136d43e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594903306 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.594903306
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.3469350544
Short name T152
Test name
Test status
Simulation time 59774947 ps
CPU time 0.71 seconds
Started Apr 04 12:33:07 PM PDT 24
Finished Apr 04 12:33:10 PM PDT 24
Peak memory 205084 kb
Host smart-87b7a5ac-1f55-425d-9115-f942a7373a0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469350544 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.3469350544
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_stress_all.302735597
Short name T36
Test name
Test status
Simulation time 3084247613 ps
CPU time 5.18 seconds
Started Apr 04 12:33:08 PM PDT 24
Finished Apr 04 12:33:14 PM PDT 24
Peak memory 205380 kb
Host smart-fb0296ff-d91d-47dd-8485-9e5279ca9b62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302735597 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.302735597
Directory /workspace/39.rv_dm_stress_all/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.1710574397
Short name T51
Test name
Test status
Simulation time 142881463 ps
CPU time 0.74 seconds
Started Apr 04 12:32:15 PM PDT 24
Finished Apr 04 12:32:17 PM PDT 24
Peak memory 205104 kb
Host smart-b7181970-fc54-4967-8085-9cfcdafc66a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710574397 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.1710574397
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.2154973748
Short name T61
Test name
Test status
Simulation time 3880682120 ps
CPU time 6.94 seconds
Started Apr 04 12:32:16 PM PDT 24
Finished Apr 04 12:32:23 PM PDT 24
Peak memory 205572 kb
Host smart-952e0329-15b1-4fe7-b74b-4bac59adbf2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154973748 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.2154973748
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.1835942356
Short name T58
Test name
Test status
Simulation time 2994532903 ps
CPU time 6.25 seconds
Started Apr 04 12:32:29 PM PDT 24
Finished Apr 04 12:32:35 PM PDT 24
Peak memory 205548 kb
Host smart-b9568177-fe35-4746-99d0-7d2e0a0c2169
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1835942356 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.1835942356
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.1895163896
Short name T191
Test name
Test status
Simulation time 37393954 ps
CPU time 0.7 seconds
Started Apr 04 12:32:34 PM PDT 24
Finished Apr 04 12:32:35 PM PDT 24
Peak memory 204956 kb
Host smart-0461bcc0-15bf-4ddc-ab86-f595428128cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895163896 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.1895163896
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.49799794
Short name T180
Test name
Test status
Simulation time 4355979281 ps
CPU time 7.47 seconds
Started Apr 04 12:32:21 PM PDT 24
Finished Apr 04 12:32:28 PM PDT 24
Peak memory 214644 kb
Host smart-2e0361fa-bd7e-46bb-8d09-b94b743ced7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49799794 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.49799794
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.1474548664
Short name T28
Test name
Test status
Simulation time 382576410 ps
CPU time 1.19 seconds
Started Apr 04 12:32:15 PM PDT 24
Finished Apr 04 12:32:16 PM PDT 24
Peak memory 229124 kb
Host smart-5c380ce6-b215-48af-92e0-c46fda5667e6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474548664 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.1474548664
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.1828330704
Short name T125
Test name
Test status
Simulation time 38298743 ps
CPU time 0.73 seconds
Started Apr 04 12:33:13 PM PDT 24
Finished Apr 04 12:33:14 PM PDT 24
Peak memory 205104 kb
Host smart-1ac57dae-0789-48b2-8848-960c711d8940
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828330704 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.1828330704
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.3276261881
Short name T153
Test name
Test status
Simulation time 49337777 ps
CPU time 0.72 seconds
Started Apr 04 12:33:14 PM PDT 24
Finished Apr 04 12:33:15 PM PDT 24
Peak memory 205136 kb
Host smart-60056c55-0c04-4149-8ee5-a68affab0561
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276261881 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.3276261881
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.3724186088
Short name T38
Test name
Test status
Simulation time 55112593 ps
CPU time 0.73 seconds
Started Apr 04 12:33:11 PM PDT 24
Finished Apr 04 12:33:13 PM PDT 24
Peak memory 205088 kb
Host smart-e46707df-914d-48bb-b2b9-2ad531b2eb93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724186088 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.3724186088
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.438240595
Short name T168
Test name
Test status
Simulation time 27609592 ps
CPU time 0.74 seconds
Started Apr 04 12:33:03 PM PDT 24
Finished Apr 04 12:33:04 PM PDT 24
Peak memory 204988 kb
Host smart-31410004-a6b3-4170-bc8b-9c125b3add3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438240595 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.438240595
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.3602480800
Short name T175
Test name
Test status
Simulation time 24272694 ps
CPU time 0.7 seconds
Started Apr 04 12:33:09 PM PDT 24
Finished Apr 04 12:33:10 PM PDT 24
Peak memory 205116 kb
Host smart-4202111e-e165-421c-8762-de31787500ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602480800 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.3602480800
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.1873356412
Short name T223
Test name
Test status
Simulation time 30391898 ps
CPU time 0.75 seconds
Started Apr 04 12:33:03 PM PDT 24
Finished Apr 04 12:33:04 PM PDT 24
Peak memory 204992 kb
Host smart-9417f91d-3dbe-42ba-8a11-a7a8d6c766a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873356412 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.1873356412
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.2168159609
Short name T167
Test name
Test status
Simulation time 19401349 ps
CPU time 0.76 seconds
Started Apr 04 12:33:04 PM PDT 24
Finished Apr 04 12:33:04 PM PDT 24
Peak memory 205044 kb
Host smart-3e2c19cf-ae7c-44b0-964a-ac4220ce3eca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168159609 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.2168159609
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.215939901
Short name T176
Test name
Test status
Simulation time 35614910 ps
CPU time 0.82 seconds
Started Apr 04 12:33:08 PM PDT 24
Finished Apr 04 12:33:10 PM PDT 24
Peak memory 205140 kb
Host smart-cfb57726-edda-4318-8b0b-7e10979b4c33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215939901 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.215939901
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.812053098
Short name T217
Test name
Test status
Simulation time 21239878 ps
CPU time 0.77 seconds
Started Apr 04 12:33:20 PM PDT 24
Finished Apr 04 12:33:23 PM PDT 24
Peak memory 205140 kb
Host smart-d2ea224e-35ca-4090-87cd-1119a3217623
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812053098 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.812053098
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_stress_all.580002054
Short name T15
Test name
Test status
Simulation time 1671647823 ps
CPU time 6.1 seconds
Started Apr 04 12:33:19 PM PDT 24
Finished Apr 04 12:33:28 PM PDT 24
Peak memory 205232 kb
Host smart-9244e262-dae0-4ea2-8d32-cc928f6469dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580002054 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.580002054
Directory /workspace/48.rv_dm_stress_all/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.3204202077
Short name T162
Test name
Test status
Simulation time 23161021 ps
CPU time 0.74 seconds
Started Apr 04 12:33:17 PM PDT 24
Finished Apr 04 12:33:18 PM PDT 24
Peak memory 205056 kb
Host smart-809be5a9-0837-4a70-b9e5-94f4f19808a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204202077 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.3204202077
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.238084617
Short name T222
Test name
Test status
Simulation time 131284772 ps
CPU time 0.7 seconds
Started Apr 04 12:32:13 PM PDT 24
Finished Apr 04 12:32:14 PM PDT 24
Peak memory 205108 kb
Host smart-591da34e-a7b8-410c-b7f7-ed447b0218a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238084617 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.238084617
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.3399087716
Short name T21
Test name
Test status
Simulation time 13320997047 ps
CPU time 42.74 seconds
Started Apr 04 12:32:16 PM PDT 24
Finished Apr 04 12:32:59 PM PDT 24
Peak memory 213732 kb
Host smart-5ed908f4-a713-4ec4-a32f-0d8082b96541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399087716 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.3399087716
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.3902860980
Short name T12
Test name
Test status
Simulation time 4765667522 ps
CPU time 9.68 seconds
Started Apr 04 12:32:15 PM PDT 24
Finished Apr 04 12:32:26 PM PDT 24
Peak memory 213756 kb
Host smart-8fecba9c-2b9c-4371-960a-af75a8ccabe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902860980 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.3902860980
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.1246264826
Short name T230
Test name
Test status
Simulation time 15502412686 ps
CPU time 54 seconds
Started Apr 04 12:33:23 PM PDT 24
Finished Apr 04 12:34:17 PM PDT 24
Peak memory 215144 kb
Host smart-5a847884-3606-4a16-ac77-690e7bafc7d2
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1246264826 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t
l_access.1246264826
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.1638088478
Short name T203
Test name
Test status
Simulation time 7221355983 ps
CPU time 25.28 seconds
Started Apr 04 12:32:18 PM PDT 24
Finished Apr 04 12:32:43 PM PDT 24
Peak memory 205612 kb
Host smart-c23e42e5-3dd2-49d4-9c3e-f94206100d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638088478 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.1638088478
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.3010183707
Short name T169
Test name
Test status
Simulation time 60298295 ps
CPU time 0.72 seconds
Started Apr 04 12:32:22 PM PDT 24
Finished Apr 04 12:32:23 PM PDT 24
Peak memory 204996 kb
Host smart-ac9363e4-bc7c-4702-bdd7-f80918547e9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010183707 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.3010183707
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.4023977012
Short name T130
Test name
Test status
Simulation time 39667221859 ps
CPU time 116.31 seconds
Started Apr 04 12:32:29 PM PDT 24
Finished Apr 04 12:34:25 PM PDT 24
Peak memory 213712 kb
Host smart-60527fe1-a259-48c2-b10d-ffc11ae97769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023977012 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.4023977012
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.2753424046
Short name T229
Test name
Test status
Simulation time 15390792536 ps
CPU time 43.25 seconds
Started Apr 04 12:32:18 PM PDT 24
Finished Apr 04 12:33:02 PM PDT 24
Peak memory 213748 kb
Host smart-f98d9828-be0c-451d-8ddd-2ca05a11e9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753424046 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.2753424046
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.638182463
Short name T238
Test name
Test status
Simulation time 3512469205 ps
CPU time 7.63 seconds
Started Apr 04 12:32:18 PM PDT 24
Finished Apr 04 12:32:26 PM PDT 24
Peak memory 205560 kb
Host smart-64033cb1-30b2-4e55-a7c4-9bd41d187c0a
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=638182463 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_tl
_access.638182463
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.2879793779
Short name T190
Test name
Test status
Simulation time 701428704 ps
CPU time 3.5 seconds
Started Apr 04 12:32:17 PM PDT 24
Finished Apr 04 12:32:20 PM PDT 24
Peak memory 205444 kb
Host smart-f9a9164c-27c3-4a9f-b832-771c9bf90a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879793779 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.2879793779
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.262449569
Short name T160
Test name
Test status
Simulation time 127396787 ps
CPU time 0.71 seconds
Started Apr 04 12:32:22 PM PDT 24
Finished Apr 04 12:32:23 PM PDT 24
Peak memory 205116 kb
Host smart-05d121f7-735f-43f4-b925-93b022554552
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262449569 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.262449569
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.528811103
Short name T212
Test name
Test status
Simulation time 9962655613 ps
CPU time 13.13 seconds
Started Apr 04 12:32:21 PM PDT 24
Finished Apr 04 12:32:34 PM PDT 24
Peak memory 215780 kb
Host smart-884fa41d-8901-4392-b786-0dc415f6b199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528811103 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.528811103
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.4180000884
Short name T210
Test name
Test status
Simulation time 1696661052 ps
CPU time 3.86 seconds
Started Apr 04 12:32:29 PM PDT 24
Finished Apr 04 12:32:33 PM PDT 24
Peak memory 205428 kb
Host smart-10ecc756-fb05-4966-af18-c72fcf42fc03
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4180000884 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.4180000884
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.1568250293
Short name T173
Test name
Test status
Simulation time 34992715 ps
CPU time 0.72 seconds
Started Apr 04 12:32:23 PM PDT 24
Finished Apr 04 12:32:24 PM PDT 24
Peak memory 204988 kb
Host smart-4b21ae37-6ac8-4921-bedd-4bdd19010ed7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568250293 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.1568250293
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.348855152
Short name T196
Test name
Test status
Simulation time 798535019 ps
CPU time 3.98 seconds
Started Apr 04 12:32:22 PM PDT 24
Finished Apr 04 12:32:26 PM PDT 24
Peak memory 205412 kb
Host smart-cd8ab525-6de6-42e7-b0c6-1396927f5bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348855152 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.348855152
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.19170755
Short name T220
Test name
Test status
Simulation time 1614670076 ps
CPU time 9.01 seconds
Started Apr 04 12:32:31 PM PDT 24
Finished Apr 04 12:32:40 PM PDT 24
Peak memory 205316 kb
Host smart-5ac07170-0310-4dd7-a42f-592b82e4a8e9
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=19170755 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_tl_
access.19170755
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.1228377408
Short name T184
Test name
Test status
Simulation time 340869644 ps
CPU time 2.3 seconds
Started Apr 04 12:32:23 PM PDT 24
Finished Apr 04 12:32:26 PM PDT 24
Peak memory 205288 kb
Host smart-75d42c9a-3dcc-462c-a4c3-7e498f7672ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228377408 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.1228377408
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.1274027574
Short name T171
Test name
Test status
Simulation time 32501396 ps
CPU time 0.73 seconds
Started Apr 04 12:32:33 PM PDT 24
Finished Apr 04 12:32:34 PM PDT 24
Peak memory 205072 kb
Host smart-eb0425ab-ee8c-428c-ae3b-0444754b26ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274027574 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.1274027574
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.3250148182
Short name T206
Test name
Test status
Simulation time 21665091829 ps
CPU time 45.8 seconds
Started Apr 04 12:32:32 PM PDT 24
Finished Apr 04 12:33:18 PM PDT 24
Peak memory 213740 kb
Host smart-bff8986e-e9cf-4415-afe7-6fd7a07dca0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250148182 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.3250148182
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.3058487874
Short name T192
Test name
Test status
Simulation time 2850149256 ps
CPU time 13.43 seconds
Started Apr 04 12:32:23 PM PDT 24
Finished Apr 04 12:32:37 PM PDT 24
Peak memory 205488 kb
Host smart-e1d2b1a8-89de-4640-a414-561d982ecbc0
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3058487874 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t
l_access.3058487874
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.2630312228
Short name T228
Test name
Test status
Simulation time 5334064392 ps
CPU time 10.53 seconds
Started Apr 04 12:32:31 PM PDT 24
Finished Apr 04 12:32:41 PM PDT 24
Peak memory 205476 kb
Host smart-5b933f28-a66f-414d-8d1c-7dd5a0144b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630312228 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.2630312228
Directory /workspace/9.rv_dm_sba_tl_access/latest
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