Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
81.07 94.49 80.19 87.69 75.64 83.83 98.52 47.10


Total test records in report: 378
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html
T274 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.38416152 Apr 15 12:30:42 PM PDT 24 Apr 15 12:30:46 PM PDT 24 722821873 ps
T99 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3800527012 Apr 15 12:30:39 PM PDT 24 Apr 15 12:30:44 PM PDT 24 76442713 ps
T275 /workspace/coverage/cover_reg_top/16.rv_dm_tap_fsm_rand_reset.3000665071 Apr 15 12:30:42 PM PDT 24 Apr 15 12:30:58 PM PDT 24 12218516182 ps
T106 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3718117978 Apr 15 12:30:42 PM PDT 24 Apr 15 12:30:45 PM PDT 24 61493758 ps
T116 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.1032589011 Apr 15 12:30:44 PM PDT 24 Apr 15 12:30:50 PM PDT 24 509501758 ps
T276 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.4122792019 Apr 15 12:30:38 PM PDT 24 Apr 15 12:30:41 PM PDT 24 60105165 ps
T100 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.331182773 Apr 15 12:30:35 PM PDT 24 Apr 15 12:30:40 PM PDT 24 162204558 ps
T277 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.4166398574 Apr 15 12:30:32 PM PDT 24 Apr 15 12:30:35 PM PDT 24 949443899 ps
T278 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3948452876 Apr 15 12:30:34 PM PDT 24 Apr 15 12:30:39 PM PDT 24 638755623 ps
T279 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.4119308339 Apr 15 12:30:36 PM PDT 24 Apr 15 12:30:39 PM PDT 24 527145851 ps
T280 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3064579347 Apr 15 12:30:46 PM PDT 24 Apr 15 12:30:55 PM PDT 24 5679630707 ps
T281 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.3895559518 Apr 15 12:30:43 PM PDT 24 Apr 15 12:30:46 PM PDT 24 500223015 ps
T282 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.2922219665 Apr 15 12:30:37 PM PDT 24 Apr 15 12:30:42 PM PDT 24 162085743 ps
T283 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.4138816431 Apr 15 12:31:12 PM PDT 24 Apr 15 12:31:14 PM PDT 24 157547590 ps
T284 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.3308287322 Apr 15 12:30:46 PM PDT 24 Apr 15 12:30:50 PM PDT 24 239594667 ps
T132 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.464503265 Apr 15 12:30:44 PM PDT 24 Apr 15 12:31:05 PM PDT 24 1858542784 ps
T285 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.1463138403 Apr 15 12:30:48 PM PDT 24 Apr 15 12:30:59 PM PDT 24 1244173160 ps
T107 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.2671455864 Apr 15 12:30:51 PM PDT 24 Apr 15 12:30:54 PM PDT 24 39808523 ps
T286 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.1139327200 Apr 15 12:30:46 PM PDT 24 Apr 15 12:30:50 PM PDT 24 46006641 ps
T287 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3681387384 Apr 15 12:31:05 PM PDT 24 Apr 15 12:31:10 PM PDT 24 902234949 ps
T288 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.2127473891 Apr 15 12:30:37 PM PDT 24 Apr 15 12:30:39 PM PDT 24 106775286 ps
T101 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.1021224463 Apr 15 12:30:38 PM PDT 24 Apr 15 12:30:44 PM PDT 24 313288222 ps
T289 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.2221548896 Apr 15 12:30:38 PM PDT 24 Apr 15 12:30:41 PM PDT 24 123238113 ps
T290 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.1067834942 Apr 15 12:30:46 PM PDT 24 Apr 15 12:31:11 PM PDT 24 5544686490 ps
T291 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.487544469 Apr 15 12:30:46 PM PDT 24 Apr 15 12:30:48 PM PDT 24 26946770 ps
T292 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.4009735613 Apr 15 12:30:32 PM PDT 24 Apr 15 12:30:34 PM PDT 24 67586974 ps
T293 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.3503350919 Apr 15 12:30:48 PM PDT 24 Apr 15 12:30:50 PM PDT 24 663292027 ps
T294 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1983254662 Apr 15 12:30:41 PM PDT 24 Apr 15 12:30:45 PM PDT 24 816445326 ps
T295 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3108483434 Apr 15 12:30:51 PM PDT 24 Apr 15 12:30:54 PM PDT 24 621380301 ps
T108 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2861776325 Apr 15 12:30:36 PM PDT 24 Apr 15 12:31:53 PM PDT 24 14892508887 ps
T102 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.132783149 Apr 15 12:30:28 PM PDT 24 Apr 15 12:30:31 PM PDT 24 68425272 ps
T296 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.1637446374 Apr 15 12:30:39 PM PDT 24 Apr 15 12:30:51 PM PDT 24 4026045330 ps
T103 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2022072808 Apr 15 12:30:41 PM PDT 24 Apr 15 12:30:45 PM PDT 24 413778398 ps
T117 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.2667228353 Apr 15 12:30:47 PM PDT 24 Apr 15 12:30:55 PM PDT 24 144991899 ps
T297 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.895399826 Apr 15 12:30:37 PM PDT 24 Apr 15 12:30:46 PM PDT 24 389458666 ps
T298 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2095472539 Apr 15 12:30:48 PM PDT 24 Apr 15 12:30:51 PM PDT 24 68028357 ps
T299 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.635022058 Apr 15 12:30:49 PM PDT 24 Apr 15 12:30:51 PM PDT 24 1582082187 ps
T300 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.679717695 Apr 15 12:30:33 PM PDT 24 Apr 15 12:30:35 PM PDT 24 83018018 ps
T301 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2774917399 Apr 15 12:30:38 PM PDT 24 Apr 15 12:30:40 PM PDT 24 24219727 ps
T94 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.1722927076 Apr 15 12:30:36 PM PDT 24 Apr 15 12:30:42 PM PDT 24 2528159310 ps
T302 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.1656159243 Apr 15 12:30:42 PM PDT 24 Apr 15 12:30:45 PM PDT 24 95697474 ps
T303 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.3690948081 Apr 15 12:30:46 PM PDT 24 Apr 15 12:31:14 PM PDT 24 718033042 ps
T133 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.571123558 Apr 15 12:30:42 PM PDT 24 Apr 15 12:31:03 PM PDT 24 4148952366 ps
T110 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1799603774 Apr 15 12:30:39 PM PDT 24 Apr 15 12:30:42 PM PDT 24 118139759 ps
T304 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.1287328481 Apr 15 12:30:38 PM PDT 24 Apr 15 12:30:41 PM PDT 24 43590404 ps
T305 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3897435491 Apr 15 12:31:09 PM PDT 24 Apr 15 12:31:11 PM PDT 24 27230215 ps
T124 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.3874280184 Apr 15 12:30:41 PM PDT 24 Apr 15 12:30:47 PM PDT 24 196212661 ps
T306 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.1825980090 Apr 15 12:30:30 PM PDT 24 Apr 15 12:30:32 PM PDT 24 92085867 ps
T307 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1193890838 Apr 15 12:30:50 PM PDT 24 Apr 15 12:30:52 PM PDT 24 195119476 ps
T308 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.112181073 Apr 15 12:31:02 PM PDT 24 Apr 15 12:31:08 PM PDT 24 80222375 ps
T111 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.3902049042 Apr 15 12:30:47 PM PDT 24 Apr 15 12:30:50 PM PDT 24 83519104 ps
T309 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.577350632 Apr 15 12:30:41 PM PDT 24 Apr 15 12:30:43 PM PDT 24 25450958 ps
T310 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.59270102 Apr 15 12:30:50 PM PDT 24 Apr 15 12:30:58 PM PDT 24 424567309 ps
T311 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3348312105 Apr 15 12:30:52 PM PDT 24 Apr 15 12:30:55 PM PDT 24 134584917 ps
T312 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.4107612894 Apr 15 12:31:04 PM PDT 24 Apr 15 12:31:20 PM PDT 24 776308781 ps
T313 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.2519611529 Apr 15 12:30:51 PM PDT 24 Apr 15 12:30:56 PM PDT 24 262500523 ps
T314 /workspace/coverage/cover_reg_top/15.rv_dm_tap_fsm_rand_reset.2540347902 Apr 15 12:30:41 PM PDT 24 Apr 15 12:31:07 PM PDT 24 13757962294 ps
T315 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.1539274424 Apr 15 12:30:41 PM PDT 24 Apr 15 12:31:02 PM PDT 24 844297745 ps
T316 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3157843465 Apr 15 12:30:49 PM PDT 24 Apr 15 12:30:52 PM PDT 24 84393320 ps
T317 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.4030842553 Apr 15 12:30:44 PM PDT 24 Apr 15 12:30:48 PM PDT 24 100227963 ps
T95 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2208374269 Apr 15 12:30:39 PM PDT 24 Apr 15 12:30:43 PM PDT 24 1379542899 ps
T318 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2655406708 Apr 15 12:30:37 PM PDT 24 Apr 15 12:30:40 PM PDT 24 56145837 ps
T319 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.1622764170 Apr 15 12:30:34 PM PDT 24 Apr 15 12:30:36 PM PDT 24 47590962 ps
T320 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.1981283727 Apr 15 12:30:34 PM PDT 24 Apr 15 12:30:48 PM PDT 24 5960626247 ps
T321 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.3147800634 Apr 15 12:30:37 PM PDT 24 Apr 15 12:30:39 PM PDT 24 51011363 ps
T322 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3962055238 Apr 15 12:30:41 PM PDT 24 Apr 15 12:30:51 PM PDT 24 3745706560 ps
T323 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.1448140969 Apr 15 12:30:43 PM PDT 24 Apr 15 12:30:47 PM PDT 24 218985908 ps
T324 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.596300519 Apr 15 12:30:47 PM PDT 24 Apr 15 12:30:58 PM PDT 24 532999662 ps
T325 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.3380557436 Apr 15 12:30:44 PM PDT 24 Apr 15 12:30:49 PM PDT 24 1615365272 ps
T326 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.2235001706 Apr 15 12:30:49 PM PDT 24 Apr 15 12:30:55 PM PDT 24 241768653 ps
T327 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.2948795750 Apr 15 12:30:51 PM PDT 24 Apr 15 12:30:54 PM PDT 24 113963625 ps
T328 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1524838166 Apr 15 12:30:54 PM PDT 24 Apr 15 12:30:56 PM PDT 24 39521232 ps
T329 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.4231900185 Apr 15 12:30:43 PM PDT 24 Apr 15 12:30:45 PM PDT 24 50733680 ps
T330 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2656535707 Apr 15 12:30:56 PM PDT 24 Apr 15 12:30:58 PM PDT 24 21106210 ps
T331 /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.2167922854 Apr 15 12:30:39 PM PDT 24 Apr 15 12:31:07 PM PDT 24 16395149234 ps
T332 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.1428677869 Apr 15 12:30:44 PM PDT 24 Apr 15 12:30:47 PM PDT 24 520371614 ps
T333 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1802182089 Apr 15 12:30:34 PM PDT 24 Apr 15 12:30:36 PM PDT 24 68760833 ps
T334 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1584291149 Apr 15 12:30:44 PM PDT 24 Apr 15 12:30:48 PM PDT 24 125800649 ps
T335 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3065071773 Apr 15 12:30:37 PM PDT 24 Apr 15 12:30:40 PM PDT 24 329718563 ps
T336 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3651913118 Apr 15 12:30:44 PM PDT 24 Apr 15 12:30:46 PM PDT 24 74363077 ps
T337 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3260739711 Apr 15 12:30:37 PM PDT 24 Apr 15 12:32:39 PM PDT 24 33959789284 ps
T338 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.1547628331 Apr 15 12:31:02 PM PDT 24 Apr 15 12:31:11 PM PDT 24 1771341987 ps
T112 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.1671535211 Apr 15 12:30:46 PM PDT 24 Apr 15 12:30:48 PM PDT 24 208693815 ps
T113 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.221706025 Apr 15 12:30:34 PM PDT 24 Apr 15 12:30:37 PM PDT 24 174829985 ps
T339 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.1301088233 Apr 15 12:30:50 PM PDT 24 Apr 15 12:30:54 PM PDT 24 163748543 ps
T340 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.3091344901 Apr 15 12:30:36 PM PDT 24 Apr 15 12:30:41 PM PDT 24 609077207 ps
T341 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.2920995177 Apr 15 12:30:43 PM PDT 24 Apr 15 12:30:49 PM PDT 24 1563928313 ps
T342 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.822341693 Apr 15 12:30:33 PM PDT 24 Apr 15 12:30:43 PM PDT 24 2343344737 ps
T343 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2047982188 Apr 15 12:30:36 PM PDT 24 Apr 15 12:30:38 PM PDT 24 117209090 ps
T344 /workspace/coverage/cover_reg_top/10.rv_dm_tap_fsm_rand_reset.3986749298 Apr 15 12:30:54 PM PDT 24 Apr 15 12:31:06 PM PDT 24 13036784879 ps
T345 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3717041550 Apr 15 12:30:38 PM PDT 24 Apr 15 12:30:49 PM PDT 24 4485233805 ps
T346 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2813368818 Apr 15 12:30:36 PM PDT 24 Apr 15 12:30:38 PM PDT 24 14309725 ps
T114 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.2104614508 Apr 15 12:30:51 PM PDT 24 Apr 15 12:30:53 PM PDT 24 300735050 ps
T347 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2702983140 Apr 15 12:30:43 PM PDT 24 Apr 15 12:30:46 PM PDT 24 163359556 ps
T348 /workspace/coverage/cover_reg_top/35.rv_dm_tap_fsm_rand_reset.3803875905 Apr 15 12:31:10 PM PDT 24 Apr 15 12:31:36 PM PDT 24 6363609320 ps
T349 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.2937161532 Apr 15 12:30:54 PM PDT 24 Apr 15 12:30:56 PM PDT 24 173613826 ps
T350 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.4014944793 Apr 15 12:30:49 PM PDT 24 Apr 15 12:30:54 PM PDT 24 318835458 ps
T351 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1936298996 Apr 15 12:30:42 PM PDT 24 Apr 15 12:30:44 PM PDT 24 161944230 ps
T60 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.2908052804 Apr 15 12:30:46 PM PDT 24 Apr 15 12:30:49 PM PDT 24 403268033 ps
T352 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3663540552 Apr 15 12:30:43 PM PDT 24 Apr 15 12:30:48 PM PDT 24 1997005569 ps
T109 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.3674054942 Apr 15 12:30:54 PM PDT 24 Apr 15 12:30:57 PM PDT 24 443345308 ps
T353 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.1338392521 Apr 15 12:30:37 PM PDT 24 Apr 15 12:30:41 PM PDT 24 37963689 ps
T354 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2221858908 Apr 15 12:30:42 PM PDT 24 Apr 15 12:30:44 PM PDT 24 369307132 ps
T355 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.3421026013 Apr 15 12:30:35 PM PDT 24 Apr 15 12:30:46 PM PDT 24 806802522 ps
T356 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.3541400383 Apr 15 12:30:43 PM PDT 24 Apr 15 12:30:46 PM PDT 24 111027282 ps
T357 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3016221859 Apr 15 12:30:38 PM PDT 24 Apr 15 12:30:40 PM PDT 24 128950777 ps
T358 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.3906719678 Apr 15 12:30:43 PM PDT 24 Apr 15 12:30:46 PM PDT 24 326815082 ps
T359 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1772402502 Apr 15 12:30:34 PM PDT 24 Apr 15 12:31:01 PM PDT 24 540535784 ps
T360 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2700752936 Apr 15 12:30:46 PM PDT 24 Apr 15 12:30:51 PM PDT 24 83968057 ps
T361 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.4152126780 Apr 15 12:30:33 PM PDT 24 Apr 15 12:30:36 PM PDT 24 856167578 ps
T362 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.952685908 Apr 15 12:31:14 PM PDT 24 Apr 15 12:31:19 PM PDT 24 825038870 ps
T363 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.1292858052 Apr 15 12:30:48 PM PDT 24 Apr 15 12:30:54 PM PDT 24 2058950571 ps
T364 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1223714731 Apr 15 12:30:50 PM PDT 24 Apr 15 12:30:55 PM PDT 24 1106175026 ps
T365 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.157848978 Apr 15 12:30:47 PM PDT 24 Apr 15 12:31:13 PM PDT 24 11906135120 ps
T366 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.76189078 Apr 15 12:30:40 PM PDT 24 Apr 15 12:30:48 PM PDT 24 2789614057 ps
T367 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2051072714 Apr 15 12:30:37 PM PDT 24 Apr 15 12:30:48 PM PDT 24 2702316099 ps
T368 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2683809226 Apr 15 12:31:05 PM PDT 24 Apr 15 12:31:10 PM PDT 24 2876252035 ps
T369 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.3846601897 Apr 15 12:31:04 PM PDT 24 Apr 15 12:31:10 PM PDT 24 1232767803 ps
T370 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.4259598178 Apr 15 12:30:43 PM PDT 24 Apr 15 12:30:50 PM PDT 24 50747419 ps
T371 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3390942954 Apr 15 12:30:38 PM PDT 24 Apr 15 12:30:43 PM PDT 24 161785446 ps
T372 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1207368158 Apr 15 12:30:29 PM PDT 24 Apr 15 12:30:55 PM PDT 24 11521594616 ps
T373 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.2407963450 Apr 15 12:30:42 PM PDT 24 Apr 15 12:30:45 PM PDT 24 121580682 ps
T130 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.3421954381 Apr 15 12:30:43 PM PDT 24 Apr 15 12:31:01 PM PDT 24 737563011 ps
T374 /workspace/coverage/cover_reg_top/20.rv_dm_tap_fsm_rand_reset.3766469849 Apr 15 12:31:10 PM PDT 24 Apr 15 12:31:23 PM PDT 24 10775002897 ps
T375 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.3537755944 Apr 15 12:30:33 PM PDT 24 Apr 15 12:30:42 PM PDT 24 815151729 ps
T376 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.974859613 Apr 15 12:30:46 PM PDT 24 Apr 15 12:30:49 PM PDT 24 186961380 ps
T377 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.4094726680 Apr 15 12:30:42 PM PDT 24 Apr 15 12:30:46 PM PDT 24 438614349 ps
T378 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.849285871 Apr 15 12:30:47 PM PDT 24 Apr 15 12:30:53 PM PDT 24 209193034 ps

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.2744080655
Short name T13
Test name
Test status
Simulation time 3016459567 ps
CPU time 10.39 seconds
Started Apr 15 12:35:18 PM PDT 24
Finished Apr 15 12:35:29 PM PDT 24
Peak memory 205480 kb
Host smart-11c437ac-c34d-413e-8c32-2be57c559bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744080655 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.2744080655
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all.3362678467
Short name T6
Test name
Test status
Simulation time 8917398540 ps
CPU time 7.86 seconds
Started Apr 15 12:35:01 PM PDT 24
Finished Apr 15 12:35:10 PM PDT 24
Peak memory 205336 kb
Host smart-cf9f138c-d968-4ed9-a5d1-018095aeefd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362678467 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.3362678467
Directory /workspace/0.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.1681073911
Short name T67
Test name
Test status
Simulation time 215268991 ps
CPU time 3.18 seconds
Started Apr 15 12:30:43 PM PDT 24
Finished Apr 15 12:30:47 PM PDT 24
Peak memory 212984 kb
Host smart-5d448c8d-8861-40aa-8100-7cf22df7d2bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681073911 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.1681073911
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/4.rv_dm_stress_all.4087951279
Short name T17
Test name
Test status
Simulation time 11557108235 ps
CPU time 12.55 seconds
Started Apr 15 12:35:14 PM PDT 24
Finished Apr 15 12:35:27 PM PDT 24
Peak memory 205316 kb
Host smart-87f40f0e-1cbd-4f25-a87b-2ace0cbc3d43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087951279 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.4087951279
Directory /workspace/4.rv_dm_stress_all/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.3158091297
Short name T28
Test name
Test status
Simulation time 51485023 ps
CPU time 0.7 seconds
Started Apr 15 12:35:47 PM PDT 24
Finished Apr 15 12:35:49 PM PDT 24
Peak memory 205020 kb
Host smart-71bcaa80-4adc-47f7-a34c-cb658bfa3c5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158091297 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.3158091297
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.2955215683
Short name T38
Test name
Test status
Simulation time 17054438918 ps
CPU time 14.07 seconds
Started Apr 15 12:30:30 PM PDT 24
Finished Apr 15 12:30:46 PM PDT 24
Peak memory 220616 kb
Host smart-707a992c-9ae0-43cd-8337-82445b731430
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955215683 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.2955215683
Directory /workspace/0.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.1777665354
Short name T76
Test name
Test status
Simulation time 1038770863 ps
CPU time 17.97 seconds
Started Apr 15 12:30:49 PM PDT 24
Finished Apr 15 12:31:08 PM PDT 24
Peak memory 212712 kb
Host smart-d302b442-14f3-45f2-ac0c-1837139dac87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777665354 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.1777665354
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.541558517
Short name T87
Test name
Test status
Simulation time 2444927977 ps
CPU time 68.69 seconds
Started Apr 15 12:30:37 PM PDT 24
Finished Apr 15 12:31:48 PM PDT 24
Peak memory 217412 kb
Host smart-48e15eae-2dc8-42f4-93e6-713cd863a285
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541558517 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.rv_dm_csr_aliasing.541558517
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/default/46.rv_dm_stress_all.1065683405
Short name T33
Test name
Test status
Simulation time 1886199253 ps
CPU time 3.92 seconds
Started Apr 15 12:35:46 PM PDT 24
Finished Apr 15 12:35:51 PM PDT 24
Peak memory 205276 kb
Host smart-3701bfab-1801-41cf-99d8-42413ad3715c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065683405 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.1065683405
Directory /workspace/46.rv_dm_stress_all/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.759032929
Short name T25
Test name
Test status
Simulation time 382048331 ps
CPU time 1.31 seconds
Started Apr 15 12:35:12 PM PDT 24
Finished Apr 15 12:35:14 PM PDT 24
Peak memory 229336 kb
Host smart-798d7c24-632b-408e-ba8d-37cdf65cd227
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759032929 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.759032929
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.1055650930
Short name T179
Test name
Test status
Simulation time 1933648769 ps
CPU time 5.03 seconds
Started Apr 15 12:35:19 PM PDT 24
Finished Apr 15 12:35:25 PM PDT 24
Peak memory 213572 kb
Host smart-ef6e067f-77e0-4da3-8f16-57f7bc5a102e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1055650930 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.1055650930
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.2440155322
Short name T122
Test name
Test status
Simulation time 1058951046 ps
CPU time 20.01 seconds
Started Apr 15 12:30:37 PM PDT 24
Finished Apr 15 12:30:58 PM PDT 24
Peak memory 213256 kb
Host smart-81725d14-86c5-439b-a682-9dd9285f24e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440155322 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.2440155322
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.1131276345
Short name T22
Test name
Test status
Simulation time 29375179205 ps
CPU time 85.93 seconds
Started Apr 15 12:35:21 PM PDT 24
Finished Apr 15 12:36:47 PM PDT 24
Peak memory 213732 kb
Host smart-d8a760d6-5d3e-4a20-af20-7c8f6f2209b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131276345 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.1131276345
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.4176028160
Short name T30
Test name
Test status
Simulation time 103219235 ps
CPU time 0.78 seconds
Started Apr 15 12:35:00 PM PDT 24
Finished Apr 15 12:35:02 PM PDT 24
Peak memory 213256 kb
Host smart-c4a9ae59-3397-4776-a7ac-228b51c45f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176028160 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.4176028160
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.2058976791
Short name T55
Test name
Test status
Simulation time 342487902 ps
CPU time 0.9 seconds
Started Apr 15 12:35:03 PM PDT 24
Finished Apr 15 12:35:04 PM PDT 24
Peak memory 205044 kb
Host smart-c27245e8-fb6c-43ce-9cb4-871e0982bf85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058976791 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.2058976791
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/cover_reg_top/27.rv_dm_tap_fsm_rand_reset.392699857
Short name T37
Test name
Test status
Simulation time 29152379724 ps
CPU time 17.66 seconds
Started Apr 15 12:30:55 PM PDT 24
Finished Apr 15 12:31:13 PM PDT 24
Peak memory 219508 kb
Host smart-d5ded955-d580-4756-8a7d-70e09b1e1cdf
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392699857 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 27.rv_dm_tap_fsm_rand_reset.392699857
Directory /workspace/27.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.933650037
Short name T53
Test name
Test status
Simulation time 243682199 ps
CPU time 1.55 seconds
Started Apr 15 12:35:01 PM PDT 24
Finished Apr 15 12:35:04 PM PDT 24
Peak memory 205300 kb
Host smart-8216fa2b-341e-4cfd-afc1-09a8578e0f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933650037 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.933650037
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.1259596028
Short name T31
Test name
Test status
Simulation time 85820476 ps
CPU time 1.01 seconds
Started Apr 15 12:35:01 PM PDT 24
Finished Apr 15 12:35:03 PM PDT 24
Peak memory 204984 kb
Host smart-8f931760-b8ea-45c9-b0a4-02d87dd72e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259596028 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.1259596028
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.2036970162
Short name T245
Test name
Test status
Simulation time 45581149 ps
CPU time 0.69 seconds
Started Apr 15 12:30:54 PM PDT 24
Finished Apr 15 12:30:55 PM PDT 24
Peak memory 204396 kb
Host smart-fc145190-ec21-4d34-921a-4ee99d48c906
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036970162 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.
2036970162
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.234921371
Short name T126
Test name
Test status
Simulation time 3831545551 ps
CPU time 15.31 seconds
Started Apr 15 12:30:44 PM PDT 24
Finished Apr 15 12:31:00 PM PDT 24
Peak memory 213104 kb
Host smart-5cc9c86d-824a-49a4-a935-6653956a3ec0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234921371 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.234921371
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.377071843
Short name T127
Test name
Test status
Simulation time 2102984161 ps
CPU time 19.53 seconds
Started Apr 15 12:31:11 PM PDT 24
Finished Apr 15 12:31:31 PM PDT 24
Peak memory 212940 kb
Host smart-c39b4a38-7123-46fb-b226-2aad8820bd47
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377071843 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.377071843
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1160581230
Short name T41
Test name
Test status
Simulation time 1616202370 ps
CPU time 7.74 seconds
Started Apr 15 12:30:33 PM PDT 24
Finished Apr 15 12:30:42 PM PDT 24
Peak memory 204840 kb
Host smart-241eaf81-d2ff-44c9-9000-00473a263d58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160581230 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.1160581230
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2208374269
Short name T95
Test name
Test status
Simulation time 1379542899 ps
CPU time 2.67 seconds
Started Apr 15 12:30:39 PM PDT 24
Finished Apr 15 12:30:43 PM PDT 24
Peak memory 204744 kb
Host smart-58131283-8c2d-4e56-b2ed-f60bc97913ac
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208374269 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.2208374269
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.3674054942
Short name T109
Test name
Test status
Simulation time 443345308 ps
CPU time 2.2 seconds
Started Apr 15 12:30:54 PM PDT 24
Finished Apr 15 12:30:57 PM PDT 24
Peak memory 212888 kb
Host smart-ca60663b-2f98-49bc-9ecd-eab864f2651a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674054942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.3674054942
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.260293020
Short name T121
Test name
Test status
Simulation time 5316061158 ps
CPU time 8.78 seconds
Started Apr 15 12:34:51 PM PDT 24
Finished Apr 15 12:35:00 PM PDT 24
Peak memory 213664 kb
Host smart-1920c8a8-d9b2-4a20-936e-2c29aa682765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260293020 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.260293020
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.135684519
Short name T49
Test name
Test status
Simulation time 93358430 ps
CPU time 0.85 seconds
Started Apr 15 12:34:59 PM PDT 24
Finished Apr 15 12:35:02 PM PDT 24
Peak memory 204864 kb
Host smart-049e3609-a770-4e1b-bc69-c75186e2c6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135684519 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.135684519
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.624873963
Short name T125
Test name
Test status
Simulation time 1593129380 ps
CPU time 17.77 seconds
Started Apr 15 12:30:51 PM PDT 24
Finished Apr 15 12:31:09 PM PDT 24
Peak memory 212928 kb
Host smart-31ac4bff-7093-46ee-aabb-bbec9e7a6360
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624873963 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.624873963
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.3874280184
Short name T124
Test name
Test status
Simulation time 196212661 ps
CPU time 4.31 seconds
Started Apr 15 12:30:41 PM PDT 24
Finished Apr 15 12:30:47 PM PDT 24
Peak memory 219356 kb
Host smart-bcb0d3ec-fcd3-4d2f-84ba-c7a7e6021ff8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874280184 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.3874280184
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.950792646
Short name T104
Test name
Test status
Simulation time 69514648 ps
CPU time 2.06 seconds
Started Apr 15 12:30:32 PM PDT 24
Finished Apr 15 12:30:35 PM PDT 24
Peak memory 212908 kb
Host smart-b7d90c27-542e-4a10-a479-0227d8044897
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950792646 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.950792646
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1772402502
Short name T359
Test name
Test status
Simulation time 540535784 ps
CPU time 25.85 seconds
Started Apr 15 12:30:34 PM PDT 24
Finished Apr 15 12:31:01 PM PDT 24
Peak memory 204716 kb
Host smart-2d6b32a2-86a7-4ffa-90dc-eca6c1282897
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772402502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.1772402502
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.1590965049
Short name T88
Test name
Test status
Simulation time 20400519728 ps
CPU time 71.49 seconds
Started Apr 15 12:30:31 PM PDT 24
Finished Apr 15 12:31:44 PM PDT 24
Peak memory 205028 kb
Host smart-099e3c2a-01e9-48cd-bd33-4003b39c87eb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590965049 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.1590965049
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.132783149
Short name T102
Test name
Test status
Simulation time 68425272 ps
CPU time 1.65 seconds
Started Apr 15 12:30:28 PM PDT 24
Finished Apr 15 12:30:31 PM PDT 24
Peak memory 212964 kb
Host smart-74281845-e1ef-480c-ad0c-8fac47c79baa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132783149 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.132783149
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1536520247
Short name T253
Test name
Test status
Simulation time 2700091580 ps
CPU time 5.15 seconds
Started Apr 15 12:30:36 PM PDT 24
Finished Apr 15 12:30:42 PM PDT 24
Peak memory 218012 kb
Host smart-6c09f433-a257-402c-b797-f6c3a414cbee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536520247 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.1536520247
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.460262540
Short name T240
Test name
Test status
Simulation time 9965673977 ps
CPU time 12.15 seconds
Started Apr 15 12:30:35 PM PDT 24
Finished Apr 15 12:30:48 PM PDT 24
Peak memory 204732 kb
Host smart-83645f46-cfe5-4cbb-9738-75562c94b66c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460262540 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr
_aliasing.460262540
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.1691115249
Short name T241
Test name
Test status
Simulation time 1362777494 ps
CPU time 2.11 seconds
Started Apr 15 12:30:30 PM PDT 24
Finished Apr 15 12:30:34 PM PDT 24
Peak memory 204684 kb
Host smart-d504fc01-8dc9-4459-98c3-215034c51d98
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691115249 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.1691115249
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3948452876
Short name T278
Test name
Test status
Simulation time 638755623 ps
CPU time 2.82 seconds
Started Apr 15 12:30:34 PM PDT 24
Finished Apr 15 12:30:39 PM PDT 24
Peak memory 204548 kb
Host smart-b2d58f98-9a27-43cb-a5d3-5d41fadfde1d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948452876 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.3
948452876
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2047982188
Short name T343
Test name
Test status
Simulation time 117209090 ps
CPU time 0.89 seconds
Started Apr 15 12:30:36 PM PDT 24
Finished Apr 15 12:30:38 PM PDT 24
Peak memory 204420 kb
Host smart-8d9c07ed-b1ec-48f3-bdcd-4e8cff8abba5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047982188 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.2047982188
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.822341693
Short name T342
Test name
Test status
Simulation time 2343344737 ps
CPU time 8.06 seconds
Started Apr 15 12:30:33 PM PDT 24
Finished Apr 15 12:30:43 PM PDT 24
Peak memory 204880 kb
Host smart-3d63ebad-d501-4db0-a6b7-e739b253087b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822341693 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr
_bit_bash.822341693
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.1825980090
Short name T306
Test name
Test status
Simulation time 92085867 ps
CPU time 0.82 seconds
Started Apr 15 12:30:30 PM PDT 24
Finished Apr 15 12:30:32 PM PDT 24
Peak memory 204504 kb
Host smart-b47a66e7-afdd-4da6-bdb6-7b5d9306dfb3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825980090 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.1825980090
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.679717695
Short name T300
Test name
Test status
Simulation time 83018018 ps
CPU time 0.7 seconds
Started Apr 15 12:30:33 PM PDT 24
Finished Apr 15 12:30:35 PM PDT 24
Peak memory 204368 kb
Host smart-1f88df50-56d1-46fb-887c-81a84b21f0f1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679717695 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.679717695
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1170539842
Short name T238
Test name
Test status
Simulation time 89763535 ps
CPU time 0.7 seconds
Started Apr 15 12:30:32 PM PDT 24
Finished Apr 15 12:30:34 PM PDT 24
Peak memory 204436 kb
Host smart-75af3d1d-b4a6-44f2-b0de-8dba405d4c1f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170539842 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.1170539842
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.3147800634
Short name T321
Test name
Test status
Simulation time 51011363 ps
CPU time 0.69 seconds
Started Apr 15 12:30:37 PM PDT 24
Finished Apr 15 12:30:39 PM PDT 24
Peak memory 204392 kb
Host smart-f07a6dba-ed5a-472a-a8d3-e4e439fef52c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147800634 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.3147800634
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.1058059857
Short name T66
Test name
Test status
Simulation time 183809059 ps
CPU time 3.93 seconds
Started Apr 15 12:30:37 PM PDT 24
Finished Apr 15 12:30:42 PM PDT 24
Peak memory 213024 kb
Host smart-0aacda63-6213-4f71-8eb2-0da0f6e4b62b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058059857 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.1058059857
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.1638953157
Short name T131
Test name
Test status
Simulation time 1316664084 ps
CPU time 7.66 seconds
Started Apr 15 12:30:34 PM PDT 24
Finished Apr 15 12:30:43 PM PDT 24
Peak memory 213060 kb
Host smart-44443c5d-3291-4121-8f12-03cc397b0fd8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638953157 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.1638953157
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3995753433
Short name T97
Test name
Test status
Simulation time 1152541213 ps
CPU time 66.05 seconds
Started Apr 15 12:30:29 PM PDT 24
Finished Apr 15 12:31:37 PM PDT 24
Peak memory 217032 kb
Host smart-ce374c1e-85d7-4e57-b965-3fa233ef9034
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995753433 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.3995753433
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2688887772
Short name T86
Test name
Test status
Simulation time 3661672757 ps
CPU time 36.62 seconds
Started Apr 15 12:30:38 PM PDT 24
Finished Apr 15 12:31:16 PM PDT 24
Peak memory 213144 kb
Host smart-b2ef3d6d-4a86-46e1-a596-1febf7e866ed
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688887772 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.2688887772
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.221706025
Short name T113
Test name
Test status
Simulation time 174829985 ps
CPU time 2.4 seconds
Started Apr 15 12:30:34 PM PDT 24
Finished Apr 15 12:30:37 PM PDT 24
Peak memory 212972 kb
Host smart-54b96bc5-3146-437f-864e-b999b21f8e6a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221706025 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.221706025
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3503806167
Short name T256
Test name
Test status
Simulation time 316365126 ps
CPU time 2.23 seconds
Started Apr 15 12:30:38 PM PDT 24
Finished Apr 15 12:30:42 PM PDT 24
Peak memory 215224 kb
Host smart-1e8c18c0-cd3a-4464-b7cb-316a6adbc1eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503806167 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.3503806167
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2702983140
Short name T347
Test name
Test status
Simulation time 163359556 ps
CPU time 2.28 seconds
Started Apr 15 12:30:43 PM PDT 24
Finished Apr 15 12:30:46 PM PDT 24
Peak memory 212980 kb
Host smart-303871fe-e94a-42f0-8a5e-e8426e8bb379
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702983140 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.2702983140
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.157481386
Short name T266
Test name
Test status
Simulation time 17325467661 ps
CPU time 55.51 seconds
Started Apr 15 12:30:38 PM PDT 24
Finished Apr 15 12:31:35 PM PDT 24
Peak memory 204768 kb
Host smart-ee57bb0f-1a8a-4d37-a1f8-22e125ef8bb0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157481386 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr
_aliasing.157481386
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1207368158
Short name T372
Test name
Test status
Simulation time 11521594616 ps
CPU time 24.51 seconds
Started Apr 15 12:30:29 PM PDT 24
Finished Apr 15 12:30:55 PM PDT 24
Peak memory 204816 kb
Host smart-ec4173d0-ac85-48f4-8923-b454af45466c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207368158 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_bit_bash.1207368158
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.4166398574
Short name T277
Test name
Test status
Simulation time 949443899 ps
CPU time 1.65 seconds
Started Apr 15 12:30:32 PM PDT 24
Finished Apr 15 12:30:35 PM PDT 24
Peak memory 204580 kb
Host smart-bbf9b0e6-e486-4c6a-a6ff-01b0e067fde8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166398574 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.4
166398574
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.4009735613
Short name T292
Test name
Test status
Simulation time 67586974 ps
CPU time 0.7 seconds
Started Apr 15 12:30:32 PM PDT 24
Finished Apr 15 12:30:34 PM PDT 24
Peak memory 204404 kb
Host smart-b6d12948-7e32-40ef-928c-133df5428e19
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009735613 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.4009735613
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.3091344901
Short name T340
Test name
Test status
Simulation time 609077207 ps
CPU time 3.04 seconds
Started Apr 15 12:30:36 PM PDT 24
Finished Apr 15 12:30:41 PM PDT 24
Peak memory 204600 kb
Host smart-15a4e3bd-9d88-4e99-9f52-cfdaa131d143
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091344901 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.3091344901
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1802182089
Short name T333
Test name
Test status
Simulation time 68760833 ps
CPU time 0.74 seconds
Started Apr 15 12:30:34 PM PDT 24
Finished Apr 15 12:30:36 PM PDT 24
Peak memory 204412 kb
Host smart-91c4f831-56b5-4991-beae-952ab075a7bf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802182089 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.1802182089
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.2127473891
Short name T288
Test name
Test status
Simulation time 106775286 ps
CPU time 0.83 seconds
Started Apr 15 12:30:37 PM PDT 24
Finished Apr 15 12:30:39 PM PDT 24
Peak memory 204432 kb
Host smart-69eeff50-abf8-44b3-9534-d378878a4c84
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127473891 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.2
127473891
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2655406708
Short name T318
Test name
Test status
Simulation time 56145837 ps
CPU time 0.66 seconds
Started Apr 15 12:30:37 PM PDT 24
Finished Apr 15 12:30:40 PM PDT 24
Peak memory 204424 kb
Host smart-9eb73e0a-6cb4-410e-9523-77dac28610d9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655406708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.2655406708
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.1622764170
Short name T319
Test name
Test status
Simulation time 47590962 ps
CPU time 0.65 seconds
Started Apr 15 12:30:34 PM PDT 24
Finished Apr 15 12:30:36 PM PDT 24
Peak memory 204400 kb
Host smart-1fae9873-24c2-4c67-aea0-56bf5be3cfe4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622764170 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.1622764170
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.952685908
Short name T362
Test name
Test status
Simulation time 825038870 ps
CPU time 4.09 seconds
Started Apr 15 12:31:14 PM PDT 24
Finished Apr 15 12:31:19 PM PDT 24
Peak memory 204880 kb
Host smart-4e28db36-0c62-4879-92dd-cda856325089
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952685908 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_c
sr_outstanding.952685908
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1874366873
Short name T154
Test name
Test status
Simulation time 196931939 ps
CPU time 4.4 seconds
Started Apr 15 12:30:32 PM PDT 24
Finished Apr 15 12:30:38 PM PDT 24
Peak memory 212984 kb
Host smart-6c3ed9b3-67dd-45d9-a80d-15b707540745
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874366873 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.1874366873
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.1333958050
Short name T258
Test name
Test status
Simulation time 69020012 ps
CPU time 2.06 seconds
Started Apr 15 12:30:43 PM PDT 24
Finished Apr 15 12:30:46 PM PDT 24
Peak memory 214496 kb
Host smart-490adcdd-a0d0-4df8-b24c-42918e70bacd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333958050 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.1333958050
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.2671455864
Short name T107
Test name
Test status
Simulation time 39808523 ps
CPU time 2.1 seconds
Started Apr 15 12:30:51 PM PDT 24
Finished Apr 15 12:30:54 PM PDT 24
Peak memory 212972 kb
Host smart-2ff44b80-bd2d-4dd4-91f5-dc04dda6e27b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671455864 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.2671455864
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.974859613
Short name T376
Test name
Test status
Simulation time 186961380 ps
CPU time 1.16 seconds
Started Apr 15 12:30:46 PM PDT 24
Finished Apr 15 12:30:49 PM PDT 24
Peak memory 204560 kb
Host smart-0716683d-c012-424d-a751-1c5d11cff383
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974859613 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.974859613
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.579436426
Short name T255
Test name
Test status
Simulation time 34412297 ps
CPU time 0.68 seconds
Started Apr 15 12:30:55 PM PDT 24
Finished Apr 15 12:30:57 PM PDT 24
Peak memory 204432 kb
Host smart-186bc81d-f3bb-4e51-91a8-9d6fc05ebe06
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579436426 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.579436426
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3390942954
Short name T371
Test name
Test status
Simulation time 161785446 ps
CPU time 3.54 seconds
Started Apr 15 12:30:38 PM PDT 24
Finished Apr 15 12:30:43 PM PDT 24
Peak memory 204732 kb
Host smart-b2030130-6350-42f7-8908-b0b8b30f0365
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390942954 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.3390942954
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tap_fsm_rand_reset.3986749298
Short name T344
Test name
Test status
Simulation time 13036784879 ps
CPU time 11.71 seconds
Started Apr 15 12:30:54 PM PDT 24
Finished Apr 15 12:31:06 PM PDT 24
Peak memory 215104 kb
Host smart-2303a393-3bf8-4342-ac66-2abaf1b6d32a
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986749298 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rv_dm_tap_fsm_rand_reset.3986749298
Directory /workspace/10.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.1139327200
Short name T286
Test name
Test status
Simulation time 46006641 ps
CPU time 2.44 seconds
Started Apr 15 12:30:46 PM PDT 24
Finished Apr 15 12:30:50 PM PDT 24
Peak memory 212948 kb
Host smart-d1cde8fd-78ad-4c9a-a6be-87cd365aae2e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139327200 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.1139327200
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1553667567
Short name T128
Test name
Test status
Simulation time 1701693521 ps
CPU time 9.66 seconds
Started Apr 15 12:30:56 PM PDT 24
Finished Apr 15 12:31:07 PM PDT 24
Peak memory 212964 kb
Host smart-c4d3d304-ca6e-4d7a-bd6c-09f9f3530b77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553667567 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.1
553667567
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.2920995177
Short name T341
Test name
Test status
Simulation time 1563928313 ps
CPU time 4.98 seconds
Started Apr 15 12:30:43 PM PDT 24
Finished Apr 15 12:30:49 PM PDT 24
Peak memory 218948 kb
Host smart-54af2baa-8eb6-4b6d-b44e-ec7913b94b0b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920995177 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.2920995177
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.2104614508
Short name T114
Test name
Test status
Simulation time 300735050 ps
CPU time 1.51 seconds
Started Apr 15 12:30:51 PM PDT 24
Finished Apr 15 12:30:53 PM PDT 24
Peak memory 212920 kb
Host smart-c6e288b1-e9a5-43ce-9cc6-4576c0df396d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104614508 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.2104614508
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3108483434
Short name T295
Test name
Test status
Simulation time 621380301 ps
CPU time 2.25 seconds
Started Apr 15 12:30:51 PM PDT 24
Finished Apr 15 12:30:54 PM PDT 24
Peak memory 204512 kb
Host smart-dff2e6d2-2310-4001-99c2-88ef6e05ac1d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108483434 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
3108483434
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.2519611529
Short name T313
Test name
Test status
Simulation time 262500523 ps
CPU time 4.21 seconds
Started Apr 15 12:30:51 PM PDT 24
Finished Apr 15 12:30:56 PM PDT 24
Peak memory 204572 kb
Host smart-647af0be-e0b6-47cc-9b1b-76b553437e36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519611529 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same
_csr_outstanding.2519611529
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.2948795750
Short name T327
Test name
Test status
Simulation time 113963625 ps
CPU time 2.03 seconds
Started Apr 15 12:30:51 PM PDT 24
Finished Apr 15 12:30:54 PM PDT 24
Peak memory 213040 kb
Host smart-5749179e-87b9-4622-a673-6f2e240337d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948795750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.2948795750
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1584291149
Short name T334
Test name
Test status
Simulation time 125800649 ps
CPU time 3.24 seconds
Started Apr 15 12:30:44 PM PDT 24
Finished Apr 15 12:30:48 PM PDT 24
Peak memory 217932 kb
Host smart-7351b7b4-31bf-4e52-8278-1b382a475d63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584291149 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.1584291149
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.3380557436
Short name T325
Test name
Test status
Simulation time 1615365272 ps
CPU time 3.94 seconds
Started Apr 15 12:30:44 PM PDT 24
Finished Apr 15 12:30:49 PM PDT 24
Peak memory 204620 kb
Host smart-9d720869-3734-4223-96c2-27c6e481b303
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380557436 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
3380557436
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1524838166
Short name T328
Test name
Test status
Simulation time 39521232 ps
CPU time 0.81 seconds
Started Apr 15 12:30:54 PM PDT 24
Finished Apr 15 12:30:56 PM PDT 24
Peak memory 204396 kb
Host smart-e5725871-f58f-499a-816f-ebd091e5fc2e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524838166 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
1524838166
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.115313803
Short name T40
Test name
Test status
Simulation time 1506096906 ps
CPU time 4.7 seconds
Started Apr 15 12:30:42 PM PDT 24
Finished Apr 15 12:30:47 PM PDT 24
Peak memory 204904 kb
Host smart-da45c0f2-a9ab-4e43-819b-9de4dc80dfb1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115313803 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same_
csr_outstanding.115313803
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.2872512444
Short name T39
Test name
Test status
Simulation time 101511611 ps
CPU time 2.47 seconds
Started Apr 15 12:30:39 PM PDT 24
Finished Apr 15 12:30:42 PM PDT 24
Peak memory 213012 kb
Host smart-48a0b55a-3f9e-4749-bcde-06b834d7ee6a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872512444 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.2872512444
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2051072714
Short name T367
Test name
Test status
Simulation time 2702316099 ps
CPU time 9.76 seconds
Started Apr 15 12:30:37 PM PDT 24
Finished Apr 15 12:30:48 PM PDT 24
Peak memory 213080 kb
Host smart-f2e9945d-c9a8-4cbd-96ee-32394f445178
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051072714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.2
051072714
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3962055238
Short name T322
Test name
Test status
Simulation time 3745706560 ps
CPU time 8.85 seconds
Started Apr 15 12:30:41 PM PDT 24
Finished Apr 15 12:30:51 PM PDT 24
Peak memory 219028 kb
Host smart-24d8b687-c2b1-45c7-9dbb-f64e13c18bef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962055238 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.3962055238
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.4259598178
Short name T370
Test name
Test status
Simulation time 50747419 ps
CPU time 1.5 seconds
Started Apr 15 12:30:43 PM PDT 24
Finished Apr 15 12:30:50 PM PDT 24
Peak memory 213080 kb
Host smart-06c9a001-b16c-4084-bba2-a10ad4c73bb5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259598178 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.4259598178
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.3895559518
Short name T281
Test name
Test status
Simulation time 500223015 ps
CPU time 2.32 seconds
Started Apr 15 12:30:43 PM PDT 24
Finished Apr 15 12:30:46 PM PDT 24
Peak memory 204612 kb
Host smart-70de992e-9514-4c01-aa5c-766b37f63cf7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895559518 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
3895559518
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3651913118
Short name T336
Test name
Test status
Simulation time 74363077 ps
CPU time 0.76 seconds
Started Apr 15 12:30:44 PM PDT 24
Finished Apr 15 12:30:46 PM PDT 24
Peak memory 204432 kb
Host smart-0b510408-1987-4210-a4d7-1edb3e49ddff
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651913118 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
3651913118
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.76189078
Short name T366
Test name
Test status
Simulation time 2789614057 ps
CPU time 7.56 seconds
Started Apr 15 12:30:40 PM PDT 24
Finished Apr 15 12:30:48 PM PDT 24
Peak memory 204896 kb
Host smart-aa1a4e20-548f-4d27-8aa4-07dacd9f06bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76189078 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same_c
sr_outstanding.76189078
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tap_fsm_rand_reset.1673979487
Short name T79
Test name
Test status
Simulation time 7228234493 ps
CPU time 23.32 seconds
Started Apr 15 12:30:51 PM PDT 24
Finished Apr 15 12:31:15 PM PDT 24
Peak memory 215544 kb
Host smart-19e9e930-0304-42a7-99d0-74d532ce78f1
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673979487 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rv_dm_tap_fsm_rand_reset.1673979487
Directory /workspace/13.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.112181073
Short name T308
Test name
Test status
Simulation time 80222375 ps
CPU time 5.07 seconds
Started Apr 15 12:31:02 PM PDT 24
Finished Apr 15 12:31:08 PM PDT 24
Peak memory 212992 kb
Host smart-241bf54b-c5d6-4809-b4d8-c088b7e7e386
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112181073 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.112181073
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3865831541
Short name T92
Test name
Test status
Simulation time 674432577 ps
CPU time 8.63 seconds
Started Apr 15 12:30:44 PM PDT 24
Finished Apr 15 12:30:53 PM PDT 24
Peak memory 213264 kb
Host smart-1c48c240-95ba-4f06-b2a2-48952dfa7ac3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865831541 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.3
865831541
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3157843465
Short name T316
Test name
Test status
Simulation time 84393320 ps
CPU time 2.54 seconds
Started Apr 15 12:30:49 PM PDT 24
Finished Apr 15 12:30:52 PM PDT 24
Peak memory 221128 kb
Host smart-64dc7a43-f834-4fc1-90d5-081c3ec02699
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157843465 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.3157843465
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.3541400383
Short name T356
Test name
Test status
Simulation time 111027282 ps
CPU time 1.54 seconds
Started Apr 15 12:30:43 PM PDT 24
Finished Apr 15 12:30:46 PM PDT 24
Peak memory 212912 kb
Host smart-52822dbf-8e4a-42cb-9704-f89d94a7bb89
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541400383 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.3541400383
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2221858908
Short name T354
Test name
Test status
Simulation time 369307132 ps
CPU time 1.15 seconds
Started Apr 15 12:30:42 PM PDT 24
Finished Apr 15 12:30:44 PM PDT 24
Peak memory 204492 kb
Host smart-213a9994-fc60-4405-b1b8-1407f8b57e2c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221858908 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
2221858908
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.3695036601
Short name T259
Test name
Test status
Simulation time 51227761 ps
CPU time 0.76 seconds
Started Apr 15 12:31:03 PM PDT 24
Finished Apr 15 12:31:04 PM PDT 24
Peak memory 204428 kb
Host smart-72c93a6c-3546-4a16-9d60-401655d26147
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695036601 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
3695036601
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3663540552
Short name T352
Test name
Test status
Simulation time 1997005569 ps
CPU time 4.27 seconds
Started Apr 15 12:30:43 PM PDT 24
Finished Apr 15 12:30:48 PM PDT 24
Peak memory 204772 kb
Host smart-a46f4065-d54f-46bc-916d-b2ba3a7e9c7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663540552 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.3663540552
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tap_fsm_rand_reset.2153426637
Short name T248
Test name
Test status
Simulation time 19347313524 ps
CPU time 11.76 seconds
Started Apr 15 12:30:58 PM PDT 24
Finished Apr 15 12:31:10 PM PDT 24
Peak memory 221228 kb
Host smart-0784b01a-b461-4960-a8d8-2832611f448c
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153426637 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rv_dm_tap_fsm_rand_reset.2153426637
Directory /workspace/14.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.2407963450
Short name T373
Test name
Test status
Simulation time 121580682 ps
CPU time 2.15 seconds
Started Apr 15 12:30:42 PM PDT 24
Finished Apr 15 12:30:45 PM PDT 24
Peak memory 212976 kb
Host smart-05e0300b-7bca-4e70-91f2-b9b00ae6555f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407963450 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.2407963450
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.4231900185
Short name T329
Test name
Test status
Simulation time 50733680 ps
CPU time 1.46 seconds
Started Apr 15 12:30:43 PM PDT 24
Finished Apr 15 12:30:45 PM PDT 24
Peak memory 212912 kb
Host smart-815cd6af-2075-473e-ab1f-ca61c962a3be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231900185 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.4231900185
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.505484547
Short name T268
Test name
Test status
Simulation time 193706113 ps
CPU time 0.99 seconds
Started Apr 15 12:30:44 PM PDT 24
Finished Apr 15 12:30:46 PM PDT 24
Peak memory 204640 kb
Host smart-a08439b8-c436-4a8d-be83-69dac0bed126
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505484547 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.505484547
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3486471308
Short name T273
Test name
Test status
Simulation time 121640964 ps
CPU time 0.65 seconds
Started Apr 15 12:30:50 PM PDT 24
Finished Apr 15 12:30:51 PM PDT 24
Peak memory 204500 kb
Host smart-1c25ea04-3cb9-4f37-b1d3-bf5fde912cfb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486471308 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
3486471308
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.1032589011
Short name T116
Test name
Test status
Simulation time 509501758 ps
CPU time 5.85 seconds
Started Apr 15 12:30:44 PM PDT 24
Finished Apr 15 12:30:50 PM PDT 24
Peak memory 204844 kb
Host smart-b4a471ce-2b2b-4c9b-bb7e-8da028de867c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032589011 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.1032589011
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tap_fsm_rand_reset.2540347902
Short name T314
Test name
Test status
Simulation time 13757962294 ps
CPU time 24.55 seconds
Started Apr 15 12:30:41 PM PDT 24
Finished Apr 15 12:31:07 PM PDT 24
Peak memory 229436 kb
Host smart-d7c0942a-2c56-41f1-9f60-7b0b7c56d2a1
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540347902 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rv_dm_tap_fsm_rand_reset.2540347902
Directory /workspace/15.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.4030842553
Short name T317
Test name
Test status
Simulation time 100227963 ps
CPU time 2.58 seconds
Started Apr 15 12:30:44 PM PDT 24
Finished Apr 15 12:30:48 PM PDT 24
Peak memory 213128 kb
Host smart-c55a088e-183e-47c8-914b-7a565fe89920
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030842553 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.4030842553
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.1539274424
Short name T315
Test name
Test status
Simulation time 844297745 ps
CPU time 19.44 seconds
Started Apr 15 12:30:41 PM PDT 24
Finished Apr 15 12:31:02 PM PDT 24
Peak memory 220992 kb
Host smart-14acd8eb-cd1b-4f9e-85d6-635397702adb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539274424 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.1
539274424
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.1292858052
Short name T363
Test name
Test status
Simulation time 2058950571 ps
CPU time 5.45 seconds
Started Apr 15 12:30:48 PM PDT 24
Finished Apr 15 12:30:54 PM PDT 24
Peak memory 217104 kb
Host smart-99368e12-aca1-4248-afe8-cbbf47d597c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292858052 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.1292858052
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.1671535211
Short name T112
Test name
Test status
Simulation time 208693815 ps
CPU time 1.61 seconds
Started Apr 15 12:30:46 PM PDT 24
Finished Apr 15 12:30:48 PM PDT 24
Peak memory 212928 kb
Host smart-ec8a6dcf-cee7-4cc4-ab6d-33d3d65c319c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671535211 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.1671535211
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.635022058
Short name T299
Test name
Test status
Simulation time 1582082187 ps
CPU time 2.07 seconds
Started Apr 15 12:30:49 PM PDT 24
Finished Apr 15 12:30:51 PM PDT 24
Peak memory 204664 kb
Host smart-92bf7d3d-f25e-45a1-865d-922414053c8c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635022058 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.635022058
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3897435491
Short name T305
Test name
Test status
Simulation time 27230215 ps
CPU time 0.76 seconds
Started Apr 15 12:31:09 PM PDT 24
Finished Apr 15 12:31:11 PM PDT 24
Peak memory 204420 kb
Host smart-3c1ee58e-6b56-46c9-b386-3361635c384b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897435491 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
3897435491
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.2667228353
Short name T117
Test name
Test status
Simulation time 144991899 ps
CPU time 6.33 seconds
Started Apr 15 12:30:47 PM PDT 24
Finished Apr 15 12:30:55 PM PDT 24
Peak memory 204728 kb
Host smart-620823a3-7b92-4979-8a91-60dcfae2818f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667228353 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.2667228353
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tap_fsm_rand_reset.3000665071
Short name T275
Test name
Test status
Simulation time 12218516182 ps
CPU time 14.6 seconds
Started Apr 15 12:30:42 PM PDT 24
Finished Apr 15 12:30:58 PM PDT 24
Peak memory 215116 kb
Host smart-84558b2d-5bee-4bcd-9fde-626aa73a537d
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000665071 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rv_dm_tap_fsm_rand_reset.3000665071
Directory /workspace/16.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.849285871
Short name T378
Test name
Test status
Simulation time 209193034 ps
CPU time 4.58 seconds
Started Apr 15 12:30:47 PM PDT 24
Finished Apr 15 12:30:53 PM PDT 24
Peak memory 213024 kb
Host smart-a9ab6a8c-3cba-4b33-b823-7bd454a3d5bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849285871 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.849285871
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.1463138403
Short name T285
Test name
Test status
Simulation time 1244173160 ps
CPU time 10.42 seconds
Started Apr 15 12:30:48 PM PDT 24
Finished Apr 15 12:30:59 PM PDT 24
Peak memory 212952 kb
Host smart-58f6f4e8-eeb2-4b64-92a9-f3fa8cc8adab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463138403 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.1
463138403
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2683809226
Short name T368
Test name
Test status
Simulation time 2876252035 ps
CPU time 3.81 seconds
Started Apr 15 12:31:05 PM PDT 24
Finished Apr 15 12:31:10 PM PDT 24
Peak memory 216880 kb
Host smart-ab52d889-ae95-499e-963f-a4a48f1185a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683809226 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.2683809226
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.3890048288
Short name T252
Test name
Test status
Simulation time 216480305 ps
CPU time 1.75 seconds
Started Apr 15 12:31:12 PM PDT 24
Finished Apr 15 12:31:15 PM PDT 24
Peak memory 212880 kb
Host smart-f67edf20-1333-463d-9098-eca5c699636b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890048288 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.3890048288
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.641859067
Short name T260
Test name
Test status
Simulation time 338927693 ps
CPU time 1.79 seconds
Started Apr 15 12:31:00 PM PDT 24
Finished Apr 15 12:31:02 PM PDT 24
Peak memory 204664 kb
Host smart-9d0389c6-6d55-490c-9831-8f88828b3ab0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641859067 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.641859067
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.736819884
Short name T63
Test name
Test status
Simulation time 76461085 ps
CPU time 0.69 seconds
Started Apr 15 12:31:07 PM PDT 24
Finished Apr 15 12:31:09 PM PDT 24
Peak memory 204512 kb
Host smart-a51587c4-e816-4cc3-bb2d-5a0a712635bc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736819884 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.736819884
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.1547628331
Short name T338
Test name
Test status
Simulation time 1771341987 ps
CPU time 8.16 seconds
Started Apr 15 12:31:02 PM PDT 24
Finished Apr 15 12:31:11 PM PDT 24
Peak memory 204732 kb
Host smart-173d5e19-e097-41ab-a06c-8249eaa24205
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547628331 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.1547628331
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2095472539
Short name T298
Test name
Test status
Simulation time 68028357 ps
CPU time 2.26 seconds
Started Apr 15 12:30:48 PM PDT 24
Finished Apr 15 12:30:51 PM PDT 24
Peak memory 213048 kb
Host smart-b3958a71-8223-4fa4-b488-e26496dd2d5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095472539 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.2095472539
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.4014944793
Short name T350
Test name
Test status
Simulation time 318835458 ps
CPU time 3.86 seconds
Started Apr 15 12:30:49 PM PDT 24
Finished Apr 15 12:30:54 PM PDT 24
Peak memory 221076 kb
Host smart-88249c5e-b9e9-4e0a-9816-5340c0ccf505
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014944793 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.4014944793
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.3610850906
Short name T83
Test name
Test status
Simulation time 94344946 ps
CPU time 2.4 seconds
Started Apr 15 12:31:08 PM PDT 24
Finished Apr 15 12:31:12 PM PDT 24
Peak memory 218520 kb
Host smart-73e962a5-5fc6-4818-b905-1dd36cd8ba2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610850906 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.3610850906
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1193890838
Short name T307
Test name
Test status
Simulation time 195119476 ps
CPU time 1.1 seconds
Started Apr 15 12:30:50 PM PDT 24
Finished Apr 15 12:30:52 PM PDT 24
Peak memory 204600 kb
Host smart-6db8e3a0-99b2-476f-bf61-fd92db0c7d3a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193890838 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
1193890838
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2656535707
Short name T330
Test name
Test status
Simulation time 21106210 ps
CPU time 0.72 seconds
Started Apr 15 12:30:56 PM PDT 24
Finished Apr 15 12:30:58 PM PDT 24
Peak memory 204472 kb
Host smart-19758245-e0ce-4958-a8d5-a187a2fe5596
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656535707 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
2656535707
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1223714731
Short name T364
Test name
Test status
Simulation time 1106175026 ps
CPU time 4.52 seconds
Started Apr 15 12:30:50 PM PDT 24
Finished Apr 15 12:30:55 PM PDT 24
Peak memory 204712 kb
Host smart-969e9d31-f429-4945-addb-c707501c24a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223714731 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.1223714731
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.3846601897
Short name T369
Test name
Test status
Simulation time 1232767803 ps
CPU time 4.78 seconds
Started Apr 15 12:31:04 PM PDT 24
Finished Apr 15 12:31:10 PM PDT 24
Peak memory 221152 kb
Host smart-4f5bec35-9ac3-49d5-a751-b8e2c6289ce0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846601897 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.3846601897
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.4107612894
Short name T312
Test name
Test status
Simulation time 776308781 ps
CPU time 16.04 seconds
Started Apr 15 12:31:04 PM PDT 24
Finished Apr 15 12:31:20 PM PDT 24
Peak memory 221052 kb
Host smart-9a0ec670-8fd3-4038-9613-f7b043d38ffe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107612894 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.4
107612894
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3681387384
Short name T287
Test name
Test status
Simulation time 902234949 ps
CPU time 4.73 seconds
Started Apr 15 12:31:05 PM PDT 24
Finished Apr 15 12:31:10 PM PDT 24
Peak memory 219008 kb
Host smart-cb0e2d89-6f1f-4bf5-80ef-2d6ae5077a6c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681387384 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.3681387384
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.4281559095
Short name T105
Test name
Test status
Simulation time 86083797 ps
CPU time 2.29 seconds
Started Apr 15 12:31:07 PM PDT 24
Finished Apr 15 12:31:10 PM PDT 24
Peak memory 212872 kb
Host smart-a56584ba-8f5b-4096-96d8-6b798adad4f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281559095 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.4281559095
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.3503350919
Short name T293
Test name
Test status
Simulation time 663292027 ps
CPU time 1.33 seconds
Started Apr 15 12:30:48 PM PDT 24
Finished Apr 15 12:30:50 PM PDT 24
Peak memory 204612 kb
Host smart-f2c9ccca-bbd9-47b5-8a63-aea9464a17ec
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503350919 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
3503350919
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.4138816431
Short name T283
Test name
Test status
Simulation time 157547590 ps
CPU time 1.07 seconds
Started Apr 15 12:31:12 PM PDT 24
Finished Apr 15 12:31:14 PM PDT 24
Peak memory 204416 kb
Host smart-6d34fad7-b95f-4d28-b204-cd63beeca8c2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138816431 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
4138816431
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.3096132284
Short name T115
Test name
Test status
Simulation time 5736537494 ps
CPU time 7.74 seconds
Started Apr 15 12:31:09 PM PDT 24
Finished Apr 15 12:31:17 PM PDT 24
Peak memory 204884 kb
Host smart-d622d1b1-bbec-4f80-943e-505b96555dce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096132284 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.3096132284
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.2235001706
Short name T326
Test name
Test status
Simulation time 241768653 ps
CPU time 5.15 seconds
Started Apr 15 12:30:49 PM PDT 24
Finished Apr 15 12:30:55 PM PDT 24
Peak memory 213056 kb
Host smart-c7afcc16-8170-4b2e-b28d-966fe08bc215
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235001706 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.2235001706
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.596300519
Short name T324
Test name
Test status
Simulation time 532999662 ps
CPU time 10.1 seconds
Started Apr 15 12:30:47 PM PDT 24
Finished Apr 15 12:30:58 PM PDT 24
Peak memory 221084 kb
Host smart-27a1e07a-9020-4e3d-8696-e868e3f9b4c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596300519 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.596300519
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2861776325
Short name T108
Test name
Test status
Simulation time 14892508887 ps
CPU time 75.26 seconds
Started Apr 15 12:30:36 PM PDT 24
Finished Apr 15 12:31:53 PM PDT 24
Peak memory 213096 kb
Host smart-67451026-426c-4624-815f-982b97c7cb3e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861776325 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.2861776325
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3125016729
Short name T82
Test name
Test status
Simulation time 180080848 ps
CPU time 2.43 seconds
Started Apr 15 12:30:38 PM PDT 24
Finished Apr 15 12:30:42 PM PDT 24
Peak memory 212968 kb
Host smart-01a704ba-7a1c-4727-8b59-1e3568d24f09
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125016729 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.3125016729
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3717041550
Short name T345
Test name
Test status
Simulation time 4485233805 ps
CPU time 9.78 seconds
Started Apr 15 12:30:38 PM PDT 24
Finished Apr 15 12:30:49 PM PDT 24
Peak memory 221224 kb
Host smart-4d324b48-746c-470a-9512-579a8e42799c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717041550 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.3717041550
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3718117978
Short name T106
Test name
Test status
Simulation time 61493758 ps
CPU time 1.58 seconds
Started Apr 15 12:30:42 PM PDT 24
Finished Apr 15 12:30:45 PM PDT 24
Peak memory 212928 kb
Host smart-3e79e765-acd7-4aa3-afd8-1eed7bd1c906
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718117978 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.3718117978
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.1981283727
Short name T320
Test name
Test status
Simulation time 5960626247 ps
CPU time 12.34 seconds
Started Apr 15 12:30:34 PM PDT 24
Finished Apr 15 12:30:48 PM PDT 24
Peak memory 204748 kb
Host smart-5c32d2cf-6c84-47b5-8c53-b842c1e0d73a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981283727 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.1981283727
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.157848978
Short name T365
Test name
Test status
Simulation time 11906135120 ps
CPU time 24.69 seconds
Started Apr 15 12:30:47 PM PDT 24
Finished Apr 15 12:31:13 PM PDT 24
Peak memory 204708 kb
Host smart-78c3d44a-0bbb-4b43-bbda-e3d9c715a341
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157848978 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr
_bit_bash.157848978
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2066558752
Short name T93
Test name
Test status
Simulation time 1715268469 ps
CPU time 2.34 seconds
Started Apr 15 12:30:49 PM PDT 24
Finished Apr 15 12:30:52 PM PDT 24
Peak memory 204780 kb
Host smart-09da3d5b-ce3c-4f1a-8c2d-2c7c39adcd5e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066558752 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.2066558752
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.4063597559
Short name T270
Test name
Test status
Simulation time 366006804 ps
CPU time 1.91 seconds
Started Apr 15 12:30:34 PM PDT 24
Finished Apr 15 12:30:37 PM PDT 24
Peak memory 204600 kb
Host smart-ceaf01a2-6cee-4767-8603-87f4646c4c2e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063597559 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.4
063597559
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3016221859
Short name T357
Test name
Test status
Simulation time 128950777 ps
CPU time 0.72 seconds
Started Apr 15 12:30:38 PM PDT 24
Finished Apr 15 12:30:40 PM PDT 24
Peak memory 204436 kb
Host smart-16517935-e7b5-4cbb-87e3-24e5ff083df5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016221859 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_aliasing.3016221859
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.4119308339
Short name T279
Test name
Test status
Simulation time 527145851 ps
CPU time 1.61 seconds
Started Apr 15 12:30:36 PM PDT 24
Finished Apr 15 12:30:39 PM PDT 24
Peak memory 204620 kb
Host smart-55f67dc5-9b40-48d5-980d-404de6cc818b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119308339 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.4119308339
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3065071773
Short name T335
Test name
Test status
Simulation time 329718563 ps
CPU time 0.71 seconds
Started Apr 15 12:30:37 PM PDT 24
Finished Apr 15 12:30:40 PM PDT 24
Peak memory 204496 kb
Host smart-f37c24d2-5ca8-4fc8-91bf-025c391ef924
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065071773 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.3065071773
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.1287328481
Short name T304
Test name
Test status
Simulation time 43590404 ps
CPU time 0.75 seconds
Started Apr 15 12:30:38 PM PDT 24
Finished Apr 15 12:30:41 PM PDT 24
Peak memory 204400 kb
Host smart-f1ba4237-b0f6-49d7-92df-58885066c084
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287328481 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.1
287328481
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2813368818
Short name T346
Test name
Test status
Simulation time 14309725 ps
CPU time 0.66 seconds
Started Apr 15 12:30:36 PM PDT 24
Finished Apr 15 12:30:38 PM PDT 24
Peak memory 204396 kb
Host smart-7c61ae9b-70fe-48f7-9485-f671d6e54b2e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813368818 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.2813368818
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.567639045
Short name T247
Test name
Test status
Simulation time 20990100 ps
CPU time 0.69 seconds
Started Apr 15 12:30:37 PM PDT 24
Finished Apr 15 12:30:39 PM PDT 24
Peak memory 204360 kb
Host smart-3e77fd09-3fe7-44a9-b086-c22acf65626f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567639045 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.567639045
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.331182773
Short name T100
Test name
Test status
Simulation time 162204558 ps
CPU time 3.64 seconds
Started Apr 15 12:30:35 PM PDT 24
Finished Apr 15 12:30:40 PM PDT 24
Peak memory 204824 kb
Host smart-c87eebc7-02b2-4a1d-8d91-eaeb52faf45f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331182773 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_c
sr_outstanding.331182773
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.2167922854
Short name T331
Test name
Test status
Simulation time 16395149234 ps
CPU time 26.96 seconds
Started Apr 15 12:30:39 PM PDT 24
Finished Apr 15 12:31:07 PM PDT 24
Peak memory 221300 kb
Host smart-483d6ddf-811f-4e29-9898-639a8d81aeed
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167922854 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.2167922854
Directory /workspace/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.2922219665
Short name T282
Test name
Test status
Simulation time 162085743 ps
CPU time 2.41 seconds
Started Apr 15 12:30:37 PM PDT 24
Finished Apr 15 12:30:42 PM PDT 24
Peak memory 212956 kb
Host smart-a96aaf95-00fc-4134-b007-19f01d7b5c07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922219665 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.2922219665
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.3421026013
Short name T355
Test name
Test status
Simulation time 806802522 ps
CPU time 9.95 seconds
Started Apr 15 12:30:35 PM PDT 24
Finished Apr 15 12:30:46 PM PDT 24
Peak memory 221036 kb
Host smart-963f79d9-e872-413b-8008-941427adb62a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421026013 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.3421026013
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_dm_tap_fsm_rand_reset.3766469849
Short name T374
Test name
Test status
Simulation time 10775002897 ps
CPU time 12.19 seconds
Started Apr 15 12:31:10 PM PDT 24
Finished Apr 15 12:31:23 PM PDT 24
Peak memory 221288 kb
Host smart-cb0af95b-1c36-4ff2-922d-8d17c1592340
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766469849 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 20.rv_dm_tap_fsm_rand_reset.3766469849
Directory /workspace/20.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/24.rv_dm_tap_fsm_rand_reset.2320155738
Short name T254
Test name
Test status
Simulation time 8914216803 ps
CPU time 13.29 seconds
Started Apr 15 12:31:06 PM PDT 24
Finished Apr 15 12:31:20 PM PDT 24
Peak memory 214788 kb
Host smart-c593891a-e68a-4b17-bebb-2109c4124def
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320155738 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 24.rv_dm_tap_fsm_rand_reset.2320155738
Directory /workspace/24.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/26.rv_dm_tap_fsm_rand_reset.2923609986
Short name T36
Test name
Test status
Simulation time 24572951818 ps
CPU time 10.8 seconds
Started Apr 15 12:30:55 PM PDT 24
Finished Apr 15 12:31:08 PM PDT 24
Peak memory 215164 kb
Host smart-8c828c50-1c7f-4060-b34f-963759316017
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923609986 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 26.rv_dm_tap_fsm_rand_reset.2923609986
Directory /workspace/26.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.4279433073
Short name T85
Test name
Test status
Simulation time 18395223481 ps
CPU time 80.03 seconds
Started Apr 15 12:30:42 PM PDT 24
Finished Apr 15 12:32:03 PM PDT 24
Peak memory 213044 kb
Host smart-284a6d36-fff2-4934-b9ac-52d4e5e50d10
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279433073 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.4279433073
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.3690948081
Short name T303
Test name
Test status
Simulation time 718033042 ps
CPU time 27.45 seconds
Started Apr 15 12:30:46 PM PDT 24
Finished Apr 15 12:31:14 PM PDT 24
Peak memory 204796 kb
Host smart-625957d4-f2e2-484e-924a-6388fb0dc22d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690948081 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.3690948081
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1799603774
Short name T110
Test name
Test status
Simulation time 118139759 ps
CPU time 2.17 seconds
Started Apr 15 12:30:39 PM PDT 24
Finished Apr 15 12:30:42 PM PDT 24
Peak memory 212984 kb
Host smart-b812c74d-4d7e-46e9-9ed6-49811135ec98
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799603774 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.1799603774
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.2821257501
Short name T74
Test name
Test status
Simulation time 57472333 ps
CPU time 2.44 seconds
Started Apr 15 12:30:41 PM PDT 24
Finished Apr 15 12:30:44 PM PDT 24
Peak memory 217964 kb
Host smart-0cd8eb20-831f-4829-8397-1cc416912635
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821257501 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.2821257501
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2022072808
Short name T103
Test name
Test status
Simulation time 413778398 ps
CPU time 2.15 seconds
Started Apr 15 12:30:41 PM PDT 24
Finished Apr 15 12:30:45 PM PDT 24
Peak memory 212932 kb
Host smart-ce87dc72-e7f9-4fde-bd3c-d9096d9e2e5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022072808 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.2022072808
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.3982514071
Short name T265
Test name
Test status
Simulation time 2163541935 ps
CPU time 11.1 seconds
Started Apr 15 12:30:44 PM PDT 24
Finished Apr 15 12:30:56 PM PDT 24
Peak memory 204792 kb
Host smart-ea47a950-bcef-4864-8772-6a567ae9c721
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982514071 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.3982514071
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.3069817324
Short name T239
Test name
Test status
Simulation time 30200878571 ps
CPU time 33.84 seconds
Started Apr 15 12:30:42 PM PDT 24
Finished Apr 15 12:31:17 PM PDT 24
Peak memory 204816 kb
Host smart-fb055a84-fec4-4727-ad56-fed160858fa2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069817324 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_bit_bash.3069817324
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.1722927076
Short name T94
Test name
Test status
Simulation time 2528159310 ps
CPU time 5.53 seconds
Started Apr 15 12:30:36 PM PDT 24
Finished Apr 15 12:30:42 PM PDT 24
Peak memory 204844 kb
Host smart-9f566f76-8b01-43be-81fb-5f6f875d000a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722927076 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.1722927076
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1936298996
Short name T351
Test name
Test status
Simulation time 161944230 ps
CPU time 0.89 seconds
Started Apr 15 12:30:42 PM PDT 24
Finished Apr 15 12:30:44 PM PDT 24
Peak memory 204536 kb
Host smart-de6c6309-8b24-4ff0-bb67-f1fbfc3c9863
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936298996 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.1
936298996
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.2221548896
Short name T289
Test name
Test status
Simulation time 123238113 ps
CPU time 1.01 seconds
Started Apr 15 12:30:38 PM PDT 24
Finished Apr 15 12:30:41 PM PDT 24
Peak memory 204444 kb
Host smart-b766286c-246a-4dc7-932b-3f1891e72aaa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221548896 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.2221548896
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2122151043
Short name T246
Test name
Test status
Simulation time 3239021019 ps
CPU time 11.04 seconds
Started Apr 15 12:30:37 PM PDT 24
Finished Apr 15 12:30:50 PM PDT 24
Peak memory 204724 kb
Host smart-c40fe519-7e68-4369-98db-7fd1cafb1c96
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122151043 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.2122151043
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.593678182
Short name T267
Test name
Test status
Simulation time 132871836 ps
CPU time 0.82 seconds
Started Apr 15 12:30:38 PM PDT 24
Finished Apr 15 12:30:40 PM PDT 24
Peak memory 204488 kb
Host smart-72d53508-06fe-49ed-ad26-11907a81da4d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593678182 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr
_hw_reset.593678182
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.561512632
Short name T269
Test name
Test status
Simulation time 36256052 ps
CPU time 0.74 seconds
Started Apr 15 12:30:36 PM PDT 24
Finished Apr 15 12:30:38 PM PDT 24
Peak memory 204420 kb
Host smart-3b757669-d019-4b2e-9465-b6e22fff3ddb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561512632 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.561512632
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.2054347672
Short name T264
Test name
Test status
Simulation time 53605597 ps
CPU time 0.71 seconds
Started Apr 15 12:30:46 PM PDT 24
Finished Apr 15 12:30:48 PM PDT 24
Peak memory 204420 kb
Host smart-8feb3762-8843-4ad7-836b-e1f5548db1de
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054347672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.2054347672
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.487544469
Short name T291
Test name
Test status
Simulation time 26946770 ps
CPU time 0.67 seconds
Started Apr 15 12:30:46 PM PDT 24
Finished Apr 15 12:30:48 PM PDT 24
Peak memory 204212 kb
Host smart-4fc2558b-c252-42fa-8ef8-60a7d3279c6d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487544469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.487544469
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.3537755944
Short name T375
Test name
Test status
Simulation time 815151729 ps
CPU time 7.21 seconds
Started Apr 15 12:30:33 PM PDT 24
Finished Apr 15 12:30:42 PM PDT 24
Peak memory 204676 kb
Host smart-12a838d8-fa46-4542-a660-64a7b6187126
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537755944 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.3537755944
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.3755963229
Short name T78
Test name
Test status
Simulation time 509983917 ps
CPU time 5.97 seconds
Started Apr 15 12:30:35 PM PDT 24
Finished Apr 15 12:30:42 PM PDT 24
Peak memory 213036 kb
Host smart-25a42e11-644e-49ee-88c8-0c3ac1e6ff9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755963229 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.3755963229
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/34.rv_dm_tap_fsm_rand_reset.3386222489
Short name T261
Test name
Test status
Simulation time 13009256275 ps
CPU time 12.05 seconds
Started Apr 15 12:31:13 PM PDT 24
Finished Apr 15 12:31:26 PM PDT 24
Peak memory 213444 kb
Host smart-833a6400-e79f-4f8c-9f13-2201adca2df5
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386222489 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 34.rv_dm_tap_fsm_rand_reset.3386222489
Directory /workspace/34.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/35.rv_dm_tap_fsm_rand_reset.3803875905
Short name T348
Test name
Test status
Simulation time 6363609320 ps
CPU time 24.73 seconds
Started Apr 15 12:31:10 PM PDT 24
Finished Apr 15 12:31:36 PM PDT 24
Peak memory 219452 kb
Host smart-8a2e1a17-864d-4262-9012-6c7a4dfe8778
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803875905 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 35.rv_dm_tap_fsm_rand_reset.3803875905
Directory /workspace/35.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2217312289
Short name T98
Test name
Test status
Simulation time 584480543 ps
CPU time 27.1 seconds
Started Apr 15 12:30:41 PM PDT 24
Finished Apr 15 12:31:09 PM PDT 24
Peak memory 214020 kb
Host smart-604ece0b-beeb-4730-9c8b-225b510e7ad7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217312289 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.2217312289
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.4152126780
Short name T361
Test name
Test status
Simulation time 856167578 ps
CPU time 1.66 seconds
Started Apr 15 12:30:33 PM PDT 24
Finished Apr 15 12:30:36 PM PDT 24
Peak memory 213008 kb
Host smart-33f2d978-feb3-47ce-99c2-33eb3d461cb9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152126780 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.4152126780
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.1338392521
Short name T353
Test name
Test status
Simulation time 37963689 ps
CPU time 2.53 seconds
Started Apr 15 12:30:37 PM PDT 24
Finished Apr 15 12:30:41 PM PDT 24
Peak memory 220564 kb
Host smart-6876abb6-8c68-4424-a392-7c80b0d262e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338392521 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.1338392521
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.3906719678
Short name T358
Test name
Test status
Simulation time 326815082 ps
CPU time 2.3 seconds
Started Apr 15 12:30:43 PM PDT 24
Finished Apr 15 12:30:46 PM PDT 24
Peak memory 212928 kb
Host smart-8d42e3e5-7716-4ecd-a19f-1dc8c99dede0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906719678 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.3906719678
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.1067834942
Short name T290
Test name
Test status
Simulation time 5544686490 ps
CPU time 23.44 seconds
Started Apr 15 12:30:46 PM PDT 24
Finished Apr 15 12:31:11 PM PDT 24
Peak memory 204684 kb
Host smart-8a11aa37-b9ba-4987-a861-75687331dd20
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067834942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.1067834942
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3260739711
Short name T337
Test name
Test status
Simulation time 33959789284 ps
CPU time 119.99 seconds
Started Apr 15 12:30:37 PM PDT 24
Finished Apr 15 12:32:39 PM PDT 24
Peak memory 204752 kb
Host smart-dc800597-411a-4fc2-a38b-a2471400ecec
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260739711 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_bit_bash.3260739711
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.1020011427
Short name T242
Test name
Test status
Simulation time 232762127 ps
CPU time 1.14 seconds
Started Apr 15 12:30:34 PM PDT 24
Finished Apr 15 12:30:37 PM PDT 24
Peak memory 204700 kb
Host smart-9dad1147-4626-4df9-af7d-b1be0e9c66a8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020011427 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.1020011427
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3502105371
Short name T257
Test name
Test status
Simulation time 238032922 ps
CPU time 1.35 seconds
Started Apr 15 12:30:42 PM PDT 24
Finished Apr 15 12:30:44 PM PDT 24
Peak memory 204676 kb
Host smart-26c06ad8-f39a-4409-9963-1f5b5f89a078
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502105371 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.3
502105371
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.3708515471
Short name T250
Test name
Test status
Simulation time 196407064 ps
CPU time 0.74 seconds
Started Apr 15 12:30:38 PM PDT 24
Finished Apr 15 12:30:45 PM PDT 24
Peak memory 204388 kb
Host smart-32adec44-5071-4e91-a7a1-8118d44353af
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708515471 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.3708515471
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.1637446374
Short name T296
Test name
Test status
Simulation time 4026045330 ps
CPU time 11.17 seconds
Started Apr 15 12:30:39 PM PDT 24
Finished Apr 15 12:30:51 PM PDT 24
Peak memory 204684 kb
Host smart-c6574dc5-5eea-4541-9210-fabb3b9c4bb2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637446374 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.1637446374
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2261439373
Short name T64
Test name
Test status
Simulation time 95356937 ps
CPU time 0.72 seconds
Started Apr 15 12:30:49 PM PDT 24
Finished Apr 15 12:30:51 PM PDT 24
Peak memory 204236 kb
Host smart-9d5daf63-cdca-437c-a279-bf3d70714fed
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261439373 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.2261439373
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.967262527
Short name T244
Test name
Test status
Simulation time 150464562 ps
CPU time 0.74 seconds
Started Apr 15 12:31:03 PM PDT 24
Finished Apr 15 12:31:05 PM PDT 24
Peak memory 204472 kb
Host smart-7e38b0e0-61d6-4e06-a841-ef849ef80b48
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967262527 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.967262527
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.577350632
Short name T309
Test name
Test status
Simulation time 25450958 ps
CPU time 0.71 seconds
Started Apr 15 12:30:41 PM PDT 24
Finished Apr 15 12:30:43 PM PDT 24
Peak memory 204468 kb
Host smart-8a180582-3e34-4fdb-9f88-0c37b7fbdcce
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577350632 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_part
ial_access.577350632
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.1695736447
Short name T271
Test name
Test status
Simulation time 34721766 ps
CPU time 0.64 seconds
Started Apr 15 12:30:41 PM PDT 24
Finished Apr 15 12:30:43 PM PDT 24
Peak memory 204428 kb
Host smart-e0a5357b-aa6f-4817-88fe-f0bcb79aefc3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695736447 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.1695736447
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3767225088
Short name T96
Test name
Test status
Simulation time 85383300 ps
CPU time 3.64 seconds
Started Apr 15 12:30:36 PM PDT 24
Finished Apr 15 12:30:41 PM PDT 24
Peak memory 204744 kb
Host smart-c2c3b6b0-1253-4530-8965-da410addd836
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767225088 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.3767225088
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.3322478159
Short name T272
Test name
Test status
Simulation time 7142747339 ps
CPU time 13.94 seconds
Started Apr 15 12:30:44 PM PDT 24
Finished Apr 15 12:30:59 PM PDT 24
Peak memory 221256 kb
Host smart-c06204f7-5544-4c3e-a1a5-30d29bd28e4e
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322478159 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.3322478159
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.1301088233
Short name T339
Test name
Test status
Simulation time 163748543 ps
CPU time 2.61 seconds
Started Apr 15 12:30:50 PM PDT 24
Finished Apr 15 12:30:54 PM PDT 24
Peak memory 213104 kb
Host smart-09596d39-7c59-47b2-97a0-a9389f3b9385
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301088233 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.1301088233
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.571123558
Short name T133
Test name
Test status
Simulation time 4148952366 ps
CPU time 20 seconds
Started Apr 15 12:30:42 PM PDT 24
Finished Apr 15 12:31:03 PM PDT 24
Peak memory 213108 kb
Host smart-137931ee-6a01-4a3c-a31b-e48085b7ca0e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571123558 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.571123558
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3064579347
Short name T280
Test name
Test status
Simulation time 5679630707 ps
CPU time 7.69 seconds
Started Apr 15 12:30:46 PM PDT 24
Finished Apr 15 12:30:55 PM PDT 24
Peak memory 217908 kb
Host smart-b6f365ac-f65e-4eb9-b0e3-89a64b0105ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064579347 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.3064579347
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.1448140969
Short name T323
Test name
Test status
Simulation time 218985908 ps
CPU time 2.14 seconds
Started Apr 15 12:30:43 PM PDT 24
Finished Apr 15 12:30:47 PM PDT 24
Peak memory 212876 kb
Host smart-aa3a4f0f-a77d-41d6-98aa-8e4d4266e106
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448140969 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.1448140969
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.322926432
Short name T262
Test name
Test status
Simulation time 308770075 ps
CPU time 1.19 seconds
Started Apr 15 12:30:49 PM PDT 24
Finished Apr 15 12:30:51 PM PDT 24
Peak memory 204648 kb
Host smart-f076d6bd-7216-4eaa-8241-e7825fea6504
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322926432 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.322926432
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3295561462
Short name T243
Test name
Test status
Simulation time 41725013 ps
CPU time 0.77 seconds
Started Apr 15 12:30:41 PM PDT 24
Finished Apr 15 12:30:43 PM PDT 24
Peak memory 204464 kb
Host smart-29573067-4b77-4dbf-a227-f0b9c8013363
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295561462 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.3
295561462
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.59270102
Short name T310
Test name
Test status
Simulation time 424567309 ps
CPU time 7.58 seconds
Started Apr 15 12:30:50 PM PDT 24
Finished Apr 15 12:30:58 PM PDT 24
Peak memory 204772 kb
Host smart-36973ff4-9434-4e47-a2e6-93ff0cd94124
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59270102 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_cs
r_outstanding.59270102
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2321449848
Short name T263
Test name
Test status
Simulation time 880088438 ps
CPU time 9.56 seconds
Started Apr 15 12:30:47 PM PDT 24
Finished Apr 15 12:30:58 PM PDT 24
Peak memory 213044 kb
Host smart-8a2d46f7-ef51-4d72-b15d-f244cb1f9b3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321449848 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.2321449848
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.3308287322
Short name T284
Test name
Test status
Simulation time 239594667 ps
CPU time 2.56 seconds
Started Apr 15 12:30:46 PM PDT 24
Finished Apr 15 12:30:50 PM PDT 24
Peak memory 218116 kb
Host smart-9beadd4a-e839-4f45-8729-e94095ba46bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308287322 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.3308287322
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.3902049042
Short name T111
Test name
Test status
Simulation time 83519104 ps
CPU time 2.34 seconds
Started Apr 15 12:30:47 PM PDT 24
Finished Apr 15 12:30:50 PM PDT 24
Peak memory 212916 kb
Host smart-627275c9-aa6c-45a5-a001-1b3312e7f5b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902049042 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.3902049042
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.1428677869
Short name T332
Test name
Test status
Simulation time 520371614 ps
CPU time 2.35 seconds
Started Apr 15 12:30:44 PM PDT 24
Finished Apr 15 12:30:47 PM PDT 24
Peak memory 204640 kb
Host smart-4e0b4357-2396-4680-b1ae-98a163248e53
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428677869 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.1
428677869
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2774917399
Short name T301
Test name
Test status
Simulation time 24219727 ps
CPU time 0.71 seconds
Started Apr 15 12:30:38 PM PDT 24
Finished Apr 15 12:30:40 PM PDT 24
Peak memory 204428 kb
Host smart-bf0825a0-42bb-484d-a82d-eec608910bf7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774917399 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.2
774917399
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.1021224463
Short name T101
Test name
Test status
Simulation time 313288222 ps
CPU time 4.53 seconds
Started Apr 15 12:30:38 PM PDT 24
Finished Apr 15 12:30:44 PM PDT 24
Peak memory 204824 kb
Host smart-c4c95730-4dec-4cfa-98a3-8db61d436d11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021224463 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.1021224463
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.1872836265
Short name T75
Test name
Test status
Simulation time 99626745 ps
CPU time 4.93 seconds
Started Apr 15 12:30:41 PM PDT 24
Finished Apr 15 12:30:52 PM PDT 24
Peak memory 213064 kb
Host smart-843b67e1-b1a8-489e-bdad-eea621c64930
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872836265 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.1872836265
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2253666240
Short name T129
Test name
Test status
Simulation time 544085028 ps
CPU time 9.64 seconds
Started Apr 15 12:30:44 PM PDT 24
Finished Apr 15 12:30:55 PM PDT 24
Peak memory 213008 kb
Host smart-4332ff4b-1d48-45e9-84ce-3cbcbf9a0ffe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253666240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.2253666240
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3853588986
Short name T120
Test name
Test status
Simulation time 523367705 ps
CPU time 2.47 seconds
Started Apr 15 12:30:44 PM PDT 24
Finished Apr 15 12:30:47 PM PDT 24
Peak memory 216012 kb
Host smart-c2197c6e-2a0b-45f5-8277-d4f05ce38c87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853588986 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.3853588986
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.1656159243
Short name T302
Test name
Test status
Simulation time 95697474 ps
CPU time 1.48 seconds
Started Apr 15 12:30:42 PM PDT 24
Finished Apr 15 12:30:45 PM PDT 24
Peak memory 212884 kb
Host smart-9d1ab1e1-1bf7-4dd1-8f9f-75a8e614335a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656159243 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.1656159243
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.38416152
Short name T274
Test name
Test status
Simulation time 722821873 ps
CPU time 2.87 seconds
Started Apr 15 12:30:42 PM PDT 24
Finished Apr 15 12:30:46 PM PDT 24
Peak memory 204404 kb
Host smart-11760cfd-5aaf-4c9e-8a34-784c61c1d36c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38416152 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.38416152
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.4122792019
Short name T276
Test name
Test status
Simulation time 60105165 ps
CPU time 0.75 seconds
Started Apr 15 12:30:38 PM PDT 24
Finished Apr 15 12:30:41 PM PDT 24
Peak memory 204404 kb
Host smart-8a04c0df-5dd2-4115-9dd1-b16f86d9ca19
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122792019 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.4
122792019
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3800527012
Short name T99
Test name
Test status
Simulation time 76442713 ps
CPU time 3.37 seconds
Started Apr 15 12:30:39 PM PDT 24
Finished Apr 15 12:30:44 PM PDT 24
Peak memory 204888 kb
Host smart-3cb950d9-c32f-42a1-9938-60918bb828fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800527012 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.3800527012
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.4094726680
Short name T377
Test name
Test status
Simulation time 438614349 ps
CPU time 2.52 seconds
Started Apr 15 12:30:42 PM PDT 24
Finished Apr 15 12:30:46 PM PDT 24
Peak memory 213028 kb
Host smart-617ba357-dfbc-46b6-91cc-e7b94c782cf1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094726680 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.4094726680
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.464503265
Short name T132
Test name
Test status
Simulation time 1858542784 ps
CPU time 19.65 seconds
Started Apr 15 12:30:44 PM PDT 24
Finished Apr 15 12:31:05 PM PDT 24
Peak memory 212936 kb
Host smart-57f8be37-f40b-4991-8016-87ecc38f8d83
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464503265 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.464503265
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1983254662
Short name T294
Test name
Test status
Simulation time 816445326 ps
CPU time 3.53 seconds
Started Apr 15 12:30:41 PM PDT 24
Finished Apr 15 12:30:45 PM PDT 24
Peak memory 216716 kb
Host smart-d67e5b33-d064-4c3b-bee3-050964f64800
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983254662 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.1983254662
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.2908052804
Short name T60
Test name
Test status
Simulation time 403268033 ps
CPU time 1.39 seconds
Started Apr 15 12:30:46 PM PDT 24
Finished Apr 15 12:30:49 PM PDT 24
Peak memory 218148 kb
Host smart-359872ec-a96f-4771-ac5c-0a0d1edd9efc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908052804 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.2908052804
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.626991584
Short name T251
Test name
Test status
Simulation time 1627986130 ps
CPU time 1.81 seconds
Started Apr 15 12:30:39 PM PDT 24
Finished Apr 15 12:30:42 PM PDT 24
Peak memory 204764 kb
Host smart-a54bfa63-fca8-40bd-b071-8ce3f2b872a7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626991584 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.626991584
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.283676209
Short name T65
Test name
Test status
Simulation time 122555585 ps
CPU time 0.77 seconds
Started Apr 15 12:30:54 PM PDT 24
Finished Apr 15 12:30:56 PM PDT 24
Peak memory 204396 kb
Host smart-06408615-d7e6-4cf6-899f-43f265374435
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283676209 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.283676209
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2700752936
Short name T360
Test name
Test status
Simulation time 83968057 ps
CPU time 3.57 seconds
Started Apr 15 12:30:46 PM PDT 24
Finished Apr 15 12:30:51 PM PDT 24
Peak memory 204708 kb
Host smart-614a5dd7-d78d-4fff-b4a0-ce18cabfc8a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700752936 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_
csr_outstanding.2700752936
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2808322788
Short name T77
Test name
Test status
Simulation time 482074560 ps
CPU time 4.96 seconds
Started Apr 15 12:30:38 PM PDT 24
Finished Apr 15 12:30:45 PM PDT 24
Peak memory 213080 kb
Host smart-f9ae6f00-7534-4a11-9973-8734f9fe9d9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808322788 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.2808322788
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.895399826
Short name T297
Test name
Test status
Simulation time 389458666 ps
CPU time 8.1 seconds
Started Apr 15 12:30:37 PM PDT 24
Finished Apr 15 12:30:46 PM PDT 24
Peak memory 213008 kb
Host smart-75a16352-0680-49f8-be76-1863a898fe6c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895399826 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.895399826
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3348312105
Short name T311
Test name
Test status
Simulation time 134584917 ps
CPU time 2.25 seconds
Started Apr 15 12:30:52 PM PDT 24
Finished Apr 15 12:30:55 PM PDT 24
Peak memory 216952 kb
Host smart-6b0edf64-4212-4139-8a17-9701a50bf8a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348312105 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.3348312105
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1623179684
Short name T84
Test name
Test status
Simulation time 57426977 ps
CPU time 1.59 seconds
Started Apr 15 12:30:50 PM PDT 24
Finished Apr 15 12:30:53 PM PDT 24
Peak memory 212856 kb
Host smart-872c24ca-314a-4bb5-9a35-c0094dd0f143
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623179684 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.1623179684
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.2937161532
Short name T349
Test name
Test status
Simulation time 173613826 ps
CPU time 1.28 seconds
Started Apr 15 12:30:54 PM PDT 24
Finished Apr 15 12:30:56 PM PDT 24
Peak memory 204572 kb
Host smart-8ed21e9f-1249-411b-8422-dbb57b2eed6b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937161532 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.2
937161532
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1853474275
Short name T249
Test name
Test status
Simulation time 122290685 ps
CPU time 0.73 seconds
Started Apr 15 12:30:50 PM PDT 24
Finished Apr 15 12:30:52 PM PDT 24
Peak memory 204408 kb
Host smart-ecb0e75e-51d6-487e-aee6-e1dfae14b252
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853474275 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.1
853474275
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.2588556980
Short name T81
Test name
Test status
Simulation time 159548008 ps
CPU time 3.54 seconds
Started Apr 15 12:30:42 PM PDT 24
Finished Apr 15 12:30:47 PM PDT 24
Peak memory 204792 kb
Host smart-fccabaf0-87c1-4553-8716-bb01ce936af5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588556980 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.2588556980
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.2962725695
Short name T68
Test name
Test status
Simulation time 395951730 ps
CPU time 4.91 seconds
Started Apr 15 12:30:54 PM PDT 24
Finished Apr 15 12:31:00 PM PDT 24
Peak memory 212992 kb
Host smart-8dc6763f-ed02-4e29-aec6-2b4f7fb64c4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962725695 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.2962725695
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.3421954381
Short name T130
Test name
Test status
Simulation time 737563011 ps
CPU time 16.95 seconds
Started Apr 15 12:30:43 PM PDT 24
Finished Apr 15 12:31:01 PM PDT 24
Peak memory 212924 kb
Host smart-bdbf3aaf-5201-4b2d-aeef-be70c3dce90c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421954381 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.3421954381
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.4051217018
Short name T199
Test name
Test status
Simulation time 27482090 ps
CPU time 0.75 seconds
Started Apr 15 12:35:00 PM PDT 24
Finished Apr 15 12:35:02 PM PDT 24
Peak memory 205024 kb
Host smart-f8cf68e0-dab8-471d-bc50-85d6de3b79d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051217018 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.4051217018
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.3021043621
Short name T219
Test name
Test status
Simulation time 2939757990 ps
CPU time 6.97 seconds
Started Apr 15 12:35:04 PM PDT 24
Finished Apr 15 12:35:11 PM PDT 24
Peak memory 205452 kb
Host smart-dc73be0d-6be2-4ee2-8c40-1de8e4b396ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021043621 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.3021043621
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.1780798426
Short name T10
Test name
Test status
Simulation time 2193754331 ps
CPU time 7.1 seconds
Started Apr 15 12:35:00 PM PDT 24
Finished Apr 15 12:35:09 PM PDT 24
Peak memory 205324 kb
Host smart-737c7f08-8bf9-447d-869b-55b65b7b2f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780798426 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.1780798426
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.1030602594
Short name T4
Test name
Test status
Simulation time 2002809908 ps
CPU time 4.7 seconds
Started Apr 15 12:34:58 PM PDT 24
Finished Apr 15 12:35:04 PM PDT 24
Peak memory 205232 kb
Host smart-6a6c32c9-c4f9-4304-8b89-4bcef8259cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030602594 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.1030602594
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.3938631141
Short name T24
Test name
Test status
Simulation time 99593685 ps
CPU time 0.8 seconds
Started Apr 15 12:35:00 PM PDT 24
Finished Apr 15 12:35:03 PM PDT 24
Peak memory 205092 kb
Host smart-0b5033a8-d26c-4bea-a6e9-8385c8d278e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938631141 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.3938631141
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.1024121349
Short name T176
Test name
Test status
Simulation time 1837866688 ps
CPU time 3.19 seconds
Started Apr 15 12:34:58 PM PDT 24
Finished Apr 15 12:35:02 PM PDT 24
Peak memory 205292 kb
Host smart-d353cecd-1b92-43b3-981b-bf3240677f18
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1024121349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t
l_access.1024121349
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.1723211582
Short name T52
Test name
Test status
Simulation time 406539745 ps
CPU time 1.92 seconds
Started Apr 15 12:35:04 PM PDT 24
Finished Apr 15 12:35:06 PM PDT 24
Peak memory 205048 kb
Host smart-fdb54068-19de-4a14-b4c1-5ee8993ff7ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723211582 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.1723211582
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.3137882133
Short name T235
Test name
Test status
Simulation time 54081744 ps
CPU time 0.7 seconds
Started Apr 15 12:34:55 PM PDT 24
Finished Apr 15 12:34:56 PM PDT 24
Peak memory 204892 kb
Host smart-2d3fb215-f878-4759-b2ef-67183a1417de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137882133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.3137882133
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.3799168961
Short name T165
Test name
Test status
Simulation time 158626165 ps
CPU time 0.92 seconds
Started Apr 15 12:34:57 PM PDT 24
Finished Apr 15 12:34:58 PM PDT 24
Peak memory 204864 kb
Host smart-7f2471dd-6193-442f-b9c1-2234ee754ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799168961 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.3799168961
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.298060238
Short name T57
Test name
Test status
Simulation time 1217535401 ps
CPU time 2.48 seconds
Started Apr 15 12:34:56 PM PDT 24
Finished Apr 15 12:34:59 PM PDT 24
Peak memory 205096 kb
Host smart-bbf91b6c-62d6-487c-b1ca-898e6403eb54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298060238 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.298060238
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.2386249046
Short name T62
Test name
Test status
Simulation time 27064979 ps
CPU time 0.73 seconds
Started Apr 15 12:34:57 PM PDT 24
Finished Apr 15 12:34:58 PM PDT 24
Peak memory 204904 kb
Host smart-1186e51f-d599-4d1f-b242-cdeb59a68529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386249046 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.2386249046
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.1034100707
Short name T73
Test name
Test status
Simulation time 242410938 ps
CPU time 0.78 seconds
Started Apr 15 12:35:00 PM PDT 24
Finished Apr 15 12:35:03 PM PDT 24
Peak memory 205000 kb
Host smart-cb296b75-7622-45d9-b823-a165ed11ec4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034100707 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.1034100707
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.3135933886
Short name T50
Test name
Test status
Simulation time 443796185 ps
CPU time 1.31 seconds
Started Apr 15 12:35:00 PM PDT 24
Finished Apr 15 12:35:04 PM PDT 24
Peak memory 205228 kb
Host smart-c13eb8c7-410e-4636-8689-a770a480271b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135933886 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.3135933886
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.9840368
Short name T137
Test name
Test status
Simulation time 3050009950 ps
CPU time 1.97 seconds
Started Apr 15 12:34:59 PM PDT 24
Finished Apr 15 12:35:02 PM PDT 24
Peak memory 205312 kb
Host smart-2311d049-c8c5-490b-a320-9bdab3b73ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9840368 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.9840368
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.3558672030
Short name T193
Test name
Test status
Simulation time 1267074008 ps
CPU time 5.03 seconds
Started Apr 15 12:34:58 PM PDT 24
Finished Apr 15 12:35:03 PM PDT 24
Peak memory 205272 kb
Host smart-9f6cec5a-ccda-461c-aa1f-c7967dfb2c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558672030 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.3558672030
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.703308061
Short name T43
Test name
Test status
Simulation time 91175398 ps
CPU time 1.07 seconds
Started Apr 15 12:34:58 PM PDT 24
Finished Apr 15 12:35:00 PM PDT 24
Peak memory 229572 kb
Host smart-aad4e224-1b7e-4dd8-8de5-659d87569397
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703308061 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.703308061
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.493996376
Short name T228
Test name
Test status
Simulation time 481117462 ps
CPU time 1.17 seconds
Started Apr 15 12:34:59 PM PDT 24
Finished Apr 15 12:35:02 PM PDT 24
Peak memory 204884 kb
Host smart-9c21b1f9-43b4-4ecf-9b34-65d441ffff67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493996376 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.493996376
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.1852296923
Short name T58
Test name
Test status
Simulation time 1947949447 ps
CPU time 4.34 seconds
Started Apr 15 12:34:58 PM PDT 24
Finished Apr 15 12:35:04 PM PDT 24
Peak memory 205176 kb
Host smart-050db1ed-6342-478d-bcd5-a78d65c22e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852296923 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.1852296923
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.4015892674
Short name T177
Test name
Test status
Simulation time 59436415 ps
CPU time 0.79 seconds
Started Apr 15 12:35:00 PM PDT 24
Finished Apr 15 12:35:03 PM PDT 24
Peak memory 205084 kb
Host smart-d1c798b7-7544-4270-bac8-8840b58dedb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015892674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.4015892674
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.4109360226
Short name T54
Test name
Test status
Simulation time 56282412 ps
CPU time 0.83 seconds
Started Apr 15 12:35:01 PM PDT 24
Finished Apr 15 12:35:04 PM PDT 24
Peak memory 205048 kb
Host smart-27e6d6c9-8c75-4b31-be6d-4ff327cb7144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109360226 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.4109360226
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.3976625577
Short name T48
Test name
Test status
Simulation time 231434405 ps
CPU time 0.84 seconds
Started Apr 15 12:34:59 PM PDT 24
Finished Apr 15 12:35:01 PM PDT 24
Peak memory 204904 kb
Host smart-f5ba0425-bea5-419f-b517-c66e11011e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976625577 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.3976625577
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.1432392912
Short name T231
Test name
Test status
Simulation time 1975825685 ps
CPU time 4.56 seconds
Started Apr 15 12:35:04 PM PDT 24
Finished Apr 15 12:35:09 PM PDT 24
Peak memory 205332 kb
Host smart-3e5252b9-5d77-4be1-b169-22b615fb8121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432392912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.1432392912
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.3488811262
Short name T138
Test name
Test status
Simulation time 236014413 ps
CPU time 0.69 seconds
Started Apr 15 12:35:05 PM PDT 24
Finished Apr 15 12:35:07 PM PDT 24
Peak memory 205068 kb
Host smart-0505b8b1-d808-4cff-9f80-f422def43f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488811262 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.3488811262
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.3539145148
Short name T201
Test name
Test status
Simulation time 2124010658 ps
CPU time 8.47 seconds
Started Apr 15 12:34:58 PM PDT 24
Finished Apr 15 12:35:07 PM PDT 24
Peak memory 205352 kb
Host smart-cf55635d-677d-4e36-a267-fc5c12f7aa7d
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3539145148 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.3539145148
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.1546126270
Short name T134
Test name
Test status
Simulation time 224799682 ps
CPU time 0.91 seconds
Started Apr 15 12:34:59 PM PDT 24
Finished Apr 15 12:35:01 PM PDT 24
Peak memory 205040 kb
Host smart-c7d10732-0461-4144-b8a9-ce301ea43867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546126270 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.1546126270
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.4230436564
Short name T221
Test name
Test status
Simulation time 59795353 ps
CPU time 0.91 seconds
Started Apr 15 12:34:59 PM PDT 24
Finished Apr 15 12:35:01 PM PDT 24
Peak memory 204992 kb
Host smart-d24d013c-b91d-4d8c-b469-9feccbe6248d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230436564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.4230436564
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.553412878
Short name T32
Test name
Test status
Simulation time 476076725 ps
CPU time 1.05 seconds
Started Apr 15 12:34:59 PM PDT 24
Finished Apr 15 12:35:01 PM PDT 24
Peak memory 204876 kb
Host smart-d1bd0209-064f-43c4-b426-6d5c834ee9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553412878 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.553412878
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.3648276542
Short name T20
Test name
Test status
Simulation time 240223145 ps
CPU time 1.02 seconds
Started Apr 15 12:35:01 PM PDT 24
Finished Apr 15 12:35:03 PM PDT 24
Peak memory 204856 kb
Host smart-49b619ef-1247-4612-86c4-120b678e666d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648276542 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.3648276542
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.3277262713
Short name T192
Test name
Test status
Simulation time 182756557 ps
CPU time 1.28 seconds
Started Apr 15 12:35:05 PM PDT 24
Finished Apr 15 12:35:07 PM PDT 24
Peak memory 205132 kb
Host smart-cd68d301-f2d5-402f-8598-27cd34af8bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277262713 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.3277262713
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.3084013564
Short name T61
Test name
Test status
Simulation time 31343331 ps
CPU time 0.7 seconds
Started Apr 15 12:34:59 PM PDT 24
Finished Apr 15 12:35:01 PM PDT 24
Peak memory 205004 kb
Host smart-c4c608c8-107b-43b2-8b57-a7bbeb07a32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084013564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.3084013564
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.2383316905
Short name T7
Test name
Test status
Simulation time 126649393 ps
CPU time 0.76 seconds
Started Apr 15 12:35:01 PM PDT 24
Finished Apr 15 12:35:03 PM PDT 24
Peak memory 205036 kb
Host smart-bc7a2374-60f2-4549-8e4e-19c0ce7a38f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383316905 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.2383316905
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.3296783391
Short name T19
Test name
Test status
Simulation time 287102825 ps
CPU time 0.91 seconds
Started Apr 15 12:34:57 PM PDT 24
Finished Apr 15 12:34:58 PM PDT 24
Peak memory 204996 kb
Host smart-a91bd46b-d704-4d23-8d36-8ecacc9d57ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296783391 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.3296783391
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.1362912208
Short name T135
Test name
Test status
Simulation time 818338557 ps
CPU time 3.33 seconds
Started Apr 15 12:34:58 PM PDT 24
Finished Apr 15 12:35:02 PM PDT 24
Peak memory 205312 kb
Host smart-1745c1e6-51e4-4cb5-9ed7-227f7f421bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362912208 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.1362912208
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.3862817151
Short name T12
Test name
Test status
Simulation time 161694333 ps
CPU time 1.06 seconds
Started Apr 15 12:34:59 PM PDT 24
Finished Apr 15 12:35:02 PM PDT 24
Peak memory 205256 kb
Host smart-7b89f1a1-2cfa-452e-9b8f-2ebfe461ec8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862817151 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.3862817151
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.3235828614
Short name T56
Test name
Test status
Simulation time 59822671 ps
CPU time 0.84 seconds
Started Apr 15 12:35:00 PM PDT 24
Finished Apr 15 12:35:02 PM PDT 24
Peak memory 205084 kb
Host smart-d6f0bc1c-cfcd-446a-9884-83cb73a0ac46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235828614 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.3235828614
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.3514325243
Short name T51
Test name
Test status
Simulation time 24778251 ps
CPU time 0.82 seconds
Started Apr 15 12:34:59 PM PDT 24
Finished Apr 15 12:35:01 PM PDT 24
Peak memory 213348 kb
Host smart-7b4f50cc-845f-42a5-a5e8-1537df61c1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514325243 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.3514325243
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.1542692419
Short name T3
Test name
Test status
Simulation time 4976279546 ps
CPU time 7.92 seconds
Started Apr 15 12:35:03 PM PDT 24
Finished Apr 15 12:35:12 PM PDT 24
Peak memory 213700 kb
Host smart-e9b27ebc-6de9-43a1-96ca-eaa4c8f1bc43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542692419 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.1542692419
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.1434986199
Short name T209
Test name
Test status
Simulation time 414740194 ps
CPU time 1.36 seconds
Started Apr 15 12:34:59 PM PDT 24
Finished Apr 15 12:35:02 PM PDT 24
Peak memory 204924 kb
Host smart-1c4dab51-6714-4d7e-beef-efe899aeaa54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434986199 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.1434986199
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.1366620017
Short name T59
Test name
Test status
Simulation time 122393030 ps
CPU time 0.71 seconds
Started Apr 15 12:35:19 PM PDT 24
Finished Apr 15 12:35:21 PM PDT 24
Peak memory 204984 kb
Host smart-d3657aa6-742c-480d-97be-607b734884fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366620017 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.1366620017
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.2973918694
Short name T202
Test name
Test status
Simulation time 1399569355 ps
CPU time 3.55 seconds
Started Apr 15 12:35:21 PM PDT 24
Finished Apr 15 12:35:25 PM PDT 24
Peak memory 205400 kb
Host smart-58c9ab45-c2c6-4d62-8f1a-2d79a51a73d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973918694 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.2973918694
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.3520119493
Short name T222
Test name
Test status
Simulation time 4504954936 ps
CPU time 4.07 seconds
Started Apr 15 12:35:19 PM PDT 24
Finished Apr 15 12:35:24 PM PDT 24
Peak memory 205456 kb
Host smart-4f0f13ec-58b0-4b4b-84c2-79d0325d9e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520119493 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.3520119493
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.2120631079
Short name T197
Test name
Test status
Simulation time 26483351 ps
CPU time 0.72 seconds
Started Apr 15 12:35:23 PM PDT 24
Finished Apr 15 12:35:24 PM PDT 24
Peak memory 205044 kb
Host smart-c6fda6b8-0164-4a0a-85db-aa4b51272bbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120631079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.2120631079
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.1209766157
Short name T207
Test name
Test status
Simulation time 13421531193 ps
CPU time 39.11 seconds
Started Apr 15 12:35:24 PM PDT 24
Finished Apr 15 12:36:04 PM PDT 24
Peak memory 213640 kb
Host smart-1c62b71a-4e74-4670-9a07-504829a48bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209766157 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.1209766157
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.356704410
Short name T123
Test name
Test status
Simulation time 2182425224 ps
CPU time 7.52 seconds
Started Apr 15 12:35:24 PM PDT 24
Finished Apr 15 12:35:32 PM PDT 24
Peak memory 214780 kb
Host smart-7eeefd01-b7c8-41db-a0f4-e6cf9c523092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356704410 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.356704410
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.1464907066
Short name T11
Test name
Test status
Simulation time 594407374 ps
CPU time 3.21 seconds
Started Apr 15 12:35:19 PM PDT 24
Finished Apr 15 12:35:23 PM PDT 24
Peak memory 205308 kb
Host smart-dfe104c2-f371-456a-8e45-eda97dcd1815
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1464907066 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_
tl_access.1464907066
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.1568096876
Short name T185
Test name
Test status
Simulation time 4523296968 ps
CPU time 9.74 seconds
Started Apr 15 12:35:25 PM PDT 24
Finished Apr 15 12:35:36 PM PDT 24
Peak memory 205424 kb
Host smart-8a2f6497-f4c4-4329-b897-ba75dcea3597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568096876 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.1568096876
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_stress_all.476124215
Short name T136
Test name
Test status
Simulation time 4735333275 ps
CPU time 16.47 seconds
Started Apr 15 12:35:39 PM PDT 24
Finished Apr 15 12:35:57 PM PDT 24
Peak memory 205368 kb
Host smart-968c5641-9b64-4c64-a886-289b77e428c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476124215 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.476124215
Directory /workspace/11.rv_dm_stress_all/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.1859221684
Short name T164
Test name
Test status
Simulation time 21357040 ps
CPU time 0.75 seconds
Started Apr 15 12:35:32 PM PDT 24
Finished Apr 15 12:35:33 PM PDT 24
Peak memory 205016 kb
Host smart-fdb4026e-8b18-42ee-a1d4-d2456fb2c500
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859221684 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.1859221684
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.4192768152
Short name T236
Test name
Test status
Simulation time 2813801472 ps
CPU time 4.78 seconds
Started Apr 15 12:35:26 PM PDT 24
Finished Apr 15 12:35:31 PM PDT 24
Peak memory 205524 kb
Host smart-40cdf838-b85c-405f-a7aa-e1aaeb158341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192768152 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.4192768152
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.4058245437
Short name T69
Test name
Test status
Simulation time 1381481273 ps
CPU time 3.83 seconds
Started Apr 15 12:35:31 PM PDT 24
Finished Apr 15 12:35:35 PM PDT 24
Peak memory 205280 kb
Host smart-5b088df6-7a92-4f8f-87a4-b9b0350ddc3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058245437 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.4058245437
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.315050223
Short name T225
Test name
Test status
Simulation time 5564366735 ps
CPU time 20.05 seconds
Started Apr 15 12:35:25 PM PDT 24
Finished Apr 15 12:35:46 PM PDT 24
Peak memory 213652 kb
Host smart-06485549-0897-43a3-b361-a1118585dab9
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=315050223 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_t
l_access.315050223
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.2013820946
Short name T8
Test name
Test status
Simulation time 3385888613 ps
CPU time 6.36 seconds
Started Apr 15 12:35:25 PM PDT 24
Finished Apr 15 12:35:32 PM PDT 24
Peak memory 205492 kb
Host smart-5929d101-096f-4376-841b-3300157464f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013820946 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.2013820946
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_stress_all.2949011635
Short name T9
Test name
Test status
Simulation time 5994660736 ps
CPU time 6.67 seconds
Started Apr 15 12:35:34 PM PDT 24
Finished Apr 15 12:35:41 PM PDT 24
Peak memory 205340 kb
Host smart-b8a757f4-b301-4656-ade2-ce34dc6d068d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949011635 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.2949011635
Directory /workspace/12.rv_dm_stress_all/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.3917488826
Short name T162
Test name
Test status
Simulation time 26957820 ps
CPU time 0.69 seconds
Started Apr 15 12:35:29 PM PDT 24
Finished Apr 15 12:35:30 PM PDT 24
Peak memory 205108 kb
Host smart-e4fe1c18-2447-4cdb-a13f-f1a56ac4494e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917488826 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.3917488826
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.1088703875
Short name T227
Test name
Test status
Simulation time 1198221948 ps
CPU time 4.93 seconds
Started Apr 15 12:35:28 PM PDT 24
Finished Apr 15 12:35:34 PM PDT 24
Peak memory 205412 kb
Host smart-50bb6e37-f6f2-4e74-b0fc-907d9e481d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088703875 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.1088703875
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.2615299035
Short name T214
Test name
Test status
Simulation time 13410797269 ps
CPU time 43.47 seconds
Started Apr 15 12:35:36 PM PDT 24
Finished Apr 15 12:36:20 PM PDT 24
Peak memory 213636 kb
Host smart-cd6e707c-c6e1-42c1-9e6f-19466f0c219c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615299035 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.2615299035
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.817925611
Short name T203
Test name
Test status
Simulation time 2886154637 ps
CPU time 5.67 seconds
Started Apr 15 12:35:33 PM PDT 24
Finished Apr 15 12:35:40 PM PDT 24
Peak memory 205488 kb
Host smart-3b178116-0b38-47aa-a8ee-1b83f0106625
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=817925611 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_t
l_access.817925611
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.2150040754
Short name T229
Test name
Test status
Simulation time 4021408584 ps
CPU time 3.49 seconds
Started Apr 15 12:35:38 PM PDT 24
Finished Apr 15 12:35:42 PM PDT 24
Peak memory 205372 kb
Host smart-71b6ea8b-aa93-4df5-ac81-3d74f348407a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150040754 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.2150040754
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.1524902721
Short name T149
Test name
Test status
Simulation time 81315209 ps
CPU time 0.72 seconds
Started Apr 15 12:35:38 PM PDT 24
Finished Apr 15 12:35:39 PM PDT 24
Peak memory 205032 kb
Host smart-864f4e91-2b99-4d4d-b3c2-983ff368b5c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524902721 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.1524902721
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.3211935310
Short name T173
Test name
Test status
Simulation time 13415466053 ps
CPU time 42.72 seconds
Started Apr 15 12:35:35 PM PDT 24
Finished Apr 15 12:36:18 PM PDT 24
Peak memory 215844 kb
Host smart-9911ed8c-0250-4deb-9cf5-ea12b4c0c08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211935310 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.3211935310
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.920247167
Short name T172
Test name
Test status
Simulation time 3726406071 ps
CPU time 5.55 seconds
Started Apr 15 12:35:34 PM PDT 24
Finished Apr 15 12:35:40 PM PDT 24
Peak memory 213644 kb
Host smart-dbe1f45c-fc85-48c7-8e5d-24aad3135702
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=920247167 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_t
l_access.920247167
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.222350288
Short name T189
Test name
Test status
Simulation time 4636241581 ps
CPU time 8.47 seconds
Started Apr 15 12:35:32 PM PDT 24
Finished Apr 15 12:35:41 PM PDT 24
Peak memory 205508 kb
Host smart-de3ae9c1-e77f-428d-b023-912052d13a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222350288 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.222350288
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.1378228564
Short name T1
Test name
Test status
Simulation time 78194646 ps
CPU time 0.72 seconds
Started Apr 15 12:35:35 PM PDT 24
Finished Apr 15 12:35:36 PM PDT 24
Peak memory 205088 kb
Host smart-8d0e7156-32f9-4695-a5ea-e887edfe8891
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378228564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.1378228564
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.1122688455
Short name T220
Test name
Test status
Simulation time 5964337621 ps
CPU time 20.71 seconds
Started Apr 15 12:35:35 PM PDT 24
Finished Apr 15 12:35:57 PM PDT 24
Peak memory 215368 kb
Host smart-d78c1ed7-6ffe-4736-9e51-bc1f71b915e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122688455 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.1122688455
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.2955140842
Short name T198
Test name
Test status
Simulation time 2599068564 ps
CPU time 7.55 seconds
Started Apr 15 12:35:39 PM PDT 24
Finished Apr 15 12:35:48 PM PDT 24
Peak memory 205476 kb
Host smart-9f25906a-7b45-43f1-80e8-0d0db8c3a2d3
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2955140842 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_
tl_access.2955140842
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.2737204955
Short name T237
Test name
Test status
Simulation time 815053506 ps
CPU time 1.76 seconds
Started Apr 15 12:35:39 PM PDT 24
Finished Apr 15 12:35:42 PM PDT 24
Peak memory 205448 kb
Host smart-293d6533-6b69-4b3f-987e-eb0820ff5524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737204955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.2737204955
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.2333666670
Short name T2
Test name
Test status
Simulation time 38118623 ps
CPU time 0.73 seconds
Started Apr 15 12:35:37 PM PDT 24
Finished Apr 15 12:35:38 PM PDT 24
Peak memory 205020 kb
Host smart-b8eb8125-29a4-4d7d-969b-894d8df5762a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333666670 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.2333666670
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.3430085794
Short name T178
Test name
Test status
Simulation time 6236680594 ps
CPU time 9.1 seconds
Started Apr 15 12:35:38 PM PDT 24
Finished Apr 15 12:35:48 PM PDT 24
Peak memory 213672 kb
Host smart-392f7225-6af3-4f3d-8708-5edf83141e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430085794 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.3430085794
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.335206167
Short name T215
Test name
Test status
Simulation time 4704431977 ps
CPU time 16.64 seconds
Started Apr 15 12:35:39 PM PDT 24
Finished Apr 15 12:35:56 PM PDT 24
Peak memory 205564 kb
Host smart-f0e7375d-20e3-4fa9-af9b-e2a66914265b
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=335206167 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_t
l_access.335206167
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.1252833274
Short name T167
Test name
Test status
Simulation time 713674462 ps
CPU time 3.38 seconds
Started Apr 15 12:35:44 PM PDT 24
Finished Apr 15 12:35:48 PM PDT 24
Peak memory 205256 kb
Host smart-a4364fee-40ac-439c-8af6-014ed1c6f98c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252833274 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.1252833274
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.799594038
Short name T194
Test name
Test status
Simulation time 34448826 ps
CPU time 0.7 seconds
Started Apr 15 12:35:46 PM PDT 24
Finished Apr 15 12:35:48 PM PDT 24
Peak memory 205020 kb
Host smart-169cbd39-412e-494a-a263-7c187bb44fc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799594038 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.799594038
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.3755661525
Short name T234
Test name
Test status
Simulation time 21222700174 ps
CPU time 41.98 seconds
Started Apr 15 12:35:35 PM PDT 24
Finished Apr 15 12:36:18 PM PDT 24
Peak memory 213640 kb
Host smart-ff3d5963-aa72-4e6d-ad8c-742879f1e47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755661525 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.3755661525
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.2145041291
Short name T15
Test name
Test status
Simulation time 991734769 ps
CPU time 2.8 seconds
Started Apr 15 12:35:36 PM PDT 24
Finished Apr 15 12:35:40 PM PDT 24
Peak memory 205384 kb
Host smart-62bd537c-28ab-48b3-9012-a0b0c398ec1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145041291 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.2145041291
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.3584553649
Short name T182
Test name
Test status
Simulation time 13621528353 ps
CPU time 11.52 seconds
Started Apr 15 12:35:39 PM PDT 24
Finished Apr 15 12:35:51 PM PDT 24
Peak memory 213696 kb
Host smart-bb3a29b4-bd22-40c5-8f9b-8b9105088406
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3584553649 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_
tl_access.3584553649
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.1725458140
Short name T205
Test name
Test status
Simulation time 2356204212 ps
CPU time 10.47 seconds
Started Apr 15 12:35:33 PM PDT 24
Finished Apr 15 12:35:44 PM PDT 24
Peak memory 205576 kb
Host smart-637487ae-8d69-4d21-b6ab-071b9b636d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725458140 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.1725458140
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.1720709825
Short name T72
Test name
Test status
Simulation time 24918330 ps
CPU time 0.7 seconds
Started Apr 15 12:35:39 PM PDT 24
Finished Apr 15 12:35:41 PM PDT 24
Peak memory 205088 kb
Host smart-f3fff768-94a3-476d-8848-039139c62a64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720709825 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.1720709825
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.4263296442
Short name T190
Test name
Test status
Simulation time 4713747007 ps
CPU time 10.46 seconds
Started Apr 15 12:35:48 PM PDT 24
Finished Apr 15 12:35:59 PM PDT 24
Peak memory 213716 kb
Host smart-2f6d9a26-8150-4c48-b305-d46fb194b8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263296442 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.4263296442
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.2067620733
Short name T184
Test name
Test status
Simulation time 4838829814 ps
CPU time 19.27 seconds
Started Apr 15 12:35:40 PM PDT 24
Finished Apr 15 12:36:00 PM PDT 24
Peak memory 213732 kb
Host smart-d2959772-c01c-48f6-9184-458ed1f1a2fc
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2067620733 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_
tl_access.2067620733
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.300763581
Short name T206
Test name
Test status
Simulation time 3145285844 ps
CPU time 14.72 seconds
Started Apr 15 12:35:45 PM PDT 24
Finished Apr 15 12:36:01 PM PDT 24
Peak memory 205484 kb
Host smart-bc661ae0-76b5-4696-a99a-312663fd166a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300763581 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.300763581
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.2235580353
Short name T157
Test name
Test status
Simulation time 233516985 ps
CPU time 0.75 seconds
Started Apr 15 12:35:44 PM PDT 24
Finished Apr 15 12:35:45 PM PDT 24
Peak memory 205116 kb
Host smart-d2e1a4d7-6473-4ff6-8fc4-6c3c4bb8b9bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235580353 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.2235580353
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.2074251888
Short name T180
Test name
Test status
Simulation time 2626470241 ps
CPU time 4.64 seconds
Started Apr 15 12:35:34 PM PDT 24
Finished Apr 15 12:35:39 PM PDT 24
Peak memory 205460 kb
Host smart-11fdde32-54ba-4201-94d0-98e571999566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074251888 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.2074251888
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.671835500
Short name T169
Test name
Test status
Simulation time 12793235001 ps
CPU time 15.58 seconds
Started Apr 15 12:35:34 PM PDT 24
Finished Apr 15 12:35:51 PM PDT 24
Peak memory 215160 kb
Host smart-66fc631a-3814-4bbf-a4b2-f1f259adf282
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=671835500 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_t
l_access.671835500
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.1424831113
Short name T187
Test name
Test status
Simulation time 4996408534 ps
CPU time 7.08 seconds
Started Apr 15 12:35:35 PM PDT 24
Finished Apr 15 12:35:43 PM PDT 24
Peak memory 205548 kb
Host smart-2a4f4c0e-3d64-44a5-99dd-883672ee619a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424831113 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.1424831113
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.3037863487
Short name T45
Test name
Test status
Simulation time 22808901 ps
CPU time 0.69 seconds
Started Apr 15 12:35:10 PM PDT 24
Finished Apr 15 12:35:12 PM PDT 24
Peak memory 205076 kb
Host smart-aaadccbd-ade4-4bbd-81ed-ee77df23c39d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037863487 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.3037863487
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.344129108
Short name T211
Test name
Test status
Simulation time 10371209380 ps
CPU time 37.88 seconds
Started Apr 15 12:34:59 PM PDT 24
Finished Apr 15 12:35:38 PM PDT 24
Peak memory 215328 kb
Host smart-f7ce7496-c1b0-4c82-8a54-7bf5296a0d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344129108 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.344129108
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.818019007
Short name T183
Test name
Test status
Simulation time 688513492 ps
CPU time 4.54 seconds
Started Apr 15 12:35:01 PM PDT 24
Finished Apr 15 12:35:07 PM PDT 24
Peak memory 205356 kb
Host smart-8f21448a-5356-4c1d-b507-911408303bb3
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=818019007 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_tl
_access.818019007
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.2383238032
Short name T174
Test name
Test status
Simulation time 89594595 ps
CPU time 0.69 seconds
Started Apr 15 12:35:08 PM PDT 24
Finished Apr 15 12:35:09 PM PDT 24
Peak memory 204888 kb
Host smart-dbcda58f-9b3b-4b03-8ae0-c398d946d3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383238032 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.2383238032
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.1614267741
Short name T216
Test name
Test status
Simulation time 1715708446 ps
CPU time 6.09 seconds
Started Apr 15 12:34:58 PM PDT 24
Finished Apr 15 12:35:05 PM PDT 24
Peak memory 205308 kb
Host smart-da87975b-937e-4788-ba4a-611ab35dc813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614267741 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.1614267741
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.1300564673
Short name T44
Test name
Test status
Simulation time 154317678 ps
CPU time 1.45 seconds
Started Apr 15 12:35:10 PM PDT 24
Finished Apr 15 12:35:12 PM PDT 24
Peak memory 229240 kb
Host smart-2cb91df6-647c-4dd3-95af-98425ea6292b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300564673 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.1300564673
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all.2851417347
Short name T16
Test name
Test status
Simulation time 2234263479 ps
CPU time 4.69 seconds
Started Apr 15 12:35:01 PM PDT 24
Finished Apr 15 12:35:07 PM PDT 24
Peak memory 205432 kb
Host smart-caf7699a-5f3f-4f2e-ad61-3d6ebf276ab3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851417347 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.2851417347
Directory /workspace/2.rv_dm_stress_all/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.415612674
Short name T46
Test name
Test status
Simulation time 42264306 ps
CPU time 0.66 seconds
Started Apr 15 12:35:38 PM PDT 24
Finished Apr 15 12:35:39 PM PDT 24
Peak memory 204960 kb
Host smart-fd92df0c-89cf-479a-b177-66ebf5a71586
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415612674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.415612674
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/20.rv_dm_stress_all.3027056019
Short name T18
Test name
Test status
Simulation time 2062742281 ps
CPU time 4.7 seconds
Started Apr 15 12:35:46 PM PDT 24
Finished Apr 15 12:35:52 PM PDT 24
Peak memory 205212 kb
Host smart-fbb3c185-cbf2-4229-a8a0-e104d0e18952
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027056019 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.3027056019
Directory /workspace/20.rv_dm_stress_all/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.498774195
Short name T163
Test name
Test status
Simulation time 58475310 ps
CPU time 0.7 seconds
Started Apr 15 12:35:46 PM PDT 24
Finished Apr 15 12:35:47 PM PDT 24
Peak memory 205108 kb
Host smart-8227b4f5-6483-4ae0-9fa4-bbd5b44bb0c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498774195 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.498774195
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.2150455706
Short name T152
Test name
Test status
Simulation time 52250849 ps
CPU time 0.71 seconds
Started Apr 15 12:35:48 PM PDT 24
Finished Apr 15 12:35:50 PM PDT 24
Peak memory 205124 kb
Host smart-1a55f657-77c7-4d59-b2d4-3df739c02f1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150455706 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.2150455706
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.2923279879
Short name T181
Test name
Test status
Simulation time 18363419 ps
CPU time 0.71 seconds
Started Apr 15 12:35:41 PM PDT 24
Finished Apr 15 12:35:42 PM PDT 24
Peak memory 205024 kb
Host smart-e6afd9ba-5d02-48b3-8119-dc03daf2f537
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923279879 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.2923279879
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.2659127704
Short name T90
Test name
Test status
Simulation time 16137166 ps
CPU time 0.7 seconds
Started Apr 15 12:35:39 PM PDT 24
Finished Apr 15 12:35:41 PM PDT 24
Peak memory 205092 kb
Host smart-97bfb561-9b29-4332-9719-4231f86a9dbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659127704 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.2659127704
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.2607927650
Short name T144
Test name
Test status
Simulation time 18645140 ps
CPU time 0.78 seconds
Started Apr 15 12:35:48 PM PDT 24
Finished Apr 15 12:35:50 PM PDT 24
Peak memory 205060 kb
Host smart-f3f47abe-9239-4c13-8544-141942706dff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607927650 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.2607927650
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.3571764320
Short name T151
Test name
Test status
Simulation time 52960588 ps
CPU time 0.71 seconds
Started Apr 15 12:35:39 PM PDT 24
Finished Apr 15 12:35:41 PM PDT 24
Peak memory 205028 kb
Host smart-b364b917-ba35-4bad-88a8-cca41cb26c90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571764320 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.3571764320
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.1699281509
Short name T159
Test name
Test status
Simulation time 71671282 ps
CPU time 0.7 seconds
Started Apr 15 12:35:43 PM PDT 24
Finished Apr 15 12:35:44 PM PDT 24
Peak memory 205032 kb
Host smart-da56d97a-ed67-49b2-b2cb-e8be193a3cc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699281509 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.1699281509
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.841287381
Short name T155
Test name
Test status
Simulation time 57024740 ps
CPU time 0.73 seconds
Started Apr 15 12:35:38 PM PDT 24
Finished Apr 15 12:35:40 PM PDT 24
Peak memory 205028 kb
Host smart-2a7c2268-89df-4cb2-8ae3-26af358cf1de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841287381 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.841287381
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.3649942492
Short name T232
Test name
Test status
Simulation time 53014782 ps
CPU time 0.69 seconds
Started Apr 15 12:35:45 PM PDT 24
Finished Apr 15 12:35:47 PM PDT 24
Peak memory 205084 kb
Host smart-a49fd2fb-aef7-4438-96dd-c8bdcf87237b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649942492 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.3649942492
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.1802727837
Short name T143
Test name
Test status
Simulation time 58870952 ps
CPU time 0.68 seconds
Started Apr 15 12:35:10 PM PDT 24
Finished Apr 15 12:35:12 PM PDT 24
Peak memory 205012 kb
Host smart-25c5116b-1cc1-4a2b-bfc6-3ff0dafdbed9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802727837 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.1802727837
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.2025861596
Short name T218
Test name
Test status
Simulation time 2764415455 ps
CPU time 4.99 seconds
Started Apr 15 12:35:11 PM PDT 24
Finished Apr 15 12:35:17 PM PDT 24
Peak memory 214848 kb
Host smart-43477ea2-b73c-41bd-85d2-76c62c0867fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025861596 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.2025861596
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.2226007594
Short name T212
Test name
Test status
Simulation time 11972455763 ps
CPU time 36.82 seconds
Started Apr 15 12:35:10 PM PDT 24
Finished Apr 15 12:35:47 PM PDT 24
Peak memory 213632 kb
Host smart-c7d549ad-9154-4e52-867d-e0764ed4b332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226007594 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.2226007594
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.3264933858
Short name T175
Test name
Test status
Simulation time 2506604674 ps
CPU time 11.86 seconds
Started Apr 15 12:34:59 PM PDT 24
Finished Apr 15 12:35:12 PM PDT 24
Peak memory 205608 kb
Host smart-547a0388-1869-4ec5-ad69-55cfe26b9e82
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3264933858 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.3264933858
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.3954650665
Short name T166
Test name
Test status
Simulation time 51153039 ps
CPU time 0.77 seconds
Started Apr 15 12:35:08 PM PDT 24
Finished Apr 15 12:35:09 PM PDT 24
Peak memory 205168 kb
Host smart-7d6fdbe4-0a5f-4901-b77c-86a4e87fd656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954650665 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.3954650665
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.3602443867
Short name T191
Test name
Test status
Simulation time 12714967523 ps
CPU time 24.56 seconds
Started Apr 15 12:34:59 PM PDT 24
Finished Apr 15 12:35:25 PM PDT 24
Peak memory 213692 kb
Host smart-c8795d51-c274-479b-98d1-e12f6536ef3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602443867 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.3602443867
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.1987294959
Short name T26
Test name
Test status
Simulation time 485487272 ps
CPU time 1.36 seconds
Started Apr 15 12:35:09 PM PDT 24
Finished Apr 15 12:35:11 PM PDT 24
Peak memory 229296 kb
Host smart-476a4a0e-e07d-4f14-838b-bf14b3e2fcef
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987294959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.1987294959
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all.3797751113
Short name T80
Test name
Test status
Simulation time 698388038 ps
CPU time 2.9 seconds
Started Apr 15 12:35:09 PM PDT 24
Finished Apr 15 12:35:12 PM PDT 24
Peak memory 205220 kb
Host smart-ddb2a0ee-0b2d-4a10-8781-057b12b59710
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797751113 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.3797751113
Directory /workspace/3.rv_dm_stress_all/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.2062883138
Short name T161
Test name
Test status
Simulation time 27403804 ps
CPU time 0.72 seconds
Started Apr 15 12:35:45 PM PDT 24
Finished Apr 15 12:35:46 PM PDT 24
Peak memory 205124 kb
Host smart-783313d3-afa4-4879-8e1e-a5951e817de7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062883138 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.2062883138
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/30.rv_dm_stress_all.3749864611
Short name T5
Test name
Test status
Simulation time 852851196 ps
CPU time 2.11 seconds
Started Apr 15 12:35:48 PM PDT 24
Finished Apr 15 12:35:51 PM PDT 24
Peak memory 205136 kb
Host smart-b6a1257e-b3ee-4426-aca6-db2fbb41caad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749864611 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.3749864611
Directory /workspace/30.rv_dm_stress_all/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.3304973151
Short name T210
Test name
Test status
Simulation time 21457857 ps
CPU time 0.72 seconds
Started Apr 15 12:35:45 PM PDT 24
Finished Apr 15 12:35:46 PM PDT 24
Peak memory 205028 kb
Host smart-88900219-0b3c-461a-a09c-a2def68c31d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304973151 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.3304973151
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.4008447429
Short name T156
Test name
Test status
Simulation time 29160680 ps
CPU time 0.8 seconds
Started Apr 15 12:35:46 PM PDT 24
Finished Apr 15 12:35:48 PM PDT 24
Peak memory 204984 kb
Host smart-fc607b43-ffc1-4598-8972-1329969746bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008447429 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.4008447429
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.2909295216
Short name T142
Test name
Test status
Simulation time 24695894 ps
CPU time 0.76 seconds
Started Apr 15 12:35:46 PM PDT 24
Finished Apr 15 12:35:47 PM PDT 24
Peak memory 204984 kb
Host smart-b2764223-0f24-49ec-9ad1-a61e5ec0dc8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909295216 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.2909295216
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.3735046656
Short name T146
Test name
Test status
Simulation time 34180017 ps
CPU time 0.74 seconds
Started Apr 15 12:35:46 PM PDT 24
Finished Apr 15 12:35:48 PM PDT 24
Peak memory 205072 kb
Host smart-1ceb0067-fa70-4170-910f-d6b7f6740acf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735046656 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.3735046656
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.148598386
Short name T140
Test name
Test status
Simulation time 23342539 ps
CPU time 0.7 seconds
Started Apr 15 12:35:44 PM PDT 24
Finished Apr 15 12:35:45 PM PDT 24
Peak memory 205020 kb
Host smart-5e33f6a1-a2f7-4a1c-832b-d9a97f7ba89b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148598386 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.148598386
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.3741030921
Short name T119
Test name
Test status
Simulation time 53097183 ps
CPU time 0.7 seconds
Started Apr 15 12:35:49 PM PDT 24
Finished Apr 15 12:35:50 PM PDT 24
Peak memory 205016 kb
Host smart-944630ca-3cc8-4270-a9a5-58eca8a66d63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741030921 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.3741030921
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.26350007
Short name T170
Test name
Test status
Simulation time 18657443 ps
CPU time 0.71 seconds
Started Apr 15 12:35:44 PM PDT 24
Finished Apr 15 12:35:45 PM PDT 24
Peak memory 205104 kb
Host smart-e64558a7-2fc1-4a04-9c6e-24b885203e7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26350007 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.26350007
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.3789823319
Short name T42
Test name
Test status
Simulation time 43431031 ps
CPU time 0.71 seconds
Started Apr 15 12:35:55 PM PDT 24
Finished Apr 15 12:35:57 PM PDT 24
Peak memory 205024 kb
Host smart-85222ecb-b01b-4b5c-b8e9-6e7f70196646
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789823319 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.3789823319
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.80158540
Short name T35
Test name
Test status
Simulation time 16451335 ps
CPU time 0.77 seconds
Started Apr 15 12:35:49 PM PDT 24
Finished Apr 15 12:35:50 PM PDT 24
Peak memory 205024 kb
Host smart-a4fa4d80-3ab5-49da-8684-c91bf871801c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80158540 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.80158540
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.592006868
Short name T195
Test name
Test status
Simulation time 51431427 ps
CPU time 0.7 seconds
Started Apr 15 12:35:10 PM PDT 24
Finished Apr 15 12:35:12 PM PDT 24
Peak memory 205108 kb
Host smart-88572e5e-c2cc-4ad3-82c8-5611a2ad6a28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592006868 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.592006868
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.1577834791
Short name T21
Test name
Test status
Simulation time 2187589639 ps
CPU time 5.83 seconds
Started Apr 15 12:35:10 PM PDT 24
Finished Apr 15 12:35:17 PM PDT 24
Peak memory 205620 kb
Host smart-3764f394-4b0b-49ed-af9c-8e93fc2184f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577834791 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.1577834791
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.2353466947
Short name T14
Test name
Test status
Simulation time 1758347977 ps
CPU time 3.78 seconds
Started Apr 15 12:35:09 PM PDT 24
Finished Apr 15 12:35:14 PM PDT 24
Peak memory 205412 kb
Host smart-22f9729c-2579-4b83-bad6-bdaa35aaedba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353466947 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.2353466947
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.733535632
Short name T208
Test name
Test status
Simulation time 1483003715 ps
CPU time 3.53 seconds
Started Apr 15 12:35:04 PM PDT 24
Finished Apr 15 12:35:08 PM PDT 24
Peak memory 205408 kb
Host smart-3d9644a0-e91f-4901-b20d-c43de0e830ee
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=733535632 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_tl
_access.733535632
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.1835757263
Short name T226
Test name
Test status
Simulation time 41858178 ps
CPU time 0.7 seconds
Started Apr 15 12:35:04 PM PDT 24
Finished Apr 15 12:35:05 PM PDT 24
Peak memory 204980 kb
Host smart-0cb8c61b-fc4c-49df-be9e-3d002cd957cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835757263 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.1835757263
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.413291997
Short name T27
Test name
Test status
Simulation time 134551394 ps
CPU time 1.01 seconds
Started Apr 15 12:35:14 PM PDT 24
Finished Apr 15 12:35:20 PM PDT 24
Peak memory 229584 kb
Host smart-89b1a8fa-1bc0-4fa1-8013-a7090f30522d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413291997 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.413291997
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.1557924419
Short name T145
Test name
Test status
Simulation time 65124840 ps
CPU time 0.71 seconds
Started Apr 15 12:35:42 PM PDT 24
Finished Apr 15 12:35:43 PM PDT 24
Peak memory 205020 kb
Host smart-63b98a28-e091-4f37-ada3-f25c8e166bce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557924419 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.1557924419
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.2703982937
Short name T223
Test name
Test status
Simulation time 29590952 ps
CPU time 0.76 seconds
Started Apr 15 12:35:49 PM PDT 24
Finished Apr 15 12:35:51 PM PDT 24
Peak memory 205028 kb
Host smart-1c60f8ce-559b-4b04-9608-134aa1edc8c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703982937 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.2703982937
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.3162288050
Short name T71
Test name
Test status
Simulation time 28714517 ps
CPU time 0.82 seconds
Started Apr 15 12:35:46 PM PDT 24
Finished Apr 15 12:35:47 PM PDT 24
Peak memory 205104 kb
Host smart-e1c44cfd-2139-4a18-8a86-41d7bc26095f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162288050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.3162288050
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.301847347
Short name T160
Test name
Test status
Simulation time 37941607 ps
CPU time 0.72 seconds
Started Apr 15 12:35:55 PM PDT 24
Finished Apr 15 12:35:57 PM PDT 24
Peak memory 205020 kb
Host smart-d3df0221-f8ee-486f-ae01-c0de0a5099c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301847347 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.301847347
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_stress_all.1685561244
Short name T29
Test name
Test status
Simulation time 1750188393 ps
CPU time 5.98 seconds
Started Apr 15 12:35:46 PM PDT 24
Finished Apr 15 12:35:53 PM PDT 24
Peak memory 205340 kb
Host smart-00e925ad-c464-4990-a396-7178badafeb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685561244 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.1685561244
Directory /workspace/43.rv_dm_stress_all/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.3778796157
Short name T118
Test name
Test status
Simulation time 17427588 ps
CPU time 0.76 seconds
Started Apr 15 12:35:46 PM PDT 24
Finished Apr 15 12:35:48 PM PDT 24
Peak memory 205032 kb
Host smart-0fc4c8be-434b-4fa5-9c98-eeb0680b7489
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778796157 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.3778796157
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.2623650911
Short name T139
Test name
Test status
Simulation time 20241571 ps
CPU time 0.69 seconds
Started Apr 15 12:35:55 PM PDT 24
Finished Apr 15 12:35:57 PM PDT 24
Peak memory 204732 kb
Host smart-bad971b9-48c9-40e1-8cb4-b394d0b75c88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623650911 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.2623650911
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.1516851414
Short name T158
Test name
Test status
Simulation time 41675778 ps
CPU time 0.69 seconds
Started Apr 15 12:35:50 PM PDT 24
Finished Apr 15 12:35:52 PM PDT 24
Peak memory 205048 kb
Host smart-aad9c7ce-5536-4e3a-ba4e-82dd0d160f04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516851414 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.1516851414
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.1781933561
Short name T141
Test name
Test status
Simulation time 18691486 ps
CPU time 0.72 seconds
Started Apr 15 12:35:49 PM PDT 24
Finished Apr 15 12:35:50 PM PDT 24
Peak memory 205116 kb
Host smart-18968b1b-e699-4024-abad-c7c73709345e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781933561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.1781933561
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.3297701304
Short name T147
Test name
Test status
Simulation time 51972786 ps
CPU time 0.71 seconds
Started Apr 15 12:35:56 PM PDT 24
Finished Apr 15 12:35:58 PM PDT 24
Peak memory 205060 kb
Host smart-9158c1f1-9de7-407a-b523-f0d8f7142d9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297701304 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.3297701304
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.2164277997
Short name T153
Test name
Test status
Simulation time 22727196 ps
CPU time 0.7 seconds
Started Apr 15 12:35:10 PM PDT 24
Finished Apr 15 12:35:12 PM PDT 24
Peak memory 205032 kb
Host smart-a887ef03-1a21-4947-aaf0-e0cc5544c953
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164277997 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.2164277997
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.4212120240
Short name T213
Test name
Test status
Simulation time 12845397585 ps
CPU time 39.83 seconds
Started Apr 15 12:35:09 PM PDT 24
Finished Apr 15 12:35:50 PM PDT 24
Peak memory 213672 kb
Host smart-40a1115e-7453-41f1-947d-c6c48b74a4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212120240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.4212120240
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.3728725078
Short name T171
Test name
Test status
Simulation time 7194724944 ps
CPU time 14.54 seconds
Started Apr 15 12:35:09 PM PDT 24
Finished Apr 15 12:35:24 PM PDT 24
Peak memory 215668 kb
Host smart-1e4eeaf9-e003-4a8c-a6f5-80f4aab1690a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728725078 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.3728725078
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.3447571822
Short name T196
Test name
Test status
Simulation time 2500509847 ps
CPU time 4.75 seconds
Started Apr 15 12:35:16 PM PDT 24
Finished Apr 15 12:35:22 PM PDT 24
Peak memory 205460 kb
Host smart-2212284b-4d9c-4761-8752-a0f2a83f3ecf
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3447571822 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t
l_access.3447571822
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.689652940
Short name T34
Test name
Test status
Simulation time 1071256870 ps
CPU time 3.16 seconds
Started Apr 15 12:35:11 PM PDT 24
Finished Apr 15 12:35:15 PM PDT 24
Peak memory 205304 kb
Host smart-665cbe54-b876-4836-b158-f4a0ab453df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689652940 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.689652940
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.2368549419
Short name T150
Test name
Test status
Simulation time 45250073 ps
CPU time 0.7 seconds
Started Apr 15 12:35:10 PM PDT 24
Finished Apr 15 12:35:12 PM PDT 24
Peak memory 205024 kb
Host smart-f2761a26-8129-4c22-9d0e-09a388589bbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368549419 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.2368549419
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.2304258449
Short name T204
Test name
Test status
Simulation time 13618223381 ps
CPU time 19.57 seconds
Started Apr 15 12:35:13 PM PDT 24
Finished Apr 15 12:35:33 PM PDT 24
Peak memory 213640 kb
Host smart-0db27cc9-bbcc-4480-81e6-7b87b1a02477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304258449 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.2304258449
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.3517286659
Short name T89
Test name
Test status
Simulation time 2969932360 ps
CPU time 11.32 seconds
Started Apr 15 12:35:11 PM PDT 24
Finished Apr 15 12:35:23 PM PDT 24
Peak memory 205120 kb
Host smart-657444c9-924f-4d35-b897-3821e5e2c4ca
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3517286659 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t
l_access.3517286659
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.2617610648
Short name T217
Test name
Test status
Simulation time 4547027902 ps
CPU time 6.61 seconds
Started Apr 15 12:35:10 PM PDT 24
Finished Apr 15 12:35:18 PM PDT 24
Peak memory 205432 kb
Host smart-2f2e8e29-e0d3-4cbb-8700-fffe1402daa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617610648 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.2617610648
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.2490294563
Short name T148
Test name
Test status
Simulation time 66403804 ps
CPU time 0.73 seconds
Started Apr 15 12:35:13 PM PDT 24
Finished Apr 15 12:35:14 PM PDT 24
Peak memory 205020 kb
Host smart-1231422d-d1dc-4c91-b41a-7c6febbf921f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490294563 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.2490294563
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.862735484
Short name T233
Test name
Test status
Simulation time 6527153726 ps
CPU time 9.23 seconds
Started Apr 15 12:35:20 PM PDT 24
Finished Apr 15 12:35:30 PM PDT 24
Peak memory 215476 kb
Host smart-1cd60382-9471-4d13-a2b2-e0f84ac79e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862735484 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.862735484
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.909325029
Short name T91
Test name
Test status
Simulation time 771939745 ps
CPU time 2.99 seconds
Started Apr 15 12:35:15 PM PDT 24
Finished Apr 15 12:35:18 PM PDT 24
Peak memory 205296 kb
Host smart-d4546d9d-484f-48e6-a7e4-0077d3816746
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=909325029 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_tl
_access.909325029
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.150418820
Short name T200
Test name
Test status
Simulation time 11312751625 ps
CPU time 9.94 seconds
Started Apr 15 12:35:10 PM PDT 24
Finished Apr 15 12:35:21 PM PDT 24
Peak memory 205396 kb
Host smart-4622dc78-0e53-4aef-a4a4-ec110da5cf4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150418820 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.150418820
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.1150705350
Short name T186
Test name
Test status
Simulation time 63478210 ps
CPU time 0.69 seconds
Started Apr 15 12:35:15 PM PDT 24
Finished Apr 15 12:35:17 PM PDT 24
Peak memory 205060 kb
Host smart-faae9cd6-bb06-4beb-8a9d-b971b677d6cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150705350 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.1150705350
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.1646471546
Short name T23
Test name
Test status
Simulation time 5078991382 ps
CPU time 18.48 seconds
Started Apr 15 12:35:15 PM PDT 24
Finished Apr 15 12:35:34 PM PDT 24
Peak memory 213624 kb
Host smart-40a6b1ca-d9d1-4e32-aaf9-7dff2097da76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646471546 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.1646471546
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.1947699164
Short name T70
Test name
Test status
Simulation time 2516218356 ps
CPU time 5.56 seconds
Started Apr 15 12:35:17 PM PDT 24
Finished Apr 15 12:35:23 PM PDT 24
Peak memory 205416 kb
Host smart-672dab40-6001-47b4-882c-f5c7f03c6410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947699164 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.1947699164
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.3605784349
Short name T224
Test name
Test status
Simulation time 846507701 ps
CPU time 2.38 seconds
Started Apr 15 12:35:14 PM PDT 24
Finished Apr 15 12:35:17 PM PDT 24
Peak memory 205332 kb
Host smart-1884e0c7-995b-4eac-a9d6-2266dab8066e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3605784349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t
l_access.3605784349
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.3400035396
Short name T188
Test name
Test status
Simulation time 3047944591 ps
CPU time 13.91 seconds
Started Apr 15 12:35:16 PM PDT 24
Finished Apr 15 12:35:31 PM PDT 24
Peak memory 213608 kb
Host smart-7d1eb871-78de-4044-aea3-0ff3acd8da43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400035396 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.3400035396
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.1801587391
Short name T47
Test name
Test status
Simulation time 56531826 ps
CPU time 0.73 seconds
Started Apr 15 12:35:20 PM PDT 24
Finished Apr 15 12:35:21 PM PDT 24
Peak memory 205120 kb
Host smart-1edf52bd-2630-4e41-8e70-8224a58a2fe9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801587391 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.1801587391
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.1500393473
Short name T230
Test name
Test status
Simulation time 3119500724 ps
CPU time 6.91 seconds
Started Apr 15 12:35:21 PM PDT 24
Finished Apr 15 12:35:29 PM PDT 24
Peak memory 213732 kb
Host smart-ebe2e6c2-f966-4587-8754-023d2f158b9e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1500393473 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t
l_access.1500393473
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.1896092832
Short name T168
Test name
Test status
Simulation time 7745815370 ps
CPU time 13.37 seconds
Started Apr 15 12:35:22 PM PDT 24
Finished Apr 15 12:35:36 PM PDT 24
Peak memory 205424 kb
Host smart-5f88ef47-27fa-4e24-93af-3c207ad10705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896092832 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.1896092832
Directory /workspace/9.rv_dm_sba_tl_access/latest
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