| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 78.45 | 93.81 | 79.26 | 87.53 | 71.79 | 82.67 | 98.52 | 35.57 |
| T257 | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2572389041 | May 09 01:16:51 PM PDT 24 | May 09 01:16:53 PM PDT 24 | 72133133 ps | ||
| T258 | /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3534849484 | May 09 01:16:47 PM PDT 24 | May 09 01:17:06 PM PDT 24 | 1815408880 ps | ||
| T110 | /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.2239146328 | May 09 01:16:37 PM PDT 24 | May 09 01:16:56 PM PDT 24 | 1294312246 ps | ||
| T259 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.1274036126 | May 09 01:16:37 PM PDT 24 | May 09 01:16:44 PM PDT 24 | 213812692 ps | ||
| T260 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.2951460887 | May 09 01:16:45 PM PDT 24 | May 09 01:16:48 PM PDT 24 | 482789729 ps | ||
| T261 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.1287023639 | May 09 01:16:36 PM PDT 24 | May 09 01:16:40 PM PDT 24 | 80525978 ps | ||
| T84 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2787168025 | May 09 01:16:26 PM PDT 24 | May 09 01:16:35 PM PDT 24 | 1699000304 ps | ||
| T262 | /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.512750372 | May 09 01:16:51 PM PDT 24 | May 09 01:17:01 PM PDT 24 | 1628750135 ps | ||
| T263 | /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.4045106011 | May 09 01:16:34 PM PDT 24 | May 09 01:16:42 PM PDT 24 | 241606844 ps | ||
| T264 | /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.1168160682 | May 09 01:16:51 PM PDT 24 | May 09 01:16:57 PM PDT 24 | 2346443273 ps | ||
| T265 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2374354378 | May 09 01:16:36 PM PDT 24 | May 09 01:16:39 PM PDT 24 | 92063560 ps | ||
| T266 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1946246188 | May 09 01:16:37 PM PDT 24 | May 09 01:16:42 PM PDT 24 | 509616642 ps | ||
| T267 | /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.729815181 | May 09 01:16:40 PM PDT 24 | May 09 01:16:44 PM PDT 24 | 19584528 ps | ||
| T268 | /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.3261774058 | May 09 01:16:37 PM PDT 24 | May 09 01:16:59 PM PDT 24 | 15482465457 ps | ||
| T269 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.3695079771 | May 09 01:16:26 PM PDT 24 | May 09 01:16:39 PM PDT 24 | 2397815199 ps | ||
| T270 | /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.63712917 | May 09 01:16:49 PM PDT 24 | May 09 01:16:58 PM PDT 24 | 792110755 ps | ||
| T271 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3837338998 | May 09 01:16:36 PM PDT 24 | May 09 01:16:40 PM PDT 24 | 95615579 ps | ||
| T272 | /workspace/coverage/cover_reg_top/29.rv_dm_tap_fsm_rand_reset.401271601 | May 09 01:16:54 PM PDT 24 | May 09 01:17:28 PM PDT 24 | 23485465946 ps | ||
| T273 | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.367741348 | May 09 01:16:54 PM PDT 24 | May 09 01:16:59 PM PDT 24 | 32687765 ps | ||
| T274 | /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2971986203 | May 09 01:16:47 PM PDT 24 | May 09 01:16:51 PM PDT 24 | 64584952 ps | ||
| T275 | /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.1275941110 | May 09 01:16:48 PM PDT 24 | May 09 01:16:59 PM PDT 24 | 612333037 ps | ||
| T119 | /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.2787576498 | May 09 01:16:36 PM PDT 24 | May 09 01:17:00 PM PDT 24 | 2715408788 ps | ||
| T276 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.341508325 | May 09 01:16:39 PM PDT 24 | May 09 01:16:45 PM PDT 24 | 1532076051 ps | ||
| T277 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2159424693 | May 09 01:16:35 PM PDT 24 | May 09 01:16:39 PM PDT 24 | 129215364 ps | ||
| T278 | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.4031850685 | May 09 01:16:51 PM PDT 24 | May 09 01:16:53 PM PDT 24 | 51397823 ps | ||
| T279 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.3830699881 | May 09 01:16:35 PM PDT 24 | May 09 01:16:47 PM PDT 24 | 6098617454 ps | ||
| T280 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.1811780539 | May 09 01:16:45 PM PDT 24 | May 09 01:16:48 PM PDT 24 | 138200767 ps | ||
| T281 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3638277608 | May 09 01:16:36 PM PDT 24 | May 09 01:16:41 PM PDT 24 | 378950371 ps | ||
| T282 | /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3533694788 | May 09 01:16:55 PM PDT 24 | May 09 01:17:06 PM PDT 24 | 603222514 ps | ||
| T283 | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.872445550 | May 09 01:16:46 PM PDT 24 | May 09 01:16:49 PM PDT 24 | 339759182 ps | ||
| T113 | /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2988676108 | May 09 01:16:59 PM PDT 24 | May 09 01:17:17 PM PDT 24 | 699552485 ps | ||
| T284 | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1645807018 | May 09 01:16:54 PM PDT 24 | May 09 01:16:59 PM PDT 24 | 213210001 ps | ||
| T285 | /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.1379596316 | May 09 01:16:52 PM PDT 24 | May 09 01:16:58 PM PDT 24 | 56515207 ps | ||
| T286 | /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.1247466656 | May 09 01:16:41 PM PDT 24 | May 09 01:16:47 PM PDT 24 | 65025235 ps | ||
| T118 | /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2970167861 | May 09 01:16:52 PM PDT 24 | May 09 01:17:13 PM PDT 24 | 2084391324 ps | ||
| T287 | /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3585190793 | May 09 01:16:48 PM PDT 24 | May 09 01:16:54 PM PDT 24 | 3005823181 ps | ||
| T288 | /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.554126908 | May 09 01:16:52 PM PDT 24 | May 09 01:16:58 PM PDT 24 | 1991113557 ps | ||
| T289 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.3744949079 | May 09 01:16:34 PM PDT 24 | May 09 01:16:36 PM PDT 24 | 512799651 ps | ||
| T290 | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.2717574953 | May 09 01:16:43 PM PDT 24 | May 09 01:16:46 PM PDT 24 | 126458942 ps | ||
| T291 | /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2254008166 | May 09 01:16:40 PM PDT 24 | May 09 01:16:46 PM PDT 24 | 131035178 ps | ||
| T292 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1144897332 | May 09 01:16:27 PM PDT 24 | May 09 01:16:57 PM PDT 24 | 1128391612 ps | ||
| T114 | /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3919541478 | May 09 01:16:56 PM PDT 24 | May 09 01:17:15 PM PDT 24 | 1944097737 ps | ||
| T293 | /workspace/coverage/cover_reg_top/10.rv_dm_tap_fsm_rand_reset.3174404273 | May 09 01:16:44 PM PDT 24 | May 09 01:17:01 PM PDT 24 | 21888233773 ps | ||
| T294 | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.682926831 | May 09 01:16:40 PM PDT 24 | May 09 01:16:44 PM PDT 24 | 258241078 ps | ||
| T295 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.2060879191 | May 09 01:16:28 PM PDT 24 | May 09 01:17:16 PM PDT 24 | 38338988285 ps | ||
| T296 | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.4161689171 | May 09 01:16:56 PM PDT 24 | May 09 01:17:02 PM PDT 24 | 258569687 ps | ||
| T297 | /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.780606069 | May 09 01:16:50 PM PDT 24 | May 09 01:17:01 PM PDT 24 | 285985058 ps | ||
| T298 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.772677008 | May 09 01:16:38 PM PDT 24 | May 09 01:16:43 PM PDT 24 | 206471595 ps | ||
| T299 | /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3248115168 | May 09 01:16:37 PM PDT 24 | May 09 01:16:45 PM PDT 24 | 913412729 ps | ||
| T300 | /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.544267157 | May 09 01:16:54 PM PDT 24 | May 09 01:17:04 PM PDT 24 | 3932766531 ps | ||
| T301 | /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3523867739 | May 09 01:16:50 PM PDT 24 | May 09 01:16:58 PM PDT 24 | 283206845 ps | ||
| T302 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1583225272 | May 09 01:16:36 PM PDT 24 | May 09 01:16:39 PM PDT 24 | 89762283 ps | ||
| T303 | /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.3170803245 | May 09 01:16:51 PM PDT 24 | May 09 01:16:59 PM PDT 24 | 228349225 ps | ||
| T304 | /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2564747613 | May 09 01:16:56 PM PDT 24 | May 09 01:17:02 PM PDT 24 | 137216839 ps | ||
| T305 | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1738272544 | May 09 01:16:49 PM PDT 24 | May 09 01:16:57 PM PDT 24 | 1961670755 ps | ||
| T306 | /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.1579692507 | May 09 01:16:53 PM PDT 24 | May 09 01:17:17 PM PDT 24 | 2003694276 ps | ||
| T307 | /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.3744481305 | May 09 01:16:45 PM PDT 24 | May 09 01:16:48 PM PDT 24 | 41574996 ps | ||
| T308 | /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.2112011998 | May 09 01:16:39 PM PDT 24 | May 09 01:16:50 PM PDT 24 | 2315454078 ps | ||
| T309 | /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.961652185 | May 09 01:16:54 PM PDT 24 | May 09 01:17:18 PM PDT 24 | 3332523603 ps |
| Test location | /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.731276637 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 3609758353 ps |
| CPU time | 5.06 seconds |
| Started | May 09 01:17:05 PM PDT 24 |
| Finished | May 09 01:17:12 PM PDT 24 |
| Peak memory | 213796 kb |
| Host | smart-4a256235-3953-46f6-951a-7e7c88099b4b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=731276637 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.731276637 |
| Directory | /workspace/1.rv_dm_bad_sba_tl_access/latest |
| Test location | /workspace/coverage/default/38.rv_dm_stress_all.3177412977 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 7334287851 ps |
| CPU time | 24.86 seconds |
| Started | May 09 01:29:03 PM PDT 24 |
| Finished | May 09 01:29:29 PM PDT 24 |
| Peak memory | 205476 kb |
| Host | smart-395e9ce3-3be5-4480-a319-87b8880a59d6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177412977 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.3177412977 |
| Directory | /workspace/38.rv_dm_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/37.rv_dm_tap_fsm_rand_reset.2706456655 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 7838454020 ps |
| CPU time | 27.53 seconds |
| Started | May 09 01:16:54 PM PDT 24 |
| Finished | May 09 01:17:26 PM PDT 24 |
| Peak memory | 215104 kb |
| Host | smart-63673dd4-1228-4744-baf6-81a1f0054a48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706456655 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 37.rv_dm_tap_fsm_rand_reset.2706456655 |
| Directory | /workspace/37.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2917547401 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 1860220957 ps |
| CPU time | 18.86 seconds |
| Started | May 09 01:16:52 PM PDT 24 |
| Finished | May 09 01:17:14 PM PDT 24 |
| Peak memory | 213132 kb |
| Host | smart-4ae7f660-71bb-4ad6-be47-592aa06515c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917547401 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.2 917547401 |
| Directory | /workspace/15.rv_dm_tl_intg_err/latest |
| Test location | /workspace/coverage/default/36.rv_dm_alert_test.711037898 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 43937164 ps |
| CPU time | 0.74 seconds |
| Started | May 09 01:29:06 PM PDT 24 |
| Finished | May 09 01:29:08 PM PDT 24 |
| Peak memory | 205088 kb |
| Host | smart-51f95ef7-e11f-459f-b48f-ee00c07b1634 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711037898 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.711037898 |
| Directory | /workspace/36.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.3970419998 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 110581785 ps |
| CPU time | 0.82 seconds |
| Started | May 09 01:17:09 PM PDT 24 |
| Finished | May 09 01:17:13 PM PDT 24 |
| Peak memory | 205152 kb |
| Host | smart-e48f3532-d92f-43d5-8f0b-b8aee26974a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3970419998 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.3970419998 |
| Directory | /workspace/1.rv_dm_progbuf_read_write_execute/latest |
| Test location | /workspace/coverage/default/11.rv_dm_stress_all.1790605004 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 3952081258 ps |
| CPU time | 13.85 seconds |
| Started | May 09 01:17:23 PM PDT 24 |
| Finished | May 09 01:17:38 PM PDT 24 |
| Peak memory | 205428 kb |
| Host | smart-c8f250ab-1b78-450c-b057-c9d5727e8e1c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790605004 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.1790605004 |
| Directory | /workspace/11.rv_dm_stress_all/latest |
| Test location | /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.4283504720 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 16962350986 ps |
| CPU time | 16.97 seconds |
| Started | May 09 01:27:31 PM PDT 24 |
| Finished | May 09 01:27:49 PM PDT 24 |
| Peak memory | 213888 kb |
| Host | smart-58a6b63d-eb0f-4b9e-8e9f-11fff876cfe8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4283504720 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.4283504720 |
| Directory | /workspace/12.rv_dm_autoincr_sba_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.97954209 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 183447936 ps |
| CPU time | 2.19 seconds |
| Started | May 09 01:16:49 PM PDT 24 |
| Finished | May 09 01:16:53 PM PDT 24 |
| Peak memory | 213128 kb |
| Host | smart-91b88199-809b-418c-b0fa-b908d8bfe655 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97954209 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.97954209 |
| Directory | /workspace/9.rv_dm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2970167861 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 2084391324 ps |
| CPU time | 18.61 seconds |
| Started | May 09 01:16:52 PM PDT 24 |
| Finished | May 09 01:17:13 PM PDT 24 |
| Peak memory | 221080 kb |
| Host | smart-4fcd1aba-7f7c-46dd-96f3-c3a4ad3c16fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970167861 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.2970167861 |
| Directory | /workspace/6.rv_dm_tl_intg_err/latest |
| Test location | /workspace/coverage/default/1.rv_dm_sec_cm.1815056705 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 183039494 ps |
| CPU time | 1.29 seconds |
| Started | May 09 01:17:05 PM PDT 24 |
| Finished | May 09 01:17:08 PM PDT 24 |
| Peak memory | 229212 kb |
| Host | smart-8788d047-0007-4181-a654-b83889f2a4db |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815056705 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.1815056705 |
| Directory | /workspace/1.rv_dm_sec_cm/latest |
| Test location | /workspace/coverage/default/1.rv_dm_rom_read_access.650299445 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 119157452 ps |
| CPU time | 0.8 seconds |
| Started | May 09 01:17:07 PM PDT 24 |
| Finished | May 09 01:17:10 PM PDT 24 |
| Peak memory | 213332 kb |
| Host | smart-52ae6911-f505-4e44-bac1-d48860a91ac2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=650299445 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.650299445 |
| Directory | /workspace/1.rv_dm_rom_read_access/latest |
| Test location | /workspace/coverage/default/0.rv_dm_abstractcmd_status.3988352415 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 40463072 ps |
| CPU time | 0.72 seconds |
| Started | May 09 01:17:07 PM PDT 24 |
| Finished | May 09 01:17:10 PM PDT 24 |
| Peak memory | 205120 kb |
| Host | smart-de8ddd77-304d-4d63-bf54-b38b1312cf65 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3988352415 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.3988352415 |
| Directory | /workspace/0.rv_dm_abstractcmd_status/latest |
| Test location | /workspace/coverage/default/1.rv_dm_cmderr_exception.549197671 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 169000996 ps |
| CPU time | 0.85 seconds |
| Started | May 09 01:17:05 PM PDT 24 |
| Finished | May 09 01:17:08 PM PDT 24 |
| Peak memory | 205116 kb |
| Host | smart-f682a919-946f-474e-9f32-115e10e10014 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=549197671 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.549197671 |
| Directory | /workspace/1.rv_dm_cmderr_exception/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.280721748 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 377729823 ps |
| CPU time | 2.45 seconds |
| Started | May 09 01:16:36 PM PDT 24 |
| Finished | May 09 01:16:41 PM PDT 24 |
| Peak memory | 213156 kb |
| Host | smart-36f80252-6c16-4636-a06d-65aa25e0ddad |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280721748 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.280721748 |
| Directory | /workspace/0.rv_dm_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.186844473 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 1476516427 ps |
| CPU time | 15 seconds |
| Started | May 09 01:16:38 PM PDT 24 |
| Finished | May 09 01:16:56 PM PDT 24 |
| Peak memory | 213112 kb |
| Host | smart-6d9a060a-1696-43fc-aa7f-0bd602772e55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186844473 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.186844473 |
| Directory | /workspace/2.rv_dm_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.353349063 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 1220710536 ps |
| CPU time | 3.8 seconds |
| Started | May 09 01:16:54 PM PDT 24 |
| Finished | May 09 01:17:02 PM PDT 24 |
| Peak memory | 213256 kb |
| Host | smart-6c3c6235-5dbd-4fc0-bb46-32fe6b8ade60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353349063 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.353349063 |
| Directory | /workspace/8.rv_dm_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.3597834842 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 3721126752 ps |
| CPU time | 4.64 seconds |
| Started | May 09 01:16:48 PM PDT 24 |
| Finished | May 09 01:16:54 PM PDT 24 |
| Peak memory | 204992 kb |
| Host | smart-f2cea310-7a23-42d0-95be-e1985751539c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597834842 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same _csr_outstanding.3597834842 |
| Directory | /workspace/11.rv_dm_same_csr_outstanding/latest |
| Test location | /workspace/coverage/default/0.rv_dm_progbuf_busy.4126101366 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 482358401 ps |
| CPU time | 1.63 seconds |
| Started | May 09 01:17:05 PM PDT 24 |
| Finished | May 09 01:17:08 PM PDT 24 |
| Peak memory | 205084 kb |
| Host | smart-c0eb7edd-1dd6-4f38-bdad-e5cf2a76fd7d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4126101366 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.4126101366 |
| Directory | /workspace/0.rv_dm_progbuf_busy/latest |
| Test location | /workspace/coverage/cover_reg_top/24.rv_dm_tap_fsm_rand_reset.2751178579 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 13140622629 ps |
| CPU time | 46.7 seconds |
| Started | May 09 01:16:54 PM PDT 24 |
| Finished | May 09 01:17:46 PM PDT 24 |
| Peak memory | 221528 kb |
| Host | smart-1df25510-967a-45d7-99d0-6a6db8243968 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751178579 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 24.rv_dm_tap_fsm_rand_reset.2751178579 |
| Directory | /workspace/24.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2081876075 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 42276237 ps |
| CPU time | 0.78 seconds |
| Started | May 09 01:16:25 PM PDT 24 |
| Finished | May 09 01:16:30 PM PDT 24 |
| Peak memory | 204608 kb |
| Host | smart-d564b7c9-a719-43e4-9abd-14483b70c610 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081876075 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_hw_reset.2081876075 |
| Directory | /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.2530056068 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 388862620 ps |
| CPU time | 1.06 seconds |
| Started | May 09 01:17:06 PM PDT 24 |
| Finished | May 09 01:17:09 PM PDT 24 |
| Peak memory | 205176 kb |
| Host | smart-7d970ac4-19d2-4ed7-beb0-777c3037fc91 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2530056068 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.2530056068 |
| Directory | /workspace/0.rv_dm_mem_tl_access_resuming/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1248462343 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 1429772427 ps |
| CPU time | 20.18 seconds |
| Started | May 09 01:16:41 PM PDT 24 |
| Finished | May 09 01:17:04 PM PDT 24 |
| Peak memory | 221236 kb |
| Host | smart-c6e34457-73be-45d2-a292-96337004c0d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248462343 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.1248462343 |
| Directory | /workspace/4.rv_dm_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/34.rv_dm_tap_fsm_rand_reset.1287718387 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 15218960063 ps |
| CPU time | 31.44 seconds |
| Started | May 09 01:16:53 PM PDT 24 |
| Finished | May 09 01:17:29 PM PDT 24 |
| Peak memory | 221500 kb |
| Host | smart-bead7cd9-23dd-476f-a13d-97aed81ab52c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287718387 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 34.rv_dm_tap_fsm_rand_reset.1287718387 |
| Directory | /workspace/34.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspace/coverage/default/0.rv_dm_alert_test.3662659965 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 18443531 ps |
| CPU time | 0.72 seconds |
| Started | May 09 01:17:06 PM PDT 24 |
| Finished | May 09 01:17:09 PM PDT 24 |
| Peak memory | 205168 kb |
| Host | smart-98ad8259-dd42-44e8-8eaf-d572f8cdaea4 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662659965 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.3662659965 |
| Directory | /workspace/0.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.3754284509 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 138463826 ps |
| CPU time | 1.13 seconds |
| Started | May 09 01:17:06 PM PDT 24 |
| Finished | May 09 01:17:10 PM PDT 24 |
| Peak memory | 205032 kb |
| Host | smart-f2863a9e-7cd8-4eb3-a2e8-0de346759637 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3754284509 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.3754284509 |
| Directory | /workspace/0.rv_dm_cmderr_halt_resume/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2787168025 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 1699000304 ps |
| CPU time | 5.23 seconds |
| Started | May 09 01:16:26 PM PDT 24 |
| Finished | May 09 01:16:35 PM PDT 24 |
| Peak memory | 204800 kb |
| Host | smart-2b9bd984-9b0b-4c3a-8e9e-cf9607c9df38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787168025 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs r_hw_reset.2787168025 |
| Directory | /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.816068805 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 371230717 ps |
| CPU time | 4.38 seconds |
| Started | May 09 01:16:37 PM PDT 24 |
| Finished | May 09 01:16:44 PM PDT 24 |
| Peak memory | 213232 kb |
| Host | smart-faa49464-d897-4380-b383-f11dc6fefdbd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816068805 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.816068805 |
| Directory | /workspace/1.rv_dm_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2988676108 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 699552485 ps |
| CPU time | 15.67 seconds |
| Started | May 09 01:16:59 PM PDT 24 |
| Finished | May 09 01:17:17 PM PDT 24 |
| Peak memory | 221284 kb |
| Host | smart-2708da2e-1d06-4518-b915-43ab9d957683 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988676108 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.2988676108 |
| Directory | /workspace/9.rv_dm_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3534849484 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 1815408880 ps |
| CPU time | 18.03 seconds |
| Started | May 09 01:16:47 PM PDT 24 |
| Finished | May 09 01:17:06 PM PDT 24 |
| Peak memory | 221204 kb |
| Host | smart-50f4122f-0659-4ea6-9e50-83514225f3b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534849484 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.3 534849484 |
| Directory | /workspace/11.rv_dm_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.4264577701 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 9942687854 ps |
| CPU time | 33.6 seconds |
| Started | May 09 01:16:40 PM PDT 24 |
| Finished | May 09 01:17:16 PM PDT 24 |
| Peak memory | 213352 kb |
| Host | smart-91459bd9-9ab6-4ac0-bca5-893622ff967f |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264577701 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 4.rv_dm_csr_aliasing.4264577701 |
| Directory | /workspace/4.rv_dm_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.780606069 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 285985058 ps |
| CPU time | 8.58 seconds |
| Started | May 09 01:16:50 PM PDT 24 |
| Finished | May 09 01:17:01 PM PDT 24 |
| Peak memory | 213200 kb |
| Host | smart-d9eae931-fefc-43f1-95fc-90e117664e1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780606069 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.780606069 |
| Directory | /workspace/17.rv_dm_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1637451096 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 2038328856 ps |
| CPU time | 7.25 seconds |
| Started | May 09 01:16:53 PM PDT 24 |
| Finished | May 09 01:17:05 PM PDT 24 |
| Peak memory | 204924 kb |
| Host | smart-5994fdf4-5c8c-4507-b75a-27e44e47bb78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637451096 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same _csr_outstanding.1637451096 |
| Directory | /workspace/19.rv_dm_same_csr_outstanding/latest |
| Test location | /workspace/coverage/default/1.rv_dm_hart_unavail.2831983630 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 96542731 ps |
| CPU time | 0.75 seconds |
| Started | May 09 01:17:07 PM PDT 24 |
| Finished | May 09 01:17:10 PM PDT 24 |
| Peak memory | 205040 kb |
| Host | smart-e9e88d81-ad43-4035-b47a-8fdf7d4f93d8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2831983630 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.2831983630 |
| Directory | /workspace/1.rv_dm_hart_unavail/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1144897332 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 1128391612 ps |
| CPU time | 26.08 seconds |
| Started | May 09 01:16:27 PM PDT 24 |
| Finished | May 09 01:16:57 PM PDT 24 |
| Peak memory | 214200 kb |
| Host | smart-8fd66021-daf6-4692-9d11-fb9b3c61cfdf |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144897332 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 0.rv_dm_csr_aliasing.1144897332 |
| Directory | /workspace/0.rv_dm_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.2112467079 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 2823060492 ps |
| CPU time | 27.28 seconds |
| Started | May 09 01:16:36 PM PDT 24 |
| Finished | May 09 01:17:06 PM PDT 24 |
| Peak memory | 205016 kb |
| Host | smart-2b3dfab9-433e-47cc-ba52-0977b87ffa05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112467079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.2112467079 |
| Directory | /workspace/0.rv_dm_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3601581484 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 490176624 ps |
| CPU time | 2.56 seconds |
| Started | May 09 01:16:37 PM PDT 24 |
| Finished | May 09 01:16:43 PM PDT 24 |
| Peak memory | 217208 kb |
| Host | smart-e91d3924-20f5-4d64-9b10-87cec544950f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601581484 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.3601581484 |
| Directory | /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2159424693 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 129215364 ps |
| CPU time | 2.42 seconds |
| Started | May 09 01:16:35 PM PDT 24 |
| Finished | May 09 01:16:39 PM PDT 24 |
| Peak memory | 213164 kb |
| Host | smart-0d2a4c82-a682-4095-ad00-100deedb91c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159424693 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.2159424693 |
| Directory | /workspace/0.rv_dm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1760511018 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 8707153552 ps |
| CPU time | 9.1 seconds |
| Started | May 09 01:16:24 PM PDT 24 |
| Finished | May 09 01:16:37 PM PDT 24 |
| Peak memory | 204864 kb |
| Host | smart-ab8a1f68-beb0-46d3-88b2-1e8b1a3d4b5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760511018 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs r_aliasing.1760511018 |
| Directory | /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.2060879191 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 38338988285 ps |
| CPU time | 44.06 seconds |
| Started | May 09 01:16:28 PM PDT 24 |
| Finished | May 09 01:17:16 PM PDT 24 |
| Peak memory | 204932 kb |
| Host | smart-ab306ea6-0d77-477b-a92a-984bdc3f0ba6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060879191 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs r_bit_bash.2060879191 |
| Directory | /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3706869535 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 192894942 ps |
| CPU time | 1.05 seconds |
| Started | May 09 01:16:24 PM PDT 24 |
| Finished | May 09 01:16:27 PM PDT 24 |
| Peak memory | 204816 kb |
| Host | smart-195e8d55-5c8f-48ba-8b43-2401d9002001 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706869535 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.3 706869535 |
| Directory | /workspace/0.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.1492434353 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 165767066 ps |
| CPU time | 0.92 seconds |
| Started | May 09 01:16:25 PM PDT 24 |
| Finished | May 09 01:16:30 PM PDT 24 |
| Peak memory | 204636 kb |
| Host | smart-e4658f58-a7b3-40ca-94af-46ca31cbc1a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492434353 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_aliasing.1492434353 |
| Directory | /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.3695079771 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 2397815199 ps |
| CPU time | 8.59 seconds |
| Started | May 09 01:16:26 PM PDT 24 |
| Finished | May 09 01:16:39 PM PDT 24 |
| Peak memory | 204848 kb |
| Host | smart-8ad4a442-79aa-4a36-88f9-415d0013474f |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695079771 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_bit_bash.3695079771 |
| Directory | /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.998189301 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 47231673 ps |
| CPU time | 0.8 seconds |
| Started | May 09 01:16:26 PM PDT 24 |
| Finished | May 09 01:16:31 PM PDT 24 |
| Peak memory | 204592 kb |
| Host | smart-a80fdbe9-87a9-45a2-9ec2-ab5ba65d876c |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998189301 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.998189301 |
| Directory | /workspace/0.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1900178518 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 27271021 ps |
| CPU time | 0.72 seconds |
| Started | May 09 01:16:34 PM PDT 24 |
| Finished | May 09 01:16:36 PM PDT 24 |
| Peak memory | 204616 kb |
| Host | smart-32ecefd5-bf6a-44f7-98d7-fa5e48881b7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900178518 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par tial_access.1900178518 |
| Directory | /workspace/0.rv_dm_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.729815181 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 19584528 ps |
| CPU time | 0.71 seconds |
| Started | May 09 01:16:40 PM PDT 24 |
| Finished | May 09 01:16:44 PM PDT 24 |
| Peak memory | 204568 kb |
| Host | smart-22d1fd56-bd94-4227-9b13-9a5556412a41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729815181 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.729815181 |
| Directory | /workspace/0.rv_dm_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.4045106011 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 241606844 ps |
| CPU time | 6.22 seconds |
| Started | May 09 01:16:34 PM PDT 24 |
| Finished | May 09 01:16:42 PM PDT 24 |
| Peak memory | 204876 kb |
| Host | smart-5660361f-0ab5-49aa-bda3-41ba2e734467 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045106011 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_ csr_outstanding.4045106011 |
| Directory | /workspace/0.rv_dm_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.353117187 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 492705432 ps |
| CPU time | 4.77 seconds |
| Started | May 09 01:16:35 PM PDT 24 |
| Finished | May 09 01:16:41 PM PDT 24 |
| Peak memory | 213188 kb |
| Host | smart-3b587e3d-d97c-4f33-b008-35d1f7bd7f47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353117187 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.353117187 |
| Directory | /workspace/0.rv_dm_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.2787576498 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 2715408788 ps |
| CPU time | 20.62 seconds |
| Started | May 09 01:16:36 PM PDT 24 |
| Finished | May 09 01:17:00 PM PDT 24 |
| Peak memory | 213172 kb |
| Host | smart-c279bcc1-48b3-4c73-920b-6866dc465b8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787576498 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.2787576498 |
| Directory | /workspace/0.rv_dm_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1835328515 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 8723645684 ps |
| CPU time | 33.04 seconds |
| Started | May 09 01:16:38 PM PDT 24 |
| Finished | May 09 01:17:14 PM PDT 24 |
| Peak memory | 213248 kb |
| Host | smart-3ecc543d-92fd-487d-b552-16c002dd0abc |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835328515 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 1.rv_dm_csr_aliasing.1835328515 |
| Directory | /workspace/1.rv_dm_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.758443678 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 2826239252 ps |
| CPU time | 28.19 seconds |
| Started | May 09 01:16:38 PM PDT 24 |
| Finished | May 09 01:17:09 PM PDT 24 |
| Peak memory | 205028 kb |
| Host | smart-7311b3e4-350e-4942-9414-1c2c1b02f00a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758443678 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.758443678 |
| Directory | /workspace/1.rv_dm_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.772677008 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 206471595 ps |
| CPU time | 1.63 seconds |
| Started | May 09 01:16:38 PM PDT 24 |
| Finished | May 09 01:16:43 PM PDT 24 |
| Peak memory | 213096 kb |
| Host | smart-28eaece3-1144-4592-b267-df2ac17dbc64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772677008 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.772677008 |
| Directory | /workspace/1.rv_dm_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2318821248 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 2785452996 ps |
| CPU time | 3.26 seconds |
| Started | May 09 01:16:38 PM PDT 24 |
| Finished | May 09 01:16:44 PM PDT 24 |
| Peak memory | 215708 kb |
| Host | smart-79085da0-0f56-4fc5-bb7b-7b0ab4bb0358 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318821248 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.2318821248 |
| Directory | /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.3210199297 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 38958994 ps |
| CPU time | 2.14 seconds |
| Started | May 09 01:16:35 PM PDT 24 |
| Finished | May 09 01:16:40 PM PDT 24 |
| Peak memory | 213156 kb |
| Host | smart-67d2e3f8-a831-4357-93cd-6baa663ee80d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210199297 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.3210199297 |
| Directory | /workspace/1.rv_dm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1691414049 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 16220628327 ps |
| CPU time | 13.89 seconds |
| Started | May 09 01:16:36 PM PDT 24 |
| Finished | May 09 01:16:53 PM PDT 24 |
| Peak memory | 204912 kb |
| Host | smart-65386548-93c7-49ce-b3e3-e60c001a0242 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691414049 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs r_aliasing.1691414049 |
| Directory | /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.84305493 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 49199746341 ps |
| CPU time | 176.68 seconds |
| Started | May 09 01:16:33 PM PDT 24 |
| Finished | May 09 01:19:31 PM PDT 24 |
| Peak memory | 204960 kb |
| Host | smart-279ea60f-9c5e-46df-92f8-ffb3e6c9cedd |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84305493 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_ bit_bash.84305493 |
| Directory | /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.3140590313 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 1001267613 ps |
| CPU time | 3.82 seconds |
| Started | May 09 01:16:36 PM PDT 24 |
| Finished | May 09 01:16:42 PM PDT 24 |
| Peak memory | 204840 kb |
| Host | smart-ca2e0d68-dc16-4047-84c7-96f6a8ae72e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140590313 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs r_hw_reset.3140590313 |
| Directory | /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1374550940 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 783882363 ps |
| CPU time | 2.89 seconds |
| Started | May 09 01:16:36 PM PDT 24 |
| Finished | May 09 01:16:42 PM PDT 24 |
| Peak memory | 204864 kb |
| Host | smart-b28ec8bc-4213-4111-a3a2-368ac65e12bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374550940 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.1 374550940 |
| Directory | /workspace/1.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2010477020 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 428087441 ps |
| CPU time | 1.05 seconds |
| Started | May 09 01:16:37 PM PDT 24 |
| Finished | May 09 01:16:41 PM PDT 24 |
| Peak memory | 204600 kb |
| Host | smart-eeecd4aa-d452-4554-97b8-6efefc1a2ed8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010477020 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_aliasing.2010477020 |
| Directory | /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.3172733161 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 514681384 ps |
| CPU time | 1.41 seconds |
| Started | May 09 01:16:37 PM PDT 24 |
| Finished | May 09 01:16:41 PM PDT 24 |
| Peak memory | 204784 kb |
| Host | smart-efdef1f5-90d7-46a6-b481-f6dcfbc1f375 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172733161 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_bit_bash.3172733161 |
| Directory | /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2374354378 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 92063560 ps |
| CPU time | 0.79 seconds |
| Started | May 09 01:16:36 PM PDT 24 |
| Finished | May 09 01:16:39 PM PDT 24 |
| Peak memory | 204668 kb |
| Host | smart-135e866b-898a-4021-8e17-709eb7dbf3c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374354378 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_hw_reset.2374354378 |
| Directory | /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3837338998 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 95615579 ps |
| CPU time | 0.94 seconds |
| Started | May 09 01:16:36 PM PDT 24 |
| Finished | May 09 01:16:40 PM PDT 24 |
| Peak memory | 204608 kb |
| Host | smart-17e4b820-3b3e-4457-8c30-31a68aa1a29f |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837338998 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.3 837338998 |
| Directory | /workspace/1.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2056915891 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 23812474 ps |
| CPU time | 0.68 seconds |
| Started | May 09 01:16:36 PM PDT 24 |
| Finished | May 09 01:16:39 PM PDT 24 |
| Peak memory | 204612 kb |
| Host | smart-721eaa00-f029-45e9-b4a7-ef499da7bf3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056915891 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par tial_access.2056915891 |
| Directory | /workspace/1.rv_dm_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.3310154526 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 20518503 ps |
| CPU time | 0.69 seconds |
| Started | May 09 01:16:35 PM PDT 24 |
| Finished | May 09 01:16:37 PM PDT 24 |
| Peak memory | 204632 kb |
| Host | smart-d33cb940-1259-433b-8a63-75fc576c3f0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310154526 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.3310154526 |
| Directory | /workspace/1.rv_dm_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3248115168 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 913412729 ps |
| CPU time | 4.05 seconds |
| Started | May 09 01:16:37 PM PDT 24 |
| Finished | May 09 01:16:45 PM PDT 24 |
| Peak memory | 204912 kb |
| Host | smart-dce49fdd-366d-4458-aef3-a788f6243155 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248115168 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_ csr_outstanding.3248115168 |
| Directory | /workspace/1.rv_dm_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.2239146328 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 1294312246 ps |
| CPU time | 15.37 seconds |
| Started | May 09 01:16:37 PM PDT 24 |
| Finished | May 09 01:16:56 PM PDT 24 |
| Peak memory | 221164 kb |
| Host | smart-7edeea8b-8ee1-435e-84c5-788708cfc3f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239146328 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.2239146328 |
| Directory | /workspace/1.rv_dm_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3916493183 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 52647151 ps |
| CPU time | 2.41 seconds |
| Started | May 09 01:16:51 PM PDT 24 |
| Finished | May 09 01:16:55 PM PDT 24 |
| Peak memory | 218956 kb |
| Host | smart-22d89ecc-67fd-4060-9c8e-71a43899481e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916493183 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.3916493183 |
| Directory | /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.1840104550 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 314624820 ps |
| CPU time | 2.49 seconds |
| Started | May 09 01:16:48 PM PDT 24 |
| Finished | May 09 01:16:51 PM PDT 24 |
| Peak memory | 221352 kb |
| Host | smart-dc858509-9191-4947-8682-094704e95ccf |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840104550 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.1840104550 |
| Directory | /workspace/10.rv_dm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3181251658 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 798586778 ps |
| CPU time | 3.23 seconds |
| Started | May 09 01:16:45 PM PDT 24 |
| Finished | May 09 01:16:50 PM PDT 24 |
| Peak memory | 204748 kb |
| Host | smart-1f6d3fbb-e394-4004-b91c-7ae62b1c942f |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181251658 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw. 3181251658 |
| Directory | /workspace/10.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.3704882944 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 40345006 ps |
| CPU time | 0.7 seconds |
| Started | May 09 01:16:52 PM PDT 24 |
| Finished | May 09 01:16:56 PM PDT 24 |
| Peak memory | 204636 kb |
| Host | smart-9ed0618c-97ab-45cc-af08-94cea60e7e0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704882944 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw. 3704882944 |
| Directory | /workspace/10.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.1941595102 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 449610179 ps |
| CPU time | 3.79 seconds |
| Started | May 09 01:16:46 PM PDT 24 |
| Finished | May 09 01:16:51 PM PDT 24 |
| Peak memory | 205152 kb |
| Host | smart-ac541ee1-1159-402c-96ac-2850507a63e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941595102 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same _csr_outstanding.1941595102 |
| Directory | /workspace/10.rv_dm_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_dm_tap_fsm_rand_reset.3174404273 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 21888233773 ps |
| CPU time | 14.96 seconds |
| Started | May 09 01:16:44 PM PDT 24 |
| Finished | May 09 01:17:01 PM PDT 24 |
| Peak memory | 221452 kb |
| Host | smart-ed42552f-43b7-4ca8-abf6-d49e609d2284 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174404273 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 10.rv_dm_tap_fsm_rand_reset.3174404273 |
| Directory | /workspace/10.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.2840710461 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 724546514 ps |
| CPU time | 5.06 seconds |
| Started | May 09 01:16:54 PM PDT 24 |
| Finished | May 09 01:17:03 PM PDT 24 |
| Peak memory | 213116 kb |
| Host | smart-01e0b512-e074-4bb5-9431-2e9ae60ee4f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840710461 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.2840710461 |
| Directory | /workspace/10.rv_dm_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.961652185 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 3332523603 ps |
| CPU time | 19.33 seconds |
| Started | May 09 01:16:54 PM PDT 24 |
| Finished | May 09 01:17:18 PM PDT 24 |
| Peak memory | 219360 kb |
| Host | smart-a0611d4f-34d4-4d96-a73e-6d8b77ef55c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961652185 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.961652185 |
| Directory | /workspace/10.rv_dm_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.494808266 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 76079625 ps |
| CPU time | 3.49 seconds |
| Started | May 09 01:16:51 PM PDT 24 |
| Finished | May 09 01:16:56 PM PDT 24 |
| Peak memory | 218744 kb |
| Host | smart-cc244010-c195-49eb-b34b-cbc0473b431c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494808266 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.494808266 |
| Directory | /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.3936796099 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 397511250 ps |
| CPU time | 2.26 seconds |
| Started | May 09 01:16:51 PM PDT 24 |
| Finished | May 09 01:16:54 PM PDT 24 |
| Peak memory | 213208 kb |
| Host | smart-3c42deb1-a719-4fc0-a8ab-307666558bda |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936796099 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.3936796099 |
| Directory | /workspace/11.rv_dm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.2647493422 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 307405086 ps |
| CPU time | 1.69 seconds |
| Started | May 09 01:16:52 PM PDT 24 |
| Finished | May 09 01:16:57 PM PDT 24 |
| Peak memory | 204816 kb |
| Host | smart-d3f91752-3618-48e9-af2c-9026d4560d17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647493422 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw. 2647493422 |
| Directory | /workspace/11.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.2094175806 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 28194536 ps |
| CPU time | 0.74 seconds |
| Started | May 09 01:16:52 PM PDT 24 |
| Finished | May 09 01:16:57 PM PDT 24 |
| Peak memory | 204640 kb |
| Host | smart-3ad2f8d5-0a33-4042-be5e-9f1607204135 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094175806 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw. 2094175806 |
| Directory | /workspace/11.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.4265439225 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 86245732 ps |
| CPU time | 2.67 seconds |
| Started | May 09 01:16:53 PM PDT 24 |
| Finished | May 09 01:17:00 PM PDT 24 |
| Peak memory | 213240 kb |
| Host | smart-7ebe733d-49e6-480d-8ba1-17a1970dd788 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265439225 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.4265439225 |
| Directory | /workspace/11.rv_dm_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.59444087 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 1642373894 ps |
| CPU time | 3.77 seconds |
| Started | May 09 01:16:46 PM PDT 24 |
| Finished | May 09 01:16:51 PM PDT 24 |
| Peak memory | 221032 kb |
| Host | smart-a9fee915-5922-4071-b44a-1eba0f0d1c21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59444087 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.59444087 |
| Directory | /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.2971793276 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 106768840 ps |
| CPU time | 2.41 seconds |
| Started | May 09 01:16:51 PM PDT 24 |
| Finished | May 09 01:16:57 PM PDT 24 |
| Peak memory | 221248 kb |
| Host | smart-d15d1597-fb8f-4788-b902-46b697badd63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971793276 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.2971793276 |
| Directory | /workspace/12.rv_dm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.2357258101 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 1816021865 ps |
| CPU time | 4.02 seconds |
| Started | May 09 01:16:54 PM PDT 24 |
| Finished | May 09 01:17:02 PM PDT 24 |
| Peak memory | 204824 kb |
| Host | smart-0cd398c8-7baa-49e6-98cc-03cdc657fa33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357258101 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw. 2357258101 |
| Directory | /workspace/12.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2572389041 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 72133133 ps |
| CPU time | 0.72 seconds |
| Started | May 09 01:16:51 PM PDT 24 |
| Finished | May 09 01:16:53 PM PDT 24 |
| Peak memory | 204652 kb |
| Host | smart-15d91f46-a8ee-4cda-bc67-dc8054f25096 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572389041 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw. 2572389041 |
| Directory | /workspace/12.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.2954829092 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 290516414 ps |
| CPU time | 6.42 seconds |
| Started | May 09 01:16:53 PM PDT 24 |
| Finished | May 09 01:17:03 PM PDT 24 |
| Peak memory | 204820 kb |
| Host | smart-dfd8af0a-54c4-4ff7-b0f5-0815ea0b1b4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954829092 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same _csr_outstanding.2954829092 |
| Directory | /workspace/12.rv_dm_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.356877627 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 273678061 ps |
| CPU time | 4.79 seconds |
| Started | May 09 01:16:47 PM PDT 24 |
| Finished | May 09 01:16:53 PM PDT 24 |
| Peak memory | 213176 kb |
| Host | smart-c3858dcd-56ad-452e-895d-1105dbf51144 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356877627 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.356877627 |
| Directory | /workspace/12.rv_dm_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.1579692507 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 2003694276 ps |
| CPU time | 18.86 seconds |
| Started | May 09 01:16:53 PM PDT 24 |
| Finished | May 09 01:17:17 PM PDT 24 |
| Peak memory | 213192 kb |
| Host | smart-50c27f48-0959-4e34-859b-47af0ae219aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579692507 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.1 579692507 |
| Directory | /workspace/12.rv_dm_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3487715590 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 1694249406 ps |
| CPU time | 4.82 seconds |
| Started | May 09 01:16:54 PM PDT 24 |
| Finished | May 09 01:17:03 PM PDT 24 |
| Peak memory | 214268 kb |
| Host | smart-df5be509-2cd5-4624-a739-ecc5a31a05ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487715590 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.3487715590 |
| Directory | /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.4197234236 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 89657970 ps |
| CPU time | 2.32 seconds |
| Started | May 09 01:16:52 PM PDT 24 |
| Finished | May 09 01:16:58 PM PDT 24 |
| Peak memory | 221280 kb |
| Host | smart-8c2d75c8-0eb3-4b4c-b3d4-3432edaefa67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197234236 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.4197234236 |
| Directory | /workspace/13.rv_dm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.1390744813 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 870841346 ps |
| CPU time | 3.19 seconds |
| Started | May 09 01:16:54 PM PDT 24 |
| Finished | May 09 01:17:01 PM PDT 24 |
| Peak memory | 204764 kb |
| Host | smart-9c8cdf39-cfd2-42eb-a023-83708a0d9a10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390744813 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw. 1390744813 |
| Directory | /workspace/13.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.367741348 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 32687765 ps |
| CPU time | 0.69 seconds |
| Started | May 09 01:16:54 PM PDT 24 |
| Finished | May 09 01:16:59 PM PDT 24 |
| Peak memory | 204644 kb |
| Host | smart-eeb572f6-b1ab-4126-a081-248a62bae612 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367741348 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.367741348 |
| Directory | /workspace/13.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.4235903881 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 2361949354 ps |
| CPU time | 7.24 seconds |
| Started | May 09 01:16:50 PM PDT 24 |
| Finished | May 09 01:16:58 PM PDT 24 |
| Peak memory | 204988 kb |
| Host | smart-0d1c5ed4-0358-4ef9-a2c7-843375b18cbc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235903881 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same _csr_outstanding.4235903881 |
| Directory | /workspace/13.rv_dm_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.4052330377 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 349576821 ps |
| CPU time | 4.32 seconds |
| Started | May 09 01:16:59 PM PDT 24 |
| Finished | May 09 01:17:06 PM PDT 24 |
| Peak memory | 212564 kb |
| Host | smart-3405d4b7-9b03-4eb8-b2be-73afd4ea6639 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052330377 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.4052330377 |
| Directory | /workspace/13.rv_dm_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.188984902 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 1583873819 ps |
| CPU time | 14.59 seconds |
| Started | May 09 01:16:51 PM PDT 24 |
| Finished | May 09 01:17:08 PM PDT 24 |
| Peak memory | 221372 kb |
| Host | smart-1e17f761-4cbd-4db8-b5d8-269d37e0c4d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188984902 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.188984902 |
| Directory | /workspace/13.rv_dm_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.544267157 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 3932766531 ps |
| CPU time | 5.06 seconds |
| Started | May 09 01:16:54 PM PDT 24 |
| Finished | May 09 01:17:04 PM PDT 24 |
| Peak memory | 217356 kb |
| Host | smart-f80a4de8-7156-4142-909d-a8fcbe9053b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544267157 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.544267157 |
| Directory | /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.1379596316 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 56515207 ps |
| CPU time | 1.4 seconds |
| Started | May 09 01:16:52 PM PDT 24 |
| Finished | May 09 01:16:58 PM PDT 24 |
| Peak memory | 221228 kb |
| Host | smart-ad149091-d4e0-4f9a-8ad0-98fa7b1e06b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379596316 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.1379596316 |
| Directory | /workspace/14.rv_dm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.516677549 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 416041733 ps |
| CPU time | 1.12 seconds |
| Started | May 09 01:16:53 PM PDT 24 |
| Finished | May 09 01:16:58 PM PDT 24 |
| Peak memory | 204812 kb |
| Host | smart-6188c7c6-d056-41e9-a5fe-f174e66ebba1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516677549 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.516677549 |
| Directory | /workspace/14.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.3999566830 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 30550959 ps |
| CPU time | 0.7 seconds |
| Started | May 09 01:16:53 PM PDT 24 |
| Finished | May 09 01:16:58 PM PDT 24 |
| Peak memory | 204644 kb |
| Host | smart-7f4f4cae-62b6-4f50-8ac9-c782500d9468 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999566830 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw. 3999566830 |
| Directory | /workspace/14.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.198379399 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 522449147 ps |
| CPU time | 3.95 seconds |
| Started | May 09 01:16:56 PM PDT 24 |
| Finished | May 09 01:17:04 PM PDT 24 |
| Peak memory | 204884 kb |
| Host | smart-5492ee44-b843-431e-90d5-6e3170087783 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198379399 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same_ csr_outstanding.198379399 |
| Directory | /workspace/14.rv_dm_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.169291190 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 1554225746 ps |
| CPU time | 3.51 seconds |
| Started | May 09 01:16:53 PM PDT 24 |
| Finished | May 09 01:17:00 PM PDT 24 |
| Peak memory | 213232 kb |
| Host | smart-84b21c38-87a1-4d4b-9f82-2e631039f5fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169291190 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.169291190 |
| Directory | /workspace/14.rv_dm_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3919541478 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 1944097737 ps |
| CPU time | 14.99 seconds |
| Started | May 09 01:16:56 PM PDT 24 |
| Finished | May 09 01:17:15 PM PDT 24 |
| Peak memory | 214952 kb |
| Host | smart-69fa0cf4-6554-4566-b1e6-c1d731948314 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919541478 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.3 919541478 |
| Directory | /workspace/14.rv_dm_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.610804202 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 643434008 ps |
| CPU time | 4.28 seconds |
| Started | May 09 01:16:59 PM PDT 24 |
| Finished | May 09 01:17:06 PM PDT 24 |
| Peak memory | 221296 kb |
| Host | smart-3d086aa6-c7f9-411b-a74f-fcc5e54b2795 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610804202 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.610804202 |
| Directory | /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2564747613 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 137216839 ps |
| CPU time | 2.16 seconds |
| Started | May 09 01:16:56 PM PDT 24 |
| Finished | May 09 01:17:02 PM PDT 24 |
| Peak memory | 213180 kb |
| Host | smart-7a4ed6fa-8ab5-45d3-88f2-c2b1da7c3175 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564747613 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.2564747613 |
| Directory | /workspace/15.rv_dm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.872445550 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 339759182 ps |
| CPU time | 2 seconds |
| Started | May 09 01:16:46 PM PDT 24 |
| Finished | May 09 01:16:49 PM PDT 24 |
| Peak memory | 204796 kb |
| Host | smart-d8f327ff-dc8d-4e56-beb9-55c7441ff445 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872445550 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.872445550 |
| Directory | /workspace/15.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3057353314 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 250831154 ps |
| CPU time | 0.75 seconds |
| Started | May 09 01:16:52 PM PDT 24 |
| Finished | May 09 01:16:55 PM PDT 24 |
| Peak memory | 204636 kb |
| Host | smart-b6a265a2-dc4f-463c-a6f4-324198abe224 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057353314 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw. 3057353314 |
| Directory | /workspace/15.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.870416171 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 396556089 ps |
| CPU time | 3.89 seconds |
| Started | May 09 01:16:56 PM PDT 24 |
| Finished | May 09 01:17:04 PM PDT 24 |
| Peak memory | 204992 kb |
| Host | smart-892eb052-d558-4959-a411-db7ee4e28a4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870416171 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same_ csr_outstanding.870416171 |
| Directory | /workspace/15.rv_dm_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_dm_tap_fsm_rand_reset.1447379859 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 19101289072 ps |
| CPU time | 32.96 seconds |
| Started | May 09 01:16:54 PM PDT 24 |
| Finished | May 09 01:17:31 PM PDT 24 |
| Peak memory | 221524 kb |
| Host | smart-3f31ccbd-98e4-4714-9114-fb4d5b77c930 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447379859 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 15.rv_dm_tap_fsm_rand_reset.1447379859 |
| Directory | /workspace/15.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.2428693429 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 624858984 ps |
| CPU time | 3.64 seconds |
| Started | May 09 01:16:59 PM PDT 24 |
| Finished | May 09 01:17:05 PM PDT 24 |
| Peak memory | 212544 kb |
| Host | smart-394b0c41-eec5-41a9-b22b-c9c2074efa3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428693429 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.2428693429 |
| Directory | /workspace/15.rv_dm_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.554126908 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 1991113557 ps |
| CPU time | 3.38 seconds |
| Started | May 09 01:16:52 PM PDT 24 |
| Finished | May 09 01:16:58 PM PDT 24 |
| Peak memory | 214504 kb |
| Host | smart-7d901476-c231-40b2-afea-99dbad4cb4a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554126908 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.554126908 |
| Directory | /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2382236857 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 218155630 ps |
| CPU time | 1.54 seconds |
| Started | May 09 01:16:55 PM PDT 24 |
| Finished | May 09 01:17:01 PM PDT 24 |
| Peak memory | 213072 kb |
| Host | smart-67d272bb-2558-46eb-b2b3-e68d6a64c6de |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382236857 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.2382236857 |
| Directory | /workspace/16.rv_dm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2184287999 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 743719680 ps |
| CPU time | 2.91 seconds |
| Started | May 09 01:16:44 PM PDT 24 |
| Finished | May 09 01:16:48 PM PDT 24 |
| Peak memory | 204876 kb |
| Host | smart-81aa0dad-58eb-4832-ad4b-6a518ba9e68c |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184287999 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw. 2184287999 |
| Directory | /workspace/16.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3926595212 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 45427281 ps |
| CPU time | 0.82 seconds |
| Started | May 09 01:16:59 PM PDT 24 |
| Finished | May 09 01:17:02 PM PDT 24 |
| Peak memory | 204640 kb |
| Host | smart-2a89850b-2a73-4716-b2bf-3e13a956c7a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926595212 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw. 3926595212 |
| Directory | /workspace/16.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3523867739 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 283206845 ps |
| CPU time | 6.62 seconds |
| Started | May 09 01:16:50 PM PDT 24 |
| Finished | May 09 01:16:58 PM PDT 24 |
| Peak memory | 204996 kb |
| Host | smart-9daeed92-4619-4ef9-adc4-af8590c8dd70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523867739 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same _csr_outstanding.3523867739 |
| Directory | /workspace/16.rv_dm_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.2933529495 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 248754791 ps |
| CPU time | 4.39 seconds |
| Started | May 09 01:16:58 PM PDT 24 |
| Finished | May 09 01:17:06 PM PDT 24 |
| Peak memory | 213216 kb |
| Host | smart-64e060cb-137d-41a5-b215-b4aee9f9cb54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933529495 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.2933529495 |
| Directory | /workspace/16.rv_dm_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.3433630408 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 764575816 ps |
| CPU time | 16.26 seconds |
| Started | May 09 01:16:51 PM PDT 24 |
| Finished | May 09 01:17:10 PM PDT 24 |
| Peak memory | 213140 kb |
| Host | smart-affdae7c-88a4-4b15-8a83-343553ca3a84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433630408 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.3 433630408 |
| Directory | /workspace/16.rv_dm_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.1168160682 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 2346443273 ps |
| CPU time | 4.29 seconds |
| Started | May 09 01:16:51 PM PDT 24 |
| Finished | May 09 01:16:57 PM PDT 24 |
| Peak memory | 215336 kb |
| Host | smart-03c1d2da-2019-452b-86f3-bdecd1a5c323 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168160682 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.1168160682 |
| Directory | /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.247233876 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 101492307 ps |
| CPU time | 2.4 seconds |
| Started | May 09 01:16:55 PM PDT 24 |
| Finished | May 09 01:17:02 PM PDT 24 |
| Peak memory | 218712 kb |
| Host | smart-b84b6661-aa60-41a1-9d22-9f4e81c50286 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247233876 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.247233876 |
| Directory | /workspace/17.rv_dm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.4153165123 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 1670631589 ps |
| CPU time | 5.87 seconds |
| Started | May 09 01:16:44 PM PDT 24 |
| Finished | May 09 01:16:52 PM PDT 24 |
| Peak memory | 204916 kb |
| Host | smart-704fa762-d28d-426c-9aa1-7ce8425c1357 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153165123 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw. 4153165123 |
| Directory | /workspace/17.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.4031850685 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 51397823 ps |
| CPU time | 0.74 seconds |
| Started | May 09 01:16:51 PM PDT 24 |
| Finished | May 09 01:16:53 PM PDT 24 |
| Peak memory | 204624 kb |
| Host | smart-9cc01af8-e7f3-406b-92ba-337fab10bc77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031850685 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw. 4031850685 |
| Directory | /workspace/17.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2633819071 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 802050185 ps |
| CPU time | 7.39 seconds |
| Started | May 09 01:16:56 PM PDT 24 |
| Finished | May 09 01:17:07 PM PDT 24 |
| Peak memory | 204984 kb |
| Host | smart-83fddcba-7372-4934-b126-1ead4ea817aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633819071 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same _csr_outstanding.2633819071 |
| Directory | /workspace/17.rv_dm_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_dm_tap_fsm_rand_reset.3306390435 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 9913411195 ps |
| CPU time | 17.34 seconds |
| Started | May 09 01:16:56 PM PDT 24 |
| Finished | May 09 01:17:17 PM PDT 24 |
| Peak memory | 219476 kb |
| Host | smart-f24ec736-2d2a-455f-9a52-cbbe13b585c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306390435 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 17.rv_dm_tap_fsm_rand_reset.3306390435 |
| Directory | /workspace/17.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.827104349 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 98874966 ps |
| CPU time | 3.24 seconds |
| Started | May 09 01:16:56 PM PDT 24 |
| Finished | May 09 01:17:03 PM PDT 24 |
| Peak memory | 213248 kb |
| Host | smart-0eb09107-f288-4dcc-a0c3-84b51687101a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827104349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.827104349 |
| Directory | /workspace/17.rv_dm_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.19984183 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 2196610376 ps |
| CPU time | 5.78 seconds |
| Started | May 09 01:16:53 PM PDT 24 |
| Finished | May 09 01:17:02 PM PDT 24 |
| Peak memory | 218048 kb |
| Host | smart-8d400ce7-f697-412e-adf7-055700fe428c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19984183 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.19984183 |
| Directory | /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2701204295 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 108915401 ps |
| CPU time | 2.39 seconds |
| Started | May 09 01:16:53 PM PDT 24 |
| Finished | May 09 01:16:59 PM PDT 24 |
| Peak memory | 213176 kb |
| Host | smart-a14d8074-9acd-4dd0-875d-14b024eb86ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701204295 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.2701204295 |
| Directory | /workspace/18.rv_dm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1738272544 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 1961670755 ps |
| CPU time | 6.78 seconds |
| Started | May 09 01:16:49 PM PDT 24 |
| Finished | May 09 01:16:57 PM PDT 24 |
| Peak memory | 204860 kb |
| Host | smart-1d8d23da-5bb0-44cf-bbf3-71631bb963c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738272544 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw. 1738272544 |
| Directory | /workspace/18.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.4246909381 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 26804416 ps |
| CPU time | 0.72 seconds |
| Started | May 09 01:16:50 PM PDT 24 |
| Finished | May 09 01:16:52 PM PDT 24 |
| Peak memory | 204624 kb |
| Host | smart-a4be9cd6-ad17-493b-8286-516749d0c8e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246909381 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw. 4246909381 |
| Directory | /workspace/18.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3533694788 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 603222514 ps |
| CPU time | 6.39 seconds |
| Started | May 09 01:16:55 PM PDT 24 |
| Finished | May 09 01:17:06 PM PDT 24 |
| Peak memory | 204832 kb |
| Host | smart-5492d254-0646-4d42-811f-18d0264d2e57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533694788 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same _csr_outstanding.3533694788 |
| Directory | /workspace/18.rv_dm_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.1776473209 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 818322717 ps |
| CPU time | 3.44 seconds |
| Started | May 09 01:16:49 PM PDT 24 |
| Finished | May 09 01:16:53 PM PDT 24 |
| Peak memory | 213204 kb |
| Host | smart-b0766404-6a04-4309-9e51-3cef7d5735fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776473209 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.1776473209 |
| Directory | /workspace/18.rv_dm_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3317857447 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 314257415 ps |
| CPU time | 8.57 seconds |
| Started | May 09 01:16:51 PM PDT 24 |
| Finished | May 09 01:17:02 PM PDT 24 |
| Peak memory | 221164 kb |
| Host | smart-af6b3380-50ca-4ac8-8281-353883c9b648 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317857447 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.3 317857447 |
| Directory | /workspace/18.rv_dm_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.583623187 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 3899042056 ps |
| CPU time | 8.73 seconds |
| Started | May 09 01:16:52 PM PDT 24 |
| Finished | May 09 01:17:04 PM PDT 24 |
| Peak memory | 221048 kb |
| Host | smart-86c086df-638f-4e4c-a36b-b3ab1d283aa5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583623187 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.583623187 |
| Directory | /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.655174793 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 365000773 ps |
| CPU time | 2.35 seconds |
| Started | May 09 01:16:55 PM PDT 24 |
| Finished | May 09 01:17:01 PM PDT 24 |
| Peak memory | 221324 kb |
| Host | smart-0bde9c38-57d2-4143-86ff-6794b4e07774 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655174793 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.655174793 |
| Directory | /workspace/19.rv_dm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.4161689171 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 258569687 ps |
| CPU time | 1.65 seconds |
| Started | May 09 01:16:56 PM PDT 24 |
| Finished | May 09 01:17:02 PM PDT 24 |
| Peak memory | 204860 kb |
| Host | smart-4b161293-cb61-4982-b501-fb6e590f0159 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161689171 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw. 4161689171 |
| Directory | /workspace/19.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.187138334 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 34095380 ps |
| CPU time | 0.74 seconds |
| Started | May 09 01:16:54 PM PDT 24 |
| Finished | May 09 01:17:00 PM PDT 24 |
| Peak memory | 204652 kb |
| Host | smart-3ed77e7f-3f42-4cab-892c-5c9729e6ffe5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187138334 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.187138334 |
| Directory | /workspace/19.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.2535833294 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 252172162 ps |
| CPU time | 3.87 seconds |
| Started | May 09 01:16:53 PM PDT 24 |
| Finished | May 09 01:17:01 PM PDT 24 |
| Peak memory | 213132 kb |
| Host | smart-89af179d-839f-411d-b069-d9df19a752f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535833294 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.2535833294 |
| Directory | /workspace/19.rv_dm_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2611946322 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 1162928338 ps |
| CPU time | 10.24 seconds |
| Started | May 09 01:16:52 PM PDT 24 |
| Finished | May 09 01:17:06 PM PDT 24 |
| Peak memory | 213196 kb |
| Host | smart-c76a56db-7aab-466d-90db-cd35b2d3b3ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611946322 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.2 611946322 |
| Directory | /workspace/19.rv_dm_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1723009114 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 6700807865 ps |
| CPU time | 32.72 seconds |
| Started | May 09 01:16:35 PM PDT 24 |
| Finished | May 09 01:17:10 PM PDT 24 |
| Peak memory | 205040 kb |
| Host | smart-f7a8f736-999a-4e3d-a75c-48c829a704da |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723009114 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 2.rv_dm_csr_aliasing.1723009114 |
| Directory | /workspace/2.rv_dm_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.3490636199 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 720313385 ps |
| CPU time | 27.71 seconds |
| Started | May 09 01:16:34 PM PDT 24 |
| Finished | May 09 01:17:03 PM PDT 24 |
| Peak memory | 205184 kb |
| Host | smart-18e01d08-a1d0-4af9-b419-dbb88296286d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490636199 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.3490636199 |
| Directory | /workspace/2.rv_dm_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.1535502225 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 391138624 ps |
| CPU time | 2.56 seconds |
| Started | May 09 01:16:35 PM PDT 24 |
| Finished | May 09 01:16:40 PM PDT 24 |
| Peak memory | 213212 kb |
| Host | smart-2a127156-d9b7-4eee-b3b6-3a59ee45dcb5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535502225 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.1535502225 |
| Directory | /workspace/2.rv_dm_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.1274036126 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 213812692 ps |
| CPU time | 4.24 seconds |
| Started | May 09 01:16:37 PM PDT 24 |
| Finished | May 09 01:16:44 PM PDT 24 |
| Peak memory | 218896 kb |
| Host | smart-d05bdb1a-2d42-42d2-bc83-f1c112b3b6bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274036126 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.1274036126 |
| Directory | /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3638277608 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 378950371 ps |
| CPU time | 2.26 seconds |
| Started | May 09 01:16:36 PM PDT 24 |
| Finished | May 09 01:16:41 PM PDT 24 |
| Peak memory | 217964 kb |
| Host | smart-afd8a871-212b-4485-a95a-35ffef8b68b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638277608 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.3638277608 |
| Directory | /workspace/2.rv_dm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.1449096481 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 3135698868 ps |
| CPU time | 7.39 seconds |
| Started | May 09 01:16:33 PM PDT 24 |
| Finished | May 09 01:16:42 PM PDT 24 |
| Peak memory | 204876 kb |
| Host | smart-bf25beee-75c1-4cfb-adab-061e27fa804f |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449096481 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs r_aliasing.1449096481 |
| Directory | /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2858460555 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 779307075 ps |
| CPU time | 3.14 seconds |
| Started | May 09 01:16:35 PM PDT 24 |
| Finished | May 09 01:16:40 PM PDT 24 |
| Peak memory | 204820 kb |
| Host | smart-b72e6ce3-c8b9-48b8-b18b-309a3e4a1576 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858460555 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs r_hw_reset.2858460555 |
| Directory | /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.3744949079 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 512799651 ps |
| CPU time | 1.19 seconds |
| Started | May 09 01:16:34 PM PDT 24 |
| Finished | May 09 01:16:36 PM PDT 24 |
| Peak memory | 204816 kb |
| Host | smart-3244469a-ab92-48df-8662-03ff98918210 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744949079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.3 744949079 |
| Directory | /workspace/2.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.2609750175 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 143645875 ps |
| CPU time | 1.14 seconds |
| Started | May 09 01:16:36 PM PDT 24 |
| Finished | May 09 01:16:39 PM PDT 24 |
| Peak memory | 204524 kb |
| Host | smart-ea7cdb02-7b4a-4eac-a480-cdd9c626ce69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609750175 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_aliasing.2609750175 |
| Directory | /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1069080947 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 845009988 ps |
| CPU time | 3.72 seconds |
| Started | May 09 01:16:36 PM PDT 24 |
| Finished | May 09 01:16:42 PM PDT 24 |
| Peak memory | 204780 kb |
| Host | smart-ec6060db-865b-4186-a4d9-7c032b0b7ff1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069080947 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_bit_bash.1069080947 |
| Directory | /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2368202890 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 58070779 ps |
| CPU time | 0.73 seconds |
| Started | May 09 01:16:32 PM PDT 24 |
| Finished | May 09 01:16:35 PM PDT 24 |
| Peak memory | 204656 kb |
| Host | smart-d3008851-c7d1-4b7d-96e7-79835d1b0bcd |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368202890 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_hw_reset.2368202890 |
| Directory | /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2399660359 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 43299229 ps |
| CPU time | 0.8 seconds |
| Started | May 09 01:16:34 PM PDT 24 |
| Finished | May 09 01:16:36 PM PDT 24 |
| Peak memory | 204644 kb |
| Host | smart-3ff1f67b-2ce6-4934-8c1f-c7c9e5afd231 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399660359 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.2 399660359 |
| Directory | /workspace/2.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.3212422121 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 22555897 ps |
| CPU time | 0.69 seconds |
| Started | May 09 01:16:37 PM PDT 24 |
| Finished | May 09 01:16:41 PM PDT 24 |
| Peak memory | 204592 kb |
| Host | smart-d8f5496c-35e4-42cb-abcd-0a5dd4e6093e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212422121 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par tial_access.3212422121 |
| Directory | /workspace/2.rv_dm_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.1605372418 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 32449622 ps |
| CPU time | 0.68 seconds |
| Started | May 09 01:16:33 PM PDT 24 |
| Finished | May 09 01:16:35 PM PDT 24 |
| Peak memory | 204624 kb |
| Host | smart-34cc5619-5450-4b64-9a62-0f2bf79fb202 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605372418 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.1605372418 |
| Directory | /workspace/2.rv_dm_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.1748829902 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 1109611228 ps |
| CPU time | 7.96 seconds |
| Started | May 09 01:16:39 PM PDT 24 |
| Finished | May 09 01:16:49 PM PDT 24 |
| Peak memory | 204888 kb |
| Host | smart-f8640be1-d218-4926-b296-6f98b8277220 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748829902 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_ csr_outstanding.1748829902 |
| Directory | /workspace/2.rv_dm_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.3782452522 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 277873718 ps |
| CPU time | 4.99 seconds |
| Started | May 09 01:16:36 PM PDT 24 |
| Finished | May 09 01:16:44 PM PDT 24 |
| Peak memory | 213232 kb |
| Host | smart-a364310c-40e9-48ef-b58a-8146bf43dfa3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782452522 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.3782452522 |
| Directory | /workspace/2.rv_dm_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/22.rv_dm_tap_fsm_rand_reset.3310699571 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 13474085687 ps |
| CPU time | 12.4 seconds |
| Started | May 09 01:16:54 PM PDT 24 |
| Finished | May 09 01:17:10 PM PDT 24 |
| Peak memory | 214916 kb |
| Host | smart-73378ff7-4e68-4e47-9cb6-10261d80e5e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310699571 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 22.rv_dm_tap_fsm_rand_reset.3310699571 |
| Directory | /workspace/22.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/25.rv_dm_tap_fsm_rand_reset.870685228 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 16783286635 ps |
| CPU time | 12.91 seconds |
| Started | May 09 01:16:56 PM PDT 24 |
| Finished | May 09 01:17:13 PM PDT 24 |
| Peak memory | 220272 kb |
| Host | smart-1415aaa8-999f-4dc2-88ba-33cc43583494 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870685228 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 25.rv_dm_tap_fsm_rand_reset.870685228 |
| Directory | /workspace/25.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/26.rv_dm_tap_fsm_rand_reset.4006203118 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 7906919428 ps |
| CPU time | 26.72 seconds |
| Started | May 09 01:16:53 PM PDT 24 |
| Finished | May 09 01:17:24 PM PDT 24 |
| Peak memory | 213352 kb |
| Host | smart-f35f3354-65dc-43e1-b877-9e3f7a00c90a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006203118 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 26.rv_dm_tap_fsm_rand_reset.4006203118 |
| Directory | /workspace/26.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/29.rv_dm_tap_fsm_rand_reset.401271601 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 23485465946 ps |
| CPU time | 30.35 seconds |
| Started | May 09 01:16:54 PM PDT 24 |
| Finished | May 09 01:17:28 PM PDT 24 |
| Peak memory | 226828 kb |
| Host | smart-aaba420e-b620-44fd-87f5-266222818e01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401271601 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 29.rv_dm_tap_fsm_rand_reset.401271601 |
| Directory | /workspace/29.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2362110577 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 13437769884 ps |
| CPU time | 73.83 seconds |
| Started | May 09 01:16:35 PM PDT 24 |
| Finished | May 09 01:17:51 PM PDT 24 |
| Peak memory | 205048 kb |
| Host | smart-3923b9da-29d8-449c-9f34-cf1c310c032c |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362110577 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 3.rv_dm_csr_aliasing.2362110577 |
| Directory | /workspace/3.rv_dm_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1420102925 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 9800640186 ps |
| CPU time | 68.98 seconds |
| Started | May 09 01:16:36 PM PDT 24 |
| Finished | May 09 01:17:47 PM PDT 24 |
| Peak memory | 205080 kb |
| Host | smart-b9e0b80b-f611-4b90-a7b3-9e31e1ec73f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420102925 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.1420102925 |
| Directory | /workspace/3.rv_dm_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1623689106 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 47682135 ps |
| CPU time | 2.33 seconds |
| Started | May 09 01:16:40 PM PDT 24 |
| Finished | May 09 01:16:45 PM PDT 24 |
| Peak memory | 213112 kb |
| Host | smart-301dff95-e139-41ba-9419-581bf4323af0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623689106 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.1623689106 |
| Directory | /workspace/3.rv_dm_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.886016336 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 41403466 ps |
| CPU time | 2.17 seconds |
| Started | May 09 01:16:39 PM PDT 24 |
| Finished | May 09 01:16:44 PM PDT 24 |
| Peak memory | 217724 kb |
| Host | smart-9c21f569-86ec-403c-86f8-6b1890353b50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886016336 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.886016336 |
| Directory | /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.783444935 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 555763728 ps |
| CPU time | 2.32 seconds |
| Started | May 09 01:16:40 PM PDT 24 |
| Finished | May 09 01:16:45 PM PDT 24 |
| Peak memory | 221320 kb |
| Host | smart-7964490c-e4e7-4749-bafc-150cd60667a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783444935 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.783444935 |
| Directory | /workspace/3.rv_dm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.3830699881 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 6098617454 ps |
| CPU time | 9.58 seconds |
| Started | May 09 01:16:35 PM PDT 24 |
| Finished | May 09 01:16:47 PM PDT 24 |
| Peak memory | 204916 kb |
| Host | smart-ed184a79-8d46-4101-ab93-457bc198c81d |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830699881 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs r_aliasing.3830699881 |
| Directory | /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1062179847 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 11882263716 ps |
| CPU time | 12.47 seconds |
| Started | May 09 01:16:36 PM PDT 24 |
| Finished | May 09 01:16:51 PM PDT 24 |
| Peak memory | 204944 kb |
| Host | smart-a9dc8dee-2c8a-4f51-90d8-eb1c186050b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062179847 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs r_bit_bash.1062179847 |
| Directory | /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2511136981 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 599225054 ps |
| CPU time | 1.81 seconds |
| Started | May 09 01:16:35 PM PDT 24 |
| Finished | May 09 01:16:39 PM PDT 24 |
| Peak memory | 204860 kb |
| Host | smart-42838129-04c6-4cdf-8763-aafd6809a4c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511136981 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs r_hw_reset.2511136981 |
| Directory | /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1946246188 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 509616642 ps |
| CPU time | 1.93 seconds |
| Started | May 09 01:16:37 PM PDT 24 |
| Finished | May 09 01:16:42 PM PDT 24 |
| Peak memory | 204736 kb |
| Host | smart-ac899b82-67fe-426d-80ae-132f196ce277 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946246188 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.1 946246188 |
| Directory | /workspace/3.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1093633860 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 267395780 ps |
| CPU time | 1.13 seconds |
| Started | May 09 01:16:35 PM PDT 24 |
| Finished | May 09 01:16:37 PM PDT 24 |
| Peak memory | 204532 kb |
| Host | smart-875995da-f038-47ed-8632-8b823d1cee62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093633860 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_aliasing.1093633860 |
| Directory | /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2967783789 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 2999706458 ps |
| CPU time | 6.59 seconds |
| Started | May 09 01:16:41 PM PDT 24 |
| Finished | May 09 01:16:50 PM PDT 24 |
| Peak memory | 204936 kb |
| Host | smart-1321a439-422c-42f5-a9ea-9fbb6e102b44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967783789 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_bit_bash.2967783789 |
| Directory | /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1583225272 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 89762283 ps |
| CPU time | 0.7 seconds |
| Started | May 09 01:16:36 PM PDT 24 |
| Finished | May 09 01:16:39 PM PDT 24 |
| Peak memory | 204584 kb |
| Host | smart-32b6c0d5-9a4f-48ea-b99b-583b9104b742 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583225272 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_hw_reset.1583225272 |
| Directory | /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2167333927 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 99014880 ps |
| CPU time | 0.94 seconds |
| Started | May 09 01:16:36 PM PDT 24 |
| Finished | May 09 01:16:39 PM PDT 24 |
| Peak memory | 204548 kb |
| Host | smart-c34af8db-c808-4733-8de5-f0daf457f503 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167333927 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.2 167333927 |
| Directory | /workspace/3.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.401174386 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 70518097 ps |
| CPU time | 0.69 seconds |
| Started | May 09 01:16:40 PM PDT 24 |
| Finished | May 09 01:16:43 PM PDT 24 |
| Peak memory | 204588 kb |
| Host | smart-d4f0972a-b594-4c92-9a4c-273d7a1af5c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401174386 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_part ial_access.401174386 |
| Directory | /workspace/3.rv_dm_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.2298988036 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 29031806 ps |
| CPU time | 0.72 seconds |
| Started | May 09 01:16:39 PM PDT 24 |
| Finished | May 09 01:16:43 PM PDT 24 |
| Peak memory | 204596 kb |
| Host | smart-ebcbbe83-0bb8-49c1-aff1-57cfbba613d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298988036 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.2298988036 |
| Directory | /workspace/3.rv_dm_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.1396527290 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 248886889 ps |
| CPU time | 4.31 seconds |
| Started | May 09 01:16:39 PM PDT 24 |
| Finished | May 09 01:16:46 PM PDT 24 |
| Peak memory | 205012 kb |
| Host | smart-a92cff63-e882-44ff-bb79-3e4224430124 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396527290 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_ csr_outstanding.1396527290 |
| Directory | /workspace/3.rv_dm_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.3261774058 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 15482465457 ps |
| CPU time | 19 seconds |
| Started | May 09 01:16:37 PM PDT 24 |
| Finished | May 09 01:16:59 PM PDT 24 |
| Peak memory | 214544 kb |
| Host | smart-d17c562d-860c-4480-b6e0-880a16a1b5d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261774058 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.3261774058 |
| Directory | /workspace/3.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2254008166 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 131035178 ps |
| CPU time | 3.08 seconds |
| Started | May 09 01:16:40 PM PDT 24 |
| Finished | May 09 01:16:46 PM PDT 24 |
| Peak memory | 213216 kb |
| Host | smart-09ae8e5f-e5b6-468d-a843-f250883745c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254008166 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.2254008166 |
| Directory | /workspace/3.rv_dm_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3845054845 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 1167776624 ps |
| CPU time | 10.35 seconds |
| Started | May 09 01:16:41 PM PDT 24 |
| Finished | May 09 01:16:54 PM PDT 24 |
| Peak memory | 213228 kb |
| Host | smart-552ca37a-8344-4134-b7ff-a83bebfa3a74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845054845 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.3845054845 |
| Directory | /workspace/3.rv_dm_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/30.rv_dm_tap_fsm_rand_reset.1889996411 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 20364888108 ps |
| CPU time | 15.47 seconds |
| Started | May 09 01:16:53 PM PDT 24 |
| Finished | May 09 01:17:13 PM PDT 24 |
| Peak memory | 219940 kb |
| Host | smart-7acc5d93-2573-4e17-8944-45da3fe3deb5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889996411 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 30.rv_dm_tap_fsm_rand_reset.1889996411 |
| Directory | /workspace/30.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/35.rv_dm_tap_fsm_rand_reset.1732486489 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 14176562667 ps |
| CPU time | 11.52 seconds |
| Started | May 09 01:16:55 PM PDT 24 |
| Finished | May 09 01:17:10 PM PDT 24 |
| Peak memory | 218604 kb |
| Host | smart-5e805d08-ae21-45a9-ace6-9af53e6e1be2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732486489 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 35.rv_dm_tap_fsm_rand_reset.1732486489 |
| Directory | /workspace/35.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.923085844 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 8255547181 ps |
| CPU time | 56.79 seconds |
| Started | May 09 01:16:36 PM PDT 24 |
| Finished | May 09 01:17:36 PM PDT 24 |
| Peak memory | 205104 kb |
| Host | smart-516e3317-82a7-402f-a8ae-ceca16897279 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923085844 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.923085844 |
| Directory | /workspace/4.rv_dm_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.1682879173 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 1243121661 ps |
| CPU time | 2.57 seconds |
| Started | May 09 01:16:45 PM PDT 24 |
| Finished | May 09 01:16:49 PM PDT 24 |
| Peak memory | 213196 kb |
| Host | smart-3ce36d81-935d-4861-a78c-e74414ad8e3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682879173 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.1682879173 |
| Directory | /workspace/4.rv_dm_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.1811780539 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 138200767 ps |
| CPU time | 2.21 seconds |
| Started | May 09 01:16:45 PM PDT 24 |
| Finished | May 09 01:16:48 PM PDT 24 |
| Peak memory | 215308 kb |
| Host | smart-2a893a14-ebcf-42c0-951f-f1a60f499dfa |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811780539 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.1811780539 |
| Directory | /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.2955693059 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 425719658 ps |
| CPU time | 2.42 seconds |
| Started | May 09 01:16:39 PM PDT 24 |
| Finished | May 09 01:16:45 PM PDT 24 |
| Peak memory | 218836 kb |
| Host | smart-999050cd-3576-492d-b461-b469f69bc26f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955693059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.2955693059 |
| Directory | /workspace/4.rv_dm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.1650993301 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 45799721714 ps |
| CPU time | 16.81 seconds |
| Started | May 09 01:16:41 PM PDT 24 |
| Finished | May 09 01:17:00 PM PDT 24 |
| Peak memory | 205244 kb |
| Host | smart-c1f0736c-3cf8-4dc5-aaf4-0ca52e8e105b |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650993301 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs r_aliasing.1650993301 |
| Directory | /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3126846894 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 14324293925 ps |
| CPU time | 28.09 seconds |
| Started | May 09 01:16:44 PM PDT 24 |
| Finished | May 09 01:17:14 PM PDT 24 |
| Peak memory | 204992 kb |
| Host | smart-b96ab6c4-24b3-4756-945a-0ac6695636a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126846894 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs r_bit_bash.3126846894 |
| Directory | /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.42323134 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 1755831801 ps |
| CPU time | 2.48 seconds |
| Started | May 09 01:16:38 PM PDT 24 |
| Finished | May 09 01:16:43 PM PDT 24 |
| Peak memory | 204888 kb |
| Host | smart-74533e2f-8153-42ab-8864-b052d4f3a41e |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42323134 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_ hw_reset.42323134 |
| Directory | /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.2951460887 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 482789729 ps |
| CPU time | 1.86 seconds |
| Started | May 09 01:16:45 PM PDT 24 |
| Finished | May 09 01:16:48 PM PDT 24 |
| Peak memory | 204824 kb |
| Host | smart-2ac47246-3e23-4e24-bb7d-809ab2f9d654 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951460887 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.2 951460887 |
| Directory | /workspace/4.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.1752577907 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 94293542 ps |
| CPU time | 0.95 seconds |
| Started | May 09 01:16:37 PM PDT 24 |
| Finished | May 09 01:16:40 PM PDT 24 |
| Peak memory | 204544 kb |
| Host | smart-85f00698-8c96-4705-8645-e8c10468723d |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752577907 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs r_aliasing.1752577907 |
| Directory | /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.341508325 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 1532076051 ps |
| CPU time | 2.87 seconds |
| Started | May 09 01:16:39 PM PDT 24 |
| Finished | May 09 01:16:45 PM PDT 24 |
| Peak memory | 204800 kb |
| Host | smart-fd3819da-9956-49c5-b840-01cba2594bac |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341508325 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr _bit_bash.341508325 |
| Directory | /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.1287023639 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 80525978 ps |
| CPU time | 0.78 seconds |
| Started | May 09 01:16:36 PM PDT 24 |
| Finished | May 09 01:16:40 PM PDT 24 |
| Peak memory | 204616 kb |
| Host | smart-00d41bf4-e4ad-4457-b574-31d08c7c26cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287023639 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs r_hw_reset.1287023639 |
| Directory | /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.1556047616 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 50760822 ps |
| CPU time | 0.78 seconds |
| Started | May 09 01:16:36 PM PDT 24 |
| Finished | May 09 01:16:39 PM PDT 24 |
| Peak memory | 204648 kb |
| Host | smart-8beca44f-b99a-4331-afa9-c44890658dbe |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556047616 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.1 556047616 |
| Directory | /workspace/4.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1549457201 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 15999920 ps |
| CPU time | 0.73 seconds |
| Started | May 09 01:16:39 PM PDT 24 |
| Finished | May 09 01:16:42 PM PDT 24 |
| Peak memory | 204636 kb |
| Host | smart-cfd5e598-ab54-4b8b-bee4-aca50f09102c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549457201 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par tial_access.1549457201 |
| Directory | /workspace/4.rv_dm_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.4209338761 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 21006826 ps |
| CPU time | 0.69 seconds |
| Started | May 09 01:16:42 PM PDT 24 |
| Finished | May 09 01:16:45 PM PDT 24 |
| Peak memory | 204552 kb |
| Host | smart-f382def9-5380-4ed0-8a05-47f48afa4740 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209338761 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.4209338761 |
| Directory | /workspace/4.rv_dm_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.2112011998 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 2315454078 ps |
| CPU time | 8.66 seconds |
| Started | May 09 01:16:39 PM PDT 24 |
| Finished | May 09 01:16:50 PM PDT 24 |
| Peak memory | 205076 kb |
| Host | smart-1e390b31-cd64-4ba7-ace7-1ef7a075d72f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112011998 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_ csr_outstanding.2112011998 |
| Directory | /workspace/4.rv_dm_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.1247466656 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 65025235 ps |
| CPU time | 3.21 seconds |
| Started | May 09 01:16:41 PM PDT 24 |
| Finished | May 09 01:16:47 PM PDT 24 |
| Peak memory | 213476 kb |
| Host | smart-c1fa6020-7ceb-471a-96de-e059f0bfedb4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247466656 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.1247466656 |
| Directory | /workspace/4.rv_dm_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3160584563 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 346953784 ps |
| CPU time | 3.63 seconds |
| Started | May 09 01:16:36 PM PDT 24 |
| Finished | May 09 01:16:43 PM PDT 24 |
| Peak memory | 218088 kb |
| Host | smart-ba0fd907-6d30-49c2-8924-5f76f7eae899 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160584563 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.3160584563 |
| Directory | /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.3744481305 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 41574996 ps |
| CPU time | 2.04 seconds |
| Started | May 09 01:16:45 PM PDT 24 |
| Finished | May 09 01:16:48 PM PDT 24 |
| Peak memory | 213116 kb |
| Host | smart-ca7f42cb-ba96-41cb-a86d-d5de087edaff |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744481305 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.3744481305 |
| Directory | /workspace/5.rv_dm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.1743333379 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 418843916 ps |
| CPU time | 1.29 seconds |
| Started | May 09 01:16:39 PM PDT 24 |
| Finished | May 09 01:16:44 PM PDT 24 |
| Peak memory | 204896 kb |
| Host | smart-8dc15ebe-810d-49bf-b5ec-d08ca3f590b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743333379 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.1 743333379 |
| Directory | /workspace/5.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.2717574953 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 126458942 ps |
| CPU time | 0.82 seconds |
| Started | May 09 01:16:43 PM PDT 24 |
| Finished | May 09 01:16:46 PM PDT 24 |
| Peak memory | 204584 kb |
| Host | smart-7caa1c6f-6e62-432b-a24f-71a2067d6856 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717574953 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.2 717574953 |
| Directory | /workspace/5.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.439007332 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 288820711 ps |
| CPU time | 4.02 seconds |
| Started | May 09 01:16:43 PM PDT 24 |
| Finished | May 09 01:16:49 PM PDT 24 |
| Peak memory | 204804 kb |
| Host | smart-0711aa9b-f9e8-40ff-af54-3085b6f73d89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439007332 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_c sr_outstanding.439007332 |
| Directory | /workspace/5.rv_dm_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.1996327386 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 355854337 ps |
| CPU time | 4.52 seconds |
| Started | May 09 01:16:40 PM PDT 24 |
| Finished | May 09 01:16:48 PM PDT 24 |
| Peak memory | 213056 kb |
| Host | smart-bf9e78b8-a666-487b-aef1-ff44fd061e3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996327386 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.1996327386 |
| Directory | /workspace/5.rv_dm_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.744625246 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 3773484336 ps |
| CPU time | 19.59 seconds |
| Started | May 09 01:16:41 PM PDT 24 |
| Finished | May 09 01:17:03 PM PDT 24 |
| Peak memory | 212964 kb |
| Host | smart-368f16ef-6382-455d-b9a7-d877ebdc1dad |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744625246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.744625246 |
| Directory | /workspace/5.rv_dm_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.3155743891 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 2163817199 ps |
| CPU time | 6.84 seconds |
| Started | May 09 01:16:59 PM PDT 24 |
| Finished | May 09 01:17:08 PM PDT 24 |
| Peak memory | 221476 kb |
| Host | smart-be14c6c1-01bb-44d6-befc-4ac3f8cc6997 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155743891 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.3155743891 |
| Directory | /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1496919187 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 218910177 ps |
| CPU time | 1.45 seconds |
| Started | May 09 01:16:49 PM PDT 24 |
| Finished | May 09 01:16:52 PM PDT 24 |
| Peak memory | 213132 kb |
| Host | smart-bbb96512-4c9b-4c9d-963a-b93ad70ce173 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496919187 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.1496919187 |
| Directory | /workspace/6.rv_dm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.682926831 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 258241078 ps |
| CPU time | 1.27 seconds |
| Started | May 09 01:16:40 PM PDT 24 |
| Finished | May 09 01:16:44 PM PDT 24 |
| Peak memory | 204816 kb |
| Host | smart-b4ab4597-5a16-4399-8694-36c176bc3ade |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682926831 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.682926831 |
| Directory | /workspace/6.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2317398830 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 83261748 ps |
| CPU time | 0.9 seconds |
| Started | May 09 01:16:38 PM PDT 24 |
| Finished | May 09 01:16:42 PM PDT 24 |
| Peak memory | 204652 kb |
| Host | smart-a9208f01-846c-4237-b2aa-49a5bb1d4e25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317398830 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.2 317398830 |
| Directory | /workspace/6.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.63712917 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 792110755 ps |
| CPU time | 7.34 seconds |
| Started | May 09 01:16:49 PM PDT 24 |
| Finished | May 09 01:16:58 PM PDT 24 |
| Peak memory | 205000 kb |
| Host | smart-6e4df9ef-8a52-4ab9-9493-5f662186f0ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63712917 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_cs r_outstanding.63712917 |
| Directory | /workspace/6.rv_dm_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.3170803245 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 228349225 ps |
| CPU time | 5.23 seconds |
| Started | May 09 01:16:51 PM PDT 24 |
| Finished | May 09 01:16:59 PM PDT 24 |
| Peak memory | 213212 kb |
| Host | smart-e62173e2-70ac-441d-bf8a-7c7151f8a36d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170803245 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.3170803245 |
| Directory | /workspace/6.rv_dm_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3585190793 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 3005823181 ps |
| CPU time | 4.27 seconds |
| Started | May 09 01:16:48 PM PDT 24 |
| Finished | May 09 01:16:54 PM PDT 24 |
| Peak memory | 219152 kb |
| Host | smart-83d25aba-ae09-4e00-b73e-5335958c7583 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585190793 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.3585190793 |
| Directory | /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.3300036098 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 105652964 ps |
| CPU time | 2.31 seconds |
| Started | May 09 01:16:44 PM PDT 24 |
| Finished | May 09 01:16:48 PM PDT 24 |
| Peak memory | 221248 kb |
| Host | smart-e6749033-e584-4409-973d-623919332416 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300036098 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.3300036098 |
| Directory | /workspace/7.rv_dm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.1664494861 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 259000169 ps |
| CPU time | 1.56 seconds |
| Started | May 09 01:16:43 PM PDT 24 |
| Finished | May 09 01:16:46 PM PDT 24 |
| Peak memory | 204816 kb |
| Host | smart-e630767f-dede-4cd1-a0d7-e5f74024f5fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664494861 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.1 664494861 |
| Directory | /workspace/7.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1328131472 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 42669831 ps |
| CPU time | 0.77 seconds |
| Started | May 09 01:16:51 PM PDT 24 |
| Finished | May 09 01:16:54 PM PDT 24 |
| Peak memory | 204564 kb |
| Host | smart-ededc589-c0ac-4d2f-8beb-9b7f95ef0833 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328131472 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.1 328131472 |
| Directory | /workspace/7.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.512750372 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 1628750135 ps |
| CPU time | 7.13 seconds |
| Started | May 09 01:16:51 PM PDT 24 |
| Finished | May 09 01:17:01 PM PDT 24 |
| Peak memory | 204808 kb |
| Host | smart-2ffad5bc-3d3d-4a11-8754-6b46751d3cf8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512750372 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_c sr_outstanding.512750372 |
| Directory | /workspace/7.rv_dm_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.4233267025 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 18185380755 ps |
| CPU time | 10.83 seconds |
| Started | May 09 01:16:52 PM PDT 24 |
| Finished | May 09 01:17:07 PM PDT 24 |
| Peak memory | 214772 kb |
| Host | smart-bb39ca28-a3e7-4239-ad5d-2d1f2252fd44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233267025 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.4233267025 |
| Directory | /workspace/7.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.1170069010 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 160697185 ps |
| CPU time | 2.93 seconds |
| Started | May 09 01:16:55 PM PDT 24 |
| Finished | May 09 01:17:02 PM PDT 24 |
| Peak memory | 213284 kb |
| Host | smart-9e60c860-7d59-49b3-afd1-2d1534955281 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170069010 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.1170069010 |
| Directory | /workspace/7.rv_dm_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2214330617 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 1341605739 ps |
| CPU time | 9.69 seconds |
| Started | May 09 01:16:52 PM PDT 24 |
| Finished | May 09 01:17:04 PM PDT 24 |
| Peak memory | 213188 kb |
| Host | smart-f69b79fa-3b64-4462-983e-f65393e8d3c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214330617 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.2214330617 |
| Directory | /workspace/7.rv_dm_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2971986203 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 64584952 ps |
| CPU time | 2.18 seconds |
| Started | May 09 01:16:47 PM PDT 24 |
| Finished | May 09 01:16:51 PM PDT 24 |
| Peak memory | 218088 kb |
| Host | smart-41a5b631-5ed0-498e-b1fc-30b73644aa9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971986203 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.2971986203 |
| Directory | /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.3873016882 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 320808650 ps |
| CPU time | 2.28 seconds |
| Started | May 09 01:16:52 PM PDT 24 |
| Finished | May 09 01:16:56 PM PDT 24 |
| Peak memory | 221164 kb |
| Host | smart-0fca1934-6493-4158-a310-0de295f7f1cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873016882 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.3873016882 |
| Directory | /workspace/8.rv_dm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1645807018 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 213210001 ps |
| CPU time | 1.16 seconds |
| Started | May 09 01:16:54 PM PDT 24 |
| Finished | May 09 01:16:59 PM PDT 24 |
| Peak memory | 204888 kb |
| Host | smart-dc3079dc-fcf3-4a98-b4d0-2621cb4c3235 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645807018 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.1 645807018 |
| Directory | /workspace/8.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3934702739 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 96538548 ps |
| CPU time | 0.83 seconds |
| Started | May 09 01:16:47 PM PDT 24 |
| Finished | May 09 01:16:49 PM PDT 24 |
| Peak memory | 204604 kb |
| Host | smart-f7b66764-c37e-45df-8901-6a9dcce913f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934702739 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.3 934702739 |
| Directory | /workspace/8.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2814960476 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 275057372 ps |
| CPU time | 4.07 seconds |
| Started | May 09 01:16:48 PM PDT 24 |
| Finished | May 09 01:16:53 PM PDT 24 |
| Peak memory | 204976 kb |
| Host | smart-71c1fcc2-8ff4-46b3-88a4-e52d6161f50c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814960476 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_ csr_outstanding.2814960476 |
| Directory | /workspace/8.rv_dm_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.4199708089 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 12304557891 ps |
| CPU time | 12.44 seconds |
| Started | May 09 01:16:53 PM PDT 24 |
| Finished | May 09 01:17:09 PM PDT 24 |
| Peak memory | 218200 kb |
| Host | smart-9560749a-30d5-42e1-b43f-fcea12e1106b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199708089 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.4199708089 |
| Directory | /workspace/8.rv_dm_tap_fsm_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.1275941110 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 612333037 ps |
| CPU time | 10.08 seconds |
| Started | May 09 01:16:48 PM PDT 24 |
| Finished | May 09 01:16:59 PM PDT 24 |
| Peak memory | 213156 kb |
| Host | smart-97abaac6-c22a-48cf-9072-cce0bdaf0a46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275941110 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.1275941110 |
| Directory | /workspace/8.rv_dm_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.921908387 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 164161520 ps |
| CPU time | 2.28 seconds |
| Started | May 09 01:16:54 PM PDT 24 |
| Finished | May 09 01:17:00 PM PDT 24 |
| Peak memory | 216864 kb |
| Host | smart-09b5facf-e085-433f-926d-40221404801c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921908387 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.921908387 |
| Directory | /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.4290224655 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 293892459 ps |
| CPU time | 1.74 seconds |
| Started | May 09 01:16:48 PM PDT 24 |
| Finished | May 09 01:16:51 PM PDT 24 |
| Peak memory | 204656 kb |
| Host | smart-62e6fa03-f170-4275-951c-a285295459c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290224655 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.4 290224655 |
| Directory | /workspace/9.rv_dm_jtag_dmi_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.3590055090 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 165994713 ps |
| CPU time | 0.77 seconds |
| Started | May 09 01:16:52 PM PDT 24 |
| Finished | May 09 01:16:56 PM PDT 24 |
| Peak memory | 204568 kb |
| Host | smart-f9991617-2aef-4208-a7f9-4018cb39b117 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590055090 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.3 590055090 |
| Directory | /workspace/9.rv_dm_jtag_dtm_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.100371707 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 1153426819 ps |
| CPU time | 4.2 seconds |
| Started | May 09 01:16:48 PM PDT 24 |
| Finished | May 09 01:16:53 PM PDT 24 |
| Peak memory | 204964 kb |
| Host | smart-6b8c7a98-6de3-453b-9f8d-137b2f16c1d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100371707 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_c sr_outstanding.100371707 |
| Directory | /workspace/9.rv_dm_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.2864439863 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 167505314 ps |
| CPU time | 5.97 seconds |
| Started | May 09 01:16:43 PM PDT 24 |
| Finished | May 09 01:16:51 PM PDT 24 |
| Peak memory | 213264 kb |
| Host | smart-11e1f01f-90e8-4db7-96e6-72a456974375 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864439863 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.2864439863 |
| Directory | /workspace/9.rv_dm_tl_errors/latest |
| Test location | /workspace/coverage/default/0.rv_dm_cmderr_busy.2807731516 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 2322078021 ps |
| CPU time | 4.83 seconds |
| Started | May 09 01:17:07 PM PDT 24 |
| Finished | May 09 01:17:14 PM PDT 24 |
| Peak memory | 205424 kb |
| Host | smart-d1ed3edb-167c-41f2-860b-294863bd6f42 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2807731516 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.2807731516 |
| Directory | /workspace/0.rv_dm_cmderr_busy/latest |
| Test location | /workspace/coverage/default/0.rv_dm_cmderr_exception.3188570443 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 336611660 ps |
| CPU time | 1.25 seconds |
| Started | May 09 01:17:11 PM PDT 24 |
| Finished | May 09 01:17:15 PM PDT 24 |
| Peak memory | 205148 kb |
| Host | smart-d9bc0ffc-a49b-4c40-9235-6ff064969cae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3188570443 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.3188570443 |
| Directory | /workspace/0.rv_dm_cmderr_exception/latest |
| Test location | /workspace/coverage/default/0.rv_dm_cmderr_not_supported.1975851001 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 957971223 ps |
| CPU time | 2.32 seconds |
| Started | May 09 01:17:05 PM PDT 24 |
| Finished | May 09 01:17:09 PM PDT 24 |
| Peak memory | 205364 kb |
| Host | smart-4cdcf512-ba3a-4160-8c9f-0cd69bbfc207 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1975851001 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.1975851001 |
| Directory | /workspace/0.rv_dm_cmderr_not_supported/latest |
| Test location | /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.4040197896 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 123572242 ps |
| CPU time | 0.79 seconds |
| Started | May 09 01:17:08 PM PDT 24 |
| Finished | May 09 01:17:13 PM PDT 24 |
| Peak memory | 205180 kb |
| Host | smart-8ab644e5-1b5b-46bf-b5c3-d968600e390c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4040197896 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.4040197896 |
| Directory | /workspace/0.rv_dm_dataaddr_rw_access/latest |
| Test location | /workspace/coverage/default/0.rv_dm_hart_unavail.2765924624 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 33842171 ps |
| CPU time | 0.72 seconds |
| Started | May 09 01:17:14 PM PDT 24 |
| Finished | May 09 01:17:16 PM PDT 24 |
| Peak memory | 204972 kb |
| Host | smart-800cc0be-960d-4134-8bf2-7453efe8f2ef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2765924624 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.2765924624 |
| Directory | /workspace/0.rv_dm_hart_unavail/latest |
| Test location | /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.1146664494 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 144067003 ps |
| CPU time | 0.89 seconds |
| Started | May 09 01:17:07 PM PDT 24 |
| Finished | May 09 01:17:11 PM PDT 24 |
| Peak memory | 205008 kb |
| Host | smart-6ed794b5-5525-47a7-bbae-e2b6d4bc1433 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1146664494 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.1146664494 |
| Directory | /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest |
| Test location | /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.2820832568 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 292030371 ps |
| CPU time | 1.34 seconds |
| Started | May 09 01:17:08 PM PDT 24 |
| Finished | May 09 01:17:13 PM PDT 24 |
| Peak memory | 205236 kb |
| Host | smart-dad1a243-6433-40f6-aedb-475b248b814e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2820832568 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.2820832568 |
| Directory | /workspace/0.rv_dm_jtag_dtm_hard_reset/latest |
| Test location | /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.3557594446 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 161664309 ps |
| CPU time | 0.86 seconds |
| Started | May 09 01:17:11 PM PDT 24 |
| Finished | May 09 01:17:14 PM PDT 24 |
| Peak memory | 205144 kb |
| Host | smart-6558ff4c-3893-4c58-a9f1-807b7c5411fb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3557594446 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.3557594446 |
| Directory | /workspace/0.rv_dm_mem_tl_access_halted/latest |
| Test location | /workspace/coverage/default/0.rv_dm_ndmreset_req.1819245882 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 774173738 ps |
| CPU time | 3.23 seconds |
| Started | May 09 01:17:06 PM PDT 24 |
| Finished | May 09 01:17:12 PM PDT 24 |
| Peak memory | 205384 kb |
| Host | smart-a068af2e-cebd-4c82-9c05-839a8cbe398f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1819245882 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.1819245882 |
| Directory | /workspace/0.rv_dm_ndmreset_req/latest |
| Test location | /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.1930345172 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 64951231 ps |
| CPU time | 0.9 seconds |
| Started | May 09 01:17:06 PM PDT 24 |
| Finished | May 09 01:17:09 PM PDT 24 |
| Peak memory | 205192 kb |
| Host | smart-033a6942-0756-4705-9a0c-c6af7ca8ca75 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1930345172 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.1930345172 |
| Directory | /workspace/0.rv_dm_progbuf_read_write_execute/latest |
| Test location | /workspace/coverage/default/0.rv_dm_rom_read_access.2806239141 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 177889954 ps |
| CPU time | 0.81 seconds |
| Started | May 09 01:17:08 PM PDT 24 |
| Finished | May 09 01:17:12 PM PDT 24 |
| Peak memory | 213368 kb |
| Host | smart-31a0e0f1-8883-4d1f-a664-f5519bf347b1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2806239141 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.2806239141 |
| Directory | /workspace/0.rv_dm_rom_read_access/latest |
| Test location | /workspace/coverage/default/0.rv_dm_sec_cm.1509450073 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 250915879 ps |
| CPU time | 1 seconds |
| Started | May 09 01:17:08 PM PDT 24 |
| Finished | May 09 01:17:13 PM PDT 24 |
| Peak memory | 229512 kb |
| Host | smart-a2b572a3-d4af-46be-9554-170aefc37ba5 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509450073 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.1509450073 |
| Directory | /workspace/0.rv_dm_sec_cm/latest |
| Test location | /workspace/coverage/default/0.rv_dm_smoke.3646622815 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 274193948 ps |
| CPU time | 1.22 seconds |
| Started | May 09 01:16:52 PM PDT 24 |
| Finished | May 09 01:16:56 PM PDT 24 |
| Peak memory | 205052 kb |
| Host | smart-e0647770-9862-4008-a1b0-00bdc9aeec82 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3646622815 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.3646622815 |
| Directory | /workspace/0.rv_dm_smoke/latest |
| Test location | /workspace/coverage/default/0.rv_dm_tap_fsm.962899045 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 2498061649 ps |
| CPU time | 5.31 seconds |
| Started | May 09 01:16:55 PM PDT 24 |
| Finished | May 09 01:17:05 PM PDT 24 |
| Peak memory | 205476 kb |
| Host | smart-3b01dc6e-373f-4a0e-98fa-d139e0a3e08b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=962899045 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.962899045 |
| Directory | /workspace/0.rv_dm_tap_fsm/latest |
| Test location | /workspace/coverage/default/1.rv_dm_abstractcmd_status.149704128 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 27389954 ps |
| CPU time | 0.76 seconds |
| Started | May 09 01:17:07 PM PDT 24 |
| Finished | May 09 01:17:10 PM PDT 24 |
| Peak memory | 205188 kb |
| Host | smart-b6695049-69f8-4ed5-a516-a5fb9056ef66 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=149704128 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.149704128 |
| Directory | /workspace/1.rv_dm_abstractcmd_status/latest |
| Test location | /workspace/coverage/default/1.rv_dm_alert_test.3602269173 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 24010296 ps |
| CPU time | 0.75 seconds |
| Started | May 09 01:17:08 PM PDT 24 |
| Finished | May 09 01:17:12 PM PDT 24 |
| Peak memory | 205088 kb |
| Host | smart-f498957d-30b3-4ce8-8fbb-49ace93561fc |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602269173 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.3602269173 |
| Directory | /workspace/1.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/1.rv_dm_cmderr_busy.2021943085 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4878793625 ps |
| CPU time | 16.58 seconds |
| Started | May 09 01:17:06 PM PDT 24 |
| Finished | May 09 01:17:24 PM PDT 24 |
| Peak memory | 205512 kb |
| Host | smart-327d7b24-c207-4b97-88dc-badc08a9a206 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2021943085 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.2021943085 |
| Directory | /workspace/1.rv_dm_cmderr_busy/latest |
| Test location | /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.2313095744 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 262723548 ps |
| CPU time | 1.47 seconds |
| Started | May 09 01:17:08 PM PDT 24 |
| Finished | May 09 01:17:13 PM PDT 24 |
| Peak memory | 205056 kb |
| Host | smart-372deb3f-d56d-406b-bce3-c4f57e7cfa55 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2313095744 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.2313095744 |
| Directory | /workspace/1.rv_dm_cmderr_halt_resume/latest |
| Test location | /workspace/coverage/default/1.rv_dm_cmderr_not_supported.2973915451 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 724898798 ps |
| CPU time | 3.13 seconds |
| Started | May 09 01:17:09 PM PDT 24 |
| Finished | May 09 01:17:16 PM PDT 24 |
| Peak memory | 205284 kb |
| Host | smart-e36b20c4-4d67-42dc-8186-73e789b15449 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2973915451 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.2973915451 |
| Directory | /workspace/1.rv_dm_cmderr_not_supported/latest |
| Test location | /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.4018774628 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 83490246 ps |
| CPU time | 0.87 seconds |
| Started | May 09 01:17:04 PM PDT 24 |
| Finished | May 09 01:17:07 PM PDT 24 |
| Peak memory | 205132 kb |
| Host | smart-15d595ec-3e0e-4a79-86de-a73e2ba45200 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4018774628 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.4018774628 |
| Directory | /workspace/1.rv_dm_dataaddr_rw_access/latest |
| Test location | /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.1792047985 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 79354667 ps |
| CPU time | 0.93 seconds |
| Started | May 09 01:17:13 PM PDT 24 |
| Finished | May 09 01:17:15 PM PDT 24 |
| Peak memory | 204988 kb |
| Host | smart-a7b786c3-b766-4ae2-a4bb-a4720bb2bb8d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1792047985 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.1792047985 |
| Directory | /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest |
| Test location | /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.805750039 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 246516754 ps |
| CPU time | 1.38 seconds |
| Started | May 09 01:17:11 PM PDT 24 |
| Finished | May 09 01:17:15 PM PDT 24 |
| Peak memory | 205044 kb |
| Host | smart-0ee484b2-3a89-4203-b393-48b9c6dd2fed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=805750039 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.805750039 |
| Directory | /workspace/1.rv_dm_jtag_dtm_hard_reset/latest |
| Test location | /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.1859469135 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 314587977 ps |
| CPU time | 0.88 seconds |
| Started | May 09 01:17:07 PM PDT 24 |
| Finished | May 09 01:17:11 PM PDT 24 |
| Peak memory | 205192 kb |
| Host | smart-be1349cd-dc52-4175-9baf-6b307b56e6ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1859469135 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.1859469135 |
| Directory | /workspace/1.rv_dm_mem_tl_access_halted/latest |
| Test location | /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.2986543650 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 401174148 ps |
| CPU time | 1.98 seconds |
| Started | May 09 01:17:07 PM PDT 24 |
| Finished | May 09 01:17:12 PM PDT 24 |
| Peak memory | 205380 kb |
| Host | smart-58ec6a0f-cb42-41fe-b176-638451af24c5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2986543650 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.2986543650 |
| Directory | /workspace/1.rv_dm_mem_tl_access_resuming/latest |
| Test location | /workspace/coverage/default/1.rv_dm_ndmreset_req.96334315 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 1098904330 ps |
| CPU time | 2.44 seconds |
| Started | May 09 01:17:12 PM PDT 24 |
| Finished | May 09 01:17:16 PM PDT 24 |
| Peak memory | 205304 kb |
| Host | smart-5d3eb17f-4440-4ae4-8de1-637c429c52d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=96334315 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.96334315 |
| Directory | /workspace/1.rv_dm_ndmreset_req/latest |
| Test location | /workspace/coverage/default/1.rv_dm_progbuf_busy.2286455300 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 418533580 ps |
| CPU time | 1.53 seconds |
| Started | May 09 01:17:11 PM PDT 24 |
| Finished | May 09 01:17:15 PM PDT 24 |
| Peak memory | 205396 kb |
| Host | smart-a79ca23c-b4a8-499a-9ce2-23a04985257d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2286455300 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.2286455300 |
| Directory | /workspace/1.rv_dm_progbuf_busy/latest |
| Test location | /workspace/coverage/default/1.rv_dm_smoke.2565605437 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 478148921 ps |
| CPU time | 1.45 seconds |
| Started | May 09 01:17:07 PM PDT 24 |
| Finished | May 09 01:17:12 PM PDT 24 |
| Peak memory | 205316 kb |
| Host | smart-b2581e0f-5b19-4e46-b27d-3025aac85dea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2565605437 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.2565605437 |
| Directory | /workspace/1.rv_dm_smoke/latest |
| Test location | /workspace/coverage/default/10.rv_dm_alert_test.3828974073 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 72749278 ps |
| CPU time | 0.7 seconds |
| Started | May 09 01:17:22 PM PDT 24 |
| Finished | May 09 01:17:25 PM PDT 24 |
| Peak memory | 205144 kb |
| Host | smart-71b091ea-faae-4145-b6b3-9c055c13a54b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828974073 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.3828974073 |
| Directory | /workspace/10.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/11.rv_dm_alert_test.1081230653 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 33790245 ps |
| CPU time | 0.74 seconds |
| Started | May 09 01:17:23 PM PDT 24 |
| Finished | May 09 01:17:25 PM PDT 24 |
| Peak memory | 205096 kb |
| Host | smart-1649174a-f8b0-41e4-807b-582d433f3837 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081230653 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.1081230653 |
| Directory | /workspace/11.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/12.rv_dm_alert_test.1066438831 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 245753695 ps |
| CPU time | 0.72 seconds |
| Started | May 09 01:27:30 PM PDT 24 |
| Finished | May 09 01:27:32 PM PDT 24 |
| Peak memory | 205160 kb |
| Host | smart-18a62685-dafd-45ca-8066-dd5fa1e14388 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066438831 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.1066438831 |
| Directory | /workspace/12.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/13.rv_dm_alert_test.904245017 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 38439716 ps |
| CPU time | 0.69 seconds |
| Started | May 09 01:27:45 PM PDT 24 |
| Finished | May 09 01:27:47 PM PDT 24 |
| Peak memory | 205180 kb |
| Host | smart-055a49ed-b743-4626-9b2a-d4ee696624ab |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904245017 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.904245017 |
| Directory | /workspace/13.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/14.rv_dm_alert_test.2484374092 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 174614755 ps |
| CPU time | 0.77 seconds |
| Started | May 09 01:27:46 PM PDT 24 |
| Finished | May 09 01:27:47 PM PDT 24 |
| Peak memory | 205152 kb |
| Host | smart-fafa27d5-1e27-4a37-b98a-f4c1c6d8b594 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484374092 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.2484374092 |
| Directory | /workspace/14.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.4135823516 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 2291128429 ps |
| CPU time | 3.48 seconds |
| Started | May 09 01:27:48 PM PDT 24 |
| Finished | May 09 01:27:52 PM PDT 24 |
| Peak memory | 205616 kb |
| Host | smart-6b336e50-1549-4f7e-9028-f7ab9efb1b37 |
| User | root |
| Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4135823516 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_ tl_access.4135823516 |
| Directory | /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest |
| Test location | /workspace/coverage/default/15.rv_dm_alert_test.2827941102 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 21782595 ps |
| CPU time | 0.74 seconds |
| Started | May 09 01:27:58 PM PDT 24 |
| Finished | May 09 01:28:00 PM PDT 24 |
| Peak memory | 205156 kb |
| Host | smart-3ee447f6-1109-4ced-a423-6d99bd2a50ee |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827941102 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.2827941102 |
| Directory | /workspace/15.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/16.rv_dm_alert_test.1057620937 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 28394491 ps |
| CPU time | 0.78 seconds |
| Started | May 09 01:27:59 PM PDT 24 |
| Finished | May 09 01:28:00 PM PDT 24 |
| Peak memory | 205088 kb |
| Host | smart-0b8f527d-62e2-4ae4-bb53-f87f76f30c22 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057620937 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.1057620937 |
| Directory | /workspace/16.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/17.rv_dm_alert_test.1655304831 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 30961958 ps |
| CPU time | 0.73 seconds |
| Started | May 09 01:28:37 PM PDT 24 |
| Finished | May 09 01:28:39 PM PDT 24 |
| Peak memory | 205164 kb |
| Host | smart-be4efcb9-bb3a-442c-8b43-298ec6e3eed1 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655304831 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.1655304831 |
| Directory | /workspace/17.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/18.rv_dm_alert_test.3562567244 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 18614190 ps |
| CPU time | 0.74 seconds |
| Started | May 09 01:28:37 PM PDT 24 |
| Finished | May 09 01:28:38 PM PDT 24 |
| Peak memory | 205156 kb |
| Host | smart-02e29f75-5d4e-413e-851a-183adb2c05e0 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562567244 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.3562567244 |
| Directory | /workspace/18.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/18.rv_dm_sba_tl_access.1601258692 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 1890286846 ps |
| CPU time | 2.55 seconds |
| Started | May 09 01:28:42 PM PDT 24 |
| Finished | May 09 01:28:46 PM PDT 24 |
| Peak memory | 205540 kb |
| Host | smart-f455ba49-d150-46d7-8806-7586580ec0de |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1601258692 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.1601258692 |
| Directory | /workspace/18.rv_dm_sba_tl_access/latest |
| Test location | /workspace/coverage/default/19.rv_dm_alert_test.823597696 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 42073829 ps |
| CPU time | 0.76 seconds |
| Started | May 09 01:28:49 PM PDT 24 |
| Finished | May 09 01:28:51 PM PDT 24 |
| Peak memory | 205140 kb |
| Host | smart-c9075cfb-3d6f-4dd3-a43b-ed7af2100001 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823597696 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.823597696 |
| Directory | /workspace/19.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/2.rv_dm_alert_test.2551274142 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 27333335 ps |
| CPU time | 0.71 seconds |
| Started | May 09 01:17:22 PM PDT 24 |
| Finished | May 09 01:17:24 PM PDT 24 |
| Peak memory | 205132 kb |
| Host | smart-d96527b7-a29c-4d6c-a6ca-74ce2e3bbcba |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551274142 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.2551274142 |
| Directory | /workspace/2.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/2.rv_dm_hart_unavail.2815690020 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 212880039 ps |
| CPU time | 0.83 seconds |
| Started | May 09 01:17:09 PM PDT 24 |
| Finished | May 09 01:17:13 PM PDT 24 |
| Peak memory | 205060 kb |
| Host | smart-5269c2a5-00a4-444c-96cc-a04f766af641 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2815690020 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.2815690020 |
| Directory | /workspace/2.rv_dm_hart_unavail/latest |
| Test location | /workspace/coverage/default/2.rv_dm_sec_cm.3493759413 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 282918018 ps |
| CPU time | 1.57 seconds |
| Started | May 09 01:17:17 PM PDT 24 |
| Finished | May 09 01:17:21 PM PDT 24 |
| Peak memory | 229492 kb |
| Host | smart-4b63e4ce-9aaa-4361-8504-9daa7faefc87 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493759413 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.3493759413 |
| Directory | /workspace/2.rv_dm_sec_cm/latest |
| Test location | /workspace/coverage/default/20.rv_dm_alert_test.2987408707 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 18822907 ps |
| CPU time | 0.75 seconds |
| Started | May 09 01:28:49 PM PDT 24 |
| Finished | May 09 01:28:51 PM PDT 24 |
| Peak memory | 205144 kb |
| Host | smart-20bfe626-3b3d-422b-96f6-df04b45801de |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987408707 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.2987408707 |
| Directory | /workspace/20.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/21.rv_dm_alert_test.1079083419 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 20231884 ps |
| CPU time | 0.73 seconds |
| Started | May 09 01:28:49 PM PDT 24 |
| Finished | May 09 01:28:51 PM PDT 24 |
| Peak memory | 205144 kb |
| Host | smart-296cf561-110a-434c-a832-c28517a1f779 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079083419 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.1079083419 |
| Directory | /workspace/21.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/22.rv_dm_alert_test.4257860931 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 30729035 ps |
| CPU time | 0.72 seconds |
| Started | May 09 01:28:45 PM PDT 24 |
| Finished | May 09 01:28:47 PM PDT 24 |
| Peak memory | 205172 kb |
| Host | smart-49d9f636-23df-4d6c-9e3b-421c3526b877 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257860931 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.4257860931 |
| Directory | /workspace/22.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/23.rv_dm_alert_test.2533744911 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 49699003 ps |
| CPU time | 0.71 seconds |
| Started | May 09 01:28:52 PM PDT 24 |
| Finished | May 09 01:28:54 PM PDT 24 |
| Peak memory | 205184 kb |
| Host | smart-c1478065-cb41-4d80-a004-8619205997a6 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533744911 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.2533744911 |
| Directory | /workspace/23.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/24.rv_dm_alert_test.1371437427 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 20348855 ps |
| CPU time | 0.8 seconds |
| Started | May 09 01:28:52 PM PDT 24 |
| Finished | May 09 01:28:54 PM PDT 24 |
| Peak memory | 205204 kb |
| Host | smart-408071aa-0118-43b9-86d0-5e98e721ff45 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371437427 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.1371437427 |
| Directory | /workspace/24.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/25.rv_dm_alert_test.3892948136 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 26123384 ps |
| CPU time | 0.71 seconds |
| Started | May 09 01:28:50 PM PDT 24 |
| Finished | May 09 01:28:52 PM PDT 24 |
| Peak memory | 205156 kb |
| Host | smart-129ab079-7a79-47fd-b140-01e3661f1809 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892948136 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.3892948136 |
| Directory | /workspace/25.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/26.rv_dm_alert_test.428558994 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 30893564 ps |
| CPU time | 0.69 seconds |
| Started | May 09 01:28:58 PM PDT 24 |
| Finished | May 09 01:29:00 PM PDT 24 |
| Peak memory | 205176 kb |
| Host | smart-cd737b27-542c-4944-94c8-9cb77f7d6f31 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428558994 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.428558994 |
| Directory | /workspace/26.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/27.rv_dm_alert_test.3000788615 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 39059081 ps |
| CPU time | 0.77 seconds |
| Started | May 09 01:29:08 PM PDT 24 |
| Finished | May 09 01:29:11 PM PDT 24 |
| Peak memory | 205068 kb |
| Host | smart-fb6094e9-3def-4461-b469-3bab5d34de8b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000788615 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.3000788615 |
| Directory | /workspace/27.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/28.rv_dm_alert_test.2922880195 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 109138708 ps |
| CPU time | 0.72 seconds |
| Started | May 09 01:29:08 PM PDT 24 |
| Finished | May 09 01:29:10 PM PDT 24 |
| Peak memory | 205192 kb |
| Host | smart-2b54266e-ff61-4de2-8861-72d26a23a823 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922880195 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.2922880195 |
| Directory | /workspace/28.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/29.rv_dm_alert_test.4082157186 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 22582745 ps |
| CPU time | 0.71 seconds |
| Started | May 09 01:29:07 PM PDT 24 |
| Finished | May 09 01:29:10 PM PDT 24 |
| Peak memory | 205192 kb |
| Host | smart-73b7bbb5-259a-40d2-81ae-6ac7a19eb133 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082157186 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.4082157186 |
| Directory | /workspace/29.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/3.rv_dm_alert_test.2236790464 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 25876208 ps |
| CPU time | 0.74 seconds |
| Started | May 09 01:17:19 PM PDT 24 |
| Finished | May 09 01:17:21 PM PDT 24 |
| Peak memory | 205184 kb |
| Host | smart-89de3dd8-8cdc-457a-beb1-f5b49f5bce5f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236790464 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.2236790464 |
| Directory | /workspace/3.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/3.rv_dm_hart_unavail.3772909095 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 24362476 ps |
| CPU time | 0.7 seconds |
| Started | May 09 01:17:24 PM PDT 24 |
| Finished | May 09 01:17:26 PM PDT 24 |
| Peak memory | 205000 kb |
| Host | smart-14a97e8c-2f86-40b0-a3bb-029e27feb1a4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3772909095 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.3772909095 |
| Directory | /workspace/3.rv_dm_hart_unavail/latest |
| Test location | /workspace/coverage/default/3.rv_dm_sec_cm.1623764682 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 162278475 ps |
| CPU time | 1.43 seconds |
| Started | May 09 01:17:16 PM PDT 24 |
| Finished | May 09 01:17:18 PM PDT 24 |
| Peak memory | 229384 kb |
| Host | smart-1abd0f10-94e7-4467-ae35-9ab50beb4a34 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623764682 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.1623764682 |
| Directory | /workspace/3.rv_dm_sec_cm/latest |
| Test location | /workspace/coverage/default/30.rv_dm_alert_test.3542334839 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 27347284 ps |
| CPU time | 0.69 seconds |
| Started | May 09 01:29:02 PM PDT 24 |
| Finished | May 09 01:29:03 PM PDT 24 |
| Peak memory | 205188 kb |
| Host | smart-757b7aa6-aac3-4d10-9ad3-7ebe0cdc402b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542334839 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.3542334839 |
| Directory | /workspace/30.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/31.rv_dm_alert_test.2070043238 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 195946985 ps |
| CPU time | 0.74 seconds |
| Started | May 09 01:29:02 PM PDT 24 |
| Finished | May 09 01:29:03 PM PDT 24 |
| Peak memory | 205120 kb |
| Host | smart-de7bd5c5-394f-4082-b3e0-df492084ee7a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070043238 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.2070043238 |
| Directory | /workspace/31.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/32.rv_dm_alert_test.1401646653 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 37943492 ps |
| CPU time | 0.7 seconds |
| Started | May 09 01:29:02 PM PDT 24 |
| Finished | May 09 01:29:03 PM PDT 24 |
| Peak memory | 205152 kb |
| Host | smart-11a94920-8098-40a8-a7cd-e07d46653b28 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401646653 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.1401646653 |
| Directory | /workspace/32.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/33.rv_dm_alert_test.1862744055 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 20100533 ps |
| CPU time | 0.68 seconds |
| Started | May 09 01:29:07 PM PDT 24 |
| Finished | May 09 01:29:09 PM PDT 24 |
| Peak memory | 205192 kb |
| Host | smart-69ecdcb9-9c0c-4d6f-a9a7-26baa5971089 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862744055 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.1862744055 |
| Directory | /workspace/33.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/34.rv_dm_alert_test.2593046523 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 18668132 ps |
| CPU time | 0.68 seconds |
| Started | May 09 01:29:05 PM PDT 24 |
| Finished | May 09 01:29:07 PM PDT 24 |
| Peak memory | 205108 kb |
| Host | smart-a41bebe4-0453-4e10-9263-f0bff88d61ba |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593046523 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.2593046523 |
| Directory | /workspace/34.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/35.rv_dm_alert_test.2749999117 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 18948509 ps |
| CPU time | 0.72 seconds |
| Started | May 09 01:29:03 PM PDT 24 |
| Finished | May 09 01:29:05 PM PDT 24 |
| Peak memory | 205188 kb |
| Host | smart-2dc44a47-4335-4935-9d37-a532864a0f4b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749999117 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.2749999117 |
| Directory | /workspace/35.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/37.rv_dm_alert_test.1641235743 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 24425725 ps |
| CPU time | 0.78 seconds |
| Started | May 09 01:29:08 PM PDT 24 |
| Finished | May 09 01:29:11 PM PDT 24 |
| Peak memory | 205084 kb |
| Host | smart-45f2b7b7-9698-4d03-874e-6bb3e0a2230f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641235743 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.1641235743 |
| Directory | /workspace/37.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/37.rv_dm_stress_all.545981636 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 2862160142 ps |
| CPU time | 1.42 seconds |
| Started | May 09 01:29:07 PM PDT 24 |
| Finished | May 09 01:29:10 PM PDT 24 |
| Peak memory | 205504 kb |
| Host | smart-a2ef9c94-fdbc-4438-a64a-a6a18c03fbe7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545981636 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.545981636 |
| Directory | /workspace/37.rv_dm_stress_all/latest |
| Test location | /workspace/coverage/default/38.rv_dm_alert_test.188771244 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 95208770 ps |
| CPU time | 0.76 seconds |
| Started | May 09 01:29:18 PM PDT 24 |
| Finished | May 09 01:29:20 PM PDT 24 |
| Peak memory | 205136 kb |
| Host | smart-9c931313-46b2-4e4e-a8ea-fc743bcbcffe |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188771244 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.188771244 |
| Directory | /workspace/38.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/39.rv_dm_alert_test.3583135446 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 31531252 ps |
| CPU time | 0.77 seconds |
| Started | May 09 01:29:21 PM PDT 24 |
| Finished | May 09 01:29:24 PM PDT 24 |
| Peak memory | 205120 kb |
| Host | smart-8a808f2e-0f63-48d8-ae3e-0935f2d6401c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583135446 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.3583135446 |
| Directory | /workspace/39.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/4.rv_dm_alert_test.348272568 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 63238426 ps |
| CPU time | 0.75 seconds |
| Started | May 09 01:17:27 PM PDT 24 |
| Finished | May 09 01:17:29 PM PDT 24 |
| Peak memory | 205068 kb |
| Host | smart-3eab671c-67be-44e0-a565-8f788f918fd9 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348272568 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.348272568 |
| Directory | /workspace/4.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/4.rv_dm_hart_unavail.1064409066 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 49412958 ps |
| CPU time | 0.7 seconds |
| Started | May 09 01:17:19 PM PDT 24 |
| Finished | May 09 01:17:21 PM PDT 24 |
| Peak memory | 204992 kb |
| Host | smart-cf6de43c-a700-446d-b1e2-9af56d4c2b6d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1064409066 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.1064409066 |
| Directory | /workspace/4.rv_dm_hart_unavail/latest |
| Test location | /workspace/coverage/default/4.rv_dm_sba_tl_access.10958446 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 955710825 ps |
| CPU time | 1.53 seconds |
| Started | May 09 01:17:20 PM PDT 24 |
| Finished | May 09 01:17:23 PM PDT 24 |
| Peak memory | 205436 kb |
| Host | smart-7f283f65-0aad-4584-a970-cf073bc1c5bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=10958446 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.10958446 |
| Directory | /workspace/4.rv_dm_sba_tl_access/latest |
| Test location | /workspace/coverage/default/4.rv_dm_sec_cm.3944804582 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 610364214 ps |
| CPU time | 1.3 seconds |
| Started | May 09 01:17:16 PM PDT 24 |
| Finished | May 09 01:17:19 PM PDT 24 |
| Peak memory | 229380 kb |
| Host | smart-9b043956-f7d3-4d97-bcb6-ff2839faef29 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944804582 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.3944804582 |
| Directory | /workspace/4.rv_dm_sec_cm/latest |
| Test location | /workspace/coverage/default/40.rv_dm_alert_test.1626189865 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 29426679 ps |
| CPU time | 0.75 seconds |
| Started | May 09 01:29:13 PM PDT 24 |
| Finished | May 09 01:29:14 PM PDT 24 |
| Peak memory | 205188 kb |
| Host | smart-f8c3a3f4-dcdd-47e3-a846-f80084893a3f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626189865 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.1626189865 |
| Directory | /workspace/40.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/41.rv_dm_alert_test.1159833423 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 18101606 ps |
| CPU time | 0.71 seconds |
| Started | May 09 01:29:31 PM PDT 24 |
| Finished | May 09 01:29:32 PM PDT 24 |
| Peak memory | 205196 kb |
| Host | smart-bed63278-80a8-433a-85c8-a23e2988323d |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159833423 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.1159833423 |
| Directory | /workspace/41.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/42.rv_dm_alert_test.2668859300 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 25903445 ps |
| CPU time | 0.73 seconds |
| Started | May 09 01:29:20 PM PDT 24 |
| Finished | May 09 01:29:22 PM PDT 24 |
| Peak memory | 205136 kb |
| Host | smart-691fb9f8-fa45-4f92-aff8-67b57d26e44e |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668859300 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.2668859300 |
| Directory | /workspace/42.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/43.rv_dm_alert_test.2476683857 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 22787484 ps |
| CPU time | 0.71 seconds |
| Started | May 09 01:29:20 PM PDT 24 |
| Finished | May 09 01:29:23 PM PDT 24 |
| Peak memory | 205120 kb |
| Host | smart-8f760df7-6a2d-45ec-b330-a14529615a75 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476683857 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.2476683857 |
| Directory | /workspace/43.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/44.rv_dm_alert_test.46743157 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 87938331 ps |
| CPU time | 0.7 seconds |
| Started | May 09 01:29:19 PM PDT 24 |
| Finished | May 09 01:29:20 PM PDT 24 |
| Peak memory | 205136 kb |
| Host | smart-ae916c4c-102f-4b42-b00d-ee45f6531cda |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46743157 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.46743157 |
| Directory | /workspace/44.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/45.rv_dm_alert_test.1908332089 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 41362637 ps |
| CPU time | 0.76 seconds |
| Started | May 09 01:29:13 PM PDT 24 |
| Finished | May 09 01:29:15 PM PDT 24 |
| Peak memory | 205188 kb |
| Host | smart-7a3accbc-ec05-4132-ad24-473e4011049e |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908332089 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.1908332089 |
| Directory | /workspace/45.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/46.rv_dm_alert_test.3671993756 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 49705366 ps |
| CPU time | 0.71 seconds |
| Started | May 09 01:29:20 PM PDT 24 |
| Finished | May 09 01:29:23 PM PDT 24 |
| Peak memory | 205120 kb |
| Host | smart-07823c18-63b0-4a3c-a553-8521eb0be839 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671993756 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.3671993756 |
| Directory | /workspace/46.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/47.rv_dm_alert_test.1637626207 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 40959921 ps |
| CPU time | 0.7 seconds |
| Started | May 09 01:29:20 PM PDT 24 |
| Finished | May 09 01:29:22 PM PDT 24 |
| Peak memory | 205192 kb |
| Host | smart-959d8d40-5fbb-4d2d-af06-ca7efbf37733 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637626207 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.1637626207 |
| Directory | /workspace/47.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/48.rv_dm_alert_test.2128944382 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 59941615 ps |
| CPU time | 0.69 seconds |
| Started | May 09 01:29:20 PM PDT 24 |
| Finished | May 09 01:29:23 PM PDT 24 |
| Peak memory | 205196 kb |
| Host | smart-1b7a223e-d799-4f8b-b5e5-9d8e377dca8c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128944382 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.2128944382 |
| Directory | /workspace/48.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/49.rv_dm_alert_test.4070103929 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 30877301 ps |
| CPU time | 0.71 seconds |
| Started | May 09 01:29:20 PM PDT 24 |
| Finished | May 09 01:29:22 PM PDT 24 |
| Peak memory | 205124 kb |
| Host | smart-1afcc120-0afe-4441-a0fd-ca4e95d3c2b0 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070103929 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.4070103929 |
| Directory | /workspace/49.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/5.rv_dm_alert_test.965000845 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 52784557 ps |
| CPU time | 0.72 seconds |
| Started | May 09 01:17:19 PM PDT 24 |
| Finished | May 09 01:17:21 PM PDT 24 |
| Peak memory | 205124 kb |
| Host | smart-4cca60d2-0373-4c11-8f49-1482d88bb314 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965000845 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.965000845 |
| Directory | /workspace/5.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/6.rv_dm_alert_test.618395498 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 47665280 ps |
| CPU time | 0.74 seconds |
| Started | May 09 01:17:20 PM PDT 24 |
| Finished | May 09 01:17:23 PM PDT 24 |
| Peak memory | 205132 kb |
| Host | smart-fa5a85e8-b2db-46f0-bdbb-37cfec5063ad |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618395498 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.618395498 |
| Directory | /workspace/6.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/7.rv_dm_alert_test.1110297063 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 30156473 ps |
| CPU time | 0.76 seconds |
| Started | May 09 01:17:18 PM PDT 24 |
| Finished | May 09 01:17:21 PM PDT 24 |
| Peak memory | 205080 kb |
| Host | smart-03da6ee9-1ad6-4619-b767-76b246988d5c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110297063 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.1110297063 |
| Directory | /workspace/7.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/8.rv_dm_alert_test.2103811452 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 31686898 ps |
| CPU time | 0.79 seconds |
| Started | May 09 01:17:20 PM PDT 24 |
| Finished | May 09 01:17:23 PM PDT 24 |
| Peak memory | 205144 kb |
| Host | smart-20658cb7-bd64-48e0-a0fe-f2de4e0222a5 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103811452 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.2103811452 |
| Directory | /workspace/8.rv_dm_alert_test/latest |
| Test location | /workspace/coverage/default/8.rv_dm_stress_all.233453162 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 3755647892 ps |
| CPU time | 11.6 seconds |
| Started | May 09 01:17:18 PM PDT 24 |
| Finished | May 09 01:17:31 PM PDT 24 |
| Peak memory | 205412 kb |
| Host | smart-eb3c8bed-ab9b-4a81-b436-907f8cdc5d45 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233453162 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.233453162 |
| Directory | /workspace/8.rv_dm_stress_all/latest |
| Test location | /workspace/coverage/default/9.rv_dm_alert_test.1687900077 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 90046611 ps |
| CPU time | 0.76 seconds |
| Started | May 09 01:17:20 PM PDT 24 |
| Finished | May 09 01:17:23 PM PDT 24 |
| Peak memory | 205136 kb |
| Host | smart-3e3b2f5c-11e5-4e16-937d-c6f02fb17c62 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687900077 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.1687900077 |
| Directory | /workspace/9.rv_dm_alert_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |