Unified Coverage Report :: Tests

Tests

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Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
74.82	90.63	76.24	85.73	60.26	77.17	98.42	35.31

Total test records in report: 269

tests.html | tests1.html | tests2.html | tests3.html | tests4.html

T253	/workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.2889786854			May 19 01:07:17 PM PDT 24	May 19 01:07:21 PM PDT 24	31003494 ps
T254	/workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2441583586			May 19 01:07:20 PM PDT 24	May 19 01:07:22 PM PDT 24	66921417 ps
T255	/workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.368418799			May 19 01:07:30 PM PDT 24	May 19 01:07:32 PM PDT 24	26692894 ps
T70	/workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.649777310			May 19 01:07:22 PM PDT 24	May 19 01:07:39 PM PDT 24	769007289 ps
T256	/workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.3640855055			May 19 01:07:08 PM PDT 24	May 19 01:07:47 PM PDT 24	13293156487 ps
T257	/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.780816682			May 19 01:07:15 PM PDT 24	May 19 01:07:18 PM PDT 24	92502460 ps
T258	/workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.1327839760			May 19 01:07:22 PM PDT 24	May 19 01:07:29 PM PDT 24	2999003285 ps
T58	/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.680922884			May 19 01:07:17 PM PDT 24	May 19 01:07:22 PM PDT 24	739132641 ps
T259	/workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.476273846			May 19 01:07:33 PM PDT 24	May 19 01:07:40 PM PDT 24	461975872 ps
T260	/workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.3483984888			May 19 01:07:34 PM PDT 24	May 19 01:07:53 PM PDT 24	935817493 ps
T261	/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2152182599			May 19 01:07:11 PM PDT 24	May 19 01:07:38 PM PDT 24	12126004065 ps
T262	/workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.923683378			May 19 01:07:23 PM PDT 24	May 19 01:07:30 PM PDT 24	763709751 ps
T263	/workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.2279688900			May 19 01:07:18 PM PDT 24	May 19 01:07:47 PM PDT 24	1515113780 ps
T264	/workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.2716280264			May 19 01:07:14 PM PDT 24	May 19 01:07:25 PM PDT 24	666165807 ps
T265	/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.566578528			May 19 01:07:06 PM PDT 24	May 19 01:07:10 PM PDT 24	453540836 ps
T266	/workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.800307656			May 19 01:07:15 PM PDT 24	May 19 01:07:18 PM PDT 24	15643802 ps
T267	/workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.862260386			May 19 01:07:34 PM PDT 24	May 19 01:07:41 PM PDT 24	249428171 ps
T268	/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.4129818596			May 19 01:07:18 PM PDT 24	May 19 01:08:33 PM PDT 24	17810295142 ps
T269	/workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.505761988			May 19 01:07:23 PM PDT 24	May 19 01:07:30 PM PDT 24	802795421 ps

Test location	/workspace/coverage/default/48.rv_dm_alert_test.4180336029
Short name	T1
Test name
Test status
Simulation time	30546090 ps
CPU time	0.78 seconds
Started	May 19 01:08:32 PM PDT 24
Finished	May 19 01:08:45 PM PDT 24
Peak memory	204628 kb
Host	smart-ef11ef11-9391-48b7-9aaa-ca765983a7be
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180336029 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.4180336029
Directory	/workspace/48.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/47.rv_dm_stress_all.3038257434
Short name	T10
Test name
Test status
Simulation time	3461194953 ps
CPU time	4.93 seconds
Started	May 19 01:08:30 PM PDT 24
Finished	May 19 01:08:46 PM PDT 24
Peak memory	204916 kb
Host	smart-6fe0781c-a586-44ca-bc1c-a424498625e3
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038257434 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.3038257434
Directory	/workspace/47.rv_dm_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/21.rv_dm_tap_fsm_rand_reset.2576199776
Short name	T28
Test name
Test status
Simulation time	7506340355 ps
CPU time	25.02 seconds
Started	May 19 01:07:37 PM PDT 24
Finished	May 19 01:08:04 PM PDT 24
Peak memory	219008 kb
Host	smart-1604d02e-39df-4f3e-b51a-03bc77975426
User	root
Command	/workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576199776 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 21.rv_dm_tap_fsm_rand_reset.2576199776
Directory	/workspace/21.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.1339226543
Short name	T81
Test name
Test status
Simulation time	787233721 ps
CPU time	8.25 seconds
Started	May 19 01:07:23 PM PDT 24
Finished	May 19 01:07:34 PM PDT 24
Peak memory	221328 kb
Host	smart-640c34de-d936-4017-baec-841aebb9c9c0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339226543 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.1339226543
Directory	/workspace/2.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/default/28.rv_dm_stress_all.1135915870
Short name	T7
Test name
Test status
Simulation time	7055161285 ps
CPU time	7.76 seconds
Started	May 19 01:08:26 PM PDT 24
Finished	May 19 01:08:44 PM PDT 24
Peak memory	204936 kb
Host	smart-86fa9d64-2903-4321-ab4d-0898bf6ccd1f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135915870 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.1135915870
Directory	/workspace/28.rv_dm_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2636400879
Short name	T45
Test name
Test status
Simulation time	606986883 ps
CPU time	1.87 seconds
Started	May 19 01:07:10 PM PDT 24
Finished	May 19 01:07:13 PM PDT 24
Peak memory	205096 kb
Host	smart-b46afb67-33a9-42c7-be00-78e62816d31f
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636400879 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs r_hw_reset.2636400879
Directory	/workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1143794457
Short name	T91
Test name
Test status
Simulation time	1136115302 ps
CPU time	67.27 seconds
Started	May 19 01:07:09 PM PDT 24
Finished	May 19 01:08:17 PM PDT 24
Peak memory	205104 kb
Host	smart-752f0a28-4a47-4ffc-97b2-d828453d0b9e
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143794457 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 1.rv_dm_csr_aliasing.1143794457
Directory	/workspace/1.rv_dm_csr_aliasing/latest

Test location	/workspace/coverage/default/13.rv_dm_stress_all.3312005187
Short name	T9
Test name
Test status
Simulation time	4172256531 ps
CPU time	4.43 seconds
Started	May 19 01:08:10 PM PDT 24
Finished	May 19 01:08:21 PM PDT 24
Peak memory	204932 kb
Host	smart-402b3d79-95f9-48cc-a34c-54f9391b2b3b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312005187 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.3312005187
Directory	/workspace/13.rv_dm_stress_all/latest

Test location	/workspace/coverage/default/1.rv_dm_sec_cm.2964262708
Short name	T38
Test name
Test status
Simulation time	146298776 ps
CPU time	1.05 seconds
Started	May 19 01:07:56 PM PDT 24
Finished	May 19 01:07:59 PM PDT 24
Peak memory	228772 kb
Host	smart-73425c02-493f-49c0-bc3a-6b888256961f
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964262708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.2964262708
Directory	/workspace/1.rv_dm_sec_cm/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2813001904
Short name	T96
Test name
Test status
Simulation time	354339175 ps
CPU time	5.61 seconds
Started	May 19 01:07:16 PM PDT 24
Finished	May 19 01:07:24 PM PDT 24
Peak memory	213332 kb
Host	smart-07f4e9df-7566-4889-856b-a7749c325b0b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813001904 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.2813001904
Directory	/workspace/4.rv_dm_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.588298105
Short name	T60
Test name
Test status
Simulation time	20176859673 ps
CPU time	20.33 seconds
Started	May 19 01:07:21 PM PDT 24
Finished	May 19 01:07:42 PM PDT 24
Peak memory	221568 kb
Host	smart-28bb5c94-5727-4fd7-85c5-cb6b2fec5554
User	root
Command	/workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588298105 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.588298105
Directory	/workspace/8.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspace/coverage/default/1.rv_dm_rom_read_access.1584642838
Short name	T11
Test name
Test status
Simulation time	229207647 ps
CPU time	0.78 seconds
Started	May 19 01:07:55 PM PDT 24
Finished	May 19 01:07:56 PM PDT 24
Peak memory	212916 kb
Host	smart-eb0334e3-744e-4fad-9bc5-f0bf3768b3b8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1584642838 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.1584642838
Directory	/workspace/1.rv_dm_rom_read_access/latest

Test location	/workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.649777310
Short name	T70
Test name
Test status
Simulation time	769007289 ps
CPU time	15.65 seconds
Started	May 19 01:07:22 PM PDT 24
Finished	May 19 01:07:39 PM PDT 24
Peak memory	213252 kb
Host	smart-e8a659e5-74c9-4036-95d5-d288cf30d915
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649777310 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.649777310
Directory	/workspace/7.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2108749607
Short name	T30
Test name
Test status
Simulation time	595807524 ps
CPU time	1.62 seconds
Started	May 19 01:07:10 PM PDT 24
Finished	May 19 01:07:12 PM PDT 24
Peak memory	205064 kb
Host	smart-6ced2cc7-608d-4617-b4b4-c604915c3702
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108749607 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs r_hw_reset.2108749607
Directory	/workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.2774596571
Short name	T82
Test name
Test status
Simulation time	1390752944 ps
CPU time	15.45 seconds
Started	May 19 01:07:19 PM PDT 24
Finished	May 19 01:07:36 PM PDT 24
Peak memory	221460 kb
Host	smart-2e75d59c-2d83-4658-b88a-4145eb1d34cc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774596571 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.2774596571
Directory	/workspace/8.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1048185342
Short name	T49
Test name
Test status
Simulation time	63820217392 ps
CPU time	88.33 seconds
Started	May 19 01:07:11 PM PDT 24
Finished	May 19 01:08:42 PM PDT 24
Peak memory	205256 kb
Host	smart-7395bf48-61eb-403a-a799-6fe16e416831
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048185342 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_bit_bash.1048185342
Directory	/workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2621209844
Short name	T66
Test name
Test status
Simulation time	1080985882 ps
CPU time	9.75 seconds
Started	May 19 01:07:35 PM PDT 24
Finished	May 19 01:07:47 PM PDT 24
Peak memory	221280 kb
Host	smart-a34a04b0-945d-482a-a183-27d384aec88a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621209844 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.2 621209844
Directory	/workspace/13.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/default/8.rv_dm_alert_test.2626127157
Short name	T22
Test name
Test status
Simulation time	35378059 ps
CPU time	0.73 seconds
Started	May 19 01:08:02 PM PDT 24
Finished	May 19 01:08:08 PM PDT 24
Peak memory	204628 kb
Host	smart-442abb49-f5b1-4dbb-8c4d-433362a93c16
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626127157 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.2626127157
Directory	/workspace/8.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/12.rv_dm_stress_all.769068737
Short name	T12
Test name
Test status
Simulation time	4484947841 ps
CPU time	10.79 seconds
Started	May 19 01:08:09 PM PDT 24
Finished	May 19 01:08:26 PM PDT 24
Peak memory	204828 kb
Host	smart-7931f65a-43d3-46a0-aca1-33be79653965
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769068737 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.769068737
Directory	/workspace/12.rv_dm_stress_all/latest

Test location	/workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.2034295385
Short name	T18
Test name
Test status
Simulation time	159546073 ps
CPU time	1.16 seconds
Started	May 19 01:07:56 PM PDT 24
Finished	May 19 01:07:59 PM PDT 24
Peak memory	204652 kb
Host	smart-4c9ebbc4-8e66-4de3-ab2b-f946d9c53320
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2034295385 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.2034295385
Directory	/workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.4035167283
Short name	T32
Test name
Test status
Simulation time	4992717201 ps
CPU time	8.88 seconds
Started	May 19 01:07:17 PM PDT 24
Finished	May 19 01:07:28 PM PDT 24
Peak memory	205188 kb
Host	smart-5f55d10c-51b8-4698-a09d-2e8fb4e9b869
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035167283 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_ csr_outstanding.4035167283
Directory	/workspace/4.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.4258477622
Short name	T68
Test name
Test status
Simulation time	477895102 ps
CPU time	9.04 seconds
Started	May 19 01:07:36 PM PDT 24
Finished	May 19 01:07:47 PM PDT 24
Peak memory	221388 kb
Host	smart-16ddc551-2d5d-4230-9bda-81f4de92f9dc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258477622 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.4 258477622
Directory	/workspace/18.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/default/2.rv_dm_sec_cm.3523097586
Short name	T25
Test name
Test status
Simulation time	202578910 ps
CPU time	1.33 seconds
Started	May 19 01:07:54 PM PDT 24
Finished	May 19 01:07:56 PM PDT 24
Peak memory	228788 kb
Host	smart-871c117b-8971-424d-8250-5e58de914d75
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523097586 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.3523097586
Directory	/workspace/2.rv_dm_sec_cm/latest

Test location	/workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.3135083805
Short name	T65
Test name
Test status
Simulation time	2522779521 ps
CPU time	19.97 seconds
Started	May 19 01:07:24 PM PDT 24
Finished	May 19 01:07:46 PM PDT 24
Peak memory	213284 kb
Host	smart-13f476fd-b687-4b24-8341-4d4559f37ff3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135083805 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.3135083805
Directory	/workspace/6.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1544910186
Short name	T157
Test name
Test status
Simulation time	81481395 ps
CPU time	0.92 seconds
Started	May 19 01:07:06 PM PDT 24
Finished	May 19 01:07:08 PM PDT 24
Peak memory	204820 kb
Host	smart-27142d06-c121-4f9f-927f-246f8a8751e4
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544910186 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_hw_reset.1544910186
Directory	/workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.2716280264
Short name	T264
Test name
Test status
Simulation time	666165807 ps
CPU time	8.49 seconds
Started	May 19 01:07:14 PM PDT 24
Finished	May 19 01:07:25 PM PDT 24
Peak memory	221452 kb
Host	smart-e4d7e88a-e31c-4e9d-aa58-654b062a28ec
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716280264 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.2716280264
Directory	/workspace/1.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.1595471062
Short name	T47
Test name
Test status
Simulation time	3434157067 ps
CPU time	4.23 seconds
Started	May 19 01:07:12 PM PDT 24
Finished	May 19 01:07:19 PM PDT 24
Peak memory	205136 kb
Host	smart-8388f1dd-affa-436c-a839-dfbc7aa14f96
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595471062 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs r_hw_reset.1595471062
Directory	/workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.1239871348
Short name	T94
Test name
Test status
Simulation time	209333226 ps
CPU time	2.46 seconds
Started	May 19 01:07:34 PM PDT 24
Finished	May 19 01:07:38 PM PDT 24
Peak memory	213236 kb
Host	smart-5dd85de7-ead5-417f-b2f5-bc9c031db0f8
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239871348 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.1239871348
Directory	/workspace/14.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.157925265
Short name	T118
Test name
Test status
Simulation time	315176987 ps
CPU time	5.88 seconds
Started	May 19 01:07:32 PM PDT 24
Finished	May 19 01:07:39 PM PDT 24
Peak memory	213356 kb
Host	smart-d1a8d6a8-e782-4889-9fa5-825c9546e8c2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157925265 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.157925265
Directory	/workspace/13.rv_dm_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2808329111
Short name	T61
Test name
Test status
Simulation time	47353270 ps
CPU time	0.75 seconds
Started	May 19 01:07:07 PM PDT 24
Finished	May 19 01:07:09 PM PDT 24
Peak memory	204832 kb
Host	smart-28ee6d1d-4640-4533-a06b-8f057c8c72e1
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808329111 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_hw_reset.2808329111
Directory	/workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location	/workspace/coverage/default/35.rv_dm_stress_all.1982816383
Short name	T75
Test name
Test status
Simulation time	446771913 ps
CPU time	1.87 seconds
Started	May 19 01:08:22 PM PDT 24
Finished	May 19 01:08:31 PM PDT 24
Peak memory	204828 kb
Host	smart-a6398d2a-6637-45e2-8c55-c19f411cf61f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982816383 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.1982816383
Directory	/workspace/35.rv_dm_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.1445694939
Short name	T59
Test name
Test status
Simulation time	104098080 ps
CPU time	2.41 seconds
Started	May 19 01:07:04 PM PDT 24
Finished	May 19 01:07:07 PM PDT 24
Peak memory	218960 kb
Host	smart-632b6947-2f49-4304-8225-e07a25d8e709
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445694939 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.1445694939
Directory	/workspace/0.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1321306486
Short name	T73
Test name
Test status
Simulation time	1275768700 ps
CPU time	2.78 seconds
Started	May 19 01:07:24 PM PDT 24
Finished	May 19 01:07:30 PM PDT 24
Peak memory	204996 kb
Host	smart-88d3cbc2-e9d9-4dd5-acfc-e2fd01c561f7
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321306486 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw. 1321306486
Directory	/workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/23.rv_dm_tap_fsm_rand_reset.4236838723
Short name	T64
Test name
Test status
Simulation time	14234453809 ps
CPU time	14.48 seconds
Started	May 19 01:07:37 PM PDT 24
Finished	May 19 01:07:53 PM PDT 24
Peak memory	217836 kb
Host	smart-b2434943-c75c-41ad-b60e-96462b4bdab3
User	root
Command	/workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236838723 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 23.rv_dm_tap_fsm_rand_reset.4236838723
Directory	/workspace/23.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1991254217
Short name	T111
Test name
Test status
Simulation time	5293013288 ps
CPU time	31.84 seconds
Started	May 19 01:07:05 PM PDT 24
Finished	May 19 01:07:37 PM PDT 24
Peak memory	213632 kb
Host	smart-f614b715-9a50-4148-85eb-9f4aa0607510
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991254217 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 0.rv_dm_csr_aliasing.1991254217
Directory	/workspace/0.rv_dm_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.3640855055
Short name	T256
Test name
Test status
Simulation time	13293156487 ps
CPU time	38.25 seconds
Started	May 19 01:07:08 PM PDT 24
Finished	May 19 01:07:47 PM PDT 24
Peak memory	213312 kb
Host	smart-f7863cb1-308c-4efd-ab6e-e09255459448
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640855055 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.3640855055
Directory	/workspace/0.rv_dm_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3707799955
Short name	T95
Test name
Test status
Simulation time	37755584 ps
CPU time	1.51 seconds
Started	May 19 01:07:06 PM PDT 24
Finished	May 19 01:07:09 PM PDT 24
Peak memory	213292 kb
Host	smart-b2905949-32cb-431f-b8c0-486dae8036c7
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707799955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.3707799955
Directory	/workspace/0.rv_dm_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3393968124
Short name	T213
Test name
Test status
Simulation time	278860290 ps
CPU time	2.18 seconds
Started	May 19 01:07:06 PM PDT 24
Finished	May 19 01:07:10 PM PDT 24
Peak memory	213352 kb
Host	smart-9e28f22a-cd51-4a94-bde3-c9b11009196e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393968124 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.3393968124
Directory	/workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3824235825
Short name	T250
Test name
Test status
Simulation time	15112355363 ps
CPU time	26.98 seconds
Started	May 19 01:07:06 PM PDT 24
Finished	May 19 01:07:34 PM PDT 24
Peak memory	205080 kb
Host	smart-f6edd911-50a5-47d1-afb4-48cb53998b72
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824235825 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs r_aliasing.3824235825
Directory	/workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2620718751
Short name	T46
Test name
Test status
Simulation time	3974437261 ps
CPU time	8.04 seconds
Started	May 19 01:07:11 PM PDT 24
Finished	May 19 01:07:20 PM PDT 24
Peak memory	205124 kb
Host	smart-4c859ad7-8dc2-4087-9464-761be3cf87bd
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620718751 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs r_hw_reset.2620718751
Directory	/workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2393967108
Short name	T51
Test name
Test status
Simulation time	1205471795 ps
CPU time	2.59 seconds
Started	May 19 01:07:09 PM PDT 24
Finished	May 19 01:07:13 PM PDT 24
Peak memory	204964 kb
Host	smart-fe103fd9-fbdb-494b-97c7-0fc415dd2bb2
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393967108 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.2 393967108
Directory	/workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3798566557
Short name	T203
Test name
Test status
Simulation time	91946854 ps
CPU time	0.95 seconds
Started	May 19 01:07:11 PM PDT 24
Finished	May 19 01:07:13 PM PDT 24
Peak memory	204712 kb
Host	smart-8416f3aa-35a7-4ec3-b42a-80a7631b7037
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798566557 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_aliasing.3798566557
Directory	/workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.566578528
Short name	T265
Test name
Test status
Simulation time	453540836 ps
CPU time	2.75 seconds
Started	May 19 01:07:06 PM PDT 24
Finished	May 19 01:07:10 PM PDT 24
Peak memory	205036 kb
Host	smart-16b78fea-235e-4f27-b242-884dfe15e90c
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566578528 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr _bit_bash.566578528
Directory	/workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3011712901
Short name	T166
Test name
Test status
Simulation time	84158760 ps
CPU time	0.87 seconds
Started	May 19 01:07:09 PM PDT 24
Finished	May 19 01:07:11 PM PDT 24
Peak memory	204752 kb
Host	smart-22587033-8ea3-4fd0-8e6c-cf94f0531cd5
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011712901 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.3 011712901
Directory	/workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.115397679
Short name	T182
Test name
Test status
Simulation time	21785668 ps
CPU time	0.69 seconds
Started	May 19 01:07:05 PM PDT 24
Finished	May 19 01:07:06 PM PDT 24
Peak memory	204652 kb
Host	smart-ca8ffe43-38c3-4f5a-898a-a73e10ff60f3
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115397679 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_part ial_access.115397679
Directory	/workspace/0.rv_dm_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.1286876412
Short name	T234
Test name
Test status
Simulation time	34520288 ps
CPU time	0.74 seconds
Started	May 19 01:07:06 PM PDT 24
Finished	May 19 01:07:08 PM PDT 24
Peak memory	204756 kb
Host	smart-a8f41ab3-d903-4a3f-933b-20a91efcc096
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286876412 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.1286876412
Directory	/workspace/0.rv_dm_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2687648038
Short name	T206
Test name
Test status
Simulation time	1266677479 ps
CPU time	7.69 seconds
Started	May 19 01:07:09 PM PDT 24
Finished	May 19 01:07:17 PM PDT 24
Peak memory	205084 kb
Host	smart-73bf7807-cb77-4622-ad0a-8da1ea2a031e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687648038 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_ csr_outstanding.2687648038
Directory	/workspace/0.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.907111225
Short name	T189
Test name
Test status
Simulation time	3767501766 ps
CPU time	15.83 seconds
Started	May 19 01:07:08 PM PDT 24
Finished	May 19 01:07:24 PM PDT 24
Peak memory	213296 kb
Host	smart-2d193c4e-d228-4910-8b8d-721ed010cdd4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907111225 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.907111225
Directory	/workspace/0.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2716530534
Short name	T200
Test name
Test status
Simulation time	3451418577 ps
CPU time	33.2 seconds
Started	May 19 01:07:13 PM PDT 24
Finished	May 19 01:07:48 PM PDT 24
Peak memory	205096 kb
Host	smart-2496edf0-6d20-432b-90ae-69823331fdd8
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716530534 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.2716530534
Directory	/workspace/1.rv_dm_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.1559993459
Short name	T63
Test name
Test status
Simulation time	63515150 ps
CPU time	1.48 seconds
Started	May 19 01:07:11 PM PDT 24
Finished	May 19 01:07:14 PM PDT 24
Peak memory	213244 kb
Host	smart-0c308bcf-0854-4e5b-82ea-72488c8ffe6f
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559993459 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.1559993459
Directory	/workspace/1.rv_dm_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.1770003808
Short name	T71
Test name
Test status
Simulation time	71741335 ps
CPU time	2.25 seconds
Started	May 19 01:07:10 PM PDT 24
Finished	May 19 01:07:13 PM PDT 24
Peak memory	217456 kb
Host	smart-c77ea4d2-76c4-4769-bed6-4bcf96f34be2
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770003808 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.1770003808
Directory	/workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.1494091713
Short name	T222
Test name
Test status
Simulation time	39157914 ps
CPU time	2.16 seconds
Started	May 19 01:07:11 PM PDT 24
Finished	May 19 01:07:15 PM PDT 24
Peak memory	219072 kb
Host	smart-1e231205-06b1-4353-84e2-a30ab12452fc
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494091713 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.1494091713
Directory	/workspace/1.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2152182599
Short name	T261
Test name
Test status
Simulation time	12126004065 ps
CPU time	24.66 seconds
Started	May 19 01:07:11 PM PDT 24
Finished	May 19 01:07:38 PM PDT 24
Peak memory	204996 kb
Host	smart-e3e2e34b-d8a5-41af-a4a8-c9d7aa17dc00
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152182599 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs r_aliasing.2152182599
Directory	/workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.4146443360
Short name	T246
Test name
Test status
Simulation time	86299487815 ps
CPU time	262.78 seconds
Started	May 19 01:07:13 PM PDT 24
Finished	May 19 01:11:38 PM PDT 24
Peak memory	205056 kb
Host	smart-3d830526-7593-4a04-a6f5-6098d27d74f0
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146443360 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_bit_bash.4146443360
Directory	/workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.3948587318
Short name	T48
Test name
Test status
Simulation time	678235099 ps
CPU time	1.8 seconds
Started	May 19 01:07:15 PM PDT 24
Finished	May 19 01:07:19 PM PDT 24
Peak memory	204916 kb
Host	smart-2cf7a1ce-f2f3-4ebd-8769-dbc0184a3894
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948587318 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.3 948587318
Directory	/workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.1496928743
Short name	T198
Test name
Test status
Simulation time	76961182 ps
CPU time	0.84 seconds
Started	May 19 01:07:11 PM PDT 24
Finished	May 19 01:07:13 PM PDT 24
Peak memory	204740 kb
Host	smart-8520ccdc-f7c3-4dc1-9cb4-14a2049f3658
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496928743 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_aliasing.1496928743
Directory	/workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.182820296
Short name	T170
Test name
Test status
Simulation time	491747389 ps
CPU time	1.97 seconds
Started	May 19 01:07:11 PM PDT 24
Finished	May 19 01:07:13 PM PDT 24
Peak memory	204892 kb
Host	smart-85949dd8-33a4-4d70-93ba-155aef9cfabb
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182820296 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr _bit_bash.182820296
Directory	/workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.452619259
Short name	T190
Test name
Test status
Simulation time	59398004 ps
CPU time	0.84 seconds
Started	May 19 01:07:06 PM PDT 24
Finished	May 19 01:07:08 PM PDT 24
Peak memory	204780 kb
Host	smart-96d22aa9-efa5-4487-a691-dd36251ece7f
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452619259 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.452619259
Directory	/workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1451367984
Short name	T164
Test name
Test status
Simulation time	120061324 ps
CPU time	0.66 seconds
Started	May 19 01:07:12 PM PDT 24
Finished	May 19 01:07:15 PM PDT 24
Peak memory	204776 kb
Host	smart-d7266678-d37b-4bb0-8ce1-723dc71de159
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451367984 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par tial_access.1451367984
Directory	/workspace/1.rv_dm_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.8903415
Short name	T207
Test name
Test status
Simulation time	24111039 ps
CPU time	0.65 seconds
Started	May 19 01:07:11 PM PDT 24
Finished	May 19 01:07:13 PM PDT 24
Peak memory	204768 kb
Host	smart-33667a0b-6b46-4d3d-8286-a5412ad613dc
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8903415 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.8903415
Directory	/workspace/1.rv_dm_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3134395166
Short name	T104
Test name
Test status
Simulation time	478193696 ps
CPU time	4.14 seconds
Started	May 19 01:07:11 PM PDT 24
Finished	May 19 01:07:16 PM PDT 24
Peak memory	205136 kb
Host	smart-02cc8fdb-85e6-443a-9a50-f17ab0a8e23a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134395166 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_ csr_outstanding.3134395166
Directory	/workspace/1.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3823384652
Short name	T212
Test name
Test status
Simulation time	266675826 ps
CPU time	3.6 seconds
Started	May 19 01:07:28 PM PDT 24
Finished	May 19 01:07:34 PM PDT 24
Peak memory	217416 kb
Host	smart-173450fd-849e-4f08-9aed-2193420144b2
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823384652 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.3823384652
Directory	/workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.224511372
Short name	T112
Test name
Test status
Simulation time	51805677 ps
CPU time	1.43 seconds
Started	May 19 01:07:25 PM PDT 24
Finished	May 19 01:07:29 PM PDT 24
Peak memory	213296 kb
Host	smart-0745d8bb-9f4c-460e-b458-b58c311aac81
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224511372 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.224511372
Directory	/workspace/10.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3996269463
Short name	T229
Test name
Test status
Simulation time	412489896 ps
CPU time	1.65 seconds
Started	May 19 01:07:23 PM PDT 24
Finished	May 19 01:07:27 PM PDT 24
Peak memory	204952 kb
Host	smart-fd5cc87a-62e4-4c20-a91a-22892673ecc9
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996269463 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw. 3996269463
Directory	/workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.2225924954
Short name	T153
Test name
Test status
Simulation time	70384441 ps
CPU time	0.88 seconds
Started	May 19 01:07:22 PM PDT 24
Finished	May 19 01:07:24 PM PDT 24
Peak memory	204768 kb
Host	smart-415afa1b-5c21-41b2-adbb-eb76f3d44fd3
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225924954 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw. 2225924954
Directory	/workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.2503005995
Short name	T93
Test name
Test status
Simulation time	1805062695 ps
CPU time	7.79 seconds
Started	May 19 01:07:27 PM PDT 24
Finished	May 19 01:07:37 PM PDT 24
Peak memory	205128 kb
Host	smart-b85d828b-920f-4961-b630-3fd0f9dcf760
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503005995 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same _csr_outstanding.2503005995
Directory	/workspace/10.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.2289215384
Short name	T223
Test name
Test status
Simulation time	272731346 ps
CPU time	4.62 seconds
Started	May 19 01:07:25 PM PDT 24
Finished	May 19 01:07:32 PM PDT 24
Peak memory	213304 kb
Host	smart-3de07f91-41b8-4868-86dc-8c99c6f56c51
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289215384 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.2289215384
Directory	/workspace/10.rv_dm_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2296598017
Short name	T122
Test name
Test status
Simulation time	1005176361 ps
CPU time	19.31 seconds
Started	May 19 01:07:24 PM PDT 24
Finished	May 19 01:07:46 PM PDT 24
Peak memory	221420 kb
Host	smart-1308f577-0e8e-41a4-8627-c959e1217988
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296598017 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.2 296598017
Directory	/workspace/10.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1051436986
Short name	T209
Test name
Test status
Simulation time	127831826 ps
CPU time	2.1 seconds
Started	May 19 01:07:27 PM PDT 24
Finished	May 19 01:07:31 PM PDT 24
Peak memory	216268 kb
Host	smart-0c01934e-1d21-426a-848b-2a5df038125e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051436986 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.1051436986
Directory	/workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.1015795708
Short name	T225
Test name
Test status
Simulation time	260793758 ps
CPU time	2.35 seconds
Started	May 19 01:07:26 PM PDT 24
Finished	May 19 01:07:31 PM PDT 24
Peak memory	221436 kb
Host	smart-a8ad52f6-17d3-4934-9e52-4e72b940fcc0
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015795708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.1015795708
Directory	/workspace/11.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.670960476
Short name	T62
Test name
Test status
Simulation time	503318412 ps
CPU time	2.67 seconds
Started	May 19 01:07:29 PM PDT 24
Finished	May 19 01:07:33 PM PDT 24
Peak memory	204976 kb
Host	smart-cfd9a6fb-3f08-487b-ad6b-2e25c0846ae6
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670960476 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.670960476
Directory	/workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.1454409464
Short name	T196
Test name
Test status
Simulation time	47753618 ps
CPU time	0.77 seconds
Started	May 19 01:07:23 PM PDT 24
Finished	May 19 01:07:27 PM PDT 24
Peak memory	204772 kb
Host	smart-1988badd-19cf-4e4e-91a9-d5781db22db7
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454409464 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw. 1454409464
Directory	/workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.985681191
Short name	T92
Test name
Test status
Simulation time	386476770 ps
CPU time	3.77 seconds
Started	May 19 01:07:29 PM PDT 24
Finished	May 19 01:07:34 PM PDT 24
Peak memory	205100 kb
Host	smart-8cb9c344-880f-4373-a219-65fc305ce315
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985681191 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same_ csr_outstanding.985681191
Directory	/workspace/11.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.3471559911
Short name	T224
Test name
Test status
Simulation time	127221810 ps
CPU time	3.44 seconds
Started	May 19 01:07:25 PM PDT 24
Finished	May 19 01:07:31 PM PDT 24
Peak memory	213364 kb
Host	smart-bfc251bd-5e96-420b-9607-271b7242eae7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471559911 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.3471559911
Directory	/workspace/11.rv_dm_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3549283644
Short name	T84
Test name
Test status
Simulation time	4692894260 ps
CPU time	20.24 seconds
Started	May 19 01:07:24 PM PDT 24
Finished	May 19 01:07:47 PM PDT 24
Peak memory	213540 kb
Host	smart-abbf0fa6-d665-468a-b7bb-090973fccc20
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549283644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.3 549283644
Directory	/workspace/11.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.2832037582
Short name	T214
Test name
Test status
Simulation time	3726825709 ps
CPU time	7.43 seconds
Started	May 19 01:07:26 PM PDT 24
Finished	May 19 01:07:36 PM PDT 24
Peak memory	217488 kb
Host	smart-c0b88f68-37d5-4ade-9286-3c3dbbba6e72
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832037582 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.2832037582
Directory	/workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.2566625461
Short name	T113
Test name
Test status
Simulation time	322858539 ps
CPU time	2.26 seconds
Started	May 19 01:07:26 PM PDT 24
Finished	May 19 01:07:30 PM PDT 24
Peak memory	218544 kb
Host	smart-229e1853-e0de-44c6-b14b-fa1a884e7c07
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566625461 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.2566625461
Directory	/workspace/12.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.4109878057
Short name	T169
Test name
Test status
Simulation time	78176666 ps
CPU time	0.84 seconds
Started	May 19 01:07:28 PM PDT 24
Finished	May 19 01:07:31 PM PDT 24
Peak memory	204776 kb
Host	smart-3ee41caa-b8fb-47a4-b6f8-f66c0f26738f
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109878057 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw. 4109878057
Directory	/workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1409882206
Short name	T101
Test name
Test status
Simulation time	492921547 ps
CPU time	7.56 seconds
Started	May 19 01:07:26 PM PDT 24
Finished	May 19 01:07:36 PM PDT 24
Peak memory	205112 kb
Host	smart-79c98a8d-1b96-40d4-a6eb-dc3c0566744c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409882206 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same _csr_outstanding.1409882206
Directory	/workspace/12.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.1283056820
Short name	T183
Test name
Test status
Simulation time	577417881 ps
CPU time	6.39 seconds
Started	May 19 01:07:25 PM PDT 24
Finished	May 19 01:07:34 PM PDT 24
Peak memory	213312 kb
Host	smart-be76b737-6845-4c33-ae49-e0ceda0e4f62
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283056820 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.1283056820
Directory	/workspace/12.rv_dm_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3758711286
Short name	T127
Test name
Test status
Simulation time	447844467 ps
CPU time	9.63 seconds
Started	May 19 01:07:25 PM PDT 24
Finished	May 19 01:07:37 PM PDT 24
Peak memory	213196 kb
Host	smart-44ca7614-a36d-41fc-aab0-aa697a3691db
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758711286 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.3 758711286
Directory	/workspace/12.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.2958912830
Short name	T175
Test name
Test status
Simulation time	3293647704 ps
CPU time	3.84 seconds
Started	May 19 01:07:31 PM PDT 24
Finished	May 19 01:07:35 PM PDT 24
Peak memory	218220 kb
Host	smart-923cf062-048f-40f4-8f24-5a2d001f1fde
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958912830 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.2958912830
Directory	/workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.634504072
Short name	T109
Test name
Test status
Simulation time	60881141 ps
CPU time	1.45 seconds
Started	May 19 01:07:36 PM PDT 24
Finished	May 19 01:07:39 PM PDT 24
Peak memory	213308 kb
Host	smart-6b0334f8-1d2b-4e74-b176-6d571515e5d0
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634504072 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.634504072
Directory	/workspace/13.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.909521615
Short name	T165
Test name
Test status
Simulation time	371025859 ps
CPU time	1.42 seconds
Started	May 19 01:07:28 PM PDT 24
Finished	May 19 01:07:31 PM PDT 24
Peak memory	204988 kb
Host	smart-3a6c76e6-6f1a-4713-b9cc-ebeada65a096
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909521615 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.909521615
Directory	/workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2425272625
Short name	T187
Test name
Test status
Simulation time	48897170 ps
CPU time	0.79 seconds
Started	May 19 01:07:27 PM PDT 24
Finished	May 19 01:07:30 PM PDT 24
Peak memory	204776 kb
Host	smart-1180993f-5c0d-4dcb-95d0-ae531d7c497a
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425272625 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw. 2425272625
Directory	/workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.476273846
Short name	T259
Test name
Test status
Simulation time	461975872 ps
CPU time	4.1 seconds
Started	May 19 01:07:33 PM PDT 24
Finished	May 19 01:07:40 PM PDT 24
Peak memory	205108 kb
Host	smart-2bc94435-c559-4238-826d-7b083dcde866
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476273846 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same_ csr_outstanding.476273846
Directory	/workspace/13.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3973441176
Short name	T80
Test name
Test status
Simulation time	147866526 ps
CPU time	2.32 seconds
Started	May 19 01:07:33 PM PDT 24
Finished	May 19 01:07:38 PM PDT 24
Peak memory	221512 kb
Host	smart-7cfec566-b640-437c-86de-77025cc31601
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973441176 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.3973441176
Directory	/workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1518932106
Short name	T72
Test name
Test status
Simulation time	388736349 ps
CPU time	1.64 seconds
Started	May 19 01:07:34 PM PDT 24
Finished	May 19 01:07:38 PM PDT 24
Peak memory	204880 kb
Host	smart-5a516913-2398-4106-975b-c4a299b8776e
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518932106 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw. 1518932106
Directory	/workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.3830015128
Short name	T231
Test name
Test status
Simulation time	40275381 ps
CPU time	0.7 seconds
Started	May 19 01:07:31 PM PDT 24
Finished	May 19 01:07:33 PM PDT 24
Peak memory	204752 kb
Host	smart-cecc5074-0e21-4a71-bd7d-d6c13e175cde
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830015128 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw. 3830015128
Directory	/workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2682719983
Short name	T238
Test name
Test status
Simulation time	299784064 ps
CPU time	3.62 seconds
Started	May 19 01:07:33 PM PDT 24
Finished	May 19 01:07:37 PM PDT 24
Peak memory	205040 kb
Host	smart-718d35e7-a962-4701-b530-12526ad74dd1
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682719983 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same _csr_outstanding.2682719983
Directory	/workspace/14.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.rv_dm_tap_fsm_rand_reset.3974357681
Short name	T245
Test name
Test status
Simulation time	10748878515 ps
CPU time	20.39 seconds
Started	May 19 01:07:34 PM PDT 24
Finished	May 19 01:07:56 PM PDT 24
Peak memory	215372 kb
Host	smart-9e2fefd3-f1db-4187-801c-a18756d02f74
User	root
Command	/workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974357681 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 14.rv_dm_tap_fsm_rand_reset.3974357681
Directory	/workspace/14.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.2081384545
Short name	T85
Test name
Test status
Simulation time	3249395750 ps
CPU time	20.17 seconds
Started	May 19 01:07:35 PM PDT 24
Finished	May 19 01:07:58 PM PDT 24
Peak memory	221492 kb
Host	smart-3a14a1c6-697c-4dce-a701-e87d0c541039
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081384545 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.2 081384545
Directory	/workspace/14.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.3009920434
Short name	T83
Test name
Test status
Simulation time	2688561394 ps
CPU time	2.93 seconds
Started	May 19 01:07:34 PM PDT 24
Finished	May 19 01:07:40 PM PDT 24
Peak memory	221056 kb
Host	smart-ff06ed81-3071-43c1-a0ac-4631f35c0c85
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009920434 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.3009920434
Directory	/workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.3479509572
Short name	T215
Test name
Test status
Simulation time	331483384 ps
CPU time	2.25 seconds
Started	May 19 01:07:32 PM PDT 24
Finished	May 19 01:07:36 PM PDT 24
Peak memory	218372 kb
Host	smart-3b180045-70cc-4237-991a-79ad6ad8ab84
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479509572 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.3479509572
Directory	/workspace/15.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.4249532716
Short name	T156
Test name
Test status
Simulation time	601171726 ps
CPU time	1.47 seconds
Started	May 19 01:07:32 PM PDT 24
Finished	May 19 01:07:34 PM PDT 24
Peak memory	204868 kb
Host	smart-f73a4bff-7c94-4080-923f-6ee7b1e44084
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249532716 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw. 4249532716
Directory	/workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.918254880
Short name	T236
Test name
Test status
Simulation time	43361783 ps
CPU time	0.84 seconds
Started	May 19 01:07:34 PM PDT 24
Finished	May 19 01:07:37 PM PDT 24
Peak memory	204704 kb
Host	smart-129deb2d-f2f0-4753-b4e8-fc04a2d067c1
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918254880 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.918254880
Directory	/workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.862260386
Short name	T267
Test name
Test status
Simulation time	249428171 ps
CPU time	4.22 seconds
Started	May 19 01:07:34 PM PDT 24
Finished	May 19 01:07:41 PM PDT 24
Peak memory	204940 kb
Host	smart-dc11ad55-195b-46cd-b2b1-b981ee5132de
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862260386 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same_ csr_outstanding.862260386
Directory	/workspace/15.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.3365470124
Short name	T221
Test name
Test status
Simulation time	207483722 ps
CPU time	2.49 seconds
Started	May 19 01:07:32 PM PDT 24
Finished	May 19 01:07:35 PM PDT 24
Peak memory	213368 kb
Host	smart-7af99570-c4e5-448a-8e78-01da76d9c8a8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365470124 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.3365470124
Directory	/workspace/15.rv_dm_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2015582836
Short name	T125
Test name
Test status
Simulation time	997771462 ps
CPU time	17.33 seconds
Started	May 19 01:07:32 PM PDT 24
Finished	May 19 01:07:50 PM PDT 24
Peak memory	221376 kb
Host	smart-4246dfcf-ffc6-4422-9bb9-112bc94907c1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015582836 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.2 015582836
Directory	/workspace/15.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.4278220448
Short name	T193
Test name
Test status
Simulation time	2825590151 ps
CPU time	3.09 seconds
Started	May 19 01:07:34 PM PDT 24
Finished	May 19 01:07:39 PM PDT 24
Peak memory	215440 kb
Host	smart-3288dc97-3a8c-482a-affa-21e118720ee1
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278220448 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.4278220448
Directory	/workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.3770265487
Short name	T107
Test name
Test status
Simulation time	576558354 ps
CPU time	1.44 seconds
Started	May 19 01:07:32 PM PDT 24
Finished	May 19 01:07:34 PM PDT 24
Peak memory	213256 kb
Host	smart-b242d440-22d4-4daf-be41-748c388530cc
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770265487 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.3770265487
Directory	/workspace/16.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2824232378
Short name	T240
Test name
Test status
Simulation time	1786933700 ps
CPU time	6.58 seconds
Started	May 19 01:07:33 PM PDT 24
Finished	May 19 01:07:42 PM PDT 24
Peak memory	205008 kb
Host	smart-9f0771de-f9d7-43c1-96f1-56f3702ed711
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824232378 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw. 2824232378
Directory	/workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.368418799
Short name	T255
Test name
Test status
Simulation time	26692894 ps
CPU time	0.7 seconds
Started	May 19 01:07:30 PM PDT 24
Finished	May 19 01:07:32 PM PDT 24
Peak memory	204784 kb
Host	smart-252ea878-7185-4dd4-af0f-cdd269a5a437
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368418799 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.368418799
Directory	/workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.2768737145
Short name	T199
Test name
Test status
Simulation time	86420078 ps
CPU time	3.36 seconds
Started	May 19 01:07:36 PM PDT 24
Finished	May 19 01:07:42 PM PDT 24
Peak memory	205072 kb
Host	smart-2e318cf7-3e63-43f3-b9d3-c555e3756f10
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768737145 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same _csr_outstanding.2768737145
Directory	/workspace/16.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3733840594
Short name	T184
Test name
Test status
Simulation time	62594728 ps
CPU time	3.29 seconds
Started	May 19 01:07:37 PM PDT 24
Finished	May 19 01:07:42 PM PDT 24
Peak memory	213240 kb
Host	smart-d3a2e4a2-4b6f-4276-b556-7ea2faf2c6df
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733840594 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.3733840594
Directory	/workspace/16.rv_dm_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.3483984888
Short name	T260
Test name
Test status
Simulation time	935817493 ps
CPU time	16.56 seconds
Started	May 19 01:07:34 PM PDT 24
Finished	May 19 01:07:53 PM PDT 24
Peak memory	221488 kb
Host	smart-0aa56b40-75c2-4894-93e6-190ae1acecb8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483984888 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.3 483984888
Directory	/workspace/16.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2208777
Short name	T98
Test name
Test status
Simulation time	72537041 ps
CPU time	2.35 seconds
Started	May 19 01:07:36 PM PDT 24
Finished	May 19 01:07:41 PM PDT 24
Peak memory	221420 kb
Host	smart-d832dfe0-ea46-4d9c-82d8-03c24d76e3a5
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208777 -assert nopostproc +UVM_TESTNAME=rv _dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.2208777
Directory	/workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.2023273711
Short name	T106
Test name
Test status
Simulation time	261293547 ps
CPU time	1.57 seconds
Started	May 19 01:07:36 PM PDT 24
Finished	May 19 01:07:40 PM PDT 24
Peak memory	218320 kb
Host	smart-ce6cb69d-44c5-465f-87cf-45776c23993a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023273711 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.2023273711
Directory	/workspace/17.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.627007109
Short name	T219
Test name
Test status
Simulation time	1572854190 ps
CPU time	5.72 seconds
Started	May 19 01:07:34 PM PDT 24
Finished	May 19 01:07:42 PM PDT 24
Peak memory	204916 kb
Host	smart-e70e2738-b5aa-4e49-8197-c8ba9b2c250f
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627007109 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.627007109
Directory	/workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2811077802
Short name	T248
Test name
Test status
Simulation time	51976016 ps
CPU time	0.69 seconds
Started	May 19 01:07:33 PM PDT 24
Finished	May 19 01:07:37 PM PDT 24
Peak memory	204776 kb
Host	smart-2fdbfb3c-8d95-4ff2-abd4-aeb69db9bf30
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811077802 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw. 2811077802
Directory	/workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2746315330
Short name	T191
Test name
Test status
Simulation time	228132107 ps
CPU time	3.68 seconds
Started	May 19 01:07:38 PM PDT 24
Finished	May 19 01:07:43 PM PDT 24
Peak memory	205084 kb
Host	smart-66bdc679-595d-4a7b-9bd6-e393629fc910
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746315330 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same _csr_outstanding.2746315330
Directory	/workspace/17.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.697418122
Short name	T178
Test name
Test status
Simulation time	122056167 ps
CPU time	3.97 seconds
Started	May 19 01:07:33 PM PDT 24
Finished	May 19 01:07:39 PM PDT 24
Peak memory	213320 kb
Host	smart-41e33a1d-963d-4016-b50d-bb168051e827
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697418122 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.697418122
Directory	/workspace/17.rv_dm_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.1176885299
Short name	T99
Test name
Test status
Simulation time	496080987 ps
CPU time	16.21 seconds
Started	May 19 01:07:33 PM PDT 24
Finished	May 19 01:07:52 PM PDT 24
Peak memory	221388 kb
Host	smart-12806321-6680-4bc2-8965-e9feb64961e6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176885299 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.1 176885299
Directory	/workspace/17.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.3588255922
Short name	T31
Test name
Test status
Simulation time	88613735 ps
CPU time	2.27 seconds
Started	May 19 01:07:36 PM PDT 24
Finished	May 19 01:07:41 PM PDT 24
Peak memory	221580 kb
Host	smart-d14eaad0-48c8-4612-89aa-8ce015cdbebf
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588255922 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.3588255922
Directory	/workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.4190899308
Short name	T108
Test name
Test status
Simulation time	835782780 ps
CPU time	2.61 seconds
Started	May 19 01:07:38 PM PDT 24
Finished	May 19 01:07:42 PM PDT 24
Peak memory	213332 kb
Host	smart-64546bbc-b332-4a86-9035-0e55c1e4a638
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190899308 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.4190899308
Directory	/workspace/18.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.3499603175
Short name	T204
Test name
Test status
Simulation time	265464567 ps
CPU time	1.49 seconds
Started	May 19 01:07:42 PM PDT 24
Finished	May 19 01:07:45 PM PDT 24
Peak memory	204872 kb
Host	smart-9bf685bc-e162-4e02-9b49-020df71c82fd
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499603175 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw. 3499603175
Directory	/workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.451518784
Short name	T168
Test name
Test status
Simulation time	46130787 ps
CPU time	0.72 seconds
Started	May 19 01:07:35 PM PDT 24
Finished	May 19 01:07:38 PM PDT 24
Peak memory	204788 kb
Host	smart-1999c3be-c0b6-42d4-b1f8-6d316f4bf3a8
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451518784 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.451518784
Directory	/workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.2831814385
Short name	T242
Test name
Test status
Simulation time	215605306 ps
CPU time	4.03 seconds
Started	May 19 01:07:36 PM PDT 24
Finished	May 19 01:07:42 PM PDT 24
Peak memory	205056 kb
Host	smart-a3f3a5df-f654-4128-a8c2-7d779b245ba9
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831814385 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same _csr_outstanding.2831814385
Directory	/workspace/18.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1290771515
Short name	T216
Test name
Test status
Simulation time	4518232227 ps
CPU time	5.79 seconds
Started	May 19 01:07:37 PM PDT 24
Finished	May 19 01:07:45 PM PDT 24
Peak memory	219488 kb
Host	smart-d4f0008e-9452-4342-8ab7-e1dfcc6f177a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290771515 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.1290771515
Directory	/workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.2201828704
Short name	T228
Test name
Test status
Simulation time	182258307 ps
CPU time	1.54 seconds
Started	May 19 01:07:42 PM PDT 24
Finished	May 19 01:07:45 PM PDT 24
Peak memory	213212 kb
Host	smart-e0af31c5-b910-403e-af06-5a9dd182405c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201828704 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.2201828704
Directory	/workspace/19.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2000621718
Short name	T251
Test name
Test status
Simulation time	196107478 ps
CPU time	1.19 seconds
Started	May 19 01:07:36 PM PDT 24
Finished	May 19 01:07:40 PM PDT 24
Peak memory	204936 kb
Host	smart-167884da-7b7f-4565-a721-ee0edfba46b9
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000621718 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw. 2000621718
Directory	/workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.1353433579
Short name	T235
Test name
Test status
Simulation time	92112226 ps
CPU time	0.72 seconds
Started	May 19 01:07:36 PM PDT 24
Finished	May 19 01:07:39 PM PDT 24
Peak memory	204788 kb
Host	smart-9430909c-a9e8-49b4-a46e-ed0a388098d9
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353433579 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw. 1353433579
Directory	/workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.3766037986
Short name	T208
Test name
Test status
Simulation time	396107124 ps
CPU time	3.43 seconds
Started	May 19 01:07:37 PM PDT 24
Finished	May 19 01:07:42 PM PDT 24
Peak memory	205080 kb
Host	smart-9ad7dca3-f487-43bd-8400-73b58394fb63
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766037986 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same _csr_outstanding.3766037986
Directory	/workspace/19.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.rv_dm_tap_fsm_rand_reset.2748692641
Short name	T217
Test name
Test status
Simulation time	11312892420 ps
CPU time	17.39 seconds
Started	May 19 01:07:37 PM PDT 24
Finished	May 19 01:07:56 PM PDT 24
Peak memory	221532 kb
Host	smart-c1303f3d-d4d2-4132-b61f-b8709b961d07
User	root
Command	/workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748692641 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 19.rv_dm_tap_fsm_rand_reset.2748692641
Directory	/workspace/19.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.2431461543
Short name	T171
Test name
Test status
Simulation time	193262975 ps
CPU time	3.87 seconds
Started	May 19 01:07:42 PM PDT 24
Finished	May 19 01:07:47 PM PDT 24
Peak memory	213260 kb
Host	smart-7228d323-7aab-46e7-a4de-d8ce8ae18a87
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431461543 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.2431461543
Directory	/workspace/19.rv_dm_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.1834951341
Short name	T123
Test name
Test status
Simulation time	4267227586 ps
CPU time	20.62 seconds
Started	May 19 01:07:35 PM PDT 24
Finished	May 19 01:07:58 PM PDT 24
Peak memory	221496 kb
Host	smart-b10f15be-accc-47fe-b9f0-c6f888916e23
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834951341 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.1 834951341
Directory	/workspace/19.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2910434407
Short name	T86
Test name
Test status
Simulation time	2485146620 ps
CPU time	27.77 seconds
Started	May 19 01:07:23 PM PDT 24
Finished	May 19 01:07:53 PM PDT 24
Peak memory	213416 kb
Host	smart-e215aaf2-7d27-413d-a8c4-92b0db7b43f9
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910434407 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 2.rv_dm_csr_aliasing.2910434407
Directory	/workspace/2.rv_dm_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.1108368134
Short name	T173
Test name
Test status
Simulation time	4963308693 ps
CPU time	33.06 seconds
Started	May 19 01:07:12 PM PDT 24
Finished	May 19 01:07:47 PM PDT 24
Peak memory	213344 kb
Host	smart-5e41485d-5d12-41af-95e1-0ca5c907d1ff
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108368134 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.1108368134
Directory	/workspace/2.rv_dm_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3910815842
Short name	T237
Test name
Test status
Simulation time	44313448 ps
CPU time	1.53 seconds
Started	May 19 01:07:13 PM PDT 24
Finished	May 19 01:07:17 PM PDT 24
Peak memory	213300 kb
Host	smart-49197828-72fc-4942-967f-30f5c7e8fe42
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910815842 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.3910815842
Directory	/workspace/2.rv_dm_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.1565464771
Short name	T79
Test name
Test status
Simulation time	1462366515 ps
CPU time	4.06 seconds
Started	May 19 01:07:10 PM PDT 24
Finished	May 19 01:07:15 PM PDT 24
Peak memory	218340 kb
Host	smart-06bef37b-20a6-4510-b209-ae8db54033d5
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565464771 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.1565464771
Directory	/workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1820852049
Short name	T195
Test name
Test status
Simulation time	60677204 ps
CPU time	1.62 seconds
Started	May 19 01:07:13 PM PDT 24
Finished	May 19 01:07:17 PM PDT 24
Peak memory	218544 kb
Host	smart-6ed37cb4-d70f-4114-affd-ccc7fb9fe3b6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820852049 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.1820852049
Directory	/workspace/2.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.3215931065
Short name	T226
Test name
Test status
Simulation time	18068400877 ps
CPU time	15.75 seconds
Started	May 19 01:07:13 PM PDT 24
Finished	May 19 01:07:30 PM PDT 24
Peak memory	205004 kb
Host	smart-57dfef98-52d4-4f95-bd6f-4462f3246aa6
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215931065 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs r_aliasing.3215931065
Directory	/workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1528544578
Short name	T205
Test name
Test status
Simulation time	28951468985 ps
CPU time	22.03 seconds
Started	May 19 01:07:11 PM PDT 24
Finished	May 19 01:07:35 PM PDT 24
Peak memory	204856 kb
Host	smart-fed4899d-447c-4e47-8597-8c02eb9352f1
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528544578 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_bit_bash.1528544578
Directory	/workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.4102671273
Short name	T192
Test name
Test status
Simulation time	750610119 ps
CPU time	2.39 seconds
Started	May 19 01:07:13 PM PDT 24
Finished	May 19 01:07:17 PM PDT 24
Peak memory	204988 kb
Host	smart-6f5524f7-1ee6-4ff6-a7ab-3041d61a2784
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102671273 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.4 102671273
Directory	/workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.1314959162
Short name	T67
Test name
Test status
Simulation time	117970691 ps
CPU time	0.78 seconds
Started	May 19 01:07:23 PM PDT 24
Finished	May 19 01:07:25 PM PDT 24
Peak memory	204764 kb
Host	smart-702aad30-943a-4cba-953b-ac044bf0a344
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314959162 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_aliasing.1314959162
Directory	/workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.3352689342
Short name	T181
Test name
Test status
Simulation time	471131876 ps
CPU time	1.93 seconds
Started	May 19 01:07:12 PM PDT 24
Finished	May 19 01:07:17 PM PDT 24
Peak memory	204944 kb
Host	smart-76faaf16-15bb-4468-ba19-7a46bf43ae83
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352689342 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_bit_bash.3352689342
Directory	/workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.64749160
Short name	T163
Test name
Test status
Simulation time	177328802 ps
CPU time	1.16 seconds
Started	May 19 01:07:12 PM PDT 24
Finished	May 19 01:07:15 PM PDT 24
Peak memory	204756 kb
Host	smart-acc61443-7967-4304-afa5-f1295d3291a7
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64749160 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_ hw_reset.64749160
Directory	/workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.334068294
Short name	T230
Test name
Test status
Simulation time	71693197 ps
CPU time	0.74 seconds
Started	May 19 01:07:09 PM PDT 24
Finished	May 19 01:07:11 PM PDT 24
Peak memory	204756 kb
Host	smart-660c8f79-c869-4a9d-a82d-5d75ce2a2d14
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334068294 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.334068294
Directory	/workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1543560189
Short name	T152
Test name
Test status
Simulation time	47697568 ps
CPU time	0.68 seconds
Started	May 19 01:07:13 PM PDT 24
Finished	May 19 01:07:15 PM PDT 24
Peak memory	204772 kb
Host	smart-ae6b6a23-2474-439c-83ac-728fd02b12a6
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543560189 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par tial_access.1543560189
Directory	/workspace/2.rv_dm_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.1775275718
Short name	T233
Test name
Test status
Simulation time	33196528 ps
CPU time	0.69 seconds
Started	May 19 01:07:13 PM PDT 24
Finished	May 19 01:07:16 PM PDT 24
Peak memory	204804 kb
Host	smart-b2a88bce-9130-44eb-846f-43bddaecc993
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775275718 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.1775275718
Directory	/workspace/2.rv_dm_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.4144570400
Short name	T115
Test name
Test status
Simulation time	81997807 ps
CPU time	3.48 seconds
Started	May 19 01:07:13 PM PDT 24
Finished	May 19 01:07:19 PM PDT 24
Peak memory	205036 kb
Host	smart-e5d92a5e-4695-4c01-87cd-47daeaaceca8
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144570400 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_ csr_outstanding.4144570400
Directory	/workspace/2.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.3030717377
Short name	T119
Test name
Test status
Simulation time	335597569 ps
CPU time	2.51 seconds
Started	May 19 01:07:23 PM PDT 24
Finished	May 19 01:07:28 PM PDT 24
Peak memory	213320 kb
Host	smart-0238577c-48a0-4dc0-998e-23c513db8144
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030717377 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.3030717377
Directory	/workspace/2.rv_dm_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1109690474
Short name	T89
Test name
Test status
Simulation time	4568830252 ps
CPU time	65.87 seconds
Started	May 19 01:07:23 PM PDT 24
Finished	May 19 01:08:31 PM PDT 24
Peak memory	213348 kb
Host	smart-6ef69c3a-d0cc-4465-8bfd-551e5031b615
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109690474 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 3.rv_dm_csr_aliasing.1109690474
Directory	/workspace/3.rv_dm_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.2279688900
Short name	T263
Test name
Test status
Simulation time	1515113780 ps
CPU time	26.98 seconds
Started	May 19 01:07:18 PM PDT 24
Finished	May 19 01:07:47 PM PDT 24
Peak memory	205024 kb
Host	smart-53df685b-4f0d-4133-807e-57710eba0642
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279688900 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.2279688900
Directory	/workspace/3.rv_dm_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.2586936804
Short name	T232
Test name
Test status
Simulation time	55481511 ps
CPU time	1.56 seconds
Started	May 19 01:07:15 PM PDT 24
Finished	May 19 01:07:20 PM PDT 24
Peak memory	213244 kb
Host	smart-4dc072d8-2749-401c-acd2-423f95ebfd4f
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586936804 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.2586936804
Directory	/workspace/3.rv_dm_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1169611531
Short name	T174
Test name
Test status
Simulation time	40380971 ps
CPU time	2.55 seconds
Started	May 19 01:07:15 PM PDT 24
Finished	May 19 01:07:20 PM PDT 24
Peak memory	218632 kb
Host	smart-2d6d5229-eea8-4a74-9f66-a78a16749091
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169611531 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.1169611531
Directory	/workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.701685494
Short name	T218
Test name
Test status
Simulation time	62368367 ps
CPU time	1.54 seconds
Started	May 19 01:07:15 PM PDT 24
Finished	May 19 01:07:19 PM PDT 24
Peak memory	221456 kb
Host	smart-1ec43f33-cfad-4c20-afcc-4d0423dd7bf6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701685494 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.701685494
Directory	/workspace/3.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.775654207
Short name	T69
Test name
Test status
Simulation time	10028637775 ps
CPU time	11.02 seconds
Started	May 19 01:07:16 PM PDT 24
Finished	May 19 01:07:29 PM PDT 24
Peak memory	204984 kb
Host	smart-8ad6c84e-7909-4c6a-b24e-531f8bc24adb
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775654207 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr _aliasing.775654207
Directory	/workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.4129818596
Short name	T268
Test name
Test status
Simulation time	17810295142 ps
CPU time	73.49 seconds
Started	May 19 01:07:18 PM PDT 24
Finished	May 19 01:08:33 PM PDT 24
Peak memory	205040 kb
Host	smart-542d55cf-d88f-4711-84d0-eced65bd8b0b
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129818596 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_bit_bash.4129818596
Directory	/workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1555413652
Short name	T241
Test name
Test status
Simulation time	871214473 ps
CPU time	1.91 seconds
Started	May 19 01:07:23 PM PDT 24
Finished	May 19 01:07:27 PM PDT 24
Peak memory	204996 kb
Host	smart-d0908a5e-c106-43eb-ae14-34709cd9fdd4
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555413652 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.1 555413652
Directory	/workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3965672648
Short name	T220
Test name
Test status
Simulation time	69743097 ps
CPU time	0.72 seconds
Started	May 19 01:07:14 PM PDT 24
Finished	May 19 01:07:17 PM PDT 24
Peak memory	204728 kb
Host	smart-723fd77f-1ab3-4680-ab6a-db02663b9f88
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965672648 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_aliasing.3965672648
Directory	/workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2560220821
Short name	T78
Test name
Test status
Simulation time	813736304 ps
CPU time	3.29 seconds
Started	May 19 01:07:23 PM PDT 24
Finished	May 19 01:07:28 PM PDT 24
Peak memory	204948 kb
Host	smart-3580fc1d-1269-49e9-acc5-7a03dc77114f
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560220821 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_bit_bash.2560220821
Directory	/workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.780816682
Short name	T257
Test name
Test status
Simulation time	92502460 ps
CPU time	0.82 seconds
Started	May 19 01:07:15 PM PDT 24
Finished	May 19 01:07:18 PM PDT 24
Peak memory	204824 kb
Host	smart-1f1e6499-c0d8-4b2d-958c-44999b22fc66
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780816682 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr _hw_reset.780816682
Directory	/workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.568016423
Short name	T172
Test name
Test status
Simulation time	54319951 ps
CPU time	0.69 seconds
Started	May 19 01:07:13 PM PDT 24
Finished	May 19 01:07:16 PM PDT 24
Peak memory	204788 kb
Host	smart-c1568754-ff76-447a-bb8f-7374688d4e1c
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568016423 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.568016423
Directory	/workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.825873490
Short name	T202
Test name
Test status
Simulation time	20438129 ps
CPU time	0.69 seconds
Started	May 19 01:07:15 PM PDT 24
Finished	May 19 01:07:18 PM PDT 24
Peak memory	204812 kb
Host	smart-24ab9fed-74b3-4c8f-9154-bd6bb8de2ce4
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825873490 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_part ial_access.825873490
Directory	/workspace/3.rv_dm_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.2122188904
Short name	T179
Test name
Test status
Simulation time	27442079 ps
CPU time	0.68 seconds
Started	May 19 01:07:15 PM PDT 24
Finished	May 19 01:07:18 PM PDT 24
Peak memory	204748 kb
Host	smart-41a7edd1-a864-4fc7-ac1a-afc346534b38
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122188904 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.2122188904
Directory	/workspace/3.rv_dm_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.3920900297
Short name	T102
Test name
Test status
Simulation time	387539918 ps
CPU time	3.78 seconds
Started	May 19 01:07:16 PM PDT 24
Finished	May 19 01:07:22 PM PDT 24
Peak memory	205044 kb
Host	smart-703327a6-ee92-4f2f-94f9-7eb15cc92fa1
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920900297 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_ csr_outstanding.3920900297
Directory	/workspace/3.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.2153540251
Short name	T210
Test name
Test status
Simulation time	7389122067 ps
CPU time	25.48 seconds
Started	May 19 01:07:19 PM PDT 24
Finished	May 19 01:07:46 PM PDT 24
Peak memory	213360 kb
Host	smart-f0ef3b23-3ae1-498e-be16-f107ce7c4bca
User	root
Command	/workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153540251 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.2153540251
Directory	/workspace/3.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.117034875
Short name	T211
Test name
Test status
Simulation time	122062749 ps
CPU time	3.79 seconds
Started	May 19 01:07:15 PM PDT 24
Finished	May 19 01:07:21 PM PDT 24
Peak memory	213400 kb
Host	smart-d6d6c32d-54db-4cce-a321-96c3db0bc5c8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117034875 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.117034875
Directory	/workspace/3.rv_dm_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2670665748
Short name	T128
Test name
Test status
Simulation time	812625592 ps
CPU time	10.13 seconds
Started	May 19 01:07:18 PM PDT 24
Finished	May 19 01:07:30 PM PDT 24
Peak memory	213300 kb
Host	smart-39bee7d1-c511-46c9-b786-7fb1ad90dfbf
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670665748 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.2670665748
Directory	/workspace/3.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/33.rv_dm_tap_fsm_rand_reset.1539156024
Short name	T131
Test name
Test status
Simulation time	16230922480 ps
CPU time	15.92 seconds
Started	May 19 01:07:46 PM PDT 24
Finished	May 19 01:08:03 PM PDT 24
Peak memory	221432 kb
Host	smart-99cc6a3b-1a18-4195-ad17-3e2e32defe32
User	root
Command	/workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539156024 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 33.rv_dm_tap_fsm_rand_reset.1539156024
Directory	/workspace/33.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/34.rv_dm_tap_fsm_rand_reset.2572672915
Short name	T29
Test name
Test status
Simulation time	33384079273 ps
CPU time	13.54 seconds
Started	May 19 01:07:41 PM PDT 24
Finished	May 19 01:07:56 PM PDT 24
Peak memory	221580 kb
Host	smart-2291fef4-5a5c-4a3e-84bd-da81ca3fa366
User	root
Command	/workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572672915 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 34.rv_dm_tap_fsm_rand_reset.2572672915
Directory	/workspace/34.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/37.rv_dm_tap_fsm_rand_reset.785728826
Short name	T129
Test name
Test status
Simulation time	5913867898 ps
CPU time	20.33 seconds
Started	May 19 01:07:43 PM PDT 24
Finished	May 19 01:08:04 PM PDT 24
Peak memory	221524 kb
Host	smart-4f0b0eea-9d41-4366-b3c7-03fc2a692bce
User	root
Command	/workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785728826 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 37.rv_dm_tap_fsm_rand_reset.785728826
Directory	/workspace/37.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2521031505
Short name	T201
Test name
Test status
Simulation time	2096526790 ps
CPU time	31.15 seconds
Started	May 19 01:07:18 PM PDT 24
Finished	May 19 01:07:51 PM PDT 24
Peak memory	205120 kb
Host	smart-4dc929c1-857b-48de-ac37-2953ab81027c
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521031505 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 4.rv_dm_csr_aliasing.2521031505
Directory	/workspace/4.rv_dm_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.2418923284
Short name	T244
Test name
Test status
Simulation time	8799265766 ps
CPU time	29.5 seconds
Started	May 19 01:07:16 PM PDT 24
Finished	May 19 01:07:48 PM PDT 24
Peak memory	204992 kb
Host	smart-00f45bd2-0138-4202-8edc-599450bd8e9d
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418923284 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.2418923284
Directory	/workspace/4.rv_dm_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2647748841
Short name	T105
Test name
Test status
Simulation time	243960739 ps
CPU time	2.51 seconds
Started	May 19 01:07:20 PM PDT 24
Finished	May 19 01:07:23 PM PDT 24
Peak memory	213072 kb
Host	smart-51e0e497-5e61-4aa1-8c6e-1adf68d5e511
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647748841 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.2647748841
Directory	/workspace/4.rv_dm_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.333863483
Short name	T167
Test name
Test status
Simulation time	3590534299 ps
CPU time	10.1 seconds
Started	May 19 01:07:18 PM PDT 24
Finished	May 19 01:07:30 PM PDT 24
Peak memory	221404 kb
Host	smart-c4e4a236-e1ee-40e8-8e5f-39ffd1004fcc
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333863483 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.333863483
Directory	/workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.2889786854
Short name	T253
Test name
Test status
Simulation time	31003494 ps
CPU time	1.44 seconds
Started	May 19 01:07:17 PM PDT 24
Finished	May 19 01:07:21 PM PDT 24
Peak memory	218272 kb
Host	smart-405e3f4b-4cba-4d63-b8b7-8027329f3d3c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889786854 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.2889786854
Directory	/workspace/4.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2806149606
Short name	T161
Test name
Test status
Simulation time	3467157966 ps
CPU time	18.27 seconds
Started	May 19 01:07:17 PM PDT 24
Finished	May 19 01:07:37 PM PDT 24
Peak memory	205020 kb
Host	smart-95bce6fb-62aa-40dc-8479-ceb99239e9af
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806149606 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs r_aliasing.2806149606
Directory	/workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3377148221
Short name	T50
Test name
Test status
Simulation time	24574465632 ps
CPU time	81.02 seconds
Started	May 19 01:07:15 PM PDT 24
Finished	May 19 01:08:38 PM PDT 24
Peak memory	205048 kb
Host	smart-4521fa26-4c29-4fbc-888c-5b650b9d5e15
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377148221 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_bit_bash.3377148221
Directory	/workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.680922884
Short name	T58
Test name
Test status
Simulation time	739132641 ps
CPU time	2.66 seconds
Started	May 19 01:07:17 PM PDT 24
Finished	May 19 01:07:22 PM PDT 24
Peak memory	205048 kb
Host	smart-77e0eef6-f474-4afe-aee8-62f5f4f50bd8
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680922884 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr _hw_reset.680922884
Directory	/workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.1542481993
Short name	T159
Test name
Test status
Simulation time	1300544145 ps
CPU time	2.06 seconds
Started	May 19 01:07:16 PM PDT 24
Finished	May 19 01:07:20 PM PDT 24
Peak memory	204880 kb
Host	smart-30c54110-0ab6-49e7-b73a-cd9f190a322b
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542481993 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.1 542481993
Directory	/workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.2449874089
Short name	T154
Test name
Test status
Simulation time	204763052 ps
CPU time	0.83 seconds
Started	May 19 01:07:14 PM PDT 24
Finished	May 19 01:07:17 PM PDT 24
Peak memory	204756 kb
Host	smart-3a70a698-e850-41b9-808b-51c20043a23b
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449874089 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs r_aliasing.2449874089
Directory	/workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2525650913
Short name	T160
Test name
Test status
Simulation time	2674454474 ps
CPU time	4.44 seconds
Started	May 19 01:07:15 PM PDT 24
Finished	May 19 01:07:22 PM PDT 24
Peak memory	205072 kb
Host	smart-3061f603-387f-4c9b-8837-db7100a88b25
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525650913 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs r_bit_bash.2525650913
Directory	/workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2059083822
Short name	T77
Test name
Test status
Simulation time	76850262 ps
CPU time	0.79 seconds
Started	May 19 01:07:16 PM PDT 24
Finished	May 19 01:07:19 PM PDT 24
Peak memory	204756 kb
Host	smart-2172c22f-850c-4efe-b2bb-b1255abc8f39
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059083822 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs r_hw_reset.2059083822
Directory	/workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.612452691
Short name	T158
Test name
Test status
Simulation time	34896060 ps
CPU time	0.75 seconds
Started	May 19 01:07:18 PM PDT 24
Finished	May 19 01:07:20 PM PDT 24
Peak memory	204812 kb
Host	smart-7abfdb72-820d-436f-88c1-ee363c6b2700
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612452691 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.612452691
Directory	/workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1364536535
Short name	T252
Test name
Test status
Simulation time	47294947 ps
CPU time	0.7 seconds
Started	May 19 01:07:15 PM PDT 24
Finished	May 19 01:07:18 PM PDT 24
Peak memory	204796 kb
Host	smart-a4bbdd7e-23c5-40b8-9da8-8a634e36ec3a
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364536535 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par tial_access.1364536535
Directory	/workspace/4.rv_dm_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.800307656
Short name	T266
Test name
Test status
Simulation time	15643802 ps
CPU time	0.66 seconds
Started	May 19 01:07:15 PM PDT 24
Finished	May 19 01:07:18 PM PDT 24
Peak memory	204724 kb
Host	smart-920cc141-4844-4b3d-8d28-0719e0d70d34
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800307656 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.800307656
Directory	/workspace/4.rv_dm_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.673938259
Short name	T188
Test name
Test status
Simulation time	13051241162 ps
CPU time	14.72 seconds
Started	May 19 01:07:15 PM PDT 24
Finished	May 19 01:07:33 PM PDT 24
Peak memory	220308 kb
Host	smart-2a2d089b-fbd9-4dd0-9509-cfb125ca87e7
User	root
Command	/workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673938259 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.673938259
Directory	/workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.3448833418
Short name	T121
Test name
Test status
Simulation time	807590966 ps
CPU time	9.66 seconds
Started	May 19 01:07:16 PM PDT 24
Finished	May 19 01:07:28 PM PDT 24
Peak memory	213132 kb
Host	smart-20fc2f7b-c399-4ab4-8d87-e69dc563fa76
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448833418 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.3448833418
Directory	/workspace/4.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.319325542
Short name	T176
Test name
Test status
Simulation time	44594104 ps
CPU time	2.38 seconds
Started	May 19 01:07:29 PM PDT 24
Finished	May 19 01:07:33 PM PDT 24
Peak memory	216932 kb
Host	smart-e4609eb6-a763-4be8-820f-b33f09fd3d93
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319325542 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.319325542
Directory	/workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.2363484019
Short name	T88
Test name
Test status
Simulation time	98281999 ps
CPU time	1.45 seconds
Started	May 19 01:07:17 PM PDT 24
Finished	May 19 01:07:21 PM PDT 24
Peak memory	221468 kb
Host	smart-6bf4ae08-d6e5-42c8-b20e-c8e75a121eca
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363484019 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.2363484019
Directory	/workspace/5.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3446923275
Short name	T180
Test name
Test status
Simulation time	1391178426 ps
CPU time	2.9 seconds
Started	May 19 01:07:18 PM PDT 24
Finished	May 19 01:07:23 PM PDT 24
Peak memory	205052 kb
Host	smart-56040203-0132-405b-96aa-cc487a683635
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446923275 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.3 446923275
Directory	/workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.1867448776
Short name	T227
Test name
Test status
Simulation time	42595274 ps
CPU time	0.68 seconds
Started	May 19 01:07:21 PM PDT 24
Finished	May 19 01:07:23 PM PDT 24
Peak memory	204716 kb
Host	smart-4dc95ccd-5325-4bb6-b4e5-899fb60387c6
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867448776 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.1 867448776
Directory	/workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.721678542
Short name	T114
Test name
Test status
Simulation time	212866973 ps
CPU time	4.27 seconds
Started	May 19 01:07:19 PM PDT 24
Finished	May 19 01:07:25 PM PDT 24
Peak memory	205040 kb
Host	smart-27a4493d-d64b-49d6-a36d-5cb4f4166f67
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721678542 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_c sr_outstanding.721678542
Directory	/workspace/5.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.2974783308
Short name	T27
Test name
Test status
Simulation time	21679926245 ps
CPU time	12.34 seconds
Started	May 19 01:07:15 PM PDT 24
Finished	May 19 01:07:30 PM PDT 24
Peak memory	216592 kb
Host	smart-360ca406-b815-48a6-817e-22c66d5e3277
User	root
Command	/workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974783308 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.2974783308
Directory	/workspace/5.rv_dm_tap_fsm_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.4281797625
Short name	T247
Test name
Test status
Simulation time	184659074 ps
CPU time	2.59 seconds
Started	May 19 01:07:17 PM PDT 24
Finished	May 19 01:07:22 PM PDT 24
Peak memory	213320 kb
Host	smart-bbe9ae31-59b0-438e-bf2f-5bd85feab9b8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281797625 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.4281797625
Directory	/workspace/5.rv_dm_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.977397203
Short name	T124
Test name
Test status
Simulation time	625794876 ps
CPU time	8.03 seconds
Started	May 19 01:07:20 PM PDT 24
Finished	May 19 01:07:29 PM PDT 24
Peak memory	221224 kb
Host	smart-ea0e3918-83ab-4b27-a8d4-133e8a9e6e69
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977397203 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.977397203
Directory	/workspace/5.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2785050235
Short name	T239
Test name
Test status
Simulation time	2507650807 ps
CPU time	3.46 seconds
Started	May 19 01:07:22 PM PDT 24
Finished	May 19 01:07:27 PM PDT 24
Peak memory	217288 kb
Host	smart-e41f4886-88eb-4649-8e87-b17f5a38dc5c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785050235 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.2785050235
Directory	/workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.3787357825
Short name	T100
Test name
Test status
Simulation time	394633474 ps
CPU time	2.44 seconds
Started	May 19 01:07:26 PM PDT 24
Finished	May 19 01:07:31 PM PDT 24
Peak memory	219156 kb
Host	smart-b1e1423a-96d0-47e6-a5e7-7f9f51f50b7b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787357825 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.3787357825
Directory	/workspace/6.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.1522979459
Short name	T249
Test name
Test status
Simulation time	267358644 ps
CPU time	1.7 seconds
Started	May 19 01:07:20 PM PDT 24
Finished	May 19 01:07:23 PM PDT 24
Peak memory	204924 kb
Host	smart-994109b0-3a51-4d54-96fd-37bc12bef792
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522979459 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.1 522979459
Directory	/workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2441583586
Short name	T254
Test name
Test status
Simulation time	66921417 ps
CPU time	0.75 seconds
Started	May 19 01:07:20 PM PDT 24
Finished	May 19 01:07:22 PM PDT 24
Peak memory	204972 kb
Host	smart-8c9b658b-5dc8-4ee8-9c38-263a08c479b0
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441583586 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.2 441583586
Directory	/workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.505761988
Short name	T269
Test name
Test status
Simulation time	802795421 ps
CPU time	4.24 seconds
Started	May 19 01:07:23 PM PDT 24
Finished	May 19 01:07:30 PM PDT 24
Peak memory	205056 kb
Host	smart-c214553a-aca5-4b73-b97a-aa4907406b78
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505761988 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_c sr_outstanding.505761988
Directory	/workspace/6.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.2478667390
Short name	T177
Test name
Test status
Simulation time	132129380 ps
CPU time	2.18 seconds
Started	May 19 01:07:29 PM PDT 24
Finished	May 19 01:07:33 PM PDT 24
Peak memory	213552 kb
Host	smart-991447cd-05f2-4f5f-8079-7660d9073db9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478667390 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.2478667390
Directory	/workspace/6.rv_dm_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2810512173
Short name	T97
Test name
Test status
Simulation time	358003124 ps
CPU time	4.03 seconds
Started	May 19 01:07:21 PM PDT 24
Finished	May 19 01:07:27 PM PDT 24
Peak memory	221548 kb
Host	smart-554ff730-6ee2-48b1-9e7a-5b84e68d1224
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810512173 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.2810512173
Directory	/workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.916113841
Short name	T194
Test name
Test status
Simulation time	91503712 ps
CPU time	1.57 seconds
Started	May 19 01:07:23 PM PDT 24
Finished	May 19 01:07:27 PM PDT 24
Peak memory	218896 kb
Host	smart-53b323a9-fd3c-4dcd-9ae0-d4c889bcdbee
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916113841 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.916113841
Directory	/workspace/7.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.1807558471
Short name	T197
Test name
Test status
Simulation time	528643790 ps
CPU time	2.58 seconds
Started	May 19 01:07:21 PM PDT 24
Finished	May 19 01:07:24 PM PDT 24
Peak memory	204932 kb
Host	smart-3f476348-ebbf-4e6f-adf4-9e3cabd3c021
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807558471 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.1 807558471
Directory	/workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.3515847027
Short name	T76
Test name
Test status
Simulation time	73567528 ps
CPU time	0.78 seconds
Started	May 19 01:07:21 PM PDT 24
Finished	May 19 01:07:23 PM PDT 24
Peak memory	204776 kb
Host	smart-e8e81726-a83c-4e69-9e00-734a23828e9f
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515847027 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.3 515847027
Directory	/workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3183950570
Short name	T87
Test name
Test status
Simulation time	147710675 ps
CPU time	6.47 seconds
Started	May 19 01:07:22 PM PDT 24
Finished	May 19 01:07:30 PM PDT 24
Peak memory	205064 kb
Host	smart-b3153778-40eb-4905-8797-aed41b00a6bb
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183950570 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_ csr_outstanding.3183950570
Directory	/workspace/7.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.923683378
Short name	T262
Test name
Test status
Simulation time	763709751 ps
CPU time	5.34 seconds
Started	May 19 01:07:23 PM PDT 24
Finished	May 19 01:07:30 PM PDT 24
Peak memory	213396 kb
Host	smart-4693eb9a-4809-462e-b824-40ef8401641e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923683378 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.923683378
Directory	/workspace/7.rv_dm_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2342051300
Short name	T74
Test name
Test status
Simulation time	4754378422 ps
CPU time	11.73 seconds
Started	May 19 01:07:22 PM PDT 24
Finished	May 19 01:07:36 PM PDT 24
Peak memory	219680 kb
Host	smart-464a6eb3-a9c5-47a0-932c-69836bd3c687
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342051300 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.2342051300
Directory	/workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1180311663
Short name	T185
Test name
Test status
Simulation time	89779328 ps
CPU time	1.48 seconds
Started	May 19 01:07:20 PM PDT 24
Finished	May 19 01:07:23 PM PDT 24
Peak memory	213260 kb
Host	smart-75491da5-b2ec-414e-a38e-3b87435db1dc
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180311663 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.1180311663
Directory	/workspace/8.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.2096308975
Short name	T155
Test name
Test status
Simulation time	419978477 ps
CPU time	2.24 seconds
Started	May 19 01:07:23 PM PDT 24
Finished	May 19 01:07:27 PM PDT 24
Peak memory	204952 kb
Host	smart-8bea3c0b-9632-4834-a1b8-c16893c7921e
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096308975 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.2 096308975
Directory	/workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.256114067
Short name	T162
Test name
Test status
Simulation time	70598317 ps
CPU time	0.69 seconds
Started	May 19 01:07:24 PM PDT 24
Finished	May 19 01:07:27 PM PDT 24
Peak memory	204780 kb
Host	smart-012555dc-1c46-4691-b0b0-1e32e8eda1e9
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256114067 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.256114067
Directory	/workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2202990884
Short name	T90
Test name
Test status
Simulation time	582643511 ps
CPU time	8.11 seconds
Started	May 19 01:07:23 PM PDT 24
Finished	May 19 01:07:33 PM PDT 24
Peak memory	205140 kb
Host	smart-73a9b29d-3840-47a8-a719-bc763da13126
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202990884 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_ csr_outstanding.2202990884
Directory	/workspace/8.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.1327839760
Short name	T258
Test name
Test status
Simulation time	2999003285 ps
CPU time	4.98 seconds
Started	May 19 01:07:22 PM PDT 24
Finished	May 19 01:07:29 PM PDT 24
Peak memory	221204 kb
Host	smart-988e2da1-d07a-4d5e-ab06-2faca127f0dd
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327839760 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.1327839760
Directory	/workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.2039195047
Short name	T110
Test name
Test status
Simulation time	198191612 ps
CPU time	2.41 seconds
Started	May 19 01:07:22 PM PDT 24
Finished	May 19 01:07:26 PM PDT 24
Peak memory	213240 kb
Host	smart-b88783bc-2b13-43bb-8e14-84db5710d435
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039195047 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.2039195047
Directory	/workspace/9.rv_dm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.1509240139
Short name	T243
Test name
Test status
Simulation time	196137420 ps
CPU time	1.04 seconds
Started	May 19 01:07:25 PM PDT 24
Finished	May 19 01:07:29 PM PDT 24
Peak memory	204940 kb
Host	smart-561a83d0-a906-454f-ae5a-1f625be4fd62
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509240139 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.1 509240139
Directory	/workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1798438414
Short name	T186
Test name
Test status
Simulation time	29196206 ps
CPU time	0.7 seconds
Started	May 19 01:07:19 PM PDT 24
Finished	May 19 01:07:21 PM PDT 24
Peak memory	204692 kb
Host	smart-c1b2fa0c-d4c2-4f92-8c36-54753667b409
User	root
Command	/workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798438414 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.1 798438414
Directory	/workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.1035656684
Short name	T103
Test name
Test status
Simulation time	261724241 ps
CPU time	4.34 seconds
Started	May 19 01:07:23 PM PDT 24
Finished	May 19 01:07:30 PM PDT 24
Peak memory	205112 kb
Host	smart-b31b896d-5331-44b6-9e24-ba7c84ec6c81
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035656684 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_ csr_outstanding.1035656684
Directory	/workspace/9.rv_dm_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.357954500
Short name	T120
Test name
Test status
Simulation time	281521180 ps
CPU time	5.57 seconds
Started	May 19 01:07:21 PM PDT 24
Finished	May 19 01:07:28 PM PDT 24
Peak memory	213384 kb
Host	smart-7b1a4bad-db8d-46c1-8b98-9d65ceb8303c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357954500 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.357954500
Directory	/workspace/9.rv_dm_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2977002932
Short name	T126
Test name
Test status
Simulation time	497878381 ps
CPU time	15.73 seconds
Started	May 19 01:07:20 PM PDT 24
Finished	May 19 01:07:37 PM PDT 24
Peak memory	213252 kb
Host	smart-d7e278ef-8349-4ce0-b76e-9f8ff42ecd81
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977002932 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.2977002932
Directory	/workspace/9.rv_dm_tl_intg_err/latest

Test location	/workspace/coverage/default/0.rv_dm_alert_test.2980185633
Short name	T134
Test name
Test status
Simulation time	35077512 ps
CPU time	0.74 seconds
Started	May 19 01:07:50 PM PDT 24
Finished	May 19 01:07:52 PM PDT 24
Peak memory	204636 kb
Host	smart-5e68889e-94e5-45fb-ba45-14bdd826a162
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980185633 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.2980185633
Directory	/workspace/0.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.2853358270
Short name	T14
Test name
Test status
Simulation time	25396501 ps
CPU time	0.71 seconds
Started	May 19 01:07:50 PM PDT 24
Finished	May 19 01:07:52 PM PDT 24
Peak memory	204544 kb
Host	smart-c373c758-f5ab-47fd-b83a-f6d45db79bc7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2853358270 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.2853358270
Directory	/workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location	/workspace/coverage/default/0.rv_dm_sec_cm.2903672130
Short name	T26
Test name
Test status
Simulation time	329841416 ps
CPU time	1.46 seconds
Started	May 19 01:07:48 PM PDT 24
Finished	May 19 01:07:50 PM PDT 24
Peak memory	229104 kb
Host	smart-9961e5e6-436b-4dab-ba54-c191c3de663f
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903672130 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.2903672130
Directory	/workspace/0.rv_dm_sec_cm/latest

Test location	/workspace/coverage/default/0.rv_dm_smoke.77658429
Short name	T149
Test name
Test status
Simulation time	845436084 ps
CPU time	1.4 seconds
Started	May 19 01:07:41 PM PDT 24
Finished	May 19 01:07:43 PM PDT 24
Peak memory	204684 kb
Host	smart-bf78a12b-f09d-49ef-8900-007660c0cb94
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=77658429 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.77658429
Directory	/workspace/0.rv_dm_smoke/latest

Test location	/workspace/coverage/default/1.rv_dm_alert_test.2359472764
Short name	T20
Test name
Test status
Simulation time	58363079 ps
CPU time	0.71 seconds
Started	May 19 01:07:55 PM PDT 24
Finished	May 19 01:07:57 PM PDT 24
Peak memory	204636 kb
Host	smart-e4ac35f3-b382-4235-8277-bf5818102064
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359472764 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.2359472764
Directory	/workspace/1.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.1111646979
Short name	T13
Test name
Test status
Simulation time	42054311 ps
CPU time	0.79 seconds
Started	May 19 01:07:54 PM PDT 24
Finished	May 19 01:07:56 PM PDT 24
Peak memory	204532 kb
Host	smart-283fca1c-350c-4fb7-998f-3e0ac0730c0a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1111646979 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.1111646979
Directory	/workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location	/workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.2661989934
Short name	T6
Test name
Test status
Simulation time	167458949 ps
CPU time	1.07 seconds
Started	May 19 01:07:55 PM PDT 24
Finished	May 19 01:07:58 PM PDT 24
Peak memory	204656 kb
Host	smart-3dfd3979-b7a4-4412-be9c-c77c59218454
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2661989934 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.2661989934
Directory	/workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location	/workspace/coverage/default/10.rv_dm_alert_test.3577345672
Short name	T5
Test name
Test status
Simulation time	37416751 ps
CPU time	0.76 seconds
Started	May 19 01:08:04 PM PDT 24
Finished	May 19 01:08:10 PM PDT 24
Peak memory	204632 kb
Host	smart-3a980c6f-8bf7-492e-9527-66c8e7843ed4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577345672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.3577345672
Directory	/workspace/10.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/11.rv_dm_alert_test.3105714662
Short name	T136
Test name
Test status
Simulation time	33463722 ps
CPU time	0.76 seconds
Started	May 19 01:08:02 PM PDT 24
Finished	May 19 01:08:07 PM PDT 24
Peak memory	204628 kb
Host	smart-9d59a0e3-28c7-4b83-beb6-01b1a9d3443c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105714662 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.3105714662
Directory	/workspace/11.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/12.rv_dm_alert_test.1020788142
Short name	T53
Test name
Test status
Simulation time	26935924 ps
CPU time	0.74 seconds
Started	May 19 01:08:15 PM PDT 24
Finished	May 19 01:08:21 PM PDT 24
Peak memory	204564 kb
Host	smart-483174af-f576-4c26-8ea0-a6e5f49d9509
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020788142 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.1020788142
Directory	/workspace/12.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/13.rv_dm_alert_test.145536284
Short name	T41
Test name
Test status
Simulation time	17583032 ps
CPU time	0.72 seconds
Started	May 19 01:08:09 PM PDT 24
Finished	May 19 01:08:16 PM PDT 24
Peak memory	204612 kb
Host	smart-9cb43136-3b81-4a19-bc0f-029459d8e9a7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145536284 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.145536284
Directory	/workspace/13.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/14.rv_dm_alert_test.1033239595
Short name	T130
Test name
Test status
Simulation time	27636633 ps
CPU time	0.71 seconds
Started	May 19 01:08:13 PM PDT 24
Finished	May 19 01:08:20 PM PDT 24
Peak memory	204656 kb
Host	smart-2d63b3ab-a89d-4f9f-86a3-c338beec6121
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033239595 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.1033239595
Directory	/workspace/14.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/15.rv_dm_alert_test.3652076665
Short name	T44
Test name
Test status
Simulation time	33815592 ps
CPU time	0.74 seconds
Started	May 19 01:08:11 PM PDT 24
Finished	May 19 01:08:18 PM PDT 24
Peak memory	204892 kb
Host	smart-dd3140bc-0565-4863-941d-dacb87d21120
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652076665 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.3652076665
Directory	/workspace/15.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/16.rv_dm_alert_test.229431992
Short name	T117
Test name
Test status
Simulation time	24856050 ps
CPU time	0.77 seconds
Started	May 19 01:08:13 PM PDT 24
Finished	May 19 01:08:19 PM PDT 24
Peak memory	204680 kb
Host	smart-27855f8e-1a7a-49cc-8034-50126ea2841d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229431992 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.229431992
Directory	/workspace/16.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/17.rv_dm_alert_test.807578913
Short name	T43
Test name
Test status
Simulation time	46146329 ps
CPU time	0.7 seconds
Started	May 19 01:08:15 PM PDT 24
Finished	May 19 01:08:22 PM PDT 24
Peak memory	204632 kb
Host	smart-9ccdbd77-eb97-4f29-b13d-b75c2d7a6c5e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807578913 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.807578913
Directory	/workspace/17.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/18.rv_dm_alert_test.371541316
Short name	T36
Test name
Test status
Simulation time	19663715 ps
CPU time	0.75 seconds
Started	May 19 01:08:19 PM PDT 24
Finished	May 19 01:08:25 PM PDT 24
Peak memory	204616 kb
Host	smart-f46d1a84-c46c-414b-9b9d-aad8c8fc3d2f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371541316 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.371541316
Directory	/workspace/18.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/19.rv_dm_alert_test.3941886543
Short name	T147
Test name
Test status
Simulation time	45342972 ps
CPU time	0.69 seconds
Started	May 19 01:08:17 PM PDT 24
Finished	May 19 01:08:24 PM PDT 24
Peak memory	204532 kb
Host	smart-3a82dd1d-0665-454b-b3e5-00dedad0b081
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941886543 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.3941886543
Directory	/workspace/19.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/2.rv_dm_alert_test.193180119
Short name	T35
Test name
Test status
Simulation time	83982894 ps
CPU time	0.77 seconds
Started	May 19 01:07:56 PM PDT 24
Finished	May 19 01:07:59 PM PDT 24
Peak memory	204892 kb
Host	smart-bc31623c-c270-44df-9b7d-fecbb62955f7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193180119 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.193180119
Directory	/workspace/2.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/20.rv_dm_alert_test.2354504615
Short name	T141
Test name
Test status
Simulation time	51178173 ps
CPU time	0.7 seconds
Started	May 19 01:08:18 PM PDT 24
Finished	May 19 01:08:25 PM PDT 24
Peak memory	204640 kb
Host	smart-6bc3177d-fc97-4497-9ff0-64d1e6a0ff88
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354504615 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.2354504615
Directory	/workspace/20.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/21.rv_dm_alert_test.123328526
Short name	T15
Test name
Test status
Simulation time	41986946 ps
CPU time	0.7 seconds
Started	May 19 01:08:17 PM PDT 24
Finished	May 19 01:08:24 PM PDT 24
Peak memory	204652 kb
Host	smart-ebb35318-c803-4e98-a417-20d5332b3266
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123328526 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.123328526
Directory	/workspace/21.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/22.rv_dm_alert_test.641777431
Short name	T37
Test name
Test status
Simulation time	18116981 ps
CPU time	0.7 seconds
Started	May 19 01:08:19 PM PDT 24
Finished	May 19 01:08:26 PM PDT 24
Peak memory	204620 kb
Host	smart-a87bb07e-8e3e-4c6b-ada8-9be0cf645821
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641777431 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.641777431
Directory	/workspace/22.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/23.rv_dm_alert_test.195245581
Short name	T34
Test name
Test status
Simulation time	57672744 ps
CPU time	0.71 seconds
Started	May 19 01:08:17 PM PDT 24
Finished	May 19 01:08:25 PM PDT 24
Peak memory	204648 kb
Host	smart-94560161-91a5-4389-a752-c4bdb97705f2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195245581 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.195245581
Directory	/workspace/23.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/24.rv_dm_alert_test.2064546964
Short name	T54
Test name
Test status
Simulation time	44434579 ps
CPU time	0.76 seconds
Started	May 19 01:08:19 PM PDT 24
Finished	May 19 01:08:26 PM PDT 24
Peak memory	204640 kb
Host	smart-1aa8f7ef-2c35-49aa-8820-c9f536499737
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064546964 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.2064546964
Directory	/workspace/24.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/25.rv_dm_alert_test.461467215
Short name	T144
Test name
Test status
Simulation time	15803493 ps
CPU time	0.72 seconds
Started	May 19 01:08:17 PM PDT 24
Finished	May 19 01:08:24 PM PDT 24
Peak memory	204608 kb
Host	smart-169abef7-4a58-4024-8316-c980f31e6648
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461467215 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.461467215
Directory	/workspace/25.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/26.rv_dm_alert_test.778728203
Short name	T56
Test name
Test status
Simulation time	46560134 ps
CPU time	0.7 seconds
Started	May 19 01:08:18 PM PDT 24
Finished	May 19 01:08:25 PM PDT 24
Peak memory	204616 kb
Host	smart-23c9ac98-2be9-4eb3-9892-f2dec8baa0b4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778728203 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.778728203
Directory	/workspace/26.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/27.rv_dm_alert_test.4166337870
Short name	T135
Test name
Test status
Simulation time	33689016 ps
CPU time	0.73 seconds
Started	May 19 01:08:24 PM PDT 24
Finished	May 19 01:08:32 PM PDT 24
Peak memory	203592 kb
Host	smart-9946006e-d5d6-451d-895d-73a7a28e9a56
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166337870 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.4166337870
Directory	/workspace/27.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/28.rv_dm_alert_test.670233684
Short name	T2
Test name
Test status
Simulation time	30421397 ps
CPU time	0.82 seconds
Started	May 19 01:08:22 PM PDT 24
Finished	May 19 01:08:29 PM PDT 24
Peak memory	204592 kb
Host	smart-a6fba10b-85d6-4bbd-9126-f7bb52218bb9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670233684 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.670233684
Directory	/workspace/28.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/29.rv_dm_alert_test.1068321044
Short name	T151
Test name
Test status
Simulation time	55853501 ps
CPU time	0.69 seconds
Started	May 19 01:08:23 PM PDT 24
Finished	May 19 01:08:31 PM PDT 24
Peak memory	204636 kb
Host	smart-1518e421-06ce-42b7-8ca9-0935abdfc03b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068321044 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.1068321044
Directory	/workspace/29.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/3.rv_dm_alert_test.2905310768
Short name	T116
Test name
Test status
Simulation time	90848604 ps
CPU time	0.72 seconds
Started	May 19 01:07:57 PM PDT 24
Finished	May 19 01:08:01 PM PDT 24
Peak memory	204616 kb
Host	smart-79002bf7-8be5-4331-b66a-618761e02cb0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905310768 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.2905310768
Directory	/workspace/3.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/3.rv_dm_sec_cm.2428258640
Short name	T55
Test name
Test status
Simulation time	250285559 ps
CPU time	1.26 seconds
Started	May 19 01:08:01 PM PDT 24
Finished	May 19 01:08:07 PM PDT 24
Peak memory	229112 kb
Host	smart-d12321b1-61fa-4d7a-8009-593bbb145f0d
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428258640 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.2428258640
Directory	/workspace/3.rv_dm_sec_cm/latest

Test location	/workspace/coverage/default/30.rv_dm_alert_test.19099655
Short name	T57
Test name
Test status
Simulation time	162715193 ps
CPU time	0.68 seconds
Started	May 19 01:08:22 PM PDT 24
Finished	May 19 01:08:30 PM PDT 24
Peak memory	204568 kb
Host	smart-93b8615c-5ea3-417c-898f-d3f592115692
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19099655 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.19099655
Directory	/workspace/30.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/31.rv_dm_alert_test.2952544867
Short name	T19
Test name
Test status
Simulation time	29513116 ps
CPU time	0.75 seconds
Started	May 19 01:08:26 PM PDT 24
Finished	May 19 01:08:35 PM PDT 24
Peak memory	204556 kb
Host	smart-008fad1b-be3c-4f6a-8b9a-30147f7ea17b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952544867 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.2952544867
Directory	/workspace/31.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/32.rv_dm_alert_test.2767308096
Short name	T145
Test name
Test status
Simulation time	193738459 ps
CPU time	0.74 seconds
Started	May 19 01:08:28 PM PDT 24
Finished	May 19 01:08:39 PM PDT 24
Peak memory	204620 kb
Host	smart-15bcc488-185a-43ca-aad9-4a284d2d6936
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767308096 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.2767308096
Directory	/workspace/32.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/33.rv_dm_alert_test.1988611286
Short name	T142
Test name
Test status
Simulation time	35999253 ps
CPU time	0.68 seconds
Started	May 19 01:08:23 PM PDT 24
Finished	May 19 01:08:32 PM PDT 24
Peak memory	204616 kb
Host	smart-9ab4e9e0-3fb4-4a0b-bab5-03984a9f6b7c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988611286 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.1988611286
Directory	/workspace/33.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/34.rv_dm_alert_test.2503609063
Short name	T16
Test name
Test status
Simulation time	40769218 ps
CPU time	0.68 seconds
Started	May 19 01:08:23 PM PDT 24
Finished	May 19 01:08:32 PM PDT 24
Peak memory	204576 kb
Host	smart-42cb3e61-8c14-4ede-ac88-97dfb7364e6c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503609063 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.2503609063
Directory	/workspace/34.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/35.rv_dm_alert_test.2701504755
Short name	T143
Test name
Test status
Simulation time	162113026 ps
CPU time	0.7 seconds
Started	May 19 01:08:26 PM PDT 24
Finished	May 19 01:08:37 PM PDT 24
Peak memory	204640 kb
Host	smart-fc0a70e9-c734-4e6b-a711-3a37983a9fba
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701504755 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.2701504755
Directory	/workspace/35.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/36.rv_dm_alert_test.3153771492
Short name	T140
Test name
Test status
Simulation time	48394248 ps
CPU time	0.7 seconds
Started	May 19 01:08:29 PM PDT 24
Finished	May 19 01:08:42 PM PDT 24
Peak memory	204564 kb
Host	smart-86609030-c393-44a9-b76f-4c34cdbed159
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153771492 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.3153771492
Directory	/workspace/36.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/36.rv_dm_stress_all.2799702710
Short name	T17
Test name
Test status
Simulation time	4925490844 ps
CPU time	5.19 seconds
Started	May 19 01:08:24 PM PDT 24
Finished	May 19 01:08:37 PM PDT 24
Peak memory	204040 kb
Host	smart-903052f7-3de5-4b55-b90a-7e245338ca93
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799702710 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.2799702710
Directory	/workspace/36.rv_dm_stress_all/latest

Test location	/workspace/coverage/default/37.rv_dm_alert_test.2255980717
Short name	T40
Test name
Test status
Simulation time	15266625 ps
CPU time	0.71 seconds
Started	May 19 01:08:22 PM PDT 24
Finished	May 19 01:08:29 PM PDT 24
Peak memory	204568 kb
Host	smart-575761a0-b48f-47a5-ba43-9c39493a8d11
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255980717 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.2255980717
Directory	/workspace/37.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/38.rv_dm_alert_test.4212702505
Short name	T132
Test name
Test status
Simulation time	62527455 ps
CPU time	0.73 seconds
Started	May 19 01:08:25 PM PDT 24
Finished	May 19 01:08:35 PM PDT 24
Peak memory	204604 kb
Host	smart-9d060fc5-2f92-4b37-8a66-57e7ca84ef1e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212702505 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.4212702505
Directory	/workspace/38.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/38.rv_dm_stress_all.3360231050
Short name	T8
Test name
Test status
Simulation time	4826977360 ps
CPU time	10.42 seconds
Started	May 19 01:08:26 PM PDT 24
Finished	May 19 01:08:47 PM PDT 24
Peak memory	204912 kb
Host	smart-7fa1da52-6139-4eac-a171-bd4135fa06f6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360231050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.3360231050
Directory	/workspace/38.rv_dm_stress_all/latest

Test location	/workspace/coverage/default/39.rv_dm_alert_test.4197788152
Short name	T39
Test name
Test status
Simulation time	48678373 ps
CPU time	0.71 seconds
Started	May 19 01:08:25 PM PDT 24
Finished	May 19 01:08:35 PM PDT 24
Peak memory	204616 kb
Host	smart-00a7609e-486d-4ff9-9e4a-355659d8df64
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197788152 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.4197788152
Directory	/workspace/39.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/4.rv_dm_alert_test.3352408294
Short name	T21
Test name
Test status
Simulation time	25569613 ps
CPU time	0.75 seconds
Started	May 19 01:07:59 PM PDT 24
Finished	May 19 01:08:04 PM PDT 24
Peak memory	204648 kb
Host	smart-6a5494e9-62e7-4578-b887-dc937938d934
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352408294 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.3352408294
Directory	/workspace/4.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/4.rv_dm_sec_cm.2618122522
Short name	T24
Test name
Test status
Simulation time	202986780 ps
CPU time	1.29 seconds
Started	May 19 01:07:59 PM PDT 24
Finished	May 19 01:08:04 PM PDT 24
Peak memory	228860 kb
Host	smart-9f4d99a9-6fda-4dbf-a119-46eaad622c6d
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618122522 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.2618122522
Directory	/workspace/4.rv_dm_sec_cm/latest

Test location	/workspace/coverage/default/40.rv_dm_alert_test.656096211
Short name	T23
Test name
Test status
Simulation time	21670434 ps
CPU time	0.7 seconds
Started	May 19 01:08:27 PM PDT 24
Finished	May 19 01:08:39 PM PDT 24
Peak memory	204644 kb
Host	smart-2b990b7f-3eaf-4246-9410-a4aff7e5d169
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656096211 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.656096211
Directory	/workspace/40.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/41.rv_dm_alert_test.1362733383
Short name	T146
Test name
Test status
Simulation time	91003351 ps
CPU time	0.7 seconds
Started	May 19 01:08:28 PM PDT 24
Finished	May 19 01:08:41 PM PDT 24
Peak memory	204848 kb
Host	smart-80f76d23-36d6-466e-98e0-4df9bd6c9999
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362733383 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.1362733383
Directory	/workspace/41.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/42.rv_dm_alert_test.2982898626
Short name	T139
Test name
Test status
Simulation time	225729814 ps
CPU time	0.75 seconds
Started	May 19 01:08:30 PM PDT 24
Finished	May 19 01:08:42 PM PDT 24
Peak memory	204656 kb
Host	smart-a7d7757b-8996-408a-9d56-404d6c9b0705
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982898626 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.2982898626
Directory	/workspace/42.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/43.rv_dm_alert_test.4051567213
Short name	T3
Test name
Test status
Simulation time	56440556 ps
CPU time	0.7 seconds
Started	May 19 01:08:27 PM PDT 24
Finished	May 19 01:08:38 PM PDT 24
Peak memory	204656 kb
Host	smart-620d2a40-931b-4c1d-92d7-b60f8a7b096a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051567213 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.4051567213
Directory	/workspace/43.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/44.rv_dm_alert_test.1304958474
Short name	T137
Test name
Test status
Simulation time	18371472 ps
CPU time	0.72 seconds
Started	May 19 01:08:29 PM PDT 24
Finished	May 19 01:08:41 PM PDT 24
Peak memory	204892 kb
Host	smart-1aa22ff4-ce02-45f1-86a7-4da8e9e8ec33
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304958474 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.1304958474
Directory	/workspace/44.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/45.rv_dm_alert_test.4239654370
Short name	T33
Test name
Test status
Simulation time	16664834 ps
CPU time	0.74 seconds
Started	May 19 01:08:25 PM PDT 24
Finished	May 19 01:08:35 PM PDT 24
Peak memory	204636 kb
Host	smart-fc7687b4-a889-4960-a63b-baa46ed1863c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239654370 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.4239654370
Directory	/workspace/45.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/46.rv_dm_alert_test.761499893
Short name	T4
Test name
Test status
Simulation time	17754662 ps
CPU time	0.7 seconds
Started	May 19 01:08:30 PM PDT 24
Finished	May 19 01:08:43 PM PDT 24
Peak memory	204560 kb
Host	smart-b1f6dc41-8486-4238-a8f8-1a78b91f413e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761499893 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.761499893
Directory	/workspace/46.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/47.rv_dm_alert_test.2181464148
Short name	T133
Test name
Test status
Simulation time	64946305 ps
CPU time	0.74 seconds
Started	May 19 01:08:26 PM PDT 24
Finished	May 19 01:08:37 PM PDT 24
Peak memory	204556 kb
Host	smart-f8e46f89-80d6-4a3d-b2e5-b59b41360896
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181464148 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.2181464148
Directory	/workspace/47.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/49.rv_dm_alert_test.2033566080
Short name	T148
Test name
Test status
Simulation time	67235226 ps
CPU time	0.72 seconds
Started	May 19 01:08:30 PM PDT 24
Finished	May 19 01:08:42 PM PDT 24
Peak memory	204652 kb
Host	smart-45ba8ef4-e837-4de6-a511-8e15a141a25d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033566080 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.2033566080
Directory	/workspace/49.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/5.rv_dm_alert_test.1794160048
Short name	T150
Test name
Test status
Simulation time	20909552 ps
CPU time	0.77 seconds
Started	May 19 01:08:01 PM PDT 24
Finished	May 19 01:08:07 PM PDT 24
Peak memory	204600 kb
Host	smart-792bd3a5-a8f9-4715-a88b-c2acfeaac470
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794160048 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.1794160048
Directory	/workspace/5.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/6.rv_dm_alert_test.4254697944
Short name	T52
Test name
Test status
Simulation time	20843668 ps
CPU time	0.71 seconds
Started	May 19 01:08:02 PM PDT 24
Finished	May 19 01:08:07 PM PDT 24
Peak memory	204556 kb
Host	smart-ab22c727-09e0-4c16-b106-39ea9322377d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254697944 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.4254697944
Directory	/workspace/6.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/7.rv_dm_alert_test.1281194758
Short name	T138
Test name
Test status
Simulation time	47983524 ps
CPU time	0.8 seconds
Started	May 19 01:08:06 PM PDT 24
Finished	May 19 01:08:12 PM PDT 24
Peak memory	204604 kb
Host	smart-971b6d71-c572-4f3c-826f-135b65044689
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281194758 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.1281194758
Directory	/workspace/7.rv_dm_alert_test/latest

Test location	/workspace/coverage/default/9.rv_dm_alert_test.1364594537
Short name	T42
Test name
Test status
Simulation time	54882164 ps
CPU time	0.7 seconds
Started	May 19 01:08:06 PM PDT 24
Finished	May 19 01:08:13 PM PDT 24
Peak memory	204640 kb
Host	smart-955600fa-9af6-4a58-9817-14cee39e5a6e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364594537 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.1364594537
Directory	/workspace/9.rv_dm_alert_test/latest

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