Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
78.09 94.66 81.18 86.65 70.51 84.50 98.52 30.59


Total test records in report: 348
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html
T267 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.3870804782 May 30 02:33:02 PM PDT 24 May 30 02:33:06 PM PDT 24 358838669 ps
T268 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2624539764 May 30 02:33:07 PM PDT 24 May 30 02:33:22 PM PDT 24 1808610050 ps
T269 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.1526714817 May 30 02:33:03 PM PDT 24 May 30 02:33:10 PM PDT 24 1347810760 ps
T94 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.1271760167 May 30 02:32:51 PM PDT 24 May 30 02:32:57 PM PDT 24 160554080 ps
T270 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.4131362277 May 30 02:32:52 PM PDT 24 May 30 02:33:00 PM PDT 24 269925931 ps
T271 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.2007945745 May 30 02:32:53 PM PDT 24 May 30 02:32:59 PM PDT 24 770802706 ps
T87 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.3622435995 May 30 02:32:46 PM PDT 24 May 30 02:32:52 PM PDT 24 11143071867 ps
T272 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.1054013572 May 30 02:33:06 PM PDT 24 May 30 02:33:12 PM PDT 24 503281069 ps
T273 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.1357984352 May 30 02:32:51 PM PDT 24 May 30 02:32:57 PM PDT 24 702887600 ps
T274 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.1862684763 May 30 02:32:51 PM PDT 24 May 30 02:32:58 PM PDT 24 4561339725 ps
T275 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2439907635 May 30 02:33:17 PM PDT 24 May 30 02:33:24 PM PDT 24 2472423464 ps
T276 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.4260522858 May 30 02:32:53 PM PDT 24 May 30 02:33:01 PM PDT 24 934833992 ps
T277 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.2203287825 May 30 02:33:05 PM PDT 24 May 30 02:33:13 PM PDT 24 5403032570 ps
T278 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.2781976928 May 30 02:32:49 PM PDT 24 May 30 02:32:51 PM PDT 24 91490870 ps
T279 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.4221969664 May 30 02:32:50 PM PDT 24 May 30 02:34:56 PM PDT 24 48347730671 ps
T280 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1002314797 May 30 02:32:51 PM PDT 24 May 30 02:33:03 PM PDT 24 2695726230 ps
T105 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.3546672370 May 30 02:32:46 PM PDT 24 May 30 02:32:49 PM PDT 24 172216467 ps
T281 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.114288067 May 30 02:33:16 PM PDT 24 May 30 02:33:24 PM PDT 24 258642969 ps
T282 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.3847083946 May 30 02:32:52 PM PDT 24 May 30 02:33:22 PM PDT 24 3103932557 ps
T283 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.74196689 May 30 02:33:06 PM PDT 24 May 30 02:33:12 PM PDT 24 156371658 ps
T284 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.531771275 May 30 02:32:38 PM PDT 24 May 30 02:32:42 PM PDT 24 193006166 ps
T285 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.3650784569 May 30 02:32:53 PM PDT 24 May 30 02:33:01 PM PDT 24 3345104644 ps
T286 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.1871874187 May 30 02:32:48 PM PDT 24 May 30 02:32:55 PM PDT 24 387561699 ps
T287 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1270618314 May 30 02:32:47 PM PDT 24 May 30 02:37:09 PM PDT 24 92402543339 ps
T95 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.85529311 May 30 02:32:50 PM PDT 24 May 30 02:33:20 PM PDT 24 2296067487 ps
T288 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1985010516 May 30 02:33:02 PM PDT 24 May 30 02:33:06 PM PDT 24 599769655 ps
T289 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1909353067 May 30 02:33:04 PM PDT 24 May 30 02:33:31 PM PDT 24 2606956319 ps
T96 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.1375928248 May 30 02:32:51 PM PDT 24 May 30 02:32:56 PM PDT 24 106394204 ps
T290 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.3872806443 May 30 02:33:18 PM PDT 24 May 30 02:33:25 PM PDT 24 670980266 ps
T291 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.1776643276 May 30 02:33:00 PM PDT 24 May 30 02:33:04 PM PDT 24 1997913931 ps
T292 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.1752982692 May 30 02:32:54 PM PDT 24 May 30 02:33:01 PM PDT 24 221280621 ps
T88 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1922705161 May 30 02:32:57 PM PDT 24 May 30 02:33:01 PM PDT 24 5779669035 ps
T293 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.403444888 May 30 02:33:07 PM PDT 24 May 30 02:33:15 PM PDT 24 2465130052 ps
T129 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.1387642958 May 30 02:33:06 PM PDT 24 May 30 02:33:26 PM PDT 24 1577508741 ps
T294 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.712425813 May 30 02:32:51 PM PDT 24 May 30 02:32:59 PM PDT 24 4399899233 ps
T295 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3371247835 May 30 02:32:55 PM PDT 24 May 30 02:33:00 PM PDT 24 653916296 ps
T126 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.186261030 May 30 02:32:56 PM PDT 24 May 30 02:33:23 PM PDT 24 5478280426 ps
T296 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.4205209850 May 30 02:32:48 PM PDT 24 May 30 02:32:54 PM PDT 24 2638143806 ps
T297 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.2689990190 May 30 02:32:49 PM PDT 24 May 30 02:32:52 PM PDT 24 29835636 ps
T298 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3127710991 May 30 02:33:22 PM PDT 24 May 30 02:33:35 PM PDT 24 610785869 ps
T299 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.3230016199 May 30 02:32:51 PM PDT 24 May 30 02:33:03 PM PDT 24 11096302834 ps
T300 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.1021038843 May 30 02:32:52 PM PDT 24 May 30 02:32:59 PM PDT 24 4476456965 ps
T301 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.2829505128 May 30 02:32:52 PM PDT 24 May 30 02:32:56 PM PDT 24 47390716 ps
T302 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.4033508713 May 30 02:33:01 PM PDT 24 May 30 02:33:06 PM PDT 24 219061153 ps
T303 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.4129835795 May 30 02:32:38 PM PDT 24 May 30 02:32:43 PM PDT 24 1109886506 ps
T120 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2317049743 May 30 02:33:08 PM PDT 24 May 30 02:33:13 PM PDT 24 110328539 ps
T304 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.76446265 May 30 02:32:49 PM PDT 24 May 30 02:33:22 PM PDT 24 1817523046 ps
T305 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3908776669 May 30 02:33:00 PM PDT 24 May 30 02:33:05 PM PDT 24 207864306 ps
T306 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.1226672136 May 30 02:32:55 PM PDT 24 May 30 02:32:58 PM PDT 24 116855075 ps
T307 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3610956046 May 30 02:33:02 PM PDT 24 May 30 02:33:04 PM PDT 24 278720206 ps
T308 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2238028207 May 30 02:32:52 PM PDT 24 May 30 02:32:55 PM PDT 24 110458149 ps
T309 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2701617384 May 30 02:33:09 PM PDT 24 May 30 02:33:13 PM PDT 24 269693480 ps
T97 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.1375011475 May 30 02:33:15 PM PDT 24 May 30 02:33:20 PM PDT 24 272112610 ps
T310 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3135118062 May 30 02:33:06 PM PDT 24 May 30 02:33:12 PM PDT 24 1889751160 ps
T311 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2913169198 May 30 02:32:54 PM PDT 24 May 30 02:32:58 PM PDT 24 1336793538 ps
T121 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.1736574472 May 30 02:33:23 PM PDT 24 May 30 02:33:31 PM PDT 24 98664927 ps
T312 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.4075961597 May 30 02:32:51 PM PDT 24 May 30 02:32:55 PM PDT 24 378084307 ps
T313 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1327993956 May 30 02:32:52 PM PDT 24 May 30 02:32:56 PM PDT 24 920719974 ps
T314 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.143431387 May 30 02:33:04 PM PDT 24 May 30 02:33:09 PM PDT 24 282274186 ps
T315 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3976685460 May 30 02:32:59 PM PDT 24 May 30 02:33:12 PM PDT 24 8293904099 ps
T316 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.3413339204 May 30 02:33:19 PM PDT 24 May 30 02:33:30 PM PDT 24 1162322665 ps
T317 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.1851714849 May 30 02:33:03 PM PDT 24 May 30 02:33:06 PM PDT 24 92909958 ps
T318 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1902782367 May 30 02:32:51 PM PDT 24 May 30 02:33:29 PM PDT 24 11284386015 ps
T319 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.1531003891 May 30 02:32:51 PM PDT 24 May 30 02:32:56 PM PDT 24 171602420 ps
T320 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2968540634 May 30 02:32:50 PM PDT 24 May 30 02:32:55 PM PDT 24 2338659525 ps
T321 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.1547934192 May 30 02:33:06 PM PDT 24 May 30 02:33:20 PM PDT 24 3647464899 ps
T322 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.457426378 May 30 02:32:47 PM PDT 24 May 30 02:33:34 PM PDT 24 83983526970 ps
T323 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.304386588 May 30 02:33:04 PM PDT 24 May 30 02:33:11 PM PDT 24 176811327 ps
T324 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.1062304459 May 30 02:32:49 PM PDT 24 May 30 02:32:52 PM PDT 24 671684079 ps
T127 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.3327064334 May 30 02:32:52 PM PDT 24 May 30 02:33:12 PM PDT 24 1280344355 ps
T325 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.2422089687 May 30 02:33:17 PM PDT 24 May 30 02:33:23 PM PDT 24 444413262 ps
T326 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.4005350835 May 30 02:32:50 PM PDT 24 May 30 02:32:54 PM PDT 24 2373536260 ps
T327 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1269195714 May 30 02:33:03 PM PDT 24 May 30 02:33:13 PM PDT 24 3746319652 ps
T328 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.2254435623 May 30 02:32:59 PM PDT 24 May 30 02:33:02 PM PDT 24 171301782 ps
T329 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.4266546564 May 30 02:32:48 PM PDT 24 May 30 02:32:51 PM PDT 24 1545674008 ps
T330 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.846954026 May 30 02:33:03 PM PDT 24 May 30 02:33:06 PM PDT 24 654876101 ps
T331 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.3990533887 May 30 02:32:50 PM PDT 24 May 30 02:33:44 PM PDT 24 1482294047 ps
T123 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.161649909 May 30 02:32:45 PM PDT 24 May 30 02:33:06 PM PDT 24 2594197454 ps
T98 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.110076561 May 30 02:33:01 PM PDT 24 May 30 02:33:09 PM PDT 24 1180514966 ps
T332 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2908124772 May 30 02:32:50 PM PDT 24 May 30 02:32:53 PM PDT 24 476290177 ps
T333 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.123658201 May 30 02:32:59 PM PDT 24 May 30 02:33:11 PM PDT 24 6283810843 ps
T334 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.3922724216 May 30 02:33:18 PM PDT 24 May 30 02:33:24 PM PDT 24 456467686 ps
T335 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1478608318 May 30 02:32:47 PM PDT 24 May 30 02:32:50 PM PDT 24 1318998211 ps
T99 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.3046687160 May 30 02:32:50 PM PDT 24 May 30 02:32:54 PM PDT 24 201002527 ps
T336 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.326808044 May 30 02:33:06 PM PDT 24 May 30 02:33:13 PM PDT 24 347901390 ps
T100 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1645499867 May 30 02:32:53 PM PDT 24 May 30 02:33:00 PM PDT 24 247493049 ps
T337 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3926596666 May 30 02:33:04 PM PDT 24 May 30 02:33:09 PM PDT 24 4014596691 ps
T338 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.511959930 May 30 02:33:07 PM PDT 24 May 30 02:33:11 PM PDT 24 280491049 ps
T339 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.209280633 May 30 02:33:01 PM PDT 24 May 30 02:33:06 PM PDT 24 264303877 ps
T340 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.402937176 May 30 02:32:40 PM PDT 24 May 30 02:33:08 PM PDT 24 632731782 ps
T341 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2285996633 May 30 02:33:05 PM PDT 24 May 30 02:33:24 PM PDT 24 5721994889 ps
T342 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3373152456 May 30 02:32:46 PM PDT 24 May 30 02:32:49 PM PDT 24 318906676 ps
T343 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3560074687 May 30 02:33:03 PM PDT 24 May 30 02:33:16 PM PDT 24 3432503040 ps
T344 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.1488748548 May 30 02:33:18 PM PDT 24 May 30 02:34:08 PM PDT 24 15793190767 ps
T345 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3236965911 May 30 02:33:00 PM PDT 24 May 30 02:33:04 PM PDT 24 1969248638 ps
T346 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.1174224319 May 30 02:33:08 PM PDT 24 May 30 02:33:11 PM PDT 24 321995721 ps
T347 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.1236025781 May 30 02:33:21 PM PDT 24 May 30 02:33:36 PM PDT 24 2426111847 ps
T348 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1519683728 May 30 02:32:45 PM PDT 24 May 30 02:34:29 PM PDT 24 36760848322 ps

Test location /workspace/coverage/default/46.rv_dm_stress_all.1255412178
Short name T4
Test name
Test status
Simulation time 11196084456 ps
CPU time 9.3 seconds
Started May 30 02:08:56 PM PDT 24
Finished May 30 02:09:07 PM PDT 24
Peak memory 205424 kb
Host smart-ee7b21a7-b5c4-43a9-ac01-66a08cd3c043
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255412178 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.1255412178
Directory /workspace/46.rv_dm_stress_all/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.417408111
Short name T3
Test name
Test status
Simulation time 23529526754 ps
CPU time 20.81 seconds
Started May 30 02:08:40 PM PDT 24
Finished May 30 02:09:02 PM PDT 24
Peak memory 216860 kb
Host smart-1fa2befb-e284-44fa-8dd6-7bb00f7ac8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417408111 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.417408111
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.3170914008
Short name T48
Test name
Test status
Simulation time 2321802633 ps
CPU time 67.38 seconds
Started May 30 02:32:53 PM PDT 24
Finished May 30 02:34:03 PM PDT 24
Peak memory 213940 kb
Host smart-79c852a7-bad7-4f8d-a467-52b27f8c85e3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170914008 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.3170914008
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.3357925936
Short name T24
Test name
Test status
Simulation time 63515503 ps
CPU time 0.77 seconds
Started May 30 02:08:47 PM PDT 24
Finished May 30 02:08:49 PM PDT 24
Peak memory 205064 kb
Host smart-22c4d9f1-b2a5-45eb-8f47-e324024d50fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357925936 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.3357925936
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.3033909712
Short name T61
Test name
Test status
Simulation time 45625086613 ps
CPU time 33.55 seconds
Started May 30 02:32:56 PM PDT 24
Finished May 30 02:33:32 PM PDT 24
Peak memory 218312 kb
Host smart-8ae1f1a3-39eb-4683-91cb-014743221695
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033909712 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.3033909712
Directory /workspace/5.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.2153616689
Short name T46
Test name
Test status
Simulation time 1386034839 ps
CPU time 17.66 seconds
Started May 30 02:33:00 PM PDT 24
Finished May 30 02:33:18 PM PDT 24
Peak memory 213880 kb
Host smart-863e4423-9987-40ad-af5b-02a11cedaf86
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153616689 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.2
153616689
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/12.rv_dm_stress_all.2014641304
Short name T13
Test name
Test status
Simulation time 10534470744 ps
CPU time 30.76 seconds
Started May 30 02:08:48 PM PDT 24
Finished May 30 02:09:20 PM PDT 24
Peak memory 205436 kb
Host smart-31ed1eee-df18-4c3b-a3aa-beb2057e5871
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014641304 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.2014641304
Directory /workspace/12.rv_dm_stress_all/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.3463760521
Short name T172
Test name
Test status
Simulation time 22387087154 ps
CPU time 23.29 seconds
Started May 30 02:08:39 PM PDT 24
Finished May 30 02:09:04 PM PDT 24
Peak memory 213648 kb
Host smart-f8cc5da9-10c3-4a8f-b726-8bf0d5b1c47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463760521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.3463760521
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/48.rv_dm_stress_all.1252022890
Short name T18
Test name
Test status
Simulation time 8145234588 ps
CPU time 7 seconds
Started May 30 02:08:53 PM PDT 24
Finished May 30 02:09:01 PM PDT 24
Peak memory 213652 kb
Host smart-17b8bc10-25f6-47b0-837a-0e551f9167c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252022890 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.1252022890
Directory /workspace/48.rv_dm_stress_all/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.3367395032
Short name T21
Test name
Test status
Simulation time 21135937124 ps
CPU time 11.66 seconds
Started May 30 02:07:22 PM PDT 24
Finished May 30 02:07:35 PM PDT 24
Peak memory 205560 kb
Host smart-7c065036-0c8f-4ec5-af01-3d214a9982c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367395032 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.3367395032
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.111763203
Short name T74
Test name
Test status
Simulation time 363928375 ps
CPU time 2.55 seconds
Started May 30 02:32:54 PM PDT 24
Finished May 30 02:32:59 PM PDT 24
Peak memory 213936 kb
Host smart-bfb188fb-65ad-43e9-ac1d-e0efa208942a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111763203 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.111763203
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.2718730198
Short name T39
Test name
Test status
Simulation time 646369156 ps
CPU time 2.62 seconds
Started May 30 02:07:23 PM PDT 24
Finished May 30 02:07:27 PM PDT 24
Peak memory 236792 kb
Host smart-4b1298cb-7c26-479b-9614-ea009b78447c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718730198 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.2718730198
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.1009593227
Short name T38
Test name
Test status
Simulation time 426922708 ps
CPU time 1.8 seconds
Started May 30 02:07:22 PM PDT 24
Finished May 30 02:07:26 PM PDT 24
Peak memory 204848 kb
Host smart-95e7cec6-bde0-4285-b9fb-6aaaff179945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009593227 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.1009593227
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.2060374635
Short name T29
Test name
Test status
Simulation time 148299001 ps
CPU time 0.84 seconds
Started May 30 02:07:17 PM PDT 24
Finished May 30 02:07:20 PM PDT 24
Peak memory 213348 kb
Host smart-2f7d64d1-0401-461e-bdc8-4cf51c862aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060374635 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.2060374635
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.3369396926
Short name T32
Test name
Test status
Simulation time 913823068 ps
CPU time 1.29 seconds
Started May 30 02:07:13 PM PDT 24
Finished May 30 02:07:16 PM PDT 24
Peak memory 205008 kb
Host smart-c673e3db-ecc6-42cb-9523-e630be3a5b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369396926 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.3369396926
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/31.rv_dm_stress_all.2453898315
Short name T131
Test name
Test status
Simulation time 12453522971 ps
CPU time 11.71 seconds
Started May 30 02:08:49 PM PDT 24
Finished May 30 02:09:02 PM PDT 24
Peak memory 213572 kb
Host smart-563c4c85-b4af-49ff-9bae-b5f75570300f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453898315 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.2453898315
Directory /workspace/31.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.1319355534
Short name T122
Test name
Test status
Simulation time 3270451716 ps
CPU time 20.1 seconds
Started May 30 02:32:53 PM PDT 24
Finished May 30 02:33:16 PM PDT 24
Peak memory 213968 kb
Host smart-0dbdc75e-9491-45ff-83f6-bb1d75bf094c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319355534 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.1319355534
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.4162833569
Short name T171
Test name
Test status
Simulation time 13951337209 ps
CPU time 43.24 seconds
Started May 30 02:08:42 PM PDT 24
Finished May 30 02:09:27 PM PDT 24
Peak memory 213808 kb
Host smart-790f0818-8f72-42f7-b1fd-97e3fba5fe44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162833569 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.4162833569
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.917659565
Short name T37
Test name
Test status
Simulation time 1151332061 ps
CPU time 1.45 seconds
Started May 30 02:07:14 PM PDT 24
Finished May 30 02:07:17 PM PDT 24
Peak memory 205028 kb
Host smart-3d85507f-72f6-4ba1-a27e-4a3f42658d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917659565 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.917659565
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.2281886906
Short name T79
Test name
Test status
Simulation time 2194252954 ps
CPU time 4.73 seconds
Started May 30 02:32:51 PM PDT 24
Finished May 30 02:32:59 PM PDT 24
Peak memory 205748 kb
Host smart-6674c641-519e-4134-b2bd-1c356bb0f7aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281886906 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.2281886906
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2040914496
Short name T63
Test name
Test status
Simulation time 27170796941 ps
CPU time 38.38 seconds
Started May 30 02:32:50 PM PDT 24
Finished May 30 02:33:30 PM PDT 24
Peak memory 205592 kb
Host smart-a37b77b1-0ae2-434c-a81b-55eafbdcc642
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040914496 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.2040914496
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1922705161
Short name T88
Test name
Test status
Simulation time 5779669035 ps
CPU time 2.82 seconds
Started May 30 02:32:57 PM PDT 24
Finished May 30 02:33:01 PM PDT 24
Peak memory 205648 kb
Host smart-ef9ec425-b308-4479-9323-3d8cdf73575e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922705161 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.1922705161
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.4088120358
Short name T44
Test name
Test status
Simulation time 942423287 ps
CPU time 10.71 seconds
Started May 30 02:33:04 PM PDT 24
Finished May 30 02:33:18 PM PDT 24
Peak memory 213868 kb
Host smart-88bb95ad-4a4c-40fb-bb79-cbe52b44a9b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088120358 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.4
088120358
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.1408105124
Short name T25
Test name
Test status
Simulation time 282020019 ps
CPU time 1.45 seconds
Started May 30 02:07:14 PM PDT 24
Finished May 30 02:07:17 PM PDT 24
Peak memory 204884 kb
Host smart-bc7030dc-be4f-4172-931e-413d93396580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408105124 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.1408105124
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.2356953375
Short name T16
Test name
Test status
Simulation time 1170840169 ps
CPU time 1.82 seconds
Started May 30 02:07:16 PM PDT 24
Finished May 30 02:07:20 PM PDT 24
Peak memory 205116 kb
Host smart-a946552f-490f-4fa5-b281-da3ead18e92c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356953375 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.2356953375
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.1375928248
Short name T96
Test name
Test status
Simulation time 106394204 ps
CPU time 1.52 seconds
Started May 30 02:32:51 PM PDT 24
Finished May 30 02:32:56 PM PDT 24
Peak memory 213632 kb
Host smart-c5bad641-d469-49fd-af6a-08859b2fc170
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375928248 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.1375928248
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.402937176
Short name T340
Test name
Test status
Simulation time 632731782 ps
CPU time 26.3 seconds
Started May 30 02:32:40 PM PDT 24
Finished May 30 02:33:08 PM PDT 24
Peak memory 214832 kb
Host smart-13b45c3b-210e-485a-ae5e-c75bb77fbcec
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402937176 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.rv_dm_csr_aliasing.402937176
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.3990533887
Short name T331
Test name
Test status
Simulation time 1482294047 ps
CPU time 52.42 seconds
Started May 30 02:32:50 PM PDT 24
Finished May 30 02:33:44 PM PDT 24
Peak memory 213780 kb
Host smart-0db0f736-4b14-4f5a-b4ff-5f8fe05b4434
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990533887 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.3990533887
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.1271760167
Short name T94
Test name
Test status
Simulation time 160554080 ps
CPU time 2.64 seconds
Started May 30 02:32:51 PM PDT 24
Finished May 30 02:32:57 PM PDT 24
Peak memory 213996 kb
Host smart-e0afb734-36f4-4e5b-8945-b24807706675
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271760167 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.1271760167
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.56312263
Short name T84
Test name
Test status
Simulation time 3077351552 ps
CPU time 4.36 seconds
Started May 30 02:32:51 PM PDT 24
Finished May 30 02:32:58 PM PDT 24
Peak memory 222224 kb
Host smart-4a3e1f5e-d1e0-45a2-a75e-dfde94b3e3d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56312263 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.56312263
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.3546672370
Short name T105
Test name
Test status
Simulation time 172216467 ps
CPU time 2.02 seconds
Started May 30 02:32:46 PM PDT 24
Finished May 30 02:32:49 PM PDT 24
Peak memory 213860 kb
Host smart-e1eb73a3-c5a7-47a8-aeee-7044bfa9dfd6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546672370 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.3546672370
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1270618314
Short name T287
Test name
Test status
Simulation time 92402543339 ps
CPU time 261.01 seconds
Started May 30 02:32:47 PM PDT 24
Finished May 30 02:37:09 PM PDT 24
Peak memory 205596 kb
Host smart-38d835bb-d697-4e92-aeec-39e0f8905ca6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270618314 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.rv_dm_jtag_dmi_csr_bit_bash.1270618314
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2968540634
Short name T320
Test name
Test status
Simulation time 2338659525 ps
CPU time 2.64 seconds
Started May 30 02:32:50 PM PDT 24
Finished May 30 02:32:55 PM PDT 24
Peak memory 205640 kb
Host smart-e82b30d3-e967-4d2b-84ac-2d343f152bc3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968540634 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.2968540634
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.1206321961
Short name T246
Test name
Test status
Simulation time 10971268187 ps
CPU time 10.17 seconds
Started May 30 02:32:56 PM PDT 24
Finished May 30 02:33:08 PM PDT 24
Peak memory 205528 kb
Host smart-d1d9aaee-130f-45f4-bc05-d82f1f52ea7c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206321961 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.1
206321961
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.1062304459
Short name T324
Test name
Test status
Simulation time 671684079 ps
CPU time 1.18 seconds
Started May 30 02:32:49 PM PDT 24
Finished May 30 02:32:52 PM PDT 24
Peak memory 205264 kb
Host smart-a2bc5156-8362-41b2-aa0e-448195d3a41a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062304459 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.1062304459
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.3230016199
Short name T299
Test name
Test status
Simulation time 11096302834 ps
CPU time 9.26 seconds
Started May 30 02:32:51 PM PDT 24
Finished May 30 02:33:03 PM PDT 24
Peak memory 205628 kb
Host smart-2058a3ab-d768-487c-b222-78ddd9cfbe72
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230016199 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.3230016199
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.531771275
Short name T284
Test name
Test status
Simulation time 193006166 ps
CPU time 1.29 seconds
Started May 30 02:32:38 PM PDT 24
Finished May 30 02:32:42 PM PDT 24
Peak memory 205328 kb
Host smart-89a7a179-5e9f-491c-9d45-cacb7a3da0b4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531771275 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr
_hw_reset.531771275
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.4129835795
Short name T303
Test name
Test status
Simulation time 1109886506 ps
CPU time 1.57 seconds
Started May 30 02:32:38 PM PDT 24
Finished May 30 02:32:43 PM PDT 24
Peak memory 205276 kb
Host smart-1c08166b-2ded-4e80-a093-5f6e3c26661d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129835795 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.4
129835795
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.2689990190
Short name T297
Test name
Test status
Simulation time 29835636 ps
CPU time 0.73 seconds
Started May 30 02:32:49 PM PDT 24
Finished May 30 02:32:52 PM PDT 24
Peak memory 205320 kb
Host smart-0fb8ff3a-ab34-4213-82c8-93da72c09d58
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689990190 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.2689990190
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.2009892616
Short name T247
Test name
Test status
Simulation time 153078680 ps
CPU time 0.79 seconds
Started May 30 02:32:48 PM PDT 24
Finished May 30 02:32:50 PM PDT 24
Peak memory 205244 kb
Host smart-337a4af2-ac12-4ec5-8a66-a51b6088c9d2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009892616 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.2009892616
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2390447768
Short name T108
Test name
Test status
Simulation time 272228522 ps
CPU time 6.56 seconds
Started May 30 02:32:56 PM PDT 24
Finished May 30 02:33:04 PM PDT 24
Peak memory 205596 kb
Host smart-6e521d67-c3eb-4ba9-b996-cfd9a9f03711
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390447768 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.2390447768
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.85529311
Short name T95
Test name
Test status
Simulation time 2296067487 ps
CPU time 27.86 seconds
Started May 30 02:32:50 PM PDT 24
Finished May 30 02:33:20 PM PDT 24
Peak memory 205716 kb
Host smart-28e8db52-0e1d-4fa0-9831-d571b525cb80
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85529311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UV
M_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 1.rv_dm_csr_aliasing.85529311
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.709231057
Short name T104
Test name
Test status
Simulation time 14939071037 ps
CPU time 75.43 seconds
Started May 30 02:32:49 PM PDT 24
Finished May 30 02:34:05 PM PDT 24
Peak memory 213908 kb
Host smart-227a737e-d867-49fe-a755-6e0fb357b9ed
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709231057 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.709231057
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.1731744360
Short name T80
Test name
Test status
Simulation time 328637993 ps
CPU time 1.73 seconds
Started May 30 02:32:51 PM PDT 24
Finished May 30 02:32:55 PM PDT 24
Peak memory 213804 kb
Host smart-5f4e0522-f3b1-4e8e-b1bc-132af99ee3fb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731744360 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.1731744360
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1519683728
Short name T348
Test name
Test status
Simulation time 36760848322 ps
CPU time 103.28 seconds
Started May 30 02:32:45 PM PDT 24
Finished May 30 02:34:29 PM PDT 24
Peak memory 205596 kb
Host smart-8f749003-a395-46b9-9dce-3967d63166ef
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519683728 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.1519683728
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.457426378
Short name T322
Test name
Test status
Simulation time 83983526970 ps
CPU time 45.89 seconds
Started May 30 02:32:47 PM PDT 24
Finished May 30 02:33:34 PM PDT 24
Peak memory 205536 kb
Host smart-6b498732-f9b6-42de-a81f-2c60c825b08a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457426378 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.rv_dm_jtag_dmi_csr_bit_bash.457426378
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2859020915
Short name T257
Test name
Test status
Simulation time 4661446695 ps
CPU time 14.54 seconds
Started May 30 02:32:47 PM PDT 24
Finished May 30 02:33:02 PM PDT 24
Peak memory 205588 kb
Host smart-368f61a4-d815-4a35-b9cb-825d8be423ba
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859020915 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.2
859020915
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3373152456
Short name T342
Test name
Test status
Simulation time 318906676 ps
CPU time 1.65 seconds
Started May 30 02:32:46 PM PDT 24
Finished May 30 02:32:49 PM PDT 24
Peak memory 205264 kb
Host smart-4e0904d2-f239-4c0c-836c-218803f87edc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373152456 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.3373152456
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.4266546564
Short name T329
Test name
Test status
Simulation time 1545674008 ps
CPU time 2.24 seconds
Started May 30 02:32:48 PM PDT 24
Finished May 30 02:32:51 PM PDT 24
Peak memory 205320 kb
Host smart-8027c707-581f-4302-856b-36b75f78d4d0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266546564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.4266546564
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.4229407496
Short name T253
Test name
Test status
Simulation time 161510899 ps
CPU time 0.7 seconds
Started May 30 02:32:56 PM PDT 24
Finished May 30 02:32:58 PM PDT 24
Peak memory 205220 kb
Host smart-dfdbca79-8704-4e04-9b45-f7e5c71ee58d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229407496 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.4
229407496
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.4021352633
Short name T233
Test name
Test status
Simulation time 90270751 ps
CPU time 0.76 seconds
Started May 30 02:32:49 PM PDT 24
Finished May 30 02:32:52 PM PDT 24
Peak memory 205320 kb
Host smart-ad19006c-7c36-46b4-9bfe-baa85d0cba76
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021352633 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.4021352633
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.2534855747
Short name T266
Test name
Test status
Simulation time 193649577 ps
CPU time 0.93 seconds
Started May 30 02:32:52 PM PDT 24
Finished May 30 02:32:56 PM PDT 24
Peak memory 205252 kb
Host smart-59e7e6af-aa82-4793-bd18-584884ff3599
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534855747 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.2534855747
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.712425813
Short name T294
Test name
Test status
Simulation time 4399899233 ps
CPU time 4.52 seconds
Started May 30 02:32:51 PM PDT 24
Finished May 30 02:32:59 PM PDT 24
Peak memory 205816 kb
Host smart-abbfd058-0483-4357-9e6e-a783aaf8c6a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712425813 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_c
sr_outstanding.712425813
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.638788998
Short name T47
Test name
Test status
Simulation time 562572099 ps
CPU time 5.59 seconds
Started May 30 02:32:49 PM PDT 24
Finished May 30 02:32:56 PM PDT 24
Peak memory 213948 kb
Host smart-a6d7f22c-c2ec-4277-9eb1-8c57c936101e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638788998 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.638788998
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.946574152
Short name T85
Test name
Test status
Simulation time 1921072422 ps
CPU time 8.78 seconds
Started May 30 02:32:54 PM PDT 24
Finished May 30 02:33:06 PM PDT 24
Peak memory 213824 kb
Host smart-2c05a844-a9a4-4f6c-9353-c6e56ab1b4da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946574152 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.946574152
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3560074687
Short name T343
Test name
Test status
Simulation time 3432503040 ps
CPU time 10.32 seconds
Started May 30 02:33:03 PM PDT 24
Finished May 30 02:33:16 PM PDT 24
Peak memory 222096 kb
Host smart-63a6cae3-d5a3-446f-bf25-d833de08fdb8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560074687 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.3560074687
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.2824744319
Short name T92
Test name
Test status
Simulation time 74565116 ps
CPU time 1.58 seconds
Started May 30 02:33:01 PM PDT 24
Finished May 30 02:33:04 PM PDT 24
Peak memory 213792 kb
Host smart-8f42d854-d2ca-4aaa-8629-9bf6265a6e00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824744319 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.2824744319
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3926596666
Short name T337
Test name
Test status
Simulation time 4014596691 ps
CPU time 2.37 seconds
Started May 30 02:33:04 PM PDT 24
Finished May 30 02:33:09 PM PDT 24
Peak memory 205644 kb
Host smart-bb97db79-79cf-48df-9f22-ef10318ca4c4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926596666 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
3926596666
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.3436922937
Short name T244
Test name
Test status
Simulation time 296742565 ps
CPU time 1.05 seconds
Started May 30 02:33:06 PM PDT 24
Finished May 30 02:33:10 PM PDT 24
Peak memory 205292 kb
Host smart-367f047a-9df9-44cb-af66-da0ef4fa0425
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436922937 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
3436922937
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3908776669
Short name T305
Test name
Test status
Simulation time 207864306 ps
CPU time 3.71 seconds
Started May 30 02:33:00 PM PDT 24
Finished May 30 02:33:05 PM PDT 24
Peak memory 205584 kb
Host smart-9c5d7007-e32e-4ce5-9990-82fb6e042224
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908776669 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.3908776669
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.4138899908
Short name T261
Test name
Test status
Simulation time 173848735 ps
CPU time 4.1 seconds
Started May 30 02:33:02 PM PDT 24
Finished May 30 02:33:07 PM PDT 24
Peak memory 213916 kb
Host smart-83a6f3df-e6f0-47fc-a4d6-552bb8f144b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138899908 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.4138899908
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2624539764
Short name T268
Test name
Test status
Simulation time 1808610050 ps
CPU time 12.13 seconds
Started May 30 02:33:07 PM PDT 24
Finished May 30 02:33:22 PM PDT 24
Peak memory 213872 kb
Host smart-9201fd0e-cb2a-4f7d-a7a3-ad88f9c90fea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624539764 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.2
624539764
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.209280633
Short name T339
Test name
Test status
Simulation time 264303877 ps
CPU time 3.09 seconds
Started May 30 02:33:01 PM PDT 24
Finished May 30 02:33:06 PM PDT 24
Peak memory 219172 kb
Host smart-ef671acd-3278-4338-b90a-f1876785e031
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209280633 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.209280633
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.3870804782
Short name T267
Test name
Test status
Simulation time 358838669 ps
CPU time 1.65 seconds
Started May 30 02:33:02 PM PDT 24
Finished May 30 02:33:06 PM PDT 24
Peak memory 213768 kb
Host smart-124a785a-7706-4470-9e98-668e024f5769
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870804782 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.3870804782
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.1882160973
Short name T238
Test name
Test status
Simulation time 17515111430 ps
CPU time 17.15 seconds
Started May 30 02:32:59 PM PDT 24
Finished May 30 02:33:18 PM PDT 24
Peak memory 205580 kb
Host smart-42333a99-a28b-4ac1-87d8-12d8ec247698
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882160973 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
1882160973
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.1400320527
Short name T248
Test name
Test status
Simulation time 1208530825 ps
CPU time 3.76 seconds
Started May 30 02:33:04 PM PDT 24
Finished May 30 02:33:12 PM PDT 24
Peak memory 205288 kb
Host smart-1b538e3d-02ca-4adf-bdc7-7c4715e13e52
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400320527 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.
1400320527
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.123658201
Short name T333
Test name
Test status
Simulation time 6283810843 ps
CPU time 10.06 seconds
Started May 30 02:32:59 PM PDT 24
Finished May 30 02:33:11 PM PDT 24
Peak memory 205784 kb
Host smart-d73b40d1-9fa3-4424-bbdc-f614882097f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123658201 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same_
csr_outstanding.123658201
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.3776130033
Short name T265
Test name
Test status
Simulation time 310984474 ps
CPU time 4.6 seconds
Started May 30 02:33:07 PM PDT 24
Finished May 30 02:33:14 PM PDT 24
Peak memory 222112 kb
Host smart-99f9b9d6-df1b-472c-97ba-c9c58078081f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776130033 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.3776130033
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.315025431
Short name T263
Test name
Test status
Simulation time 5489424603 ps
CPU time 5.79 seconds
Started May 30 02:33:06 PM PDT 24
Finished May 30 02:33:15 PM PDT 24
Peak memory 222232 kb
Host smart-62de383f-0cce-41d0-a2f1-7258c4f98b27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315025431 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.315025431
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.143431387
Short name T314
Test name
Test status
Simulation time 282274186 ps
CPU time 1.68 seconds
Started May 30 02:33:04 PM PDT 24
Finished May 30 02:33:09 PM PDT 24
Peak memory 213868 kb
Host smart-01028853-1757-4575-b5f8-a0be1fd2b012
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143431387 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.143431387
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.403444888
Short name T293
Test name
Test status
Simulation time 2465130052 ps
CPU time 4.81 seconds
Started May 30 02:33:07 PM PDT 24
Finished May 30 02:33:15 PM PDT 24
Peak memory 205612 kb
Host smart-90fc1347-14eb-45e7-906e-d38cf772f0da
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403444888 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.403444888
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3610956046
Short name T307
Test name
Test status
Simulation time 278720206 ps
CPU time 1.04 seconds
Started May 30 02:33:02 PM PDT 24
Finished May 30 02:33:04 PM PDT 24
Peak memory 205296 kb
Host smart-a7014919-4996-4de8-ad7e-7590f52ba3c4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610956046 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
3610956046
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3477261135
Short name T110
Test name
Test status
Simulation time 311481744 ps
CPU time 3.74 seconds
Started May 30 02:33:04 PM PDT 24
Finished May 30 02:33:11 PM PDT 24
Peak memory 205604 kb
Host smart-4405b4f1-3edf-4912-92ed-5b5e36fe24ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477261135 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.3477261135
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.3832677835
Short name T70
Test name
Test status
Simulation time 399190606 ps
CPU time 3.85 seconds
Started May 30 02:33:07 PM PDT 24
Finished May 30 02:33:14 PM PDT 24
Peak memory 213968 kb
Host smart-19216c20-d7e0-49c6-9ba9-104d03c406ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832677835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.3832677835
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3755040765
Short name T125
Test name
Test status
Simulation time 2408651694 ps
CPU time 22.27 seconds
Started May 30 02:33:04 PM PDT 24
Finished May 30 02:33:30 PM PDT 24
Peak memory 213896 kb
Host smart-4d19b6b2-602d-41fb-92ab-7907dae78ebe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755040765 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.3
755040765
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.3333743820
Short name T241
Test name
Test status
Simulation time 58882969 ps
CPU time 1.51 seconds
Started May 30 02:33:04 PM PDT 24
Finished May 30 02:33:08 PM PDT 24
Peak memory 213828 kb
Host smart-6d325837-0e92-4347-ad6b-991d56afb9b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333743820 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.3333743820
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.1633268391
Short name T252
Test name
Test status
Simulation time 3908900309 ps
CPU time 6.16 seconds
Started May 30 02:33:02 PM PDT 24
Finished May 30 02:33:09 PM PDT 24
Peak memory 205624 kb
Host smart-8a34d9e5-9007-4b88-8cd7-5261d7f6cc44
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633268391 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
1633268391
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.511959930
Short name T338
Test name
Test status
Simulation time 280491049 ps
CPU time 0.83 seconds
Started May 30 02:33:07 PM PDT 24
Finished May 30 02:33:11 PM PDT 24
Peak memory 205304 kb
Host smart-80cdced9-b4b9-4636-9dc4-5737bce0fe25
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511959930 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.511959930
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.3889720561
Short name T91
Test name
Test status
Simulation time 267697688 ps
CPU time 4.18 seconds
Started May 30 02:33:02 PM PDT 24
Finished May 30 02:33:08 PM PDT 24
Peak memory 205704 kb
Host smart-111eb343-1d6c-408f-9cab-d99e1502b1f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889720561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.3889720561
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2317049743
Short name T120
Test name
Test status
Simulation time 110328539 ps
CPU time 2.11 seconds
Started May 30 02:33:08 PM PDT 24
Finished May 30 02:33:13 PM PDT 24
Peak memory 213404 kb
Host smart-5b53c3e2-5ffc-448f-aca3-273d0237b8f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317049743 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.2317049743
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3135118062
Short name T310
Test name
Test status
Simulation time 1889751160 ps
CPU time 2.4 seconds
Started May 30 02:33:06 PM PDT 24
Finished May 30 02:33:12 PM PDT 24
Peak memory 217592 kb
Host smart-9c4ffcd4-d817-499c-a95a-888587d1b9ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135118062 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.3135118062
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.1016658736
Short name T77
Test name
Test status
Simulation time 126500674 ps
CPU time 1.73 seconds
Started May 30 02:33:05 PM PDT 24
Finished May 30 02:33:10 PM PDT 24
Peak memory 213836 kb
Host smart-050a4549-229c-48c9-bf01-1975a92275d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016658736 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.1016658736
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2456241616
Short name T250
Test name
Test status
Simulation time 2372474068 ps
CPU time 7.78 seconds
Started May 30 02:33:09 PM PDT 24
Finished May 30 02:33:19 PM PDT 24
Peak memory 205480 kb
Host smart-a459202c-9de5-4764-936c-25560bbcd126
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456241616 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
2456241616
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2701617384
Short name T309
Test name
Test status
Simulation time 269693480 ps
CPU time 0.71 seconds
Started May 30 02:33:09 PM PDT 24
Finished May 30 02:33:13 PM PDT 24
Peak memory 205228 kb
Host smart-33bd0d4d-c03b-4f76-925d-7aac3e00bba8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701617384 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
2701617384
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3908744125
Short name T111
Test name
Test status
Simulation time 357867179 ps
CPU time 4.65 seconds
Started May 30 02:33:06 PM PDT 24
Finished May 30 02:33:14 PM PDT 24
Peak memory 205624 kb
Host smart-8025a6f6-600d-4102-b647-0aab7abcbf91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908744125 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.3908744125
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.3541137875
Short name T116
Test name
Test status
Simulation time 1433950869 ps
CPU time 3.2 seconds
Started May 30 02:33:06 PM PDT 24
Finished May 30 02:33:12 PM PDT 24
Peak memory 213936 kb
Host smart-1d3051b3-e39f-4d8d-9c83-9663a010a9e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541137875 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.3541137875
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1909353067
Short name T289
Test name
Test status
Simulation time 2606956319 ps
CPU time 23.61 seconds
Started May 30 02:33:04 PM PDT 24
Finished May 30 02:33:31 PM PDT 24
Peak memory 214040 kb
Host smart-e378db0c-4b94-4b0f-a417-63b43b0c40b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909353067 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.1
909353067
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.2203287825
Short name T277
Test name
Test status
Simulation time 5403032570 ps
CPU time 5.02 seconds
Started May 30 02:33:05 PM PDT 24
Finished May 30 02:33:13 PM PDT 24
Peak memory 221400 kb
Host smart-91e754ae-4006-49df-a585-90e208b34c44
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203287825 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.2203287825
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.543630598
Short name T93
Test name
Test status
Simulation time 85603504 ps
CPU time 1.52 seconds
Started May 30 02:33:05 PM PDT 24
Finished May 30 02:33:10 PM PDT 24
Peak memory 213264 kb
Host smart-a481ee7e-9b30-45be-ac4c-f3c0a073e030
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543630598 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.543630598
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1891282072
Short name T228
Test name
Test status
Simulation time 4466679381 ps
CPU time 13.08 seconds
Started May 30 02:33:08 PM PDT 24
Finished May 30 02:33:24 PM PDT 24
Peak memory 204984 kb
Host smart-132a4ad3-06e1-4431-8889-9147529f82cf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891282072 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
1891282072
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.1533568794
Short name T62
Test name
Test status
Simulation time 455668470 ps
CPU time 1.87 seconds
Started May 30 02:33:08 PM PDT 24
Finished May 30 02:33:13 PM PDT 24
Peak memory 205204 kb
Host smart-c213befa-99cc-400d-a1c9-aff95ea3a298
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533568794 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
1533568794
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.4218625692
Short name T81
Test name
Test status
Simulation time 254173792 ps
CPU time 4.2 seconds
Started May 30 02:33:03 PM PDT 24
Finished May 30 02:33:10 PM PDT 24
Peak memory 205668 kb
Host smart-774c8f97-32c5-4792-8b12-6f23453498b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218625692 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.4218625692
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.74196689
Short name T283
Test name
Test status
Simulation time 156371658 ps
CPU time 3.53 seconds
Started May 30 02:33:06 PM PDT 24
Finished May 30 02:33:12 PM PDT 24
Peak memory 213856 kb
Host smart-151769b1-aa64-4cda-8364-acb601961bf3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74196689 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.74196689
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3885112635
Short name T83
Test name
Test status
Simulation time 2833597276 ps
CPU time 15.15 seconds
Started May 30 02:33:06 PM PDT 24
Finished May 30 02:33:25 PM PDT 24
Peak memory 213936 kb
Host smart-3426a49f-21ec-4d1d-908c-bf2338c8a546
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885112635 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.3
885112635
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2439907635
Short name T275
Test name
Test status
Simulation time 2472423464 ps
CPU time 4.03 seconds
Started May 30 02:33:17 PM PDT 24
Finished May 30 02:33:24 PM PDT 24
Peak memory 215560 kb
Host smart-64a467f5-defd-4809-a54f-82cf0933f798
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439907635 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.2439907635
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.1375011475
Short name T97
Test name
Test status
Simulation time 272112610 ps
CPU time 2.49 seconds
Started May 30 02:33:15 PM PDT 24
Finished May 30 02:33:20 PM PDT 24
Peak memory 213844 kb
Host smart-d065f817-27d9-4b35-844c-49726e31abeb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375011475 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.1375011475
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2285996633
Short name T341
Test name
Test status
Simulation time 5721994889 ps
CPU time 15.68 seconds
Started May 30 02:33:05 PM PDT 24
Finished May 30 02:33:24 PM PDT 24
Peak memory 204996 kb
Host smart-4ac1692c-cc0d-4618-bd5e-860712db9f11
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285996633 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
2285996633
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.1174224319
Short name T346
Test name
Test status
Simulation time 321995721 ps
CPU time 0.83 seconds
Started May 30 02:33:08 PM PDT 24
Finished May 30 02:33:11 PM PDT 24
Peak memory 205228 kb
Host smart-e0788f3b-5e04-46c1-894d-8bec561bded6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174224319 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
1174224319
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3127710991
Short name T298
Test name
Test status
Simulation time 610785869 ps
CPU time 8.15 seconds
Started May 30 02:33:22 PM PDT 24
Finished May 30 02:33:35 PM PDT 24
Peak memory 205656 kb
Host smart-06f409d4-2929-4220-9a09-c7e60bac32be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127710991 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.3127710991
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.326808044
Short name T336
Test name
Test status
Simulation time 347901390 ps
CPU time 4.35 seconds
Started May 30 02:33:06 PM PDT 24
Finished May 30 02:33:13 PM PDT 24
Peak memory 213964 kb
Host smart-17f86487-53b6-4c19-95a6-ab79e0faa2d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326808044 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.326808044
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.1547934192
Short name T321
Test name
Test status
Simulation time 3647464899 ps
CPU time 10.83 seconds
Started May 30 02:33:06 PM PDT 24
Finished May 30 02:33:20 PM PDT 24
Peak memory 213960 kb
Host smart-4d637b2a-c650-4465-b2e2-3b4920d5dfcc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547934192 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.1
547934192
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.1736574472
Short name T121
Test name
Test status
Simulation time 98664927 ps
CPU time 2.96 seconds
Started May 30 02:33:23 PM PDT 24
Finished May 30 02:33:31 PM PDT 24
Peak memory 218300 kb
Host smart-dff3716a-d011-4c90-bf1f-5f2a9ddeea4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736574472 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.1736574472
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.2422089687
Short name T325
Test name
Test status
Simulation time 444413262 ps
CPU time 2.23 seconds
Started May 30 02:33:17 PM PDT 24
Finished May 30 02:33:23 PM PDT 24
Peak memory 213792 kb
Host smart-b83cb228-7780-4a1e-941f-bd3933df8caa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422089687 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.2422089687
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.1488748548
Short name T344
Test name
Test status
Simulation time 15793190767 ps
CPU time 46.71 seconds
Started May 30 02:33:18 PM PDT 24
Finished May 30 02:34:08 PM PDT 24
Peak memory 205592 kb
Host smart-34cf47c0-1d1d-4867-b449-848ab84f272a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488748548 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
1488748548
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.3922724216
Short name T334
Test name
Test status
Simulation time 456467686 ps
CPU time 1.93 seconds
Started May 30 02:33:18 PM PDT 24
Finished May 30 02:33:24 PM PDT 24
Peak memory 205296 kb
Host smart-42ad2169-d479-4fcb-a8dc-5f7aed321a65
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922724216 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
3922724216
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.1301220149
Short name T49
Test name
Test status
Simulation time 412517852 ps
CPU time 7.39 seconds
Started May 30 02:33:16 PM PDT 24
Finished May 30 02:33:27 PM PDT 24
Peak memory 205684 kb
Host smart-f93f35a8-a632-431e-b3d9-0d269796a33f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301220149 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.1301220149
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.114288067
Short name T281
Test name
Test status
Simulation time 258642969 ps
CPU time 4.85 seconds
Started May 30 02:33:16 PM PDT 24
Finished May 30 02:33:24 PM PDT 24
Peak memory 213896 kb
Host smart-98412e88-7b23-46e3-91ba-cb25d37b9da5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114288067 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.114288067
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2252709397
Short name T45
Test name
Test status
Simulation time 1095794369 ps
CPU time 9.48 seconds
Started May 30 02:33:17 PM PDT 24
Finished May 30 02:33:30 PM PDT 24
Peak memory 213860 kb
Host smart-d277e5ca-cf1b-454e-a9da-3d118712f205
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252709397 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.2
252709397
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.445332062
Short name T65
Test name
Test status
Simulation time 4142696218 ps
CPU time 5.73 seconds
Started May 30 02:33:17 PM PDT 24
Finished May 30 02:33:26 PM PDT 24
Peak memory 221812 kb
Host smart-090c444f-54cb-43ee-a28e-b39fa8086be7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445332062 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.445332062
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.3872806443
Short name T290
Test name
Test status
Simulation time 670980266 ps
CPU time 2.49 seconds
Started May 30 02:33:18 PM PDT 24
Finished May 30 02:33:25 PM PDT 24
Peak memory 213760 kb
Host smart-909b7c15-711d-4a31-983e-cf7daf562d77
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872806443 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.3872806443
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.790915559
Short name T230
Test name
Test status
Simulation time 3236543334 ps
CPU time 6.57 seconds
Started May 30 02:33:21 PM PDT 24
Finished May 30 02:33:34 PM PDT 24
Peak memory 205576 kb
Host smart-84e31800-0194-4f67-8c43-a0b0362f823f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790915559 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.790915559
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2288742454
Short name T64
Test name
Test status
Simulation time 173664692 ps
CPU time 1.16 seconds
Started May 30 02:33:21 PM PDT 24
Finished May 30 02:33:27 PM PDT 24
Peak memory 205272 kb
Host smart-d670e3d1-82e9-4e2b-963f-5972b855bbbb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288742454 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
2288742454
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1816105204
Short name T107
Test name
Test status
Simulation time 476526958 ps
CPU time 6.58 seconds
Started May 30 02:33:22 PM PDT 24
Finished May 30 02:33:34 PM PDT 24
Peak memory 205588 kb
Host smart-e537b8f2-6d75-430c-947a-98d2449acba8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816105204 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.1816105204
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.3413339204
Short name T316
Test name
Test status
Simulation time 1162322665 ps
CPU time 6.49 seconds
Started May 30 02:33:19 PM PDT 24
Finished May 30 02:33:30 PM PDT 24
Peak memory 213972 kb
Host smart-0ed0aa3d-0208-4a1d-9e1c-e776ab60d2e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413339204 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.3413339204
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.1236025781
Short name T347
Test name
Test status
Simulation time 2426111847 ps
CPU time 9.6 seconds
Started May 30 02:33:21 PM PDT 24
Finished May 30 02:33:36 PM PDT 24
Peak memory 214008 kb
Host smart-34fdb23c-6056-4ec9-8274-be2a91a76f57
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236025781 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.1
236025781
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.2790231766
Short name T115
Test name
Test status
Simulation time 886155513 ps
CPU time 1.77 seconds
Started May 30 02:33:16 PM PDT 24
Finished May 30 02:33:21 PM PDT 24
Peak memory 213776 kb
Host smart-ba4ce014-ca9c-4a9b-bccd-b9aa04bfa21c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790231766 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.2790231766
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.172382264
Short name T234
Test name
Test status
Simulation time 13080735762 ps
CPU time 18.59 seconds
Started May 30 02:33:18 PM PDT 24
Finished May 30 02:33:40 PM PDT 24
Peak memory 205604 kb
Host smart-fc2fb99f-0a66-4a6c-b51b-2b44b1481ec9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172382264 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.172382264
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.1344107837
Short name T235
Test name
Test status
Simulation time 813836228 ps
CPU time 1.77 seconds
Started May 30 02:33:18 PM PDT 24
Finished May 30 02:33:23 PM PDT 24
Peak memory 205300 kb
Host smart-cd56a00a-73c2-4ef7-9ec3-13ca40f323ad
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344107837 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
1344107837
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.128166105
Short name T259
Test name
Test status
Simulation time 995921124 ps
CPU time 7.93 seconds
Started May 30 02:33:18 PM PDT 24
Finished May 30 02:33:29 PM PDT 24
Peak memory 205640 kb
Host smart-d6be1675-1961-4b5a-a613-281dbc6a9393
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128166105 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same_
csr_outstanding.128166105
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.2570862724
Short name T255
Test name
Test status
Simulation time 229679148 ps
CPU time 4.8 seconds
Started May 30 02:33:19 PM PDT 24
Finished May 30 02:33:28 PM PDT 24
Peak memory 213948 kb
Host smart-98ba88ab-c220-4755-bced-d190942e4b3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570862724 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.2570862724
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.1663804662
Short name T72
Test name
Test status
Simulation time 8562399697 ps
CPU time 21.9 seconds
Started May 30 02:33:20 PM PDT 24
Finished May 30 02:33:47 PM PDT 24
Peak memory 214020 kb
Host smart-5b4cb49a-bbba-45d8-8f96-36bff9f8eefd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663804662 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.1
663804662
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.3771372150
Short name T75
Test name
Test status
Simulation time 13196908796 ps
CPU time 72.79 seconds
Started May 30 02:32:50 PM PDT 24
Finished May 30 02:34:05 PM PDT 24
Peak memory 213920 kb
Host smart-1f30c46c-8c51-4356-b2dc-6f1e76cde52f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771372150 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.3771372150
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.763599523
Short name T50
Test name
Test status
Simulation time 277505062 ps
CPU time 1.67 seconds
Started May 30 02:32:47 PM PDT 24
Finished May 30 02:32:50 PM PDT 24
Peak memory 213828 kb
Host smart-7a141e0f-eada-40be-9df0-415a2010f916
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763599523 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.763599523
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.2672208810
Short name T71
Test name
Test status
Simulation time 138109878 ps
CPU time 2.62 seconds
Started May 30 02:32:56 PM PDT 24
Finished May 30 02:33:00 PM PDT 24
Peak memory 218428 kb
Host smart-9585e97a-c434-4150-b518-a3f0bc5cbed1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672208810 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.2672208810
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.2829505128
Short name T301
Test name
Test status
Simulation time 47390716 ps
CPU time 1.58 seconds
Started May 30 02:32:52 PM PDT 24
Finished May 30 02:32:56 PM PDT 24
Peak memory 213748 kb
Host smart-2557a4b9-bee2-4959-858f-344370800953
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829505128 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.2829505128
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.4273832061
Short name T229
Test name
Test status
Simulation time 30966756863 ps
CPU time 58.84 seconds
Started May 30 02:32:52 PM PDT 24
Finished May 30 02:33:54 PM PDT 24
Peak memory 205580 kb
Host smart-0f199e35-0c46-4f18-87c5-ae10a6c86d4d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273832061 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.4273832061
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.3622435995
Short name T87
Test name
Test status
Simulation time 11143071867 ps
CPU time 4.29 seconds
Started May 30 02:32:46 PM PDT 24
Finished May 30 02:32:52 PM PDT 24
Peak memory 205760 kb
Host smart-6140f002-1dec-4c2a-b1bd-0ac485118bba
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622435995 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.3622435995
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1002314797
Short name T280
Test name
Test status
Simulation time 2695726230 ps
CPU time 8.85 seconds
Started May 30 02:32:51 PM PDT 24
Finished May 30 02:33:03 PM PDT 24
Peak memory 205624 kb
Host smart-b84a0def-7678-432d-af9f-8fc5cde96de7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002314797 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.1
002314797
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3811009751
Short name T262
Test name
Test status
Simulation time 1897930995 ps
CPU time 1.78 seconds
Started May 30 02:32:48 PM PDT 24
Finished May 30 02:32:51 PM PDT 24
Peak memory 205288 kb
Host smart-476cfa20-7d28-4dab-8226-931b9afe8c4b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811009751 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_aliasing.3811009751
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.145667293
Short name T251
Test name
Test status
Simulation time 29460950935 ps
CPU time 74.68 seconds
Started May 30 02:32:51 PM PDT 24
Finished May 30 02:34:08 PM PDT 24
Peak memory 205560 kb
Host smart-7a2cd469-6e57-427f-866a-9976886e36d2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145667293 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_bit_bash.145667293
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1327993956
Short name T313
Test name
Test status
Simulation time 920719974 ps
CPU time 1.41 seconds
Started May 30 02:32:52 PM PDT 24
Finished May 30 02:32:56 PM PDT 24
Peak memory 205336 kb
Host smart-c1ea09d0-e634-4725-b9e3-9278d394d4e0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327993956 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.1327993956
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.4075961597
Short name T312
Test name
Test status
Simulation time 378084307 ps
CPU time 0.92 seconds
Started May 30 02:32:51 PM PDT 24
Finished May 30 02:32:55 PM PDT 24
Peak memory 205292 kb
Host smart-9a43b53a-12ea-4833-a72d-0661e85989bd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075961597 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.4
075961597
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2238028207
Short name T308
Test name
Test status
Simulation time 110458149 ps
CPU time 0.69 seconds
Started May 30 02:32:52 PM PDT 24
Finished May 30 02:32:55 PM PDT 24
Peak memory 205320 kb
Host smart-93ec9947-1da4-4155-8d74-81f699f29cf5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238028207 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.2238028207
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.3119303898
Short name T242
Test name
Test status
Simulation time 74324116 ps
CPU time 0.73 seconds
Started May 30 02:32:51 PM PDT 24
Finished May 30 02:32:54 PM PDT 24
Peak memory 205280 kb
Host smart-3547f75c-62aa-4df7-983e-f14504016631
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119303898 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.3119303898
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.1871874187
Short name T286
Test name
Test status
Simulation time 387561699 ps
CPU time 5.8 seconds
Started May 30 02:32:48 PM PDT 24
Finished May 30 02:32:55 PM PDT 24
Peak memory 213896 kb
Host smart-4992414f-6046-493e-a6ca-a48f87d65392
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871874187 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.1871874187
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.161649909
Short name T123
Test name
Test status
Simulation time 2594197454 ps
CPU time 20.22 seconds
Started May 30 02:32:45 PM PDT 24
Finished May 30 02:33:06 PM PDT 24
Peak memory 213940 kb
Host smart-72a07f2e-435d-4ae4-8878-5a202d0d20bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161649909 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.161649909
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.76446265
Short name T304
Test name
Test status
Simulation time 1817523046 ps
CPU time 30.83 seconds
Started May 30 02:32:49 PM PDT 24
Finished May 30 02:33:22 PM PDT 24
Peak memory 205584 kb
Host smart-18d9d10e-a79a-4e77-9e3a-7dea0c522343
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76446265 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UV
M_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 3.rv_dm_csr_aliasing.76446265
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1902782367
Short name T318
Test name
Test status
Simulation time 11284386015 ps
CPU time 36.41 seconds
Started May 30 02:32:51 PM PDT 24
Finished May 30 02:33:29 PM PDT 24
Peak memory 213888 kb
Host smart-d6c8acb3-84af-490a-b8b1-ef5324b83279
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902782367 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.1902782367
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.3710855311
Short name T103
Test name
Test status
Simulation time 289787646 ps
CPU time 2.49 seconds
Started May 30 02:32:52 PM PDT 24
Finished May 30 02:32:57 PM PDT 24
Peak memory 213856 kb
Host smart-5c0e1a29-7b8b-4228-90a4-f6bbe1c356db
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710855311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.3710855311
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.4205209850
Short name T296
Test name
Test status
Simulation time 2638143806 ps
CPU time 5.18 seconds
Started May 30 02:32:48 PM PDT 24
Finished May 30 02:32:54 PM PDT 24
Peak memory 219896 kb
Host smart-81af8129-7ded-4455-9c52-59682addad37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205209850 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.4205209850
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.3046687160
Short name T99
Test name
Test status
Simulation time 201002527 ps
CPU time 2.42 seconds
Started May 30 02:32:50 PM PDT 24
Finished May 30 02:32:54 PM PDT 24
Peak memory 213852 kb
Host smart-7cb01747-1c99-456a-bddf-ef6d74932800
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046687160 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.3046687160
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.2897940658
Short name T240
Test name
Test status
Simulation time 49469491447 ps
CPU time 36.45 seconds
Started May 30 02:32:49 PM PDT 24
Finished May 30 02:33:27 PM PDT 24
Peak memory 205604 kb
Host smart-1f1e49af-01da-4892-842c-0efe0afad84b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897940658 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.rv_dm_jtag_dmi_csr_bit_bash.2897940658
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.595830382
Short name T260
Test name
Test status
Simulation time 8583672740 ps
CPU time 22.87 seconds
Started May 30 02:32:46 PM PDT 24
Finished May 30 02:33:10 PM PDT 24
Peak memory 205636 kb
Host smart-21d2e95c-8590-4660-a358-3b29d79802ed
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595830382 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr
_hw_reset.595830382
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.2568886645
Short name T249
Test name
Test status
Simulation time 2305353757 ps
CPU time 7.09 seconds
Started May 30 02:32:47 PM PDT 24
Finished May 30 02:32:55 PM PDT 24
Peak memory 205428 kb
Host smart-9ad34e91-0437-46d9-82a3-7e418f07c471
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568886645 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.2
568886645
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3371247835
Short name T295
Test name
Test status
Simulation time 653916296 ps
CPU time 2.56 seconds
Started May 30 02:32:55 PM PDT 24
Finished May 30 02:33:00 PM PDT 24
Peak memory 204420 kb
Host smart-2d1bb6fc-000a-447f-bf3a-294d49c93df9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371247835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.3371247835
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.4221969664
Short name T279
Test name
Test status
Simulation time 48347730671 ps
CPU time 124.16 seconds
Started May 30 02:32:50 PM PDT 24
Finished May 30 02:34:56 PM PDT 24
Peak memory 205584 kb
Host smart-40ea1333-9fae-43f2-8a1e-fb7c2ca9dc6a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221969664 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.4221969664
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1478608318
Short name T335
Test name
Test status
Simulation time 1318998211 ps
CPU time 2.49 seconds
Started May 30 02:32:47 PM PDT 24
Finished May 30 02:32:50 PM PDT 24
Peak memory 205276 kb
Host smart-21c59aa1-2838-4550-a67a-67494c7637a4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478608318 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.1478608318
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2913169198
Short name T311
Test name
Test status
Simulation time 1336793538 ps
CPU time 1.57 seconds
Started May 30 02:32:54 PM PDT 24
Finished May 30 02:32:58 PM PDT 24
Peak memory 205272 kb
Host smart-422fe51a-fde9-4740-875b-e29da282b78b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913169198 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.2
913169198
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.1226672136
Short name T306
Test name
Test status
Simulation time 116855075 ps
CPU time 0.72 seconds
Started May 30 02:32:55 PM PDT 24
Finished May 30 02:32:58 PM PDT 24
Peak memory 204572 kb
Host smart-4132cefc-5413-4f7a-9f00-4390875708d1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226672136 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.1226672136
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.2149245321
Short name T236
Test name
Test status
Simulation time 77564806 ps
CPU time 0.72 seconds
Started May 30 02:32:50 PM PDT 24
Finished May 30 02:32:52 PM PDT 24
Peak memory 205276 kb
Host smart-d4901ca5-e4f5-4b53-b9fa-24f2cd4328df
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149245321 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.2149245321
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.1845035268
Short name T106
Test name
Test status
Simulation time 1008468401 ps
CPU time 4.29 seconds
Started May 30 02:32:46 PM PDT 24
Finished May 30 02:32:51 PM PDT 24
Peak memory 205688 kb
Host smart-cb9f85f3-baa5-4054-8bf8-ac991c821afc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845035268 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.1845035268
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.4131362277
Short name T270
Test name
Test status
Simulation time 269925931 ps
CPU time 5.36 seconds
Started May 30 02:32:52 PM PDT 24
Finished May 30 02:33:00 PM PDT 24
Peak memory 213976 kb
Host smart-f2fcfe5d-669c-43a3-a7a4-608b96707c86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131362277 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.4131362277
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3639199584
Short name T114
Test name
Test status
Simulation time 7920263681 ps
CPU time 23.65 seconds
Started May 30 02:32:49 PM PDT 24
Finished May 30 02:33:14 PM PDT 24
Peak memory 213952 kb
Host smart-a4c24f00-07e8-4cc5-9264-9bf263f9e118
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639199584 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.3639199584
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.3847083946
Short name T282
Test name
Test status
Simulation time 3103932557 ps
CPU time 25.91 seconds
Started May 30 02:32:52 PM PDT 24
Finished May 30 02:33:22 PM PDT 24
Peak memory 213920 kb
Host smart-94182a53-3d60-45aa-ab7c-54dc0683b6e0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847083946 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.3847083946
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.854708118
Short name T89
Test name
Test status
Simulation time 13214876361 ps
CPU time 38.36 seconds
Started May 30 02:32:53 PM PDT 24
Finished May 30 02:33:34 PM PDT 24
Peak memory 213908 kb
Host smart-72a19c92-6256-4396-97bf-b45ba1e1bc29
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854708118 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.854708118
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.1531003891
Short name T319
Test name
Test status
Simulation time 171602420 ps
CPU time 2.05 seconds
Started May 30 02:32:51 PM PDT 24
Finished May 30 02:32:56 PM PDT 24
Peak memory 213692 kb
Host smart-e9463b88-55c9-4bcf-b039-4e6b59e0fd24
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531003891 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.1531003891
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.3650784569
Short name T285
Test name
Test status
Simulation time 3345104644 ps
CPU time 5.24 seconds
Started May 30 02:32:53 PM PDT 24
Finished May 30 02:33:01 PM PDT 24
Peak memory 220772 kb
Host smart-1e50278e-a030-4b4d-8044-e493055bddb6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650784569 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.3650784569
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.3588064074
Short name T102
Test name
Test status
Simulation time 345559292 ps
CPU time 1.68 seconds
Started May 30 02:32:51 PM PDT 24
Finished May 30 02:32:55 PM PDT 24
Peak memory 213796 kb
Host smart-2e3b10de-00dd-4017-81cf-c2ffa7840815
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588064074 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.3588064074
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.1862684763
Short name T274
Test name
Test status
Simulation time 4561339725 ps
CPU time 4.25 seconds
Started May 30 02:32:51 PM PDT 24
Finished May 30 02:32:58 PM PDT 24
Peak memory 205616 kb
Host smart-e61cb377-1ff6-4ed7-b9f5-edc051f73148
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862684763 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.1862684763
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.1627843674
Short name T237
Test name
Test status
Simulation time 1022370882 ps
CPU time 1.54 seconds
Started May 30 02:32:49 PM PDT 24
Finished May 30 02:32:53 PM PDT 24
Peak memory 205488 kb
Host smart-58f9f854-3630-4064-8e83-3e2610bc3457
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627843674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.1
627843674
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.4005350835
Short name T326
Test name
Test status
Simulation time 2373536260 ps
CPU time 2.61 seconds
Started May 30 02:32:50 PM PDT 24
Finished May 30 02:32:54 PM PDT 24
Peak memory 205404 kb
Host smart-2cf19435-0ba2-4d52-bd94-fd8462356adb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005350835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.4005350835
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.1021038843
Short name T300
Test name
Test status
Simulation time 4476456965 ps
CPU time 4.89 seconds
Started May 30 02:32:52 PM PDT 24
Finished May 30 02:32:59 PM PDT 24
Peak memory 205584 kb
Host smart-75a95418-9ddd-4998-8335-9d5b0e6b8611
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021038843 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.1021038843
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2908124772
Short name T332
Test name
Test status
Simulation time 476290177 ps
CPU time 1.02 seconds
Started May 30 02:32:50 PM PDT 24
Finished May 30 02:32:53 PM PDT 24
Peak memory 205380 kb
Host smart-1a707cb7-65c7-4afb-966a-78004021bcf8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908124772 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.2908124772
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.3779961134
Short name T243
Test name
Test status
Simulation time 168475222 ps
CPU time 1.09 seconds
Started May 30 02:32:52 PM PDT 24
Finished May 30 02:32:56 PM PDT 24
Peak memory 205264 kb
Host smart-c8ee6da0-6312-419c-abba-f22a10ef1618
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779961134 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.3
779961134
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1166129742
Short name T254
Test name
Test status
Simulation time 106141748 ps
CPU time 0.87 seconds
Started May 30 02:32:56 PM PDT 24
Finished May 30 02:32:58 PM PDT 24
Peak memory 205352 kb
Host smart-72d9f2c6-71f8-457f-bd2a-23a7710b9f58
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166129742 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.1166129742
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.2781976928
Short name T278
Test name
Test status
Simulation time 91490870 ps
CPU time 0.89 seconds
Started May 30 02:32:49 PM PDT 24
Finished May 30 02:32:51 PM PDT 24
Peak memory 205288 kb
Host smart-aaf34d06-8a48-45f5-a988-d644d4d81ecc
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781976928 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.2781976928
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.2961120445
Short name T258
Test name
Test status
Simulation time 403981531 ps
CPU time 7.26 seconds
Started May 30 02:32:52 PM PDT 24
Finished May 30 02:33:02 PM PDT 24
Peak memory 205644 kb
Host smart-4006b5b2-ac86-4695-8dc0-71d4ed56a5d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961120445 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.2961120445
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2683910063
Short name T73
Test name
Test status
Simulation time 322993766 ps
CPU time 3.25 seconds
Started May 30 02:32:53 PM PDT 24
Finished May 30 02:32:59 PM PDT 24
Peak memory 213972 kb
Host smart-da373e1d-c446-4296-a117-6535236c2db6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683910063 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.2683910063
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.3327064334
Short name T127
Test name
Test status
Simulation time 1280344355 ps
CPU time 16.22 seconds
Started May 30 02:32:52 PM PDT 24
Finished May 30 02:33:12 PM PDT 24
Peak memory 221588 kb
Host smart-3e0294c5-8f13-4d78-831b-8f72d0984a61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327064334 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.3327064334
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.1205894893
Short name T66
Test name
Test status
Simulation time 156508048 ps
CPU time 2.39 seconds
Started May 30 02:32:52 PM PDT 24
Finished May 30 02:32:57 PM PDT 24
Peak memory 218012 kb
Host smart-79a95e0f-97f7-479c-b2a0-777644bdf2d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205894893 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.1205894893
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.3273281313
Short name T78
Test name
Test status
Simulation time 221758584 ps
CPU time 1.55 seconds
Started May 30 02:32:52 PM PDT 24
Finished May 30 02:32:57 PM PDT 24
Peak memory 213804 kb
Host smart-2466764a-ba2e-41c9-8a10-f5661ba5843f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273281313 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.3273281313
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3236965911
Short name T345
Test name
Test status
Simulation time 1969248638 ps
CPU time 2.63 seconds
Started May 30 02:33:00 PM PDT 24
Finished May 30 02:33:04 PM PDT 24
Peak memory 205432 kb
Host smart-0b8aa5ec-2646-4384-917a-4703ff2ac2ee
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236965911 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.3
236965911
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.2007945745
Short name T271
Test name
Test status
Simulation time 770802706 ps
CPU time 2.73 seconds
Started May 30 02:32:53 PM PDT 24
Finished May 30 02:32:59 PM PDT 24
Peak memory 205272 kb
Host smart-a90586c8-944b-419d-836b-6680f72cd451
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007945745 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.2
007945745
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1645499867
Short name T100
Test name
Test status
Simulation time 247493049 ps
CPU time 3.76 seconds
Started May 30 02:32:53 PM PDT 24
Finished May 30 02:33:00 PM PDT 24
Peak memory 205684 kb
Host smart-623f9304-c6da-4de3-a482-321b3e7993a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645499867 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.1645499867
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.4260522858
Short name T276
Test name
Test status
Simulation time 934833992 ps
CPU time 5.15 seconds
Started May 30 02:32:53 PM PDT 24
Finished May 30 02:33:01 PM PDT 24
Peak memory 213896 kb
Host smart-d7965bad-638c-4f6c-9463-a8a2f5f6f28b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260522858 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.4260522858
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.186261030
Short name T126
Test name
Test status
Simulation time 5478280426 ps
CPU time 24.77 seconds
Started May 30 02:32:56 PM PDT 24
Finished May 30 02:33:23 PM PDT 24
Peak memory 213912 kb
Host smart-1dd77c9b-eee9-4409-b36f-192be3c5ccc1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186261030 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.186261030
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.1776643276
Short name T291
Test name
Test status
Simulation time 1997913931 ps
CPU time 3 seconds
Started May 30 02:33:00 PM PDT 24
Finished May 30 02:33:04 PM PDT 24
Peak memory 217904 kb
Host smart-8a9f13b6-eb5c-4be2-a427-80747fb10f88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776643276 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.1776643276
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1841954726
Short name T90
Test name
Test status
Simulation time 227320887 ps
CPU time 1.38 seconds
Started May 30 02:33:03 PM PDT 24
Finished May 30 02:33:07 PM PDT 24
Peak memory 213788 kb
Host smart-d53ed322-d640-40d9-a94d-0dba3c0f2b26
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841954726 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.1841954726
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.3962385403
Short name T245
Test name
Test status
Simulation time 5084389509 ps
CPU time 7.95 seconds
Started May 30 02:32:52 PM PDT 24
Finished May 30 02:33:03 PM PDT 24
Peak memory 205568 kb
Host smart-f092905e-849a-4ea4-bd6e-946e36d0c799
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962385403 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.3
962385403
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.1357984352
Short name T273
Test name
Test status
Simulation time 702887600 ps
CPU time 2.62 seconds
Started May 30 02:32:51 PM PDT 24
Finished May 30 02:32:57 PM PDT 24
Peak memory 205288 kb
Host smart-c2fac972-aaa7-45f5-b14d-b50fd8dda37d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357984352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.1
357984352
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2332627309
Short name T256
Test name
Test status
Simulation time 817599692 ps
CPU time 3.97 seconds
Started May 30 02:33:06 PM PDT 24
Finished May 30 02:33:13 PM PDT 24
Peak memory 205700 kb
Host smart-d6934572-582e-4217-b6bc-abb652c4be24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332627309 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.2332627309
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.1752982692
Short name T292
Test name
Test status
Simulation time 221280621 ps
CPU time 4.06 seconds
Started May 30 02:32:54 PM PDT 24
Finished May 30 02:33:01 PM PDT 24
Peak memory 213960 kb
Host smart-42ed481f-26c3-4c11-8ca7-fb11b746abda
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752982692 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.1752982692
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1248484190
Short name T124
Test name
Test status
Simulation time 3627558139 ps
CPU time 23.4 seconds
Started May 30 02:32:58 PM PDT 24
Finished May 30 02:33:23 PM PDT 24
Peak memory 222056 kb
Host smart-d6d8c0b9-e204-4cc0-a268-19fc54e638f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248484190 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.1248484190
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.1054013572
Short name T272
Test name
Test status
Simulation time 503281069 ps
CPU time 2.52 seconds
Started May 30 02:33:06 PM PDT 24
Finished May 30 02:33:12 PM PDT 24
Peak memory 222120 kb
Host smart-9183d721-7010-4996-b947-bb903f4e7f0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054013572 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.1054013572
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.2254435623
Short name T328
Test name
Test status
Simulation time 171301782 ps
CPU time 1.6 seconds
Started May 30 02:32:59 PM PDT 24
Finished May 30 02:33:02 PM PDT 24
Peak memory 213832 kb
Host smart-8bb65c5f-aa2d-4509-b9cf-ed9de5830fab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254435623 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.2254435623
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3976685460
Short name T315
Test name
Test status
Simulation time 8293904099 ps
CPU time 11.84 seconds
Started May 30 02:32:59 PM PDT 24
Finished May 30 02:33:12 PM PDT 24
Peak memory 205592 kb
Host smart-fd0d9c55-5bd5-4cc2-8ed8-842f836e6361
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976685460 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.3
976685460
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1985010516
Short name T288
Test name
Test status
Simulation time 599769655 ps
CPU time 2.47 seconds
Started May 30 02:33:02 PM PDT 24
Finished May 30 02:33:06 PM PDT 24
Peak memory 205268 kb
Host smart-d0d185a1-118b-4792-bef8-16ecd22cccdc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985010516 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.1
985010516
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.660823744
Short name T264
Test name
Test status
Simulation time 568199223 ps
CPU time 7.86 seconds
Started May 30 02:33:02 PM PDT 24
Finished May 30 02:33:12 PM PDT 24
Peak memory 205676 kb
Host smart-38d800a2-1d9b-479b-92fa-6b618457ee23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660823744 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_c
sr_outstanding.660823744
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.1851714849
Short name T317
Test name
Test status
Simulation time 92909958 ps
CPU time 1.93 seconds
Started May 30 02:33:03 PM PDT 24
Finished May 30 02:33:06 PM PDT 24
Peak memory 213912 kb
Host smart-3e16edc3-302f-47af-872a-72748e924e8e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851714849 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.1851714849
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.1387642958
Short name T129
Test name
Test status
Simulation time 1577508741 ps
CPU time 16.45 seconds
Started May 30 02:33:06 PM PDT 24
Finished May 30 02:33:26 PM PDT 24
Peak memory 213832 kb
Host smart-9368f03e-bee7-48f7-be54-66f189f69b51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387642958 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.1387642958
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.34449108
Short name T232
Test name
Test status
Simulation time 3965059265 ps
CPU time 6.29 seconds
Started May 30 02:33:07 PM PDT 24
Finished May 30 02:33:16 PM PDT 24
Peak memory 222212 kb
Host smart-2a089d9e-5f08-4857-bef5-cb9dcd97e0f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34449108 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.34449108
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.2707654289
Short name T101
Test name
Test status
Simulation time 181005274 ps
CPU time 1.86 seconds
Started May 30 02:33:05 PM PDT 24
Finished May 30 02:33:10 PM PDT 24
Peak memory 213756 kb
Host smart-939a9359-2455-42b9-83bf-2cf4cd061503
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707654289 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.2707654289
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1269195714
Short name T327
Test name
Test status
Simulation time 3746319652 ps
CPU time 7.28 seconds
Started May 30 02:33:03 PM PDT 24
Finished May 30 02:33:13 PM PDT 24
Peak memory 205616 kb
Host smart-89b1cbca-fc0f-45b7-be3f-6e24b2a4bb75
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269195714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.1
269195714
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2482279869
Short name T239
Test name
Test status
Simulation time 461638834 ps
CPU time 0.88 seconds
Started May 30 02:33:00 PM PDT 24
Finished May 30 02:33:03 PM PDT 24
Peak memory 205280 kb
Host smart-57d17177-d228-4f3b-b616-515afc417ce8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482279869 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.2
482279869
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.110076561
Short name T98
Test name
Test status
Simulation time 1180514966 ps
CPU time 6.62 seconds
Started May 30 02:33:01 PM PDT 24
Finished May 30 02:33:09 PM PDT 24
Peak memory 205632 kb
Host smart-678a993b-5bc3-42aa-b919-a83945b44ba0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110076561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_c
sr_outstanding.110076561
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.304386588
Short name T323
Test name
Test status
Simulation time 176811327 ps
CPU time 3.14 seconds
Started May 30 02:33:04 PM PDT 24
Finished May 30 02:33:11 PM PDT 24
Peak memory 213976 kb
Host smart-fa8269fb-749b-4e80-9123-69867fd56303
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304386588 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.304386588
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.408644563
Short name T130
Test name
Test status
Simulation time 4834779153 ps
CPU time 25.96 seconds
Started May 30 02:33:01 PM PDT 24
Finished May 30 02:33:28 PM PDT 24
Peak memory 213944 kb
Host smart-02792e8f-58fe-4237-b85f-47a11dbafcc1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408644563 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.408644563
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.1526714817
Short name T269
Test name
Test status
Simulation time 1347810760 ps
CPU time 4.08 seconds
Started May 30 02:33:03 PM PDT 24
Finished May 30 02:33:10 PM PDT 24
Peak memory 213948 kb
Host smart-cc2be77a-a720-488f-aaa8-2834e58b392a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526714817 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.1526714817
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.2668874052
Short name T76
Test name
Test status
Simulation time 164515890 ps
CPU time 2.26 seconds
Started May 30 02:33:02 PM PDT 24
Finished May 30 02:33:06 PM PDT 24
Peak memory 213796 kb
Host smart-4b4fb86b-6ac4-4205-96f5-1ee08b04fde9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668874052 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.2668874052
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.2906766237
Short name T231
Test name
Test status
Simulation time 3317794837 ps
CPU time 9.73 seconds
Started May 30 02:33:04 PM PDT 24
Finished May 30 02:33:17 PM PDT 24
Peak memory 205616 kb
Host smart-3fc2964e-37d5-4736-a85f-6564e6a5562e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906766237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.2
906766237
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.846954026
Short name T330
Test name
Test status
Simulation time 654876101 ps
CPU time 1.11 seconds
Started May 30 02:33:03 PM PDT 24
Finished May 30 02:33:06 PM PDT 24
Peak memory 205288 kb
Host smart-6dff2bb9-c122-4ea5-80af-f66a7691cb07
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846954026 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.846954026
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.3684860333
Short name T109
Test name
Test status
Simulation time 321959916 ps
CPU time 6.55 seconds
Started May 30 02:33:04 PM PDT 24
Finished May 30 02:33:14 PM PDT 24
Peak memory 205728 kb
Host smart-31fd8c46-ab93-40af-b2ed-22cc1fc22809
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684860333 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.3684860333
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.4033508713
Short name T302
Test name
Test status
Simulation time 219061153 ps
CPU time 3.54 seconds
Started May 30 02:33:01 PM PDT 24
Finished May 30 02:33:06 PM PDT 24
Peak memory 213928 kb
Host smart-b21cb9db-7a9d-482b-8193-c35bf1a55385
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033508713 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.4033508713
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.3789056439
Short name T128
Test name
Test status
Simulation time 5570445255 ps
CPU time 24.07 seconds
Started May 30 02:33:05 PM PDT 24
Finished May 30 02:33:32 PM PDT 24
Peak memory 213952 kb
Host smart-e596389e-8251-486e-8e6d-a362cf8d91ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789056439 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.3789056439
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.2042635827
Short name T155
Test name
Test status
Simulation time 89641527 ps
CPU time 0.86 seconds
Started May 30 02:07:22 PM PDT 24
Finished May 30 02:07:24 PM PDT 24
Peak memory 205024 kb
Host smart-fcf76781-ddad-4eb7-913c-577a5a574e5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042635827 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.2042635827
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.2163563750
Short name T134
Test name
Test status
Simulation time 7020516669 ps
CPU time 21.89 seconds
Started May 30 02:07:13 PM PDT 24
Finished May 30 02:07:37 PM PDT 24
Peak memory 205352 kb
Host smart-4a04ff91-4d52-485d-8832-ea2b71d78575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163563750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.2163563750
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.1367987950
Short name T8
Test name
Test status
Simulation time 9474080426 ps
CPU time 6.52 seconds
Started May 30 02:07:13 PM PDT 24
Finished May 30 02:07:22 PM PDT 24
Peak memory 205348 kb
Host smart-7b09dda1-a709-43f9-a3ed-17ef46744b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367987950 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.1367987950
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.2803941997
Short name T141
Test name
Test status
Simulation time 114111669 ps
CPU time 0.82 seconds
Started May 30 02:07:15 PM PDT 24
Finished May 30 02:07:18 PM PDT 24
Peak memory 205020 kb
Host smart-e8e7305c-357c-45d9-b89b-4f91ea2d0004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803941997 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.2803941997
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.1708258766
Short name T9
Test name
Test status
Simulation time 2788156445 ps
CPU time 4.15 seconds
Started May 30 02:07:16 PM PDT 24
Finished May 30 02:07:21 PM PDT 24
Peak memory 205132 kb
Host smart-ab196a2c-71f8-4f95-ab9d-1ccf9801b1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708258766 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.1708258766
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.482737617
Short name T220
Test name
Test status
Simulation time 231611672 ps
CPU time 1.38 seconds
Started May 30 02:07:14 PM PDT 24
Finished May 30 02:07:16 PM PDT 24
Peak memory 204876 kb
Host smart-21a79e45-fd73-441c-916b-a083271c5705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482737617 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.482737617
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.3886999706
Short name T216
Test name
Test status
Simulation time 4311362770 ps
CPU time 1.96 seconds
Started May 30 02:07:17 PM PDT 24
Finished May 30 02:07:21 PM PDT 24
Peak memory 205340 kb
Host smart-e2300d45-1d3c-43f2-8896-54c708526c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886999706 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.3886999706
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.4284098028
Short name T202
Test name
Test status
Simulation time 1443080920 ps
CPU time 1.71 seconds
Started May 30 02:07:16 PM PDT 24
Finished May 30 02:07:20 PM PDT 24
Peak memory 204468 kb
Host smart-ee915888-e86b-4906-bea5-0a68f20efcf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284098028 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.4284098028
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.3916488142
Short name T208
Test name
Test status
Simulation time 1775913753 ps
CPU time 5.67 seconds
Started May 30 02:07:15 PM PDT 24
Finished May 30 02:07:22 PM PDT 24
Peak memory 205116 kb
Host smart-8c12d07b-e069-4f09-a911-183d75029dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916488142 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.3916488142
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.1960188892
Short name T213
Test name
Test status
Simulation time 112889145 ps
CPU time 0.75 seconds
Started May 30 02:07:16 PM PDT 24
Finished May 30 02:07:18 PM PDT 24
Peak memory 204996 kb
Host smart-1c2195a3-2ec3-45ec-be57-d1cafc70bd37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960188892 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.1960188892
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.2208856492
Short name T138
Test name
Test status
Simulation time 298030006 ps
CPU time 1.24 seconds
Started May 30 02:07:16 PM PDT 24
Finished May 30 02:07:20 PM PDT 24
Peak memory 204588 kb
Host smart-6293e37f-31b2-43d6-b703-685529b432ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208856492 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.2208856492
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.2134385221
Short name T27
Test name
Test status
Simulation time 5573219129 ps
CPU time 15.01 seconds
Started May 30 02:07:12 PM PDT 24
Finished May 30 02:07:28 PM PDT 24
Peak memory 205404 kb
Host smart-80d9c4ca-3846-4a06-bcf1-2ac571ae1b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134385221 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.2134385221
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.1173386888
Short name T135
Test name
Test status
Simulation time 1970395537 ps
CPU time 6.11 seconds
Started May 30 02:07:16 PM PDT 24
Finished May 30 02:07:23 PM PDT 24
Peak memory 205284 kb
Host smart-21620268-6395-44c7-a736-1f34ab923fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173386888 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.1173386888
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.4280109169
Short name T218
Test name
Test status
Simulation time 33147199627 ps
CPU time 23.46 seconds
Started May 30 02:07:12 PM PDT 24
Finished May 30 02:07:37 PM PDT 24
Peak memory 205512 kb
Host smart-c0861f84-fcad-4173-a450-39226ff2c79b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280109169 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.4280109169
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.75876489
Short name T226
Test name
Test status
Simulation time 3566507237 ps
CPU time 4.14 seconds
Started May 30 02:07:14 PM PDT 24
Finished May 30 02:07:19 PM PDT 24
Peak memory 204996 kb
Host smart-8ababd49-a9bd-475e-90a6-276546d3b4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75876489 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.75876489
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all.2656835127
Short name T19
Test name
Test status
Simulation time 11092156019 ps
CPU time 32.56 seconds
Started May 30 02:07:16 PM PDT 24
Finished May 30 02:07:50 PM PDT 24
Peak memory 205380 kb
Host smart-ada8d929-19a5-4b93-95e3-ee524a020843
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656835127 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.2656835127
Directory /workspace/0.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.1700484191
Short name T10
Test name
Test status
Simulation time 7788176352 ps
CPU time 22.24 seconds
Started May 30 02:07:13 PM PDT 24
Finished May 30 02:07:37 PM PDT 24
Peak memory 205256 kb
Host smart-cc8bcb68-987e-4b26-8be5-3a88fe0ac122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700484191 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.1700484191
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.2076934830
Short name T31
Test name
Test status
Simulation time 119429331 ps
CPU time 1.02 seconds
Started May 30 02:07:22 PM PDT 24
Finished May 30 02:07:25 PM PDT 24
Peak memory 205004 kb
Host smart-0f9e6a72-a889-47b2-99b8-ae3f0a2c697f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076934830 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.2076934830
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.3793514127
Short name T157
Test name
Test status
Simulation time 189766943 ps
CPU time 0.77 seconds
Started May 30 02:07:23 PM PDT 24
Finished May 30 02:07:25 PM PDT 24
Peak memory 204992 kb
Host smart-fffeb50d-1be9-424a-a03d-c7abb77bbbf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793514127 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.3793514127
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.1700006060
Short name T215
Test name
Test status
Simulation time 20041520896 ps
CPU time 57.81 seconds
Started May 30 02:07:22 PM PDT 24
Finished May 30 02:08:21 PM PDT 24
Peak memory 205428 kb
Host smart-24074e7f-6f2a-47f8-b9fc-dcc82555d33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700006060 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.1700006060
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.306561262
Short name T14
Test name
Test status
Simulation time 21103066634 ps
CPU time 19.12 seconds
Started May 30 02:07:22 PM PDT 24
Finished May 30 02:07:42 PM PDT 24
Peak memory 205376 kb
Host smart-52c00c68-7ff5-4005-9ee1-d39c72f336e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306561262 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.306561262
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.466254910
Short name T34
Test name
Test status
Simulation time 167222146 ps
CPU time 0.88 seconds
Started May 30 02:07:22 PM PDT 24
Finished May 30 02:07:24 PM PDT 24
Peak memory 204888 kb
Host smart-ffb7ef9d-9a2d-4272-9c63-b41bb8e151b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466254910 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.466254910
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.793954192
Short name T26
Test name
Test status
Simulation time 1327299271 ps
CPU time 3.08 seconds
Started May 30 02:07:22 PM PDT 24
Finished May 30 02:07:26 PM PDT 24
Peak memory 204876 kb
Host smart-af4638a8-0dee-48d6-a6ff-1a9a421fb93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793954192 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.793954192
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.3612016987
Short name T7
Test name
Test status
Simulation time 4675532651 ps
CPU time 4.08 seconds
Started May 30 02:07:21 PM PDT 24
Finished May 30 02:07:26 PM PDT 24
Peak memory 205368 kb
Host smart-18bf05ec-4c8a-41cb-8792-3e3a3631168f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612016987 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.3612016987
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.1126518285
Short name T194
Test name
Test status
Simulation time 225948127 ps
CPU time 0.81 seconds
Started May 30 02:07:22 PM PDT 24
Finished May 30 02:07:24 PM PDT 24
Peak memory 204916 kb
Host smart-7eb44832-ecd1-44a1-88c2-38801b0f2633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126518285 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.1126518285
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.3310314817
Short name T209
Test name
Test status
Simulation time 16183110898 ps
CPU time 25.03 seconds
Started May 30 02:07:21 PM PDT 24
Finished May 30 02:07:47 PM PDT 24
Peak memory 205456 kb
Host smart-91676fc1-8b33-41d9-913a-82ea7c76efb8
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3310314817 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.3310314817
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.953052462
Short name T139
Test name
Test status
Simulation time 2645175632 ps
CPU time 4.22 seconds
Started May 30 02:07:25 PM PDT 24
Finished May 30 02:07:31 PM PDT 24
Peak memory 205132 kb
Host smart-3f911b6c-504d-4cf3-a595-4ef6ab4651f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953052462 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.953052462
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.165360880
Short name T196
Test name
Test status
Simulation time 297445480 ps
CPU time 0.82 seconds
Started May 30 02:07:22 PM PDT 24
Finished May 30 02:07:24 PM PDT 24
Peak memory 204884 kb
Host smart-63d8b39a-0e62-4b03-88ae-5d9d1488841a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165360880 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.165360880
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.994148571
Short name T224
Test name
Test status
Simulation time 856954289 ps
CPU time 2.88 seconds
Started May 30 02:07:25 PM PDT 24
Finished May 30 02:07:29 PM PDT 24
Peak memory 204844 kb
Host smart-26e2ffad-3ee4-4b07-9e3b-6d825958da40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994148571 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.994148571
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.1380031410
Short name T203
Test name
Test status
Simulation time 390894396 ps
CPU time 0.97 seconds
Started May 30 02:07:25 PM PDT 24
Finished May 30 02:07:28 PM PDT 24
Peak memory 204860 kb
Host smart-5a1f7db1-ff49-444f-8e03-c850c3a1e705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380031410 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.1380031410
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.2425215854
Short name T200
Test name
Test status
Simulation time 10763206557 ps
CPU time 15 seconds
Started May 30 02:07:22 PM PDT 24
Finished May 30 02:07:38 PM PDT 24
Peak memory 205196 kb
Host smart-fda7b6e4-4b0f-4a24-8510-bf22809ae330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425215854 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.2425215854
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.1613513711
Short name T199
Test name
Test status
Simulation time 247231494 ps
CPU time 1.35 seconds
Started May 30 02:07:23 PM PDT 24
Finished May 30 02:07:25 PM PDT 24
Peak memory 204888 kb
Host smart-5dc96fd0-0210-430c-a670-28ab714947e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613513711 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.1613513711
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.2779027512
Short name T68
Test name
Test status
Simulation time 593267707 ps
CPU time 1.24 seconds
Started May 30 02:07:25 PM PDT 24
Finished May 30 02:07:28 PM PDT 24
Peak memory 204940 kb
Host smart-4edb72d7-626f-4da8-8bb2-bbf231f4ed6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779027512 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.2779027512
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.3424881281
Short name T140
Test name
Test status
Simulation time 477905357 ps
CPU time 1.34 seconds
Started May 30 02:07:15 PM PDT 24
Finished May 30 02:07:18 PM PDT 24
Peak memory 205032 kb
Host smart-3a0fefa3-7679-4d17-98dc-fe184f455f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424881281 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.3424881281
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.1486704708
Short name T20
Test name
Test status
Simulation time 2734132019 ps
CPU time 8.15 seconds
Started May 30 02:07:22 PM PDT 24
Finished May 30 02:07:31 PM PDT 24
Peak memory 205376 kb
Host smart-3fbfeafd-d69f-43a2-8ac7-d491157cfe7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486704708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.1486704708
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.524464340
Short name T30
Test name
Test status
Simulation time 681136960 ps
CPU time 1.48 seconds
Started May 30 02:07:22 PM PDT 24
Finished May 30 02:07:25 PM PDT 24
Peak memory 205012 kb
Host smart-df774188-bc2d-4c87-ab93-76641f3da369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524464340 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.524464340
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.227666706
Short name T36
Test name
Test status
Simulation time 924133005 ps
CPU time 3.39 seconds
Started May 30 02:07:22 PM PDT 24
Finished May 30 02:07:27 PM PDT 24
Peak memory 204992 kb
Host smart-9709ff66-2a08-43b5-864b-a2ec64e2a5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227666706 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.227666706
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.1139510745
Short name T28
Test name
Test status
Simulation time 191055959 ps
CPU time 0.77 seconds
Started May 30 02:07:21 PM PDT 24
Finished May 30 02:07:23 PM PDT 24
Peak memory 213200 kb
Host smart-58c80f5a-1e75-492d-a373-e6ff0e229ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139510745 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.1139510745
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.1431636475
Short name T55
Test name
Test status
Simulation time 494375397 ps
CPU time 1.63 seconds
Started May 30 02:07:21 PM PDT 24
Finished May 30 02:07:24 PM PDT 24
Peak memory 229108 kb
Host smart-e32fdca1-c37b-4d9e-afcf-215dfac9a366
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431636475 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.1431636475
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.1806489143
Short name T177
Test name
Test status
Simulation time 746482741 ps
CPU time 1.29 seconds
Started May 30 02:07:25 PM PDT 24
Finished May 30 02:07:28 PM PDT 24
Peak memory 204860 kb
Host smart-675df037-4163-4377-9f35-734c54950eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806489143 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.1806489143
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.3847251902
Short name T164
Test name
Test status
Simulation time 59267960 ps
CPU time 0.85 seconds
Started May 30 02:08:41 PM PDT 24
Finished May 30 02:08:43 PM PDT 24
Peak memory 205020 kb
Host smart-ec948ac6-4b75-4aa6-8928-d82b1abe5995
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847251902 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.3847251902
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.1118712263
Short name T59
Test name
Test status
Simulation time 42216187467 ps
CPU time 30.44 seconds
Started May 30 02:08:43 PM PDT 24
Finished May 30 02:09:15 PM PDT 24
Peak memory 213768 kb
Host smart-f5dca481-0ada-4913-ba8e-ea7853e4aefa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118712263 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.1118712263
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.3123472820
Short name T214
Test name
Test status
Simulation time 16625011701 ps
CPU time 31.23 seconds
Started May 30 02:08:42 PM PDT 24
Finished May 30 02:09:15 PM PDT 24
Peak memory 213808 kb
Host smart-e68b998e-cdc2-4334-a0c3-07e1a60286e3
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3123472820 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.3123472820
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.3526454822
Short name T166
Test name
Test status
Simulation time 16632016725 ps
CPU time 45.09 seconds
Started May 30 02:08:41 PM PDT 24
Finished May 30 02:09:28 PM PDT 24
Peak memory 205280 kb
Host smart-bde89bb1-eb3f-417d-91d7-784051a53bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526454822 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.3526454822
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.3073567705
Short name T162
Test name
Test status
Simulation time 83873409 ps
CPU time 0.74 seconds
Started May 30 02:08:38 PM PDT 24
Finished May 30 02:08:40 PM PDT 24
Peak memory 205024 kb
Host smart-c8183f9e-ff9d-4caa-8636-b68d34a6da49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073567705 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.3073567705
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.305604271
Short name T22
Test name
Test status
Simulation time 22219213261 ps
CPU time 65.09 seconds
Started May 30 02:08:41 PM PDT 24
Finished May 30 02:09:48 PM PDT 24
Peak memory 205628 kb
Host smart-d953ce9c-ae3f-475a-8958-30d8b66c86ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305604271 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.305604271
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.1839478805
Short name T17
Test name
Test status
Simulation time 28775209227 ps
CPU time 64.15 seconds
Started May 30 02:08:42 PM PDT 24
Finished May 30 02:09:47 PM PDT 24
Peak memory 213684 kb
Host smart-bce36846-4841-497e-9306-9e4bec524c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839478805 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.1839478805
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.1368001252
Short name T175
Test name
Test status
Simulation time 4724766315 ps
CPU time 7.85 seconds
Started May 30 02:08:40 PM PDT 24
Finished May 30 02:08:49 PM PDT 24
Peak memory 205568 kb
Host smart-41150673-d20d-4ad0-8bd4-e275ca985197
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1368001252 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_
tl_access.1368001252
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.574173320
Short name T69
Test name
Test status
Simulation time 43314189115 ps
CPU time 114.01 seconds
Started May 30 02:08:41 PM PDT 24
Finished May 30 02:10:37 PM PDT 24
Peak memory 205504 kb
Host smart-d90b82ee-ffd7-4b05-85ef-fd4ad5b2bd1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574173320 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.574173320
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.541902941
Short name T156
Test name
Test status
Simulation time 202066348 ps
CPU time 0.75 seconds
Started May 30 02:08:41 PM PDT 24
Finished May 30 02:08:44 PM PDT 24
Peak memory 204996 kb
Host smart-e9f28cb8-0ba2-4f4c-ae87-9ec607ad16c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541902941 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.541902941
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.2315224122
Short name T201
Test name
Test status
Simulation time 15874015182 ps
CPU time 43.66 seconds
Started May 30 02:08:43 PM PDT 24
Finished May 30 02:09:28 PM PDT 24
Peak memory 205568 kb
Host smart-db94d7ec-f6be-4c09-86de-5d8ae0988040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315224122 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.2315224122
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.1509975021
Short name T15
Test name
Test status
Simulation time 47993591991 ps
CPU time 69.21 seconds
Started May 30 02:08:37 PM PDT 24
Finished May 30 02:09:47 PM PDT 24
Peak memory 213736 kb
Host smart-faebdd9b-b7a6-4ea9-8698-01dbb936d279
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1509975021 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.1509975021
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.4171725258
Short name T198
Test name
Test status
Simulation time 258123388 ps
CPU time 0.77 seconds
Started May 30 02:08:41 PM PDT 24
Finished May 30 02:08:44 PM PDT 24
Peak memory 204992 kb
Host smart-91f50c61-0bb7-44f8-8af5-30b463d663f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171725258 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.4171725258
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.1398730666
Short name T2
Test name
Test status
Simulation time 6663509138 ps
CPU time 22.49 seconds
Started May 30 02:08:40 PM PDT 24
Finished May 30 02:09:04 PM PDT 24
Peak memory 205488 kb
Host smart-7356251e-33bf-41c8-a29e-e4e8581c1ca4
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1398730666 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_
tl_access.1398730666
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.3499467693
Short name T180
Test name
Test status
Simulation time 27988557265 ps
CPU time 26.31 seconds
Started May 30 02:08:40 PM PDT 24
Finished May 30 02:09:07 PM PDT 24
Peak memory 213756 kb
Host smart-be75e255-7c06-459a-bf53-af8748c1f8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499467693 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.3499467693
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.3903177483
Short name T165
Test name
Test status
Simulation time 82666332 ps
CPU time 0.75 seconds
Started May 30 02:08:40 PM PDT 24
Finished May 30 02:08:42 PM PDT 24
Peak memory 205044 kb
Host smart-9b818e02-6b04-4144-bb6c-26f089e5b482
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903177483 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.3903177483
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.2951093487
Short name T5
Test name
Test status
Simulation time 34977940654 ps
CPU time 32.8 seconds
Started May 30 02:08:39 PM PDT 24
Finished May 30 02:09:13 PM PDT 24
Peak memory 213700 kb
Host smart-a1a5ec51-9ed9-4ade-a09c-72912a4b169b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951093487 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.2951093487
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.3748293381
Short name T57
Test name
Test status
Simulation time 13007772372 ps
CPU time 5.63 seconds
Started May 30 02:08:38 PM PDT 24
Finished May 30 02:08:45 PM PDT 24
Peak memory 215180 kb
Host smart-bdb8ba49-0461-44bb-9933-cc328d746886
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3748293381 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.3748293381
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_stress_all.150102745
Short name T35
Test name
Test status
Simulation time 8713720614 ps
CPU time 9.38 seconds
Started May 30 02:08:41 PM PDT 24
Finished May 30 02:08:53 PM PDT 24
Peak memory 205436 kb
Host smart-ed73b018-dc20-467d-844e-2b8018765bfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150102745 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.150102745
Directory /workspace/14.rv_dm_stress_all/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.4168332228
Short name T112
Test name
Test status
Simulation time 52193409 ps
CPU time 0.81 seconds
Started May 30 02:08:38 PM PDT 24
Finished May 30 02:08:40 PM PDT 24
Peak memory 205048 kb
Host smart-c89d94d1-d42f-4420-81e7-03ddae18a51f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168332228 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.4168332228
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.1242846556
Short name T197
Test name
Test status
Simulation time 23507149564 ps
CPU time 49.63 seconds
Started May 30 02:08:39 PM PDT 24
Finished May 30 02:09:30 PM PDT 24
Peak memory 205516 kb
Host smart-b69f39a3-3925-4dc1-abe9-ff59e9b7a23e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1242846556 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_
tl_access.1242846556
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.2714907982
Short name T186
Test name
Test status
Simulation time 23252344102 ps
CPU time 19.86 seconds
Started May 30 02:08:43 PM PDT 24
Finished May 30 02:09:04 PM PDT 24
Peak memory 213664 kb
Host smart-b9403105-73ab-4409-b5f8-05317735cef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714907982 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.2714907982
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_stress_all.1320019690
Short name T133
Test name
Test status
Simulation time 19181060271 ps
CPU time 10.66 seconds
Started May 30 02:08:40 PM PDT 24
Finished May 30 02:08:52 PM PDT 24
Peak memory 205412 kb
Host smart-131602d2-c620-4efe-be5d-5328242b845b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320019690 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.1320019690
Directory /workspace/15.rv_dm_stress_all/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.2011147310
Short name T207
Test name
Test status
Simulation time 148548821 ps
CPU time 0.82 seconds
Started May 30 02:08:41 PM PDT 24
Finished May 30 02:08:43 PM PDT 24
Peak memory 204996 kb
Host smart-c9827746-3a24-46c3-8408-3315d1684d80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011147310 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.2011147310
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.114978592
Short name T167
Test name
Test status
Simulation time 9464915631 ps
CPU time 8.8 seconds
Started May 30 02:08:41 PM PDT 24
Finished May 30 02:08:52 PM PDT 24
Peak memory 205576 kb
Host smart-4a35bad9-5dd0-489f-a6f4-78e466d31c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114978592 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.114978592
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.123942305
Short name T170
Test name
Test status
Simulation time 38455431083 ps
CPU time 30.8 seconds
Started May 30 02:08:42 PM PDT 24
Finished May 30 02:09:14 PM PDT 24
Peak memory 213772 kb
Host smart-cbe055b6-6ada-4a5f-8efa-6576cfb1a10e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=123942305 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_t
l_access.123942305
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.4065177578
Short name T60
Test name
Test status
Simulation time 19574765233 ps
CPU time 43.68 seconds
Started May 30 02:08:41 PM PDT 24
Finished May 30 02:09:26 PM PDT 24
Peak memory 215512 kb
Host smart-3757becd-814f-4535-b0cb-bcbf1fde56ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065177578 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.4065177578
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.4048209724
Short name T146
Test name
Test status
Simulation time 94783200 ps
CPU time 0.88 seconds
Started May 30 02:08:39 PM PDT 24
Finished May 30 02:08:42 PM PDT 24
Peak memory 205020 kb
Host smart-e219ec21-6d4c-4e8e-81be-b4416fcd61e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048209724 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.4048209724
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.3750197172
Short name T86
Test name
Test status
Simulation time 38460239463 ps
CPU time 30.48 seconds
Started May 30 02:08:41 PM PDT 24
Finished May 30 02:09:13 PM PDT 24
Peak memory 216464 kb
Host smart-0606ccd9-adae-4edf-bbc8-d092383947c8
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3750197172 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_
tl_access.3750197172
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.1681627555
Short name T168
Test name
Test status
Simulation time 40964097834 ps
CPU time 122.86 seconds
Started May 30 02:08:41 PM PDT 24
Finished May 30 02:10:45 PM PDT 24
Peak memory 213704 kb
Host smart-162e88a6-ea01-49b2-8c78-55ed0bc75abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681627555 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.1681627555
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.1525148377
Short name T147
Test name
Test status
Simulation time 49184566 ps
CPU time 0.8 seconds
Started May 30 02:08:47 PM PDT 24
Finished May 30 02:08:50 PM PDT 24
Peak memory 205060 kb
Host smart-3a352948-66af-4584-a2b5-476d99898889
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525148377 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.1525148377
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.1618692851
Short name T212
Test name
Test status
Simulation time 26438457100 ps
CPU time 35.49 seconds
Started May 30 02:08:47 PM PDT 24
Finished May 30 02:09:24 PM PDT 24
Peak memory 205556 kb
Host smart-c02829ca-fb5f-435f-81f6-44260656dcdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618692851 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.1618692851
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.38310566
Short name T183
Test name
Test status
Simulation time 43594605178 ps
CPU time 55.79 seconds
Started May 30 02:08:44 PM PDT 24
Finished May 30 02:09:41 PM PDT 24
Peak memory 217056 kb
Host smart-85994acc-08a5-4fbd-b48b-fbbaf79374ea
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=38310566 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_tl
_access.38310566
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.2319923800
Short name T173
Test name
Test status
Simulation time 32887771959 ps
CPU time 10.63 seconds
Started May 30 02:08:46 PM PDT 24
Finished May 30 02:08:59 PM PDT 24
Peak memory 213704 kb
Host smart-1ff0cb97-b3e5-46f3-97f5-250ebc52d313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319923800 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.2319923800
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.3739375301
Short name T119
Test name
Test status
Simulation time 176931638 ps
CPU time 0.79 seconds
Started May 30 02:08:47 PM PDT 24
Finished May 30 02:08:50 PM PDT 24
Peak memory 205056 kb
Host smart-98b6b060-bdee-4e59-82fb-45031efca0b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739375301 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.3739375301
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.1406366544
Short name T187
Test name
Test status
Simulation time 40967468031 ps
CPU time 61.82 seconds
Started May 30 02:08:48 PM PDT 24
Finished May 30 02:09:52 PM PDT 24
Peak memory 213728 kb
Host smart-106e1292-218a-4d8e-a3ec-febec1933822
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1406366544 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_
tl_access.1406366544
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_stress_all.318238052
Short name T132
Test name
Test status
Simulation time 7151808220 ps
CPU time 20.4 seconds
Started May 30 02:08:46 PM PDT 24
Finished May 30 02:09:08 PM PDT 24
Peak memory 213560 kb
Host smart-4957af79-7fff-4bb6-b821-e9757a7aa932
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318238052 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.318238052
Directory /workspace/19.rv_dm_stress_all/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.2223586409
Short name T182
Test name
Test status
Simulation time 54495013 ps
CPU time 0.72 seconds
Started May 30 02:07:22 PM PDT 24
Finished May 30 02:07:24 PM PDT 24
Peak memory 204872 kb
Host smart-cd581321-c290-454e-8049-41ac4d83aaaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223586409 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.2223586409
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.992673237
Short name T219
Test name
Test status
Simulation time 7427442426 ps
CPU time 12.42 seconds
Started May 30 02:07:21 PM PDT 24
Finished May 30 02:07:34 PM PDT 24
Peak memory 205448 kb
Host smart-ef94d6de-3b1a-4777-be0a-1bb82505dc03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992673237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.992673237
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.3755760191
Short name T222
Test name
Test status
Simulation time 14991106307 ps
CPU time 23.92 seconds
Started May 30 02:07:25 PM PDT 24
Finished May 30 02:07:50 PM PDT 24
Peak memory 213744 kb
Host smart-4a900b1c-1169-46e3-8b3a-129dd44f745f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3755760191 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.3755760191
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.1864812576
Short name T227
Test name
Test status
Simulation time 825838587 ps
CPU time 2.8 seconds
Started May 30 02:07:22 PM PDT 24
Finished May 30 02:07:26 PM PDT 24
Peak memory 204852 kb
Host smart-88d995be-5441-439b-afa1-258aa1bb1d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864812576 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.1864812576
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.2289678812
Short name T176
Test name
Test status
Simulation time 22137921581 ps
CPU time 62.81 seconds
Started May 30 02:07:22 PM PDT 24
Finished May 30 02:08:26 PM PDT 24
Peak memory 205280 kb
Host smart-f6a7fcdc-2619-4571-ac7b-c18ef28b9315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289678812 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.2289678812
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.1812021947
Short name T41
Test name
Test status
Simulation time 292915798 ps
CPU time 1.36 seconds
Started May 30 02:07:21 PM PDT 24
Finished May 30 02:07:24 PM PDT 24
Peak memory 228384 kb
Host smart-c3e1c1be-fe70-4db1-a315-1b897bf4f129
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812021947 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.1812021947
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.2392493529
Short name T189
Test name
Test status
Simulation time 37837859 ps
CPU time 0.75 seconds
Started May 30 02:08:46 PM PDT 24
Finished May 30 02:08:48 PM PDT 24
Peak memory 205000 kb
Host smart-d97ae1fa-d80c-4931-80a0-b2345d850595
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392493529 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.2392493529
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_stress_all.2296044959
Short name T12
Test name
Test status
Simulation time 22810396679 ps
CPU time 17.99 seconds
Started May 30 02:08:46 PM PDT 24
Finished May 30 02:09:06 PM PDT 24
Peak memory 205440 kb
Host smart-7cb675c3-d62b-4b8e-bd0a-3e9ff495f65f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296044959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.2296044959
Directory /workspace/21.rv_dm_stress_all/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.477126744
Short name T184
Test name
Test status
Simulation time 127302875 ps
CPU time 0.74 seconds
Started May 30 02:08:45 PM PDT 24
Finished May 30 02:08:47 PM PDT 24
Peak memory 205040 kb
Host smart-1268a127-ff61-4e47-9c1d-2314834fdb44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477126744 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.477126744
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_stress_all.1443970084
Short name T211
Test name
Test status
Simulation time 6529963315 ps
CPU time 9.23 seconds
Started May 30 02:08:46 PM PDT 24
Finished May 30 02:08:57 PM PDT 24
Peak memory 205352 kb
Host smart-5772c027-54c6-4c81-8b6a-729afbd81fef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443970084 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.1443970084
Directory /workspace/22.rv_dm_stress_all/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.1583145130
Short name T51
Test name
Test status
Simulation time 100014369 ps
CPU time 0.73 seconds
Started May 30 02:08:46 PM PDT 24
Finished May 30 02:08:48 PM PDT 24
Peak memory 205060 kb
Host smart-81c7ae33-e9ab-4a08-876d-df1b64fe3372
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583145130 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.1583145130
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.3962148341
Short name T159
Test name
Test status
Simulation time 106984584 ps
CPU time 0.73 seconds
Started May 30 02:08:46 PM PDT 24
Finished May 30 02:08:49 PM PDT 24
Peak memory 205064 kb
Host smart-9926986b-353c-4cc5-9145-f6d688967a81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962148341 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.3962148341
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.2916421537
Short name T67
Test name
Test status
Simulation time 66220711 ps
CPU time 0.86 seconds
Started May 30 02:08:48 PM PDT 24
Finished May 30 02:08:51 PM PDT 24
Peak memory 205064 kb
Host smart-9477e68c-76f8-4019-bfb1-b7b3030a40b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916421537 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.2916421537
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_stress_all.878521764
Short name T137
Test name
Test status
Simulation time 41806250264 ps
CPU time 61.78 seconds
Started May 30 02:08:47 PM PDT 24
Finished May 30 02:09:51 PM PDT 24
Peak memory 213500 kb
Host smart-84827635-9069-4f5c-be7f-23ced3676c73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878521764 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.878521764
Directory /workspace/25.rv_dm_stress_all/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.2435788348
Short name T23
Test name
Test status
Simulation time 157710712 ps
CPU time 1.12 seconds
Started May 30 02:08:47 PM PDT 24
Finished May 30 02:08:50 PM PDT 24
Peak memory 205060 kb
Host smart-a00ebe98-e652-4fbd-a5ed-3c1cb179f87e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435788348 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.2435788348
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.623687251
Short name T149
Test name
Test status
Simulation time 61339329 ps
CPU time 0.68 seconds
Started May 30 02:08:46 PM PDT 24
Finished May 30 02:08:48 PM PDT 24
Peak memory 205060 kb
Host smart-984e3eb1-9a11-430e-bf95-e23d626e4ef2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623687251 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.623687251
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.198359205
Short name T151
Test name
Test status
Simulation time 341989255 ps
CPU time 0.82 seconds
Started May 30 02:08:48 PM PDT 24
Finished May 30 02:08:51 PM PDT 24
Peak memory 205064 kb
Host smart-c71f0f48-53e1-43a2-ad9a-55aff1918eee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198359205 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.198359205
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.3394879554
Short name T161
Test name
Test status
Simulation time 55074415 ps
CPU time 0.74 seconds
Started May 30 02:08:46 PM PDT 24
Finished May 30 02:08:49 PM PDT 24
Peak memory 205048 kb
Host smart-483a026a-91f0-4837-8a26-cfb643f3bf49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394879554 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.3394879554
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.1133209936
Short name T143
Test name
Test status
Simulation time 60232657 ps
CPU time 0.68 seconds
Started May 30 02:07:21 PM PDT 24
Finished May 30 02:07:23 PM PDT 24
Peak memory 204888 kb
Host smart-a159503e-b7e6-4a97-9895-a4d3ab8b5480
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133209936 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.1133209936
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.221430246
Short name T204
Test name
Test status
Simulation time 19868384880 ps
CPU time 29.95 seconds
Started May 30 02:07:25 PM PDT 24
Finished May 30 02:07:56 PM PDT 24
Peak memory 213736 kb
Host smart-16d5582a-9987-478b-b81c-bb48fe4ae496
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=221430246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_tl
_access.221430246
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.790572456
Short name T185
Test name
Test status
Simulation time 609282151 ps
CPU time 1.14 seconds
Started May 30 02:07:25 PM PDT 24
Finished May 30 02:07:27 PM PDT 24
Peak memory 204872 kb
Host smart-59ae5c62-7a79-4a61-b7ef-7d7e47ba45c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790572456 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.790572456
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.3042694482
Short name T221
Test name
Test status
Simulation time 10027932457 ps
CPU time 16.55 seconds
Started May 30 02:07:21 PM PDT 24
Finished May 30 02:07:38 PM PDT 24
Peak memory 205492 kb
Host smart-905143c4-26e4-49c6-a9c1-1bb17e4257d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042694482 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.3042694482
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.1099526730
Short name T54
Test name
Test status
Simulation time 470200379 ps
CPU time 2.35 seconds
Started May 30 02:07:22 PM PDT 24
Finished May 30 02:07:26 PM PDT 24
Peak memory 229124 kb
Host smart-d7a3e060-2e68-4cfe-ab99-f36cef85ed1f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099526730 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.1099526730
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.241382461
Short name T150
Test name
Test status
Simulation time 48774107 ps
CPU time 0.73 seconds
Started May 30 02:08:46 PM PDT 24
Finished May 30 02:08:49 PM PDT 24
Peak memory 205000 kb
Host smart-e6e5aeb7-f200-43a1-90d8-276edf0d4afa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241382461 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.241382461
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.3419790097
Short name T160
Test name
Test status
Simulation time 78913018 ps
CPU time 0.72 seconds
Started May 30 02:08:47 PM PDT 24
Finished May 30 02:08:49 PM PDT 24
Peak memory 205068 kb
Host smart-7928b3e1-3724-4f2b-978c-64693e6b795c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419790097 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.3419790097
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.4039918671
Short name T52
Test name
Test status
Simulation time 88480023 ps
CPU time 0.7 seconds
Started May 30 02:08:47 PM PDT 24
Finished May 30 02:08:50 PM PDT 24
Peak memory 205064 kb
Host smart-7cd8d58e-d583-4c50-8fdf-3355136bee55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039918671 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.4039918671
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.1441206940
Short name T113
Test name
Test status
Simulation time 55686552 ps
CPU time 0.77 seconds
Started May 30 02:08:47 PM PDT 24
Finished May 30 02:08:50 PM PDT 24
Peak memory 205004 kb
Host smart-75fddc0f-1224-4b60-b4b4-81903b3e5563
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441206940 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.1441206940
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_stress_all.1202341539
Short name T117
Test name
Test status
Simulation time 5025042239 ps
CPU time 7.64 seconds
Started May 30 02:08:47 PM PDT 24
Finished May 30 02:08:56 PM PDT 24
Peak memory 205364 kb
Host smart-3b72e5ee-151b-4822-a581-cb11f14fbf1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202341539 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.1202341539
Directory /workspace/33.rv_dm_stress_all/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.3851402788
Short name T53
Test name
Test status
Simulation time 90077041 ps
CPU time 0.72 seconds
Started May 30 02:08:47 PM PDT 24
Finished May 30 02:08:50 PM PDT 24
Peak memory 205060 kb
Host smart-cbd35314-0fe2-4cee-a84b-27c8c785f841
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851402788 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.3851402788
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.4253080388
Short name T145
Test name
Test status
Simulation time 127416665 ps
CPU time 0.79 seconds
Started May 30 02:08:46 PM PDT 24
Finished May 30 02:08:49 PM PDT 24
Peak memory 205048 kb
Host smart-63b607f4-d043-4354-8138-6a04cbe34078
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253080388 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.4253080388
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.3097597463
Short name T153
Test name
Test status
Simulation time 52189432 ps
CPU time 0.74 seconds
Started May 30 02:09:03 PM PDT 24
Finished May 30 02:09:05 PM PDT 24
Peak memory 204824 kb
Host smart-cdb86801-4b70-42dd-a1e7-8a4267446680
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097597463 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.3097597463
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.734100181
Short name T142
Test name
Test status
Simulation time 43087437 ps
CPU time 0.72 seconds
Started May 30 02:08:55 PM PDT 24
Finished May 30 02:08:57 PM PDT 24
Peak memory 205048 kb
Host smart-190fc59d-dd37-484c-90f2-a67ab160fc10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734100181 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.734100181
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_stress_all.3857281804
Short name T33
Test name
Test status
Simulation time 59068130339 ps
CPU time 37.26 seconds
Started May 30 02:08:49 PM PDT 24
Finished May 30 02:09:28 PM PDT 24
Peak memory 213572 kb
Host smart-c2ab6c52-bfc7-45d8-b922-539e416d7503
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857281804 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.3857281804
Directory /workspace/37.rv_dm_stress_all/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.2458844287
Short name T43
Test name
Test status
Simulation time 43235375 ps
CPU time 0.77 seconds
Started May 30 02:08:50 PM PDT 24
Finished May 30 02:08:52 PM PDT 24
Peak memory 205060 kb
Host smart-db8c10a1-0650-49bf-8c88-518e1216a859
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458844287 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.2458844287
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.902711656
Short name T188
Test name
Test status
Simulation time 91147256 ps
CPU time 0.91 seconds
Started May 30 02:09:03 PM PDT 24
Finished May 30 02:09:06 PM PDT 24
Peak memory 204992 kb
Host smart-edddce54-3785-4f70-9113-89a2ecd5a6b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902711656 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.902711656
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.3851279716
Short name T1
Test name
Test status
Simulation time 62738349 ps
CPU time 0.8 seconds
Started May 30 02:07:29 PM PDT 24
Finished May 30 02:07:31 PM PDT 24
Peak memory 205068 kb
Host smart-68dd7b3a-7a23-4fdc-910e-d571be0fb7ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851279716 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.3851279716
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.3807728765
Short name T190
Test name
Test status
Simulation time 13026796120 ps
CPU time 11.92 seconds
Started May 30 02:07:21 PM PDT 24
Finished May 30 02:07:35 PM PDT 24
Peak memory 205548 kb
Host smart-c9f327c9-d4cc-4a09-9073-8871815000e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807728765 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.3807728765
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.3230910084
Short name T225
Test name
Test status
Simulation time 18375568823 ps
CPU time 28.22 seconds
Started May 30 02:07:21 PM PDT 24
Finished May 30 02:07:50 PM PDT 24
Peak memory 205532 kb
Host smart-6097fd72-8e0f-4aa3-b52b-9dd67315f703
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3230910084 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.3230910084
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.4229886724
Short name T11
Test name
Test status
Simulation time 140421588 ps
CPU time 0.76 seconds
Started May 30 02:07:21 PM PDT 24
Finished May 30 02:07:23 PM PDT 24
Peak memory 204868 kb
Host smart-add780bd-d987-414e-bdf5-eabb2868d9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229886724 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.4229886724
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.4045229316
Short name T210
Test name
Test status
Simulation time 11884938447 ps
CPU time 19.5 seconds
Started May 30 02:07:23 PM PDT 24
Finished May 30 02:07:44 PM PDT 24
Peak memory 205536 kb
Host smart-751a2ffa-17a6-448f-a887-3d5520e9291a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045229316 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.4045229316
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.243600824
Short name T40
Test name
Test status
Simulation time 1502336457 ps
CPU time 5.15 seconds
Started May 30 02:07:29 PM PDT 24
Finished May 30 02:07:35 PM PDT 24
Peak memory 237456 kb
Host smart-5c2542cf-ff50-41c5-b8a1-3c547a01eb66
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243600824 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.243600824
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.1323110857
Short name T193
Test name
Test status
Simulation time 43239367 ps
CPU time 0.74 seconds
Started May 30 02:09:02 PM PDT 24
Finished May 30 02:09:03 PM PDT 24
Peak memory 204992 kb
Host smart-9218ba96-ff65-4ddb-8f8f-398b06ec9644
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323110857 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.1323110857
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.3638926237
Short name T174
Test name
Test status
Simulation time 191574830 ps
CPU time 0.75 seconds
Started May 30 02:08:52 PM PDT 24
Finished May 30 02:08:53 PM PDT 24
Peak memory 205048 kb
Host smart-cdc940d0-499f-420c-9916-28b66fc2bbde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638926237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.3638926237
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.1125499925
Short name T163
Test name
Test status
Simulation time 57738995 ps
CPU time 0.75 seconds
Started May 30 02:08:52 PM PDT 24
Finished May 30 02:08:54 PM PDT 24
Peak memory 205096 kb
Host smart-1fe4d131-a312-46fa-9b01-ffabd8b50833
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125499925 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.1125499925
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.2160068740
Short name T195
Test name
Test status
Simulation time 162805568 ps
CPU time 0.73 seconds
Started May 30 02:08:54 PM PDT 24
Finished May 30 02:08:56 PM PDT 24
Peak memory 205068 kb
Host smart-8e3e48ab-6f64-4ac5-a3a8-da6eef1b93a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160068740 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.2160068740
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.2181579752
Short name T58
Test name
Test status
Simulation time 186791111 ps
CPU time 0.76 seconds
Started May 30 02:08:55 PM PDT 24
Finished May 30 02:08:57 PM PDT 24
Peak memory 204916 kb
Host smart-1ccd93d1-a5a8-4b09-a33a-d362efbbb34e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181579752 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.2181579752
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_stress_all.3778698186
Short name T6
Test name
Test status
Simulation time 9601013048 ps
CPU time 27.51 seconds
Started May 30 02:08:56 PM PDT 24
Finished May 30 02:09:25 PM PDT 24
Peak memory 205308 kb
Host smart-210a6ba9-f616-4a8c-89fa-d441c65e0639
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778698186 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.3778698186
Directory /workspace/44.rv_dm_stress_all/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.838152394
Short name T158
Test name
Test status
Simulation time 91331305 ps
CPU time 0.73 seconds
Started May 30 02:09:03 PM PDT 24
Finished May 30 02:09:05 PM PDT 24
Peak memory 205028 kb
Host smart-62bf562a-a8af-433e-bb08-c09cc2d271a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838152394 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.838152394
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_stress_all.1777265629
Short name T223
Test name
Test status
Simulation time 9858624358 ps
CPU time 28.93 seconds
Started May 30 02:08:55 PM PDT 24
Finished May 30 02:09:25 PM PDT 24
Peak memory 205348 kb
Host smart-dd8646d1-94bc-4da5-a4e7-c29080f18ba6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777265629 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.1777265629
Directory /workspace/45.rv_dm_stress_all/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.3314569007
Short name T206
Test name
Test status
Simulation time 57686224 ps
CPU time 0.71 seconds
Started May 30 02:08:56 PM PDT 24
Finished May 30 02:08:58 PM PDT 24
Peak memory 205028 kb
Host smart-9ba8e1bf-11dc-4b72-bf0c-784d2577cef2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314569007 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.3314569007
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.2279069325
Short name T118
Test name
Test status
Simulation time 47805179 ps
CPU time 0.73 seconds
Started May 30 02:08:53 PM PDT 24
Finished May 30 02:08:55 PM PDT 24
Peak memory 205048 kb
Host smart-f20c7a03-3ee3-4d64-ae9e-a68088246672
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279069325 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.2279069325
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.2918265448
Short name T178
Test name
Test status
Simulation time 74155793 ps
CPU time 0.7 seconds
Started May 30 02:08:55 PM PDT 24
Finished May 30 02:08:57 PM PDT 24
Peak memory 204916 kb
Host smart-13e84256-7862-4bbc-b790-25a107b45b8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918265448 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.2918265448
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.3290236336
Short name T148
Test name
Test status
Simulation time 139900982 ps
CPU time 0.76 seconds
Started May 30 02:09:02 PM PDT 24
Finished May 30 02:09:04 PM PDT 24
Peak memory 205028 kb
Host smart-d510d9ce-4dc7-4637-9325-bfd27544f58e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290236336 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.3290236336
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.3056325176
Short name T144
Test name
Test status
Simulation time 46614230 ps
CPU time 0.7 seconds
Started May 30 02:07:36 PM PDT 24
Finished May 30 02:07:38 PM PDT 24
Peak memory 205024 kb
Host smart-9a27265f-b51a-404d-9f20-d23491c02430
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056325176 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.3056325176
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.4124117870
Short name T169
Test name
Test status
Simulation time 12397847379 ps
CPU time 21.17 seconds
Started May 30 02:07:33 PM PDT 24
Finished May 30 02:07:55 PM PDT 24
Peak memory 205580 kb
Host smart-9eeffdad-4a18-49f5-9074-833fcec5e850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124117870 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.4124117870
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_stress_all.1847849237
Short name T136
Test name
Test status
Simulation time 5812933985 ps
CPU time 11.23 seconds
Started May 30 02:07:28 PM PDT 24
Finished May 30 02:07:41 PM PDT 24
Peak memory 213600 kb
Host smart-82fa6463-113c-4d29-bb8e-1f5620b7b2ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847849237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.1847849237
Directory /workspace/5.rv_dm_stress_all/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.3902757454
Short name T154
Test name
Test status
Simulation time 160765514 ps
CPU time 0.96 seconds
Started May 30 02:08:27 PM PDT 24
Finished May 30 02:08:29 PM PDT 24
Peak memory 205004 kb
Host smart-dcc63dbd-e765-4a95-8b42-3ab633b4840b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902757454 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.3902757454
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.2343785198
Short name T179
Test name
Test status
Simulation time 143807123 ps
CPU time 0.87 seconds
Started May 30 02:08:27 PM PDT 24
Finished May 30 02:08:29 PM PDT 24
Peak memory 205024 kb
Host smart-d182bc4b-0e4c-4a4f-8052-8b42dda00960
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343785198 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.2343785198
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.3186854015
Short name T192
Test name
Test status
Simulation time 32349478908 ps
CPU time 105.52 seconds
Started May 30 02:08:32 PM PDT 24
Finished May 30 02:10:18 PM PDT 24
Peak memory 221892 kb
Host smart-42398923-b45b-4fcc-aea1-2f0c1ff7e064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186854015 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.3186854015
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.326812252
Short name T217
Test name
Test status
Simulation time 46684160321 ps
CPU time 70.07 seconds
Started May 30 02:08:30 PM PDT 24
Finished May 30 02:09:41 PM PDT 24
Peak memory 213740 kb
Host smart-72d4a2a3-04ea-4331-a6f4-63621dfde05d
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=326812252 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_tl
_access.326812252
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.373112260
Short name T181
Test name
Test status
Simulation time 8325282232 ps
CPU time 7.12 seconds
Started May 30 02:08:30 PM PDT 24
Finished May 30 02:08:38 PM PDT 24
Peak memory 205560 kb
Host smart-c96b61ef-e41a-48a8-a55d-ece40fcb0771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373112260 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.373112260
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.1801155377
Short name T152
Test name
Test status
Simulation time 60458919 ps
CPU time 0.73 seconds
Started May 30 02:08:38 PM PDT 24
Finished May 30 02:08:40 PM PDT 24
Peak memory 205040 kb
Host smart-3e283a60-cca0-47af-9792-5e5993a92adc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801155377 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.1801155377
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.3113522339
Short name T82
Test name
Test status
Simulation time 39645957029 ps
CPU time 94.65 seconds
Started May 30 02:08:32 PM PDT 24
Finished May 30 02:10:07 PM PDT 24
Peak memory 213628 kb
Host smart-ac2f6c9a-e402-4a42-9ee3-d1bfc4d8c7cf
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3113522339 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t
l_access.3113522339
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.2410607046
Short name T56
Test name
Test status
Simulation time 149038035 ps
CPU time 0.8 seconds
Started May 30 02:08:41 PM PDT 24
Finished May 30 02:08:44 PM PDT 24
Peak memory 205060 kb
Host smart-be3c00ad-bc5b-46b6-aa19-05b4bbf4bf64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410607046 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.2410607046
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.1323035797
Short name T205
Test name
Test status
Simulation time 11974566696 ps
CPU time 12.84 seconds
Started May 30 02:08:41 PM PDT 24
Finished May 30 02:08:55 PM PDT 24
Peak memory 205536 kb
Host smart-137bfcdd-6ff2-40ec-b549-89f7fb964874
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1323035797 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t
l_access.1323035797
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.962246266
Short name T191
Test name
Test status
Simulation time 45419908071 ps
CPU time 105.27 seconds
Started May 30 02:08:40 PM PDT 24
Finished May 30 02:10:27 PM PDT 24
Peak memory 205492 kb
Host smart-d699bed3-447a-4ab2-a924-c02035e4f5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962246266 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.962246266
Directory /workspace/9.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_stress_all.990920578
Short name T42
Test name
Test status
Simulation time 6731467861 ps
CPU time 3.59 seconds
Started May 30 02:08:38 PM PDT 24
Finished May 30 02:08:43 PM PDT 24
Peak memory 205392 kb
Host smart-cda9a775-25c5-47af-8236-de16355728ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990920578 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.990920578
Directory /workspace/9.rv_dm_stress_all/latest
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