Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
77.98 94.56 78.98 86.17 71.79 84.50 98.42 31.44


Total test records in report: 418
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html
T79 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.1971517484 Jun 04 12:51:21 PM PDT 24 Jun 04 12:51:27 PM PDT 24 100576550 ps
T93 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.3853041756 Jun 04 12:51:02 PM PDT 24 Jun 04 12:51:10 PM PDT 24 211520744 ps
T284 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.2915388313 Jun 04 12:51:11 PM PDT 24 Jun 04 12:51:16 PM PDT 24 181402998 ps
T285 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.4147048056 Jun 04 12:51:01 PM PDT 24 Jun 04 12:51:04 PM PDT 24 440097377 ps
T286 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.2027212054 Jun 04 12:51:01 PM PDT 24 Jun 04 12:51:03 PM PDT 24 397586545 ps
T287 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3035561512 Jun 04 12:51:11 PM PDT 24 Jun 04 12:51:28 PM PDT 24 7148620308 ps
T114 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2273221976 Jun 04 12:51:00 PM PDT 24 Jun 04 12:51:23 PM PDT 24 6891176694 ps
T113 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.4068415160 Jun 04 12:51:32 PM PDT 24 Jun 04 12:51:38 PM PDT 24 277942948 ps
T98 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.888968051 Jun 04 12:51:21 PM PDT 24 Jun 04 12:51:24 PM PDT 24 63981058 ps
T99 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.236653060 Jun 04 12:51:08 PM PDT 24 Jun 04 12:51:12 PM PDT 24 200560764 ps
T44 /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.3537060987 Jun 04 12:50:53 PM PDT 24 Jun 04 12:52:08 PM PDT 24 29120538027 ps
T288 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1948106953 Jun 04 12:51:04 PM PDT 24 Jun 04 12:51:08 PM PDT 24 1457117825 ps
T289 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.10825777 Jun 04 12:51:20 PM PDT 24 Jun 04 12:51:23 PM PDT 24 1280756480 ps
T290 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1426521529 Jun 04 12:50:53 PM PDT 24 Jun 04 12:50:59 PM PDT 24 3511569059 ps
T291 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.697617374 Jun 04 12:50:55 PM PDT 24 Jun 04 12:50:56 PM PDT 24 79024318 ps
T100 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.3086563156 Jun 04 12:51:01 PM PDT 24 Jun 04 12:51:56 PM PDT 24 1437725331 ps
T292 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.4257405466 Jun 04 12:51:21 PM PDT 24 Jun 04 12:51:27 PM PDT 24 1287407520 ps
T293 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.3260566223 Jun 04 12:51:36 PM PDT 24 Jun 04 12:51:40 PM PDT 24 601841762 ps
T294 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.3726717627 Jun 04 12:51:00 PM PDT 24 Jun 04 12:51:02 PM PDT 24 1214397265 ps
T295 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2380178529 Jun 04 12:51:01 PM PDT 24 Jun 04 12:51:06 PM PDT 24 389468000 ps
T104 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.2933304695 Jun 04 12:51:31 PM PDT 24 Jun 04 12:51:37 PM PDT 24 587523471 ps
T105 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.3150172555 Jun 04 12:51:23 PM PDT 24 Jun 04 12:51:32 PM PDT 24 1758774203 ps
T106 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.579797988 Jun 04 12:51:04 PM PDT 24 Jun 04 12:51:13 PM PDT 24 522390723 ps
T110 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.168226296 Jun 04 12:51:24 PM PDT 24 Jun 04 12:51:44 PM PDT 24 4225479353 ps
T296 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2235507222 Jun 04 12:50:51 PM PDT 24 Jun 04 12:50:57 PM PDT 24 1531020419 ps
T297 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.4030718910 Jun 04 12:51:01 PM PDT 24 Jun 04 12:51:03 PM PDT 24 34997188 ps
T298 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.364602906 Jun 04 12:51:08 PM PDT 24 Jun 04 12:51:16 PM PDT 24 1687725264 ps
T299 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.2948845720 Jun 04 12:51:06 PM PDT 24 Jun 04 12:51:13 PM PDT 24 207064826 ps
T300 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.2454424793 Jun 04 12:51:23 PM PDT 24 Jun 04 12:51:48 PM PDT 24 8416895022 ps
T301 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.3286157846 Jun 04 12:51:03 PM PDT 24 Jun 04 12:51:19 PM PDT 24 17148957303 ps
T302 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.3714169268 Jun 04 12:51:00 PM PDT 24 Jun 04 12:57:05 PM PDT 24 144103128727 ps
T303 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.1064701471 Jun 04 12:51:03 PM PDT 24 Jun 04 12:51:07 PM PDT 24 283719988 ps
T117 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.3846656381 Jun 04 12:51:02 PM PDT 24 Jun 04 12:51:25 PM PDT 24 6215953974 ps
T304 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1854226610 Jun 04 12:51:23 PM PDT 24 Jun 04 12:51:28 PM PDT 24 4509330548 ps
T111 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.935714777 Jun 04 12:51:27 PM PDT 24 Jun 04 12:51:32 PM PDT 24 3073585010 ps
T305 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2444998191 Jun 04 12:51:33 PM PDT 24 Jun 04 12:51:50 PM PDT 24 5115946676 ps
T86 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2103890762 Jun 04 12:51:02 PM PDT 24 Jun 04 12:51:07 PM PDT 24 3342952104 ps
T306 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.2458209002 Jun 04 12:51:00 PM PDT 24 Jun 04 12:51:21 PM PDT 24 7349968776 ps
T120 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.3469139430 Jun 04 12:51:13 PM PDT 24 Jun 04 12:51:34 PM PDT 24 2116755172 ps
T307 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.2038961564 Jun 04 12:51:17 PM PDT 24 Jun 04 12:51:33 PM PDT 24 8584281903 ps
T112 /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.3754447682 Jun 04 12:50:59 PM PDT 24 Jun 04 12:51:44 PM PDT 24 54617892762 ps
T308 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.2600953916 Jun 04 12:51:20 PM PDT 24 Jun 04 12:51:24 PM PDT 24 328959863 ps
T309 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3564884435 Jun 04 12:51:06 PM PDT 24 Jun 04 12:51:14 PM PDT 24 987654597 ps
T310 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.2301128157 Jun 04 12:51:01 PM PDT 24 Jun 04 12:51:12 PM PDT 24 8970393019 ps
T115 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1022408969 Jun 04 12:51:20 PM PDT 24 Jun 04 12:51:41 PM PDT 24 2021092122 ps
T121 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.287687465 Jun 04 12:51:31 PM PDT 24 Jun 04 12:51:53 PM PDT 24 7368926950 ps
T311 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.355675529 Jun 04 12:51:29 PM PDT 24 Jun 04 12:51:56 PM PDT 24 23908990533 ps
T94 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.1889109615 Jun 04 12:50:59 PM PDT 24 Jun 04 12:51:06 PM PDT 24 157149359 ps
T312 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.1777892816 Jun 04 12:51:04 PM PDT 24 Jun 04 12:51:07 PM PDT 24 148332222 ps
T313 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.1966884276 Jun 04 12:50:50 PM PDT 24 Jun 04 12:50:58 PM PDT 24 8188323979 ps
T123 /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.320310167 Jun 04 12:51:03 PM PDT 24 Jun 04 12:51:22 PM PDT 24 22391228918 ps
T314 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.2755077798 Jun 04 12:50:55 PM PDT 24 Jun 04 12:50:56 PM PDT 24 553919495 ps
T87 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2780271455 Jun 04 12:51:02 PM PDT 24 Jun 04 12:51:06 PM PDT 24 1966758084 ps
T315 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1768212035 Jun 04 12:51:01 PM PDT 24 Jun 04 12:51:03 PM PDT 24 449988492 ps
T316 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.483203775 Jun 04 12:51:30 PM PDT 24 Jun 04 12:51:56 PM PDT 24 2903874378 ps
T317 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.4261668200 Jun 04 12:51:21 PM PDT 24 Jun 04 12:51:23 PM PDT 24 750808236 ps
T318 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.4000013928 Jun 04 12:51:01 PM PDT 24 Jun 04 12:52:47 PM PDT 24 53072287397 ps
T118 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2948962318 Jun 04 12:51:33 PM PDT 24 Jun 04 12:51:45 PM PDT 24 2530320953 ps
T319 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2147455176 Jun 04 12:50:58 PM PDT 24 Jun 04 12:51:31 PM PDT 24 6966869985 ps
T320 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3156089764 Jun 04 12:51:15 PM PDT 24 Jun 04 12:51:20 PM PDT 24 376356458 ps
T321 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1522036552 Jun 04 12:51:12 PM PDT 24 Jun 04 12:51:15 PM PDT 24 381335392 ps
T102 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2973786083 Jun 04 12:50:55 PM PDT 24 Jun 04 12:50:57 PM PDT 24 190550700 ps
T322 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.4268884803 Jun 04 12:51:20 PM PDT 24 Jun 04 12:51:22 PM PDT 24 310644115 ps
T101 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.208195904 Jun 04 12:50:58 PM PDT 24 Jun 04 12:52:31 PM PDT 24 52180128830 ps
T323 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1937424569 Jun 04 12:51:40 PM PDT 24 Jun 04 12:51:45 PM PDT 24 276045397 ps
T324 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.355269972 Jun 04 12:51:04 PM PDT 24 Jun 04 12:51:14 PM PDT 24 3816451046 ps
T325 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3884149610 Jun 04 12:51:15 PM PDT 24 Jun 04 12:51:49 PM PDT 24 15134909994 ps
T326 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.3751043483 Jun 04 12:51:24 PM PDT 24 Jun 04 12:51:29 PM PDT 24 277107772 ps
T327 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.1766182082 Jun 04 12:51:28 PM PDT 24 Jun 04 12:51:35 PM PDT 24 551686568 ps
T328 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.4139639239 Jun 04 12:51:09 PM PDT 24 Jun 04 12:51:13 PM PDT 24 400110480 ps
T103 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2883670212 Jun 04 12:50:58 PM PDT 24 Jun 04 12:52:09 PM PDT 24 7328927558 ps
T95 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2922491402 Jun 04 12:51:03 PM PDT 24 Jun 04 12:51:09 PM PDT 24 395059050 ps
T96 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2720058959 Jun 04 12:51:03 PM PDT 24 Jun 04 12:51:07 PM PDT 24 315607484 ps
T329 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.4101207022 Jun 04 12:51:08 PM PDT 24 Jun 04 12:51:11 PM PDT 24 137882213 ps
T330 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.1673664741 Jun 04 12:51:17 PM PDT 24 Jun 04 12:51:20 PM PDT 24 640433334 ps
T331 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2538100199 Jun 04 12:51:04 PM PDT 24 Jun 04 12:51:07 PM PDT 24 278824133 ps
T332 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1529901170 Jun 04 12:51:09 PM PDT 24 Jun 04 12:51:13 PM PDT 24 89386291 ps
T333 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1516200681 Jun 04 12:51:37 PM PDT 24 Jun 04 12:51:46 PM PDT 24 4364204007 ps
T334 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.423222028 Jun 04 12:51:03 PM PDT 24 Jun 04 12:51:15 PM PDT 24 684971391 ps
T335 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3358449759 Jun 04 12:51:30 PM PDT 24 Jun 04 12:51:34 PM PDT 24 451323770 ps
T336 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.1091101264 Jun 04 12:50:54 PM PDT 24 Jun 04 12:51:04 PM PDT 24 1863104803 ps
T337 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2725805181 Jun 04 12:51:09 PM PDT 24 Jun 04 12:51:13 PM PDT 24 495799774 ps
T338 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2714559428 Jun 04 12:51:02 PM PDT 24 Jun 04 12:51:07 PM PDT 24 2552721771 ps
T339 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3257096921 Jun 04 12:51:08 PM PDT 24 Jun 04 12:51:14 PM PDT 24 5843303620 ps
T340 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2659600738 Jun 04 12:51:33 PM PDT 24 Jun 04 12:51:52 PM PDT 24 16379268028 ps
T341 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.3298858119 Jun 04 12:51:10 PM PDT 24 Jun 04 12:51:14 PM PDT 24 180482860 ps
T88 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.3043972092 Jun 04 12:51:00 PM PDT 24 Jun 04 12:51:09 PM PDT 24 10902761978 ps
T342 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.2426191741 Jun 04 12:51:03 PM PDT 24 Jun 04 12:51:08 PM PDT 24 829067452 ps
T343 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2752171559 Jun 04 12:51:29 PM PDT 24 Jun 04 12:51:34 PM PDT 24 105501431 ps
T344 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.2906322562 Jun 04 12:51:22 PM PDT 24 Jun 04 12:51:33 PM PDT 24 13103615139 ps
T345 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.300423388 Jun 04 12:50:52 PM PDT 24 Jun 04 12:51:26 PM PDT 24 3425012432 ps
T346 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.4188471864 Jun 04 12:51:19 PM PDT 24 Jun 04 12:51:23 PM PDT 24 236211236 ps
T119 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.179167438 Jun 04 12:51:05 PM PDT 24 Jun 04 12:51:22 PM PDT 24 2109917677 ps
T347 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1994639420 Jun 04 12:51:01 PM PDT 24 Jun 04 12:51:25 PM PDT 24 8099890632 ps
T348 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.1515621146 Jun 04 12:51:32 PM PDT 24 Jun 04 12:51:37 PM PDT 24 279727047 ps
T349 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.3217277806 Jun 04 12:51:03 PM PDT 24 Jun 04 12:51:11 PM PDT 24 710310197 ps
T350 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2956382340 Jun 04 12:50:53 PM PDT 24 Jun 04 12:50:55 PM PDT 24 162735792 ps
T351 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.278897394 Jun 04 12:51:11 PM PDT 24 Jun 04 12:51:16 PM PDT 24 86126401 ps
T352 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.1833673887 Jun 04 12:51:31 PM PDT 24 Jun 04 12:51:34 PM PDT 24 145103400 ps
T116 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.1386369891 Jun 04 12:51:30 PM PDT 24 Jun 04 12:51:50 PM PDT 24 3266814092 ps
T353 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.475232451 Jun 04 12:51:18 PM PDT 24 Jun 04 12:51:24 PM PDT 24 256571632 ps
T354 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3626174430 Jun 04 12:51:00 PM PDT 24 Jun 04 12:51:03 PM PDT 24 1821406347 ps
T355 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.9539479 Jun 04 12:51:20 PM PDT 24 Jun 04 12:51:47 PM PDT 24 5314518063 ps
T124 /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.2942215957 Jun 04 12:51:02 PM PDT 24 Jun 04 12:51:57 PM PDT 24 60283142471 ps
T356 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2189265230 Jun 04 12:51:05 PM PDT 24 Jun 04 12:51:10 PM PDT 24 2864189212 ps
T357 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.1312924221 Jun 04 12:51:00 PM PDT 24 Jun 04 12:51:12 PM PDT 24 7219838169 ps
T358 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.3334088858 Jun 04 12:51:03 PM PDT 24 Jun 04 12:51:37 PM PDT 24 1759420636 ps
T359 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1794014167 Jun 04 12:51:02 PM PDT 24 Jun 04 12:51:04 PM PDT 24 76776984 ps
T360 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.1826859866 Jun 04 12:51:31 PM PDT 24 Jun 04 12:51:34 PM PDT 24 208157731 ps
T361 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.2717987514 Jun 04 12:51:01 PM PDT 24 Jun 04 12:51:02 PM PDT 24 41028354 ps
T362 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.3418925666 Jun 04 12:51:10 PM PDT 24 Jun 04 12:51:31 PM PDT 24 4007512189 ps
T363 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.1872301702 Jun 04 12:51:20 PM PDT 24 Jun 04 12:51:27 PM PDT 24 557761398 ps
T364 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.235053198 Jun 04 12:51:09 PM PDT 24 Jun 04 12:51:15 PM PDT 24 627028617 ps
T365 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.1604958249 Jun 04 12:51:13 PM PDT 24 Jun 04 12:51:16 PM PDT 24 792691030 ps
T366 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3788676327 Jun 04 12:51:31 PM PDT 24 Jun 04 12:51:36 PM PDT 24 1079561136 ps
T367 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.1359938545 Jun 04 12:51:02 PM PDT 24 Jun 04 12:51:13 PM PDT 24 4325436416 ps
T368 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2407613743 Jun 04 12:51:24 PM PDT 24 Jun 04 12:51:25 PM PDT 24 205540890 ps
T369 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.3668515101 Jun 04 12:51:22 PM PDT 24 Jun 04 12:51:27 PM PDT 24 971200825 ps
T370 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.2123769257 Jun 04 12:50:51 PM PDT 24 Jun 04 12:50:54 PM PDT 24 147673803 ps
T371 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1859560645 Jun 04 12:51:21 PM PDT 24 Jun 04 12:51:25 PM PDT 24 2237114994 ps
T372 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.3818393634 Jun 04 12:51:05 PM PDT 24 Jun 04 12:52:18 PM PDT 24 26694827529 ps
T373 /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.3664642752 Jun 04 12:51:01 PM PDT 24 Jun 04 12:52:54 PM PDT 24 36202822563 ps
T374 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.4119800693 Jun 04 12:51:11 PM PDT 24 Jun 04 12:51:22 PM PDT 24 5003688352 ps
T375 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.4156232367 Jun 04 12:51:29 PM PDT 24 Jun 04 12:51:35 PM PDT 24 3481844172 ps
T376 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.575748459 Jun 04 12:51:32 PM PDT 24 Jun 04 12:51:38 PM PDT 24 1495918691 ps
T377 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.3017307570 Jun 04 12:51:04 PM PDT 24 Jun 04 12:51:17 PM PDT 24 10931117914 ps
T378 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.2288125104 Jun 04 12:51:00 PM PDT 24 Jun 04 12:51:24 PM PDT 24 13345025195 ps
T379 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.147680527 Jun 04 12:51:02 PM PDT 24 Jun 04 12:51:07 PM PDT 24 202586226 ps
T380 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.1248323897 Jun 04 12:51:04 PM PDT 24 Jun 04 12:52:17 PM PDT 24 5135330977 ps
T381 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2180135160 Jun 04 12:51:09 PM PDT 24 Jun 04 12:51:20 PM PDT 24 567782442 ps
T382 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.4275281593 Jun 04 12:51:00 PM PDT 24 Jun 04 12:53:18 PM PDT 24 90869899619 ps
T383 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.4280410022 Jun 04 12:50:55 PM PDT 24 Jun 04 12:50:56 PM PDT 24 762133956 ps
T384 /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.826084566 Jun 04 12:51:17 PM PDT 24 Jun 04 12:51:28 PM PDT 24 26864458594 ps
T385 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.1323678552 Jun 04 12:51:14 PM PDT 24 Jun 04 12:51:19 PM PDT 24 296034450 ps
T386 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.2562357667 Jun 04 12:51:06 PM PDT 24 Jun 04 12:51:11 PM PDT 24 2850827210 ps
T387 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.4121647328 Jun 04 12:51:21 PM PDT 24 Jun 04 12:51:23 PM PDT 24 164193230 ps
T388 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.787466367 Jun 04 12:51:35 PM PDT 24 Jun 04 12:54:07 PM PDT 24 55245278945 ps
T389 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3621271793 Jun 04 12:50:51 PM PDT 24 Jun 04 12:51:14 PM PDT 24 103404182842 ps
T390 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.190171825 Jun 04 12:51:39 PM PDT 24 Jun 04 12:51:43 PM PDT 24 937280271 ps
T391 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.182894295 Jun 04 12:51:00 PM PDT 24 Jun 04 12:51:07 PM PDT 24 3110825425 ps
T392 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.2363394659 Jun 04 12:51:10 PM PDT 24 Jun 04 12:51:25 PM PDT 24 8566194276 ps
T393 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.4195581515 Jun 04 12:50:53 PM PDT 24 Jun 04 12:51:27 PM PDT 24 14402098295 ps
T394 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3437006593 Jun 04 12:51:02 PM PDT 24 Jun 04 12:51:06 PM PDT 24 360793335 ps
T395 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.1545132072 Jun 04 12:51:13 PM PDT 24 Jun 04 12:51:21 PM PDT 24 2733653698 ps
T396 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.3333257742 Jun 04 12:51:13 PM PDT 24 Jun 04 12:51:17 PM PDT 24 965460473 ps
T397 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.612044845 Jun 04 12:50:50 PM PDT 24 Jun 04 12:51:23 PM PDT 24 22172129345 ps
T398 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2219523066 Jun 04 12:51:03 PM PDT 24 Jun 04 12:51:06 PM PDT 24 62370091 ps
T399 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.2349840357 Jun 04 12:51:02 PM PDT 24 Jun 04 12:51:06 PM PDT 24 227094290 ps
T400 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.1420692899 Jun 04 12:51:01 PM PDT 24 Jun 04 12:51:03 PM PDT 24 108530189 ps
T401 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2547651359 Jun 04 12:51:00 PM PDT 24 Jun 04 12:51:12 PM PDT 24 7694985129 ps
T402 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.634927122 Jun 04 12:51:04 PM PDT 24 Jun 04 12:53:31 PM PDT 24 98496614296 ps
T403 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.2482048735 Jun 04 12:51:02 PM PDT 24 Jun 04 12:51:15 PM PDT 24 3813013511 ps
T404 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.1814284746 Jun 04 12:51:02 PM PDT 24 Jun 04 12:51:08 PM PDT 24 1135422720 ps
T405 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.3391942504 Jun 04 12:51:04 PM PDT 24 Jun 04 12:51:09 PM PDT 24 224581458 ps
T406 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.227137553 Jun 04 12:51:04 PM PDT 24 Jun 04 12:51:09 PM PDT 24 756536288 ps
T407 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.2511530793 Jun 04 12:50:58 PM PDT 24 Jun 04 12:51:00 PM PDT 24 61187429 ps
T408 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1443139710 Jun 04 12:51:03 PM PDT 24 Jun 04 12:51:06 PM PDT 24 31807286 ps
T409 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3440449091 Jun 04 12:51:10 PM PDT 24 Jun 04 12:51:17 PM PDT 24 2152730875 ps
T410 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3885977920 Jun 04 12:51:04 PM PDT 24 Jun 04 12:51:09 PM PDT 24 303869649 ps
T411 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1489691939 Jun 04 12:51:30 PM PDT 24 Jun 04 12:51:36 PM PDT 24 375126669 ps
T412 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2294013292 Jun 04 12:51:03 PM PDT 24 Jun 04 12:51:07 PM PDT 24 118471161 ps
T413 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.600816292 Jun 04 12:51:13 PM PDT 24 Jun 04 12:51:59 PM PDT 24 31080070310 ps
T122 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.4021240732 Jun 04 12:51:19 PM PDT 24 Jun 04 12:51:31 PM PDT 24 3054439999 ps
T414 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.59169217 Jun 04 12:51:06 PM PDT 24 Jun 04 12:51:18 PM PDT 24 6240591582 ps
T415 /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.1152996181 Jun 04 12:51:02 PM PDT 24 Jun 04 12:51:22 PM PDT 24 17323464704 ps
T416 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.3696498995 Jun 04 12:51:32 PM PDT 24 Jun 04 12:51:35 PM PDT 24 292641409 ps
T417 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1849133206 Jun 04 12:51:04 PM PDT 24 Jun 04 12:51:18 PM PDT 24 17197208525 ps
T418 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.931069176 Jun 04 12:50:54 PM PDT 24 Jun 04 12:50:57 PM PDT 24 488686019 ps

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.2941061956
Short name T5
Test name
Test status
Simulation time 2105217710 ps
CPU time 2.65 seconds
Started Jun 04 12:53:58 PM PDT 24
Finished Jun 04 12:54:01 PM PDT 24
Peak memory 202800 kb
Host smart-4eb88b4a-dab1-44e5-88c7-e2c06e77e0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941061956 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.2941061956
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_stress_all.4125687434
Short name T9
Test name
Test status
Simulation time 10061449189 ps
CPU time 4.3 seconds
Started Jun 04 12:52:49 PM PDT 24
Finished Jun 04 12:52:55 PM PDT 24
Peak memory 205032 kb
Host smart-d9915081-f1d2-433a-8a57-67f7c025eda5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125687434 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.4125687434
Directory /workspace/15.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.3920635136
Short name T48
Test name
Test status
Simulation time 7965790614 ps
CPU time 17.9 seconds
Started Jun 04 12:51:07 PM PDT 24
Finished Jun 04 12:51:26 PM PDT 24
Peak memory 213444 kb
Host smart-bb90abcd-2433-412e-b557-90c472367f57
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920635136 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.3
920635136
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.2290834973
Short name T43
Test name
Test status
Simulation time 29426268227 ps
CPU time 27.35 seconds
Started Jun 04 12:51:16 PM PDT 24
Finished Jun 04 12:51:44 PM PDT 24
Peak memory 221072 kb
Host smart-c1049913-d5ad-4883-a762-c537b8a59c61
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290834973 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.2290834973
Directory /workspace/9.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.295858728
Short name T62
Test name
Test status
Simulation time 71585557 ps
CPU time 0.76 seconds
Started Jun 04 12:52:47 PM PDT 24
Finished Jun 04 12:52:49 PM PDT 24
Peak memory 204840 kb
Host smart-f02bee62-3b6c-4d00-9793-97b9e132cd1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295858728 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.295858728
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.2357938590
Short name T15
Test name
Test status
Simulation time 34135534408 ps
CPU time 50.36 seconds
Started Jun 04 12:52:47 PM PDT 24
Finished Jun 04 12:53:39 PM PDT 24
Peak memory 213344 kb
Host smart-b580b6c6-3b40-4b47-9287-6aa1a3585c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357938590 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.2357938590
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_stress_all.2734266378
Short name T10
Test name
Test status
Simulation time 27773397439 ps
CPU time 36.08 seconds
Started Jun 04 12:53:06 PM PDT 24
Finished Jun 04 12:53:43 PM PDT 24
Peak memory 205080 kb
Host smart-2eaa2d35-714b-41a2-b47c-b8d34895b241
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734266378 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.2734266378
Directory /workspace/18.rv_dm_stress_all/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.1016304055
Short name T176
Test name
Test status
Simulation time 47793027766 ps
CPU time 87.19 seconds
Started Jun 04 12:53:00 PM PDT 24
Finished Jun 04 12:54:29 PM PDT 24
Peak memory 213328 kb
Host smart-b943e5c6-9fa9-4bf5-8f98-8c8d66e72741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016304055 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.1016304055
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3617436341
Short name T70
Test name
Test status
Simulation time 4820011286 ps
CPU time 70.76 seconds
Started Jun 04 12:50:53 PM PDT 24
Finished Jun 04 12:52:05 PM PDT 24
Peak memory 205056 kb
Host smart-bcaf08c1-d520-4f4c-86e0-a87b5b542bc7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617436341 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.3617436341
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all.4062963606
Short name T125
Test name
Test status
Simulation time 13633554637 ps
CPU time 12.75 seconds
Started Jun 04 12:52:38 PM PDT 24
Finished Jun 04 12:52:51 PM PDT 24
Peak memory 205060 kb
Host smart-5d4cba77-6823-4057-b7bc-cc882973a580
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062963606 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.4062963606
Directory /workspace/2.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.3352993485
Short name T25
Test name
Test status
Simulation time 7929113061 ps
CPU time 13.82 seconds
Started Jun 04 12:52:34 PM PDT 24
Finished Jun 04 12:52:49 PM PDT 24
Peak memory 204944 kb
Host smart-659e4e67-884e-47a1-8dde-48985526bdb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352993485 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.3352993485
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.3693458042
Short name T2
Test name
Test status
Simulation time 2526546010 ps
CPU time 1.73 seconds
Started Jun 04 12:53:00 PM PDT 24
Finished Jun 04 12:53:03 PM PDT 24
Peak memory 229208 kb
Host smart-863bf667-0d87-4eab-92c0-4240d4b1a8c4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693458042 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.3693458042
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.2807500254
Short name T34
Test name
Test status
Simulation time 237764853 ps
CPU time 0.77 seconds
Started Jun 04 12:52:49 PM PDT 24
Finished Jun 04 12:52:52 PM PDT 24
Peak memory 204708 kb
Host smart-6ee9b95b-b35c-481c-bcc3-4eef49098ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807500254 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.2807500254
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.1296022915
Short name T92
Test name
Test status
Simulation time 401833331 ps
CPU time 3.33 seconds
Started Jun 04 12:51:03 PM PDT 24
Finished Jun 04 12:51:09 PM PDT 24
Peak memory 213504 kb
Host smart-a0d77086-a06e-4be9-bd1e-a111b2a46963
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296022915 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.1296022915
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.89707028
Short name T1
Test name
Test status
Simulation time 41458532 ps
CPU time 0.79 seconds
Started Jun 04 12:52:47 PM PDT 24
Finished Jun 04 12:52:49 PM PDT 24
Peak memory 212920 kb
Host smart-f306f0fb-bf49-4c48-ab92-80155a05f699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89707028 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.89707028
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.3848583141
Short name T36
Test name
Test status
Simulation time 317911242 ps
CPU time 0.8 seconds
Started Jun 04 12:52:37 PM PDT 24
Finished Jun 04 12:52:39 PM PDT 24
Peak memory 204620 kb
Host smart-9c2fa60f-5bc3-4bd8-8061-95efba747764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848583141 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.3848583141
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.1767027441
Short name T46
Test name
Test status
Simulation time 2411759818 ps
CPU time 18.86 seconds
Started Jun 04 12:51:06 PM PDT 24
Finished Jun 04 12:51:27 PM PDT 24
Peak memory 213292 kb
Host smart-dec221ce-7cb9-462a-b5e7-3dddfa9387f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767027441 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.1
767027441
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.1378671584
Short name T24
Test name
Test status
Simulation time 998821200 ps
CPU time 1.6 seconds
Started Jun 04 12:52:46 PM PDT 24
Finished Jun 04 12:52:49 PM PDT 24
Peak memory 204720 kb
Host smart-03b9e1af-58df-4f7e-87a2-5b723c469ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378671584 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.1378671584
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.520162314
Short name T66
Test name
Test status
Simulation time 185191602 ps
CPU time 0.84 seconds
Started Jun 04 12:53:05 PM PDT 24
Finished Jun 04 12:53:08 PM PDT 24
Peak memory 204844 kb
Host smart-a1b500c4-bd7c-4206-8729-50253c9a9964
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520162314 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.520162314
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.1971517484
Short name T79
Test name
Test status
Simulation time 100576550 ps
CPU time 4.91 seconds
Started Jun 04 12:51:21 PM PDT 24
Finished Jun 04 12:51:27 PM PDT 24
Peak memory 213324 kb
Host smart-31317bbb-dc91-4f78-84d8-af8946e62e53
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971517484 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.1971517484
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.4009320699
Short name T55
Test name
Test status
Simulation time 132383429 ps
CPU time 1.01 seconds
Started Jun 04 12:50:53 PM PDT 24
Finished Jun 04 12:50:54 PM PDT 24
Peak memory 204488 kb
Host smart-36624d9c-9c30-43fa-8752-744fe564749b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009320699 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.4
009320699
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.710913198
Short name T8
Test name
Test status
Simulation time 570235331 ps
CPU time 0.94 seconds
Started Jun 04 12:53:00 PM PDT 24
Finished Jun 04 12:53:02 PM PDT 24
Peak memory 204708 kb
Host smart-ddedda98-8e4a-48ca-91e3-9c6b37b57e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710913198 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.710913198
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2040071176
Short name T77
Test name
Test status
Simulation time 219097661 ps
CPU time 4.03 seconds
Started Jun 04 12:50:53 PM PDT 24
Finished Jun 04 12:50:58 PM PDT 24
Peak memory 205008 kb
Host smart-1da206a8-3f4a-426a-8050-67a6c01fc551
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040071176 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.2040071176
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2103890762
Short name T86
Test name
Test status
Simulation time 3342952104 ps
CPU time 3.13 seconds
Started Jun 04 12:51:02 PM PDT 24
Finished Jun 04 12:51:07 PM PDT 24
Peak memory 205040 kb
Host smart-721b3a8c-7b8d-467a-bfe2-e8667c080d6c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103890762 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.2103890762
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.4221157064
Short name T30
Test name
Test status
Simulation time 329602797 ps
CPU time 1.61 seconds
Started Jun 04 12:52:55 PM PDT 24
Finished Jun 04 12:52:58 PM PDT 24
Peak memory 204564 kb
Host smart-2b6b583d-90cb-4f94-b7f6-772f6477305e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221157064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.4221157064
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.792378756
Short name T32
Test name
Test status
Simulation time 2325149745 ps
CPU time 2.6 seconds
Started Jun 04 12:52:56 PM PDT 24
Finished Jun 04 12:53:00 PM PDT 24
Peak memory 205052 kb
Host smart-9ca952e1-c462-4271-888e-999e4105f348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792378756 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.792378756
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2720058959
Short name T96
Test name
Test status
Simulation time 315607484 ps
CPU time 2.2 seconds
Started Jun 04 12:51:03 PM PDT 24
Finished Jun 04 12:51:07 PM PDT 24
Peak memory 213136 kb
Host smart-d9c9b679-412e-4859-9fae-e3a0a8523c8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720058959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.2720058959
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.3537060987
Short name T44
Test name
Test status
Simulation time 29120538027 ps
CPU time 74.93 seconds
Started Jun 04 12:50:53 PM PDT 24
Finished Jun 04 12:52:08 PM PDT 24
Peak memory 221436 kb
Host smart-690f171b-8465-47c3-b8cf-2e3076370d1d
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537060987 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.3537060987
Directory /workspace/0.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.3754447682
Short name T112
Test name
Test status
Simulation time 54617892762 ps
CPU time 44.47 seconds
Started Jun 04 12:50:59 PM PDT 24
Finished Jun 04 12:51:44 PM PDT 24
Peak memory 221652 kb
Host smart-40972eb9-8516-4630-833d-477ae2d332e1
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754447682 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.3754447682
Directory /workspace/1.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.168226296
Short name T110
Test name
Test status
Simulation time 4225479353 ps
CPU time 19.87 seconds
Started Jun 04 12:51:24 PM PDT 24
Finished Jun 04 12:51:44 PM PDT 24
Peak memory 213312 kb
Host smart-a92c8a96-fb6d-4848-a673-3314c78c5973
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168226296 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.168226296
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.9539479
Short name T355
Test name
Test status
Simulation time 5314518063 ps
CPU time 26.24 seconds
Started Jun 04 12:51:20 PM PDT 24
Finished Jun 04 12:51:47 PM PDT 24
Peak memory 213328 kb
Host smart-81e1733e-dc9c-4d6e-bef2-605dc374ea4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9539479 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.9539479
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.440430407
Short name T16
Test name
Test status
Simulation time 5345858863 ps
CPU time 2.76 seconds
Started Jun 04 12:52:37 PM PDT 24
Finished Jun 04 12:52:41 PM PDT 24
Peak memory 214776 kb
Host smart-9892cd2b-8840-4b26-82ba-0b38d0eecd85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440430407 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.440430407
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.1845475798
Short name T91
Test name
Test status
Simulation time 9875066122 ps
CPU time 65.48 seconds
Started Jun 04 12:50:54 PM PDT 24
Finished Jun 04 12:52:00 PM PDT 24
Peak memory 205016 kb
Host smart-0c040ff3-f646-4df0-8fbf-87309684aef4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845475798 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.1845475798
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.931069176
Short name T418
Test name
Test status
Simulation time 488686019 ps
CPU time 2.42 seconds
Started Jun 04 12:50:54 PM PDT 24
Finished Jun 04 12:50:57 PM PDT 24
Peak memory 213384 kb
Host smart-86e771a3-82ed-419c-93d2-1f01db50a675
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931069176 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.931069176
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1426521529
Short name T290
Test name
Test status
Simulation time 3511569059 ps
CPU time 5.71 seconds
Started Jun 04 12:50:53 PM PDT 24
Finished Jun 04 12:50:59 PM PDT 24
Peak memory 220328 kb
Host smart-8256d6c6-48f9-4328-9a9b-30c65df3735a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426521529 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.1426521529
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2973786083
Short name T102
Test name
Test status
Simulation time 190550700 ps
CPU time 1.51 seconds
Started Jun 04 12:50:55 PM PDT 24
Finished Jun 04 12:50:57 PM PDT 24
Peak memory 213136 kb
Host smart-12eced62-57da-482a-902d-ad731673bf75
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973786083 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.2973786083
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3621271793
Short name T389
Test name
Test status
Simulation time 103404182842 ps
CPU time 22.58 seconds
Started Jun 04 12:50:51 PM PDT 24
Finished Jun 04 12:51:14 PM PDT 24
Peak memory 204944 kb
Host smart-b6bcbd6b-4d8c-4d3e-9a02-6afa4797ac2e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621271793 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.3621271793
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.612044845
Short name T397
Test name
Test status
Simulation time 22172129345 ps
CPU time 32.16 seconds
Started Jun 04 12:50:50 PM PDT 24
Finished Jun 04 12:51:23 PM PDT 24
Peak memory 204892 kb
Host smart-49261f6f-08e3-4cf8-9402-0dc092f1143b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612044845 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.r
v_dm_jtag_dmi_csr_bit_bash.612044845
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.1966884276
Short name T313
Test name
Test status
Simulation time 8188323979 ps
CPU time 7.1 seconds
Started Jun 04 12:50:50 PM PDT 24
Finished Jun 04 12:50:58 PM PDT 24
Peak memory 205136 kb
Host smart-c29a0b86-9054-4a23-8d35-eacbb6600e33
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966884276 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.1966884276
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2673451436
Short name T277
Test name
Test status
Simulation time 4803999003 ps
CPU time 3.86 seconds
Started Jun 04 12:50:52 PM PDT 24
Finished Jun 04 12:50:56 PM PDT 24
Peak memory 204996 kb
Host smart-b6aef648-b765-4930-9521-ead87b733644
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673451436 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.2
673451436
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.4280410022
Short name T383
Test name
Test status
Simulation time 762133956 ps
CPU time 0.83 seconds
Started Jun 04 12:50:55 PM PDT 24
Finished Jun 04 12:50:56 PM PDT 24
Peak memory 204592 kb
Host smart-5cc623f2-bff4-45d9-9098-59d561607ac9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280410022 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.4280410022
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.4195581515
Short name T393
Test name
Test status
Simulation time 14402098295 ps
CPU time 32.97 seconds
Started Jun 04 12:50:53 PM PDT 24
Finished Jun 04 12:51:27 PM PDT 24
Peak memory 205044 kb
Host smart-83723792-5979-460c-bb63-beb59ace74d8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195581515 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.4195581515
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2956382340
Short name T350
Test name
Test status
Simulation time 162735792 ps
CPU time 1.12 seconds
Started Jun 04 12:50:53 PM PDT 24
Finished Jun 04 12:50:55 PM PDT 24
Peak memory 204680 kb
Host smart-8ec55505-ad7b-469b-8a59-e7cadb265805
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956382340 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.2956382340
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.2755077798
Short name T314
Test name
Test status
Simulation time 553919495 ps
CPU time 0.79 seconds
Started Jun 04 12:50:55 PM PDT 24
Finished Jun 04 12:50:56 PM PDT 24
Peak memory 204652 kb
Host smart-a1046517-1cf7-4820-a5e7-befffa73d3b6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755077798 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.2
755077798
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.697617374
Short name T291
Test name
Test status
Simulation time 79024318 ps
CPU time 0.71 seconds
Started Jun 04 12:50:55 PM PDT 24
Finished Jun 04 12:50:56 PM PDT 24
Peak memory 204696 kb
Host smart-696afb97-570b-4e5f-9d8f-534d3a769cbd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697617374 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_part
ial_access.697617374
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.2805617736
Short name T281
Test name
Test status
Simulation time 66421737 ps
CPU time 0.8 seconds
Started Jun 04 12:50:51 PM PDT 24
Finished Jun 04 12:50:52 PM PDT 24
Peak memory 204644 kb
Host smart-e93bd8c6-18f1-425b-add2-3222d71c3e70
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805617736 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.2805617736
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.2123769257
Short name T370
Test name
Test status
Simulation time 147673803 ps
CPU time 2.06 seconds
Started Jun 04 12:50:51 PM PDT 24
Finished Jun 04 12:50:54 PM PDT 24
Peak memory 213188 kb
Host smart-eafa0f4d-f3e8-4da1-a680-71af71a6074f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123769257 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.2123769257
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.1091101264
Short name T336
Test name
Test status
Simulation time 1863104803 ps
CPU time 10.15 seconds
Started Jun 04 12:50:54 PM PDT 24
Finished Jun 04 12:51:04 PM PDT 24
Peak memory 213272 kb
Host smart-182c7026-14aa-4fd4-84eb-61dc5ef283e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091101264 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.1091101264
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.300423388
Short name T345
Test name
Test status
Simulation time 3425012432 ps
CPU time 33.16 seconds
Started Jun 04 12:50:52 PM PDT 24
Finished Jun 04 12:51:26 PM PDT 24
Peak memory 213308 kb
Host smart-0e0e14a8-873c-4336-b6e8-3cedaa156cce
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300423388 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.rv_dm_csr_aliasing.300423388
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2883670212
Short name T103
Test name
Test status
Simulation time 7328927558 ps
CPU time 69.75 seconds
Started Jun 04 12:50:58 PM PDT 24
Finished Jun 04 12:52:09 PM PDT 24
Peak memory 205108 kb
Host smart-cb420aa0-df87-4480-908d-360d823285ef
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883670212 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.2883670212
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.3391942504
Short name T405
Test name
Test status
Simulation time 224581458 ps
CPU time 2.75 seconds
Started Jun 04 12:51:04 PM PDT 24
Finished Jun 04 12:51:09 PM PDT 24
Peak memory 213264 kb
Host smart-4ef03f96-08b3-45ce-88ff-474dc450d07b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391942504 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.3391942504
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.1359938545
Short name T367
Test name
Test status
Simulation time 4325436416 ps
CPU time 8.54 seconds
Started Jun 04 12:51:02 PM PDT 24
Finished Jun 04 12:51:13 PM PDT 24
Peak memory 218428 kb
Host smart-05b8bd1c-046e-4ed5-b03a-47fd4a25b467
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359938545 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.1359938545
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.4000013928
Short name T318
Test name
Test status
Simulation time 53072287397 ps
CPU time 105.4 seconds
Started Jun 04 12:51:01 PM PDT 24
Finished Jun 04 12:52:47 PM PDT 24
Peak memory 205072 kb
Host smart-7d459466-8f8a-4aea-bade-f0955b22d254
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000013928 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.4000013928
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2714559428
Short name T338
Test name
Test status
Simulation time 2552721771 ps
CPU time 3.41 seconds
Started Jun 04 12:51:02 PM PDT 24
Finished Jun 04 12:51:07 PM PDT 24
Peak memory 204968 kb
Host smart-943b8082-33da-45ae-943c-5f3c979dda57
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714559428 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
rv_dm_jtag_dmi_csr_bit_bash.2714559428
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1849133206
Short name T417
Test name
Test status
Simulation time 17197208525 ps
CPU time 11.74 seconds
Started Jun 04 12:51:04 PM PDT 24
Finished Jun 04 12:51:18 PM PDT 24
Peak memory 204956 kb
Host smart-6bbddc7a-4490-4e60-ab28-7b14d30e4241
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849133206 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.1
849133206
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3626174430
Short name T354
Test name
Test status
Simulation time 1821406347 ps
CPU time 1.36 seconds
Started Jun 04 12:51:00 PM PDT 24
Finished Jun 04 12:51:03 PM PDT 24
Peak memory 204700 kb
Host smart-551d58d6-794c-4fd8-9ab3-aa4adeb55a0b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626174430 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.3626174430
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.1312924221
Short name T357
Test name
Test status
Simulation time 7219838169 ps
CPU time 10.18 seconds
Started Jun 04 12:51:00 PM PDT 24
Finished Jun 04 12:51:12 PM PDT 24
Peak memory 204928 kb
Host smart-af90cd40-479a-4426-b360-ae74bbcfbfa7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312924221 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.1312924221
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2235507222
Short name T296
Test name
Test status
Simulation time 1531020419 ps
CPU time 4.91 seconds
Started Jun 04 12:50:51 PM PDT 24
Finished Jun 04 12:50:57 PM PDT 24
Peak memory 204588 kb
Host smart-c652a2da-c727-4fa6-ac0b-69ba55b33865
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235507222 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.2235507222
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1794014167
Short name T359
Test name
Test status
Simulation time 76776984 ps
CPU time 0.71 seconds
Started Jun 04 12:51:02 PM PDT 24
Finished Jun 04 12:51:04 PM PDT 24
Peak memory 204756 kb
Host smart-91ce4941-74fe-4c72-bdd8-59ebcb17d1df
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794014167 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.1794014167
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.2717987514
Short name T361
Test name
Test status
Simulation time 41028354 ps
CPU time 0.69 seconds
Started Jun 04 12:51:01 PM PDT 24
Finished Jun 04 12:51:02 PM PDT 24
Peak memory 204660 kb
Host smart-810faa40-c188-44dc-99e6-d83061681538
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717987514 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.2717987514
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.859135318
Short name T73
Test name
Test status
Simulation time 1291011888 ps
CPU time 7.37 seconds
Started Jun 04 12:51:01 PM PDT 24
Finished Jun 04 12:51:09 PM PDT 24
Peak memory 204960 kb
Host smart-ff63221e-1fb4-4ce3-b13b-548f981ce4ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859135318 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_c
sr_outstanding.859135318
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.3217277806
Short name T349
Test name
Test status
Simulation time 710310197 ps
CPU time 5.23 seconds
Started Jun 04 12:51:03 PM PDT 24
Finished Jun 04 12:51:11 PM PDT 24
Peak memory 213308 kb
Host smart-24038cd7-86c7-4d43-bbf3-c167da453d9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217277806 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.3217277806
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.2305734044
Short name T47
Test name
Test status
Simulation time 1138841486 ps
CPU time 11.47 seconds
Started Jun 04 12:51:03 PM PDT 24
Finished Jun 04 12:51:17 PM PDT 24
Peak memory 213272 kb
Host smart-c0698520-0b38-481a-91ca-fab0425ce1cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305734044 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.2305734044
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3440449091
Short name T409
Test name
Test status
Simulation time 2152730875 ps
CPU time 5.94 seconds
Started Jun 04 12:51:10 PM PDT 24
Finished Jun 04 12:51:17 PM PDT 24
Peak memory 221428 kb
Host smart-68e44774-1770-4538-86ac-6aa2f8dcba8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440449091 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.3440449091
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.3298858119
Short name T341
Test name
Test status
Simulation time 180482860 ps
CPU time 2.34 seconds
Started Jun 04 12:51:10 PM PDT 24
Finished Jun 04 12:51:14 PM PDT 24
Peak memory 213280 kb
Host smart-cba63207-44c6-4e5c-9441-2dbee8c25801
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298858119 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.3298858119
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.1968915388
Short name T280
Test name
Test status
Simulation time 5092897849 ps
CPU time 3.41 seconds
Started Jun 04 12:51:23 PM PDT 24
Finished Jun 04 12:51:27 PM PDT 24
Peak memory 205036 kb
Host smart-796e83d7-f520-4618-83ca-7e570c63952b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968915388 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.rv_dm_jtag_dmi_csr_bit_bash.1968915388
Directory /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3884149610
Short name T325
Test name
Test status
Simulation time 15134909994 ps
CPU time 32.73 seconds
Started Jun 04 12:51:15 PM PDT 24
Finished Jun 04 12:51:49 PM PDT 24
Peak memory 205064 kb
Host smart-6c44f5f3-56ce-4d95-9655-13a97acce6bb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884149610 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
3884149610
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.4101207022
Short name T329
Test name
Test status
Simulation time 137882213 ps
CPU time 0.83 seconds
Started Jun 04 12:51:08 PM PDT 24
Finished Jun 04 12:51:11 PM PDT 24
Peak memory 204616 kb
Host smart-1386d14f-3a8e-4372-bfc0-c477d7cc6a75
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101207022 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
4101207022
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3156089764
Short name T320
Test name
Test status
Simulation time 376356458 ps
CPU time 3.55 seconds
Started Jun 04 12:51:15 PM PDT 24
Finished Jun 04 12:51:20 PM PDT 24
Peak memory 205116 kb
Host smart-6fea2930-a5d4-4b7f-9095-bbe22faf4da9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156089764 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.3156089764
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3564884435
Short name T309
Test name
Test status
Simulation time 987654597 ps
CPU time 6.02 seconds
Started Jun 04 12:51:06 PM PDT 24
Finished Jun 04 12:51:14 PM PDT 24
Peak memory 213252 kb
Host smart-3b8b1d11-848d-421c-be1c-4f5e4418ff7e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564884435 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.3564884435
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.953092459
Short name T68
Test name
Test status
Simulation time 154820268 ps
CPU time 4.17 seconds
Started Jun 04 12:51:25 PM PDT 24
Finished Jun 04 12:51:30 PM PDT 24
Peak memory 221436 kb
Host smart-23be674f-2c1d-4532-81ae-9e870b1ad570
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953092459 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.953092459
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.4034575337
Short name T90
Test name
Test status
Simulation time 368480592 ps
CPU time 2.31 seconds
Started Jun 04 12:51:25 PM PDT 24
Finished Jun 04 12:51:28 PM PDT 24
Peak memory 213120 kb
Host smart-b6bf2664-9d1a-4512-983e-b8b7b1330d60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034575337 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.4034575337
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.59169217
Short name T414
Test name
Test status
Simulation time 6240591582 ps
CPU time 9.66 seconds
Started Jun 04 12:51:06 PM PDT 24
Finished Jun 04 12:51:18 PM PDT 24
Peak memory 204944 kb
Host smart-742374a2-7bd7-45e9-ba21-42345766b8cb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59169217 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.r
v_dm_jtag_dmi_csr_bit_bash.59169217
Directory /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.4212040673
Short name T266
Test name
Test status
Simulation time 3195030949 ps
CPU time 4.31 seconds
Started Jun 04 12:51:13 PM PDT 24
Finished Jun 04 12:51:19 PM PDT 24
Peak memory 204868 kb
Host smart-9edd02a1-0d71-45a9-8b46-7cc6939f9e63
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212040673 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
4212040673
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.1604958249
Short name T365
Test name
Test status
Simulation time 792691030 ps
CPU time 2.39 seconds
Started Jun 04 12:51:13 PM PDT 24
Finished Jun 04 12:51:16 PM PDT 24
Peak memory 204576 kb
Host smart-4c0119f9-8478-47af-8fce-5d5f874d705e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604958249 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.
1604958249
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.3751043483
Short name T326
Test name
Test status
Simulation time 277107772 ps
CPU time 4.24 seconds
Started Jun 04 12:51:24 PM PDT 24
Finished Jun 04 12:51:29 PM PDT 24
Peak memory 205004 kb
Host smart-de95a574-8568-40b1-b57a-2d101386d5a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751043483 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same
_csr_outstanding.3751043483
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.235053198
Short name T364
Test name
Test status
Simulation time 627028617 ps
CPU time 4.75 seconds
Started Jun 04 12:51:09 PM PDT 24
Finished Jun 04 12:51:15 PM PDT 24
Peak memory 213288 kb
Host smart-a39933d7-4bfd-40c8-9162-570c57a6453d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235053198 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.235053198
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.3668515101
Short name T369
Test name
Test status
Simulation time 971200825 ps
CPU time 3.99 seconds
Started Jun 04 12:51:22 PM PDT 24
Finished Jun 04 12:51:27 PM PDT 24
Peak memory 220436 kb
Host smart-c470178d-b74b-433b-9be8-9767aa7c3153
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668515101 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.3668515101
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.633055304
Short name T97
Test name
Test status
Simulation time 89601617 ps
CPU time 2.15 seconds
Started Jun 04 12:51:22 PM PDT 24
Finished Jun 04 12:51:26 PM PDT 24
Peak memory 213224 kb
Host smart-8bb1beb0-4fa4-4534-ba3c-bdb8a6900914
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633055304 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.633055304
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.3986666005
Short name T270
Test name
Test status
Simulation time 44473120130 ps
CPU time 38.41 seconds
Started Jun 04 12:51:29 PM PDT 24
Finished Jun 04 12:52:08 PM PDT 24
Peak memory 204960 kb
Host smart-a5a16674-41dd-4377-bd5c-27a3a9f42c4e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986666005 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.rv_dm_jtag_dmi_csr_bit_bash.3986666005
Directory /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.10825777
Short name T289
Test name
Test status
Simulation time 1280756480 ps
CPU time 1.29 seconds
Started Jun 04 12:51:20 PM PDT 24
Finished Jun 04 12:51:23 PM PDT 24
Peak memory 204892 kb
Host smart-77454afa-c461-4f0f-a01c-c2c66d6cbe31
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10825777 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.10825777
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.4261668200
Short name T317
Test name
Test status
Simulation time 750808236 ps
CPU time 1.67 seconds
Started Jun 04 12:51:21 PM PDT 24
Finished Jun 04 12:51:23 PM PDT 24
Peak memory 204720 kb
Host smart-c6d29614-e0a3-4e84-95fb-f94f46abf253
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261668200 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
4261668200
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.255406248
Short name T89
Test name
Test status
Simulation time 379225455 ps
CPU time 3.62 seconds
Started Jun 04 12:51:21 PM PDT 24
Finished Jun 04 12:51:26 PM PDT 24
Peak memory 205000 kb
Host smart-db44fa75-61c0-4139-832c-4ed6de4ad198
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255406248 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same_
csr_outstanding.255406248
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.2600953916
Short name T308
Test name
Test status
Simulation time 328959863 ps
CPU time 2.53 seconds
Started Jun 04 12:51:20 PM PDT 24
Finished Jun 04 12:51:24 PM PDT 24
Peak memory 213276 kb
Host smart-348b0fbc-0951-458e-9f10-1917df9776ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600953916 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.2600953916
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.4021240732
Short name T122
Test name
Test status
Simulation time 3054439999 ps
CPU time 11.27 seconds
Started Jun 04 12:51:19 PM PDT 24
Finished Jun 04 12:51:31 PM PDT 24
Peak memory 213292 kb
Host smart-866ca30f-1780-46d1-aaaf-ed51b2ae715e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021240732 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.4
021240732
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.4188471864
Short name T346
Test name
Test status
Simulation time 236211236 ps
CPU time 2.15 seconds
Started Jun 04 12:51:19 PM PDT 24
Finished Jun 04 12:51:23 PM PDT 24
Peak memory 221552 kb
Host smart-f18fe6bb-5f92-4a65-91bd-232c14533a57
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188471864 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.4188471864
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.2942393855
Short name T71
Test name
Test status
Simulation time 137690305 ps
CPU time 1.56 seconds
Started Jun 04 12:51:21 PM PDT 24
Finished Jun 04 12:51:23 PM PDT 24
Peak memory 213180 kb
Host smart-66a92cce-8998-42e3-8d7f-817a0a678460
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942393855 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.2942393855
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.2906322562
Short name T344
Test name
Test status
Simulation time 13103615139 ps
CPU time 10.02 seconds
Started Jun 04 12:51:22 PM PDT 24
Finished Jun 04 12:51:33 PM PDT 24
Peak memory 205004 kb
Host smart-c957e63f-2fc3-4550-a9fc-0e62c20c565b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906322562 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.rv_dm_jtag_dmi_csr_bit_bash.2906322562
Directory /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.106199788
Short name T271
Test name
Test status
Simulation time 6506575973 ps
CPU time 10.5 seconds
Started Jun 04 12:51:27 PM PDT 24
Finished Jun 04 12:51:38 PM PDT 24
Peak memory 205064 kb
Host smart-43ee0fc5-8f4a-486f-9243-6dd3496bd409
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106199788 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.106199788
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2407613743
Short name T368
Test name
Test status
Simulation time 205540890 ps
CPU time 0.81 seconds
Started Jun 04 12:51:24 PM PDT 24
Finished Jun 04 12:51:25 PM PDT 24
Peak memory 204712 kb
Host smart-f7268d2d-602e-450f-9fc8-f70384faf173
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407613743 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
2407613743
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.1766182082
Short name T327
Test name
Test status
Simulation time 551686568 ps
CPU time 6.18 seconds
Started Jun 04 12:51:28 PM PDT 24
Finished Jun 04 12:51:35 PM PDT 24
Peak memory 205144 kb
Host smart-546aab28-ec98-4d2c-96a0-b5e881ff0cce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766182082 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.1766182082
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2752171559
Short name T343
Test name
Test status
Simulation time 105501431 ps
CPU time 4.7 seconds
Started Jun 04 12:51:29 PM PDT 24
Finished Jun 04 12:51:34 PM PDT 24
Peak memory 213320 kb
Host smart-d5aefdb1-69c3-4ead-9946-1d6fd120a6d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752171559 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.2752171559
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1022408969
Short name T115
Test name
Test status
Simulation time 2021092122 ps
CPU time 19.69 seconds
Started Jun 04 12:51:20 PM PDT 24
Finished Jun 04 12:51:41 PM PDT 24
Peak memory 213292 kb
Host smart-45ec54ab-31f7-42fd-a05c-31b0cc1cc2f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022408969 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.1
022408969
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.4257405466
Short name T292
Test name
Test status
Simulation time 1287407520 ps
CPU time 4.16 seconds
Started Jun 04 12:51:21 PM PDT 24
Finished Jun 04 12:51:27 PM PDT 24
Peak memory 219768 kb
Host smart-17a6d718-070c-43d2-a83e-587becd33827
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257405466 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.4257405466
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.3334599963
Short name T274
Test name
Test status
Simulation time 221049837 ps
CPU time 1.78 seconds
Started Jun 04 12:51:21 PM PDT 24
Finished Jun 04 12:51:24 PM PDT 24
Peak memory 213200 kb
Host smart-9bc3c3af-5b2a-4e18-af9f-d8cba8cd26c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334599963 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.3334599963
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.3384190678
Short name T279
Test name
Test status
Simulation time 27663235986 ps
CPU time 43 seconds
Started Jun 04 12:51:27 PM PDT 24
Finished Jun 04 12:52:11 PM PDT 24
Peak memory 205032 kb
Host smart-d5b87896-baf7-4d0a-bab1-b51675eae52b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384190678 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.rv_dm_jtag_dmi_csr_bit_bash.3384190678
Directory /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2079742536
Short name T267
Test name
Test status
Simulation time 1410961476 ps
CPU time 2.72 seconds
Started Jun 04 12:51:20 PM PDT 24
Finished Jun 04 12:51:24 PM PDT 24
Peak memory 204892 kb
Host smart-8f1fbbe0-0cc0-41cf-b475-99924f554bd3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079742536 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
2079742536
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.4121647328
Short name T387
Test name
Test status
Simulation time 164193230 ps
CPU time 0.75 seconds
Started Jun 04 12:51:21 PM PDT 24
Finished Jun 04 12:51:23 PM PDT 24
Peak memory 204700 kb
Host smart-69740e6f-3c7d-4874-bd0e-6d1d98a2e9e9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121647328 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
4121647328
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1489691939
Short name T411
Test name
Test status
Simulation time 375126669 ps
CPU time 4.69 seconds
Started Jun 04 12:51:30 PM PDT 24
Finished Jun 04 12:51:36 PM PDT 24
Peak memory 205128 kb
Host smart-5ca3f01a-7eeb-4539-b775-0be6a95c62d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489691939 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.1489691939
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1859560645
Short name T371
Test name
Test status
Simulation time 2237114994 ps
CPU time 2.83 seconds
Started Jun 04 12:51:21 PM PDT 24
Finished Jun 04 12:51:25 PM PDT 24
Peak memory 217504 kb
Host smart-29fc12cb-e941-44cf-85ee-fdb416303df5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859560645 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.1859560645
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.1673664741
Short name T330
Test name
Test status
Simulation time 640433334 ps
CPU time 2.4 seconds
Started Jun 04 12:51:17 PM PDT 24
Finished Jun 04 12:51:20 PM PDT 24
Peak memory 213092 kb
Host smart-86105a54-c916-4f20-92e9-dbe50c33813b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673664741 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.1673664741
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.2038961564
Short name T307
Test name
Test status
Simulation time 8584281903 ps
CPU time 15.19 seconds
Started Jun 04 12:51:17 PM PDT 24
Finished Jun 04 12:51:33 PM PDT 24
Peak memory 205052 kb
Host smart-69ff6078-d84d-471f-960b-bfeeb041a4bc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038961564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.rv_dm_jtag_dmi_csr_bit_bash.2038961564
Directory /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1854226610
Short name T304
Test name
Test status
Simulation time 4509330548 ps
CPU time 4.41 seconds
Started Jun 04 12:51:23 PM PDT 24
Finished Jun 04 12:51:28 PM PDT 24
Peak memory 205044 kb
Host smart-37a09848-09ad-4b3b-bc79-e68cfa71fdb8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854226610 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
1854226610
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.791338682
Short name T272
Test name
Test status
Simulation time 217745822 ps
CPU time 1.23 seconds
Started Jun 04 12:51:24 PM PDT 24
Finished Jun 04 12:51:26 PM PDT 24
Peak memory 204712 kb
Host smart-fec15bbe-5884-4d3e-a14a-80da052c1266
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791338682 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.791338682
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.3150172555
Short name T105
Test name
Test status
Simulation time 1758774203 ps
CPU time 7.43 seconds
Started Jun 04 12:51:23 PM PDT 24
Finished Jun 04 12:51:32 PM PDT 24
Peak memory 205080 kb
Host smart-1655dafb-c6f7-4094-943b-d0fe99477671
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150172555 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.3150172555
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.1872301702
Short name T363
Test name
Test status
Simulation time 557761398 ps
CPU time 5 seconds
Started Jun 04 12:51:20 PM PDT 24
Finished Jun 04 12:51:27 PM PDT 24
Peak memory 213348 kb
Host smart-1f12cfb9-4503-486e-8a38-bada79586488
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872301702 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.1872301702
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.287687465
Short name T121
Test name
Test status
Simulation time 7368926950 ps
CPU time 20.72 seconds
Started Jun 04 12:51:31 PM PDT 24
Finished Jun 04 12:51:53 PM PDT 24
Peak memory 213380 kb
Host smart-67e416bb-8727-4752-90ba-17d3aab0bf0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287687465 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.287687465
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.935714777
Short name T111
Test name
Test status
Simulation time 3073585010 ps
CPU time 4.16 seconds
Started Jun 04 12:51:27 PM PDT 24
Finished Jun 04 12:51:32 PM PDT 24
Peak memory 218680 kb
Host smart-5996cfb6-82f7-44cd-b482-0f0904a43c8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935714777 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.935714777
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.888968051
Short name T98
Test name
Test status
Simulation time 63981058 ps
CPU time 2.18 seconds
Started Jun 04 12:51:21 PM PDT 24
Finished Jun 04 12:51:24 PM PDT 24
Peak memory 213104 kb
Host smart-ec22871a-beb6-4cd4-9ae7-d5a8adcd4981
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888968051 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.888968051
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.2454424793
Short name T300
Test name
Test status
Simulation time 8416895022 ps
CPU time 23.86 seconds
Started Jun 04 12:51:23 PM PDT 24
Finished Jun 04 12:51:48 PM PDT 24
Peak memory 204956 kb
Host smart-c18a160d-8dc0-4d1e-899d-e7da18f055c5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454424793 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.rv_dm_jtag_dmi_csr_bit_bash.2454424793
Directory /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2653871094
Short name T265
Test name
Test status
Simulation time 2463977867 ps
CPU time 4.81 seconds
Started Jun 04 12:51:20 PM PDT 24
Finished Jun 04 12:51:27 PM PDT 24
Peak memory 204976 kb
Host smart-12404a00-2478-4ea5-971a-cfe0840b53cb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653871094 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
2653871094
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.4268884803
Short name T322
Test name
Test status
Simulation time 310644115 ps
CPU time 0.88 seconds
Started Jun 04 12:51:20 PM PDT 24
Finished Jun 04 12:51:22 PM PDT 24
Peak memory 204612 kb
Host smart-af93b1f0-a1b4-4964-83df-66d9904cbf63
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268884803 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
4268884803
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.2674725408
Short name T76
Test name
Test status
Simulation time 180257162 ps
CPU time 6.59 seconds
Started Jun 04 12:51:21 PM PDT 24
Finished Jun 04 12:51:29 PM PDT 24
Peak memory 204992 kb
Host smart-461f42a7-0f11-403b-ae42-f40507f3499d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674725408 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.2674725408
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.475232451
Short name T353
Test name
Test status
Simulation time 256571632 ps
CPU time 4.96 seconds
Started Jun 04 12:51:18 PM PDT 24
Finished Jun 04 12:51:24 PM PDT 24
Peak memory 213376 kb
Host smart-377133ca-3f6a-441b-a86d-8ab6da9692d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475232451 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.475232451
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.4156232367
Short name T375
Test name
Test status
Simulation time 3481844172 ps
CPU time 4.54 seconds
Started Jun 04 12:51:29 PM PDT 24
Finished Jun 04 12:51:35 PM PDT 24
Peak memory 218484 kb
Host smart-ad543a6d-15c7-400b-8c95-71d2342e4bc5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156232367 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.4156232367
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.1826859866
Short name T360
Test name
Test status
Simulation time 208157731 ps
CPU time 1.61 seconds
Started Jun 04 12:51:31 PM PDT 24
Finished Jun 04 12:51:34 PM PDT 24
Peak memory 213088 kb
Host smart-6a4abeeb-5f24-436e-a7fa-fb6900c02883
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826859866 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.1826859866
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.2955182391
Short name T268
Test name
Test status
Simulation time 4283271678 ps
CPU time 4.44 seconds
Started Jun 04 12:51:30 PM PDT 24
Finished Jun 04 12:51:35 PM PDT 24
Peak memory 204912 kb
Host smart-84ed6622-5a24-4d8e-aae5-df82eb482373
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955182391 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.rv_dm_jtag_dmi_csr_bit_bash.2955182391
Directory /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2444998191
Short name T305
Test name
Test status
Simulation time 5115946676 ps
CPU time 14.66 seconds
Started Jun 04 12:51:33 PM PDT 24
Finished Jun 04 12:51:50 PM PDT 24
Peak memory 205044 kb
Host smart-a7c300c2-15fa-40d3-a36a-a5e1a05d004a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444998191 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
2444998191
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.3260566223
Short name T293
Test name
Test status
Simulation time 601841762 ps
CPU time 1.72 seconds
Started Jun 04 12:51:36 PM PDT 24
Finished Jun 04 12:51:40 PM PDT 24
Peak memory 204644 kb
Host smart-6bc9f571-6415-4c77-a1a3-f5570181dcde
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260566223 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
3260566223
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3788676327
Short name T366
Test name
Test status
Simulation time 1079561136 ps
CPU time 4.19 seconds
Started Jun 04 12:51:31 PM PDT 24
Finished Jun 04 12:51:36 PM PDT 24
Peak memory 205104 kb
Host smart-87e1170a-1d49-4c3d-a5bc-f266980e491e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788676327 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.3788676327
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2598105516
Short name T60
Test name
Test status
Simulation time 542454855 ps
CPU time 4.26 seconds
Started Jun 04 12:51:34 PM PDT 24
Finished Jun 04 12:51:40 PM PDT 24
Peak memory 213396 kb
Host smart-86492145-37a9-4cdf-8fa4-d22f89e876e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598105516 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.2598105516
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2948962318
Short name T118
Test name
Test status
Simulation time 2530320953 ps
CPU time 10.46 seconds
Started Jun 04 12:51:33 PM PDT 24
Finished Jun 04 12:51:45 PM PDT 24
Peak memory 213380 kb
Host smart-9bdc9372-fb32-4745-bc9e-f085cf7a9503
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948962318 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.2
948962318
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.190171825
Short name T390
Test name
Test status
Simulation time 937280271 ps
CPU time 2.66 seconds
Started Jun 04 12:51:39 PM PDT 24
Finished Jun 04 12:51:43 PM PDT 24
Peak memory 214680 kb
Host smart-c25f93ca-e002-4211-82bc-4bf99d6d7b16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190171825 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.190171825
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.3696498995
Short name T416
Test name
Test status
Simulation time 292641409 ps
CPU time 1.42 seconds
Started Jun 04 12:51:32 PM PDT 24
Finished Jun 04 12:51:35 PM PDT 24
Peak memory 213172 kb
Host smart-1968e436-ddaf-43d7-a436-05abcaba5a2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696498995 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.3696498995
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.355675529
Short name T311
Test name
Test status
Simulation time 23908990533 ps
CPU time 26.3 seconds
Started Jun 04 12:51:29 PM PDT 24
Finished Jun 04 12:51:56 PM PDT 24
Peak memory 205056 kb
Host smart-2738ddfc-6d6c-4259-9cbf-b83a840d35f5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355675529 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
rv_dm_jtag_dmi_csr_bit_bash.355675529
Directory /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.575748459
Short name T376
Test name
Test status
Simulation time 1495918691 ps
CPU time 4.67 seconds
Started Jun 04 12:51:32 PM PDT 24
Finished Jun 04 12:51:38 PM PDT 24
Peak memory 204916 kb
Host smart-8d817ef8-2c1f-4bc9-88d5-80162f3d1907
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575748459 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.575748459
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.1465337472
Short name T282
Test name
Test status
Simulation time 343181977 ps
CPU time 1.57 seconds
Started Jun 04 12:51:30 PM PDT 24
Finished Jun 04 12:51:32 PM PDT 24
Peak memory 204720 kb
Host smart-5631d01e-9e03-4147-ba7d-3429f49e6a8c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465337472 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
1465337472
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1937424569
Short name T323
Test name
Test status
Simulation time 276045397 ps
CPU time 3.84 seconds
Started Jun 04 12:51:40 PM PDT 24
Finished Jun 04 12:51:45 PM PDT 24
Peak memory 205004 kb
Host smart-14505423-efd5-41a0-9f89-fcfe3ab7b9e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937424569 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.1937424569
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.4068415160
Short name T113
Test name
Test status
Simulation time 277942948 ps
CPU time 4.12 seconds
Started Jun 04 12:51:32 PM PDT 24
Finished Jun 04 12:51:38 PM PDT 24
Peak memory 213324 kb
Host smart-13a4235b-ad2f-4b62-bdb1-94184bcdaccc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068415160 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.4068415160
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.483203775
Short name T316
Test name
Test status
Simulation time 2903874378 ps
CPU time 24.11 seconds
Started Jun 04 12:51:30 PM PDT 24
Finished Jun 04 12:51:56 PM PDT 24
Peak memory 213300 kb
Host smart-4b11ea3f-321f-4720-8802-487650ab8d78
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483203775 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.483203775
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1516200681
Short name T333
Test name
Test status
Simulation time 4364204007 ps
CPU time 7.09 seconds
Started Jun 04 12:51:37 PM PDT 24
Finished Jun 04 12:51:46 PM PDT 24
Peak memory 213468 kb
Host smart-c4a5c278-63e8-40a8-814d-5725928d3462
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516200681 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.1516200681
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.1515621146
Short name T348
Test name
Test status
Simulation time 279727047 ps
CPU time 2.57 seconds
Started Jun 04 12:51:32 PM PDT 24
Finished Jun 04 12:51:37 PM PDT 24
Peak memory 213184 kb
Host smart-423f8620-c45f-4cbd-b40b-a1167931c3e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515621146 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.1515621146
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.787466367
Short name T388
Test name
Test status
Simulation time 55245278945 ps
CPU time 149.8 seconds
Started Jun 04 12:51:35 PM PDT 24
Finished Jun 04 12:54:07 PM PDT 24
Peak memory 204976 kb
Host smart-b25bd7d6-24cb-4fbd-b2d3-2b9e097cca81
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787466367 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
rv_dm_jtag_dmi_csr_bit_bash.787466367
Directory /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2659600738
Short name T340
Test name
Test status
Simulation time 16379268028 ps
CPU time 16.31 seconds
Started Jun 04 12:51:33 PM PDT 24
Finished Jun 04 12:51:52 PM PDT 24
Peak memory 205036 kb
Host smart-f6e1945e-0596-4363-b916-bbf83101f722
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659600738 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
2659600738
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.1833673887
Short name T352
Test name
Test status
Simulation time 145103400 ps
CPU time 1.07 seconds
Started Jun 04 12:51:31 PM PDT 24
Finished Jun 04 12:51:34 PM PDT 24
Peak memory 204684 kb
Host smart-88fbae67-5414-4f5e-80c3-bace2039340e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833673887 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
1833673887
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.2933304695
Short name T104
Test name
Test status
Simulation time 587523471 ps
CPU time 4.29 seconds
Started Jun 04 12:51:31 PM PDT 24
Finished Jun 04 12:51:37 PM PDT 24
Peak memory 204980 kb
Host smart-ae8853b1-8b3d-416c-a52f-13a696a2facf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933304695 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.2933304695
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3358449759
Short name T335
Test name
Test status
Simulation time 451323770 ps
CPU time 3.63 seconds
Started Jun 04 12:51:30 PM PDT 24
Finished Jun 04 12:51:34 PM PDT 24
Peak memory 213268 kb
Host smart-0b63b4e8-478b-4897-8a6a-6a9c29453676
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358449759 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.3358449759
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.1386369891
Short name T116
Test name
Test status
Simulation time 3266814092 ps
CPU time 17.74 seconds
Started Jun 04 12:51:30 PM PDT 24
Finished Jun 04 12:51:50 PM PDT 24
Peak memory 213264 kb
Host smart-e83f2f92-da0f-4674-9124-c218c9a80102
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386369891 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.1
386369891
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.3334088858
Short name T358
Test name
Test status
Simulation time 1759420636 ps
CPU time 31.8 seconds
Started Jun 04 12:51:03 PM PDT 24
Finished Jun 04 12:51:37 PM PDT 24
Peak memory 213120 kb
Host smart-8a1791d9-d07e-46d6-b20f-b0a997f87e3b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334088858 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.3334088858
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.3086563156
Short name T100
Test name
Test status
Simulation time 1437725331 ps
CPU time 53.53 seconds
Started Jun 04 12:51:01 PM PDT 24
Finished Jun 04 12:51:56 PM PDT 24
Peak memory 204928 kb
Host smart-f33da224-d43d-4a48-bfd4-a9fed3879d7c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086563156 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.3086563156
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.227137553
Short name T406
Test name
Test status
Simulation time 756536288 ps
CPU time 2.9 seconds
Started Jun 04 12:51:04 PM PDT 24
Finished Jun 04 12:51:09 PM PDT 24
Peak memory 213160 kb
Host smart-ce14ea77-a35a-4c6a-9316-52e59f8b248c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227137553 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.227137553
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3885977920
Short name T410
Test name
Test status
Simulation time 303869649 ps
CPU time 3.05 seconds
Started Jun 04 12:51:04 PM PDT 24
Finished Jun 04 12:51:09 PM PDT 24
Peak memory 218448 kb
Host smart-1cb2fffe-e90e-4ae8-b23e-e2da48fb0025
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885977920 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.3885977920
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.2349840357
Short name T399
Test name
Test status
Simulation time 227094290 ps
CPU time 1.57 seconds
Started Jun 04 12:51:02 PM PDT 24
Finished Jun 04 12:51:06 PM PDT 24
Peak memory 213248 kb
Host smart-c60cb4e0-4d7d-4ca2-a3c8-908e2e3f6e7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349840357 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.2349840357
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.3714169268
Short name T302
Test name
Test status
Simulation time 144103128727 ps
CPU time 363.58 seconds
Started Jun 04 12:51:00 PM PDT 24
Finished Jun 04 12:57:05 PM PDT 24
Peak memory 205244 kb
Host smart-4358124a-4dd7-4e8e-a7c7-a7845669afca
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714169268 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.3714169268
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.2301128157
Short name T310
Test name
Test status
Simulation time 8970393019 ps
CPU time 9.64 seconds
Started Jun 04 12:51:01 PM PDT 24
Finished Jun 04 12:51:12 PM PDT 24
Peak memory 204880 kb
Host smart-d56b6fb1-620a-4c89-8d39-3cded80479fd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301128157 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
rv_dm_jtag_dmi_csr_bit_bash.2301128157
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.4136865004
Short name T85
Test name
Test status
Simulation time 9271332971 ps
CPU time 7.54 seconds
Started Jun 04 12:50:59 PM PDT 24
Finished Jun 04 12:51:07 PM PDT 24
Peak memory 205156 kb
Host smart-6a574f2b-93eb-4daa-8dfb-801a52106955
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136865004 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.4136865004
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.3726717627
Short name T294
Test name
Test status
Simulation time 1214397265 ps
CPU time 2.08 seconds
Started Jun 04 12:51:00 PM PDT 24
Finished Jun 04 12:51:02 PM PDT 24
Peak memory 204912 kb
Host smart-25dd58b2-ce66-4bcd-899f-0114020d59f8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726717627 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.3
726717627
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.182894295
Short name T391
Test name
Test status
Simulation time 3110825425 ps
CPU time 5.9 seconds
Started Jun 04 12:51:00 PM PDT 24
Finished Jun 04 12:51:07 PM PDT 24
Peak memory 204776 kb
Host smart-70aa64ec-3119-488f-9890-073905817699
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182894295 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_aliasing.182894295
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.3286157846
Short name T301
Test name
Test status
Simulation time 17148957303 ps
CPU time 13.55 seconds
Started Jun 04 12:51:03 PM PDT 24
Finished Jun 04 12:51:19 PM PDT 24
Peak memory 205020 kb
Host smart-decd6b65-f244-4202-a39a-c3abb5edb631
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286157846 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.3286157846
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2294013292
Short name T412
Test name
Test status
Simulation time 118471161 ps
CPU time 1.02 seconds
Started Jun 04 12:51:03 PM PDT 24
Finished Jun 04 12:51:07 PM PDT 24
Peak memory 204676 kb
Host smart-013e00eb-8958-4fa6-ab96-5631dad6d0e4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294013292 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.2294013292
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2538100199
Short name T331
Test name
Test status
Simulation time 278824133 ps
CPU time 1.08 seconds
Started Jun 04 12:51:04 PM PDT 24
Finished Jun 04 12:51:07 PM PDT 24
Peak memory 204604 kb
Host smart-26e611aa-9f21-4a6f-bcac-23ab786c8203
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538100199 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.2
538100199
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2219523066
Short name T398
Test name
Test status
Simulation time 62370091 ps
CPU time 0.82 seconds
Started Jun 04 12:51:03 PM PDT 24
Finished Jun 04 12:51:06 PM PDT 24
Peak memory 204764 kb
Host smart-ccad5750-9bd7-4f69-b13b-55717eeede16
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219523066 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.2219523066
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.1420692899
Short name T400
Test name
Test status
Simulation time 108530189 ps
CPU time 0.68 seconds
Started Jun 04 12:51:01 PM PDT 24
Finished Jun 04 12:51:03 PM PDT 24
Peak memory 204648 kb
Host smart-aadea969-d1bc-4f97-b11d-981d9905ee38
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420692899 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.1420692899
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.1889109615
Short name T94
Test name
Test status
Simulation time 157149359 ps
CPU time 6.31 seconds
Started Jun 04 12:50:59 PM PDT 24
Finished Jun 04 12:51:06 PM PDT 24
Peak memory 205048 kb
Host smart-fe8ea166-e887-444a-9976-8cd17e8dff6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889109615 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.1889109615
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.3664642752
Short name T373
Test name
Test status
Simulation time 36202822563 ps
CPU time 111.9 seconds
Started Jun 04 12:51:01 PM PDT 24
Finished Jun 04 12:52:54 PM PDT 24
Peak memory 221640 kb
Host smart-12d2a706-1898-4c80-b148-44315849da6d
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664642752 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.3664642752
Directory /workspace/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.3777502779
Short name T56
Test name
Test status
Simulation time 301790673 ps
CPU time 5.13 seconds
Started Jun 04 12:51:04 PM PDT 24
Finished Jun 04 12:51:11 PM PDT 24
Peak memory 213368 kb
Host smart-d9c47ac2-f5a5-456b-91ae-a6b3f8e39379
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777502779 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.3777502779
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2273221976
Short name T114
Test name
Test status
Simulation time 6891176694 ps
CPU time 21.31 seconds
Started Jun 04 12:51:00 PM PDT 24
Finished Jun 04 12:51:23 PM PDT 24
Peak memory 213368 kb
Host smart-193c236b-8721-4b88-9145-f667329c9a4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273221976 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.2273221976
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.3975896847
Short name T75
Test name
Test status
Simulation time 4252436814 ps
CPU time 74.38 seconds
Started Jun 04 12:51:01 PM PDT 24
Finished Jun 04 12:52:17 PM PDT 24
Peak memory 213216 kb
Host smart-ec7430e4-207a-4a00-8f66-957d08b751c1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975896847 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.3975896847
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.208195904
Short name T101
Test name
Test status
Simulation time 52180128830 ps
CPU time 92.46 seconds
Started Jun 04 12:50:58 PM PDT 24
Finished Jun 04 12:52:31 PM PDT 24
Peak memory 214520 kb
Host smart-c3254cb9-5e73-4135-8914-125ae8bbf9dd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208195904 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.208195904
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.2426191741
Short name T342
Test name
Test status
Simulation time 829067452 ps
CPU time 2.26 seconds
Started Jun 04 12:51:03 PM PDT 24
Finished Jun 04 12:51:08 PM PDT 24
Peak memory 213144 kb
Host smart-16a18518-3f43-420f-b209-c01a1d9bcc8a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426191741 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.2426191741
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.865891357
Short name T58
Test name
Test status
Simulation time 219435780 ps
CPU time 2.45 seconds
Started Jun 04 12:51:00 PM PDT 24
Finished Jun 04 12:51:03 PM PDT 24
Peak memory 218352 kb
Host smart-3d3b73dc-d13c-4e39-b870-347a695fd219
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865891357 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.865891357
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.147680527
Short name T379
Test name
Test status
Simulation time 202586226 ps
CPU time 2.73 seconds
Started Jun 04 12:51:02 PM PDT 24
Finished Jun 04 12:51:07 PM PDT 24
Peak memory 213124 kb
Host smart-645d403b-ec58-4c5e-88b4-38b0d9626fa7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147680527 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.147680527
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.4275281593
Short name T382
Test name
Test status
Simulation time 90869899619 ps
CPU time 136.12 seconds
Started Jun 04 12:51:00 PM PDT 24
Finished Jun 04 12:53:18 PM PDT 24
Peak memory 204864 kb
Host smart-1c9153a8-bf59-4b87-b693-efcf7f75fae5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275281593 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.4275281593
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.2288125104
Short name T378
Test name
Test status
Simulation time 13345025195 ps
CPU time 23.05 seconds
Started Jun 04 12:51:00 PM PDT 24
Finished Jun 04 12:51:24 PM PDT 24
Peak memory 204936 kb
Host smart-61f35780-2064-4a29-9d8a-f92f812f3553
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288125104 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
rv_dm_jtag_dmi_csr_bit_bash.2288125104
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2780271455
Short name T87
Test name
Test status
Simulation time 1966758084 ps
CPU time 2.54 seconds
Started Jun 04 12:51:02 PM PDT 24
Finished Jun 04 12:51:06 PM PDT 24
Peak memory 204896 kb
Host smart-25fa74ff-a771-421a-ae3b-4c53dc9c4b49
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780271455 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.2780271455
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1994639420
Short name T347
Test name
Test status
Simulation time 8099890632 ps
CPU time 22.85 seconds
Started Jun 04 12:51:01 PM PDT 24
Finished Jun 04 12:51:25 PM PDT 24
Peak memory 205044 kb
Host smart-f04e384b-114b-4fed-811c-6c30796d735f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994639420 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.1
994639420
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1768212035
Short name T315
Test name
Test status
Simulation time 449988492 ps
CPU time 0.86 seconds
Started Jun 04 12:51:01 PM PDT 24
Finished Jun 04 12:51:03 PM PDT 24
Peak memory 204604 kb
Host smart-05c9cfe5-8657-4def-8e02-c4f7788cfe33
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768212035 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.1768212035
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2547651359
Short name T401
Test name
Test status
Simulation time 7694985129 ps
CPU time 11.34 seconds
Started Jun 04 12:51:00 PM PDT 24
Finished Jun 04 12:51:12 PM PDT 24
Peak memory 204860 kb
Host smart-b34e7125-57c0-49a4-9338-ef2224621512
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547651359 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.2547651359
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.4147048056
Short name T285
Test name
Test status
Simulation time 440097377 ps
CPU time 1.8 seconds
Started Jun 04 12:51:01 PM PDT 24
Finished Jun 04 12:51:04 PM PDT 24
Peak memory 204728 kb
Host smart-df8d222f-a9b9-423b-b552-d507d5a3ebb7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147048056 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.4147048056
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1948106953
Short name T288
Test name
Test status
Simulation time 1457117825 ps
CPU time 1.87 seconds
Started Jun 04 12:51:04 PM PDT 24
Finished Jun 04 12:51:08 PM PDT 24
Peak memory 204640 kb
Host smart-b057129a-ff0d-49f1-abba-ee0e9506f8a3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948106953 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.1
948106953
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.3341381794
Short name T275
Test name
Test status
Simulation time 59597595 ps
CPU time 0.72 seconds
Started Jun 04 12:51:01 PM PDT 24
Finished Jun 04 12:51:03 PM PDT 24
Peak memory 204728 kb
Host smart-13f0fbcd-19b5-4b7d-972d-2c8fd928ab9f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341381794 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.3341381794
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.4030718910
Short name T297
Test name
Test status
Simulation time 34997188 ps
CPU time 0.73 seconds
Started Jun 04 12:51:01 PM PDT 24
Finished Jun 04 12:51:03 PM PDT 24
Peak memory 204584 kb
Host smart-75e10519-603f-46c3-82ed-efced0a6aaea
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030718910 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.4030718910
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2922491402
Short name T95
Test name
Test status
Simulation time 395059050 ps
CPU time 4.1 seconds
Started Jun 04 12:51:03 PM PDT 24
Finished Jun 04 12:51:09 PM PDT 24
Peak memory 205008 kb
Host smart-5df23998-ea70-4492-9ea3-d331992d3a8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922491402 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.2922491402
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.320310167
Short name T123
Test name
Test status
Simulation time 22391228918 ps
CPU time 16.76 seconds
Started Jun 04 12:51:03 PM PDT 24
Finished Jun 04 12:51:22 PM PDT 24
Peak memory 221504 kb
Host smart-29360387-038e-4cab-9889-5c8cd2461c00
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320310167 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.320310167
Directory /workspace/3.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2897562870
Short name T78
Test name
Test status
Simulation time 142726340 ps
CPU time 4.13 seconds
Started Jun 04 12:51:03 PM PDT 24
Finished Jun 04 12:51:10 PM PDT 24
Peak memory 213372 kb
Host smart-189261c5-fbc0-4b43-9f42-e81f5546881a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897562870 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.2897562870
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2325497483
Short name T67
Test name
Test status
Simulation time 1264731702 ps
CPU time 15.35 seconds
Started Jun 04 12:51:03 PM PDT 24
Finished Jun 04 12:51:21 PM PDT 24
Peak memory 213288 kb
Host smart-b29b2bac-d50c-4768-90e7-3397215c85ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325497483 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.2325497483
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2147455176
Short name T319
Test name
Test status
Simulation time 6966869985 ps
CPU time 32.63 seconds
Started Jun 04 12:50:58 PM PDT 24
Finished Jun 04 12:51:31 PM PDT 24
Peak memory 213344 kb
Host smart-d684fa24-ae10-46ae-bba7-2d245dc9e49d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147455176 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.2147455176
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.1248323897
Short name T380
Test name
Test status
Simulation time 5135330977 ps
CPU time 70.63 seconds
Started Jun 04 12:51:04 PM PDT 24
Finished Jun 04 12:52:17 PM PDT 24
Peak memory 213284 kb
Host smart-8215e0c8-d333-40a0-aa87-f1c72b01329e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248323897 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.1248323897
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2189265230
Short name T356
Test name
Test status
Simulation time 2864189212 ps
CPU time 3.44 seconds
Started Jun 04 12:51:05 PM PDT 24
Finished Jun 04 12:51:10 PM PDT 24
Peak memory 215748 kb
Host smart-cb69c17f-268d-4077-a4f9-02777edb3265
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189265230 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.2189265230
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.1064701471
Short name T303
Test name
Test status
Simulation time 283719988 ps
CPU time 1.59 seconds
Started Jun 04 12:51:03 PM PDT 24
Finished Jun 04 12:51:07 PM PDT 24
Peak memory 213212 kb
Host smart-eb322c28-2cb4-44e1-9823-d431f804c245
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064701471 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.1064701471
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.634927122
Short name T402
Test name
Test status
Simulation time 98496614296 ps
CPU time 144.6 seconds
Started Jun 04 12:51:04 PM PDT 24
Finished Jun 04 12:53:31 PM PDT 24
Peak memory 204996 kb
Host smart-91a7776d-2921-441e-a29a-8e4cccaf4fa9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634927122 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr
_aliasing.634927122
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.2482048735
Short name T403
Test name
Test status
Simulation time 3813013511 ps
CPU time 11.74 seconds
Started Jun 04 12:51:02 PM PDT 24
Finished Jun 04 12:51:15 PM PDT 24
Peak memory 204896 kb
Host smart-01f443d4-bde4-4215-995b-440e220b6404
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482048735 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
rv_dm_jtag_dmi_csr_bit_bash.2482048735
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.3043972092
Short name T88
Test name
Test status
Simulation time 10902761978 ps
CPU time 8.14 seconds
Started Jun 04 12:51:00 PM PDT 24
Finished Jun 04 12:51:09 PM PDT 24
Peak memory 205044 kb
Host smart-512ae645-c081-4339-b04c-32fc6f31dd1d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043972092 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.3043972092
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.2458209002
Short name T306
Test name
Test status
Simulation time 7349968776 ps
CPU time 20.56 seconds
Started Jun 04 12:51:00 PM PDT 24
Finished Jun 04 12:51:21 PM PDT 24
Peak memory 205012 kb
Host smart-749308ab-6821-4a44-b6f8-47c36560237e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458209002 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.2
458209002
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.2027212054
Short name T286
Test name
Test status
Simulation time 397586545 ps
CPU time 0.84 seconds
Started Jun 04 12:51:01 PM PDT 24
Finished Jun 04 12:51:03 PM PDT 24
Peak memory 204668 kb
Host smart-8222a692-3bd1-4882-8747-a5aab6141975
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027212054 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.2027212054
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.3017307570
Short name T377
Test name
Test status
Simulation time 10931117914 ps
CPU time 10.54 seconds
Started Jun 04 12:51:04 PM PDT 24
Finished Jun 04 12:51:17 PM PDT 24
Peak memory 205000 kb
Host smart-d8fcbe74-bd2b-4c91-9e3a-793850dc364c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017307570 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.3017307570
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.1814284746
Short name T404
Test name
Test status
Simulation time 1135422720 ps
CPU time 3.69 seconds
Started Jun 04 12:51:02 PM PDT 24
Finished Jun 04 12:51:08 PM PDT 24
Peak memory 204664 kb
Host smart-fbf8db3f-3aef-4196-8a35-4da4154b712a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814284746 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.1814284746
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.1688939571
Short name T278
Test name
Test status
Simulation time 256181779 ps
CPU time 1.43 seconds
Started Jun 04 12:51:03 PM PDT 24
Finished Jun 04 12:51:08 PM PDT 24
Peak memory 204724 kb
Host smart-06bf13d2-d533-4557-b797-6491a8d2a538
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688939571 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.1
688939571
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1443139710
Short name T408
Test name
Test status
Simulation time 31807286 ps
CPU time 0.78 seconds
Started Jun 04 12:51:03 PM PDT 24
Finished Jun 04 12:51:06 PM PDT 24
Peak memory 204916 kb
Host smart-b6953ee8-4f20-4199-bda6-20fa2878fb8b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443139710 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.1443139710
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.2511530793
Short name T407
Test name
Test status
Simulation time 61187429 ps
CPU time 0.76 seconds
Started Jun 04 12:50:58 PM PDT 24
Finished Jun 04 12:51:00 PM PDT 24
Peak memory 204696 kb
Host smart-423445f1-6df6-4ef0-a01b-650faa0ada30
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511530793 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.2511530793
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.579797988
Short name T106
Test name
Test status
Simulation time 522390723 ps
CPU time 6.81 seconds
Started Jun 04 12:51:04 PM PDT 24
Finished Jun 04 12:51:13 PM PDT 24
Peak memory 205260 kb
Host smart-400e20b0-044e-48d2-a8d9-0f8685280eff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579797988 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_c
sr_outstanding.579797988
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.1152996181
Short name T415
Test name
Test status
Simulation time 17323464704 ps
CPU time 17.91 seconds
Started Jun 04 12:51:02 PM PDT 24
Finished Jun 04 12:51:22 PM PDT 24
Peak memory 219616 kb
Host smart-3d5bc477-b5a3-4065-8d55-681bb55b22c8
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152996181 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.1152996181
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2380178529
Short name T295
Test name
Test status
Simulation time 389468000 ps
CPU time 4.42 seconds
Started Jun 04 12:51:01 PM PDT 24
Finished Jun 04 12:51:06 PM PDT 24
Peak memory 221468 kb
Host smart-e66e3c63-cbd2-4821-ae57-4c3289868354
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380178529 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.2380178529
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.3846656381
Short name T117
Test name
Test status
Simulation time 6215953974 ps
CPU time 21.81 seconds
Started Jun 04 12:51:02 PM PDT 24
Finished Jun 04 12:51:25 PM PDT 24
Peak memory 213308 kb
Host smart-ad521762-bd05-4623-873b-7451c1260879
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846656381 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.3846656381
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.355269972
Short name T324
Test name
Test status
Simulation time 3816451046 ps
CPU time 6.95 seconds
Started Jun 04 12:51:04 PM PDT 24
Finished Jun 04 12:51:14 PM PDT 24
Peak memory 221432 kb
Host smart-1aa0a1e5-c04b-4e37-9c90-2513121be71a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355269972 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.355269972
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.247339723
Short name T72
Test name
Test status
Simulation time 196563956 ps
CPU time 2.54 seconds
Started Jun 04 12:51:02 PM PDT 24
Finished Jun 04 12:51:07 PM PDT 24
Peak memory 213224 kb
Host smart-8525dae1-b164-48f1-a6bd-68b36ba39a9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247339723 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.247339723
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.3818393634
Short name T372
Test name
Test status
Simulation time 26694827529 ps
CPU time 70.57 seconds
Started Jun 04 12:51:05 PM PDT 24
Finished Jun 04 12:52:18 PM PDT 24
Peak memory 204912 kb
Host smart-79fb31fb-5121-4eed-ac59-252eead56975
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818393634 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
rv_dm_jtag_dmi_csr_bit_bash.3818393634
Directory /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.4239085434
Short name T273
Test name
Test status
Simulation time 1941778628 ps
CPU time 6 seconds
Started Jun 04 12:51:04 PM PDT 24
Finished Jun 04 12:51:13 PM PDT 24
Peak memory 205040 kb
Host smart-865d6f77-37b0-4d3a-a9b8-bc7380175151
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239085434 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.4
239085434
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3437006593
Short name T394
Test name
Test status
Simulation time 360793335 ps
CPU time 1.18 seconds
Started Jun 04 12:51:02 PM PDT 24
Finished Jun 04 12:51:06 PM PDT 24
Peak memory 204708 kb
Host smart-df3049b9-6446-40c0-8610-4a7b0e49155d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437006593 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.3
437006593
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.3853041756
Short name T93
Test name
Test status
Simulation time 211520744 ps
CPU time 6.5 seconds
Started Jun 04 12:51:02 PM PDT 24
Finished Jun 04 12:51:10 PM PDT 24
Peak memory 205088 kb
Host smart-124e971e-c3b8-40bd-9b91-96a432d7f979
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853041756 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.3853041756
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.2942215957
Short name T124
Test name
Test status
Simulation time 60283142471 ps
CPU time 53.78 seconds
Started Jun 04 12:51:02 PM PDT 24
Finished Jun 04 12:51:57 PM PDT 24
Peak memory 221648 kb
Host smart-2306ac22-90cf-4c02-8810-c697a0126228
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942215957 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.2942215957
Directory /workspace/5.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.4091702610
Short name T59
Test name
Test status
Simulation time 104407279 ps
CPU time 4.71 seconds
Started Jun 04 12:51:03 PM PDT 24
Finished Jun 04 12:51:11 PM PDT 24
Peak memory 213292 kb
Host smart-1c3f10ea-df6a-4319-8657-9903011018a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091702610 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.4091702610
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.423222028
Short name T334
Test name
Test status
Simulation time 684971391 ps
CPU time 9.08 seconds
Started Jun 04 12:51:03 PM PDT 24
Finished Jun 04 12:51:15 PM PDT 24
Peak memory 213244 kb
Host smart-d5c4142b-5e2f-4457-800d-f0746695a9ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423222028 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.423222028
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.3636547133
Short name T57
Test name
Test status
Simulation time 743416984 ps
CPU time 2.49 seconds
Started Jun 04 12:51:10 PM PDT 24
Finished Jun 04 12:51:14 PM PDT 24
Peak memory 215128 kb
Host smart-395db892-2c7a-4e85-b27c-fce9a46245ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636547133 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.3636547133
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1529901170
Short name T332
Test name
Test status
Simulation time 89386291 ps
CPU time 1.61 seconds
Started Jun 04 12:51:09 PM PDT 24
Finished Jun 04 12:51:13 PM PDT 24
Peak memory 213064 kb
Host smart-c51079e2-4b3c-466a-a693-3970c042fef9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529901170 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.1529901170
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.2562357667
Short name T386
Test name
Test status
Simulation time 2850827210 ps
CPU time 2.6 seconds
Started Jun 04 12:51:06 PM PDT 24
Finished Jun 04 12:51:11 PM PDT 24
Peak memory 204924 kb
Host smart-85b54892-034b-4f36-a04e-816a58e8f4b6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562357667 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
rv_dm_jtag_dmi_csr_bit_bash.2562357667
Directory /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.4119800693
Short name T374
Test name
Test status
Simulation time 5003688352 ps
CPU time 9.51 seconds
Started Jun 04 12:51:11 PM PDT 24
Finished Jun 04 12:51:22 PM PDT 24
Peak memory 204860 kb
Host smart-77df4985-85ed-4890-927b-0109eb281fe6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119800693 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.4
119800693
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.1777892816
Short name T312
Test name
Test status
Simulation time 148332222 ps
CPU time 0.73 seconds
Started Jun 04 12:51:04 PM PDT 24
Finished Jun 04 12:51:07 PM PDT 24
Peak memory 204644 kb
Host smart-32608adb-d9fc-42d8-8aa3-5cbd9a7a3d55
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777892816 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.1
777892816
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.1545132072
Short name T395
Test name
Test status
Simulation time 2733653698 ps
CPU time 7.67 seconds
Started Jun 04 12:51:13 PM PDT 24
Finished Jun 04 12:51:21 PM PDT 24
Peak memory 205092 kb
Host smart-faf3f91e-fe22-47c1-8956-0fb7dc06c64e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545132072 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.1545132072
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.826084566
Short name T384
Test name
Test status
Simulation time 26864458594 ps
CPU time 10.96 seconds
Started Jun 04 12:51:17 PM PDT 24
Finished Jun 04 12:51:28 PM PDT 24
Peak memory 220384 kb
Host smart-4cdd3c53-1652-4f08-a65f-03def9993c31
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826084566 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.826084566
Directory /workspace/6.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.278897394
Short name T351
Test name
Test status
Simulation time 86126401 ps
CPU time 3.37 seconds
Started Jun 04 12:51:11 PM PDT 24
Finished Jun 04 12:51:16 PM PDT 24
Peak memory 213392 kb
Host smart-fc7fac97-685e-4780-a2dc-afed40f22472
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278897394 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.278897394
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.3418925666
Short name T362
Test name
Test status
Simulation time 4007512189 ps
CPU time 19.46 seconds
Started Jun 04 12:51:10 PM PDT 24
Finished Jun 04 12:51:31 PM PDT 24
Peak memory 213172 kb
Host smart-0bed2949-c19b-4733-b089-770f5692b38b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418925666 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.3418925666
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.364602906
Short name T298
Test name
Test status
Simulation time 1687725264 ps
CPU time 6.97 seconds
Started Jun 04 12:51:08 PM PDT 24
Finished Jun 04 12:51:16 PM PDT 24
Peak memory 219988 kb
Host smart-55e978fb-afa1-45e4-81dc-901d61667731
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364602906 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.364602906
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.236653060
Short name T99
Test name
Test status
Simulation time 200560764 ps
CPU time 1.5 seconds
Started Jun 04 12:51:08 PM PDT 24
Finished Jun 04 12:51:12 PM PDT 24
Peak memory 213204 kb
Host smart-76966040-174f-488e-ab08-ce944f7804a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236653060 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.236653060
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.2130810861
Short name T283
Test name
Test status
Simulation time 31745800585 ps
CPU time 85.08 seconds
Started Jun 04 12:51:12 PM PDT 24
Finished Jun 04 12:52:38 PM PDT 24
Peak memory 204988 kb
Host smart-ca31af82-6ac6-4115-b72e-87bc3c33713a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130810861 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
rv_dm_jtag_dmi_csr_bit_bash.2130810861
Directory /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.1928358531
Short name T276
Test name
Test status
Simulation time 3728678588 ps
CPU time 11.34 seconds
Started Jun 04 12:51:05 PM PDT 24
Finished Jun 04 12:51:19 PM PDT 24
Peak memory 204972 kb
Host smart-780d8f88-7c87-41f0-b4b3-ba5c07abb710
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928358531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.1
928358531
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.452496401
Short name T53
Test name
Test status
Simulation time 274465643 ps
CPU time 1.12 seconds
Started Jun 04 12:51:06 PM PDT 24
Finished Jun 04 12:51:09 PM PDT 24
Peak memory 204624 kb
Host smart-7834e8cf-4e7a-4420-b15f-2ca86820105e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452496401 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.452496401
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.1190836168
Short name T49
Test name
Test status
Simulation time 1729777686 ps
CPU time 7.83 seconds
Started Jun 04 12:51:14 PM PDT 24
Finished Jun 04 12:51:23 PM PDT 24
Peak memory 205132 kb
Host smart-b709863b-1730-4475-b897-a90186887597
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190836168 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.1190836168
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.2948845720
Short name T299
Test name
Test status
Simulation time 207064826 ps
CPU time 5.2 seconds
Started Jun 04 12:51:06 PM PDT 24
Finished Jun 04 12:51:13 PM PDT 24
Peak memory 213336 kb
Host smart-a8b37a2c-0037-4ca0-b7b7-b0f7eddb7daa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948845720 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.2948845720
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.3469139430
Short name T120
Test name
Test status
Simulation time 2116755172 ps
CPU time 19.51 seconds
Started Jun 04 12:51:13 PM PDT 24
Finished Jun 04 12:51:34 PM PDT 24
Peak memory 213180 kb
Host smart-a6959b82-98c9-4b41-90bc-a07d7db1680f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469139430 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.3469139430
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.4139639239
Short name T328
Test name
Test status
Simulation time 400110480 ps
CPU time 2.11 seconds
Started Jun 04 12:51:09 PM PDT 24
Finished Jun 04 12:51:13 PM PDT 24
Peak memory 215308 kb
Host smart-89bf8f9a-188d-4e5d-bb82-91975165a398
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139639239 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.4139639239
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1522036552
Short name T321
Test name
Test status
Simulation time 381335392 ps
CPU time 2.31 seconds
Started Jun 04 12:51:12 PM PDT 24
Finished Jun 04 12:51:15 PM PDT 24
Peak memory 213160 kb
Host smart-e35431b3-ca48-40c4-b7a8-4ccd7bccb220
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522036552 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.1522036552
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.293787458
Short name T269
Test name
Test status
Simulation time 16611919605 ps
CPU time 46.07 seconds
Started Jun 04 12:51:19 PM PDT 24
Finished Jun 04 12:52:06 PM PDT 24
Peak memory 204880 kb
Host smart-5fcdb1d7-1182-4cb2-92ba-22c930ba27a8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293787458 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.r
v_dm_jtag_dmi_csr_bit_bash.293787458
Directory /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3035561512
Short name T287
Test name
Test status
Simulation time 7148620308 ps
CPU time 14.65 seconds
Started Jun 04 12:51:11 PM PDT 24
Finished Jun 04 12:51:28 PM PDT 24
Peak memory 204992 kb
Host smart-a4dcf006-eec3-4777-88e1-48b7eb2fb92e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035561512 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.3
035561512
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2116263770
Short name T54
Test name
Test status
Simulation time 756746180 ps
CPU time 1.7 seconds
Started Jun 04 12:51:12 PM PDT 24
Finished Jun 04 12:51:15 PM PDT 24
Peak memory 204588 kb
Host smart-e5323ffb-2598-47be-9bd3-985a0d1417c0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116263770 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.2
116263770
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.1634854826
Short name T74
Test name
Test status
Simulation time 2834830318 ps
CPU time 8.02 seconds
Started Jun 04 12:51:10 PM PDT 24
Finished Jun 04 12:51:19 PM PDT 24
Peak memory 205116 kb
Host smart-dd47fc8b-a9e7-42c3-83f9-fa71dca076cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634854826 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_
csr_outstanding.1634854826
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2725805181
Short name T337
Test name
Test status
Simulation time 495799774 ps
CPU time 2.89 seconds
Started Jun 04 12:51:09 PM PDT 24
Finished Jun 04 12:51:13 PM PDT 24
Peak memory 213284 kb
Host smart-4f7e08f0-b4d4-4142-b6bd-5ca87aaf21e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725805181 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.2725805181
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.179167438
Short name T119
Test name
Test status
Simulation time 2109917677 ps
CPU time 14.74 seconds
Started Jun 04 12:51:05 PM PDT 24
Finished Jun 04 12:51:22 PM PDT 24
Peak memory 213176 kb
Host smart-5bd888f3-51b4-4129-a117-0367f01b672a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179167438 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.179167438
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3257096921
Short name T339
Test name
Test status
Simulation time 5843303620 ps
CPU time 4.85 seconds
Started Jun 04 12:51:08 PM PDT 24
Finished Jun 04 12:51:14 PM PDT 24
Peak memory 219728 kb
Host smart-fdfff700-2280-44c3-b6ec-0dc18b06156a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257096921 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.3257096921
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1580942813
Short name T69
Test name
Test status
Simulation time 211897135 ps
CPU time 1.85 seconds
Started Jun 04 12:51:11 PM PDT 24
Finished Jun 04 12:51:15 PM PDT 24
Peak memory 213180 kb
Host smart-a542e7b4-953c-4f9d-b3de-7c19e5d87a1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580942813 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.1580942813
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.600816292
Short name T413
Test name
Test status
Simulation time 31080070310 ps
CPU time 44.98 seconds
Started Jun 04 12:51:13 PM PDT 24
Finished Jun 04 12:51:59 PM PDT 24
Peak memory 204964 kb
Host smart-67a79285-6bad-402f-9532-d54de8d74432
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600816292 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.r
v_dm_jtag_dmi_csr_bit_bash.600816292
Directory /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.2363394659
Short name T392
Test name
Test status
Simulation time 8566194276 ps
CPU time 13.02 seconds
Started Jun 04 12:51:10 PM PDT 24
Finished Jun 04 12:51:25 PM PDT 24
Peak memory 204944 kb
Host smart-909b22e8-b14b-4c80-ad7e-8a0ed407646c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363394659 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.2
363394659
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.3333257742
Short name T396
Test name
Test status
Simulation time 965460473 ps
CPU time 3.2 seconds
Started Jun 04 12:51:13 PM PDT 24
Finished Jun 04 12:51:17 PM PDT 24
Peak memory 204680 kb
Host smart-ff52228b-7925-4eb5-bbcb-92a0d81c4819
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333257742 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.3
333257742
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.1323678552
Short name T385
Test name
Test status
Simulation time 296034450 ps
CPU time 4.21 seconds
Started Jun 04 12:51:14 PM PDT 24
Finished Jun 04 12:51:19 PM PDT 24
Peak memory 204600 kb
Host smart-ff59b96e-950f-4714-8de4-2725045cdc8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323678552 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.1323678552
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.2915388313
Short name T284
Test name
Test status
Simulation time 181402998 ps
CPU time 3.47 seconds
Started Jun 04 12:51:11 PM PDT 24
Finished Jun 04 12:51:16 PM PDT 24
Peak memory 213340 kb
Host smart-cb46422e-eb95-4834-a9d3-6113b9154931
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915388313 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.2915388313
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2180135160
Short name T381
Test name
Test status
Simulation time 567782442 ps
CPU time 8.85 seconds
Started Jun 04 12:51:09 PM PDT 24
Finished Jun 04 12:51:20 PM PDT 24
Peak memory 213280 kb
Host smart-4747de28-a069-474c-b012-822ae5d24a0a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180135160 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.2180135160
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.1396573193
Short name T108
Test name
Test status
Simulation time 88933700 ps
CPU time 0.7 seconds
Started Jun 04 12:52:38 PM PDT 24
Finished Jun 04 12:52:40 PM PDT 24
Peak memory 204704 kb
Host smart-385a4ed9-cb79-46d5-9c6a-c3ab251bada9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396573193 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.1396573193
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.3286804458
Short name T257
Test name
Test status
Simulation time 14726229024 ps
CPU time 10.33 seconds
Started Jun 04 12:52:49 PM PDT 24
Finished Jun 04 12:53:01 PM PDT 24
Peak memory 213428 kb
Host smart-6a17c5ae-8a13-4321-a216-c44da5c7226b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286804458 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.3286804458
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.1013641539
Short name T179
Test name
Test status
Simulation time 2478031509 ps
CPU time 8.45 seconds
Started Jun 04 12:52:40 PM PDT 24
Finished Jun 04 12:52:49 PM PDT 24
Peak memory 205224 kb
Host smart-ef0c1400-9a32-45de-8595-3783af702136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013641539 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.1013641539
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.1219226197
Short name T134
Test name
Test status
Simulation time 22186506006 ps
CPU time 33.44 seconds
Started Jun 04 12:52:35 PM PDT 24
Finished Jun 04 12:53:10 PM PDT 24
Peak memory 204976 kb
Host smart-32dcd3bd-411d-426d-b69f-472d41086beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219226197 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.1219226197
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.3893167551
Short name T130
Test name
Test status
Simulation time 20186702235 ps
CPU time 15.16 seconds
Started Jun 04 12:52:43 PM PDT 24
Finished Jun 04 12:52:59 PM PDT 24
Peak memory 205048 kb
Host smart-5d930bb7-70fd-410c-a4bf-ada21edfec5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893167551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.3893167551
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.3944784402
Short name T220
Test name
Test status
Simulation time 157973535 ps
CPU time 0.85 seconds
Started Jun 04 12:52:40 PM PDT 24
Finished Jun 04 12:52:41 PM PDT 24
Peak memory 204684 kb
Host smart-aed21ae9-e611-4ac2-9005-4ab61483725b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944784402 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.3944784402
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.897215067
Short name T83
Test name
Test status
Simulation time 1514243782 ps
CPU time 1.94 seconds
Started Jun 04 12:52:38 PM PDT 24
Finished Jun 04 12:52:41 PM PDT 24
Peak memory 204968 kb
Host smart-ba5618f8-cd08-4b4a-bd83-4605b4821503
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=897215067 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_tl
_access.897215067
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.2349291787
Short name T61
Test name
Test status
Simulation time 1221055155 ps
CPU time 1.53 seconds
Started Jun 04 12:52:46 PM PDT 24
Finished Jun 04 12:52:48 PM PDT 24
Peak memory 204708 kb
Host smart-56991b53-ed39-4ac6-bc77-58c503ccc861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349291787 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.2349291787
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.952920138
Short name T251
Test name
Test status
Simulation time 202476856 ps
CPU time 1.19 seconds
Started Jun 04 12:52:38 PM PDT 24
Finished Jun 04 12:52:40 PM PDT 24
Peak memory 204520 kb
Host smart-aee1e61f-a349-4672-83c0-ef32fc8cf410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952920138 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.952920138
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.2025330013
Short name T12
Test name
Test status
Simulation time 1719023538 ps
CPU time 2.37 seconds
Started Jun 04 12:52:40 PM PDT 24
Finished Jun 04 12:52:43 PM PDT 24
Peak memory 204548 kb
Host smart-dcd630de-c30d-4180-8f84-a62393bd29ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025330013 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.2025330013
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.4229631991
Short name T19
Test name
Test status
Simulation time 2824171902 ps
CPU time 2.65 seconds
Started Jun 04 12:52:45 PM PDT 24
Finished Jun 04 12:52:48 PM PDT 24
Peak memory 204684 kb
Host smart-391a71af-51da-49aa-92e0-3b345e8df76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229631991 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.4229631991
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.3381433366
Short name T241
Test name
Test status
Simulation time 622544646 ps
CPU time 1.2 seconds
Started Jun 04 12:52:34 PM PDT 24
Finished Jun 04 12:52:36 PM PDT 24
Peak memory 204440 kb
Host smart-7507a722-796b-4541-9ce3-945aaf7e3335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381433366 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.3381433366
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.3888508953
Short name T202
Test name
Test status
Simulation time 315087796 ps
CPU time 0.8 seconds
Started Jun 04 12:52:49 PM PDT 24
Finished Jun 04 12:52:52 PM PDT 24
Peak memory 204544 kb
Host smart-5ed71476-0bf0-4ade-8b23-29b913acc2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888508953 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.3888508953
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.2845601352
Short name T137
Test name
Test status
Simulation time 849848939 ps
CPU time 1.87 seconds
Started Jun 04 12:52:36 PM PDT 24
Finished Jun 04 12:52:39 PM PDT 24
Peak memory 204668 kb
Host smart-aec9db6d-678c-4825-8a19-949b8395862c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845601352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.2845601352
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.2526261428
Short name T135
Test name
Test status
Simulation time 2976024540 ps
CPU time 4.88 seconds
Started Jun 04 12:52:32 PM PDT 24
Finished Jun 04 12:52:38 PM PDT 24
Peak memory 205104 kb
Host smart-010ec814-8bbd-423a-9542-7e39d3cc33bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526261428 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.2526261428
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.3858664557
Short name T20
Test name
Test status
Simulation time 2550126495 ps
CPU time 3.19 seconds
Started Jun 04 12:52:46 PM PDT 24
Finished Jun 04 12:52:50 PM PDT 24
Peak memory 204996 kb
Host smart-e2a3b8d2-3d68-4b9f-8b6b-a5f8421f7bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858664557 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.3858664557
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.2031279147
Short name T226
Test name
Test status
Simulation time 7481769159 ps
CPU time 20.51 seconds
Started Jun 04 12:52:48 PM PDT 24
Finished Jun 04 12:53:11 PM PDT 24
Peak memory 205204 kb
Host smart-28d35505-9985-49f0-a327-3771903d40a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031279147 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.2031279147
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.782550959
Short name T52
Test name
Test status
Simulation time 575130935 ps
CPU time 1.49 seconds
Started Jun 04 12:52:39 PM PDT 24
Finished Jun 04 12:52:41 PM PDT 24
Peak memory 228928 kb
Host smart-f47ee3db-d4df-4bc6-89fe-9225c36a4e97
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782550959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.782550959
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.3566714528
Short name T222
Test name
Test status
Simulation time 1356571611 ps
CPU time 2.56 seconds
Started Jun 04 12:52:37 PM PDT 24
Finished Jun 04 12:52:41 PM PDT 24
Peak memory 204532 kb
Host smart-6bac139c-b58a-4f63-aa93-0b2c1f9476fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566714528 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.3566714528
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all.1525762469
Short name T126
Test name
Test status
Simulation time 10999672696 ps
CPU time 19.77 seconds
Started Jun 04 12:52:49 PM PDT 24
Finished Jun 04 12:53:11 PM PDT 24
Peak memory 213164 kb
Host smart-41e4b197-4287-4ffd-9de7-c8ba86e2d7d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525762469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.1525762469
Directory /workspace/0.rv_dm_stress_all/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.3259293123
Short name T39
Test name
Test status
Simulation time 186820159 ps
CPU time 1.21 seconds
Started Jun 04 12:52:50 PM PDT 24
Finished Jun 04 12:52:53 PM PDT 24
Peak memory 204684 kb
Host smart-84aa0f0d-072d-4d21-a8d2-6b14be65665f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259293123 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.3259293123
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.4110991983
Short name T65
Test name
Test status
Simulation time 178869642 ps
CPU time 0.79 seconds
Started Jun 04 12:52:48 PM PDT 24
Finished Jun 04 12:52:50 PM PDT 24
Peak memory 204744 kb
Host smart-105e5cce-bf85-4fe6-adda-e3f65f6b2257
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110991983 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.4110991983
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.2128642597
Short name T245
Test name
Test status
Simulation time 2738888113 ps
CPU time 1.55 seconds
Started Jun 04 12:52:42 PM PDT 24
Finished Jun 04 12:52:44 PM PDT 24
Peak memory 205112 kb
Host smart-e0fad11f-820e-493f-9cd0-f939ac4fbede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128642597 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.2128642597
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.3465374368
Short name T14
Test name
Test status
Simulation time 8754216687 ps
CPU time 14.54 seconds
Started Jun 04 12:52:48 PM PDT 24
Finished Jun 04 12:53:04 PM PDT 24
Peak memory 205024 kb
Host smart-e1f6ce0a-2d9b-43a7-af13-514f6ea9513b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465374368 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.3465374368
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.1203604616
Short name T17
Test name
Test status
Simulation time 357448695 ps
CPU time 1.01 seconds
Started Jun 04 12:52:48 PM PDT 24
Finished Jun 04 12:52:51 PM PDT 24
Peak memory 204624 kb
Host smart-c2554c82-5522-414e-9970-14f1b692032a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203604616 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.1203604616
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.3109872185
Short name T29
Test name
Test status
Simulation time 2339738329 ps
CPU time 2.29 seconds
Started Jun 04 12:52:34 PM PDT 24
Finished Jun 04 12:52:37 PM PDT 24
Peak memory 204656 kb
Host smart-b54eaace-d0d6-4373-8eea-dfad78316186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109872185 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.3109872185
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.3981294973
Short name T139
Test name
Test status
Simulation time 17818506335 ps
CPU time 4.52 seconds
Started Jun 04 12:52:41 PM PDT 24
Finished Jun 04 12:52:46 PM PDT 24
Peak memory 204908 kb
Host smart-de23920c-f044-4dc5-861e-197055795e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981294973 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.3981294973
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.4218570948
Short name T219
Test name
Test status
Simulation time 353588043 ps
CPU time 0.98 seconds
Started Jun 04 12:52:48 PM PDT 24
Finished Jun 04 12:52:51 PM PDT 24
Peak memory 204712 kb
Host smart-5b4ebfda-6c6c-4dee-9e62-f8c98cf7f1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218570948 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.4218570948
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.453775252
Short name T236
Test name
Test status
Simulation time 5557485238 ps
CPU time 9.22 seconds
Started Jun 04 12:52:49 PM PDT 24
Finished Jun 04 12:53:00 PM PDT 24
Peak memory 205128 kb
Host smart-8cfbf14c-f292-49b7-aa8b-9d96d7c3a829
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=453775252 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_tl
_access.453775252
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.3743906637
Short name T198
Test name
Test status
Simulation time 161881791 ps
CPU time 1.13 seconds
Started Jun 04 12:52:35 PM PDT 24
Finished Jun 04 12:52:38 PM PDT 24
Peak memory 204504 kb
Host smart-a33e847b-7491-46b6-9415-a50aea7ebe41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743906637 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.3743906637
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.1611572123
Short name T45
Test name
Test status
Simulation time 1255818936 ps
CPU time 2.57 seconds
Started Jun 04 12:52:46 PM PDT 24
Finished Jun 04 12:52:50 PM PDT 24
Peak memory 204560 kb
Host smart-74f5db92-df7a-416b-ae50-b65a2e39faed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611572123 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.1611572123
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.2813687365
Short name T201
Test name
Test status
Simulation time 493513629 ps
CPU time 1.45 seconds
Started Jun 04 12:52:53 PM PDT 24
Finished Jun 04 12:52:55 PM PDT 24
Peak memory 204440 kb
Host smart-d1b95f70-f3d0-492d-ab44-a6747393f2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813687365 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.2813687365
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.1274587798
Short name T249
Test name
Test status
Simulation time 2895891627 ps
CPU time 8.06 seconds
Started Jun 04 12:52:49 PM PDT 24
Finished Jun 04 12:52:59 PM PDT 24
Peak memory 204808 kb
Host smart-e54596ff-4eb6-4c32-993f-d052cce69751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274587798 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.1274587798
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.1485862580
Short name T192
Test name
Test status
Simulation time 188036893 ps
CPU time 1.17 seconds
Started Jun 04 12:52:40 PM PDT 24
Finished Jun 04 12:52:42 PM PDT 24
Peak memory 204584 kb
Host smart-c29ea8ba-5d69-4571-82a3-c0d01fcbcf01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485862580 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.1485862580
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.991250700
Short name T136
Test name
Test status
Simulation time 414881947 ps
CPU time 1.32 seconds
Started Jun 04 12:52:34 PM PDT 24
Finished Jun 04 12:52:36 PM PDT 24
Peak memory 204588 kb
Host smart-5f0f35c1-6ffa-468b-a617-03db794e47ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991250700 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.991250700
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.3664982123
Short name T131
Test name
Test status
Simulation time 1573479217 ps
CPU time 3.04 seconds
Started Jun 04 12:52:42 PM PDT 24
Finished Jun 04 12:52:46 PM PDT 24
Peak memory 204656 kb
Host smart-80362d7d-46ce-41b0-b220-852e41876ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664982123 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.3664982123
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.2418066189
Short name T129
Test name
Test status
Simulation time 536023718 ps
CPU time 1.53 seconds
Started Jun 04 12:52:39 PM PDT 24
Finished Jun 04 12:52:41 PM PDT 24
Peak memory 204608 kb
Host smart-d2b98d49-90df-49cd-a30b-58e52d6ace86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418066189 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.2418066189
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.2748744888
Short name T33
Test name
Test status
Simulation time 4766877416 ps
CPU time 5.1 seconds
Started Jun 04 12:52:54 PM PDT 24
Finished Jun 04 12:53:00 PM PDT 24
Peak memory 205008 kb
Host smart-7e0b84b4-168d-4cc9-9b6d-3b89631e6fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748744888 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.2748744888
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.3805291455
Short name T7
Test name
Test status
Simulation time 730266215 ps
CPU time 1.22 seconds
Started Jun 04 12:52:55 PM PDT 24
Finished Jun 04 12:52:57 PM PDT 24
Peak memory 204720 kb
Host smart-7f60e583-44d9-4b32-a59e-4178da0dc96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805291455 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.3805291455
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.3717943665
Short name T31
Test name
Test status
Simulation time 103738522 ps
CPU time 0.87 seconds
Started Jun 04 12:52:46 PM PDT 24
Finished Jun 04 12:52:48 PM PDT 24
Peak memory 212920 kb
Host smart-52efc025-322d-4c07-9194-d4ace0083357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717943665 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.3717943665
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.1893074341
Short name T172
Test name
Test status
Simulation time 2798663099 ps
CPU time 4.9 seconds
Started Jun 04 12:52:47 PM PDT 24
Finished Jun 04 12:52:54 PM PDT 24
Peak memory 205096 kb
Host smart-dbdfb553-4285-4479-ba20-b765255e853a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893074341 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.1893074341
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.2103990981
Short name T40
Test name
Test status
Simulation time 502805907 ps
CPU time 2.02 seconds
Started Jun 04 12:52:40 PM PDT 24
Finished Jun 04 12:52:43 PM PDT 24
Peak memory 228960 kb
Host smart-56ee2f96-5e8c-4b13-98b4-0daff9dbe846
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103990981 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.2103990981
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.2804777699
Short name T195
Test name
Test status
Simulation time 924195858 ps
CPU time 3.54 seconds
Started Jun 04 12:52:41 PM PDT 24
Finished Jun 04 12:52:45 PM PDT 24
Peak memory 204608 kb
Host smart-e0e1a123-e50d-431f-ad4f-0281e497ed5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804777699 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.2804777699
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.2932515723
Short name T169
Test name
Test status
Simulation time 101855889 ps
CPU time 0.92 seconds
Started Jun 04 12:52:51 PM PDT 24
Finished Jun 04 12:52:53 PM PDT 24
Peak memory 204792 kb
Host smart-80235c29-7499-4d12-893b-c8a636261a13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932515723 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.2932515723
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.3169888015
Short name T232
Test name
Test status
Simulation time 16127187289 ps
CPU time 26.55 seconds
Started Jun 04 12:52:56 PM PDT 24
Finished Jun 04 12:53:24 PM PDT 24
Peak memory 205216 kb
Host smart-7f3f524c-33cc-44d5-ab88-c864191cd36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169888015 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.3169888015
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.4227596570
Short name T216
Test name
Test status
Simulation time 19397752879 ps
CPU time 53.64 seconds
Started Jun 04 12:52:46 PM PDT 24
Finished Jun 04 12:53:41 PM PDT 24
Peak memory 221492 kb
Host smart-7da82dc5-1c67-4e76-bd58-94476084b4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227596570 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.4227596570
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.805568229
Short name T252
Test name
Test status
Simulation time 1427278131 ps
CPU time 2.61 seconds
Started Jun 04 12:52:49 PM PDT 24
Finished Jun 04 12:52:53 PM PDT 24
Peak memory 205116 kb
Host smart-a14715ff-4a9a-4d05-a0b4-8357bec527ea
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=805568229 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_t
l_access.805568229
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.2469612400
Short name T174
Test name
Test status
Simulation time 4287002164 ps
CPU time 12.77 seconds
Started Jun 04 12:53:01 PM PDT 24
Finished Jun 04 12:53:16 PM PDT 24
Peak memory 205176 kb
Host smart-8b5e6dc9-5c9a-4a62-b68b-74e0ec7b8f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469612400 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.2469612400
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.1249047813
Short name T63
Test name
Test status
Simulation time 100439210 ps
CPU time 0.7 seconds
Started Jun 04 12:52:47 PM PDT 24
Finished Jun 04 12:52:49 PM PDT 24
Peak memory 204828 kb
Host smart-8e1ca551-a1a9-44ef-b3b4-7d76cc8091b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249047813 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.1249047813
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.2746096627
Short name T217
Test name
Test status
Simulation time 9315501825 ps
CPU time 10.6 seconds
Started Jun 04 12:52:45 PM PDT 24
Finished Jun 04 12:52:56 PM PDT 24
Peak memory 205280 kb
Host smart-a953706c-adbf-40b7-abf3-67ee1681d73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746096627 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.2746096627
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.2750408506
Short name T175
Test name
Test status
Simulation time 4151216192 ps
CPU time 6.24 seconds
Started Jun 04 12:52:50 PM PDT 24
Finished Jun 04 12:52:58 PM PDT 24
Peak memory 205152 kb
Host smart-2c155b54-d9e6-418f-afe4-c857b6d741e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750408506 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.2750408506
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.4239330674
Short name T218
Test name
Test status
Simulation time 1270467093 ps
CPU time 3.9 seconds
Started Jun 04 12:52:56 PM PDT 24
Finished Jun 04 12:53:01 PM PDT 24
Peak memory 205004 kb
Host smart-b3bcd232-94ee-46c1-9104-ec47f11f8dec
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4239330674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_
tl_access.4239330674
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.1571831965
Short name T262
Test name
Test status
Simulation time 9987332403 ps
CPU time 26.07 seconds
Started Jun 04 12:52:49 PM PDT 24
Finished Jun 04 12:53:17 PM PDT 24
Peak memory 205160 kb
Host smart-020342cc-215b-4e8b-bb7a-85bea1069c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571831965 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.1571831965
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_stress_all.386192100
Short name T38
Test name
Test status
Simulation time 28648862080 ps
CPU time 84.25 seconds
Started Jun 04 12:52:47 PM PDT 24
Finished Jun 04 12:54:13 PM PDT 24
Peak memory 205080 kb
Host smart-adbf70e6-c9f4-4daf-ac57-5c9990dff6d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386192100 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.386192100
Directory /workspace/11.rv_dm_stress_all/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.1872663952
Short name T145
Test name
Test status
Simulation time 81867052 ps
CPU time 0.85 seconds
Started Jun 04 12:52:51 PM PDT 24
Finished Jun 04 12:52:53 PM PDT 24
Peak memory 204788 kb
Host smart-35c1299a-5b33-4059-8bd0-053bbe16730a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872663952 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.1872663952
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.724721005
Short name T200
Test name
Test status
Simulation time 8431907788 ps
CPU time 26.9 seconds
Started Jun 04 12:52:58 PM PDT 24
Finished Jun 04 12:53:26 PM PDT 24
Peak memory 213356 kb
Host smart-1d91cb69-1861-4a68-ba30-b931cfcbef6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724721005 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.724721005
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.160517973
Short name T173
Test name
Test status
Simulation time 1685496629 ps
CPU time 5.55 seconds
Started Jun 04 12:52:50 PM PDT 24
Finished Jun 04 12:52:57 PM PDT 24
Peak memory 204976 kb
Host smart-4be6d0fd-fc9f-4a0f-9edf-69988cb7f367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160517973 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.160517973
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.4165343506
Short name T184
Test name
Test status
Simulation time 3556898288 ps
CPU time 3.06 seconds
Started Jun 04 12:52:58 PM PDT 24
Finished Jun 04 12:53:03 PM PDT 24
Peak memory 205148 kb
Host smart-d1901267-c75d-4937-b40a-f1067b3b83fc
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4165343506 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.4165343506
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.3747267622
Short name T177
Test name
Test status
Simulation time 1130302997 ps
CPU time 1.33 seconds
Started Jun 04 12:52:57 PM PDT 24
Finished Jun 04 12:53:01 PM PDT 24
Peak memory 205060 kb
Host smart-6ad92343-8487-448e-92cb-e05ccb02b234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747267622 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.3747267622
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.2382416613
Short name T168
Test name
Test status
Simulation time 61606757 ps
CPU time 0.75 seconds
Started Jun 04 12:53:00 PM PDT 24
Finished Jun 04 12:53:02 PM PDT 24
Peak memory 204716 kb
Host smart-01f13941-4318-498e-b4ba-fb8d22988c65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382416613 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.2382416613
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.3199989331
Short name T258
Test name
Test status
Simulation time 7754455411 ps
CPU time 12.67 seconds
Started Jun 04 12:53:03 PM PDT 24
Finished Jun 04 12:53:17 PM PDT 24
Peak memory 213304 kb
Host smart-a4909d49-c40e-4dcf-910d-d9ad976f6496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199989331 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.3199989331
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.677002927
Short name T205
Test name
Test status
Simulation time 4633647791 ps
CPU time 3.83 seconds
Started Jun 04 12:53:04 PM PDT 24
Finished Jun 04 12:53:09 PM PDT 24
Peak memory 205188 kb
Host smart-74cd7365-1823-4fca-a564-7316039aa2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677002927 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.677002927
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.4067528713
Short name T227
Test name
Test status
Simulation time 3443857265 ps
CPU time 10.98 seconds
Started Jun 04 12:52:51 PM PDT 24
Finished Jun 04 12:53:03 PM PDT 24
Peak memory 205184 kb
Host smart-e25b492f-fcd8-4625-810e-74d2055ef11c
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4067528713 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_
tl_access.4067528713
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.1833878718
Short name T256
Test name
Test status
Simulation time 14072859757 ps
CPU time 11.53 seconds
Started Jun 04 12:52:49 PM PDT 24
Finished Jun 04 12:53:02 PM PDT 24
Peak memory 205112 kb
Host smart-f1e01396-6d3f-49e4-ab4c-f88d591046fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833878718 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.1833878718
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_stress_all.2467313781
Short name T35
Test name
Test status
Simulation time 58134710485 ps
CPU time 35.9 seconds
Started Jun 04 12:53:03 PM PDT 24
Finished Jun 04 12:53:41 PM PDT 24
Peak memory 213176 kb
Host smart-16eced88-687c-4ecd-9f55-c2dc35a4f1f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467313781 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.2467313781
Directory /workspace/13.rv_dm_stress_all/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.2886267398
Short name T141
Test name
Test status
Simulation time 145629685 ps
CPU time 0.69 seconds
Started Jun 04 12:52:58 PM PDT 24
Finished Jun 04 12:53:00 PM PDT 24
Peak memory 204820 kb
Host smart-ccbdd796-c854-4903-9740-4b0829185963
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886267398 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.2886267398
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.2751790630
Short name T260
Test name
Test status
Simulation time 10950015313 ps
CPU time 31.97 seconds
Started Jun 04 12:52:56 PM PDT 24
Finished Jun 04 12:53:29 PM PDT 24
Peak memory 205216 kb
Host smart-733042d4-7d1a-44c0-a8db-9cf42c4c607d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751790630 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.2751790630
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.835946685
Short name T180
Test name
Test status
Simulation time 5014484047 ps
CPU time 16.01 seconds
Started Jun 04 12:52:54 PM PDT 24
Finished Jun 04 12:53:11 PM PDT 24
Peak memory 205204 kb
Host smart-b0ae1963-fb69-49f0-9b53-357024c2753e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835946685 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.835946685
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.2568232803
Short name T188
Test name
Test status
Simulation time 1441522208 ps
CPU time 1.34 seconds
Started Jun 04 12:52:47 PM PDT 24
Finished Jun 04 12:52:50 PM PDT 24
Peak memory 205044 kb
Host smart-558874fa-d92c-4502-8dc6-f37ecd36c890
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2568232803 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.2568232803
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.2266965104
Short name T186
Test name
Test status
Simulation time 1455967943 ps
CPU time 1.94 seconds
Started Jun 04 12:52:57 PM PDT 24
Finished Jun 04 12:53:01 PM PDT 24
Peak memory 205048 kb
Host smart-c15436c5-57e4-45c8-a9f2-2610aae0cd5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266965104 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.2266965104
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_stress_all.3121347249
Short name T13
Test name
Test status
Simulation time 35658547218 ps
CPU time 29.41 seconds
Started Jun 04 12:52:57 PM PDT 24
Finished Jun 04 12:53:28 PM PDT 24
Peak memory 213176 kb
Host smart-1d2e4af4-4b34-474f-a5f6-7661b7d80779
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121347249 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.3121347249
Directory /workspace/14.rv_dm_stress_all/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.4022952962
Short name T204
Test name
Test status
Simulation time 39428109 ps
CPU time 0.79 seconds
Started Jun 04 12:53:05 PM PDT 24
Finished Jun 04 12:53:07 PM PDT 24
Peak memory 204764 kb
Host smart-d4abed36-432a-4956-9abd-58835a4380a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022952962 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.4022952962
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.2109440096
Short name T243
Test name
Test status
Simulation time 1417067876 ps
CPU time 2.89 seconds
Started Jun 04 12:53:01 PM PDT 24
Finished Jun 04 12:53:06 PM PDT 24
Peak memory 204972 kb
Host smart-2d2c0f47-331e-43f6-93a5-a25617c822c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109440096 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.2109440096
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.609193768
Short name T237
Test name
Test status
Simulation time 2522730944 ps
CPU time 2.56 seconds
Started Jun 04 12:52:52 PM PDT 24
Finished Jun 04 12:52:56 PM PDT 24
Peak memory 205164 kb
Host smart-9c32f55b-405f-4919-b7d9-13a4e294bd0e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=609193768 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_t
l_access.609193768
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.3116692531
Short name T242
Test name
Test status
Simulation time 20738979872 ps
CPU time 49.44 seconds
Started Jun 04 12:52:58 PM PDT 24
Finished Jun 04 12:53:49 PM PDT 24
Peak memory 205220 kb
Host smart-6b042476-78ac-42eb-a5c3-255743faf307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116692531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.3116692531
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.508842342
Short name T150
Test name
Test status
Simulation time 102202144 ps
CPU time 0.91 seconds
Started Jun 04 12:52:57 PM PDT 24
Finished Jun 04 12:53:00 PM PDT 24
Peak memory 204832 kb
Host smart-5dbfb141-9ca0-4d1b-87b6-a12f4ff4891e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508842342 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.508842342
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.4020559690
Short name T197
Test name
Test status
Simulation time 10821055923 ps
CPU time 18.23 seconds
Started Jun 04 12:53:01 PM PDT 24
Finished Jun 04 12:53:21 PM PDT 24
Peak memory 213296 kb
Host smart-128ecae1-ce97-4a45-be4f-addce5a292bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020559690 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.4020559690
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.2829281061
Short name T84
Test name
Test status
Simulation time 9727773054 ps
CPU time 14.21 seconds
Started Jun 04 12:52:57 PM PDT 24
Finished Jun 04 12:53:13 PM PDT 24
Peak memory 205244 kb
Host smart-cd650148-ddea-46cd-84c6-7712d414fbb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829281061 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.2829281061
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.2063014545
Short name T187
Test name
Test status
Simulation time 3761889136 ps
CPU time 7.53 seconds
Started Jun 04 12:52:58 PM PDT 24
Finished Jun 04 12:53:08 PM PDT 24
Peak memory 205144 kb
Host smart-7f83a64f-730a-4a6e-92be-a895d38aca65
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2063014545 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_
tl_access.2063014545
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.679710849
Short name T247
Test name
Test status
Simulation time 5322678807 ps
CPU time 4.41 seconds
Started Jun 04 12:52:58 PM PDT 24
Finished Jun 04 12:53:03 PM PDT 24
Peak memory 205188 kb
Host smart-a6e37af2-41d3-414e-8254-f293dc99d162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679710849 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.679710849
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.3489345932
Short name T163
Test name
Test status
Simulation time 234454283 ps
CPU time 0.68 seconds
Started Jun 04 12:52:55 PM PDT 24
Finished Jun 04 12:52:57 PM PDT 24
Peak memory 204836 kb
Host smart-ba0e32dd-c430-447e-94b0-4498ca3a3113
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489345932 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.3489345932
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.1143979158
Short name T183
Test name
Test status
Simulation time 5269371779 ps
CPU time 5.15 seconds
Started Jun 04 12:53:01 PM PDT 24
Finished Jun 04 12:53:09 PM PDT 24
Peak memory 213320 kb
Host smart-db99144a-210a-4028-9f8e-5ad4549f23a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143979158 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.1143979158
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.928501719
Short name T248
Test name
Test status
Simulation time 1424174419 ps
CPU time 4.9 seconds
Started Jun 04 12:52:55 PM PDT 24
Finished Jun 04 12:53:01 PM PDT 24
Peak memory 205104 kb
Host smart-17020508-8957-4230-95f7-adbe6cd61c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928501719 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.928501719
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.1775588837
Short name T228
Test name
Test status
Simulation time 3454196938 ps
CPU time 10.33 seconds
Started Jun 04 12:52:55 PM PDT 24
Finished Jun 04 12:53:06 PM PDT 24
Peak memory 205236 kb
Host smart-e1c779c3-6b52-4982-9a0e-212d11876636
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1775588837 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_
tl_access.1775588837
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.1266451851
Short name T221
Test name
Test status
Simulation time 1959705165 ps
CPU time 3.27 seconds
Started Jun 04 12:53:05 PM PDT 24
Finished Jun 04 12:53:09 PM PDT 24
Peak memory 204956 kb
Host smart-2a6b41ce-d107-4037-a457-1d85c189e184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266451851 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.1266451851
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.542813531
Short name T26
Test name
Test status
Simulation time 50912026 ps
CPU time 0.7 seconds
Started Jun 04 12:52:58 PM PDT 24
Finished Jun 04 12:53:00 PM PDT 24
Peak memory 204760 kb
Host smart-41699041-79e3-4bda-954c-ca9eb8cfc72f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542813531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.542813531
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.3483350152
Short name T208
Test name
Test status
Simulation time 58574273572 ps
CPU time 168.77 seconds
Started Jun 04 12:52:55 PM PDT 24
Finished Jun 04 12:55:45 PM PDT 24
Peak memory 213640 kb
Host smart-d27c4377-3f25-4027-9b22-e007eab2a6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483350152 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.3483350152
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.2464520315
Short name T196
Test name
Test status
Simulation time 2158260521 ps
CPU time 1.97 seconds
Started Jun 04 12:52:54 PM PDT 24
Finished Jun 04 12:52:57 PM PDT 24
Peak memory 205184 kb
Host smart-6c74530d-c9fc-4527-b6dc-4123f9fd7b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464520315 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.2464520315
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.2469223909
Short name T206
Test name
Test status
Simulation time 3883280123 ps
CPU time 5.64 seconds
Started Jun 04 12:52:55 PM PDT 24
Finished Jun 04 12:53:01 PM PDT 24
Peak memory 205184 kb
Host smart-225a5f93-c3b0-4229-b249-7b4ec0bf3a8f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2469223909 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_
tl_access.2469223909
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.141236684
Short name T215
Test name
Test status
Simulation time 3848366218 ps
CPU time 4.64 seconds
Started Jun 04 12:53:04 PM PDT 24
Finished Jun 04 12:53:10 PM PDT 24
Peak memory 205192 kb
Host smart-798d385a-fdfa-4043-a242-9cd7985b32d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141236684 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.141236684
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.1295351960
Short name T147
Test name
Test status
Simulation time 177587059 ps
CPU time 0.86 seconds
Started Jun 04 12:53:08 PM PDT 24
Finished Jun 04 12:53:10 PM PDT 24
Peak memory 204796 kb
Host smart-280fe491-659e-4b98-86bd-474b94549240
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295351960 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.1295351960
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.2120658401
Short name T259
Test name
Test status
Simulation time 69129782408 ps
CPU time 58.43 seconds
Started Jun 04 12:53:04 PM PDT 24
Finished Jun 04 12:54:03 PM PDT 24
Peak memory 214480 kb
Host smart-1ccbd10b-3a0c-4e62-ba23-c8b414aa249b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120658401 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.2120658401
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.1784660100
Short name T18
Test name
Test status
Simulation time 6504294867 ps
CPU time 7.86 seconds
Started Jun 04 12:53:00 PM PDT 24
Finished Jun 04 12:53:09 PM PDT 24
Peak memory 213348 kb
Host smart-f68171b9-a721-47c3-803f-a07a63305879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784660100 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.1784660100
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.2004370697
Short name T80
Test name
Test status
Simulation time 17942345004 ps
CPU time 49.86 seconds
Started Jun 04 12:53:07 PM PDT 24
Finished Jun 04 12:53:58 PM PDT 24
Peak memory 213368 kb
Host smart-e093df9b-9750-4509-bc91-e1c806895fb9
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2004370697 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_
tl_access.2004370697
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.3274381272
Short name T191
Test name
Test status
Simulation time 3955477324 ps
CPU time 2.8 seconds
Started Jun 04 12:52:59 PM PDT 24
Finished Jun 04 12:53:03 PM PDT 24
Peak memory 205232 kb
Host smart-b1e813f8-399a-4e35-818d-7182371c2c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274381272 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.3274381272
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_stress_all.466163472
Short name T128
Test name
Test status
Simulation time 25268447097 ps
CPU time 23.49 seconds
Started Jun 04 12:53:03 PM PDT 24
Finished Jun 04 12:53:28 PM PDT 24
Peak memory 213240 kb
Host smart-132b606b-31f8-434c-98f3-c757191b649e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466163472 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.466163472
Directory /workspace/19.rv_dm_stress_all/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.1511101418
Short name T158
Test name
Test status
Simulation time 31151876 ps
CPU time 0.74 seconds
Started Jun 04 12:52:40 PM PDT 24
Finished Jun 04 12:52:42 PM PDT 24
Peak memory 204792 kb
Host smart-4b5ae502-477a-4914-9f4d-6d5825fae270
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511101418 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.1511101418
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.254736114
Short name T238
Test name
Test status
Simulation time 1324808305 ps
CPU time 4.94 seconds
Started Jun 04 12:54:13 PM PDT 24
Finished Jun 04 12:54:19 PM PDT 24
Peak memory 204896 kb
Host smart-8a165712-359a-41ea-ae70-0f2274439f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254736114 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.254736114
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.930467247
Short name T233
Test name
Test status
Simulation time 10328801701 ps
CPU time 12.95 seconds
Started Jun 04 12:52:48 PM PDT 24
Finished Jun 04 12:53:02 PM PDT 24
Peak memory 205148 kb
Host smart-d448e953-b393-41ab-9770-6adca4cea688
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=930467247 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_tl
_access.930467247
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.245356886
Short name T11
Test name
Test status
Simulation time 332992325 ps
CPU time 1.17 seconds
Started Jun 04 12:52:51 PM PDT 24
Finished Jun 04 12:52:53 PM PDT 24
Peak memory 204492 kb
Host smart-b5571d92-1101-4435-b7af-8c7fa2cc8456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245356886 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.245356886
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.2285151811
Short name T209
Test name
Test status
Simulation time 3929547005 ps
CPU time 1.66 seconds
Started Jun 04 12:52:52 PM PDT 24
Finished Jun 04 12:52:55 PM PDT 24
Peak memory 205228 kb
Host smart-d06889b1-c157-4d4e-a35d-79d5890be297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285151811 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.2285151811
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.1195320905
Short name T51
Test name
Test status
Simulation time 479515488 ps
CPU time 2.45 seconds
Started Jun 04 12:52:50 PM PDT 24
Finished Jun 04 12:52:54 PM PDT 24
Peak memory 229076 kb
Host smart-0448cce6-3596-49e9-aea2-2ae761d36af6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195320905 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.1195320905
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/20.rv_dm_stress_all.608753939
Short name T132
Test name
Test status
Simulation time 7433873516 ps
CPU time 7.44 seconds
Started Jun 04 12:53:07 PM PDT 24
Finished Jun 04 12:53:16 PM PDT 24
Peak memory 213184 kb
Host smart-a8e74e0b-f2c3-4120-ab77-25aacd85e2bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608753939 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.608753939
Directory /workspace/20.rv_dm_stress_all/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.4016897836
Short name T142
Test name
Test status
Simulation time 85620663 ps
CPU time 0.7 seconds
Started Jun 04 12:52:56 PM PDT 24
Finished Jun 04 12:52:58 PM PDT 24
Peak memory 204792 kb
Host smart-03f8b924-dece-47b4-815c-3c7a3b8569d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016897836 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.4016897836
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_stress_all.177707120
Short name T127
Test name
Test status
Simulation time 14207381520 ps
CPU time 39.95 seconds
Started Jun 04 12:52:59 PM PDT 24
Finished Jun 04 12:53:40 PM PDT 24
Peak memory 205032 kb
Host smart-99143e15-45f3-4f8f-a385-0e21f61b8a5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177707120 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.177707120
Directory /workspace/21.rv_dm_stress_all/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.900688297
Short name T166
Test name
Test status
Simulation time 138081028 ps
CPU time 0.77 seconds
Started Jun 04 12:53:07 PM PDT 24
Finished Jun 04 12:53:09 PM PDT 24
Peak memory 204696 kb
Host smart-e40c8f3a-3d84-43b6-8945-ec948b396918
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900688297 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.900688297
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_stress_all.3966511791
Short name T214
Test name
Test status
Simulation time 22178045664 ps
CPU time 11.86 seconds
Started Jun 04 12:52:56 PM PDT 24
Finished Jun 04 12:53:09 PM PDT 24
Peak memory 205016 kb
Host smart-0a908d9b-ddf4-4e95-8c75-cba2cab84d7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966511791 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.3966511791
Directory /workspace/22.rv_dm_stress_all/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.281575863
Short name T144
Test name
Test status
Simulation time 138645040 ps
CPU time 0.74 seconds
Started Jun 04 12:52:58 PM PDT 24
Finished Jun 04 12:53:00 PM PDT 24
Peak memory 204812 kb
Host smart-58003ffb-7fd1-4fb2-892b-ab4890c94f37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281575863 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.281575863
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_stress_all.2979518830
Short name T6
Test name
Test status
Simulation time 30043363044 ps
CPU time 22.16 seconds
Started Jun 04 12:53:08 PM PDT 24
Finished Jun 04 12:53:32 PM PDT 24
Peak memory 204904 kb
Host smart-92a26034-1f29-4efe-b7f3-d34ab248abbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979518830 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.2979518830
Directory /workspace/23.rv_dm_stress_all/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.1887772410
Short name T140
Test name
Test status
Simulation time 102344935 ps
CPU time 0.73 seconds
Started Jun 04 12:52:57 PM PDT 24
Finished Jun 04 12:52:59 PM PDT 24
Peak memory 204816 kb
Host smart-ccc3693c-3d06-42f6-a466-51d48edc0263
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887772410 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.1887772410
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.4210465092
Short name T146
Test name
Test status
Simulation time 189034052 ps
CPU time 0.79 seconds
Started Jun 04 12:53:14 PM PDT 24
Finished Jun 04 12:53:16 PM PDT 24
Peak memory 204736 kb
Host smart-2e1491bc-37e8-4b3a-b1b8-f9232533cf0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210465092 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.4210465092
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.771909684
Short name T235
Test name
Test status
Simulation time 70096407 ps
CPU time 0.74 seconds
Started Jun 04 12:52:57 PM PDT 24
Finished Jun 04 12:52:59 PM PDT 24
Peak memory 204816 kb
Host smart-544d1e6a-86c3-4d44-a585-8681638a7159
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771909684 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.771909684
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_stress_all.3915788182
Short name T42
Test name
Test status
Simulation time 7594914269 ps
CPU time 11.07 seconds
Started Jun 04 12:53:00 PM PDT 24
Finished Jun 04 12:53:13 PM PDT 24
Peak memory 213188 kb
Host smart-3c83278e-ad65-46a7-8d49-896811888b96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915788182 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.3915788182
Directory /workspace/26.rv_dm_stress_all/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.501701116
Short name T28
Test name
Test status
Simulation time 46382947 ps
CPU time 0.72 seconds
Started Jun 04 12:53:06 PM PDT 24
Finished Jun 04 12:53:08 PM PDT 24
Peak memory 204772 kb
Host smart-318793e8-efaa-431b-acd9-c1af4b6813b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501701116 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.501701116
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.3419742598
Short name T151
Test name
Test status
Simulation time 71791220 ps
CPU time 0.76 seconds
Started Jun 04 12:53:06 PM PDT 24
Finished Jun 04 12:53:08 PM PDT 24
Peak memory 204772 kb
Host smart-249b46ae-4f7b-457d-9997-40fdfb387a44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419742598 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.3419742598
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.2887488650
Short name T107
Test name
Test status
Simulation time 143665305 ps
CPU time 0.78 seconds
Started Jun 04 12:53:07 PM PDT 24
Finished Jun 04 12:53:09 PM PDT 24
Peak memory 204696 kb
Host smart-5b829f3a-c833-48c0-9b9a-8ed1aa6e5af3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887488650 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.2887488650
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_stress_all.3435863121
Short name T138
Test name
Test status
Simulation time 13365374763 ps
CPU time 40.93 seconds
Started Jun 04 12:53:10 PM PDT 24
Finished Jun 04 12:53:52 PM PDT 24
Peak memory 213180 kb
Host smart-a6a1372a-9ee8-40e3-bf6b-5836ac8f85db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435863121 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.3435863121
Directory /workspace/29.rv_dm_stress_all/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.4097798167
Short name T3
Test name
Test status
Simulation time 65473972 ps
CPU time 0.87 seconds
Started Jun 04 12:53:02 PM PDT 24
Finished Jun 04 12:53:04 PM PDT 24
Peak memory 204664 kb
Host smart-ad40389e-13c8-4f19-812d-3d17bfdae76a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097798167 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.4097798167
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.1893874804
Short name T225
Test name
Test status
Simulation time 13955028807 ps
CPU time 16.19 seconds
Started Jun 04 12:52:40 PM PDT 24
Finished Jun 04 12:52:57 PM PDT 24
Peak memory 213388 kb
Host smart-8c0082bd-e80c-442d-a2f7-e521246ae3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893874804 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.1893874804
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.3489364227
Short name T181
Test name
Test status
Simulation time 2956165839 ps
CPU time 3.5 seconds
Started Jun 04 12:53:03 PM PDT 24
Finished Jun 04 12:53:08 PM PDT 24
Peak memory 205144 kb
Host smart-00c9e275-55d5-4fa5-8529-86fa32211a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489364227 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.3489364227
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.419276140
Short name T194
Test name
Test status
Simulation time 1897073354 ps
CPU time 6.32 seconds
Started Jun 04 12:53:58 PM PDT 24
Finished Jun 04 12:54:05 PM PDT 24
Peak memory 202848 kb
Host smart-6b6f471c-fd0f-455c-a81a-c76e6934e05e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=419276140 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_tl
_access.419276140
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.3590691574
Short name T223
Test name
Test status
Simulation time 347027880 ps
CPU time 0.9 seconds
Started Jun 04 12:52:52 PM PDT 24
Finished Jun 04 12:52:54 PM PDT 24
Peak memory 204560 kb
Host smart-911a1ced-a347-447c-8592-785c766effd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590691574 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.3590691574
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.3885744922
Short name T234
Test name
Test status
Simulation time 3330948508 ps
CPU time 9.6 seconds
Started Jun 04 12:52:39 PM PDT 24
Finished Jun 04 12:52:50 PM PDT 24
Peak memory 205164 kb
Host smart-2e854499-01b7-4a2b-8584-7a68eea95826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885744922 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.3885744922
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.2690794135
Short name T4
Test name
Test status
Simulation time 1076626312 ps
CPU time 1.9 seconds
Started Jun 04 12:52:42 PM PDT 24
Finished Jun 04 12:52:45 PM PDT 24
Peak memory 229156 kb
Host smart-b6cea2cd-50bc-4ba5-b424-cdad1abd5ca8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690794135 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.2690794135
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.1062836611
Short name T164
Test name
Test status
Simulation time 55052667 ps
CPU time 0.72 seconds
Started Jun 04 12:53:06 PM PDT 24
Finished Jun 04 12:53:08 PM PDT 24
Peak memory 204800 kb
Host smart-b277960f-1684-4676-a927-afcb8bb3e1a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062836611 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.1062836611
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.1453743212
Short name T250
Test name
Test status
Simulation time 63570487 ps
CPU time 0.75 seconds
Started Jun 04 12:53:13 PM PDT 24
Finished Jun 04 12:53:14 PM PDT 24
Peak memory 204756 kb
Host smart-bf7ef724-e878-4c66-bc76-67b03e4c68dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453743212 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.1453743212
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.1814498240
Short name T240
Test name
Test status
Simulation time 123708512 ps
CPU time 0.78 seconds
Started Jun 04 12:53:07 PM PDT 24
Finished Jun 04 12:53:09 PM PDT 24
Peak memory 204784 kb
Host smart-efc2ebe7-3c7b-4458-ba84-6ae2c593c3dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814498240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.1814498240
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_stress_all.1620409395
Short name T23
Test name
Test status
Simulation time 9865901804 ps
CPU time 14.86 seconds
Started Jun 04 12:53:09 PM PDT 24
Finished Jun 04 12:53:24 PM PDT 24
Peak memory 205048 kb
Host smart-53012807-ac56-4af0-8a76-a505e771b0e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620409395 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.1620409395
Directory /workspace/32.rv_dm_stress_all/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.2213123622
Short name T50
Test name
Test status
Simulation time 42908781 ps
CPU time 0.72 seconds
Started Jun 04 12:53:05 PM PDT 24
Finished Jun 04 12:53:07 PM PDT 24
Peak memory 204768 kb
Host smart-8da3eb71-16f4-4b9b-9c9b-ad9f7186aa8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213123622 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.2213123622
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_stress_all.3351078857
Short name T22
Test name
Test status
Simulation time 16745309058 ps
CPU time 25.64 seconds
Started Jun 04 12:53:05 PM PDT 24
Finished Jun 04 12:53:32 PM PDT 24
Peak memory 204960 kb
Host smart-8db7735b-48aa-4d27-8c53-00129abd0b0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351078857 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.3351078857
Directory /workspace/33.rv_dm_stress_all/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.2602270547
Short name T143
Test name
Test status
Simulation time 87295456 ps
CPU time 0.7 seconds
Started Jun 04 12:53:10 PM PDT 24
Finished Jun 04 12:53:12 PM PDT 24
Peak memory 204744 kb
Host smart-f2610d18-0cc5-4a0a-80f4-a1187d45be79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602270547 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.2602270547
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_stress_all.858871644
Short name T229
Test name
Test status
Simulation time 20651305476 ps
CPU time 12.04 seconds
Started Jun 04 12:53:12 PM PDT 24
Finished Jun 04 12:53:24 PM PDT 24
Peak memory 204960 kb
Host smart-47fb5d29-e6c3-483d-a89d-202cca38c9b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858871644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.858871644
Directory /workspace/34.rv_dm_stress_all/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.3622269327
Short name T156
Test name
Test status
Simulation time 79528979 ps
CPU time 0.71 seconds
Started Jun 04 12:53:15 PM PDT 24
Finished Jun 04 12:53:16 PM PDT 24
Peak memory 204736 kb
Host smart-cfa83633-d057-4ba5-97c9-a5559b9edf75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622269327 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.3622269327
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_stress_all.139680713
Short name T190
Test name
Test status
Simulation time 5550307023 ps
CPU time 12.66 seconds
Started Jun 04 12:53:05 PM PDT 24
Finished Jun 04 12:53:18 PM PDT 24
Peak memory 204984 kb
Host smart-27a6a512-4f95-4287-a53e-696f27b57e8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139680713 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.139680713
Directory /workspace/35.rv_dm_stress_all/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.2126957565
Short name T170
Test name
Test status
Simulation time 98596571 ps
CPU time 0.88 seconds
Started Jun 04 12:53:20 PM PDT 24
Finished Jun 04 12:53:22 PM PDT 24
Peak memory 204848 kb
Host smart-d3d5b940-5d58-496d-8835-355bbab1d4ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126957565 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.2126957565
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.1575697598
Short name T162
Test name
Test status
Simulation time 163810746 ps
CPU time 0.83 seconds
Started Jun 04 12:53:17 PM PDT 24
Finished Jun 04 12:53:18 PM PDT 24
Peak memory 204820 kb
Host smart-6f62e9ee-be5d-4aac-b04e-20e48399cfdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575697598 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.1575697598
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.2846527842
Short name T27
Test name
Test status
Simulation time 135887597 ps
CPU time 0.87 seconds
Started Jun 04 12:53:15 PM PDT 24
Finished Jun 04 12:53:17 PM PDT 24
Peak memory 204812 kb
Host smart-701bf0cd-e3dd-42e0-a3d4-4e84535a84c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846527842 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.2846527842
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.347747077
Short name T160
Test name
Test status
Simulation time 85289789 ps
CPU time 0.89 seconds
Started Jun 04 12:53:12 PM PDT 24
Finished Jun 04 12:53:13 PM PDT 24
Peak memory 204844 kb
Host smart-cc58258c-274b-4541-a5ae-3554dc16dd73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347747077 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.347747077
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.676511348
Short name T155
Test name
Test status
Simulation time 86465995 ps
CPU time 0.73 seconds
Started Jun 04 12:52:48 PM PDT 24
Finished Jun 04 12:52:50 PM PDT 24
Peak memory 204748 kb
Host smart-89bcc93b-3af8-41c4-b884-9c7db4aaf90d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676511348 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.676511348
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.3813963873
Short name T231
Test name
Test status
Simulation time 8905403665 ps
CPU time 4.08 seconds
Started Jun 04 12:52:54 PM PDT 24
Finished Jun 04 12:53:00 PM PDT 24
Peak memory 205176 kb
Host smart-4fa5254d-e860-472c-a682-daaddb32b615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813963873 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.3813963873
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.1561466140
Short name T178
Test name
Test status
Simulation time 1718785100 ps
CPU time 1.56 seconds
Started Jun 04 12:53:58 PM PDT 24
Finished Jun 04 12:54:00 PM PDT 24
Peak memory 203884 kb
Host smart-7eddd175-4dea-4032-93d3-b09bccf0051a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561466140 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.1561466140
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.1518356117
Short name T261
Test name
Test status
Simulation time 1473938409 ps
CPU time 4.95 seconds
Started Jun 04 12:52:48 PM PDT 24
Finished Jun 04 12:52:54 PM PDT 24
Peak memory 205064 kb
Host smart-390f7176-c4a3-4688-825d-936479d2309e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1518356117 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.1518356117
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.2770340846
Short name T224
Test name
Test status
Simulation time 336588443 ps
CPU time 1.67 seconds
Started Jun 04 12:53:58 PM PDT 24
Finished Jun 04 12:54:00 PM PDT 24
Peak memory 202412 kb
Host smart-e7777dd2-78a4-4009-9e01-6054e94f273d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770340846 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.2770340846
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.2730417927
Short name T207
Test name
Test status
Simulation time 2370999739 ps
CPU time 2.86 seconds
Started Jun 04 12:52:46 PM PDT 24
Finished Jun 04 12:52:50 PM PDT 24
Peak memory 205180 kb
Host smart-893fcf1f-42ac-4fb9-b268-0d2b4f35a135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730417927 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.2730417927
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.2495319059
Short name T154
Test name
Test status
Simulation time 35501251 ps
CPU time 0.72 seconds
Started Jun 04 12:53:12 PM PDT 24
Finished Jun 04 12:53:13 PM PDT 24
Peak memory 204748 kb
Host smart-d1198cc4-a8e3-499d-9d96-9cb3cc1f70e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495319059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.2495319059
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/40.rv_dm_stress_all.570063845
Short name T109
Test name
Test status
Simulation time 11498649383 ps
CPU time 16.26 seconds
Started Jun 04 12:53:18 PM PDT 24
Finished Jun 04 12:53:36 PM PDT 24
Peak memory 205044 kb
Host smart-022483b4-eea5-4bd3-b851-a9a72e44c5e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570063845 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.570063845
Directory /workspace/40.rv_dm_stress_all/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.3598310128
Short name T211
Test name
Test status
Simulation time 58126650 ps
CPU time 0.75 seconds
Started Jun 04 12:53:19 PM PDT 24
Finished Jun 04 12:53:21 PM PDT 24
Peak memory 204816 kb
Host smart-d7132f35-f7b0-4744-a5c1-a87e46b63660
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598310128 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.3598310128
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.3955528698
Short name T149
Test name
Test status
Simulation time 65696677 ps
CPU time 0.74 seconds
Started Jun 04 12:53:24 PM PDT 24
Finished Jun 04 12:53:25 PM PDT 24
Peak memory 204748 kb
Host smart-f5acf88a-8fda-4bbd-8eca-fb464da348ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955528698 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.3955528698
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.3620969714
Short name T153
Test name
Test status
Simulation time 74575950 ps
CPU time 0.65 seconds
Started Jun 04 12:53:20 PM PDT 24
Finished Jun 04 12:53:22 PM PDT 24
Peak memory 204704 kb
Host smart-a8a4adef-d6d3-42e5-b54c-09dbebfe732c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620969714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.3620969714
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.2315457388
Short name T171
Test name
Test status
Simulation time 110444404 ps
CPU time 0.74 seconds
Started Jun 04 12:53:26 PM PDT 24
Finished Jun 04 12:53:27 PM PDT 24
Peak memory 204848 kb
Host smart-9067d5f4-70a1-401f-8318-323026d51d86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315457388 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.2315457388
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.2829462223
Short name T152
Test name
Test status
Simulation time 63851814 ps
CPU time 0.75 seconds
Started Jun 04 12:53:21 PM PDT 24
Finished Jun 04 12:53:22 PM PDT 24
Peak memory 204836 kb
Host smart-12943704-18b7-4e32-ad88-774a8a05c81d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829462223 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.2829462223
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.1703196695
Short name T165
Test name
Test status
Simulation time 93386495 ps
CPU time 0.74 seconds
Started Jun 04 12:53:21 PM PDT 24
Finished Jun 04 12:53:22 PM PDT 24
Peak memory 204800 kb
Host smart-1e2c8fd5-19c2-4425-bc6b-af37a8d9653c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703196695 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.1703196695
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_stress_all.2089133360
Short name T41
Test name
Test status
Simulation time 32318120293 ps
CPU time 25.03 seconds
Started Jun 04 12:53:21 PM PDT 24
Finished Jun 04 12:53:47 PM PDT 24
Peak memory 213228 kb
Host smart-50a3cf0a-9e50-4908-84e8-77ccc28e4d91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089133360 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.2089133360
Directory /workspace/46.rv_dm_stress_all/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.1415964097
Short name T255
Test name
Test status
Simulation time 94158616 ps
CPU time 0.75 seconds
Started Jun 04 12:53:20 PM PDT 24
Finished Jun 04 12:53:21 PM PDT 24
Peak memory 204828 kb
Host smart-02c23b2c-004e-4af7-821e-4f438f864448
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415964097 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.1415964097
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.2572862328
Short name T148
Test name
Test status
Simulation time 27669383 ps
CPU time 0.76 seconds
Started Jun 04 12:53:23 PM PDT 24
Finished Jun 04 12:53:25 PM PDT 24
Peak memory 204756 kb
Host smart-0512bd76-f035-44a7-bf9c-801af0eee055
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572862328 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.2572862328
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_stress_all.997352243
Short name T133
Test name
Test status
Simulation time 26287525258 ps
CPU time 54.3 seconds
Started Jun 04 12:53:22 PM PDT 24
Finished Jun 04 12:54:17 PM PDT 24
Peak memory 204892 kb
Host smart-16041a92-17ab-4dbb-9081-9d799d4fd45d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997352243 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.997352243
Directory /workspace/48.rv_dm_stress_all/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.2803799948
Short name T64
Test name
Test status
Simulation time 119759918 ps
CPU time 1.03 seconds
Started Jun 04 12:53:27 PM PDT 24
Finished Jun 04 12:53:29 PM PDT 24
Peak memory 204764 kb
Host smart-4d9adad2-9594-4f43-a829-b3f1402e219d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803799948 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.2803799948
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.3386178942
Short name T167
Test name
Test status
Simulation time 42017675 ps
CPU time 0.73 seconds
Started Jun 04 12:52:56 PM PDT 24
Finished Jun 04 12:52:58 PM PDT 24
Peak memory 204832 kb
Host smart-939dd285-222c-45f7-8c80-c0587bfa159f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386178942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.3386178942
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.2938530205
Short name T182
Test name
Test status
Simulation time 39457787366 ps
CPU time 20.22 seconds
Started Jun 04 12:53:59 PM PDT 24
Finished Jun 04 12:54:20 PM PDT 24
Peak memory 212988 kb
Host smart-312359f8-b847-430a-bd86-e6ed3ae1c124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938530205 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.2938530205
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.386809321
Short name T264
Test name
Test status
Simulation time 5641944751 ps
CPU time 2.67 seconds
Started Jun 04 12:53:58 PM PDT 24
Finished Jun 04 12:54:01 PM PDT 24
Peak memory 204212 kb
Host smart-bbbc95fd-24ab-4cc8-a159-6d91155de36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386809321 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.386809321
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.1702543255
Short name T212
Test name
Test status
Simulation time 7998795897 ps
CPU time 7.5 seconds
Started Jun 04 12:52:48 PM PDT 24
Finished Jun 04 12:52:57 PM PDT 24
Peak memory 205192 kb
Host smart-2ccd490f-d394-45ef-bf85-872a1e8012e1
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1702543255 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t
l_access.1702543255
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_stress_all.2308390758
Short name T210
Test name
Test status
Simulation time 4469084089 ps
CPU time 12.62 seconds
Started Jun 04 12:53:58 PM PDT 24
Finished Jun 04 12:54:11 PM PDT 24
Peak memory 203716 kb
Host smart-6566871e-848c-4f74-9e36-97ea81292883
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308390758 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.2308390758
Directory /workspace/5.rv_dm_stress_all/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.827202702
Short name T246
Test name
Test status
Simulation time 7583995808 ps
CPU time 6.78 seconds
Started Jun 04 12:54:14 PM PDT 24
Finished Jun 04 12:54:22 PM PDT 24
Peak memory 205024 kb
Host smart-ca14d3e7-436d-4b38-b382-c2b2f551b28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827202702 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.827202702
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.1917639441
Short name T82
Test name
Test status
Simulation time 5495841032 ps
CPU time 5 seconds
Started Jun 04 12:52:56 PM PDT 24
Finished Jun 04 12:53:02 PM PDT 24
Peak memory 205348 kb
Host smart-fe1fa07a-d5d2-4494-b7a9-8940018cbd37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917639441 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.1917639441
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.2955801970
Short name T230
Test name
Test status
Simulation time 2544916335 ps
CPU time 4.77 seconds
Started Jun 04 12:52:48 PM PDT 24
Finished Jun 04 12:52:55 PM PDT 24
Peak memory 205236 kb
Host smart-02133d37-6405-493f-ade0-88b6b0d1f97e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2955801970 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t
l_access.2955801970
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.812948485
Short name T254
Test name
Test status
Simulation time 9313001408 ps
CPU time 7.53 seconds
Started Jun 04 12:52:48 PM PDT 24
Finished Jun 04 12:52:57 PM PDT 24
Peak memory 205096 kb
Host smart-093639ab-64eb-4549-8490-91089ee8f333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812948485 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.812948485
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_stress_all.2852967594
Short name T37
Test name
Test status
Simulation time 18068057501 ps
CPU time 47.8 seconds
Started Jun 04 12:52:53 PM PDT 24
Finished Jun 04 12:53:42 PM PDT 24
Peak memory 213144 kb
Host smart-c9c15655-5dfd-42dc-9ac9-7be69ca0f115
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852967594 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.2852967594
Directory /workspace/6.rv_dm_stress_all/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.1178409056
Short name T161
Test name
Test status
Simulation time 109578317 ps
CPU time 0.86 seconds
Started Jun 04 12:52:41 PM PDT 24
Finished Jun 04 12:52:43 PM PDT 24
Peak memory 204800 kb
Host smart-574f5e70-88b9-4d07-9e14-70b2554679b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178409056 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.1178409056
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.939350550
Short name T244
Test name
Test status
Simulation time 3198050403 ps
CPU time 8.25 seconds
Started Jun 04 12:52:47 PM PDT 24
Finished Jun 04 12:52:57 PM PDT 24
Peak memory 205252 kb
Host smart-b52558d7-a464-4982-8cee-170a00ca3dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939350550 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.939350550
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.3283776352
Short name T263
Test name
Test status
Simulation time 3874204343 ps
CPU time 10.48 seconds
Started Jun 04 12:52:43 PM PDT 24
Finished Jun 04 12:52:54 PM PDT 24
Peak memory 205164 kb
Host smart-ef7f0d0f-f7a9-4829-b760-32c1bb2b819b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283776352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.3283776352
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.1581435641
Short name T213
Test name
Test status
Simulation time 1651075754 ps
CPU time 5.42 seconds
Started Jun 04 12:52:48 PM PDT 24
Finished Jun 04 12:52:55 PM PDT 24
Peak memory 205112 kb
Host smart-44af18c5-8602-4b2b-a22e-58a92322bccc
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1581435641 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.1581435641
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.617794406
Short name T189
Test name
Test status
Simulation time 1262611671 ps
CPU time 1.81 seconds
Started Jun 04 12:52:42 PM PDT 24
Finished Jun 04 12:52:45 PM PDT 24
Peak memory 205068 kb
Host smart-94c51854-8876-4a4b-9107-0b601150c10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617794406 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.617794406
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.284694643
Short name T159
Test name
Test status
Simulation time 72678396 ps
CPU time 0.85 seconds
Started Jun 04 12:52:48 PM PDT 24
Finished Jun 04 12:52:50 PM PDT 24
Peak memory 204752 kb
Host smart-e44a4fed-36df-45b8-9fef-deafd0e17abc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284694643 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.284694643
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.670985382
Short name T21
Test name
Test status
Simulation time 5808057459 ps
CPU time 9.14 seconds
Started Jun 04 12:52:41 PM PDT 24
Finished Jun 04 12:52:51 PM PDT 24
Peak memory 213364 kb
Host smart-02221643-7ec1-4f81-b86c-267036914ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670985382 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.670985382
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.1210418083
Short name T199
Test name
Test status
Simulation time 5646882626 ps
CPU time 12.48 seconds
Started Jun 04 12:53:46 PM PDT 24
Finished Jun 04 12:54:00 PM PDT 24
Peak memory 204012 kb
Host smart-7fe0dc6e-7322-447f-974c-7ead6a6b189d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210418083 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.1210418083
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.2215233837
Short name T193
Test name
Test status
Simulation time 2451510924 ps
CPU time 2.13 seconds
Started Jun 04 12:53:46 PM PDT 24
Finished Jun 04 12:53:49 PM PDT 24
Peak memory 203828 kb
Host smart-600123a2-d2bc-429f-94b2-ee02592bcca7
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2215233837 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t
l_access.2215233837
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.3911608134
Short name T239
Test name
Test status
Simulation time 3258159393 ps
CPU time 5.85 seconds
Started Jun 04 12:54:00 PM PDT 24
Finished Jun 04 12:54:07 PM PDT 24
Peak memory 205036 kb
Host smart-588212bd-64e7-49d8-b0f9-31b37783822d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911608134 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.3911608134
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.2314490344
Short name T157
Test name
Test status
Simulation time 42408715 ps
CPU time 0.71 seconds
Started Jun 04 12:52:48 PM PDT 24
Finished Jun 04 12:52:50 PM PDT 24
Peak memory 204712 kb
Host smart-b55c9152-efb0-4102-aa42-a22945318f40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314490344 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.2314490344
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.4225119827
Short name T185
Test name
Test status
Simulation time 9296491498 ps
CPU time 17.54 seconds
Started Jun 04 12:52:56 PM PDT 24
Finished Jun 04 12:53:14 PM PDT 24
Peak memory 213320 kb
Host smart-0e11b60c-ab76-4d20-b066-d59112a0a2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225119827 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.4225119827
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.2604474122
Short name T203
Test name
Test status
Simulation time 6000092524 ps
CPU time 8.77 seconds
Started Jun 04 12:53:02 PM PDT 24
Finished Jun 04 12:53:13 PM PDT 24
Peak memory 205172 kb
Host smart-1687925e-79cc-440e-a8a5-34931d5eb3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604474122 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.2604474122
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.3016728267
Short name T81
Test name
Test status
Simulation time 2688015516 ps
CPU time 8.66 seconds
Started Jun 04 12:52:49 PM PDT 24
Finished Jun 04 12:53:00 PM PDT 24
Peak memory 205236 kb
Host smart-1d3c1e67-da15-4666-ab58-8d72498d439f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3016728267 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t
l_access.3016728267
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.3342762976
Short name T253
Test name
Test status
Simulation time 3602709619 ps
CPU time 3.9 seconds
Started Jun 04 12:52:51 PM PDT 24
Finished Jun 04 12:52:56 PM PDT 24
Peak memory 205196 kb
Host smart-547a196b-d3e6-45c5-be89-8f2abdabdf77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342762976 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.3342762976
Directory /workspace/9.rv_dm_sba_tl_access/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%