SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
77.52 | 94.56 | 78.98 | 86.17 | 70.51 | 84.50 | 98.52 | 29.36 |
T283 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1648202866 | Jun 05 05:39:16 PM PDT 24 | Jun 05 05:39:51 PM PDT 24 | 11965350574 ps | ||
T99 | /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.4181372437 | Jun 05 05:39:40 PM PDT 24 | Jun 05 05:39:49 PM PDT 24 | 637101926 ps | ||
T284 | /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.2938663234 | Jun 05 05:39:41 PM PDT 24 | Jun 05 05:39:43 PM PDT 24 | 487758479 ps | ||
T107 | /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.1900827545 | Jun 05 05:39:55 PM PDT 24 | Jun 05 05:39:57 PM PDT 24 | 90997028 ps | ||
T285 | /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1749629125 | Jun 05 05:39:45 PM PDT 24 | Jun 05 05:39:54 PM PDT 24 | 1979730483 ps | ||
T286 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.4180044523 | Jun 05 05:39:26 PM PDT 24 | Jun 05 05:39:32 PM PDT 24 | 2933731157 ps | ||
T123 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.816431663 | Jun 05 05:39:25 PM PDT 24 | Jun 05 05:39:31 PM PDT 24 | 3514279253 ps | ||
T108 | /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.3783537125 | Jun 05 05:39:48 PM PDT 24 | Jun 05 05:39:51 PM PDT 24 | 381853477 ps | ||
T109 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.3066166862 | Jun 05 05:39:29 PM PDT 24 | Jun 05 05:40:24 PM PDT 24 | 3310948446 ps | ||
T124 | /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.845942620 | Jun 05 05:39:29 PM PDT 24 | Jun 05 05:39:32 PM PDT 24 | 165078596 ps | ||
T134 | /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.866899067 | Jun 05 05:39:29 PM PDT 24 | Jun 05 05:39:39 PM PDT 24 | 1159578981 ps | ||
T287 | /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1465622497 | Jun 05 05:39:42 PM PDT 24 | Jun 05 05:39:45 PM PDT 24 | 142460874 ps | ||
T92 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2261972222 | Jun 05 05:39:25 PM PDT 24 | Jun 05 05:39:41 PM PDT 24 | 4910302020 ps | ||
T129 | /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.4049262050 | Jun 05 05:39:41 PM PDT 24 | Jun 05 05:39:52 PM PDT 24 | 1959596313 ps | ||
T288 | /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.2570373495 | Jun 05 05:39:47 PM PDT 24 | Jun 05 05:39:53 PM PDT 24 | 229179918 ps | ||
T100 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.489163540 | Jun 05 05:39:24 PM PDT 24 | Jun 05 05:39:27 PM PDT 24 | 273600518 ps | ||
T131 | /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3546585659 | Jun 05 05:39:40 PM PDT 24 | Jun 05 05:40:15 PM PDT 24 | 6428985065 ps | ||
T289 | /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1098996388 | Jun 05 05:39:30 PM PDT 24 | Jun 05 05:39:31 PM PDT 24 | 38475232 ps | ||
T290 | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.1492173002 | Jun 05 05:39:37 PM PDT 24 | Jun 05 05:43:24 PM PDT 24 | 90812472815 ps | ||
T291 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1697469815 | Jun 05 05:39:11 PM PDT 24 | Jun 05 05:39:22 PM PDT 24 | 11580345111 ps | ||
T46 | /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.4008329959 | Jun 05 05:39:32 PM PDT 24 | Jun 05 05:40:31 PM PDT 24 | 34820267162 ps | ||
T130 | /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.2910922021 | Jun 05 05:39:30 PM PDT 24 | Jun 05 05:39:55 PM PDT 24 | 6645471852 ps | ||
T292 | /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.686013156 | Jun 05 05:39:39 PM PDT 24 | Jun 05 05:39:43 PM PDT 24 | 234307449 ps | ||
T293 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.3616473835 | Jun 05 05:39:14 PM PDT 24 | Jun 05 05:39:22 PM PDT 24 | 8296130053 ps | ||
T294 | /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.3849173218 | Jun 05 05:39:19 PM PDT 24 | Jun 05 05:39:20 PM PDT 24 | 162811649 ps | ||
T295 | /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.3507674905 | Jun 05 05:39:31 PM PDT 24 | Jun 05 05:39:39 PM PDT 24 | 1716718819 ps | ||
T296 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3282303208 | Jun 05 05:39:16 PM PDT 24 | Jun 05 05:39:22 PM PDT 24 | 1212265913 ps | ||
T101 | /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.507737906 | Jun 05 05:39:39 PM PDT 24 | Jun 05 05:39:44 PM PDT 24 | 413803131 ps | ||
T297 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.2705409044 | Jun 05 05:39:07 PM PDT 24 | Jun 05 05:39:12 PM PDT 24 | 1452575749 ps | ||
T298 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1747104930 | Jun 05 05:39:29 PM PDT 24 | Jun 05 05:39:41 PM PDT 24 | 15813887844 ps | ||
T102 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2664802041 | Jun 05 05:39:17 PM PDT 24 | Jun 05 05:39:19 PM PDT 24 | 265211357 ps | ||
T111 | /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.1628612304 | Jun 05 05:39:47 PM PDT 24 | Jun 05 05:39:50 PM PDT 24 | 145104205 ps | ||
T299 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1700081955 | Jun 05 05:39:09 PM PDT 24 | Jun 05 05:39:22 PM PDT 24 | 15628849213 ps | ||
T132 | /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.4273749770 | Jun 05 05:39:29 PM PDT 24 | Jun 05 05:39:41 PM PDT 24 | 4486297729 ps | ||
T300 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3321626533 | Jun 05 05:39:27 PM PDT 24 | Jun 05 05:39:29 PM PDT 24 | 238632950 ps | ||
T301 | /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.3037124044 | Jun 05 05:39:21 PM PDT 24 | Jun 05 05:39:23 PM PDT 24 | 85735590 ps | ||
T302 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3663693144 | Jun 05 05:39:16 PM PDT 24 | Jun 05 05:39:23 PM PDT 24 | 12231589739 ps | ||
T303 | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.4291350486 | Jun 05 05:39:32 PM PDT 24 | Jun 05 05:39:34 PM PDT 24 | 456472261 ps | ||
T47 | /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.1069456906 | Jun 05 05:39:22 PM PDT 24 | Jun 05 05:40:11 PM PDT 24 | 81658130025 ps | ||
T304 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1961429026 | Jun 05 05:39:14 PM PDT 24 | Jun 05 05:39:54 PM PDT 24 | 14583267789 ps | ||
T305 | /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.105476833 | Jun 05 05:39:11 PM PDT 24 | Jun 05 05:39:22 PM PDT 24 | 1201141180 ps | ||
T93 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2095738656 | Jun 05 05:39:14 PM PDT 24 | Jun 05 05:39:24 PM PDT 24 | 5491333047 ps | ||
T112 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.3059471437 | Jun 05 05:39:09 PM PDT 24 | Jun 05 05:40:05 PM PDT 24 | 1423588096 ps | ||
T306 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3840072098 | Jun 05 05:39:11 PM PDT 24 | Jun 05 05:39:13 PM PDT 24 | 295997878 ps | ||
T125 | /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.370800076 | Jun 05 05:39:54 PM PDT 24 | Jun 05 05:40:04 PM PDT 24 | 2437674825 ps | ||
T307 | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2529352170 | Jun 05 05:39:39 PM PDT 24 | Jun 05 05:39:43 PM PDT 24 | 1038177247 ps | ||
T308 | /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.3077788094 | Jun 05 05:39:55 PM PDT 24 | Jun 05 05:39:58 PM PDT 24 | 186922045 ps | ||
T126 | /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2537127797 | Jun 05 05:39:25 PM PDT 24 | Jun 05 05:39:43 PM PDT 24 | 2152746013 ps | ||
T309 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.468298509 | Jun 05 05:39:18 PM PDT 24 | Jun 05 05:42:53 PM PDT 24 | 69116722803 ps | ||
T310 | /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.4173509813 | Jun 05 05:39:47 PM PDT 24 | Jun 05 05:39:50 PM PDT 24 | 781781811 ps | ||
T311 | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.348814223 | Jun 05 05:39:32 PM PDT 24 | Jun 05 05:40:08 PM PDT 24 | 11808510179 ps | ||
T133 | /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.837565068 | Jun 05 05:39:55 PM PDT 24 | Jun 05 05:40:16 PM PDT 24 | 2837896399 ps | ||
T94 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.1063019106 | Jun 05 05:39:25 PM PDT 24 | Jun 05 05:39:35 PM PDT 24 | 10418906153 ps | ||
T103 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.2595829471 | Jun 05 05:39:11 PM PDT 24 | Jun 05 05:39:15 PM PDT 24 | 296000080 ps | ||
T312 | /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.2380274458 | Jun 05 05:39:48 PM PDT 24 | Jun 05 05:39:51 PM PDT 24 | 224646619 ps | ||
T313 | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.2372784033 | Jun 05 05:39:40 PM PDT 24 | Jun 05 05:39:42 PM PDT 24 | 211711421 ps | ||
T314 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.3858031452 | Jun 05 05:39:17 PM PDT 24 | Jun 05 05:39:20 PM PDT 24 | 1113350652 ps | ||
T104 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2732757944 | Jun 05 05:39:21 PM PDT 24 | Jun 05 05:40:24 PM PDT 24 | 1143309237 ps | ||
T135 | /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.2908255825 | Jun 05 05:39:31 PM PDT 24 | Jun 05 05:40:32 PM PDT 24 | 19523627232 ps | ||
T315 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.1676618635 | Jun 05 05:39:23 PM PDT 24 | Jun 05 05:39:35 PM PDT 24 | 6091179599 ps | ||
T127 | /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2016539242 | Jun 05 05:39:38 PM PDT 24 | Jun 05 05:39:50 PM PDT 24 | 2573293286 ps | ||
T316 | /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.892586218 | Jun 05 05:39:55 PM PDT 24 | Jun 05 05:40:01 PM PDT 24 | 604602470 ps | ||
T317 | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.1057271617 | Jun 05 05:39:31 PM PDT 24 | Jun 05 05:39:33 PM PDT 24 | 363785794 ps | ||
T318 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.4136538108 | Jun 05 05:39:17 PM PDT 24 | Jun 05 05:39:21 PM PDT 24 | 2912544852 ps | ||
T319 | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.1732284706 | Jun 05 05:39:40 PM PDT 24 | Jun 05 05:39:43 PM PDT 24 | 638485561 ps | ||
T320 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2055626883 | Jun 05 05:39:14 PM PDT 24 | Jun 05 05:39:17 PM PDT 24 | 187229191 ps | ||
T321 | /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.4157165285 | Jun 05 05:39:40 PM PDT 24 | Jun 05 05:39:44 PM PDT 24 | 479651935 ps | ||
T322 | /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.452165151 | Jun 05 05:39:31 PM PDT 24 | Jun 05 05:40:22 PM PDT 24 | 63078231665 ps | ||
T323 | /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.1188547963 | Jun 05 05:39:48 PM PDT 24 | Jun 05 05:39:55 PM PDT 24 | 2334411999 ps | ||
T324 | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2092254778 | Jun 05 05:39:49 PM PDT 24 | Jun 05 05:39:50 PM PDT 24 | 249600361 ps | ||
T325 | /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.2247557780 | Jun 05 05:39:48 PM PDT 24 | Jun 05 05:39:53 PM PDT 24 | 427538552 ps | ||
T110 | /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.2113579108 | Jun 05 05:39:30 PM PDT 24 | Jun 05 05:39:32 PM PDT 24 | 37872735 ps | ||
T326 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.166710354 | Jun 05 05:39:24 PM PDT 24 | Jun 05 05:39:36 PM PDT 24 | 8165928003 ps | ||
T327 | /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.2853386853 | Jun 05 05:39:56 PM PDT 24 | Jun 05 05:40:01 PM PDT 24 | 476371232 ps | ||
T328 | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2906633583 | Jun 05 05:39:30 PM PDT 24 | Jun 05 05:40:07 PM PDT 24 | 12919218562 ps | ||
T329 | /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.2504463502 | Jun 05 05:39:08 PM PDT 24 | Jun 05 05:39:09 PM PDT 24 | 215937527 ps | ||
T330 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.1882723684 | Jun 05 05:39:30 PM PDT 24 | Jun 05 05:39:33 PM PDT 24 | 503878151 ps | ||
T331 | /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.3764643837 | Jun 05 05:39:40 PM PDT 24 | Jun 05 05:40:11 PM PDT 24 | 76067066560 ps | ||
T332 | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.3825527738 | Jun 05 05:39:57 PM PDT 24 | Jun 05 05:39:59 PM PDT 24 | 94373331 ps | ||
T333 | /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.2782396746 | Jun 05 05:39:21 PM PDT 24 | Jun 05 05:39:36 PM PDT 24 | 45947370627 ps | ||
T334 | /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2340101059 | Jun 05 05:39:11 PM PDT 24 | Jun 05 05:39:19 PM PDT 24 | 733326746 ps | ||
T335 | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.443058061 | Jun 05 05:39:29 PM PDT 24 | Jun 05 05:39:31 PM PDT 24 | 98574272 ps | ||
T336 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.1103334332 | Jun 05 05:39:23 PM PDT 24 | Jun 05 05:39:26 PM PDT 24 | 780418689 ps | ||
T337 | /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.937554446 | Jun 05 05:39:40 PM PDT 24 | Jun 05 05:39:44 PM PDT 24 | 352858447 ps | ||
T113 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.76794750 | Jun 05 05:39:13 PM PDT 24 | Jun 05 05:39:16 PM PDT 24 | 157615361 ps | ||
T338 | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3940158876 | Jun 05 05:39:39 PM PDT 24 | Jun 05 05:39:47 PM PDT 24 | 2380239590 ps | ||
T339 | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.1651570985 | Jun 05 05:39:53 PM PDT 24 | Jun 05 05:39:57 PM PDT 24 | 1729842726 ps | ||
T340 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.957609827 | Jun 05 05:39:15 PM PDT 24 | Jun 05 05:39:17 PM PDT 24 | 1230185241 ps | ||
T341 | /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.3528409994 | Jun 05 05:39:13 PM PDT 24 | Jun 05 05:40:29 PM PDT 24 | 49349480749 ps | ||
T342 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.4060187549 | Jun 05 05:39:22 PM PDT 24 | Jun 05 05:39:26 PM PDT 24 | 3362376831 ps | ||
T343 | /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.1847090474 | Jun 05 05:39:41 PM PDT 24 | Jun 05 05:39:49 PM PDT 24 | 478985199 ps | ||
T344 | /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.370845684 | Jun 05 05:39:54 PM PDT 24 | Jun 05 05:40:01 PM PDT 24 | 2072796518 ps | ||
T345 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.4091575400 | Jun 05 05:39:27 PM PDT 24 | Jun 05 05:39:43 PM PDT 24 | 5093992100 ps | ||
T114 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1619566221 | Jun 05 05:39:16 PM PDT 24 | Jun 05 05:39:19 PM PDT 24 | 205811631 ps | ||
T346 | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.146799469 | Jun 05 05:39:41 PM PDT 24 | Jun 05 05:39:47 PM PDT 24 | 6136987668 ps | ||
T347 | /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.283599977 | Jun 05 05:39:31 PM PDT 24 | Jun 05 05:40:48 PM PDT 24 | 82659061410 ps | ||
T348 | /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.64022824 | Jun 05 05:39:47 PM PDT 24 | Jun 05 05:39:53 PM PDT 24 | 4850360095 ps | ||
T349 | /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.2532200427 | Jun 05 05:39:49 PM PDT 24 | Jun 05 05:39:51 PM PDT 24 | 56505546 ps | ||
T350 | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.62121119 | Jun 05 05:39:37 PM PDT 24 | Jun 05 05:39:39 PM PDT 24 | 303923618 ps | ||
T351 | /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.1331296269 | Jun 05 05:39:25 PM PDT 24 | Jun 05 05:39:35 PM PDT 24 | 5741859208 ps | ||
T352 | /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2969059631 | Jun 05 05:39:33 PM PDT 24 | Jun 05 05:39:52 PM PDT 24 | 3726745758 ps | ||
T353 | /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.3285620499 | Jun 05 05:39:48 PM PDT 24 | Jun 05 05:39:51 PM PDT 24 | 83563500 ps | ||
T354 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.2583531249 | Jun 05 05:39:26 PM PDT 24 | Jun 05 05:39:54 PM PDT 24 | 2858454985 ps | ||
T355 | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.3200693302 | Jun 05 05:39:29 PM PDT 24 | Jun 05 05:40:21 PM PDT 24 | 36078094779 ps | ||
T356 | /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.3180820301 | Jun 05 05:39:25 PM PDT 24 | Jun 05 05:39:26 PM PDT 24 | 41112637 ps | ||
T357 | /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.244231825 | Jun 05 05:39:55 PM PDT 24 | Jun 05 05:40:01 PM PDT 24 | 214764304 ps | ||
T358 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2159902619 | Jun 05 05:39:15 PM PDT 24 | Jun 05 05:39:44 PM PDT 24 | 10151905269 ps | ||
T359 | /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1128236661 | Jun 05 05:39:11 PM PDT 24 | Jun 05 05:39:12 PM PDT 24 | 134794747 ps | ||
T360 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.3307635225 | Jun 05 05:39:32 PM PDT 24 | Jun 05 05:39:34 PM PDT 24 | 196071779 ps | ||
T361 | /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.2159769876 | Jun 05 05:39:30 PM PDT 24 | Jun 05 05:39:32 PM PDT 24 | 78865576 ps | ||
T362 | /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.4238781004 | Jun 05 05:39:53 PM PDT 24 | Jun 05 05:40:00 PM PDT 24 | 3992764497 ps | ||
T363 | /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2481922690 | Jun 05 05:39:27 PM PDT 24 | Jun 05 05:39:33 PM PDT 24 | 2707269493 ps | ||
T364 | /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2407977006 | Jun 05 05:39:29 PM PDT 24 | Jun 05 05:39:32 PM PDT 24 | 131694790 ps | ||
T365 | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.15400953 | Jun 05 05:39:53 PM PDT 24 | Jun 05 05:40:01 PM PDT 24 | 8494168168 ps | ||
T366 | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3046184402 | Jun 05 05:39:49 PM PDT 24 | Jun 05 05:40:00 PM PDT 24 | 3789679246 ps | ||
T367 | /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.3345147609 | Jun 05 05:39:51 PM PDT 24 | Jun 05 05:39:57 PM PDT 24 | 101210929 ps | ||
T368 | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.3528977397 | Jun 05 05:39:37 PM PDT 24 | Jun 05 05:39:44 PM PDT 24 | 5001272529 ps | ||
T369 | /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.680000354 | Jun 05 05:39:39 PM PDT 24 | Jun 05 05:39:41 PM PDT 24 | 482072662 ps | ||
T370 | /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.802872405 | Jun 05 05:39:30 PM PDT 24 | Jun 05 05:39:34 PM PDT 24 | 156337717 ps | ||
T371 | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.4191231445 | Jun 05 05:39:51 PM PDT 24 | Jun 05 05:40:00 PM PDT 24 | 3001620136 ps | ||
T372 | /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.612086341 | Jun 05 05:39:40 PM PDT 24 | Jun 05 05:39:46 PM PDT 24 | 152862387 ps | ||
T373 | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.1073276545 | Jun 05 05:39:56 PM PDT 24 | Jun 05 05:39:58 PM PDT 24 | 453652039 ps | ||
T374 | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.660470390 | Jun 05 05:39:48 PM PDT 24 | Jun 05 05:39:54 PM PDT 24 | 5200972917 ps | ||
T375 | /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.4194863292 | Jun 05 05:39:15 PM PDT 24 | Jun 05 05:39:26 PM PDT 24 | 1201703630 ps | ||
T376 | /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.3053796212 | Jun 05 05:39:15 PM PDT 24 | Jun 05 05:39:17 PM PDT 24 | 133152452 ps | ||
T377 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.744769 | Jun 05 05:39:32 PM PDT 24 | Jun 05 05:39:37 PM PDT 24 | 2798186382 ps | ||
T378 | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.4173633123 | Jun 05 05:39:48 PM PDT 24 | Jun 05 05:39:54 PM PDT 24 | 7147337298 ps | ||
T379 | /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3713520 | Jun 05 05:39:14 PM PDT 24 | Jun 05 05:39:21 PM PDT 24 | 252834250 ps | ||
T380 | /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.564661362 | Jun 05 05:39:47 PM PDT 24 | Jun 05 05:39:54 PM PDT 24 | 1345674810 ps | ||
T381 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.101086853 | Jun 05 05:39:18 PM PDT 24 | Jun 05 05:39:43 PM PDT 24 | 15712375555 ps | ||
T382 | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.145586367 | Jun 05 05:39:49 PM PDT 24 | Jun 05 05:39:53 PM PDT 24 | 2807265238 ps | ||
T383 | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.501307091 | Jun 05 05:39:31 PM PDT 24 | Jun 05 05:39:54 PM PDT 24 | 8381094855 ps | ||
T384 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3097740360 | Jun 05 05:39:14 PM PDT 24 | Jun 05 05:39:25 PM PDT 24 | 3498063960 ps | ||
T128 | /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2800625882 | Jun 05 05:39:54 PM PDT 24 | Jun 05 05:40:16 PM PDT 24 | 7324451699 ps | ||
T385 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1255176647 | Jun 05 05:39:22 PM PDT 24 | Jun 05 05:39:26 PM PDT 24 | 856811470 ps | ||
T386 | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.2630685353 | Jun 05 05:39:57 PM PDT 24 | Jun 05 05:40:38 PM PDT 24 | 13137961585 ps | ||
T387 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.1791509311 | Jun 05 05:39:19 PM PDT 24 | Jun 05 05:40:45 PM PDT 24 | 29575187864 ps | ||
T388 | /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.2384328369 | Jun 05 05:39:40 PM PDT 24 | Jun 05 05:39:48 PM PDT 24 | 2071799366 ps | ||
T389 | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.2570358912 | Jun 05 05:39:32 PM PDT 24 | Jun 05 05:39:33 PM PDT 24 | 113584238 ps | ||
T390 | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.3369710092 | Jun 05 05:39:47 PM PDT 24 | Jun 05 05:40:34 PM PDT 24 | 15404932313 ps | ||
T391 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.4216087086 | Jun 05 05:39:25 PM PDT 24 | Jun 05 05:39:28 PM PDT 24 | 674630798 ps | ||
T392 | /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.2807018189 | Jun 05 05:39:49 PM PDT 24 | Jun 05 05:39:59 PM PDT 24 | 642995903 ps | ||
T393 | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.3672657703 | Jun 05 05:39:53 PM PDT 24 | Jun 05 05:41:11 PM PDT 24 | 59704705077 ps | ||
T394 | /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.3366484187 | Jun 05 05:39:40 PM PDT 24 | Jun 05 05:39:45 PM PDT 24 | 366715089 ps | ||
T395 | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2363571050 | Jun 05 05:39:57 PM PDT 24 | Jun 05 05:40:11 PM PDT 24 | 8446005036 ps | ||
T396 | /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1665939596 | Jun 05 05:39:51 PM PDT 24 | Jun 05 05:40:00 PM PDT 24 | 900743743 ps | ||
T397 | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.3275756568 | Jun 05 05:39:39 PM PDT 24 | Jun 05 05:40:47 PM PDT 24 | 24434888774 ps | ||
T398 | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.2145943570 | Jun 05 05:39:31 PM PDT 24 | Jun 05 05:40:14 PM PDT 24 | 64308330832 ps | ||
T399 | /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1690143363 | Jun 05 05:39:14 PM PDT 24 | Jun 05 05:39:15 PM PDT 24 | 168994643 ps | ||
T400 | /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.3264086222 | Jun 05 05:39:39 PM PDT 24 | Jun 05 05:40:04 PM PDT 24 | 3669820654 ps | ||
T401 | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.4084771240 | Jun 05 05:39:39 PM PDT 24 | Jun 05 05:39:49 PM PDT 24 | 11483809377 ps | ||
T402 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.3868449642 | Jun 05 05:39:25 PM PDT 24 | Jun 05 05:39:52 PM PDT 24 | 815389066 ps | ||
T403 | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3465862531 | Jun 05 05:39:49 PM PDT 24 | Jun 05 05:39:54 PM PDT 24 | 1202038268 ps | ||
T404 | /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.831563093 | Jun 05 05:39:28 PM PDT 24 | Jun 05 05:41:01 PM PDT 24 | 56102712679 ps | ||
T405 | /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.4053881198 | Jun 05 05:39:56 PM PDT 24 | Jun 05 05:40:04 PM PDT 24 | 857637822 ps | ||
T406 | /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.4153932493 | Jun 05 05:39:28 PM PDT 24 | Jun 05 05:39:34 PM PDT 24 | 326797133 ps | ||
T407 | /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.652531997 | Jun 05 05:39:13 PM PDT 24 | Jun 05 05:40:11 PM PDT 24 | 70856192258 ps | ||
T408 | /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3053255031 | Jun 05 05:39:32 PM PDT 24 | Jun 05 05:39:37 PM PDT 24 | 533644841 ps | ||
T409 | /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.1439837250 | Jun 05 05:39:38 PM PDT 24 | Jun 05 05:39:40 PM PDT 24 | 248925236 ps | ||
T410 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.4197413446 | Jun 05 05:39:09 PM PDT 24 | Jun 05 05:39:12 PM PDT 24 | 1068271585 ps | ||
T411 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1756705877 | Jun 05 05:39:12 PM PDT 24 | Jun 05 05:40:21 PM PDT 24 | 123356151726 ps | ||
T412 | /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.1273639322 | Jun 05 05:39:57 PM PDT 24 | Jun 05 05:40:00 PM PDT 24 | 376634494 ps |
Test location | /workspace/coverage/default/0.rv_dm_ndmreset_req.498831294 |
Short name | T2 |
Test name | |
Test status | |
Simulation time | 608878852 ps |
CPU time | 2.39 seconds |
Started | Jun 05 05:39:55 PM PDT 24 |
Finished | Jun 05 05:39:58 PM PDT 24 |
Peak memory | 204900 kb |
Host | smart-d7faa0a5-56c8-4994-b57c-e7dece2ba150 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=498831294 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.498831294 |
Directory | /workspace/0.rv_dm_ndmreset_req/latest |
Test location | /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.1920323865 |
Short name | T16 |
Test name | |
Test status | |
Simulation time | 17044213023 ps |
CPU time | 36.08 seconds |
Started | Jun 05 05:40:25 PM PDT 24 |
Finished | Jun 05 05:41:03 PM PDT 24 |
Peak memory | 213424 kb |
Host | smart-285f7278-1e18-4cf6-a730-514addedfcb4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1920323865 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.1920323865 |
Directory | /workspace/12.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/24.rv_dm_alert_test.4213662125 |
Short name | T22 |
Test name | |
Test status | |
Simulation time | 98910718 ps |
CPU time | 0.82 seconds |
Started | Jun 05 05:40:32 PM PDT 24 |
Finished | Jun 05 05:40:34 PM PDT 24 |
Peak memory | 204836 kb |
Host | smart-c19e31c6-a67e-4dda-884f-be07ce27cb96 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213662125 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.4213662125 |
Directory | /workspace/24.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/48.rv_dm_stress_all.1840362446 |
Short name | T9 |
Test name | |
Test status | |
Simulation time | 54572069165 ps |
CPU time | 36.56 seconds |
Started | Jun 05 05:40:43 PM PDT 24 |
Finished | Jun 05 05:41:21 PM PDT 24 |
Peak memory | 205100 kb |
Host | smart-4523999a-0b60-4480-b217-848cfc20829a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840362446 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.1840362446 |
Directory | /workspace/48.rv_dm_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.3661889857 |
Short name | T51 |
Test name | |
Test status | |
Simulation time | 4570650447 ps |
CPU time | 11.66 seconds |
Started | Jun 05 05:39:18 PM PDT 24 |
Finished | Jun 05 05:39:30 PM PDT 24 |
Peak memory | 213400 kb |
Host | smart-05edd199-fca9-4381-8a17-f63b6fd22bcd |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661889857 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.3661889857 |
Directory | /workspace/2.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.3225368389 |
Short name | T71 |
Test name | |
Test status | |
Simulation time | 755223500 ps |
CPU time | 4.94 seconds |
Started | Jun 05 05:39:30 PM PDT 24 |
Finished | Jun 05 05:39:36 PM PDT 24 |
Peak memory | 213280 kb |
Host | smart-b138a2c8-ec28-4f76-b495-60effe46799c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225368389 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.3225368389 |
Directory | /workspace/6.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.4008329959 |
Short name | T46 |
Test name | |
Test status | |
Simulation time | 34820267162 ps |
CPU time | 58.12 seconds |
Started | Jun 05 05:39:32 PM PDT 24 |
Finished | Jun 05 05:40:31 PM PDT 24 |
Peak memory | 221588 kb |
Host | smart-867e1acb-d832-4717-8599-099f78b48a61 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008329959 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.4008329959 |
Directory | /workspace/8.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/default/43.rv_dm_stress_all.3996258807 |
Short name | T32 |
Test name | |
Test status | |
Simulation time | 11133781911 ps |
CPU time | 30.3 seconds |
Started | Jun 05 05:40:48 PM PDT 24 |
Finished | Jun 05 05:41:19 PM PDT 24 |
Peak memory | 205096 kb |
Host | smart-0be6640e-22a2-4e6a-a079-3ddde833c1a9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996258807 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.3996258807 |
Directory | /workspace/43.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.2243770832 |
Short name | T255 |
Test name | |
Test status | |
Simulation time | 125800068343 ps |
CPU time | 340.09 seconds |
Started | Jun 05 05:40:23 PM PDT 24 |
Finished | Jun 05 05:46:04 PM PDT 24 |
Peak memory | 218168 kb |
Host | smart-ae813883-deb2-4a83-b6d5-b61a217d4f28 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2243770832 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.2243770832 |
Directory | /workspace/11.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2131168818 |
Short name | T97 |
Test name | |
Test status | |
Simulation time | 1187726895 ps |
CPU time | 67.4 seconds |
Started | Jun 05 05:39:26 PM PDT 24 |
Finished | Jun 05 05:40:33 PM PDT 24 |
Peak memory | 213284 kb |
Host | smart-a155044a-c791-4c89-aa5d-8ddf27358390 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131168818 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 4.rv_dm_csr_aliasing.2131168818 |
Directory | /workspace/4.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/default/3.rv_dm_sec_cm.1405988803 |
Short name | T44 |
Test name | |
Test status | |
Simulation time | 392201179 ps |
CPU time | 1.85 seconds |
Started | Jun 05 05:40:10 PM PDT 24 |
Finished | Jun 05 05:40:13 PM PDT 24 |
Peak memory | 229160 kb |
Host | smart-ca332c70-a865-4f8d-aff9-60b47e45be1c |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405988803 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.1405988803 |
Directory | /workspace/3.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.2779141588 |
Short name | T85 |
Test name | |
Test status | |
Simulation time | 417691425 ps |
CPU time | 3.83 seconds |
Started | Jun 05 05:39:50 PM PDT 24 |
Finished | Jun 05 05:39:54 PM PDT 24 |
Peak memory | 205012 kb |
Host | smart-1c7d2914-0917-43ea-b690-88c9ca1a332c |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779141588 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same _csr_outstanding.2779141588 |
Directory | /workspace/16.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/default/0.rv_dm_abstractcmd_status.552721940 |
Short name | T40 |
Test name | |
Test status | |
Simulation time | 121905123 ps |
CPU time | 0.85 seconds |
Started | Jun 05 05:39:55 PM PDT 24 |
Finished | Jun 05 05:39:56 PM PDT 24 |
Peak memory | 204716 kb |
Host | smart-43af3c5c-f7c4-49d0-9050-8ccd9e6e61cb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=552721940 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.552721940 |
Directory | /workspace/0.rv_dm_abstractcmd_status/latest |
Test location | /workspace/coverage/default/0.rv_dm_rom_read_access.1849795001 |
Short name | T33 |
Test name | |
Test status | |
Simulation time | 42070414 ps |
CPU time | 0.91 seconds |
Started | Jun 05 05:40:03 PM PDT 24 |
Finished | Jun 05 05:40:04 PM PDT 24 |
Peak memory | 212912 kb |
Host | smart-12aecccc-849e-4bbe-b43f-5a2aaa909b05 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1849795001 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.1849795001 |
Directory | /workspace/0.rv_dm_rom_read_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_exception.2396146646 |
Short name | T35 |
Test name | |
Test status | |
Simulation time | 1124922949 ps |
CPU time | 1.24 seconds |
Started | Jun 05 05:39:54 PM PDT 24 |
Finished | Jun 05 05:39:56 PM PDT 24 |
Peak memory | 204672 kb |
Host | smart-215cc893-2a81-4498-90cb-012290410b0b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2396146646 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.2396146646 |
Directory | /workspace/0.rv_dm_cmderr_exception/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.912857401 |
Short name | T119 |
Test name | |
Test status | |
Simulation time | 2357404746 ps |
CPU time | 20.3 seconds |
Started | Jun 05 05:39:48 PM PDT 24 |
Finished | Jun 05 05:40:09 PM PDT 24 |
Peak memory | 213384 kb |
Host | smart-332f0401-afcb-418f-adc5-c7785df4c8ff |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912857401 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.912857401 |
Directory | /workspace/16.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.659673585 |
Short name | T38 |
Test name | |
Test status | |
Simulation time | 495218016 ps |
CPU time | 2.09 seconds |
Started | Jun 05 05:40:05 PM PDT 24 |
Finished | Jun 05 05:40:08 PM PDT 24 |
Peak memory | 204708 kb |
Host | smart-19a04957-309d-48c7-aa54-28f4faf1a5a3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=659673585 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.659673585 |
Directory | /workspace/1.rv_dm_progbuf_read_write_execute/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3768200083 |
Short name | T273 |
Test name | |
Test status | |
Simulation time | 1297031296 ps |
CPU time | 3.95 seconds |
Started | Jun 05 05:39:11 PM PDT 24 |
Finished | Jun 05 05:39:16 PM PDT 24 |
Peak memory | 204740 kb |
Host | smart-42016f35-1d6b-4165-98fc-9e535f151dd6 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768200083 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.3 768200083 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/default/47.rv_dm_alert_test.226944933 |
Short name | T72 |
Test name | |
Test status | |
Simulation time | 77316419 ps |
CPU time | 0.71 seconds |
Started | Jun 05 05:40:46 PM PDT 24 |
Finished | Jun 05 05:40:47 PM PDT 24 |
Peak memory | 204804 kb |
Host | smart-754cbfc3-df7d-4f26-8ca6-7f18556eb077 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226944933 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.226944933 |
Directory | /workspace/47.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.2973405510 |
Short name | T222 |
Test name | |
Test status | |
Simulation time | 28231017752 ps |
CPU time | 81.36 seconds |
Started | Jun 05 05:40:23 PM PDT 24 |
Finished | Jun 05 05:41:45 PM PDT 24 |
Peak memory | 213420 kb |
Host | smart-c6e98ccd-f127-47d7-b306-e9c81984776e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2973405510 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.2973405510 |
Directory | /workspace/9.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3546585659 |
Short name | T131 |
Test name | |
Test status | |
Simulation time | 6428985065 ps |
CPU time | 33.91 seconds |
Started | Jun 05 05:39:40 PM PDT 24 |
Finished | Jun 05 05:40:15 PM PDT 24 |
Peak memory | 213472 kb |
Host | smart-00b4d9ce-aacf-4100-9c28-e6fd1a148537 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546585659 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.3546585659 |
Directory | /workspace/8.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2565789369 |
Short name | T91 |
Test name | |
Test status | |
Simulation time | 2156438417 ps |
CPU time | 3.77 seconds |
Started | Jun 05 05:39:13 PM PDT 24 |
Finished | Jun 05 05:39:17 PM PDT 24 |
Peak memory | 205108 kb |
Host | smart-1af075c8-c5dd-4b0f-be3b-e13f9855ca44 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565789369 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs r_hw_reset.2565789369 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.3514935314 |
Short name | T96 |
Test name | |
Test status | |
Simulation time | 468818658 ps |
CPU time | 7.17 seconds |
Started | Jun 05 05:39:30 PM PDT 24 |
Finished | Jun 05 05:39:38 PM PDT 24 |
Peak memory | 205116 kb |
Host | smart-3b35be22-05d8-4c9a-aa17-c7cf57ca1bbf |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514935314 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_ csr_outstanding.3514935314 |
Directory | /workspace/6.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.1332214071 |
Short name | T29 |
Test name | |
Test status | |
Simulation time | 4041353459 ps |
CPU time | 2.3 seconds |
Started | Jun 05 05:39:55 PM PDT 24 |
Finished | Jun 05 05:39:59 PM PDT 24 |
Peak memory | 204704 kb |
Host | smart-d7954dda-0b5d-4e57-bce4-2c94cb25d082 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1332214071 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.1332214071 |
Directory | /workspace/0.rv_dm_cmderr_halt_resume/latest |
Test location | /workspace/coverage/default/0.rv_dm_progbuf_busy.2732083789 |
Short name | T14 |
Test name | |
Test status | |
Simulation time | 243994454 ps |
CPU time | 1.24 seconds |
Started | Jun 05 05:39:57 PM PDT 24 |
Finished | Jun 05 05:40:00 PM PDT 24 |
Peak memory | 204692 kb |
Host | smart-ce7f0a3a-3e85-4f00-aead-f4caee14b9b1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2732083789 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.2732083789 |
Directory | /workspace/0.rv_dm_progbuf_busy/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2732757944 |
Short name | T104 |
Test name | |
Test status | |
Simulation time | 1143309237 ps |
CPU time | 62.5 seconds |
Started | Jun 05 05:39:21 PM PDT 24 |
Finished | Jun 05 05:40:24 PM PDT 24 |
Peak memory | 205044 kb |
Host | smart-bf723de0-9493-4a4c-8e21-2e5adea5d2ec |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732757944 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 2.rv_dm_csr_aliasing.2732757944 |
Directory | /workspace/2.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1992639804 |
Short name | T80 |
Test name | |
Test status | |
Simulation time | 3534246844 ps |
CPU time | 76.42 seconds |
Started | Jun 05 05:39:15 PM PDT 24 |
Finished | Jun 05 05:40:32 PM PDT 24 |
Peak memory | 205096 kb |
Host | smart-e6d695c1-b223-4705-bd74-bf6982261356 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992639804 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 0.rv_dm_csr_aliasing.1992639804 |
Directory | /workspace/0.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.3264086222 |
Short name | T400 |
Test name | |
Test status | |
Simulation time | 3669820654 ps |
CPU time | 24.12 seconds |
Started | Jun 05 05:39:39 PM PDT 24 |
Finished | Jun 05 05:40:04 PM PDT 24 |
Peak memory | 213384 kb |
Host | smart-01a27f35-ace9-43c2-b551-29a3434c41d8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264086222 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.3 264086222 |
Directory | /workspace/10.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2800625882 |
Short name | T128 |
Test name | |
Test status | |
Simulation time | 7324451699 ps |
CPU time | 21.03 seconds |
Started | Jun 05 05:39:54 PM PDT 24 |
Finished | Jun 05 05:40:16 PM PDT 24 |
Peak memory | 213420 kb |
Host | smart-329ceeac-97a4-4179-a491-f539635ce46a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800625882 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.2 800625882 |
Directory | /workspace/17.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.370800076 |
Short name | T125 |
Test name | |
Test status | |
Simulation time | 2437674825 ps |
CPU time | 9.76 seconds |
Started | Jun 05 05:39:54 PM PDT 24 |
Finished | Jun 05 05:40:04 PM PDT 24 |
Peak memory | 213364 kb |
Host | smart-4d5f710e-af65-4064-b962-63505153f76e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370800076 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.370800076 |
Directory | /workspace/18.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.3059471437 |
Short name | T112 |
Test name | |
Test status | |
Simulation time | 1423588096 ps |
CPU time | 55.37 seconds |
Started | Jun 05 05:39:09 PM PDT 24 |
Finished | Jun 05 05:40:05 PM PDT 24 |
Peak memory | 213180 kb |
Host | smart-98811155-3919-4eaf-9739-ea1ebc86aacd |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059471437 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.3059471437 |
Directory | /workspace/0.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.2595829471 |
Short name | T103 |
Test name | |
Test status | |
Simulation time | 296000080 ps |
CPU time | 2.65 seconds |
Started | Jun 05 05:39:11 PM PDT 24 |
Finished | Jun 05 05:39:15 PM PDT 24 |
Peak memory | 213288 kb |
Host | smart-7ce701f1-b932-44a5-934b-1c66c9454944 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595829471 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.2595829471 |
Directory | /workspace/0.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.2705409044 |
Short name | T297 |
Test name | |
Test status | |
Simulation time | 1452575749 ps |
CPU time | 4.47 seconds |
Started | Jun 05 05:39:07 PM PDT 24 |
Finished | Jun 05 05:39:12 PM PDT 24 |
Peak memory | 217876 kb |
Host | smart-3b121e78-6eff-4533-a800-7c0a157ffe4a |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705409044 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.2705409044 |
Directory | /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.76794750 |
Short name | T113 |
Test name | |
Test status | |
Simulation time | 157615361 ps |
CPU time | 2.6 seconds |
Started | Jun 05 05:39:13 PM PDT 24 |
Finished | Jun 05 05:39:16 PM PDT 24 |
Peak memory | 213232 kb |
Host | smart-7734e799-2277-4a05-bd1f-5847871e2646 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76794750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.76794750 |
Directory | /workspace/0.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1756705877 |
Short name | T411 |
Test name | |
Test status | |
Simulation time | 123356151726 ps |
CPU time | 68.69 seconds |
Started | Jun 05 05:39:12 PM PDT 24 |
Finished | Jun 05 05:40:21 PM PDT 24 |
Peak memory | 205112 kb |
Host | smart-4b604aad-dce3-4781-9e21-9bee518f4b35 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756705877 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs r_aliasing.1756705877 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1700081955 |
Short name | T299 |
Test name | |
Test status | |
Simulation time | 15628849213 ps |
CPU time | 12.28 seconds |
Started | Jun 05 05:39:09 PM PDT 24 |
Finished | Jun 05 05:39:22 PM PDT 24 |
Peak memory | 204980 kb |
Host | smart-dce1bcca-0fc7-42f8-9a11-c8f256056dc2 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700081955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0. rv_dm_jtag_dmi_csr_bit_bash.1700081955 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.360860593 |
Short name | T271 |
Test name | |
Test status | |
Simulation time | 8342959590 ps |
CPU time | 4.33 seconds |
Started | Jun 05 05:39:07 PM PDT 24 |
Finished | Jun 05 05:39:12 PM PDT 24 |
Peak memory | 205016 kb |
Host | smart-9df63c76-15a3-41f9-bcf8-673b274e19ec |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360860593 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.360860593 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.4197413446 |
Short name | T410 |
Test name | |
Test status | |
Simulation time | 1068271585 ps |
CPU time | 1.7 seconds |
Started | Jun 05 05:39:09 PM PDT 24 |
Finished | Jun 05 05:39:12 PM PDT 24 |
Peak memory | 204692 kb |
Host | smart-5886d9ac-29dd-4892-9ba3-1dd73b7afcbc |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197413446 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_aliasing.4197413446 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1697469815 |
Short name | T291 |
Test name | |
Test status | |
Simulation time | 11580345111 ps |
CPU time | 10.34 seconds |
Started | Jun 05 05:39:11 PM PDT 24 |
Finished | Jun 05 05:39:22 PM PDT 24 |
Peak memory | 205032 kb |
Host | smart-e56e9932-7472-4006-8452-54a71b0d3ce8 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697469815 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_bit_bash.1697469815 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3840072098 |
Short name | T306 |
Test name | |
Test status | |
Simulation time | 295997878 ps |
CPU time | 1.52 seconds |
Started | Jun 05 05:39:11 PM PDT 24 |
Finished | Jun 05 05:39:13 PM PDT 24 |
Peak memory | 204752 kb |
Host | smart-09ab5004-4318-4287-adab-c329080610de |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840072098 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_hw_reset.3840072098 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1128236661 |
Short name | T359 |
Test name | |
Test status | |
Simulation time | 134794747 ps |
CPU time | 0.73 seconds |
Started | Jun 05 05:39:11 PM PDT 24 |
Finished | Jun 05 05:39:12 PM PDT 24 |
Peak memory | 204752 kb |
Host | smart-98b75d62-9ee8-49dc-8d69-87ea7ae4f7d9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128236661 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par tial_access.1128236661 |
Directory | /workspace/0.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.2504463502 |
Short name | T329 |
Test name | |
Test status | |
Simulation time | 215937527 ps |
CPU time | 0.72 seconds |
Started | Jun 05 05:39:08 PM PDT 24 |
Finished | Jun 05 05:39:09 PM PDT 24 |
Peak memory | 204712 kb |
Host | smart-25b1f77f-02c5-443a-8da8-e9d16ef59799 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504463502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.2504463502 |
Directory | /workspace/0.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2340101059 |
Short name | T334 |
Test name | |
Test status | |
Simulation time | 733326746 ps |
CPU time | 7.75 seconds |
Started | Jun 05 05:39:11 PM PDT 24 |
Finished | Jun 05 05:39:19 PM PDT 24 |
Peak memory | 205056 kb |
Host | smart-0a784c31-c681-422c-9baa-31cea0066e97 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340101059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_ csr_outstanding.2340101059 |
Directory | /workspace/0.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.652531997 |
Short name | T407 |
Test name | |
Test status | |
Simulation time | 70856192258 ps |
CPU time | 57.49 seconds |
Started | Jun 05 05:39:13 PM PDT 24 |
Finished | Jun 05 05:40:11 PM PDT 24 |
Peak memory | 225356 kb |
Host | smart-927ba240-f670-4451-95cc-acf52a5de43d |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652531997 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.652531997 |
Directory | /workspace/0.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.2791925300 |
Short name | T118 |
Test name | |
Test status | |
Simulation time | 698798320 ps |
CPU time | 5.84 seconds |
Started | Jun 05 05:39:09 PM PDT 24 |
Finished | Jun 05 05:39:15 PM PDT 24 |
Peak memory | 213360 kb |
Host | smart-675e83fd-f32f-4b10-87ee-7b23205bc545 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791925300 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.2791925300 |
Directory | /workspace/0.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.105476833 |
Short name | T305 |
Test name | |
Test status | |
Simulation time | 1201141180 ps |
CPU time | 10.27 seconds |
Started | Jun 05 05:39:11 PM PDT 24 |
Finished | Jun 05 05:39:22 PM PDT 24 |
Peak memory | 221420 kb |
Host | smart-76212a4b-7a20-4a59-a1c4-d1dd3dd88164 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105476833 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.105476833 |
Directory | /workspace/0.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.208538831 |
Short name | T95 |
Test name | |
Test status | |
Simulation time | 2351340520 ps |
CPU time | 27.03 seconds |
Started | Jun 05 05:39:09 PM PDT 24 |
Finished | Jun 05 05:39:37 PM PDT 24 |
Peak memory | 205100 kb |
Host | smart-fbfa4aad-d6b8-47be-94e9-87ce71c9c657 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208538831 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 1.rv_dm_csr_aliasing.208538831 |
Directory | /workspace/1.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.1401527840 |
Short name | T83 |
Test name | |
Test status | |
Simulation time | 21494624540 ps |
CPU time | 37.37 seconds |
Started | Jun 05 05:39:13 PM PDT 24 |
Finished | Jun 05 05:39:51 PM PDT 24 |
Peak memory | 205152 kb |
Host | smart-27cd3aa5-27b7-4a7a-b86e-ab19bf27c1d6 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401527840 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.1401527840 |
Directory | /workspace/1.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2664802041 |
Short name | T102 |
Test name | |
Test status | |
Simulation time | 265211357 ps |
CPU time | 1.7 seconds |
Started | Jun 05 05:39:17 PM PDT 24 |
Finished | Jun 05 05:39:19 PM PDT 24 |
Peak memory | 213212 kb |
Host | smart-256919f8-4895-4270-8d1f-217247e2c0d6 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664802041 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.2664802041 |
Directory | /workspace/1.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3282303208 |
Short name | T296 |
Test name | |
Test status | |
Simulation time | 1212265913 ps |
CPU time | 5.31 seconds |
Started | Jun 05 05:39:16 PM PDT 24 |
Finished | Jun 05 05:39:22 PM PDT 24 |
Peak memory | 217284 kb |
Host | smart-9acbf304-d4df-4ca2-9755-70e9e26efc53 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282303208 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.3282303208 |
Directory | /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2055626883 |
Short name | T320 |
Test name | |
Test status | |
Simulation time | 187229191 ps |
CPU time | 2.63 seconds |
Started | Jun 05 05:39:14 PM PDT 24 |
Finished | Jun 05 05:39:17 PM PDT 24 |
Peak memory | 213232 kb |
Host | smart-66f84519-188f-4447-83fb-72f456c4c170 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055626883 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.2055626883 |
Directory | /workspace/1.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.468298509 |
Short name | T309 |
Test name | |
Test status | |
Simulation time | 69116722803 ps |
CPU time | 213.95 seconds |
Started | Jun 05 05:39:18 PM PDT 24 |
Finished | Jun 05 05:42:53 PM PDT 24 |
Peak memory | 205004 kb |
Host | smart-38f528eb-1abe-4125-8cfe-f3117c557ec6 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468298509 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr _aliasing.468298509 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3663693144 |
Short name | T302 |
Test name | |
Test status | |
Simulation time | 12231589739 ps |
CPU time | 5.74 seconds |
Started | Jun 05 05:39:16 PM PDT 24 |
Finished | Jun 05 05:39:23 PM PDT 24 |
Peak memory | 205048 kb |
Host | smart-fedb88b7-27fe-4e6b-ad04-39f0b820d0ed |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663693144 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1. rv_dm_jtag_dmi_csr_bit_bash.3663693144 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.4060187549 |
Short name | T342 |
Test name | |
Test status | |
Simulation time | 3362376831 ps |
CPU time | 2.66 seconds |
Started | Jun 05 05:39:22 PM PDT 24 |
Finished | Jun 05 05:39:26 PM PDT 24 |
Peak memory | 205076 kb |
Host | smart-2dba8083-10cc-4592-aaf9-11356c934711 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060187549 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs r_hw_reset.4060187549 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.3616473835 |
Short name | T293 |
Test name | |
Test status | |
Simulation time | 8296130053 ps |
CPU time | 6.57 seconds |
Started | Jun 05 05:39:14 PM PDT 24 |
Finished | Jun 05 05:39:22 PM PDT 24 |
Peak memory | 205064 kb |
Host | smart-3c2736a8-10e6-4e4b-ae70-838733dec892 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616473835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.3 616473835 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3097740360 |
Short name | T384 |
Test name | |
Test status | |
Simulation time | 3498063960 ps |
CPU time | 10.26 seconds |
Started | Jun 05 05:39:14 PM PDT 24 |
Finished | Jun 05 05:39:25 PM PDT 24 |
Peak memory | 204800 kb |
Host | smart-635e9eb3-8763-47e0-bb8d-2326624327ed |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097740360 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_aliasing.3097740360 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2159902619 |
Short name | T358 |
Test name | |
Test status | |
Simulation time | 10151905269 ps |
CPU time | 28.4 seconds |
Started | Jun 05 05:39:15 PM PDT 24 |
Finished | Jun 05 05:39:44 PM PDT 24 |
Peak memory | 205048 kb |
Host | smart-6c1747f8-70e9-4edb-9de0-e8e19f03cf26 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159902619 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_bit_bash.2159902619 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.3973080063 |
Short name | T267 |
Test name | |
Test status | |
Simulation time | 363811726 ps |
CPU time | 1.21 seconds |
Started | Jun 05 05:39:08 PM PDT 24 |
Finished | Jun 05 05:39:10 PM PDT 24 |
Peak memory | 204768 kb |
Host | smart-a74e3c79-dd3a-45cc-a3e2-79818c5e250e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973080063 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_hw_reset.3973080063 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3412211596 |
Short name | T270 |
Test name | |
Test status | |
Simulation time | 244949310 ps |
CPU time | 0.73 seconds |
Started | Jun 05 05:39:15 PM PDT 24 |
Finished | Jun 05 05:39:17 PM PDT 24 |
Peak memory | 204728 kb |
Host | smart-a9dfb34c-5291-4c1b-a235-4fdf6b45ff24 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412211596 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.3 412211596 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.256614842 |
Short name | T281 |
Test name | |
Test status | |
Simulation time | 70696387 ps |
CPU time | 0.74 seconds |
Started | Jun 05 05:39:15 PM PDT 24 |
Finished | Jun 05 05:39:17 PM PDT 24 |
Peak memory | 204784 kb |
Host | smart-de717c41-d5db-4bf7-bb34-705faec0c17d |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256614842 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_part ial_access.256614842 |
Directory | /workspace/1.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.3053796212 |
Short name | T376 |
Test name | |
Test status | |
Simulation time | 133152452 ps |
CPU time | 0.74 seconds |
Started | Jun 05 05:39:15 PM PDT 24 |
Finished | Jun 05 05:39:17 PM PDT 24 |
Peak memory | 204720 kb |
Host | smart-811875aa-6d81-4437-b91f-bb1200f52e6d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053796212 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.3053796212 |
Directory | /workspace/1.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3713520 |
Short name | T379 |
Test name | |
Test status | |
Simulation time | 252834250 ps |
CPU time | 6.66 seconds |
Started | Jun 05 05:39:14 PM PDT 24 |
Finished | Jun 05 05:39:21 PM PDT 24 |
Peak memory | 205120 kb |
Host | smart-c7aa69dd-187b-4fd7-b06f-515ebb078000 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713520 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_csr _outstanding.3713520 |
Directory | /workspace/1.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.2782396746 |
Short name | T333 |
Test name | |
Test status | |
Simulation time | 45947370627 ps |
CPU time | 14.62 seconds |
Started | Jun 05 05:39:21 PM PDT 24 |
Finished | Jun 05 05:39:36 PM PDT 24 |
Peak memory | 221720 kb |
Host | smart-015626a4-0f9f-4494-ae5d-293d2797305d |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782396746 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.2782396746 |
Directory | /workspace/1.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.843839969 |
Short name | T54 |
Test name | |
Test status | |
Simulation time | 68914238 ps |
CPU time | 2.96 seconds |
Started | Jun 05 05:39:16 PM PDT 24 |
Finished | Jun 05 05:39:20 PM PDT 24 |
Peak memory | 213364 kb |
Host | smart-ee353391-7ce6-4df7-ab9a-b190c60eb96b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843839969 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.843839969 |
Directory | /workspace/1.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.4194863292 |
Short name | T375 |
Test name | |
Test status | |
Simulation time | 1201703630 ps |
CPU time | 9.25 seconds |
Started | Jun 05 05:39:15 PM PDT 24 |
Finished | Jun 05 05:39:26 PM PDT 24 |
Peak memory | 213320 kb |
Host | smart-8d4504bf-e51a-45c5-81d9-6879551256cf |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194863292 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.4194863292 |
Directory | /workspace/1.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.2384328369 |
Short name | T388 |
Test name | |
Test status | |
Simulation time | 2071799366 ps |
CPU time | 6.38 seconds |
Started | Jun 05 05:39:40 PM PDT 24 |
Finished | Jun 05 05:39:48 PM PDT 24 |
Peak memory | 219552 kb |
Host | smart-78277be8-d939-439f-9656-7f3944317cca |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384328369 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.2384328369 |
Directory | /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.2938663234 |
Short name | T284 |
Test name | |
Test status | |
Simulation time | 487758479 ps |
CPU time | 1.48 seconds |
Started | Jun 05 05:39:41 PM PDT 24 |
Finished | Jun 05 05:39:43 PM PDT 24 |
Peak memory | 213248 kb |
Host | smart-1e2930da-872e-4695-935e-27a99f98e05d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938663234 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.2938663234 |
Directory | /workspace/10.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.1153579535 |
Short name | T269 |
Test name | |
Test status | |
Simulation time | 21768942301 ps |
CPU time | 35.8 seconds |
Started | Jun 05 05:39:39 PM PDT 24 |
Finished | Jun 05 05:40:15 PM PDT 24 |
Peak memory | 205016 kb |
Host | smart-858b4ae1-2278-411a-969b-1b459d5c387d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153579535 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10 .rv_dm_jtag_dmi_csr_bit_bash.1153579535 |
Directory | /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2529352170 |
Short name | T307 |
Test name | |
Test status | |
Simulation time | 1038177247 ps |
CPU time | 3.47 seconds |
Started | Jun 05 05:39:39 PM PDT 24 |
Finished | Jun 05 05:39:43 PM PDT 24 |
Peak memory | 204920 kb |
Host | smart-e2ac711e-410c-4d2e-900b-cce83240e5ad |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529352170 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw. 2529352170 |
Directory | /workspace/10.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.2372784033 |
Short name | T313 |
Test name | |
Test status | |
Simulation time | 211711421 ps |
CPU time | 0.96 seconds |
Started | Jun 05 05:39:40 PM PDT 24 |
Finished | Jun 05 05:39:42 PM PDT 24 |
Peak memory | 204896 kb |
Host | smart-91a28192-1c6a-4ed5-ab5d-39314903a8a7 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372784033 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw. 2372784033 |
Directory | /workspace/10.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.4181372437 |
Short name | T99 |
Test name | |
Test status | |
Simulation time | 637101926 ps |
CPU time | 8.17 seconds |
Started | Jun 05 05:39:40 PM PDT 24 |
Finished | Jun 05 05:39:49 PM PDT 24 |
Peak memory | 205192 kb |
Host | smart-5f97a3b5-f5e9-48e0-8834-209d55afc047 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181372437 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same _csr_outstanding.4181372437 |
Directory | /workspace/10.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.612086341 |
Short name | T372 |
Test name | |
Test status | |
Simulation time | 152862387 ps |
CPU time | 4.56 seconds |
Started | Jun 05 05:39:40 PM PDT 24 |
Finished | Jun 05 05:39:46 PM PDT 24 |
Peak memory | 213444 kb |
Host | smart-8fb8a0b4-696b-4ec3-865a-8c7c8e7354c2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612086341 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.612086341 |
Directory | /workspace/10.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.4157165285 |
Short name | T321 |
Test name | |
Test status | |
Simulation time | 479651935 ps |
CPU time | 2.53 seconds |
Started | Jun 05 05:39:40 PM PDT 24 |
Finished | Jun 05 05:39:44 PM PDT 24 |
Peak memory | 218176 kb |
Host | smart-13fd1031-f277-424b-8b69-5fabc640d654 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157165285 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.4157165285 |
Directory | /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.1439837250 |
Short name | T409 |
Test name | |
Test status | |
Simulation time | 248925236 ps |
CPU time | 1.6 seconds |
Started | Jun 05 05:39:38 PM PDT 24 |
Finished | Jun 05 05:39:40 PM PDT 24 |
Peak memory | 213296 kb |
Host | smart-f931c515-9f2b-4994-a55c-5884d8947516 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439837250 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.1439837250 |
Directory | /workspace/11.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.146799469 |
Short name | T346 |
Test name | |
Test status | |
Simulation time | 6136987668 ps |
CPU time | 5.83 seconds |
Started | Jun 05 05:39:41 PM PDT 24 |
Finished | Jun 05 05:39:47 PM PDT 24 |
Peak memory | 205012 kb |
Host | smart-66e99e8d-30e1-4f6f-b217-89cf61fb6eb3 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146799469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11. rv_dm_jtag_dmi_csr_bit_bash.146799469 |
Directory | /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.4084771240 |
Short name | T401 |
Test name | |
Test status | |
Simulation time | 11483809377 ps |
CPU time | 9.33 seconds |
Started | Jun 05 05:39:39 PM PDT 24 |
Finished | Jun 05 05:39:49 PM PDT 24 |
Peak memory | 205056 kb |
Host | smart-7e9558b7-9e04-4805-9a1e-b47ebecac698 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084771240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw. 4084771240 |
Directory | /workspace/11.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.1732284706 |
Short name | T319 |
Test name | |
Test status | |
Simulation time | 638485561 ps |
CPU time | 2.1 seconds |
Started | Jun 05 05:39:40 PM PDT 24 |
Finished | Jun 05 05:39:43 PM PDT 24 |
Peak memory | 204708 kb |
Host | smart-3789ff9c-81fb-4ca7-b9fa-7578d2cfc63e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732284706 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw. 1732284706 |
Directory | /workspace/11.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.2992661607 |
Short name | T116 |
Test name | |
Test status | |
Simulation time | 108020401 ps |
CPU time | 3.83 seconds |
Started | Jun 05 05:39:39 PM PDT 24 |
Finished | Jun 05 05:39:43 PM PDT 24 |
Peak memory | 205124 kb |
Host | smart-8cb4cec3-c95e-4b71-9253-58435f3c1a0b |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992661607 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same _csr_outstanding.2992661607 |
Directory | /workspace/11.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.3366484187 |
Short name | T394 |
Test name | |
Test status | |
Simulation time | 366715089 ps |
CPU time | 4.07 seconds |
Started | Jun 05 05:39:40 PM PDT 24 |
Finished | Jun 05 05:39:45 PM PDT 24 |
Peak memory | 213448 kb |
Host | smart-6c20de2b-1bec-49be-8339-2c6cf495714c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366484187 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.3366484187 |
Directory | /workspace/11.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.4049262050 |
Short name | T129 |
Test name | |
Test status | |
Simulation time | 1959596313 ps |
CPU time | 9.85 seconds |
Started | Jun 05 05:39:41 PM PDT 24 |
Finished | Jun 05 05:39:52 PM PDT 24 |
Peak memory | 213308 kb |
Host | smart-9d816353-d1b5-4830-9598-98a7fe27dfc8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049262050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.4 049262050 |
Directory | /workspace/11.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.4173509813 |
Short name | T310 |
Test name | |
Test status | |
Simulation time | 781781811 ps |
CPU time | 2.13 seconds |
Started | Jun 05 05:39:47 PM PDT 24 |
Finished | Jun 05 05:39:50 PM PDT 24 |
Peak memory | 215384 kb |
Host | smart-e06d0219-4ea3-47d9-a428-ecefa654c3e0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173509813 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.4173509813 |
Directory | /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.2532200427 |
Short name | T349 |
Test name | |
Test status | |
Simulation time | 56505546 ps |
CPU time | 1.48 seconds |
Started | Jun 05 05:39:49 PM PDT 24 |
Finished | Jun 05 05:39:51 PM PDT 24 |
Peak memory | 213244 kb |
Host | smart-96183e4c-6913-443b-a428-c45ffd87542a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532200427 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.2532200427 |
Directory | /workspace/12.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.1492173002 |
Short name | T290 |
Test name | |
Test status | |
Simulation time | 90812472815 ps |
CPU time | 226.01 seconds |
Started | Jun 05 05:39:37 PM PDT 24 |
Finished | Jun 05 05:43:24 PM PDT 24 |
Peak memory | 205104 kb |
Host | smart-606661f2-b37b-4682-a5a4-3f81b524f768 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492173002 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12 .rv_dm_jtag_dmi_csr_bit_bash.1492173002 |
Directory | /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.3528977397 |
Short name | T368 |
Test name | |
Test status | |
Simulation time | 5001272529 ps |
CPU time | 6.51 seconds |
Started | Jun 05 05:39:37 PM PDT 24 |
Finished | Jun 05 05:39:44 PM PDT 24 |
Peak memory | 205048 kb |
Host | smart-945b7fae-c1ed-45ec-af18-3aa1a3908e22 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528977397 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw. 3528977397 |
Directory | /workspace/12.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.62121119 |
Short name | T350 |
Test name | |
Test status | |
Simulation time | 303923618 ps |
CPU time | 1.07 seconds |
Started | Jun 05 05:39:37 PM PDT 24 |
Finished | Jun 05 05:39:39 PM PDT 24 |
Peak memory | 204732 kb |
Host | smart-8f166f52-8523-422c-a185-a7daf5278a24 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62121119 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.62121119 |
Directory | /workspace/12.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1665939596 |
Short name | T396 |
Test name | |
Test status | |
Simulation time | 900743743 ps |
CPU time | 8.11 seconds |
Started | Jun 05 05:39:51 PM PDT 24 |
Finished | Jun 05 05:40:00 PM PDT 24 |
Peak memory | 205128 kb |
Host | smart-9af44002-7b4a-4cd0-83c9-0f16afd36db6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665939596 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same _csr_outstanding.1665939596 |
Directory | /workspace/12.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.2570373495 |
Short name | T288 |
Test name | |
Test status | |
Simulation time | 229179918 ps |
CPU time | 5.62 seconds |
Started | Jun 05 05:39:47 PM PDT 24 |
Finished | Jun 05 05:39:53 PM PDT 24 |
Peak memory | 213468 kb |
Host | smart-6a419f6f-5ef6-47fd-ace2-586d7e0e3ba9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570373495 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.2570373495 |
Directory | /workspace/12.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.1537392102 |
Short name | T78 |
Test name | |
Test status | |
Simulation time | 4886764701 ps |
CPU time | 20.17 seconds |
Started | Jun 05 05:39:50 PM PDT 24 |
Finished | Jun 05 05:40:11 PM PDT 24 |
Peak memory | 213420 kb |
Host | smart-98630206-5ce4-42d3-8ce2-500f83379a39 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537392102 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.1 537392102 |
Directory | /workspace/12.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.564661362 |
Short name | T380 |
Test name | |
Test status | |
Simulation time | 1345674810 ps |
CPU time | 5.92 seconds |
Started | Jun 05 05:39:47 PM PDT 24 |
Finished | Jun 05 05:39:54 PM PDT 24 |
Peak memory | 221532 kb |
Host | smart-f65c6ed9-b8ef-4b9b-927c-c4f578b8c345 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564661362 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.564661362 |
Directory | /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.1628612304 |
Short name | T111 |
Test name | |
Test status | |
Simulation time | 145104205 ps |
CPU time | 2.49 seconds |
Started | Jun 05 05:39:47 PM PDT 24 |
Finished | Jun 05 05:39:50 PM PDT 24 |
Peak memory | 213260 kb |
Host | smart-28f2bc10-fd3c-4907-8f2c-db053d8cbedb |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628612304 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.1628612304 |
Directory | /workspace/13.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.3369710092 |
Short name | T390 |
Test name | |
Test status | |
Simulation time | 15404932313 ps |
CPU time | 46.19 seconds |
Started | Jun 05 05:39:47 PM PDT 24 |
Finished | Jun 05 05:40:34 PM PDT 24 |
Peak memory | 205040 kb |
Host | smart-3049f8df-036c-4653-8278-b32a7c376615 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369710092 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13 .rv_dm_jtag_dmi_csr_bit_bash.3369710092 |
Directory | /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.145586367 |
Short name | T382 |
Test name | |
Test status | |
Simulation time | 2807265238 ps |
CPU time | 3.47 seconds |
Started | Jun 05 05:39:49 PM PDT 24 |
Finished | Jun 05 05:39:53 PM PDT 24 |
Peak memory | 204988 kb |
Host | smart-746ad43b-73f4-4e0b-b6f8-3d1e75ab553b |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145586367 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.145586367 |
Directory | /workspace/13.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3465862531 |
Short name | T403 |
Test name | |
Test status | |
Simulation time | 1202038268 ps |
CPU time | 3.9 seconds |
Started | Jun 05 05:39:49 PM PDT 24 |
Finished | Jun 05 05:39:54 PM PDT 24 |
Peak memory | 204720 kb |
Host | smart-5923146c-6cc6-4196-92cf-8bf3fbb0ce87 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465862531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw. 3465862531 |
Directory | /workspace/13.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.1081100298 |
Short name | T82 |
Test name | |
Test status | |
Simulation time | 3440967396 ps |
CPU time | 4.55 seconds |
Started | Jun 05 05:39:48 PM PDT 24 |
Finished | Jun 05 05:39:53 PM PDT 24 |
Peak memory | 205232 kb |
Host | smart-18c79067-24d7-4243-838f-fdf9eb775d7a |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081100298 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same _csr_outstanding.1081100298 |
Directory | /workspace/13.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.3345147609 |
Short name | T367 |
Test name | |
Test status | |
Simulation time | 101210929 ps |
CPU time | 4.84 seconds |
Started | Jun 05 05:39:51 PM PDT 24 |
Finished | Jun 05 05:39:57 PM PDT 24 |
Peak memory | 213344 kb |
Host | smart-37b9cefb-d700-4559-a442-20df335b6dce |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345147609 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.3345147609 |
Directory | /workspace/13.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2932053649 |
Short name | T53 |
Test name | |
Test status | |
Simulation time | 2697856830 ps |
CPU time | 23.11 seconds |
Started | Jun 05 05:39:47 PM PDT 24 |
Finished | Jun 05 05:40:11 PM PDT 24 |
Peak memory | 213416 kb |
Host | smart-b23f843f-b93d-44d7-9f58-2016043416b5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932053649 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.2 932053649 |
Directory | /workspace/13.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.1188547963 |
Short name | T323 |
Test name | |
Test status | |
Simulation time | 2334411999 ps |
CPU time | 6.04 seconds |
Started | Jun 05 05:39:48 PM PDT 24 |
Finished | Jun 05 05:39:55 PM PDT 24 |
Peak memory | 221664 kb |
Host | smart-c8d4b87a-839f-421d-a804-6eb5fca1907e |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188547963 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.1188547963 |
Directory | /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.3285620499 |
Short name | T353 |
Test name | |
Test status | |
Simulation time | 83563500 ps |
CPU time | 1.72 seconds |
Started | Jun 05 05:39:48 PM PDT 24 |
Finished | Jun 05 05:39:51 PM PDT 24 |
Peak memory | 213312 kb |
Host | smart-0fc22497-d3df-4bd9-8dd9-69a498448d86 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285620499 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.3285620499 |
Directory | /workspace/14.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.15400953 |
Short name | T365 |
Test name | |
Test status | |
Simulation time | 8494168168 ps |
CPU time | 7.2 seconds |
Started | Jun 05 05:39:53 PM PDT 24 |
Finished | Jun 05 05:40:01 PM PDT 24 |
Peak memory | 205256 kb |
Host | smart-fdc069ff-5e6f-459b-8af9-eb38e31cd8a1 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15400953 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.r v_dm_jtag_dmi_csr_bit_bash.15400953 |
Directory | /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.4191231445 |
Short name | T371 |
Test name | |
Test status | |
Simulation time | 3001620136 ps |
CPU time | 8.44 seconds |
Started | Jun 05 05:39:51 PM PDT 24 |
Finished | Jun 05 05:40:00 PM PDT 24 |
Peak memory | 205184 kb |
Host | smart-b7b2844a-1568-4039-bea7-c427b5ef1954 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191231445 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw. 4191231445 |
Directory | /workspace/14.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.881850978 |
Short name | T276 |
Test name | |
Test status | |
Simulation time | 332241367 ps |
CPU time | 1.56 seconds |
Started | Jun 05 05:39:49 PM PDT 24 |
Finished | Jun 05 05:39:51 PM PDT 24 |
Peak memory | 204736 kb |
Host | smart-a358270f-df85-4ba2-92e8-a74fb22d2bec |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881850978 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.881850978 |
Directory | /workspace/14.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1749629125 |
Short name | T285 |
Test name | |
Test status | |
Simulation time | 1979730483 ps |
CPU time | 8.24 seconds |
Started | Jun 05 05:39:45 PM PDT 24 |
Finished | Jun 05 05:39:54 PM PDT 24 |
Peak memory | 205136 kb |
Host | smart-78c738cd-63a7-4766-b785-e6fa3d0c8511 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749629125 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same _csr_outstanding.1749629125 |
Directory | /workspace/14.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.2247557780 |
Short name | T325 |
Test name | |
Test status | |
Simulation time | 427538552 ps |
CPU time | 4.54 seconds |
Started | Jun 05 05:39:48 PM PDT 24 |
Finished | Jun 05 05:39:53 PM PDT 24 |
Peak memory | 213340 kb |
Host | smart-1f564d16-ca32-4059-8fb9-45460f1bb646 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247557780 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.2247557780 |
Directory | /workspace/14.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.2807018189 |
Short name | T392 |
Test name | |
Test status | |
Simulation time | 642995903 ps |
CPU time | 9.76 seconds |
Started | Jun 05 05:39:49 PM PDT 24 |
Finished | Jun 05 05:39:59 PM PDT 24 |
Peak memory | 213368 kb |
Host | smart-abf70936-9867-403a-84f2-29b54d4b92a6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807018189 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.2 807018189 |
Directory | /workspace/14.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.64022824 |
Short name | T348 |
Test name | |
Test status | |
Simulation time | 4850360095 ps |
CPU time | 4.95 seconds |
Started | Jun 05 05:39:47 PM PDT 24 |
Finished | Jun 05 05:39:53 PM PDT 24 |
Peak memory | 221680 kb |
Host | smart-8bb87a45-1107-4889-b686-79ebceb8355f |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64022824 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.64022824 |
Directory | /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.1206911007 |
Short name | T277 |
Test name | |
Test status | |
Simulation time | 94753005 ps |
CPU time | 1.51 seconds |
Started | Jun 05 05:39:46 PM PDT 24 |
Finished | Jun 05 05:39:48 PM PDT 24 |
Peak memory | 213256 kb |
Host | smart-127d239b-dcc5-4370-aaee-4a971b3b3424 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206911007 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.1206911007 |
Directory | /workspace/15.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.2030694784 |
Short name | T266 |
Test name | |
Test status | |
Simulation time | 68507861926 ps |
CPU time | 18.65 seconds |
Started | Jun 05 05:39:48 PM PDT 24 |
Finished | Jun 05 05:40:07 PM PDT 24 |
Peak memory | 205048 kb |
Host | smart-c4b3c171-7006-441c-a039-bdc2245498c1 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030694784 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15 .rv_dm_jtag_dmi_csr_bit_bash.2030694784 |
Directory | /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3046184402 |
Short name | T366 |
Test name | |
Test status | |
Simulation time | 3789679246 ps |
CPU time | 10.11 seconds |
Started | Jun 05 05:39:49 PM PDT 24 |
Finished | Jun 05 05:40:00 PM PDT 24 |
Peak memory | 205004 kb |
Host | smart-c506fc0a-35a4-4102-8542-b4ea9abae2ea |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046184402 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw. 3046184402 |
Directory | /workspace/15.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.927517359 |
Short name | T68 |
Test name | |
Test status | |
Simulation time | 1490955433 ps |
CPU time | 1.34 seconds |
Started | Jun 05 05:39:48 PM PDT 24 |
Finished | Jun 05 05:39:50 PM PDT 24 |
Peak memory | 204720 kb |
Host | smart-b76872ab-2bdc-4374-83f8-6b08b786bfac |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927517359 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.927517359 |
Directory | /workspace/15.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.539648285 |
Short name | T87 |
Test name | |
Test status | |
Simulation time | 169065505 ps |
CPU time | 6.86 seconds |
Started | Jun 05 05:39:48 PM PDT 24 |
Finished | Jun 05 05:39:56 PM PDT 24 |
Peak memory | 205112 kb |
Host | smart-903bf36c-756b-47f2-8965-a37d4f701961 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539648285 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same_ csr_outstanding.539648285 |
Directory | /workspace/15.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.2105191247 |
Short name | T282 |
Test name | |
Test status | |
Simulation time | 190282677 ps |
CPU time | 3.64 seconds |
Started | Jun 05 05:39:49 PM PDT 24 |
Finished | Jun 05 05:39:53 PM PDT 24 |
Peak memory | 213304 kb |
Host | smart-c0e71d04-d2ed-46ff-9e94-ddc28d357c4a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105191247 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.2105191247 |
Directory | /workspace/15.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.1378139700 |
Short name | T120 |
Test name | |
Test status | |
Simulation time | 19772542315 ps |
CPU time | 24.39 seconds |
Started | Jun 05 05:39:51 PM PDT 24 |
Finished | Jun 05 05:40:16 PM PDT 24 |
Peak memory | 214544 kb |
Host | smart-203fec1d-4afd-43a8-ba28-e35b6baea7cf |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378139700 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.1 378139700 |
Directory | /workspace/15.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.370845684 |
Short name | T344 |
Test name | |
Test status | |
Simulation time | 2072796518 ps |
CPU time | 5.65 seconds |
Started | Jun 05 05:39:54 PM PDT 24 |
Finished | Jun 05 05:40:01 PM PDT 24 |
Peak memory | 213408 kb |
Host | smart-672f32ca-2678-4cb6-a3b1-0f034d164900 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370845684 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.370845684 |
Directory | /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.3783537125 |
Short name | T108 |
Test name | |
Test status | |
Simulation time | 381853477 ps |
CPU time | 2.37 seconds |
Started | Jun 05 05:39:48 PM PDT 24 |
Finished | Jun 05 05:39:51 PM PDT 24 |
Peak memory | 213228 kb |
Host | smart-17b9c92a-1ac2-4ceb-9e13-166e49e3c27f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783537125 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.3783537125 |
Directory | /workspace/16.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.660470390 |
Short name | T374 |
Test name | |
Test status | |
Simulation time | 5200972917 ps |
CPU time | 5.21 seconds |
Started | Jun 05 05:39:48 PM PDT 24 |
Finished | Jun 05 05:39:54 PM PDT 24 |
Peak memory | 205092 kb |
Host | smart-217cf37d-6a49-4077-afda-020fe745dfd7 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660470390 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16. rv_dm_jtag_dmi_csr_bit_bash.660470390 |
Directory | /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.4173633123 |
Short name | T378 |
Test name | |
Test status | |
Simulation time | 7147337298 ps |
CPU time | 6.12 seconds |
Started | Jun 05 05:39:48 PM PDT 24 |
Finished | Jun 05 05:39:54 PM PDT 24 |
Peak memory | 205020 kb |
Host | smart-b11b1611-e412-4c36-bde7-040cff82f979 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173633123 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw. 4173633123 |
Directory | /workspace/16.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2092254778 |
Short name | T324 |
Test name | |
Test status | |
Simulation time | 249600361 ps |
CPU time | 0.75 seconds |
Started | Jun 05 05:39:49 PM PDT 24 |
Finished | Jun 05 05:39:50 PM PDT 24 |
Peak memory | 204704 kb |
Host | smart-7e5d4816-f512-49b1-bf87-947ea49993c9 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092254778 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw. 2092254778 |
Directory | /workspace/16.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.2380274458 |
Short name | T312 |
Test name | |
Test status | |
Simulation time | 224646619 ps |
CPU time | 1.8 seconds |
Started | Jun 05 05:39:48 PM PDT 24 |
Finished | Jun 05 05:39:51 PM PDT 24 |
Peak memory | 213344 kb |
Host | smart-293601e1-1e72-4f9c-8f06-7e1aa4397e13 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380274458 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.2380274458 |
Directory | /workspace/16.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.4238781004 |
Short name | T362 |
Test name | |
Test status | |
Simulation time | 3992764497 ps |
CPU time | 5.95 seconds |
Started | Jun 05 05:39:53 PM PDT 24 |
Finished | Jun 05 05:40:00 PM PDT 24 |
Peak memory | 221220 kb |
Host | smart-7879e57e-0884-452b-9ac5-da38888d4483 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238781004 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.4238781004 |
Directory | /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.1273639322 |
Short name | T412 |
Test name | |
Test status | |
Simulation time | 376634494 ps |
CPU time | 2.34 seconds |
Started | Jun 05 05:39:57 PM PDT 24 |
Finished | Jun 05 05:40:00 PM PDT 24 |
Peak memory | 213244 kb |
Host | smart-e09f4a24-7806-4b0e-b41d-332897044273 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273639322 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.1273639322 |
Directory | /workspace/17.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.2630685353 |
Short name | T386 |
Test name | |
Test status | |
Simulation time | 13137961585 ps |
CPU time | 39.6 seconds |
Started | Jun 05 05:39:57 PM PDT 24 |
Finished | Jun 05 05:40:38 PM PDT 24 |
Peak memory | 205064 kb |
Host | smart-383f5cc1-f985-47da-9449-37736c02c796 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630685353 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17 .rv_dm_jtag_dmi_csr_bit_bash.2630685353 |
Directory | /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.746594053 |
Short name | T280 |
Test name | |
Test status | |
Simulation time | 7833038823 ps |
CPU time | 10.15 seconds |
Started | Jun 05 05:39:53 PM PDT 24 |
Finished | Jun 05 05:40:03 PM PDT 24 |
Peak memory | 205044 kb |
Host | smart-fed0f46b-be15-422e-9a24-3d0d1729140e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746594053 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.746594053 |
Directory | /workspace/17.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2173350983 |
Short name | T275 |
Test name | |
Test status | |
Simulation time | 337059327 ps |
CPU time | 1.03 seconds |
Started | Jun 05 05:39:56 PM PDT 24 |
Finished | Jun 05 05:39:57 PM PDT 24 |
Peak memory | 204704 kb |
Host | smart-651a985b-1fac-4057-a6b8-33866aad287a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173350983 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw. 2173350983 |
Directory | /workspace/17.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3688015845 |
Short name | T81 |
Test name | |
Test status | |
Simulation time | 372455050 ps |
CPU time | 6.9 seconds |
Started | Jun 05 05:39:55 PM PDT 24 |
Finished | Jun 05 05:40:03 PM PDT 24 |
Peak memory | 205148 kb |
Host | smart-a7657ac2-9887-490c-a29d-a3c47e7ca12b |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688015845 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same _csr_outstanding.3688015845 |
Directory | /workspace/17.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.3077788094 |
Short name | T308 |
Test name | |
Test status | |
Simulation time | 186922045 ps |
CPU time | 2.49 seconds |
Started | Jun 05 05:39:55 PM PDT 24 |
Finished | Jun 05 05:39:58 PM PDT 24 |
Peak memory | 213388 kb |
Host | smart-9a33c40c-b529-4976-83ed-57889a5ad71a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077788094 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.3077788094 |
Directory | /workspace/17.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.334974063 |
Short name | T89 |
Test name | |
Test status | |
Simulation time | 2960204489 ps |
CPU time | 4.2 seconds |
Started | Jun 05 05:39:55 PM PDT 24 |
Finished | Jun 05 05:40:00 PM PDT 24 |
Peak memory | 218608 kb |
Host | smart-c1d05441-a43a-4632-903d-05fc9cc19a6c |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334974063 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.334974063 |
Directory | /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2562473632 |
Short name | T106 |
Test name | |
Test status | |
Simulation time | 60777751 ps |
CPU time | 2.21 seconds |
Started | Jun 05 05:39:55 PM PDT 24 |
Finished | Jun 05 05:39:58 PM PDT 24 |
Peak memory | 213256 kb |
Host | smart-3da73afc-24fe-4734-8377-95146eeaa892 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562473632 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.2562473632 |
Directory | /workspace/18.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.3672657703 |
Short name | T393 |
Test name | |
Test status | |
Simulation time | 59704705077 ps |
CPU time | 78.14 seconds |
Started | Jun 05 05:39:53 PM PDT 24 |
Finished | Jun 05 05:41:11 PM PDT 24 |
Peak memory | 205048 kb |
Host | smart-53a019d8-7841-44d5-9836-78a39dae0588 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672657703 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18 .rv_dm_jtag_dmi_csr_bit_bash.3672657703 |
Directory | /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2363571050 |
Short name | T395 |
Test name | |
Test status | |
Simulation time | 8446005036 ps |
CPU time | 12.45 seconds |
Started | Jun 05 05:39:57 PM PDT 24 |
Finished | Jun 05 05:40:11 PM PDT 24 |
Peak memory | 205052 kb |
Host | smart-90e3c455-2982-4424-98e7-b6556654142b |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363571050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw. 2363571050 |
Directory | /workspace/18.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.1073276545 |
Short name | T373 |
Test name | |
Test status | |
Simulation time | 453652039 ps |
CPU time | 1.71 seconds |
Started | Jun 05 05:39:56 PM PDT 24 |
Finished | Jun 05 05:39:58 PM PDT 24 |
Peak memory | 204916 kb |
Host | smart-3db1c66a-cce1-45ec-9467-adbf9871c305 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073276545 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw. 1073276545 |
Directory | /workspace/18.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.2853386853 |
Short name | T327 |
Test name | |
Test status | |
Simulation time | 476371232 ps |
CPU time | 4.43 seconds |
Started | Jun 05 05:39:56 PM PDT 24 |
Finished | Jun 05 05:40:01 PM PDT 24 |
Peak memory | 205112 kb |
Host | smart-47d66392-67bc-496e-ac9a-f793af0fa19b |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853386853 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same _csr_outstanding.2853386853 |
Directory | /workspace/18.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.72865113 |
Short name | T90 |
Test name | |
Test status | |
Simulation time | 313083966 ps |
CPU time | 4.05 seconds |
Started | Jun 05 05:39:54 PM PDT 24 |
Finished | Jun 05 05:39:59 PM PDT 24 |
Peak memory | 213340 kb |
Host | smart-134c9ed7-4f27-4b87-a121-a466bab18be6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72865113 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.72865113 |
Directory | /workspace/18.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.892586218 |
Short name | T316 |
Test name | |
Test status | |
Simulation time | 604602470 ps |
CPU time | 4.74 seconds |
Started | Jun 05 05:39:55 PM PDT 24 |
Finished | Jun 05 05:40:01 PM PDT 24 |
Peak memory | 221460 kb |
Host | smart-45297d4b-feda-4e15-ba51-da63a9e84f9e |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892586218 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.892586218 |
Directory | /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.1900827545 |
Short name | T107 |
Test name | |
Test status | |
Simulation time | 90997028 ps |
CPU time | 1.64 seconds |
Started | Jun 05 05:39:55 PM PDT 24 |
Finished | Jun 05 05:39:57 PM PDT 24 |
Peak memory | 213240 kb |
Host | smart-551ca40c-fc31-4d73-9995-8b3856b5cfe6 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900827545 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.1900827545 |
Directory | /workspace/19.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.3825527738 |
Short name | T332 |
Test name | |
Test status | |
Simulation time | 94373331 ps |
CPU time | 0.92 seconds |
Started | Jun 05 05:39:57 PM PDT 24 |
Finished | Jun 05 05:39:59 PM PDT 24 |
Peak memory | 204728 kb |
Host | smart-7b666ca9-948e-4c03-bd01-68404cd0de90 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825527738 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19 .rv_dm_jtag_dmi_csr_bit_bash.3825527738 |
Directory | /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.1651570985 |
Short name | T339 |
Test name | |
Test status | |
Simulation time | 1729842726 ps |
CPU time | 3.4 seconds |
Started | Jun 05 05:39:53 PM PDT 24 |
Finished | Jun 05 05:39:57 PM PDT 24 |
Peak memory | 204920 kb |
Host | smart-1f8c9676-2cb2-46c5-a0b7-5684728f294a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651570985 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw. 1651570985 |
Directory | /workspace/19.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.308580649 |
Short name | T69 |
Test name | |
Test status | |
Simulation time | 181613300 ps |
CPU time | 0.93 seconds |
Started | Jun 05 05:39:53 PM PDT 24 |
Finished | Jun 05 05:39:55 PM PDT 24 |
Peak memory | 204744 kb |
Host | smart-5c6e601d-4487-4d66-ae67-3ff535446927 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308580649 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.308580649 |
Directory | /workspace/19.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.4053881198 |
Short name | T405 |
Test name | |
Test status | |
Simulation time | 857637822 ps |
CPU time | 7.71 seconds |
Started | Jun 05 05:39:56 PM PDT 24 |
Finished | Jun 05 05:40:04 PM PDT 24 |
Peak memory | 205168 kb |
Host | smart-be16bda8-ea5f-4731-a098-4e137f2b4251 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053881198 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same _csr_outstanding.4053881198 |
Directory | /workspace/19.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.244231825 |
Short name | T357 |
Test name | |
Test status | |
Simulation time | 214764304 ps |
CPU time | 5.25 seconds |
Started | Jun 05 05:39:55 PM PDT 24 |
Finished | Jun 05 05:40:01 PM PDT 24 |
Peak memory | 213412 kb |
Host | smart-efdc3d8d-439e-4306-9128-df8b330fecd2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244231825 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.244231825 |
Directory | /workspace/19.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.837565068 |
Short name | T133 |
Test name | |
Test status | |
Simulation time | 2837896399 ps |
CPU time | 20.21 seconds |
Started | Jun 05 05:39:55 PM PDT 24 |
Finished | Jun 05 05:40:16 PM PDT 24 |
Peak memory | 213436 kb |
Host | smart-71010ab4-a5d9-4985-b13f-2547cb513be8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837565068 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.837565068 |
Directory | /workspace/19.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.529975558 |
Short name | T105 |
Test name | |
Test status | |
Simulation time | 2892160260 ps |
CPU time | 53.74 seconds |
Started | Jun 05 05:39:15 PM PDT 24 |
Finished | Jun 05 05:40:09 PM PDT 24 |
Peak memory | 205096 kb |
Host | smart-856c1561-d770-46d2-a5aa-d6843cad80ed |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529975558 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.529975558 |
Directory | /workspace/2.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.4082317863 |
Short name | T88 |
Test name | |
Test status | |
Simulation time | 162825493 ps |
CPU time | 2.58 seconds |
Started | Jun 05 05:39:15 PM PDT 24 |
Finished | Jun 05 05:39:19 PM PDT 24 |
Peak memory | 213380 kb |
Host | smart-3502f71a-a536-43b5-9f40-aecd1f47de97 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082317863 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.4082317863 |
Directory | /workspace/2.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.816431663 |
Short name | T123 |
Test name | |
Test status | |
Simulation time | 3514279253 ps |
CPU time | 5.35 seconds |
Started | Jun 05 05:39:25 PM PDT 24 |
Finished | Jun 05 05:39:31 PM PDT 24 |
Peak memory | 221380 kb |
Host | smart-b21dcc0e-0117-4d9b-b9db-4713591e4b70 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816431663 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.816431663 |
Directory | /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1619566221 |
Short name | T114 |
Test name | |
Test status | |
Simulation time | 205811631 ps |
CPU time | 2.18 seconds |
Started | Jun 05 05:39:16 PM PDT 24 |
Finished | Jun 05 05:39:19 PM PDT 24 |
Peak memory | 213220 kb |
Host | smart-377e9b47-bc8e-4033-a0db-f840b9b92099 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619566221 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.1619566221 |
Directory | /workspace/2.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.1791509311 |
Short name | T387 |
Test name | |
Test status | |
Simulation time | 29575187864 ps |
CPU time | 85.23 seconds |
Started | Jun 05 05:39:19 PM PDT 24 |
Finished | Jun 05 05:40:45 PM PDT 24 |
Peak memory | 205096 kb |
Host | smart-8aa88c67-eadc-4f6a-bef7-0c25a256abfa |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791509311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs r_aliasing.1791509311 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.101086853 |
Short name | T381 |
Test name | |
Test status | |
Simulation time | 15712375555 ps |
CPU time | 25.05 seconds |
Started | Jun 05 05:39:18 PM PDT 24 |
Finished | Jun 05 05:39:43 PM PDT 24 |
Peak memory | 205040 kb |
Host | smart-f43f3071-b442-4be5-b2b7-d3f22f1c3d67 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101086853 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.r v_dm_jtag_dmi_csr_bit_bash.101086853 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2095738656 |
Short name | T93 |
Test name | |
Test status | |
Simulation time | 5491333047 ps |
CPU time | 9.36 seconds |
Started | Jun 05 05:39:14 PM PDT 24 |
Finished | Jun 05 05:39:24 PM PDT 24 |
Peak memory | 205360 kb |
Host | smart-e99bacfe-d7dc-4261-b5a2-046b9059ea15 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095738656 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs r_hw_reset.2095738656 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1961429026 |
Short name | T304 |
Test name | |
Test status | |
Simulation time | 14583267789 ps |
CPU time | 39.07 seconds |
Started | Jun 05 05:39:14 PM PDT 24 |
Finished | Jun 05 05:39:54 PM PDT 24 |
Peak memory | 205068 kb |
Host | smart-92ceb615-36a1-427a-a779-d20dccfceb15 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961429026 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.1 961429026 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.4136538108 |
Short name | T318 |
Test name | |
Test status | |
Simulation time | 2912544852 ps |
CPU time | 3.39 seconds |
Started | Jun 05 05:39:17 PM PDT 24 |
Finished | Jun 05 05:39:21 PM PDT 24 |
Peak memory | 204780 kb |
Host | smart-79df8f36-3f39-4f36-bc5b-509ad542b20f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136538108 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_aliasing.4136538108 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1648202866 |
Short name | T283 |
Test name | |
Test status | |
Simulation time | 11965350574 ps |
CPU time | 33.88 seconds |
Started | Jun 05 05:39:16 PM PDT 24 |
Finished | Jun 05 05:39:51 PM PDT 24 |
Peak memory | 205016 kb |
Host | smart-54103fda-3dae-48ee-a036-e10143feee66 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648202866 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_bit_bash.1648202866 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.957609827 |
Short name | T340 |
Test name | |
Test status | |
Simulation time | 1230185241 ps |
CPU time | 1.18 seconds |
Started | Jun 05 05:39:15 PM PDT 24 |
Finished | Jun 05 05:39:17 PM PDT 24 |
Peak memory | 204720 kb |
Host | smart-82bf49de-f9f4-423f-a79e-059c7a69383a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957609827 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr _hw_reset.957609827 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.3858031452 |
Short name | T314 |
Test name | |
Test status | |
Simulation time | 1113350652 ps |
CPU time | 2.51 seconds |
Started | Jun 05 05:39:17 PM PDT 24 |
Finished | Jun 05 05:39:20 PM PDT 24 |
Peak memory | 204740 kb |
Host | smart-2067754e-1ec7-4a4c-9c0c-f0eb08fff51a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858031452 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.3 858031452 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1690143363 |
Short name | T399 |
Test name | |
Test status | |
Simulation time | 168994643 ps |
CPU time | 0.75 seconds |
Started | Jun 05 05:39:14 PM PDT 24 |
Finished | Jun 05 05:39:15 PM PDT 24 |
Peak memory | 204788 kb |
Host | smart-47f557a9-2640-4b10-81e8-74e2a26ce02e |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690143363 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par tial_access.1690143363 |
Directory | /workspace/2.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.3849173218 |
Short name | T294 |
Test name | |
Test status | |
Simulation time | 162811649 ps |
CPU time | 0.9 seconds |
Started | Jun 05 05:39:19 PM PDT 24 |
Finished | Jun 05 05:39:20 PM PDT 24 |
Peak memory | 204728 kb |
Host | smart-55fcac64-94d9-4a02-9622-e46cdad75cff |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849173218 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.3849173218 |
Directory | /workspace/2.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.1384170211 |
Short name | T98 |
Test name | |
Test status | |
Simulation time | 2090085017 ps |
CPU time | 7.65 seconds |
Started | Jun 05 05:39:15 PM PDT 24 |
Finished | Jun 05 05:39:24 PM PDT 24 |
Peak memory | 205116 kb |
Host | smart-cda2cceb-8fe7-46a6-8a14-61bc92fda0fa |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384170211 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_ csr_outstanding.1384170211 |
Directory | /workspace/2.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.3528409994 |
Short name | T341 |
Test name | |
Test status | |
Simulation time | 49349480749 ps |
CPU time | 75.26 seconds |
Started | Jun 05 05:39:13 PM PDT 24 |
Finished | Jun 05 05:40:29 PM PDT 24 |
Peak memory | 220584 kb |
Host | smart-00de64c4-2b1f-4881-a4c1-51d920b53ba5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528409994 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.3528409994 |
Directory | /workspace/2.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.4210671760 |
Short name | T73 |
Test name | |
Test status | |
Simulation time | 512480583 ps |
CPU time | 3.66 seconds |
Started | Jun 05 05:39:19 PM PDT 24 |
Finished | Jun 05 05:39:23 PM PDT 24 |
Peak memory | 213416 kb |
Host | smart-3de71d92-7b15-4e11-923f-3c2d62d11e0a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210671760 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.4210671760 |
Directory | /workspace/2.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.3868449642 |
Short name | T402 |
Test name | |
Test status | |
Simulation time | 815389066 ps |
CPU time | 26.92 seconds |
Started | Jun 05 05:39:25 PM PDT 24 |
Finished | Jun 05 05:39:52 PM PDT 24 |
Peak memory | 205060 kb |
Host | smart-e9914dbc-c352-4139-add4-2960497c7b4c |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868449642 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 3.rv_dm_csr_aliasing.3868449642 |
Directory | /workspace/3.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.2583531249 |
Short name | T354 |
Test name | |
Test status | |
Simulation time | 2858454985 ps |
CPU time | 27.43 seconds |
Started | Jun 05 05:39:26 PM PDT 24 |
Finished | Jun 05 05:39:54 PM PDT 24 |
Peak memory | 205068 kb |
Host | smart-b6e70d4b-1dc9-4198-a51b-2e73ce926c89 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583531249 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.2583531249 |
Directory | /workspace/3.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.489163540 |
Short name | T100 |
Test name | |
Test status | |
Simulation time | 273600518 ps |
CPU time | 2.79 seconds |
Started | Jun 05 05:39:24 PM PDT 24 |
Finished | Jun 05 05:39:27 PM PDT 24 |
Peak memory | 213340 kb |
Host | smart-c0b1fc4a-3ed5-45c0-a66d-71913d9892fc |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489163540 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.489163540 |
Directory | /workspace/3.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1377981846 |
Short name | T52 |
Test name | |
Test status | |
Simulation time | 1602341433 ps |
CPU time | 2.62 seconds |
Started | Jun 05 05:39:29 PM PDT 24 |
Finished | Jun 05 05:39:33 PM PDT 24 |
Peak memory | 221516 kb |
Host | smart-9c0ac74d-f5c6-491b-abd1-37fe62e750b0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377981846 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.1377981846 |
Directory | /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.31873266 |
Short name | T84 |
Test name | |
Test status | |
Simulation time | 138103170 ps |
CPU time | 2.34 seconds |
Started | Jun 05 05:39:24 PM PDT 24 |
Finished | Jun 05 05:39:27 PM PDT 24 |
Peak memory | 213292 kb |
Host | smart-e87a604c-a44f-4859-9928-0affd8184536 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31873266 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.31873266 |
Directory | /workspace/3.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1747104930 |
Short name | T298 |
Test name | |
Test status | |
Simulation time | 15813887844 ps |
CPU time | 11.36 seconds |
Started | Jun 05 05:39:29 PM PDT 24 |
Finished | Jun 05 05:39:41 PM PDT 24 |
Peak memory | 205044 kb |
Host | smart-81e183f5-4d3a-4ccb-978a-d196b5b4bc3e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747104930 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3. rv_dm_jtag_dmi_csr_bit_bash.1747104930 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2261972222 |
Short name | T92 |
Test name | |
Test status | |
Simulation time | 4910302020 ps |
CPU time | 14.71 seconds |
Started | Jun 05 05:39:25 PM PDT 24 |
Finished | Jun 05 05:39:41 PM PDT 24 |
Peak memory | 205196 kb |
Host | smart-9ed0c4a9-c807-4157-a0b1-7d7df098c605 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261972222 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs r_hw_reset.2261972222 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3256799618 |
Short name | T272 |
Test name | |
Test status | |
Simulation time | 3143553237 ps |
CPU time | 3.3 seconds |
Started | Jun 05 05:39:27 PM PDT 24 |
Finished | Jun 05 05:39:31 PM PDT 24 |
Peak memory | 205000 kb |
Host | smart-273ae2e0-abd4-47d3-83c8-c62010dea6eb |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256799618 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.3 256799618 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.130763369 |
Short name | T278 |
Test name | |
Test status | |
Simulation time | 298579164 ps |
CPU time | 0.88 seconds |
Started | Jun 05 05:39:28 PM PDT 24 |
Finished | Jun 05 05:39:29 PM PDT 24 |
Peak memory | 204724 kb |
Host | smart-23201ecc-8397-46e2-b1cb-085b3aa4039a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130763369 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr _aliasing.130763369 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.166710354 |
Short name | T326 |
Test name | |
Test status | |
Simulation time | 8165928003 ps |
CPU time | 11.29 seconds |
Started | Jun 05 05:39:24 PM PDT 24 |
Finished | Jun 05 05:39:36 PM PDT 24 |
Peak memory | 204996 kb |
Host | smart-9fd689fc-84a2-4215-9daf-42ddad02634b |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166710354 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr _bit_bash.166710354 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3321626533 |
Short name | T300 |
Test name | |
Test status | |
Simulation time | 238632950 ps |
CPU time | 1.03 seconds |
Started | Jun 05 05:39:27 PM PDT 24 |
Finished | Jun 05 05:39:29 PM PDT 24 |
Peak memory | 204788 kb |
Host | smart-6b370422-119b-4f1a-bee9-d4482946758b |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321626533 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_hw_reset.3321626533 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1255176647 |
Short name | T385 |
Test name | |
Test status | |
Simulation time | 856811470 ps |
CPU time | 2.96 seconds |
Started | Jun 05 05:39:22 PM PDT 24 |
Finished | Jun 05 05:39:26 PM PDT 24 |
Peak memory | 204672 kb |
Host | smart-9cf3e40b-0dd9-467a-843c-e2bb39cfdb4e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255176647 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.1 255176647 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.3180820301 |
Short name | T356 |
Test name | |
Test status | |
Simulation time | 41112637 ps |
CPU time | 0.72 seconds |
Started | Jun 05 05:39:25 PM PDT 24 |
Finished | Jun 05 05:39:26 PM PDT 24 |
Peak memory | 204772 kb |
Host | smart-ec6403da-dc3a-4419-b728-102361d94c60 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180820301 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par tial_access.3180820301 |
Directory | /workspace/3.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.3037124044 |
Short name | T301 |
Test name | |
Test status | |
Simulation time | 85735590 ps |
CPU time | 0.72 seconds |
Started | Jun 05 05:39:21 PM PDT 24 |
Finished | Jun 05 05:39:23 PM PDT 24 |
Peak memory | 204728 kb |
Host | smart-8481553e-4881-42f8-847f-ab7d2c28ffb9 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037124044 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.3037124044 |
Directory | /workspace/3.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.1331296269 |
Short name | T351 |
Test name | |
Test status | |
Simulation time | 5741859208 ps |
CPU time | 9.53 seconds |
Started | Jun 05 05:39:25 PM PDT 24 |
Finished | Jun 05 05:39:35 PM PDT 24 |
Peak memory | 205232 kb |
Host | smart-171bc9c8-e032-43a8-bd64-3149efa6b44d |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331296269 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_ csr_outstanding.1331296269 |
Directory | /workspace/3.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.1069456906 |
Short name | T47 |
Test name | |
Test status | |
Simulation time | 81658130025 ps |
CPU time | 47.65 seconds |
Started | Jun 05 05:39:22 PM PDT 24 |
Finished | Jun 05 05:40:11 PM PDT 24 |
Peak memory | 225376 kb |
Host | smart-298401bd-0d15-4891-9ad3-1c29739ab120 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069456906 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.1069456906 |
Directory | /workspace/3.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2481922690 |
Short name | T363 |
Test name | |
Test status | |
Simulation time | 2707269493 ps |
CPU time | 5.43 seconds |
Started | Jun 05 05:39:27 PM PDT 24 |
Finished | Jun 05 05:39:33 PM PDT 24 |
Peak memory | 213488 kb |
Host | smart-ab79eead-e198-481c-b15c-710e4f6afe7f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481922690 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.2481922690 |
Directory | /workspace/3.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2537127797 |
Short name | T126 |
Test name | |
Test status | |
Simulation time | 2152746013 ps |
CPU time | 18.3 seconds |
Started | Jun 05 05:39:25 PM PDT 24 |
Finished | Jun 05 05:39:43 PM PDT 24 |
Peak memory | 213392 kb |
Host | smart-51f62dc8-b74e-4de6-905e-296de99ed4d5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537127797 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.2537127797 |
Directory | /workspace/3.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.3066166862 |
Short name | T109 |
Test name | |
Test status | |
Simulation time | 3310948446 ps |
CPU time | 54.73 seconds |
Started | Jun 05 05:39:29 PM PDT 24 |
Finished | Jun 05 05:40:24 PM PDT 24 |
Peak memory | 213284 kb |
Host | smart-ce7d2fb5-ae06-4176-be91-eed103f0d88d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066166862 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.3066166862 |
Directory | /workspace/4.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.3307635225 |
Short name | T360 |
Test name | |
Test status | |
Simulation time | 196071779 ps |
CPU time | 1.73 seconds |
Started | Jun 05 05:39:32 PM PDT 24 |
Finished | Jun 05 05:39:34 PM PDT 24 |
Peak memory | 213264 kb |
Host | smart-41168398-9757-45f9-bcb9-432454753c7b |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307635225 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.3307635225 |
Directory | /workspace/4.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.744769 |
Short name | T377 |
Test name | |
Test status | |
Simulation time | 2798186382 ps |
CPU time | 4.4 seconds |
Started | Jun 05 05:39:32 PM PDT 24 |
Finished | Jun 05 05:39:37 PM PDT 24 |
Peak memory | 221536 kb |
Host | smart-af780a7e-a9fd-4c61-89f9-6b9313728cb4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744769 -assert nopostproc +UVM_TESTNAME=rv_ dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.744769 |
Directory | /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.1882723684 |
Short name | T330 |
Test name | |
Test status | |
Simulation time | 503878151 ps |
CPU time | 2.27 seconds |
Started | Jun 05 05:39:30 PM PDT 24 |
Finished | Jun 05 05:39:33 PM PDT 24 |
Peak memory | 213288 kb |
Host | smart-ac320656-175c-4f92-b67f-d912b325977c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882723684 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.1882723684 |
Directory | /workspace/4.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.3211778913 |
Short name | T274 |
Test name | |
Test status | |
Simulation time | 55793354275 ps |
CPU time | 52.63 seconds |
Started | Jun 05 05:39:24 PM PDT 24 |
Finished | Jun 05 05:40:17 PM PDT 24 |
Peak memory | 205068 kb |
Host | smart-fc0f4bd0-529d-4289-be41-e76606b7ef27 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211778913 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs r_aliasing.3211778913 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.2947462028 |
Short name | T268 |
Test name | |
Test status | |
Simulation time | 119602557151 ps |
CPU time | 102.73 seconds |
Started | Jun 05 05:39:21 PM PDT 24 |
Finished | Jun 05 05:41:04 PM PDT 24 |
Peak memory | 205052 kb |
Host | smart-78a9c380-2d52-4fd1-89f3-f86f72c572e5 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947462028 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4. rv_dm_jtag_dmi_csr_bit_bash.2947462028 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.1063019106 |
Short name | T94 |
Test name | |
Test status | |
Simulation time | 10418906153 ps |
CPU time | 8.86 seconds |
Started | Jun 05 05:39:25 PM PDT 24 |
Finished | Jun 05 05:39:35 PM PDT 24 |
Peak memory | 205160 kb |
Host | smart-80ddb6bd-8a7f-4d36-9e09-bb52a148622a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063019106 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs r_hw_reset.1063019106 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.1676618635 |
Short name | T315 |
Test name | |
Test status | |
Simulation time | 6091179599 ps |
CPU time | 10.92 seconds |
Started | Jun 05 05:39:23 PM PDT 24 |
Finished | Jun 05 05:39:35 PM PDT 24 |
Peak memory | 205056 kb |
Host | smart-df7f3841-a22d-404a-8881-e02a617491f3 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676618635 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.1 676618635 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.4180044523 |
Short name | T286 |
Test name | |
Test status | |
Simulation time | 2933731157 ps |
CPU time | 4.77 seconds |
Started | Jun 05 05:39:26 PM PDT 24 |
Finished | Jun 05 05:39:32 PM PDT 24 |
Peak memory | 204772 kb |
Host | smart-65f2edab-4adc-461a-a838-16abe3681486 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180044523 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs r_aliasing.4180044523 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.4091575400 |
Short name | T345 |
Test name | |
Test status | |
Simulation time | 5093992100 ps |
CPU time | 15.67 seconds |
Started | Jun 05 05:39:27 PM PDT 24 |
Finished | Jun 05 05:39:43 PM PDT 24 |
Peak memory | 205036 kb |
Host | smart-a50a2598-4adb-43cd-b4da-609f4c60ac8d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091575400 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs r_bit_bash.4091575400 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.4216087086 |
Short name | T391 |
Test name | |
Test status | |
Simulation time | 674630798 ps |
CPU time | 2.3 seconds |
Started | Jun 05 05:39:25 PM PDT 24 |
Finished | Jun 05 05:39:28 PM PDT 24 |
Peak memory | 204768 kb |
Host | smart-2852901e-6c22-4655-9120-53d5814c6263 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216087086 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs r_hw_reset.4216087086 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.1103334332 |
Short name | T336 |
Test name | |
Test status | |
Simulation time | 780418689 ps |
CPU time | 2.7 seconds |
Started | Jun 05 05:39:23 PM PDT 24 |
Finished | Jun 05 05:39:26 PM PDT 24 |
Peak memory | 204720 kb |
Host | smart-0dcb5a27-4b46-4ae8-8579-658c21dcfa68 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103334332 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.1 103334332 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1098996388 |
Short name | T289 |
Test name | |
Test status | |
Simulation time | 38475232 ps |
CPU time | 0.73 seconds |
Started | Jun 05 05:39:30 PM PDT 24 |
Finished | Jun 05 05:39:31 PM PDT 24 |
Peak memory | 204784 kb |
Host | smart-4385fa42-9e4e-44de-9fcd-470d96941319 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098996388 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par tial_access.1098996388 |
Directory | /workspace/4.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.2159769876 |
Short name | T361 |
Test name | |
Test status | |
Simulation time | 78865576 ps |
CPU time | 0.69 seconds |
Started | Jun 05 05:39:30 PM PDT 24 |
Finished | Jun 05 05:39:32 PM PDT 24 |
Peak memory | 204736 kb |
Host | smart-d4d651e9-7938-451e-82ce-291ed2d3344f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159769876 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.2159769876 |
Directory | /workspace/4.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3642825459 |
Short name | T115 |
Test name | |
Test status | |
Simulation time | 632262138 ps |
CPU time | 7.98 seconds |
Started | Jun 05 05:39:30 PM PDT 24 |
Finished | Jun 05 05:39:39 PM PDT 24 |
Peak memory | 205096 kb |
Host | smart-a2abf0ff-dbbc-4b91-972e-08872fe88d91 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642825459 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_ csr_outstanding.3642825459 |
Directory | /workspace/4.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.831563093 |
Short name | T404 |
Test name | |
Test status | |
Simulation time | 56102712679 ps |
CPU time | 91.8 seconds |
Started | Jun 05 05:39:28 PM PDT 24 |
Finished | Jun 05 05:41:01 PM PDT 24 |
Peak memory | 221980 kb |
Host | smart-1843482c-0d6b-4c4d-af51-12c40790b21a |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831563093 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.831563093 |
Directory | /workspace/4.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.845942620 |
Short name | T124 |
Test name | |
Test status | |
Simulation time | 165078596 ps |
CPU time | 2.34 seconds |
Started | Jun 05 05:39:29 PM PDT 24 |
Finished | Jun 05 05:39:32 PM PDT 24 |
Peak memory | 213436 kb |
Host | smart-c51a8c90-e90b-409d-a912-7c9a9024d7ad |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845942620 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.845942620 |
Directory | /workspace/4.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.2910922021 |
Short name | T130 |
Test name | |
Test status | |
Simulation time | 6645471852 ps |
CPU time | 24.98 seconds |
Started | Jun 05 05:39:30 PM PDT 24 |
Finished | Jun 05 05:39:55 PM PDT 24 |
Peak memory | 213456 kb |
Host | smart-f068829a-7a00-4917-b43e-58b4426197ab |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910922021 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.2910922021 |
Directory | /workspace/4.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3053255031 |
Short name | T408 |
Test name | |
Test status | |
Simulation time | 533644841 ps |
CPU time | 4.41 seconds |
Started | Jun 05 05:39:32 PM PDT 24 |
Finished | Jun 05 05:39:37 PM PDT 24 |
Peak memory | 220900 kb |
Host | smart-9a6b19a7-ab7f-47a2-970c-ac3b17ce644d |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053255031 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.3053255031 |
Directory | /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.802872405 |
Short name | T370 |
Test name | |
Test status | |
Simulation time | 156337717 ps |
CPU time | 2.44 seconds |
Started | Jun 05 05:39:30 PM PDT 24 |
Finished | Jun 05 05:39:34 PM PDT 24 |
Peak memory | 213224 kb |
Host | smart-6556b46c-9b94-4cc9-9acb-c5cd3adb2f16 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802872405 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.802872405 |
Directory | /workspace/5.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.3200693302 |
Short name | T355 |
Test name | |
Test status | |
Simulation time | 36078094779 ps |
CPU time | 51.42 seconds |
Started | Jun 05 05:39:29 PM PDT 24 |
Finished | Jun 05 05:40:21 PM PDT 24 |
Peak memory | 205020 kb |
Host | smart-f933dcdc-b5e4-418d-891e-0a60864594d8 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200693302 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5. rv_dm_jtag_dmi_csr_bit_bash.3200693302 |
Directory | /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.501307091 |
Short name | T383 |
Test name | |
Test status | |
Simulation time | 8381094855 ps |
CPU time | 22.41 seconds |
Started | Jun 05 05:39:31 PM PDT 24 |
Finished | Jun 05 05:39:54 PM PDT 24 |
Peak memory | 205068 kb |
Host | smart-5ceaf276-e9be-415e-bc04-4474139ddc11 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501307091 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.501307091 |
Directory | /workspace/5.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.645876514 |
Short name | T70 |
Test name | |
Test status | |
Simulation time | 486895689 ps |
CPU time | 1.82 seconds |
Started | Jun 05 05:39:28 PM PDT 24 |
Finished | Jun 05 05:39:30 PM PDT 24 |
Peak memory | 204688 kb |
Host | smart-a77c5051-d1a6-4c52-83b0-90137960cdf2 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645876514 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.645876514 |
Directory | /workspace/5.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.3507674905 |
Short name | T295 |
Test name | |
Test status | |
Simulation time | 1716718819 ps |
CPU time | 7.74 seconds |
Started | Jun 05 05:39:31 PM PDT 24 |
Finished | Jun 05 05:39:39 PM PDT 24 |
Peak memory | 205132 kb |
Host | smart-ff5af5fe-c823-428c-8173-a3b2a0a00d15 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507674905 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_ csr_outstanding.3507674905 |
Directory | /workspace/5.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.2908255825 |
Short name | T135 |
Test name | |
Test status | |
Simulation time | 19523627232 ps |
CPU time | 60.41 seconds |
Started | Jun 05 05:39:31 PM PDT 24 |
Finished | Jun 05 05:40:32 PM PDT 24 |
Peak memory | 221468 kb |
Host | smart-c26644a0-9e36-4e63-8c25-c4a28e424008 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908255825 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.2908255825 |
Directory | /workspace/5.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.4148430037 |
Short name | T76 |
Test name | |
Test status | |
Simulation time | 176886487 ps |
CPU time | 2.98 seconds |
Started | Jun 05 05:39:30 PM PDT 24 |
Finished | Jun 05 05:39:34 PM PDT 24 |
Peak memory | 213424 kb |
Host | smart-60788461-759a-4335-a698-eea1567ccd8d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148430037 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.4148430037 |
Directory | /workspace/5.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2969059631 |
Short name | T352 |
Test name | |
Test status | |
Simulation time | 3726745758 ps |
CPU time | 18.72 seconds |
Started | Jun 05 05:39:33 PM PDT 24 |
Finished | Jun 05 05:39:52 PM PDT 24 |
Peak memory | 213340 kb |
Host | smart-b57f95e1-5579-44d4-9c1c-c36b3d1d7564 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969059631 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.2969059631 |
Directory | /workspace/5.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.1711005210 |
Short name | T75 |
Test name | |
Test status | |
Simulation time | 2979463198 ps |
CPU time | 6.72 seconds |
Started | Jun 05 05:39:27 PM PDT 24 |
Finished | Jun 05 05:39:34 PM PDT 24 |
Peak memory | 218420 kb |
Host | smart-c1ceba5b-761e-42f5-9e49-f1b7c04e4cd1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711005210 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.1711005210 |
Directory | /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.595046905 |
Short name | T86 |
Test name | |
Test status | |
Simulation time | 179256771 ps |
CPU time | 1.83 seconds |
Started | Jun 05 05:39:30 PM PDT 24 |
Finished | Jun 05 05:39:32 PM PDT 24 |
Peak memory | 213236 kb |
Host | smart-c19650af-aa52-4afb-935f-40e2f350c526 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595046905 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.595046905 |
Directory | /workspace/6.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.2570358912 |
Short name | T389 |
Test name | |
Test status | |
Simulation time | 113584238 ps |
CPU time | 0.83 seconds |
Started | Jun 05 05:39:32 PM PDT 24 |
Finished | Jun 05 05:39:33 PM PDT 24 |
Peak memory | 204684 kb |
Host | smart-fd49b1ca-618b-45be-b9be-67b2709097ad |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570358912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6. rv_dm_jtag_dmi_csr_bit_bash.2570358912 |
Directory | /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2906633583 |
Short name | T328 |
Test name | |
Test status | |
Simulation time | 12919218562 ps |
CPU time | 35.85 seconds |
Started | Jun 05 05:39:30 PM PDT 24 |
Finished | Jun 05 05:40:07 PM PDT 24 |
Peak memory | 205040 kb |
Host | smart-ded86afe-22a3-4c49-9dbf-81d4f7cdd7ec |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906633583 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.2 906633583 |
Directory | /workspace/6.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.4291350486 |
Short name | T303 |
Test name | |
Test status | |
Simulation time | 456472261 ps |
CPU time | 1.56 seconds |
Started | Jun 05 05:39:32 PM PDT 24 |
Finished | Jun 05 05:39:34 PM PDT 24 |
Peak memory | 204724 kb |
Host | smart-189467ac-25f3-4c04-81dc-49abc0a465bb |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291350486 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.4 291350486 |
Directory | /workspace/6.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.452165151 |
Short name | T322 |
Test name | |
Test status | |
Simulation time | 63078231665 ps |
CPU time | 50.6 seconds |
Started | Jun 05 05:39:31 PM PDT 24 |
Finished | Jun 05 05:40:22 PM PDT 24 |
Peak memory | 221988 kb |
Host | smart-1e8dccd9-a3a4-459e-889e-c85d4c2dd598 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452165151 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.452165151 |
Directory | /workspace/6.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.866899067 |
Short name | T134 |
Test name | |
Test status | |
Simulation time | 1159578981 ps |
CPU time | 9.79 seconds |
Started | Jun 05 05:39:29 PM PDT 24 |
Finished | Jun 05 05:39:39 PM PDT 24 |
Peak memory | 213580 kb |
Host | smart-627ff292-b41f-420d-af56-2189d9ca8cdf |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866899067 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.866899067 |
Directory | /workspace/6.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2407977006 |
Short name | T364 |
Test name | |
Test status | |
Simulation time | 131694790 ps |
CPU time | 2.33 seconds |
Started | Jun 05 05:39:29 PM PDT 24 |
Finished | Jun 05 05:39:32 PM PDT 24 |
Peak memory | 221516 kb |
Host | smart-044e109d-6db0-4ae5-893a-9fa03339f021 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407977006 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.2407977006 |
Directory | /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.2113579108 |
Short name | T110 |
Test name | |
Test status | |
Simulation time | 37872735 ps |
CPU time | 1.44 seconds |
Started | Jun 05 05:39:30 PM PDT 24 |
Finished | Jun 05 05:39:32 PM PDT 24 |
Peak memory | 213260 kb |
Host | smart-b9a98b8c-2fa2-47e0-94a3-c7fe6a4854ee |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113579108 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.2113579108 |
Directory | /workspace/7.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.348814223 |
Short name | T311 |
Test name | |
Test status | |
Simulation time | 11808510179 ps |
CPU time | 34.83 seconds |
Started | Jun 05 05:39:32 PM PDT 24 |
Finished | Jun 05 05:40:08 PM PDT 24 |
Peak memory | 205024 kb |
Host | smart-e0b2f392-1d17-4826-80ae-6817b4dd3f21 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348814223 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.r v_dm_jtag_dmi_csr_bit_bash.348814223 |
Directory | /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3536035874 |
Short name | T264 |
Test name | |
Test status | |
Simulation time | 1157377587 ps |
CPU time | 4.01 seconds |
Started | Jun 05 05:39:29 PM PDT 24 |
Finished | Jun 05 05:39:34 PM PDT 24 |
Peak memory | 204944 kb |
Host | smart-e8d5edca-db74-43f0-9b3c-73ac30175489 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536035874 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.3 536035874 |
Directory | /workspace/7.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.443058061 |
Short name | T335 |
Test name | |
Test status | |
Simulation time | 98574272 ps |
CPU time | 0.94 seconds |
Started | Jun 05 05:39:29 PM PDT 24 |
Finished | Jun 05 05:39:31 PM PDT 24 |
Peak memory | 204716 kb |
Host | smart-4bbf07b1-3f06-4afc-8d74-551830a09ab7 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443058061 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.443058061 |
Directory | /workspace/7.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.865761934 |
Short name | T55 |
Test name | |
Test status | |
Simulation time | 371059229 ps |
CPU time | 4.7 seconds |
Started | Jun 05 05:39:30 PM PDT 24 |
Finished | Jun 05 05:39:36 PM PDT 24 |
Peak memory | 205160 kb |
Host | smart-c15ffb66-e3b8-426c-b882-54aaacb351ad |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865761934 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_c sr_outstanding.865761934 |
Directory | /workspace/7.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.283599977 |
Short name | T347 |
Test name | |
Test status | |
Simulation time | 82659061410 ps |
CPU time | 75.66 seconds |
Started | Jun 05 05:39:31 PM PDT 24 |
Finished | Jun 05 05:40:48 PM PDT 24 |
Peak memory | 223776 kb |
Host | smart-7bac1377-4155-498c-bf8a-c3a93e634efe |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283599977 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.283599977 |
Directory | /workspace/7.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.4153932493 |
Short name | T406 |
Test name | |
Test status | |
Simulation time | 326797133 ps |
CPU time | 5.19 seconds |
Started | Jun 05 05:39:28 PM PDT 24 |
Finished | Jun 05 05:39:34 PM PDT 24 |
Peak memory | 213408 kb |
Host | smart-fb0f04fa-4945-4350-aefd-b81f78d88d2a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153932493 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.4153932493 |
Directory | /workspace/7.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.4273749770 |
Short name | T132 |
Test name | |
Test status | |
Simulation time | 4486297729 ps |
CPU time | 11.19 seconds |
Started | Jun 05 05:39:29 PM PDT 24 |
Finished | Jun 05 05:39:41 PM PDT 24 |
Peak memory | 213404 kb |
Host | smart-6889d0dc-339d-4466-9d8e-ed0b88837c84 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273749770 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.4273749770 |
Directory | /workspace/7.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.937554446 |
Short name | T337 |
Test name | |
Test status | |
Simulation time | 352858447 ps |
CPU time | 2.7 seconds |
Started | Jun 05 05:39:40 PM PDT 24 |
Finished | Jun 05 05:39:44 PM PDT 24 |
Peak memory | 218684 kb |
Host | smart-88ca26b8-c61c-43af-9816-fc3c9dcccdfc |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937554446 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.937554446 |
Directory | /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1465622497 |
Short name | T287 |
Test name | |
Test status | |
Simulation time | 142460874 ps |
CPU time | 2.46 seconds |
Started | Jun 05 05:39:42 PM PDT 24 |
Finished | Jun 05 05:39:45 PM PDT 24 |
Peak memory | 213260 kb |
Host | smart-0f42c48e-f7f2-42cc-b71a-85d986d10b64 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465622497 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.1465622497 |
Directory | /workspace/8.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.2145943570 |
Short name | T398 |
Test name | |
Test status | |
Simulation time | 64308330832 ps |
CPU time | 42.69 seconds |
Started | Jun 05 05:39:31 PM PDT 24 |
Finished | Jun 05 05:40:14 PM PDT 24 |
Peak memory | 204996 kb |
Host | smart-f0b8fd54-d3ba-494f-8d09-78955125e65f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145943570 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8. rv_dm_jtag_dmi_csr_bit_bash.2145943570 |
Directory | /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3692424949 |
Short name | T265 |
Test name | |
Test status | |
Simulation time | 2768253348 ps |
CPU time | 8.85 seconds |
Started | Jun 05 05:39:31 PM PDT 24 |
Finished | Jun 05 05:39:40 PM PDT 24 |
Peak memory | 204996 kb |
Host | smart-a544f3d6-4b29-43e9-bd26-88894a07105f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692424949 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.3 692424949 |
Directory | /workspace/8.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.1057271617 |
Short name | T317 |
Test name | |
Test status | |
Simulation time | 363785794 ps |
CPU time | 1.3 seconds |
Started | Jun 05 05:39:31 PM PDT 24 |
Finished | Jun 05 05:39:33 PM PDT 24 |
Peak memory | 204732 kb |
Host | smart-6d9de80c-6fad-4f60-88a3-ef70207202aa |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057271617 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.1 057271617 |
Directory | /workspace/8.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.1847090474 |
Short name | T343 |
Test name | |
Test status | |
Simulation time | 478985199 ps |
CPU time | 7.6 seconds |
Started | Jun 05 05:39:41 PM PDT 24 |
Finished | Jun 05 05:39:49 PM PDT 24 |
Peak memory | 205088 kb |
Host | smart-b855caa2-a3d7-41a3-bc71-c216035b8d46 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847090474 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_ csr_outstanding.1847090474 |
Directory | /workspace/8.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2493001404 |
Short name | T74 |
Test name | |
Test status | |
Simulation time | 315936986 ps |
CPU time | 4.51 seconds |
Started | Jun 05 05:39:40 PM PDT 24 |
Finished | Jun 05 05:39:45 PM PDT 24 |
Peak memory | 213360 kb |
Host | smart-96e86567-e866-4f92-a3cd-6ab204a748c6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493001404 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.2493001404 |
Directory | /workspace/8.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3568022946 |
Short name | T77 |
Test name | |
Test status | |
Simulation time | 371541004 ps |
CPU time | 2.16 seconds |
Started | Jun 05 05:39:39 PM PDT 24 |
Finished | Jun 05 05:39:42 PM PDT 24 |
Peak memory | 215188 kb |
Host | smart-f8257653-06f8-4d83-9db9-501099143bb9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568022946 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.3568022946 |
Directory | /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.680000354 |
Short name | T369 |
Test name | |
Test status | |
Simulation time | 482072662 ps |
CPU time | 1.71 seconds |
Started | Jun 05 05:39:39 PM PDT 24 |
Finished | Jun 05 05:39:41 PM PDT 24 |
Peak memory | 213236 kb |
Host | smart-fb724577-07d6-4239-82db-51fab2be38ce |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680000354 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.680000354 |
Directory | /workspace/9.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.3275756568 |
Short name | T397 |
Test name | |
Test status | |
Simulation time | 24434888774 ps |
CPU time | 66.74 seconds |
Started | Jun 05 05:39:39 PM PDT 24 |
Finished | Jun 05 05:40:47 PM PDT 24 |
Peak memory | 205040 kb |
Host | smart-c995c991-91b8-4c52-9673-690b83dd1529 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275756568 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9. rv_dm_jtag_dmi_csr_bit_bash.3275756568 |
Directory | /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3940158876 |
Short name | T338 |
Test name | |
Test status | |
Simulation time | 2380239590 ps |
CPU time | 7.15 seconds |
Started | Jun 05 05:39:39 PM PDT 24 |
Finished | Jun 05 05:39:47 PM PDT 24 |
Peak memory | 204976 kb |
Host | smart-8c02b4a7-ab68-45ab-b9bc-88fd8be855fb |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940158876 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.3 940158876 |
Directory | /workspace/9.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.3480909971 |
Short name | T279 |
Test name | |
Test status | |
Simulation time | 135194503 ps |
CPU time | 0.74 seconds |
Started | Jun 05 05:39:39 PM PDT 24 |
Finished | Jun 05 05:39:41 PM PDT 24 |
Peak memory | 204704 kb |
Host | smart-9183e91a-0e3f-4c2f-b2b2-e4ff56be6a9c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480909971 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.3 480909971 |
Directory | /workspace/9.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.507737906 |
Short name | T101 |
Test name | |
Test status | |
Simulation time | 413803131 ps |
CPU time | 3.57 seconds |
Started | Jun 05 05:39:39 PM PDT 24 |
Finished | Jun 05 05:39:44 PM PDT 24 |
Peak memory | 205180 kb |
Host | smart-3cfe9786-5a25-4594-b3c0-e7447bcb894a |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507737906 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_c sr_outstanding.507737906 |
Directory | /workspace/9.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.3764643837 |
Short name | T331 |
Test name | |
Test status | |
Simulation time | 76067066560 ps |
CPU time | 29.22 seconds |
Started | Jun 05 05:39:40 PM PDT 24 |
Finished | Jun 05 05:40:11 PM PDT 24 |
Peak memory | 221556 kb |
Host | smart-e27a35d3-da78-43af-985a-1073184adf30 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764643837 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.3764643837 |
Directory | /workspace/9.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.686013156 |
Short name | T292 |
Test name | |
Test status | |
Simulation time | 234307449 ps |
CPU time | 3.28 seconds |
Started | Jun 05 05:39:39 PM PDT 24 |
Finished | Jun 05 05:39:43 PM PDT 24 |
Peak memory | 213408 kb |
Host | smart-324acad8-6803-4a9e-8f66-09976dd19188 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686013156 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.686013156 |
Directory | /workspace/9.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2016539242 |
Short name | T127 |
Test name | |
Test status | |
Simulation time | 2573293286 ps |
CPU time | 11.86 seconds |
Started | Jun 05 05:39:38 PM PDT 24 |
Finished | Jun 05 05:39:50 PM PDT 24 |
Peak memory | 213364 kb |
Host | smart-3f2df94b-5b9e-4bfa-adc4-cc633b993fc8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016539242 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.2016539242 |
Directory | /workspace/9.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.rv_dm_alert_test.2999400917 |
Short name | T170 |
Test name | |
Test status | |
Simulation time | 60907874 ps |
CPU time | 0.86 seconds |
Started | Jun 05 05:40:04 PM PDT 24 |
Finished | Jun 05 05:40:06 PM PDT 24 |
Peak memory | 204852 kb |
Host | smart-b7208b3a-2575-4b50-a571-824ddd4df54a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999400917 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.2999400917 |
Directory | /workspace/0.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.1034031442 |
Short name | T183 |
Test name | |
Test status | |
Simulation time | 29105146349 ps |
CPU time | 79.95 seconds |
Started | Jun 05 05:39:58 PM PDT 24 |
Finished | Jun 05 05:41:18 PM PDT 24 |
Peak memory | 205200 kb |
Host | smart-535c8157-4d93-421a-b56a-036246034fa2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1034031442 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.1034031442 |
Directory | /workspace/0.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.3402866401 |
Short name | T233 |
Test name | |
Test status | |
Simulation time | 13230941473 ps |
CPU time | 14.82 seconds |
Started | Jun 05 05:39:57 PM PDT 24 |
Finished | Jun 05 05:40:13 PM PDT 24 |
Peak memory | 205208 kb |
Host | smart-960f6b37-a459-489b-9b56-3bc14c002e1c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3402866401 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.3402866401 |
Directory | /workspace/0.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_busy.2893008977 |
Short name | T138 |
Test name | |
Test status | |
Simulation time | 4186899810 ps |
CPU time | 13.79 seconds |
Started | Jun 05 05:39:55 PM PDT 24 |
Finished | Jun 05 05:40:09 PM PDT 24 |
Peak memory | 205208 kb |
Host | smart-e6da4bee-2ed8-4a21-bb50-e2c7a0e6a05e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2893008977 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.2893008977 |
Directory | /workspace/0.rv_dm_cmderr_busy/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_not_supported.1214955440 |
Short name | T141 |
Test name | |
Test status | |
Simulation time | 10622989130 ps |
CPU time | 25.99 seconds |
Started | Jun 05 05:39:56 PM PDT 24 |
Finished | Jun 05 05:40:22 PM PDT 24 |
Peak memory | 205096 kb |
Host | smart-b922ae8e-47b0-4c2f-b26f-7a989bf1b641 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1214955440 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.1214955440 |
Directory | /workspace/0.rv_dm_cmderr_not_supported/latest |
Test location | /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.2672419484 |
Short name | T206 |
Test name | |
Test status | |
Simulation time | 393790044 ps |
CPU time | 0.93 seconds |
Started | Jun 05 05:39:56 PM PDT 24 |
Finished | Jun 05 05:39:57 PM PDT 24 |
Peak memory | 204736 kb |
Host | smart-ac60f496-405c-45fb-920c-403db0918585 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2672419484 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.2672419484 |
Directory | /workspace/0.rv_dm_dataaddr_rw_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.846796176 |
Short name | T211 |
Test name | |
Test status | |
Simulation time | 1223768175 ps |
CPU time | 4.66 seconds |
Started | Jun 05 05:39:57 PM PDT 24 |
Finished | Jun 05 05:40:03 PM PDT 24 |
Peak memory | 205084 kb |
Host | smart-f4888da1-db6d-4415-8b8e-950a98a2e506 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=846796176 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_tl _access.846796176 |
Directory | /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_halt_resume_whereto.2586749364 |
Short name | T17 |
Test name | |
Test status | |
Simulation time | 945493837 ps |
CPU time | 3.34 seconds |
Started | Jun 05 05:39:57 PM PDT 24 |
Finished | Jun 05 05:40:01 PM PDT 24 |
Peak memory | 204688 kb |
Host | smart-433ec0d3-94ea-43cf-a6b3-6d0c93648bf2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2586749364 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.2586749364 |
Directory | /workspace/0.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/0.rv_dm_hart_unavail.4276521161 |
Short name | T226 |
Test name | |
Test status | |
Simulation time | 634967660 ps |
CPU time | 1.14 seconds |
Started | Jun 05 05:39:56 PM PDT 24 |
Finished | Jun 05 05:39:57 PM PDT 24 |
Peak memory | 204568 kb |
Host | smart-c4469de8-b8e0-4fe1-9e4b-a5f622924b9c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4276521161 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.4276521161 |
Directory | /workspace/0.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.1176056371 |
Short name | T239 |
Test name | |
Test status | |
Simulation time | 1027598141 ps |
CPU time | 1.73 seconds |
Started | Jun 05 05:39:55 PM PDT 24 |
Finished | Jun 05 05:39:57 PM PDT 24 |
Peak memory | 204580 kb |
Host | smart-2344cff8-9829-4a26-968c-a31e0cfa6e6e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1176056371 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.1176056371 |
Directory | /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.2947345691 |
Short name | T18 |
Test name | |
Test status | |
Simulation time | 348889332 ps |
CPU time | 1.76 seconds |
Started | Jun 05 05:39:54 PM PDT 24 |
Finished | Jun 05 05:39:56 PM PDT 24 |
Peak memory | 204600 kb |
Host | smart-d2c27f2c-daf2-4179-9b07-02ffdb288f09 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2947345691 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.2947345691 |
Directory | /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.3202945659 |
Short name | T230 |
Test name | |
Test status | |
Simulation time | 286974263 ps |
CPU time | 1.54 seconds |
Started | Jun 05 05:39:57 PM PDT 24 |
Finished | Jun 05 05:40:00 PM PDT 24 |
Peak memory | 204604 kb |
Host | smart-f2f0a7b9-fd8a-47b9-af7c-02120a17f020 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3202945659 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.3202945659 |
Directory | /workspace/0.rv_dm_jtag_dtm_hard_reset/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.1951619640 |
Short name | T202 |
Test name | |
Test status | |
Simulation time | 243438438 ps |
CPU time | 1.35 seconds |
Started | Jun 05 05:39:56 PM PDT 24 |
Finished | Jun 05 05:39:58 PM PDT 24 |
Peak memory | 204600 kb |
Host | smart-2ace7286-ce65-4f27-8793-b54c0a0f97a8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1951619640 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.1951619640 |
Directory | /workspace/0.rv_dm_jtag_dtm_idle_hint/latest |
Test location | /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.2270929862 |
Short name | T144 |
Test name | |
Test status | |
Simulation time | 487647735 ps |
CPU time | 1.29 seconds |
Started | Jun 05 05:39:54 PM PDT 24 |
Finished | Jun 05 05:39:56 PM PDT 24 |
Peak memory | 204712 kb |
Host | smart-766faa8c-eeb3-4f89-b88b-71f4608cc023 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2270929862 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.2270929862 |
Directory | /workspace/0.rv_dm_mem_tl_access_halted/latest |
Test location | /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.2367159289 |
Short name | T137 |
Test name | |
Test status | |
Simulation time | 2000431761 ps |
CPU time | 2.4 seconds |
Started | Jun 05 05:39:58 PM PDT 24 |
Finished | Jun 05 05:40:01 PM PDT 24 |
Peak memory | 204888 kb |
Host | smart-5cc5a2f9-0f48-4f07-b72a-d7157df1aff8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2367159289 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.2367159289 |
Directory | /workspace/0.rv_dm_mem_tl_access_resuming/latest |
Test location | /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.1622804464 |
Short name | T39 |
Test name | |
Test status | |
Simulation time | 466234988 ps |
CPU time | 1.22 seconds |
Started | Jun 05 05:40:08 PM PDT 24 |
Finished | Jun 05 05:40:10 PM PDT 24 |
Peak memory | 204740 kb |
Host | smart-3c33929e-4e15-4c6c-9135-b4d221a7f3d9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1622804464 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.1622804464 |
Directory | /workspace/0.rv_dm_progbuf_read_write_execute/latest |
Test location | /workspace/coverage/default/0.rv_dm_sba_tl_access.2786759227 |
Short name | T228 |
Test name | |
Test status | |
Simulation time | 1948293335 ps |
CPU time | 2.25 seconds |
Started | Jun 05 05:39:57 PM PDT 24 |
Finished | Jun 05 05:40:00 PM PDT 24 |
Peak memory | 205100 kb |
Host | smart-b4347730-1b31-4956-bf36-98e18bd1d411 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2786759227 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.2786759227 |
Directory | /workspace/0.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_sec_cm.2079679056 |
Short name | T61 |
Test name | |
Test status | |
Simulation time | 1087061132 ps |
CPU time | 2.68 seconds |
Started | Jun 05 05:40:00 PM PDT 24 |
Finished | Jun 05 05:40:03 PM PDT 24 |
Peak memory | 228432 kb |
Host | smart-9468f674-2987-4c82-a444-4bb8766d669a |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079679056 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.2079679056 |
Directory | /workspace/0.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/0.rv_dm_smoke.1083015932 |
Short name | T48 |
Test name | |
Test status | |
Simulation time | 2131957775 ps |
CPU time | 2.31 seconds |
Started | Jun 05 05:39:54 PM PDT 24 |
Finished | Jun 05 05:39:57 PM PDT 24 |
Peak memory | 204788 kb |
Host | smart-3ccc8b5b-aaeb-43d8-a054-1559bdb1abcf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1083015932 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.1083015932 |
Directory | /workspace/0.rv_dm_smoke/latest |
Test location | /workspace/coverage/default/0.rv_dm_tap_fsm.1366194173 |
Short name | T45 |
Test name | |
Test status | |
Simulation time | 5961451702 ps |
CPU time | 9.44 seconds |
Started | Jun 05 05:39:56 PM PDT 24 |
Finished | Jun 05 05:40:06 PM PDT 24 |
Peak memory | 204976 kb |
Host | smart-249f79c3-d446-43c7-9746-9561db5cf5c1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1366194173 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.1366194173 |
Directory | /workspace/0.rv_dm_tap_fsm/latest |
Test location | /workspace/coverage/default/1.rv_dm_abstractcmd_status.1355764264 |
Short name | T41 |
Test name | |
Test status | |
Simulation time | 224386208 ps |
CPU time | 0.86 seconds |
Started | Jun 05 05:40:02 PM PDT 24 |
Finished | Jun 05 05:40:03 PM PDT 24 |
Peak memory | 204744 kb |
Host | smart-4b27076b-c7c4-4bf5-862e-40a91ada79e5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1355764264 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.1355764264 |
Directory | /workspace/1.rv_dm_abstractcmd_status/latest |
Test location | /workspace/coverage/default/1.rv_dm_alert_test.1425004456 |
Short name | T50 |
Test name | |
Test status | |
Simulation time | 107287157 ps |
CPU time | 0.81 seconds |
Started | Jun 05 05:40:10 PM PDT 24 |
Finished | Jun 05 05:40:12 PM PDT 24 |
Peak memory | 204868 kb |
Host | smart-8c10de31-1b1e-4f0c-84c0-e5f30545b1cd |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425004456 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.1425004456 |
Directory | /workspace/1.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.627271249 |
Short name | T237 |
Test name | |
Test status | |
Simulation time | 827372112 ps |
CPU time | 3.17 seconds |
Started | Jun 05 05:40:07 PM PDT 24 |
Finished | Jun 05 05:40:11 PM PDT 24 |
Peak memory | 205096 kb |
Host | smart-25f25b02-2c44-4d03-befe-c4f0b152dd59 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=627271249 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.627271249 |
Directory | /workspace/1.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.28294847 |
Short name | T190 |
Test name | |
Test status | |
Simulation time | 1331901340 ps |
CPU time | 1.78 seconds |
Started | Jun 05 05:40:03 PM PDT 24 |
Finished | Jun 05 05:40:05 PM PDT 24 |
Peak memory | 205124 kb |
Host | smart-3390eb43-d66a-4848-a040-1fa302e483a4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=28294847 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.28294847 |
Directory | /workspace/1.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_busy.3987452163 |
Short name | T13 |
Test name | |
Test status | |
Simulation time | 10874662190 ps |
CPU time | 28.68 seconds |
Started | Jun 05 05:40:03 PM PDT 24 |
Finished | Jun 05 05:40:33 PM PDT 24 |
Peak memory | 205068 kb |
Host | smart-250295d1-d160-4093-8740-483b40a7a7c8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3987452163 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.3987452163 |
Directory | /workspace/1.rv_dm_cmderr_busy/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_exception.2858576416 |
Short name | T10 |
Test name | |
Test status | |
Simulation time | 781782802 ps |
CPU time | 2.14 seconds |
Started | Jun 05 05:40:09 PM PDT 24 |
Finished | Jun 05 05:40:12 PM PDT 24 |
Peak memory | 204728 kb |
Host | smart-6f2d6ad4-58e8-48aa-8207-0c6ac1ad6e73 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2858576416 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.2858576416 |
Directory | /workspace/1.rv_dm_cmderr_exception/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.2666625103 |
Short name | T28 |
Test name | |
Test status | |
Simulation time | 323140897 ps |
CPU time | 1.18 seconds |
Started | Jun 05 05:40:04 PM PDT 24 |
Finished | Jun 05 05:40:06 PM PDT 24 |
Peak memory | 204604 kb |
Host | smart-736da31c-0dde-4c7e-a150-394e0ef3a155 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2666625103 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.2666625103 |
Directory | /workspace/1.rv_dm_cmderr_halt_resume/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_not_supported.3583863986 |
Short name | T146 |
Test name | |
Test status | |
Simulation time | 2631320019 ps |
CPU time | 4.65 seconds |
Started | Jun 05 05:40:03 PM PDT 24 |
Finished | Jun 05 05:40:09 PM PDT 24 |
Peak memory | 205052 kb |
Host | smart-7b1fe213-6c0d-4898-8db2-2781e532c6da |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3583863986 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.3583863986 |
Directory | /workspace/1.rv_dm_cmderr_not_supported/latest |
Test location | /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.84699352 |
Short name | T65 |
Test name | |
Test status | |
Simulation time | 188456522 ps |
CPU time | 0.9 seconds |
Started | Jun 05 05:40:02 PM PDT 24 |
Finished | Jun 05 05:40:04 PM PDT 24 |
Peak memory | 204676 kb |
Host | smart-b69cdb02-dbc3-41fb-9a03-af166afc617a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=84699352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.84699352 |
Directory | /workspace/1.rv_dm_dataaddr_rw_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.686085584 |
Short name | T187 |
Test name | |
Test status | |
Simulation time | 5735793246 ps |
CPU time | 8.39 seconds |
Started | Jun 05 05:40:05 PM PDT 24 |
Finished | Jun 05 05:40:14 PM PDT 24 |
Peak memory | 205200 kb |
Host | smart-6562771e-9a56-468f-9d8d-d7aa2ad72df2 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=686085584 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_tl _access.686085584 |
Directory | /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_halt_resume_whereto.3475358530 |
Short name | T36 |
Test name | |
Test status | |
Simulation time | 2508827048 ps |
CPU time | 8.4 seconds |
Started | Jun 05 05:40:05 PM PDT 24 |
Finished | Jun 05 05:40:14 PM PDT 24 |
Peak memory | 204852 kb |
Host | smart-5c53c5e5-96bc-4f92-b40a-637ce83e0efe |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3475358530 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.3475358530 |
Directory | /workspace/1.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/1.rv_dm_hart_unavail.2228219065 |
Short name | T193 |
Test name | |
Test status | |
Simulation time | 332053722 ps |
CPU time | 1.64 seconds |
Started | Jun 05 05:40:01 PM PDT 24 |
Finished | Jun 05 05:40:03 PM PDT 24 |
Peak memory | 204584 kb |
Host | smart-f44a0153-0c0d-4568-979e-93fdfdc66684 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2228219065 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.2228219065 |
Directory | /workspace/1.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.2877628930 |
Short name | T199 |
Test name | |
Test status | |
Simulation time | 1248162668 ps |
CPU time | 4.28 seconds |
Started | Jun 05 05:40:02 PM PDT 24 |
Finished | Jun 05 05:40:07 PM PDT 24 |
Peak memory | 204596 kb |
Host | smart-5bc555ee-ce63-462c-999b-b442171fb7be |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2877628930 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.2877628930 |
Directory | /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.952238956 |
Short name | T208 |
Test name | |
Test status | |
Simulation time | 478154351 ps |
CPU time | 1.38 seconds |
Started | Jun 05 05:40:09 PM PDT 24 |
Finished | Jun 05 05:40:11 PM PDT 24 |
Peak memory | 204596 kb |
Host | smart-f07ac39c-51dc-43ad-a022-0956cb9dcc1a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=952238956 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.952238956 |
Directory | /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.1822837786 |
Short name | T249 |
Test name | |
Test status | |
Simulation time | 1819776763 ps |
CPU time | 1.96 seconds |
Started | Jun 05 05:40:01 PM PDT 24 |
Finished | Jun 05 05:40:04 PM PDT 24 |
Peak memory | 204836 kb |
Host | smart-9766d50b-243e-41b7-b261-86b3b0a155c4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1822837786 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.1822837786 |
Directory | /workspace/1.rv_dm_jtag_dtm_hard_reset/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.4267489803 |
Short name | T49 |
Test name | |
Test status | |
Simulation time | 136929363 ps |
CPU time | 0.9 seconds |
Started | Jun 05 05:40:02 PM PDT 24 |
Finished | Jun 05 05:40:04 PM PDT 24 |
Peak memory | 204552 kb |
Host | smart-6a1d6037-b166-46d4-8542-4c74acd5c54b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4267489803 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.4267489803 |
Directory | /workspace/1.rv_dm_jtag_dtm_idle_hint/latest |
Test location | /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.1088831474 |
Short name | T145 |
Test name | |
Test status | |
Simulation time | 1038335601 ps |
CPU time | 2.12 seconds |
Started | Jun 05 05:40:04 PM PDT 24 |
Finished | Jun 05 05:40:07 PM PDT 24 |
Peak memory | 204728 kb |
Host | smart-097354fa-dff3-4a35-8143-382f60e5f859 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1088831474 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.1088831474 |
Directory | /workspace/1.rv_dm_mem_tl_access_halted/latest |
Test location | /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.1381380925 |
Short name | T147 |
Test name | |
Test status | |
Simulation time | 2143714110 ps |
CPU time | 6.66 seconds |
Started | Jun 05 05:40:01 PM PDT 24 |
Finished | Jun 05 05:40:08 PM PDT 24 |
Peak memory | 205004 kb |
Host | smart-fe741a5b-3978-4cf3-ab8f-d97e7a692623 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1381380925 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.1381380925 |
Directory | /workspace/1.rv_dm_mem_tl_access_resuming/latest |
Test location | /workspace/coverage/default/1.rv_dm_ndmreset_req.4174061108 |
Short name | T262 |
Test name | |
Test status | |
Simulation time | 613500425 ps |
CPU time | 1.46 seconds |
Started | Jun 05 05:40:04 PM PDT 24 |
Finished | Jun 05 05:40:06 PM PDT 24 |
Peak memory | 204688 kb |
Host | smart-d02c7698-629f-48ff-9dc8-79bc76d26177 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4174061108 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.4174061108 |
Directory | /workspace/1.rv_dm_ndmreset_req/latest |
Test location | /workspace/coverage/default/1.rv_dm_progbuf_busy.760923231 |
Short name | T6 |
Test name | |
Test status | |
Simulation time | 944060701 ps |
CPU time | 1.73 seconds |
Started | Jun 05 05:40:05 PM PDT 24 |
Finished | Jun 05 05:40:07 PM PDT 24 |
Peak memory | 204960 kb |
Host | smart-247f9c68-9d91-49b9-b8a9-f2ce74e9d768 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=760923231 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.760923231 |
Directory | /workspace/1.rv_dm_progbuf_busy/latest |
Test location | /workspace/coverage/default/1.rv_dm_rom_read_access.825951111 |
Short name | T34 |
Test name | |
Test status | |
Simulation time | 45878314 ps |
CPU time | 0.85 seconds |
Started | Jun 05 05:40:09 PM PDT 24 |
Finished | Jun 05 05:40:11 PM PDT 24 |
Peak memory | 212944 kb |
Host | smart-c36d24b1-4378-4b13-95ab-5c8eaf1cc038 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=825951111 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.825951111 |
Directory | /workspace/1.rv_dm_rom_read_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_sba_tl_access.318272918 |
Short name | T221 |
Test name | |
Test status | |
Simulation time | 2720008577 ps |
CPU time | 5.41 seconds |
Started | Jun 05 05:40:03 PM PDT 24 |
Finished | Jun 05 05:40:09 PM PDT 24 |
Peak memory | 205236 kb |
Host | smart-feaaa430-2308-48a2-9af7-cbc4716e7964 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=318272918 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.318272918 |
Directory | /workspace/1.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_sec_cm.4069471620 |
Short name | T43 |
Test name | |
Test status | |
Simulation time | 1335225069 ps |
CPU time | 2.55 seconds |
Started | Jun 05 05:40:13 PM PDT 24 |
Finished | Jun 05 05:40:16 PM PDT 24 |
Peak memory | 229448 kb |
Host | smart-59cc6b3a-355e-4aa3-9c47-66afbcc82602 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069471620 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.4069471620 |
Directory | /workspace/1.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/1.rv_dm_smoke.2099584192 |
Short name | T252 |
Test name | |
Test status | |
Simulation time | 2839624596 ps |
CPU time | 2.21 seconds |
Started | Jun 05 05:40:04 PM PDT 24 |
Finished | Jun 05 05:40:07 PM PDT 24 |
Peak memory | 204860 kb |
Host | smart-700f3539-685c-405a-9e74-8dfd419d33b3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2099584192 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.2099584192 |
Directory | /workspace/1.rv_dm_smoke/latest |
Test location | /workspace/coverage/default/10.rv_dm_alert_test.3660360442 |
Short name | T156 |
Test name | |
Test status | |
Simulation time | 76806528 ps |
CPU time | 0.73 seconds |
Started | Jun 05 05:40:18 PM PDT 24 |
Finished | Jun 05 05:40:21 PM PDT 24 |
Peak memory | 204856 kb |
Host | smart-681c6dff-624c-41a2-b8e7-233b17a73749 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660360442 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.3660360442 |
Directory | /workspace/10.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.3832442665 |
Short name | T241 |
Test name | |
Test status | |
Simulation time | 12758269589 ps |
CPU time | 5.28 seconds |
Started | Jun 05 05:40:23 PM PDT 24 |
Finished | Jun 05 05:40:29 PM PDT 24 |
Peak memory | 213416 kb |
Host | smart-8b5f07b6-c329-423a-9d9b-bd2a64ea770c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3832442665 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.3832442665 |
Directory | /workspace/10.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.234958344 |
Short name | T244 |
Test name | |
Test status | |
Simulation time | 4011804720 ps |
CPU time | 2.83 seconds |
Started | Jun 05 05:40:27 PM PDT 24 |
Finished | Jun 05 05:40:31 PM PDT 24 |
Peak memory | 205208 kb |
Host | smart-c4bc938b-f6f2-4f0d-ab88-9b081f0fae04 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=234958344 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.234958344 |
Directory | /workspace/10.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.2835559018 |
Short name | T253 |
Test name | |
Test status | |
Simulation time | 9158472418 ps |
CPU time | 14.64 seconds |
Started | Jun 05 05:40:23 PM PDT 24 |
Finished | Jun 05 05:40:38 PM PDT 24 |
Peak memory | 205260 kb |
Host | smart-9ba9f7a2-47de-4313-a6bf-ea7157f96016 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2835559018 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_ tl_access.2835559018 |
Directory | /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_sba_tl_access.3292456003 |
Short name | T236 |
Test name | |
Test status | |
Simulation time | 4788809986 ps |
CPU time | 13.78 seconds |
Started | Jun 05 05:40:17 PM PDT 24 |
Finished | Jun 05 05:40:32 PM PDT 24 |
Peak memory | 205400 kb |
Host | smart-f3e485ac-9bd9-4cfb-953e-2f0079d20b9c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3292456003 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.3292456003 |
Directory | /workspace/10.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_stress_all.399435533 |
Short name | T12 |
Test name | |
Test status | |
Simulation time | 22884633200 ps |
CPU time | 21.34 seconds |
Started | Jun 05 05:40:26 PM PDT 24 |
Finished | Jun 05 05:40:48 PM PDT 24 |
Peak memory | 205048 kb |
Host | smart-e6f8b7e5-e8b1-41f3-8e63-829c1a476bf2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399435533 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.399435533 |
Directory | /workspace/10.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/11.rv_dm_alert_test.1559807561 |
Short name | T149 |
Test name | |
Test status | |
Simulation time | 127248070 ps |
CPU time | 1.02 seconds |
Started | Jun 05 05:40:27 PM PDT 24 |
Finished | Jun 05 05:40:29 PM PDT 24 |
Peak memory | 204852 kb |
Host | smart-85449c9f-291b-4b9c-8a7b-1d4d6dd3fc54 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559807561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.1559807561 |
Directory | /workspace/11.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.1719586386 |
Short name | T198 |
Test name | |
Test status | |
Simulation time | 4269846480 ps |
CPU time | 7.02 seconds |
Started | Jun 05 05:40:18 PM PDT 24 |
Finished | Jun 05 05:40:26 PM PDT 24 |
Peak memory | 205256 kb |
Host | smart-4b343de7-6957-476b-9292-bd1b1aec2956 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1719586386 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.1719586386 |
Directory | /workspace/11.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.56229734 |
Short name | T58 |
Test name | |
Test status | |
Simulation time | 3734687909 ps |
CPU time | 12.08 seconds |
Started | Jun 05 05:40:26 PM PDT 24 |
Finished | Jun 05 05:40:39 PM PDT 24 |
Peak memory | 205268 kb |
Host | smart-5fea1ea8-593c-4976-a6e1-94198110c3b6 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=56229734 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_tl _access.56229734 |
Directory | /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_sba_tl_access.4121562173 |
Short name | T217 |
Test name | |
Test status | |
Simulation time | 7462073191 ps |
CPU time | 10.34 seconds |
Started | Jun 05 05:40:26 PM PDT 24 |
Finished | Jun 05 05:40:37 PM PDT 24 |
Peak memory | 205248 kb |
Host | smart-8205b9fb-68bd-49d5-93a7-3a4efc182921 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4121562173 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.4121562173 |
Directory | /workspace/11.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_alert_test.1885337719 |
Short name | T148 |
Test name | |
Test status | |
Simulation time | 57230907 ps |
CPU time | 0.75 seconds |
Started | Jun 05 05:40:26 PM PDT 24 |
Finished | Jun 05 05:40:28 PM PDT 24 |
Peak memory | 204852 kb |
Host | smart-c8102d76-bc37-41aa-895c-5d24a3d2fe77 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885337719 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.1885337719 |
Directory | /workspace/12.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.832864722 |
Short name | T1 |
Test name | |
Test status | |
Simulation time | 3709374367 ps |
CPU time | 3.82 seconds |
Started | Jun 05 05:40:25 PM PDT 24 |
Finished | Jun 05 05:40:30 PM PDT 24 |
Peak memory | 205192 kb |
Host | smart-4afba243-5db7-4fce-8025-1cd71f05c94d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=832864722 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.832864722 |
Directory | /workspace/12.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.3872230573 |
Short name | T220 |
Test name | |
Test status | |
Simulation time | 14819900856 ps |
CPU time | 22.46 seconds |
Started | Jun 05 05:40:24 PM PDT 24 |
Finished | Jun 05 05:40:48 PM PDT 24 |
Peak memory | 205216 kb |
Host | smart-ef0dbdd3-452d-4841-9a4c-47fc765b845f |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3872230573 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_ tl_access.3872230573 |
Directory | /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_sba_tl_access.3783381410 |
Short name | T27 |
Test name | |
Test status | |
Simulation time | 9760555903 ps |
CPU time | 13.85 seconds |
Started | Jun 05 05:40:26 PM PDT 24 |
Finished | Jun 05 05:40:41 PM PDT 24 |
Peak memory | 205208 kb |
Host | smart-b685cc0b-39b8-4829-a2cc-0b99f6f7bb3c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3783381410 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.3783381410 |
Directory | /workspace/12.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_alert_test.4284932615 |
Short name | T159 |
Test name | |
Test status | |
Simulation time | 94397372 ps |
CPU time | 0.75 seconds |
Started | Jun 05 05:40:24 PM PDT 24 |
Finished | Jun 05 05:40:25 PM PDT 24 |
Peak memory | 205040 kb |
Host | smart-acfe0a6f-b9fe-42de-94ec-b6036d10103c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284932615 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.4284932615 |
Directory | /workspace/13.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.1969995659 |
Short name | T243 |
Test name | |
Test status | |
Simulation time | 16623505600 ps |
CPU time | 47.06 seconds |
Started | Jun 05 05:40:26 PM PDT 24 |
Finished | Jun 05 05:41:14 PM PDT 24 |
Peak memory | 213356 kb |
Host | smart-70979964-bfb2-4ba9-a8c6-f9eaca63049b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1969995659 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.1969995659 |
Directory | /workspace/13.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.80641465 |
Short name | T259 |
Test name | |
Test status | |
Simulation time | 1234589229 ps |
CPU time | 2.88 seconds |
Started | Jun 05 05:40:28 PM PDT 24 |
Finished | Jun 05 05:40:31 PM PDT 24 |
Peak memory | 205084 kb |
Host | smart-ad33347b-9406-4cf9-a557-da31e01ee4d3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=80641465 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.80641465 |
Directory | /workspace/13.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.1902490758 |
Short name | T260 |
Test name | |
Test status | |
Simulation time | 1726905782 ps |
CPU time | 2.14 seconds |
Started | Jun 05 05:40:24 PM PDT 24 |
Finished | Jun 05 05:40:27 PM PDT 24 |
Peak memory | 205048 kb |
Host | smart-bb7e72cc-1387-4462-974f-a0be8fbef7ce |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1902490758 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_ tl_access.1902490758 |
Directory | /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_sba_tl_access.3435150770 |
Short name | T197 |
Test name | |
Test status | |
Simulation time | 11072022568 ps |
CPU time | 29.99 seconds |
Started | Jun 05 05:40:26 PM PDT 24 |
Finished | Jun 05 05:40:57 PM PDT 24 |
Peak memory | 205352 kb |
Host | smart-11c9eb60-a54e-4bbb-ba70-9d24283d4f3e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3435150770 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.3435150770 |
Directory | /workspace/13.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/14.rv_dm_alert_test.2626049375 |
Short name | T181 |
Test name | |
Test status | |
Simulation time | 108026853 ps |
CPU time | 0.96 seconds |
Started | Jun 05 05:40:26 PM PDT 24 |
Finished | Jun 05 05:40:28 PM PDT 24 |
Peak memory | 204836 kb |
Host | smart-120f1288-7486-479e-8845-bb61e2267275 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626049375 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.2626049375 |
Directory | /workspace/14.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.1839284765 |
Short name | T234 |
Test name | |
Test status | |
Simulation time | 86706844081 ps |
CPU time | 57.62 seconds |
Started | Jun 05 05:40:26 PM PDT 24 |
Finished | Jun 05 05:41:25 PM PDT 24 |
Peak memory | 214372 kb |
Host | smart-2105b65a-3f96-4701-816d-e79e213d8302 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1839284765 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.1839284765 |
Directory | /workspace/14.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.1960730020 |
Short name | T15 |
Test name | |
Test status | |
Simulation time | 1316774051 ps |
CPU time | 4.55 seconds |
Started | Jun 05 05:40:23 PM PDT 24 |
Finished | Jun 05 05:40:28 PM PDT 24 |
Peak memory | 205088 kb |
Host | smart-df44e2ae-9ee4-4b5e-97d6-b54ec5bf98b7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1960730020 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.1960730020 |
Directory | /workspace/14.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.3836908292 |
Short name | T178 |
Test name | |
Test status | |
Simulation time | 5593479412 ps |
CPU time | 2.9 seconds |
Started | Jun 05 05:40:24 PM PDT 24 |
Finished | Jun 05 05:40:28 PM PDT 24 |
Peak memory | 205212 kb |
Host | smart-966ebed8-9a9c-4282-afbc-b6cfe03e23d9 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3836908292 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_ tl_access.3836908292 |
Directory | /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/14.rv_dm_sba_tl_access.954408885 |
Short name | T248 |
Test name | |
Test status | |
Simulation time | 2270759405 ps |
CPU time | 6.88 seconds |
Started | Jun 05 05:40:25 PM PDT 24 |
Finished | Jun 05 05:40:32 PM PDT 24 |
Peak memory | 205220 kb |
Host | smart-485264f3-581f-46d1-8998-89010199f1b8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=954408885 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.954408885 |
Directory | /workspace/14.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/14.rv_dm_stress_all.2141554486 |
Short name | T122 |
Test name | |
Test status | |
Simulation time | 12846430783 ps |
CPU time | 11.93 seconds |
Started | Jun 05 05:40:26 PM PDT 24 |
Finished | Jun 05 05:40:39 PM PDT 24 |
Peak memory | 205044 kb |
Host | smart-d58c50ea-b5fc-437a-85d7-0910d190f89d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141554486 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.2141554486 |
Directory | /workspace/14.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/15.rv_dm_alert_test.3294111904 |
Short name | T256 |
Test name | |
Test status | |
Simulation time | 87917701 ps |
CPU time | 0.96 seconds |
Started | Jun 05 05:40:25 PM PDT 24 |
Finished | Jun 05 05:40:28 PM PDT 24 |
Peak memory | 204856 kb |
Host | smart-25e93ee7-636a-4aba-822d-df5b1a573089 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294111904 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.3294111904 |
Directory | /workspace/15.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.585642770 |
Short name | T218 |
Test name | |
Test status | |
Simulation time | 5568858503 ps |
CPU time | 3.07 seconds |
Started | Jun 05 05:40:23 PM PDT 24 |
Finished | Jun 05 05:40:27 PM PDT 24 |
Peak memory | 205204 kb |
Host | smart-d57e98ad-c5dc-4cfb-93c4-017e4ff7c00d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=585642770 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.585642770 |
Directory | /workspace/15.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.1714708823 |
Short name | T201 |
Test name | |
Test status | |
Simulation time | 9158054338 ps |
CPU time | 21.07 seconds |
Started | Jun 05 05:40:25 PM PDT 24 |
Finished | Jun 05 05:40:47 PM PDT 24 |
Peak memory | 205224 kb |
Host | smart-e0ca8816-4ebd-44bb-a6f2-f096dedc84cf |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1714708823 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_ tl_access.1714708823 |
Directory | /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_sba_tl_access.862171804 |
Short name | T223 |
Test name | |
Test status | |
Simulation time | 6861023342 ps |
CPU time | 8.46 seconds |
Started | Jun 05 05:40:25 PM PDT 24 |
Finished | Jun 05 05:40:34 PM PDT 24 |
Peak memory | 205256 kb |
Host | smart-67c01612-6ce9-4ab2-94ef-0c54e8baf817 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=862171804 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.862171804 |
Directory | /workspace/15.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_alert_test.1611879750 |
Short name | T254 |
Test name | |
Test status | |
Simulation time | 106398758 ps |
CPU time | 0.87 seconds |
Started | Jun 05 05:40:31 PM PDT 24 |
Finished | Jun 05 05:40:33 PM PDT 24 |
Peak memory | 204840 kb |
Host | smart-24bd7ad3-908b-4e3b-9bbb-40a7bdc489e2 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611879750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.1611879750 |
Directory | /workspace/16.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.1190989234 |
Short name | T245 |
Test name | |
Test status | |
Simulation time | 8041490032 ps |
CPU time | 21.42 seconds |
Started | Jun 05 05:40:25 PM PDT 24 |
Finished | Jun 05 05:40:48 PM PDT 24 |
Peak memory | 213456 kb |
Host | smart-f2456ef2-fc8d-4985-9f6d-dbcd94b16574 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1190989234 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.1190989234 |
Directory | /workspace/16.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.1982780446 |
Short name | T210 |
Test name | |
Test status | |
Simulation time | 3498516737 ps |
CPU time | 3.62 seconds |
Started | Jun 05 05:40:25 PM PDT 24 |
Finished | Jun 05 05:40:30 PM PDT 24 |
Peak memory | 205228 kb |
Host | smart-74008c46-cbe8-4549-bfc8-ba73a456ec97 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1982780446 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.1982780446 |
Directory | /workspace/16.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.4049689609 |
Short name | T59 |
Test name | |
Test status | |
Simulation time | 2996766024 ps |
CPU time | 4.88 seconds |
Started | Jun 05 05:40:26 PM PDT 24 |
Finished | Jun 05 05:40:32 PM PDT 24 |
Peak memory | 205192 kb |
Host | smart-0dd55af3-f3cd-49ea-8b2a-c1e6b8972103 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4049689609 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_ tl_access.4049689609 |
Directory | /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_sba_tl_access.718482079 |
Short name | T240 |
Test name | |
Test status | |
Simulation time | 2535287944 ps |
CPU time | 2.51 seconds |
Started | Jun 05 05:40:27 PM PDT 24 |
Finished | Jun 05 05:40:30 PM PDT 24 |
Peak memory | 205212 kb |
Host | smart-3e5cfcb2-f2c6-46e1-b940-51cdbed5615a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=718482079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.718482079 |
Directory | /workspace/16.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_alert_test.143670847 |
Short name | T56 |
Test name | |
Test status | |
Simulation time | 37828130 ps |
CPU time | 0.75 seconds |
Started | Jun 05 05:40:34 PM PDT 24 |
Finished | Jun 05 05:40:35 PM PDT 24 |
Peak memory | 204836 kb |
Host | smart-216747f8-4087-43f0-8e5e-e92c0548fb57 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143670847 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.143670847 |
Directory | /workspace/17.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.4225316614 |
Short name | T246 |
Test name | |
Test status | |
Simulation time | 2083449736 ps |
CPU time | 1.86 seconds |
Started | Jun 05 05:40:31 PM PDT 24 |
Finished | Jun 05 05:40:34 PM PDT 24 |
Peak memory | 205116 kb |
Host | smart-e3b1a29f-5729-4aae-b193-d0577ae362aa |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4225316614 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.4225316614 |
Directory | /workspace/17.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.2384621826 |
Short name | T189 |
Test name | |
Test status | |
Simulation time | 8461508106 ps |
CPU time | 2.5 seconds |
Started | Jun 05 05:40:35 PM PDT 24 |
Finished | Jun 05 05:40:38 PM PDT 24 |
Peak memory | 213448 kb |
Host | smart-9e395a0b-609e-4dba-b904-476ad9f480d6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2384621826 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.2384621826 |
Directory | /workspace/17.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.1707339630 |
Short name | T200 |
Test name | |
Test status | |
Simulation time | 8451542223 ps |
CPU time | 23.25 seconds |
Started | Jun 05 05:40:31 PM PDT 24 |
Finished | Jun 05 05:40:55 PM PDT 24 |
Peak memory | 205200 kb |
Host | smart-ff540b5c-201a-4080-b45f-b6724d9bdf84 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1707339630 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_ tl_access.1707339630 |
Directory | /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_sba_tl_access.930941645 |
Short name | T209 |
Test name | |
Test status | |
Simulation time | 7064100209 ps |
CPU time | 17.84 seconds |
Started | Jun 05 05:40:31 PM PDT 24 |
Finished | Jun 05 05:40:50 PM PDT 24 |
Peak memory | 205204 kb |
Host | smart-5894138e-ceb8-4f5b-87fa-2c0b00327318 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=930941645 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.930941645 |
Directory | /workspace/17.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_alert_test.3624823414 |
Short name | T154 |
Test name | |
Test status | |
Simulation time | 93600733 ps |
CPU time | 0.98 seconds |
Started | Jun 05 05:40:33 PM PDT 24 |
Finished | Jun 05 05:40:35 PM PDT 24 |
Peak memory | 204856 kb |
Host | smart-08722b86-220b-43d8-8d83-a14b1ccd0299 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624823414 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.3624823414 |
Directory | /workspace/18.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.2160351302 |
Short name | T62 |
Test name | |
Test status | |
Simulation time | 8010908864 ps |
CPU time | 22.53 seconds |
Started | Jun 05 05:40:31 PM PDT 24 |
Finished | Jun 05 05:40:54 PM PDT 24 |
Peak memory | 205200 kb |
Host | smart-c61d4f17-2390-477e-b722-225799fce025 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2160351302 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.2160351302 |
Directory | /workspace/18.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.551121045 |
Short name | T66 |
Test name | |
Test status | |
Simulation time | 1669363567 ps |
CPU time | 2.01 seconds |
Started | Jun 05 05:40:34 PM PDT 24 |
Finished | Jun 05 05:40:37 PM PDT 24 |
Peak memory | 205124 kb |
Host | smart-2a7451f6-680f-4193-bb8f-3cd60d5f693f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=551121045 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.551121045 |
Directory | /workspace/18.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.2994023354 |
Short name | T182 |
Test name | |
Test status | |
Simulation time | 2423567739 ps |
CPU time | 6.49 seconds |
Started | Jun 05 05:40:31 PM PDT 24 |
Finished | Jun 05 05:40:39 PM PDT 24 |
Peak memory | 205208 kb |
Host | smart-0ef9cc9a-77be-4aff-88f2-b551cebbb197 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2994023354 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_ tl_access.2994023354 |
Directory | /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_sba_tl_access.3599632645 |
Short name | T242 |
Test name | |
Test status | |
Simulation time | 4070093887 ps |
CPU time | 9.45 seconds |
Started | Jun 05 05:40:33 PM PDT 24 |
Finished | Jun 05 05:40:44 PM PDT 24 |
Peak memory | 205272 kb |
Host | smart-d26dc185-c852-4fbc-a0c6-7774c45a5801 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3599632645 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.3599632645 |
Directory | /workspace/18.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_alert_test.1616941807 |
Short name | T168 |
Test name | |
Test status | |
Simulation time | 256198381 ps |
CPU time | 0.8 seconds |
Started | Jun 05 05:40:33 PM PDT 24 |
Finished | Jun 05 05:40:34 PM PDT 24 |
Peak memory | 204852 kb |
Host | smart-8aceef61-5196-4ac9-8bfc-e9ef72594de6 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616941807 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.1616941807 |
Directory | /workspace/19.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.653418299 |
Short name | T20 |
Test name | |
Test status | |
Simulation time | 30439866923 ps |
CPU time | 37.4 seconds |
Started | Jun 05 05:40:30 PM PDT 24 |
Finished | Jun 05 05:41:08 PM PDT 24 |
Peak memory | 213444 kb |
Host | smart-5079f6ab-5b6b-4da5-bad9-1fff74bf7a4d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=653418299 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.653418299 |
Directory | /workspace/19.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.2713431690 |
Short name | T235 |
Test name | |
Test status | |
Simulation time | 7158966117 ps |
CPU time | 7.01 seconds |
Started | Jun 05 05:40:32 PM PDT 24 |
Finished | Jun 05 05:40:40 PM PDT 24 |
Peak memory | 205200 kb |
Host | smart-54c03273-1689-4dc3-b5b7-68ebd328b5fc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2713431690 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.2713431690 |
Directory | /workspace/19.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.2213409236 |
Short name | T205 |
Test name | |
Test status | |
Simulation time | 6099567751 ps |
CPU time | 9.92 seconds |
Started | Jun 05 05:40:32 PM PDT 24 |
Finished | Jun 05 05:40:43 PM PDT 24 |
Peak memory | 205248 kb |
Host | smart-d7e55302-940c-40af-9394-2fe104a76eed |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2213409236 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_ tl_access.2213409236 |
Directory | /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_sba_tl_access.1756599317 |
Short name | T251 |
Test name | |
Test status | |
Simulation time | 11397455518 ps |
CPU time | 14.54 seconds |
Started | Jun 05 05:40:30 PM PDT 24 |
Finished | Jun 05 05:40:45 PM PDT 24 |
Peak memory | 205328 kb |
Host | smart-9b86690e-e00d-4705-aff3-1c8bbda7d9a0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1756599317 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.1756599317 |
Directory | /workspace/19.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_alert_test.1159315094 |
Short name | T57 |
Test name | |
Test status | |
Simulation time | 41141249 ps |
CPU time | 0.8 seconds |
Started | Jun 05 05:40:18 PM PDT 24 |
Finished | Jun 05 05:40:21 PM PDT 24 |
Peak memory | 204856 kb |
Host | smart-e284e6c3-7f34-4147-a573-3e3b321fd7bd |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159315094 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.1159315094 |
Directory | /workspace/2.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.3501728465 |
Short name | T67 |
Test name | |
Test status | |
Simulation time | 8718331547 ps |
CPU time | 10.12 seconds |
Started | Jun 05 05:40:17 PM PDT 24 |
Finished | Jun 05 05:40:28 PM PDT 24 |
Peak memory | 205144 kb |
Host | smart-7ecb4541-747d-4f99-a8b4-f9ea1d32e795 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3501728465 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.3501728465 |
Directory | /workspace/2.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.1030711635 |
Short name | T213 |
Test name | |
Test status | |
Simulation time | 11998905617 ps |
CPU time | 10.61 seconds |
Started | Jun 05 05:40:13 PM PDT 24 |
Finished | Jun 05 05:40:24 PM PDT 24 |
Peak memory | 205256 kb |
Host | smart-1ec89785-1294-4550-939b-a99eb89360fb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1030711635 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.1030711635 |
Directory | /workspace/2.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.1359060135 |
Short name | T3 |
Test name | |
Test status | |
Simulation time | 3629938218 ps |
CPU time | 3.87 seconds |
Started | Jun 05 05:40:20 PM PDT 24 |
Finished | Jun 05 05:40:25 PM PDT 24 |
Peak memory | 205204 kb |
Host | smart-3f0db412-0800-4a62-b6ab-e18fe91ff86f |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1359060135 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t l_access.1359060135 |
Directory | /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_hart_unavail.1094366403 |
Short name | T184 |
Test name | |
Test status | |
Simulation time | 144764618 ps |
CPU time | 0.87 seconds |
Started | Jun 05 05:40:12 PM PDT 24 |
Finished | Jun 05 05:40:14 PM PDT 24 |
Peak memory | 204560 kb |
Host | smart-44d44e43-b2df-4ae1-bc75-c296be49188f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1094366403 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.1094366403 |
Directory | /workspace/2.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/2.rv_dm_sba_tl_access.2904761868 |
Short name | T4 |
Test name | |
Test status | |
Simulation time | 2127430978 ps |
CPU time | 6.44 seconds |
Started | Jun 05 05:40:12 PM PDT 24 |
Finished | Jun 05 05:40:19 PM PDT 24 |
Peak memory | 205228 kb |
Host | smart-44687040-9dbf-4808-be2f-8ef0da4515c4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2904761868 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.2904761868 |
Directory | /workspace/2.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_sec_cm.3367650384 |
Short name | T42 |
Test name | |
Test status | |
Simulation time | 923659127 ps |
CPU time | 3.16 seconds |
Started | Jun 05 05:40:13 PM PDT 24 |
Finished | Jun 05 05:40:17 PM PDT 24 |
Peak memory | 229064 kb |
Host | smart-c36ac76a-4fac-40c2-b32b-e755e474ad8b |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367650384 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.3367650384 |
Directory | /workspace/2.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/20.rv_dm_alert_test.4082067819 |
Short name | T175 |
Test name | |
Test status | |
Simulation time | 65457979 ps |
CPU time | 0.75 seconds |
Started | Jun 05 05:40:33 PM PDT 24 |
Finished | Jun 05 05:40:34 PM PDT 24 |
Peak memory | 204836 kb |
Host | smart-4823981f-6bea-4ef6-9230-299378a99111 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082067819 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.4082067819 |
Directory | /workspace/20.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/20.rv_dm_stress_all.3418436346 |
Short name | T143 |
Test name | |
Test status | |
Simulation time | 18060192084 ps |
CPU time | 10.95 seconds |
Started | Jun 05 05:40:32 PM PDT 24 |
Finished | Jun 05 05:40:44 PM PDT 24 |
Peak memory | 205020 kb |
Host | smart-7889cddd-96d5-4667-b3a4-76f995296390 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418436346 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.3418436346 |
Directory | /workspace/20.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/21.rv_dm_alert_test.2915212955 |
Short name | T152 |
Test name | |
Test status | |
Simulation time | 103267367 ps |
CPU time | 0.78 seconds |
Started | Jun 05 05:40:31 PM PDT 24 |
Finished | Jun 05 05:40:33 PM PDT 24 |
Peak memory | 204828 kb |
Host | smart-1f7769f1-f3a2-48d1-b7d1-587fe5cf3e7f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915212955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.2915212955 |
Directory | /workspace/21.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/21.rv_dm_stress_all.3157171791 |
Short name | T136 |
Test name | |
Test status | |
Simulation time | 11735136916 ps |
CPU time | 10.54 seconds |
Started | Jun 05 05:40:33 PM PDT 24 |
Finished | Jun 05 05:40:45 PM PDT 24 |
Peak memory | 205112 kb |
Host | smart-9c60a0ff-61b6-4445-b5f8-6b6be27885d6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157171791 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.3157171791 |
Directory | /workspace/21.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/22.rv_dm_alert_test.1244410437 |
Short name | T64 |
Test name | |
Test status | |
Simulation time | 94175203 ps |
CPU time | 0.72 seconds |
Started | Jun 05 05:40:35 PM PDT 24 |
Finished | Jun 05 05:40:36 PM PDT 24 |
Peak memory | 204848 kb |
Host | smart-9481c0bc-e6fc-4222-8e36-af2924e372fb |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244410437 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.1244410437 |
Directory | /workspace/22.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/23.rv_dm_alert_test.1188484322 |
Short name | T173 |
Test name | |
Test status | |
Simulation time | 50446005 ps |
CPU time | 0.81 seconds |
Started | Jun 05 05:40:33 PM PDT 24 |
Finished | Jun 05 05:40:35 PM PDT 24 |
Peak memory | 204828 kb |
Host | smart-e392477f-b9de-4fcf-8f6d-ba89016e75a3 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188484322 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.1188484322 |
Directory | /workspace/23.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/25.rv_dm_alert_test.4168134365 |
Short name | T172 |
Test name | |
Test status | |
Simulation time | 133854678 ps |
CPU time | 0.77 seconds |
Started | Jun 05 05:40:33 PM PDT 24 |
Finished | Jun 05 05:40:34 PM PDT 24 |
Peak memory | 204848 kb |
Host | smart-2f411c8d-9391-464a-9dd2-89d18c4884ae |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168134365 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.4168134365 |
Directory | /workspace/25.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/26.rv_dm_alert_test.1311835528 |
Short name | T158 |
Test name | |
Test status | |
Simulation time | 40526725 ps |
CPU time | 0.86 seconds |
Started | Jun 05 05:40:41 PM PDT 24 |
Finished | Jun 05 05:40:43 PM PDT 24 |
Peak memory | 204824 kb |
Host | smart-1b39130c-3ea3-41d3-8e09-0743430c558c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311835528 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.1311835528 |
Directory | /workspace/26.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/26.rv_dm_stress_all.4098007541 |
Short name | T37 |
Test name | |
Test status | |
Simulation time | 4933631407 ps |
CPU time | 14.33 seconds |
Started | Jun 05 05:40:33 PM PDT 24 |
Finished | Jun 05 05:40:48 PM PDT 24 |
Peak memory | 205020 kb |
Host | smart-9ca0e538-4f2f-4936-b2f0-f8045c44b1b3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098007541 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.4098007541 |
Directory | /workspace/26.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/27.rv_dm_alert_test.4220257081 |
Short name | T167 |
Test name | |
Test status | |
Simulation time | 69378885 ps |
CPU time | 0.83 seconds |
Started | Jun 05 05:40:40 PM PDT 24 |
Finished | Jun 05 05:40:41 PM PDT 24 |
Peak memory | 204836 kb |
Host | smart-c340a0e3-b0f5-4a8f-88fb-6c78e3e75bf4 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220257081 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.4220257081 |
Directory | /workspace/27.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/27.rv_dm_stress_all.2647527014 |
Short name | T31 |
Test name | |
Test status | |
Simulation time | 6855740489 ps |
CPU time | 7.57 seconds |
Started | Jun 05 05:40:38 PM PDT 24 |
Finished | Jun 05 05:40:47 PM PDT 24 |
Peak memory | 205080 kb |
Host | smart-794e358f-cb5a-4eff-b012-596b4adb2e62 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647527014 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.2647527014 |
Directory | /workspace/27.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/28.rv_dm_alert_test.614213091 |
Short name | T164 |
Test name | |
Test status | |
Simulation time | 90745294 ps |
CPU time | 0.83 seconds |
Started | Jun 05 05:40:39 PM PDT 24 |
Finished | Jun 05 05:40:40 PM PDT 24 |
Peak memory | 204808 kb |
Host | smart-3d18608f-62c1-412f-88ba-6270c1f0f84e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614213091 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.614213091 |
Directory | /workspace/28.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/28.rv_dm_stress_all.2045342688 |
Short name | T140 |
Test name | |
Test status | |
Simulation time | 3058106084 ps |
CPU time | 5.7 seconds |
Started | Jun 05 05:40:42 PM PDT 24 |
Finished | Jun 05 05:40:48 PM PDT 24 |
Peak memory | 205068 kb |
Host | smart-09730445-85ee-4b17-b369-667af2fe9211 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045342688 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.2045342688 |
Directory | /workspace/28.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/29.rv_dm_alert_test.3052706759 |
Short name | T24 |
Test name | |
Test status | |
Simulation time | 50232027 ps |
CPU time | 0.77 seconds |
Started | Jun 05 05:40:36 PM PDT 24 |
Finished | Jun 05 05:40:38 PM PDT 24 |
Peak memory | 204856 kb |
Host | smart-26f239ff-2ea2-44aa-89f0-f9ef061f5f60 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052706759 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.3052706759 |
Directory | /workspace/29.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/3.rv_dm_alert_test.928734573 |
Short name | T166 |
Test name | |
Test status | |
Simulation time | 32542045 ps |
CPU time | 0.76 seconds |
Started | Jun 05 05:40:19 PM PDT 24 |
Finished | Jun 05 05:40:21 PM PDT 24 |
Peak memory | 204860 kb |
Host | smart-24fed121-9965-4d9d-bef0-9e2c059c9916 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928734573 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.928734573 |
Directory | /workspace/3.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.1091300349 |
Short name | T19 |
Test name | |
Test status | |
Simulation time | 6704570093 ps |
CPU time | 6.19 seconds |
Started | Jun 05 05:40:09 PM PDT 24 |
Finished | Jun 05 05:40:16 PM PDT 24 |
Peak memory | 213620 kb |
Host | smart-9606d791-6f67-4869-bb2c-155e62369ed6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1091300349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.1091300349 |
Directory | /workspace/3.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.1335438490 |
Short name | T188 |
Test name | |
Test status | |
Simulation time | 6162320727 ps |
CPU time | 4.75 seconds |
Started | Jun 05 05:40:16 PM PDT 24 |
Finished | Jun 05 05:40:21 PM PDT 24 |
Peak memory | 205176 kb |
Host | smart-5a9ed0ee-4912-42b3-a6ec-c89e4039897b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1335438490 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.1335438490 |
Directory | /workspace/3.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.3916979488 |
Short name | T224 |
Test name | |
Test status | |
Simulation time | 11943884175 ps |
CPU time | 10.36 seconds |
Started | Jun 05 05:40:18 PM PDT 24 |
Finished | Jun 05 05:40:30 PM PDT 24 |
Peak memory | 205200 kb |
Host | smart-70bf02c3-27aa-4157-bcaa-7a46d97dce54 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3916979488 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t l_access.3916979488 |
Directory | /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_hart_unavail.807610546 |
Short name | T179 |
Test name | |
Test status | |
Simulation time | 611548429 ps |
CPU time | 1.93 seconds |
Started | Jun 05 05:40:10 PM PDT 24 |
Finished | Jun 05 05:40:13 PM PDT 24 |
Peak memory | 204596 kb |
Host | smart-bf2b89cb-a58d-4a13-a1fd-5bf6c7446734 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=807610546 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.807610546 |
Directory | /workspace/3.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/3.rv_dm_sba_tl_access.932954858 |
Short name | T250 |
Test name | |
Test status | |
Simulation time | 2751225358 ps |
CPU time | 2.89 seconds |
Started | Jun 05 05:40:10 PM PDT 24 |
Finished | Jun 05 05:40:14 PM PDT 24 |
Peak memory | 205200 kb |
Host | smart-d67f1838-4282-4bb3-b896-da8c5a92346e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=932954858 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.932954858 |
Directory | /workspace/3.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/30.rv_dm_alert_test.3752450816 |
Short name | T176 |
Test name | |
Test status | |
Simulation time | 95219727 ps |
CPU time | 0.96 seconds |
Started | Jun 05 05:40:39 PM PDT 24 |
Finished | Jun 05 05:40:40 PM PDT 24 |
Peak memory | 204848 kb |
Host | smart-b3e50184-4245-4ea5-9c61-26391da96fea |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752450816 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.3752450816 |
Directory | /workspace/30.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/31.rv_dm_alert_test.259193634 |
Short name | T23 |
Test name | |
Test status | |
Simulation time | 49249521 ps |
CPU time | 0.76 seconds |
Started | Jun 05 05:40:37 PM PDT 24 |
Finished | Jun 05 05:40:39 PM PDT 24 |
Peak memory | 204836 kb |
Host | smart-8259adc8-e85c-4850-8df6-ba3beeff9774 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259193634 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.259193634 |
Directory | /workspace/31.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/32.rv_dm_alert_test.2989662608 |
Short name | T117 |
Test name | |
Test status | |
Simulation time | 119289097 ps |
CPU time | 0.86 seconds |
Started | Jun 05 05:40:37 PM PDT 24 |
Finished | Jun 05 05:40:38 PM PDT 24 |
Peak memory | 204856 kb |
Host | smart-a04b2c1e-1d31-43d3-88ca-a392472b48e7 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989662608 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.2989662608 |
Directory | /workspace/32.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/33.rv_dm_alert_test.2104843691 |
Short name | T25 |
Test name | |
Test status | |
Simulation time | 91893332 ps |
CPU time | 0.89 seconds |
Started | Jun 05 05:40:36 PM PDT 24 |
Finished | Jun 05 05:40:38 PM PDT 24 |
Peak memory | 204708 kb |
Host | smart-0a3cbb41-78d3-4bcd-9c55-d0cac1c1a440 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104843691 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.2104843691 |
Directory | /workspace/33.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/33.rv_dm_stress_all.1653877899 |
Short name | T30 |
Test name | |
Test status | |
Simulation time | 7418408094 ps |
CPU time | 6.62 seconds |
Started | Jun 05 05:40:36 PM PDT 24 |
Finished | Jun 05 05:40:43 PM PDT 24 |
Peak memory | 205100 kb |
Host | smart-1f5abacb-a47f-484c-8254-02cb0c07d6e1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653877899 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.1653877899 |
Directory | /workspace/33.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/34.rv_dm_alert_test.957237267 |
Short name | T174 |
Test name | |
Test status | |
Simulation time | 67548733 ps |
CPU time | 0.76 seconds |
Started | Jun 05 05:40:42 PM PDT 24 |
Finished | Jun 05 05:40:43 PM PDT 24 |
Peak memory | 204856 kb |
Host | smart-7b4ec05c-e1ef-4c3d-a358-e1d98a5876f9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957237267 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.957237267 |
Directory | /workspace/34.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/34.rv_dm_stress_all.960421575 |
Short name | T142 |
Test name | |
Test status | |
Simulation time | 15980252800 ps |
CPU time | 14.25 seconds |
Started | Jun 05 05:40:36 PM PDT 24 |
Finished | Jun 05 05:40:51 PM PDT 24 |
Peak memory | 213412 kb |
Host | smart-ee6a4b1b-ce0f-4dae-88ab-31777eb0c66b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960421575 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.960421575 |
Directory | /workspace/34.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/35.rv_dm_alert_test.2284070922 |
Short name | T121 |
Test name | |
Test status | |
Simulation time | 89999465 ps |
CPU time | 0.75 seconds |
Started | Jun 05 05:40:40 PM PDT 24 |
Finished | Jun 05 05:40:41 PM PDT 24 |
Peak memory | 204836 kb |
Host | smart-fa27fc46-0859-4719-af40-5b3510bfb023 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284070922 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.2284070922 |
Directory | /workspace/35.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/36.rv_dm_alert_test.305392554 |
Short name | T157 |
Test name | |
Test status | |
Simulation time | 320618508 ps |
CPU time | 0.8 seconds |
Started | Jun 05 05:40:39 PM PDT 24 |
Finished | Jun 05 05:40:40 PM PDT 24 |
Peak memory | 204844 kb |
Host | smart-c35aab69-9997-4d0c-8bb8-4c5c9279cdc3 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305392554 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.305392554 |
Directory | /workspace/36.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/37.rv_dm_alert_test.2439679265 |
Short name | T161 |
Test name | |
Test status | |
Simulation time | 143815320 ps |
CPU time | 0.95 seconds |
Started | Jun 05 05:40:40 PM PDT 24 |
Finished | Jun 05 05:40:41 PM PDT 24 |
Peak memory | 204832 kb |
Host | smart-d5506614-9267-4de9-8385-f56ea4ff3565 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439679265 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.2439679265 |
Directory | /workspace/37.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/38.rv_dm_alert_test.3933813385 |
Short name | T160 |
Test name | |
Test status | |
Simulation time | 84914702 ps |
CPU time | 0.73 seconds |
Started | Jun 05 05:40:35 PM PDT 24 |
Finished | Jun 05 05:40:37 PM PDT 24 |
Peak memory | 204852 kb |
Host | smart-31f79d7c-23b8-487d-b2fa-c93d623dc583 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933813385 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.3933813385 |
Directory | /workspace/38.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/38.rv_dm_stress_all.2218746132 |
Short name | T5 |
Test name | |
Test status | |
Simulation time | 37500533446 ps |
CPU time | 13.53 seconds |
Started | Jun 05 05:40:36 PM PDT 24 |
Finished | Jun 05 05:40:51 PM PDT 24 |
Peak memory | 215492 kb |
Host | smart-d1af1a73-5941-4d70-afa3-8b18505f0246 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218746132 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.2218746132 |
Directory | /workspace/38.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/39.rv_dm_alert_test.3275536404 |
Short name | T177 |
Test name | |
Test status | |
Simulation time | 45640294 ps |
CPU time | 0.84 seconds |
Started | Jun 05 05:40:39 PM PDT 24 |
Finished | Jun 05 05:40:41 PM PDT 24 |
Peak memory | 204832 kb |
Host | smart-f4906455-d0a2-43e7-af3a-2ccf25d07ab6 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275536404 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.3275536404 |
Directory | /workspace/39.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/4.rv_dm_alert_test.3231182292 |
Short name | T169 |
Test name | |
Test status | |
Simulation time | 252377689 ps |
CPU time | 0.74 seconds |
Started | Jun 05 05:40:17 PM PDT 24 |
Finished | Jun 05 05:40:18 PM PDT 24 |
Peak memory | 204832 kb |
Host | smart-66254dad-48ec-423a-9e5b-a4c76dfeec81 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231182292 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.3231182292 |
Directory | /workspace/4.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.1384198836 |
Short name | T257 |
Test name | |
Test status | |
Simulation time | 36001035572 ps |
CPU time | 103.94 seconds |
Started | Jun 05 05:40:20 PM PDT 24 |
Finished | Jun 05 05:42:05 PM PDT 24 |
Peak memory | 213440 kb |
Host | smart-fb2a20bb-00ea-4818-b6d8-82e0e8c5e8a9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1384198836 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.1384198836 |
Directory | /workspace/4.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.2912169149 |
Short name | T229 |
Test name | |
Test status | |
Simulation time | 4264723909 ps |
CPU time | 11.57 seconds |
Started | Jun 05 05:40:18 PM PDT 24 |
Finished | Jun 05 05:40:31 PM PDT 24 |
Peak memory | 213404 kb |
Host | smart-4824a7db-cbe6-458b-8a15-778d790ed438 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2912169149 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.2912169149 |
Directory | /workspace/4.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.1664556149 |
Short name | T214 |
Test name | |
Test status | |
Simulation time | 1322408279 ps |
CPU time | 2 seconds |
Started | Jun 05 05:40:10 PM PDT 24 |
Finished | Jun 05 05:40:13 PM PDT 24 |
Peak memory | 205084 kb |
Host | smart-85f3822c-4ae1-475f-b8d1-5fa860a505df |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1664556149 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t l_access.1664556149 |
Directory | /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_hart_unavail.356075051 |
Short name | T192 |
Test name | |
Test status | |
Simulation time | 1059217383 ps |
CPU time | 3.01 seconds |
Started | Jun 05 05:40:09 PM PDT 24 |
Finished | Jun 05 05:40:13 PM PDT 24 |
Peak memory | 204584 kb |
Host | smart-2874a5f8-905d-48c1-91a8-184473408601 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=356075051 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.356075051 |
Directory | /workspace/4.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/4.rv_dm_sba_tl_access.3441072459 |
Short name | T225 |
Test name | |
Test status | |
Simulation time | 2858969534 ps |
CPU time | 5.43 seconds |
Started | Jun 05 05:40:09 PM PDT 24 |
Finished | Jun 05 05:40:15 PM PDT 24 |
Peak memory | 205156 kb |
Host | smart-b7c974cd-a246-4645-b8e2-a7676edaeb35 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3441072459 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.3441072459 |
Directory | /workspace/4.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_sec_cm.1077486699 |
Short name | T60 |
Test name | |
Test status | |
Simulation time | 2071075497 ps |
CPU time | 2.04 seconds |
Started | Jun 05 05:40:14 PM PDT 24 |
Finished | Jun 05 05:40:17 PM PDT 24 |
Peak memory | 229100 kb |
Host | smart-a4c61c61-1f32-45d9-ba6e-01993704f5d5 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077486699 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.1077486699 |
Directory | /workspace/4.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/40.rv_dm_alert_test.65517525 |
Short name | T21 |
Test name | |
Test status | |
Simulation time | 69648659 ps |
CPU time | 0.79 seconds |
Started | Jun 05 05:40:43 PM PDT 24 |
Finished | Jun 05 05:40:44 PM PDT 24 |
Peak memory | 204824 kb |
Host | smart-0531130a-c530-40eb-b21e-9677663ed865 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65517525 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.65517525 |
Directory | /workspace/40.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/41.rv_dm_alert_test.1632792314 |
Short name | T162 |
Test name | |
Test status | |
Simulation time | 81032490 ps |
CPU time | 0.82 seconds |
Started | Jun 05 05:40:40 PM PDT 24 |
Finished | Jun 05 05:40:41 PM PDT 24 |
Peak memory | 204832 kb |
Host | smart-cc95c224-b622-4c73-bf57-6f62fc0ea60e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632792314 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.1632792314 |
Directory | /workspace/41.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/42.rv_dm_alert_test.2727450242 |
Short name | T153 |
Test name | |
Test status | |
Simulation time | 80367890 ps |
CPU time | 0.75 seconds |
Started | Jun 05 05:40:46 PM PDT 24 |
Finished | Jun 05 05:40:48 PM PDT 24 |
Peak memory | 204844 kb |
Host | smart-9eb35185-fabc-4ee5-9981-1058d7cdc66d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727450242 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.2727450242 |
Directory | /workspace/42.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/42.rv_dm_stress_all.2573242736 |
Short name | T11 |
Test name | |
Test status | |
Simulation time | 12266537755 ps |
CPU time | 7.04 seconds |
Started | Jun 05 05:40:38 PM PDT 24 |
Finished | Jun 05 05:40:46 PM PDT 24 |
Peak memory | 205052 kb |
Host | smart-c42bd9ad-6a32-4321-a558-42eccd9a8c38 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573242736 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.2573242736 |
Directory | /workspace/42.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/43.rv_dm_alert_test.1825111144 |
Short name | T194 |
Test name | |
Test status | |
Simulation time | 112229810 ps |
CPU time | 0.8 seconds |
Started | Jun 05 05:40:47 PM PDT 24 |
Finished | Jun 05 05:40:49 PM PDT 24 |
Peak memory | 204728 kb |
Host | smart-878dc2d9-15b6-4c6d-8d86-37d09e672067 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825111144 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.1825111144 |
Directory | /workspace/43.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/44.rv_dm_alert_test.699235540 |
Short name | T150 |
Test name | |
Test status | |
Simulation time | 98461487 ps |
CPU time | 0.74 seconds |
Started | Jun 05 05:40:46 PM PDT 24 |
Finished | Jun 05 05:40:47 PM PDT 24 |
Peak memory | 204840 kb |
Host | smart-3fe65fc0-6c6a-46c1-9979-2f8ef8156c73 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699235540 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.699235540 |
Directory | /workspace/44.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/44.rv_dm_stress_all.1078052428 |
Short name | T139 |
Test name | |
Test status | |
Simulation time | 18272322213 ps |
CPU time | 26.89 seconds |
Started | Jun 05 05:40:43 PM PDT 24 |
Finished | Jun 05 05:41:11 PM PDT 24 |
Peak memory | 205016 kb |
Host | smart-81876f2a-0f81-47e8-93a1-dfdd9759c881 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078052428 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.1078052428 |
Directory | /workspace/44.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/45.rv_dm_alert_test.2637668217 |
Short name | T151 |
Test name | |
Test status | |
Simulation time | 119549820 ps |
CPU time | 1.06 seconds |
Started | Jun 05 05:40:46 PM PDT 24 |
Finished | Jun 05 05:40:47 PM PDT 24 |
Peak memory | 204848 kb |
Host | smart-b53aa024-a5d5-448a-b177-79f5af07c46f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637668217 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.2637668217 |
Directory | /workspace/45.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/46.rv_dm_alert_test.2413059278 |
Short name | T79 |
Test name | |
Test status | |
Simulation time | 54000445 ps |
CPU time | 0.72 seconds |
Started | Jun 05 05:40:43 PM PDT 24 |
Finished | Jun 05 05:40:45 PM PDT 24 |
Peak memory | 204852 kb |
Host | smart-86744be5-69eb-41f6-afbc-a27f81e74c1d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413059278 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.2413059278 |
Directory | /workspace/46.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/46.rv_dm_stress_all.47141913 |
Short name | T238 |
Test name | |
Test status | |
Simulation time | 13237537299 ps |
CPU time | 13.41 seconds |
Started | Jun 05 05:40:45 PM PDT 24 |
Finished | Jun 05 05:40:59 PM PDT 24 |
Peak memory | 205112 kb |
Host | smart-ccc33cad-8749-414b-b007-92dd4b028fa2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47141913 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.47141913 |
Directory | /workspace/46.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/48.rv_dm_alert_test.3549984662 |
Short name | T163 |
Test name | |
Test status | |
Simulation time | 134115062 ps |
CPU time | 1.04 seconds |
Started | Jun 05 05:40:44 PM PDT 24 |
Finished | Jun 05 05:40:46 PM PDT 24 |
Peak memory | 204808 kb |
Host | smart-7653c658-b68b-485b-8f4a-c8c694ce7bbb |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549984662 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.3549984662 |
Directory | /workspace/48.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/49.rv_dm_alert_test.715176243 |
Short name | T165 |
Test name | |
Test status | |
Simulation time | 108896781 ps |
CPU time | 1 seconds |
Started | Jun 05 05:40:44 PM PDT 24 |
Finished | Jun 05 05:40:46 PM PDT 24 |
Peak memory | 205032 kb |
Host | smart-4769cfd1-aba4-4663-a5c7-87c16756b198 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715176243 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.715176243 |
Directory | /workspace/49.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/5.rv_dm_alert_test.1363020415 |
Short name | T232 |
Test name | |
Test status | |
Simulation time | 37799458 ps |
CPU time | 0.75 seconds |
Started | Jun 05 05:40:23 PM PDT 24 |
Finished | Jun 05 05:40:24 PM PDT 24 |
Peak memory | 204704 kb |
Host | smart-30b88c6d-3a0a-4198-a7fa-52f99d2a3a02 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363020415 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.1363020415 |
Directory | /workspace/5.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.4254417719 |
Short name | T203 |
Test name | |
Test status | |
Simulation time | 23465453540 ps |
CPU time | 24.77 seconds |
Started | Jun 05 05:40:18 PM PDT 24 |
Finished | Jun 05 05:40:44 PM PDT 24 |
Peak memory | 213468 kb |
Host | smart-bfce1e3a-9916-42c9-86a3-a5d9afcb75e5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4254417719 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.4254417719 |
Directory | /workspace/5.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.1440100434 |
Short name | T195 |
Test name | |
Test status | |
Simulation time | 2329500404 ps |
CPU time | 4.38 seconds |
Started | Jun 05 05:40:14 PM PDT 24 |
Finished | Jun 05 05:40:19 PM PDT 24 |
Peak memory | 205188 kb |
Host | smart-91128fa3-0dfd-4205-9abe-05fd130cfbc8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1440100434 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.1440100434 |
Directory | /workspace/5.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.250800420 |
Short name | T227 |
Test name | |
Test status | |
Simulation time | 1547866336 ps |
CPU time | 1.64 seconds |
Started | Jun 05 05:40:19 PM PDT 24 |
Finished | Jun 05 05:40:22 PM PDT 24 |
Peak memory | 205048 kb |
Host | smart-0700f511-79aa-449d-b11c-1819ffe25baf |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=250800420 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_tl _access.250800420 |
Directory | /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_sba_tl_access.2117384183 |
Short name | T231 |
Test name | |
Test status | |
Simulation time | 4721528969 ps |
CPU time | 14.87 seconds |
Started | Jun 05 05:40:20 PM PDT 24 |
Finished | Jun 05 05:40:36 PM PDT 24 |
Peak memory | 205268 kb |
Host | smart-55ff3696-3e20-4b1e-9165-512f88acef6f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2117384183 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.2117384183 |
Directory | /workspace/5.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_stress_all.4068021810 |
Short name | T8 |
Test name | |
Test status | |
Simulation time | 31504571955 ps |
CPU time | 23.4 seconds |
Started | Jun 05 05:40:11 PM PDT 24 |
Finished | Jun 05 05:40:35 PM PDT 24 |
Peak memory | 205108 kb |
Host | smart-d0f0edf4-3c3f-4c44-8864-bfa5959dc51d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068021810 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.4068021810 |
Directory | /workspace/5.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/6.rv_dm_alert_test.1201681758 |
Short name | T26 |
Test name | |
Test status | |
Simulation time | 81551375 ps |
CPU time | 0.82 seconds |
Started | Jun 05 05:40:20 PM PDT 24 |
Finished | Jun 05 05:40:22 PM PDT 24 |
Peak memory | 205016 kb |
Host | smart-6d8f0bb4-e4f5-42ae-9268-0f68998998e8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201681758 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.1201681758 |
Directory | /workspace/6.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.2322575476 |
Short name | T207 |
Test name | |
Test status | |
Simulation time | 97699868930 ps |
CPU time | 88.25 seconds |
Started | Jun 05 05:40:18 PM PDT 24 |
Finished | Jun 05 05:41:47 PM PDT 24 |
Peak memory | 221632 kb |
Host | smart-f568363b-fd70-4af0-84bf-ce661642f736 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2322575476 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.2322575476 |
Directory | /workspace/6.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.3541583510 |
Short name | T185 |
Test name | |
Test status | |
Simulation time | 15604205996 ps |
CPU time | 34.79 seconds |
Started | Jun 05 05:40:27 PM PDT 24 |
Finished | Jun 05 05:41:02 PM PDT 24 |
Peak memory | 205224 kb |
Host | smart-d6bb06bb-32cc-4f17-9935-dcc401ab1dcd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3541583510 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.3541583510 |
Directory | /workspace/6.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.1505876742 |
Short name | T247 |
Test name | |
Test status | |
Simulation time | 6017596108 ps |
CPU time | 8.82 seconds |
Started | Jun 05 05:40:27 PM PDT 24 |
Finished | Jun 05 05:40:37 PM PDT 24 |
Peak memory | 205208 kb |
Host | smart-c68d3bbd-ca87-4cd2-b2cd-320816404741 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1505876742 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t l_access.1505876742 |
Directory | /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_sba_tl_access.373679885 |
Short name | T219 |
Test name | |
Test status | |
Simulation time | 3112221386 ps |
CPU time | 5.09 seconds |
Started | Jun 05 05:40:16 PM PDT 24 |
Finished | Jun 05 05:40:22 PM PDT 24 |
Peak memory | 205240 kb |
Host | smart-c4fd4341-74c7-414a-b9cc-cbe994a153e8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=373679885 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.373679885 |
Directory | /workspace/6.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_alert_test.3497467651 |
Short name | T155 |
Test name | |
Test status | |
Simulation time | 100585548 ps |
CPU time | 0.76 seconds |
Started | Jun 05 05:40:22 PM PDT 24 |
Finished | Jun 05 05:40:23 PM PDT 24 |
Peak memory | 204848 kb |
Host | smart-ead5f7c0-ad8f-453f-8807-8933284761fe |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497467651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.3497467651 |
Directory | /workspace/7.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.2943417643 |
Short name | T216 |
Test name | |
Test status | |
Simulation time | 75362526767 ps |
CPU time | 192.2 seconds |
Started | Jun 05 05:40:18 PM PDT 24 |
Finished | Jun 05 05:43:32 PM PDT 24 |
Peak memory | 215524 kb |
Host | smart-59bc0755-8b87-4813-9f83-a9a336418f6a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2943417643 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.2943417643 |
Directory | /workspace/7.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.1631475688 |
Short name | T191 |
Test name | |
Test status | |
Simulation time | 4700744037 ps |
CPU time | 7.14 seconds |
Started | Jun 05 05:40:23 PM PDT 24 |
Finished | Jun 05 05:40:31 PM PDT 24 |
Peak memory | 205272 kb |
Host | smart-caace4ff-c40f-40c8-98fd-09bf8c1383d0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1631475688 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.1631475688 |
Directory | /workspace/7.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.3512429545 |
Short name | T261 |
Test name | |
Test status | |
Simulation time | 4670208373 ps |
CPU time | 7.39 seconds |
Started | Jun 05 05:40:17 PM PDT 24 |
Finished | Jun 05 05:40:25 PM PDT 24 |
Peak memory | 205224 kb |
Host | smart-cc02374f-7e54-4cb2-bf91-79933921466f |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3512429545 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t l_access.3512429545 |
Directory | /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_sba_tl_access.4282810213 |
Short name | T196 |
Test name | |
Test status | |
Simulation time | 4337119415 ps |
CPU time | 4.37 seconds |
Started | Jun 05 05:40:22 PM PDT 24 |
Finished | Jun 05 05:40:28 PM PDT 24 |
Peak memory | 205196 kb |
Host | smart-b852be34-478e-429f-8394-535b4db41714 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4282810213 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.4282810213 |
Directory | /workspace/7.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_alert_test.3686007156 |
Short name | T263 |
Test name | |
Test status | |
Simulation time | 151166871 ps |
CPU time | 0.74 seconds |
Started | Jun 05 05:40:19 PM PDT 24 |
Finished | Jun 05 05:40:21 PM PDT 24 |
Peak memory | 204856 kb |
Host | smart-a5e85386-38b1-4a0c-955a-45612727f361 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686007156 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.3686007156 |
Directory | /workspace/8.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.1421453604 |
Short name | T215 |
Test name | |
Test status | |
Simulation time | 21800122169 ps |
CPU time | 21.23 seconds |
Started | Jun 05 05:40:15 PM PDT 24 |
Finished | Jun 05 05:40:37 PM PDT 24 |
Peak memory | 217472 kb |
Host | smart-4e5e0cb4-f9dd-4d18-bfe3-733665ffaffa |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1421453604 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.1421453604 |
Directory | /workspace/8.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.2021125763 |
Short name | T63 |
Test name | |
Test status | |
Simulation time | 5750490540 ps |
CPU time | 9.33 seconds |
Started | Jun 05 05:40:16 PM PDT 24 |
Finished | Jun 05 05:40:27 PM PDT 24 |
Peak memory | 205208 kb |
Host | smart-381acdd3-e74a-45cb-8f47-477095bbba8a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2021125763 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.2021125763 |
Directory | /workspace/8.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.383466046 |
Short name | T258 |
Test name | |
Test status | |
Simulation time | 2688792915 ps |
CPU time | 3.16 seconds |
Started | Jun 05 05:40:17 PM PDT 24 |
Finished | Jun 05 05:40:22 PM PDT 24 |
Peak memory | 205204 kb |
Host | smart-17a08c47-7ace-4cc3-b6bb-14ecbe3f7206 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=383466046 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_tl _access.383466046 |
Directory | /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_sba_tl_access.1929865187 |
Short name | T186 |
Test name | |
Test status | |
Simulation time | 7460936586 ps |
CPU time | 12.48 seconds |
Started | Jun 05 05:40:22 PM PDT 24 |
Finished | Jun 05 05:40:35 PM PDT 24 |
Peak memory | 205172 kb |
Host | smart-54b58010-6192-43e6-902c-7a943028fc1e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1929865187 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.1929865187 |
Directory | /workspace/8.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_stress_all.3344642871 |
Short name | T7 |
Test name | |
Test status | |
Simulation time | 23339632979 ps |
CPU time | 16.99 seconds |
Started | Jun 05 05:40:26 PM PDT 24 |
Finished | Jun 05 05:40:44 PM PDT 24 |
Peak memory | 213292 kb |
Host | smart-eeb2af99-1131-4e18-8c90-28e9773fcec5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344642871 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.3344642871 |
Directory | /workspace/8.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/9.rv_dm_alert_test.300581970 |
Short name | T171 |
Test name | |
Test status | |
Simulation time | 45629377 ps |
CPU time | 0.72 seconds |
Started | Jun 05 05:40:24 PM PDT 24 |
Finished | Jun 05 05:40:25 PM PDT 24 |
Peak memory | 204852 kb |
Host | smart-aeb0a01d-285e-4def-b11f-d6214bb20e33 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300581970 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.300581970 |
Directory | /workspace/9.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.2160964206 |
Short name | T212 |
Test name | |
Test status | |
Simulation time | 1543251510 ps |
CPU time | 3.28 seconds |
Started | Jun 05 05:40:21 PM PDT 24 |
Finished | Jun 05 05:40:25 PM PDT 24 |
Peak memory | 205132 kb |
Host | smart-8651a3c7-adc2-4175-88a8-7cd87f18adb5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2160964206 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.2160964206 |
Directory | /workspace/9.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.689331741 |
Short name | T204 |
Test name | |
Test status | |
Simulation time | 16432666355 ps |
CPU time | 8.53 seconds |
Started | Jun 05 05:40:24 PM PDT 24 |
Finished | Jun 05 05:40:34 PM PDT 24 |
Peak memory | 205200 kb |
Host | smart-e8c375ac-7a07-4724-8e73-f2ac5f4d1680 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=689331741 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_tl _access.689331741 |
Directory | /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_sba_tl_access.4095444935 |
Short name | T180 |
Test name | |
Test status | |
Simulation time | 2400391027 ps |
CPU time | 7.73 seconds |
Started | Jun 05 05:40:17 PM PDT 24 |
Finished | Jun 05 05:40:26 PM PDT 24 |
Peak memory | 205248 kb |
Host | smart-7fcdb25e-ca29-42c2-8700-07e3f9174e8f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4095444935 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.4095444935 |
Directory | /workspace/9.rv_dm_sba_tl_access/latest |
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