SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
79.71 | 94.96 | 79.95 | 86.17 | 71.79 | 84.83 | 97.89 | 42.40 |
T30 | /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.805707704 | Jun 07 08:24:07 PM PDT 24 | Jun 07 08:25:01 PM PDT 24 | 73634880049 ps | ||
T99 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3829790317 | Jun 07 08:23:51 PM PDT 24 | Jun 07 08:25:09 PM PDT 24 | 3522118319 ps | ||
T107 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.3946762256 | Jun 07 08:24:08 PM PDT 24 | Jun 07 08:24:11 PM PDT 24 | 65190353 ps | ||
T31 | /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.3945123285 | Jun 07 08:24:08 PM PDT 24 | Jun 07 08:25:14 PM PDT 24 | 42405009421 ps | ||
T290 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.1732854552 | Jun 07 08:23:48 PM PDT 24 | Jun 07 08:23:51 PM PDT 24 | 387468961 ps | ||
T291 | /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1959584622 | Jun 07 08:24:09 PM PDT 24 | Jun 07 08:24:13 PM PDT 24 | 134349070 ps | ||
T108 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.3681596289 | Jun 07 08:23:58 PM PDT 24 | Jun 07 08:25:19 PM PDT 24 | 4258902438 ps | ||
T141 | /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.1521331936 | Jun 07 08:23:59 PM PDT 24 | Jun 07 08:25:43 PM PDT 24 | 75661029372 ps | ||
T292 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2917162549 | Jun 07 08:23:57 PM PDT 24 | Jun 07 08:24:00 PM PDT 24 | 911639825 ps | ||
T293 | /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.3866950992 | Jun 07 08:24:09 PM PDT 24 | Jun 07 08:24:17 PM PDT 24 | 3836608595 ps | ||
T137 | /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.2120912212 | Jun 07 08:24:17 PM PDT 24 | Jun 07 08:24:36 PM PDT 24 | 3408994293 ps | ||
T294 | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.1865667583 | Jun 07 08:24:16 PM PDT 24 | Jun 07 08:24:36 PM PDT 24 | 10022985248 ps | ||
T295 | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.1675236135 | Jun 07 08:24:20 PM PDT 24 | Jun 07 08:24:25 PM PDT 24 | 319981063 ps | ||
T296 | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.2847122705 | Jun 07 08:24:19 PM PDT 24 | Jun 07 08:24:25 PM PDT 24 | 4549434367 ps | ||
T297 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.578495854 | Jun 07 08:24:08 PM PDT 24 | Jun 07 08:24:45 PM PDT 24 | 9837883806 ps | ||
T298 | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.978652773 | Jun 07 08:24:07 PM PDT 24 | Jun 07 08:24:28 PM PDT 24 | 11687060693 ps | ||
T128 | /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3237833505 | Jun 07 08:24:08 PM PDT 24 | Jun 07 08:24:33 PM PDT 24 | 5783028341 ps | ||
T100 | /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.2018018867 | Jun 07 08:24:09 PM PDT 24 | Jun 07 08:24:14 PM PDT 24 | 141924008 ps | ||
T299 | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.1055149012 | Jun 07 08:24:12 PM PDT 24 | Jun 07 08:24:14 PM PDT 24 | 896061818 ps | ||
T300 | /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.3246084727 | Jun 07 08:24:20 PM PDT 24 | Jun 07 08:24:26 PM PDT 24 | 418130066 ps | ||
T301 | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.3103198577 | Jun 07 08:24:21 PM PDT 24 | Jun 07 08:24:27 PM PDT 24 | 125091867 ps | ||
T302 | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.6120616 | Jun 07 08:24:16 PM PDT 24 | Jun 07 08:24:19 PM PDT 24 | 185264339 ps | ||
T303 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.276365057 | Jun 07 08:23:57 PM PDT 24 | Jun 07 08:24:35 PM PDT 24 | 13511893958 ps | ||
T304 | /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1196221160 | Jun 07 08:24:22 PM PDT 24 | Jun 07 08:24:30 PM PDT 24 | 4279197571 ps | ||
T305 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1011305893 | Jun 07 08:23:50 PM PDT 24 | Jun 07 08:24:55 PM PDT 24 | 126834680318 ps | ||
T306 | /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1544619862 | Jun 07 08:23:58 PM PDT 24 | Jun 07 08:24:00 PM PDT 24 | 63941369 ps | ||
T307 | /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.3288972488 | Jun 07 08:23:46 PM PDT 24 | Jun 07 08:23:47 PM PDT 24 | 72535940 ps | ||
T308 | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3456067664 | Jun 07 08:24:10 PM PDT 24 | Jun 07 08:24:19 PM PDT 24 | 2593470790 ps | ||
T309 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.3362771517 | Jun 07 08:23:51 PM PDT 24 | Jun 07 08:23:58 PM PDT 24 | 5711163342 ps | ||
T109 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.1401316391 | Jun 07 08:23:59 PM PDT 24 | Jun 07 08:24:02 PM PDT 24 | 279793646 ps | ||
T310 | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.3189053630 | Jun 07 08:24:18 PM PDT 24 | Jun 07 08:24:24 PM PDT 24 | 9133229465 ps | ||
T311 | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.484044282 | Jun 07 08:24:19 PM PDT 24 | Jun 07 08:25:09 PM PDT 24 | 18737747339 ps | ||
T312 | /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.817069684 | Jun 07 08:24:16 PM PDT 24 | Jun 07 08:24:23 PM PDT 24 | 242859319 ps | ||
T313 | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3580768558 | Jun 07 08:24:19 PM PDT 24 | Jun 07 08:24:24 PM PDT 24 | 1319946411 ps | ||
T314 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.3111646869 | Jun 07 08:23:47 PM PDT 24 | Jun 07 08:24:10 PM PDT 24 | 13956355002 ps | ||
T315 | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.3103063440 | Jun 07 08:24:07 PM PDT 24 | Jun 07 08:24:12 PM PDT 24 | 690405114 ps | ||
T316 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3664676749 | Jun 07 08:23:56 PM PDT 24 | Jun 07 08:23:58 PM PDT 24 | 415056107 ps | ||
T317 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.498464221 | Jun 07 08:23:51 PM PDT 24 | Jun 07 08:23:59 PM PDT 24 | 2058859337 ps | ||
T116 | /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3592077057 | Jun 07 08:24:05 PM PDT 24 | Jun 07 08:24:11 PM PDT 24 | 342973679 ps | ||
T318 | /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.2602704247 | Jun 07 08:24:19 PM PDT 24 | Jun 07 08:24:33 PM PDT 24 | 3281316227 ps | ||
T319 | /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.2587805837 | Jun 07 08:24:10 PM PDT 24 | Jun 07 08:24:15 PM PDT 24 | 87302975 ps | ||
T320 | /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1354410744 | Jun 07 08:24:21 PM PDT 24 | Jun 07 08:24:34 PM PDT 24 | 4105665910 ps | ||
T110 | /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.318222380 | Jun 07 08:24:19 PM PDT 24 | Jun 07 08:24:24 PM PDT 24 | 213257887 ps | ||
T321 | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.145042091 | Jun 07 08:24:17 PM PDT 24 | Jun 07 08:24:19 PM PDT 24 | 101017115 ps | ||
T322 | /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.2547324690 | Jun 07 08:24:05 PM PDT 24 | Jun 07 08:25:10 PM PDT 24 | 77734918996 ps | ||
T135 | /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1885799579 | Jun 07 08:24:19 PM PDT 24 | Jun 07 08:24:35 PM PDT 24 | 2847861496 ps | ||
T111 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.1103529833 | Jun 07 08:24:04 PM PDT 24 | Jun 07 08:24:33 PM PDT 24 | 1448906743 ps | ||
T323 | /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2451174081 | Jun 07 08:23:50 PM PDT 24 | Jun 07 08:23:52 PM PDT 24 | 130994108 ps | ||
T324 | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.1116199627 | Jun 07 08:24:08 PM PDT 24 | Jun 07 08:24:12 PM PDT 24 | 2532204511 ps | ||
T325 | /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1157278392 | Jun 07 08:24:21 PM PDT 24 | Jun 07 08:24:29 PM PDT 24 | 272732444 ps | ||
T326 | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.792837579 | Jun 07 08:24:19 PM PDT 24 | Jun 07 08:24:25 PM PDT 24 | 355547233 ps | ||
T327 | /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.2031152770 | Jun 07 08:24:09 PM PDT 24 | Jun 07 08:24:33 PM PDT 24 | 26003017935 ps | ||
T328 | /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.745639274 | Jun 07 08:24:07 PM PDT 24 | Jun 07 08:24:11 PM PDT 24 | 945017553 ps | ||
T329 | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1691139783 | Jun 07 08:24:17 PM PDT 24 | Jun 07 08:24:25 PM PDT 24 | 3017341368 ps | ||
T330 | /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.3399709393 | Jun 07 08:24:19 PM PDT 24 | Jun 07 08:24:24 PM PDT 24 | 294749882 ps | ||
T117 | /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1172827432 | Jun 07 08:24:09 PM PDT 24 | Jun 07 08:24:18 PM PDT 24 | 1538680002 ps | ||
T331 | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.587452714 | Jun 07 08:24:07 PM PDT 24 | Jun 07 08:24:43 PM PDT 24 | 23853961398 ps | ||
T101 | /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3407068116 | Jun 07 08:24:18 PM PDT 24 | Jun 07 08:24:30 PM PDT 24 | 920402212 ps | ||
T129 | /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.763832992 | Jun 07 08:24:00 PM PDT 24 | Jun 07 08:24:10 PM PDT 24 | 571181265 ps | ||
T139 | /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.1401968570 | Jun 07 08:23:58 PM PDT 24 | Jun 07 08:24:20 PM PDT 24 | 3208288712 ps | ||
T138 | /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.894814008 | Jun 07 08:24:18 PM PDT 24 | Jun 07 08:24:48 PM PDT 24 | 4346145533 ps | ||
T332 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.3108270417 | Jun 07 08:23:50 PM PDT 24 | Jun 07 08:24:18 PM PDT 24 | 9444546364 ps | ||
T333 | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.648089281 | Jun 07 08:24:19 PM PDT 24 | Jun 07 08:24:28 PM PDT 24 | 1764775052 ps | ||
T102 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.182681316 | Jun 07 08:23:51 PM PDT 24 | Jun 07 08:24:25 PM PDT 24 | 1688960414 ps | ||
T132 | /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.82861361 | Jun 07 08:24:09 PM PDT 24 | Jun 07 08:24:21 PM PDT 24 | 2247817035 ps | ||
T334 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.945447064 | Jun 07 08:23:48 PM PDT 24 | Jun 07 08:23:58 PM PDT 24 | 5283728211 ps | ||
T335 | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.2864224181 | Jun 07 08:24:19 PM PDT 24 | Jun 07 08:24:37 PM PDT 24 | 18654133142 ps | ||
T118 | /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.4103482684 | Jun 07 08:24:24 PM PDT 24 | Jun 07 08:24:34 PM PDT 24 | 1920692769 ps | ||
T336 | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.131289115 | Jun 07 08:24:18 PM PDT 24 | Jun 07 08:24:21 PM PDT 24 | 342999126 ps | ||
T337 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.2104973374 | Jun 07 08:23:51 PM PDT 24 | Jun 07 08:23:55 PM PDT 24 | 570222356 ps | ||
T338 | /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.4073494971 | Jun 07 08:24:17 PM PDT 24 | Jun 07 08:24:24 PM PDT 24 | 595101563 ps | ||
T339 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.2324220812 | Jun 07 08:23:51 PM PDT 24 | Jun 07 08:23:55 PM PDT 24 | 543313182 ps | ||
T340 | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.3668104969 | Jun 07 08:24:06 PM PDT 24 | Jun 07 08:24:28 PM PDT 24 | 10508399134 ps | ||
T341 | /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.2165058584 | Jun 07 08:24:18 PM PDT 24 | Jun 07 08:24:24 PM PDT 24 | 102695191 ps | ||
T119 | /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.2412159336 | Jun 07 08:24:19 PM PDT 24 | Jun 07 08:24:27 PM PDT 24 | 3753326623 ps | ||
T103 | /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.60706732 | Jun 07 08:24:19 PM PDT 24 | Jun 07 08:24:26 PM PDT 24 | 89017173 ps | ||
T342 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.1599749951 | Jun 07 08:24:08 PM PDT 24 | Jun 07 08:24:20 PM PDT 24 | 13345492935 ps | ||
T343 | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.1177089889 | Jun 07 08:24:07 PM PDT 24 | Jun 07 08:24:16 PM PDT 24 | 8091547113 ps | ||
T344 | /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.3455569231 | Jun 07 08:23:49 PM PDT 24 | Jun 07 08:23:52 PM PDT 24 | 145980855 ps | ||
T345 | /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.4268338258 | Jun 07 08:24:09 PM PDT 24 | Jun 07 08:24:19 PM PDT 24 | 595561986 ps | ||
T112 | /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2823950924 | Jun 07 08:24:17 PM PDT 24 | Jun 07 08:24:20 PM PDT 24 | 190749257 ps | ||
T136 | /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.43163994 | Jun 07 08:24:19 PM PDT 24 | Jun 07 08:24:41 PM PDT 24 | 1724694973 ps | ||
T346 | /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.1503170793 | Jun 07 08:24:18 PM PDT 24 | Jun 07 08:24:23 PM PDT 24 | 258278757 ps | ||
T347 | /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.3323603692 | Jun 07 08:24:07 PM PDT 24 | Jun 07 08:24:14 PM PDT 24 | 2376139272 ps | ||
T140 | /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.727621557 | Jun 07 08:24:27 PM PDT 24 | Jun 07 08:24:40 PM PDT 24 | 3216936809 ps | ||
T348 | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.2451451544 | Jun 07 08:24:19 PM PDT 24 | Jun 07 08:24:43 PM PDT 24 | 15612796083 ps | ||
T349 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3049201205 | Jun 07 08:23:46 PM PDT 24 | Jun 07 08:23:49 PM PDT 24 | 2470719675 ps | ||
T350 | /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3669637308 | Jun 07 08:24:23 PM PDT 24 | Jun 07 08:24:29 PM PDT 24 | 378496216 ps | ||
T351 | /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.694286217 | Jun 07 08:24:16 PM PDT 24 | Jun 07 08:24:20 PM PDT 24 | 412929295 ps | ||
T352 | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3408495102 | Jun 07 08:24:18 PM PDT 24 | Jun 07 08:24:50 PM PDT 24 | 10369543696 ps | ||
T93 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2982452700 | Jun 07 08:23:49 PM PDT 24 | Jun 07 08:24:09 PM PDT 24 | 10508800839 ps | ||
T353 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3998116800 | Jun 07 08:23:48 PM PDT 24 | Jun 07 08:23:51 PM PDT 24 | 597490894 ps | ||
T104 | /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.3683158180 | Jun 07 08:24:07 PM PDT 24 | Jun 07 08:24:17 PM PDT 24 | 9111991832 ps | ||
T354 | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1888535395 | Jun 07 08:24:08 PM PDT 24 | Jun 07 08:24:13 PM PDT 24 | 862132944 ps | ||
T355 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3832855657 | Jun 07 08:23:48 PM PDT 24 | Jun 07 08:23:50 PM PDT 24 | 225437148 ps | ||
T356 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2131935031 | Jun 07 08:23:51 PM PDT 24 | Jun 07 08:24:49 PM PDT 24 | 41219909167 ps | ||
T105 | /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.1504203288 | Jun 07 08:24:17 PM PDT 24 | Jun 07 08:24:22 PM PDT 24 | 325851186 ps | ||
T357 | /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.809542712 | Jun 07 08:24:19 PM PDT 24 | Jun 07 08:24:31 PM PDT 24 | 563788195 ps | ||
T358 | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2271672567 | Jun 07 08:24:18 PM PDT 24 | Jun 07 08:24:22 PM PDT 24 | 703728755 ps | ||
T359 | /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.818729266 | Jun 07 08:24:17 PM PDT 24 | Jun 07 08:24:21 PM PDT 24 | 333942512 ps | ||
T360 | /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.1678287099 | Jun 07 08:24:20 PM PDT 24 | Jun 07 08:24:26 PM PDT 24 | 174560984 ps | ||
T361 | /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.1539345084 | Jun 07 08:24:07 PM PDT 24 | Jun 07 08:24:11 PM PDT 24 | 132103297 ps | ||
T362 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1758498034 | Jun 07 08:23:52 PM PDT 24 | Jun 07 08:24:07 PM PDT 24 | 29369498509 ps | ||
T113 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1472815312 | Jun 07 08:24:04 PM PDT 24 | Jun 07 08:24:07 PM PDT 24 | 89921424 ps | ||
T363 | /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.3769323429 | Jun 07 08:23:47 PM PDT 24 | Jun 07 08:23:52 PM PDT 24 | 383917664 ps | ||
T364 | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.2400269995 | Jun 07 08:24:21 PM PDT 24 | Jun 07 08:24:39 PM PDT 24 | 44803012317 ps | ||
T365 | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.3396956174 | Jun 07 08:24:24 PM PDT 24 | Jun 07 08:24:29 PM PDT 24 | 2835424567 ps | ||
T366 | /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.676647432 | Jun 07 08:24:19 PM PDT 24 | Jun 07 08:24:25 PM PDT 24 | 56230624 ps | ||
T367 | /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.1033556964 | Jun 07 08:24:18 PM PDT 24 | Jun 07 08:24:26 PM PDT 24 | 556393399 ps | ||
T368 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.3612522507 | Jun 07 08:23:49 PM PDT 24 | Jun 07 08:24:00 PM PDT 24 | 5522622020 ps | ||
T369 | /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.2275211875 | Jun 07 08:24:15 PM PDT 24 | Jun 07 08:24:20 PM PDT 24 | 839417380 ps | ||
T370 | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3992154863 | Jun 07 08:24:19 PM PDT 24 | Jun 07 08:24:25 PM PDT 24 | 342120708 ps | ||
T371 | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.4112550351 | Jun 07 08:24:20 PM PDT 24 | Jun 07 08:24:26 PM PDT 24 | 451631247 ps | ||
T372 | /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.1944657403 | Jun 07 08:23:59 PM PDT 24 | Jun 07 08:24:01 PM PDT 24 | 163244433 ps | ||
T373 | /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.57845883 | Jun 07 08:24:18 PM PDT 24 | Jun 07 08:24:24 PM PDT 24 | 91467020 ps | ||
T374 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1503173491 | Jun 07 08:23:48 PM PDT 24 | Jun 07 08:23:51 PM PDT 24 | 607190766 ps | ||
T106 | /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.2995768393 | Jun 07 08:24:18 PM PDT 24 | Jun 07 08:24:24 PM PDT 24 | 166446460 ps | ||
T375 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2000568787 | Jun 07 08:24:11 PM PDT 24 | Jun 07 08:24:14 PM PDT 24 | 642546686 ps | ||
T133 | /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.115065762 | Jun 07 08:24:19 PM PDT 24 | Jun 07 08:24:49 PM PDT 24 | 4168967371 ps | ||
T376 | /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1292981997 | Jun 07 08:23:58 PM PDT 24 | Jun 07 08:24:00 PM PDT 24 | 46534871 ps | ||
T377 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2678325947 | Jun 07 08:23:56 PM PDT 24 | Jun 07 08:24:01 PM PDT 24 | 3301245188 ps | ||
T378 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1363738306 | Jun 07 08:23:47 PM PDT 24 | Jun 07 08:24:33 PM PDT 24 | 30239304524 ps | ||
T114 | /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1094314500 | Jun 07 08:24:10 PM PDT 24 | Jun 07 08:24:14 PM PDT 24 | 217713053 ps | ||
T379 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2537837120 | Jun 07 08:24:07 PM PDT 24 | Jun 07 08:24:13 PM PDT 24 | 1604954062 ps | ||
T380 | /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.1097671144 | Jun 07 08:24:10 PM PDT 24 | Jun 07 08:25:28 PM PDT 24 | 27238580232 ps | ||
T131 | /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2087894594 | Jun 07 08:24:19 PM PDT 24 | Jun 07 08:24:43 PM PDT 24 | 2172066898 ps | ||
T381 | /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2454097218 | Jun 07 08:23:58 PM PDT 24 | Jun 07 08:24:14 PM PDT 24 | 2918575832 ps | ||
T382 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.588096131 | Jun 07 08:23:51 PM PDT 24 | Jun 07 08:23:55 PM PDT 24 | 393079541 ps | ||
T383 | /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.973281764 | Jun 07 08:23:49 PM PDT 24 | Jun 07 08:23:53 PM PDT 24 | 160395962 ps | ||
T384 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.2522176437 | Jun 07 08:23:56 PM PDT 24 | Jun 07 08:23:59 PM PDT 24 | 318945516 ps | ||
T385 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.487732505 | Jun 07 08:24:07 PM PDT 24 | Jun 07 08:24:13 PM PDT 24 | 4288026092 ps | ||
T386 | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.938952707 | Jun 07 08:24:21 PM PDT 24 | Jun 07 08:24:30 PM PDT 24 | 4537810746 ps | ||
T134 | /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2011202171 | Jun 07 08:24:06 PM PDT 24 | Jun 07 08:24:27 PM PDT 24 | 3229013557 ps | ||
T387 | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2013247464 | Jun 07 08:24:10 PM PDT 24 | Jun 07 08:24:23 PM PDT 24 | 3288470528 ps | ||
T388 | /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.139108801 | Jun 07 08:23:50 PM PDT 24 | Jun 07 08:24:06 PM PDT 24 | 3559157457 ps | ||
T389 | /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.811668766 | Jun 07 08:24:17 PM PDT 24 | Jun 07 08:24:23 PM PDT 24 | 278463738 ps | ||
T390 | /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.70799442 | Jun 07 08:23:49 PM PDT 24 | Jun 07 08:24:18 PM PDT 24 | 69802076410 ps | ||
T130 | /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.575272458 | Jun 07 08:24:20 PM PDT 24 | Jun 07 08:24:41 PM PDT 24 | 3039352108 ps | ||
T391 | /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.1957082889 | Jun 07 08:23:56 PM PDT 24 | Jun 07 08:24:00 PM PDT 24 | 306741261 ps | ||
T392 | /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.2675360909 | Jun 07 08:24:19 PM PDT 24 | Jun 07 08:24:24 PM PDT 24 | 204030868 ps | ||
T393 | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.2700583084 | Jun 07 08:24:10 PM PDT 24 | Jun 07 08:24:38 PM PDT 24 | 26865674611 ps | ||
T394 | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.1215068263 | Jun 07 08:24:07 PM PDT 24 | Jun 07 08:25:08 PM PDT 24 | 45372973708 ps | ||
T395 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1742502667 | Jun 07 08:23:49 PM PDT 24 | Jun 07 08:23:56 PM PDT 24 | 2251970493 ps | ||
T396 | /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.2332492764 | Jun 07 08:23:56 PM PDT 24 | Jun 07 08:23:57 PM PDT 24 | 58859043 ps | ||
T397 | /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.2529460499 | Jun 07 08:24:20 PM PDT 24 | Jun 07 08:24:32 PM PDT 24 | 902109908 ps | ||
T398 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.1839634184 | Jun 07 08:24:08 PM PDT 24 | Jun 07 08:24:11 PM PDT 24 | 204512105 ps | ||
T399 | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2698895786 | Jun 07 08:24:20 PM PDT 24 | Jun 07 08:24:25 PM PDT 24 | 101235624 ps | ||
T115 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.1808072995 | Jun 07 08:23:56 PM PDT 24 | Jun 07 08:23:58 PM PDT 24 | 383763750 ps | ||
T400 | /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3288036513 | Jun 07 08:24:08 PM PDT 24 | Jun 07 08:24:17 PM PDT 24 | 2710704905 ps | ||
T401 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.993646080 | Jun 07 08:23:55 PM PDT 24 | Jun 07 08:23:58 PM PDT 24 | 959786211 ps | ||
T94 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.3512380555 | Jun 07 08:24:06 PM PDT 24 | Jun 07 08:24:15 PM PDT 24 | 13960798340 ps | ||
T402 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3124289116 | Jun 07 08:23:49 PM PDT 24 | Jun 07 08:24:57 PM PDT 24 | 2437282592 ps | ||
T403 | /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2934191292 | Jun 07 08:23:49 PM PDT 24 | Jun 07 08:23:59 PM PDT 24 | 947917289 ps | ||
T404 | /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.2608005645 | Jun 07 08:24:10 PM PDT 24 | Jun 07 08:24:13 PM PDT 24 | 85032685 ps | ||
T405 | /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3905579371 | Jun 07 08:24:16 PM PDT 24 | Jun 07 08:24:40 PM PDT 24 | 3559187716 ps | ||
T406 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.756118383 | Jun 07 08:24:12 PM PDT 24 | Jun 07 08:24:16 PM PDT 24 | 1601388424 ps | ||
T407 | /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3094273358 | Jun 07 08:24:16 PM PDT 24 | Jun 07 08:24:49 PM PDT 24 | 4063789088 ps | ||
T408 | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2465009780 | Jun 07 08:24:22 PM PDT 24 | Jun 07 08:24:54 PM PDT 24 | 10233013092 ps | ||
T409 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.3423535833 | Jun 07 08:24:07 PM PDT 24 | Jun 07 08:24:12 PM PDT 24 | 390472557 ps | ||
T410 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.4288047996 | Jun 07 08:23:50 PM PDT 24 | Jun 07 08:24:28 PM PDT 24 | 3772011501 ps | ||
T411 | /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.793927989 | Jun 07 08:24:17 PM PDT 24 | Jun 07 08:24:21 PM PDT 24 | 49399728 ps | ||
T412 | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.328102966 | Jun 07 08:24:18 PM PDT 24 | Jun 07 08:24:29 PM PDT 24 | 2744812606 ps | ||
T413 | /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3945809016 | Jun 07 08:24:21 PM PDT 24 | Jun 07 08:24:27 PM PDT 24 | 397871413 ps |
Test location | /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.3259511663 |
Short name | T16 |
Test name | |
Test status | |
Simulation time | 69565597451 ps |
CPU time | 206.76 seconds |
Started | Jun 07 08:24:25 PM PDT 24 |
Finished | Jun 07 08:27:54 PM PDT 24 |
Peak memory | 213468 kb |
Host | smart-1c5db8c0-e83c-4a4b-849c-a09ef2c4779e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3259511663 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.3259511663 |
Directory | /workspace/2.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/33.rv_dm_stress_all.3876328669 |
Short name | T20 |
Test name | |
Test status | |
Simulation time | 12518437662 ps |
CPU time | 26.8 seconds |
Started | Jun 07 08:24:58 PM PDT 24 |
Finished | Jun 07 08:25:28 PM PDT 24 |
Peak memory | 205124 kb |
Host | smart-f84961fa-c830-4187-bcb2-a6d337b486cb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876328669 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.3876328669 |
Directory | /workspace/33.rv_dm_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.298696048 |
Short name | T75 |
Test name | |
Test status | |
Simulation time | 1380913224 ps |
CPU time | 5.94 seconds |
Started | Jun 07 08:24:19 PM PDT 24 |
Finished | Jun 07 08:24:29 PM PDT 24 |
Peak memory | 212916 kb |
Host | smart-0b56ce63-ac65-4d8e-bac6-2897e79db640 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298696048 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.298696048 |
Directory | /workspace/11.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/default/10.rv_dm_alert_test.3695180034 |
Short name | T56 |
Test name | |
Test status | |
Simulation time | 30556986 ps |
CPU time | 0.76 seconds |
Started | Jun 07 08:24:43 PM PDT 24 |
Finished | Jun 07 08:24:47 PM PDT 24 |
Peak memory | 204804 kb |
Host | smart-9c2fc230-bc07-4008-888f-7aef7b6d8bec |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695180034 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.3695180034 |
Directory | /workspace/10.rv_dm_alert_test/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.4009384405 |
Short name | T50 |
Test name | |
Test status | |
Simulation time | 1275433843 ps |
CPU time | 10.62 seconds |
Started | Jun 07 08:24:09 PM PDT 24 |
Finished | Jun 07 08:24:22 PM PDT 24 |
Peak memory | 213332 kb |
Host | smart-49199cdc-9c07-4792-903a-45c8ad472d7b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009384405 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.4009384405 |
Directory | /workspace/4.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.805707704 |
Short name | T30 |
Test name | |
Test status | |
Simulation time | 73634880049 ps |
CPU time | 52.32 seconds |
Started | Jun 07 08:24:07 PM PDT 24 |
Finished | Jun 07 08:25:01 PM PDT 24 |
Peak memory | 222004 kb |
Host | smart-a8c4cddd-b1c8-46e6-bc32-ce3e95843afe |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805707704 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.805707704 |
Directory | /workspace/7.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/default/38.rv_dm_stress_all.2637184064 |
Short name | T11 |
Test name | |
Test status | |
Simulation time | 36481644945 ps |
CPU time | 100.14 seconds |
Started | Jun 07 08:25:03 PM PDT 24 |
Finished | Jun 07 08:26:48 PM PDT 24 |
Peak memory | 213256 kb |
Host | smart-892843d8-d1a6-455e-8893-a2c4369f1a88 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637184064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.2637184064 |
Directory | /workspace/38.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/32.rv_dm_stress_all.217555944 |
Short name | T2 |
Test name | |
Test status | |
Simulation time | 9036456166 ps |
CPU time | 8.19 seconds |
Started | Jun 07 08:25:03 PM PDT 24 |
Finished | Jun 07 08:25:16 PM PDT 24 |
Peak memory | 205104 kb |
Host | smart-4dfa830a-d841-4e95-9f1f-ab055d0e7ed2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217555944 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.217555944 |
Directory | /workspace/32.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.1879281749 |
Short name | T18 |
Test name | |
Test status | |
Simulation time | 6845579555 ps |
CPU time | 7.38 seconds |
Started | Jun 07 08:24:48 PM PDT 24 |
Finished | Jun 07 08:25:01 PM PDT 24 |
Peak memory | 205200 kb |
Host | smart-b61cd9e1-0b4e-414d-b535-d2878825960f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1879281749 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.1879281749 |
Directory | /workspace/14.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/34.rv_dm_stress_all.3776571744 |
Short name | T4 |
Test name | |
Test status | |
Simulation time | 8640098386 ps |
CPU time | 24.06 seconds |
Started | Jun 07 08:25:04 PM PDT 24 |
Finished | Jun 07 08:25:33 PM PDT 24 |
Peak memory | 205068 kb |
Host | smart-b2046945-66bd-4a6d-91b2-370bce05db93 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776571744 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.3776571744 |
Directory | /workspace/34.rv_dm_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3358068158 |
Short name | T54 |
Test name | |
Test status | |
Simulation time | 99928871 ps |
CPU time | 1.49 seconds |
Started | Jun 07 08:23:57 PM PDT 24 |
Finished | Jun 07 08:23:59 PM PDT 24 |
Peak memory | 213220 kb |
Host | smart-879d75fb-7720-48ce-871b-7e58f5bd2824 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358068158 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.3358068158 |
Directory | /workspace/2.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/default/0.rv_dm_sec_cm.3693933089 |
Short name | T25 |
Test name | |
Test status | |
Simulation time | 889511597 ps |
CPU time | 1.56 seconds |
Started | Jun 07 08:24:32 PM PDT 24 |
Finished | Jun 07 08:24:36 PM PDT 24 |
Peak memory | 228876 kb |
Host | smart-859e8343-f945-4849-b791-7a025dfd07ed |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693933089 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.3693933089 |
Directory | /workspace/0.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2224638714 |
Short name | T123 |
Test name | |
Test status | |
Simulation time | 2632059289 ps |
CPU time | 22.27 seconds |
Started | Jun 07 08:24:21 PM PDT 24 |
Finished | Jun 07 08:24:47 PM PDT 24 |
Peak memory | 213300 kb |
Host | smart-58cac701-ce99-4447-81c0-bcf58de0cb75 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224638714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.2 224638714 |
Directory | /workspace/17.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_exception.2002047784 |
Short name | T40 |
Test name | |
Test status | |
Simulation time | 617455077 ps |
CPU time | 2.5 seconds |
Started | Jun 07 08:24:24 PM PDT 24 |
Finished | Jun 07 08:24:29 PM PDT 24 |
Peak memory | 204716 kb |
Host | smart-5e9b8564-61bf-46d3-a7b0-e462cc2e99c9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2002047784 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.2002047784 |
Directory | /workspace/0.rv_dm_cmderr_exception/latest |
Test location | /workspace/coverage/default/0.rv_dm_abstractcmd_status.1377126217 |
Short name | T39 |
Test name | |
Test status | |
Simulation time | 311741684 ps |
CPU time | 1.02 seconds |
Started | Jun 07 08:24:24 PM PDT 24 |
Finished | Jun 07 08:24:28 PM PDT 24 |
Peak memory | 204748 kb |
Host | smart-d8b7f1ac-13c1-4fb4-ac4b-f9862463ec1f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1377126217 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.1377126217 |
Directory | /workspace/0.rv_dm_abstractcmd_status/latest |
Test location | /workspace/coverage/default/0.rv_dm_rom_read_access.2614139166 |
Short name | T36 |
Test name | |
Test status | |
Simulation time | 72367615 ps |
CPU time | 0.87 seconds |
Started | Jun 07 08:24:32 PM PDT 24 |
Finished | Jun 07 08:24:35 PM PDT 24 |
Peak memory | 212948 kb |
Host | smart-50496206-b193-46fd-beff-be3fb10276f6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2614139166 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.2614139166 |
Directory | /workspace/0.rv_dm_rom_read_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_sba_tl_access.1535794155 |
Short name | T226 |
Test name | |
Test status | |
Simulation time | 7302619248 ps |
CPU time | 12.89 seconds |
Started | Jun 07 08:24:31 PM PDT 24 |
Finished | Jun 07 08:24:46 PM PDT 24 |
Peak memory | 205276 kb |
Host | smart-58215c78-838b-484b-8432-3602bf11445d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1535794155 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.1535794155 |
Directory | /workspace/2.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_stress_all.3796327367 |
Short name | T10 |
Test name | |
Test status | |
Simulation time | 21257944399 ps |
CPU time | 54.72 seconds |
Started | Jun 07 08:24:45 PM PDT 24 |
Finished | Jun 07 08:25:44 PM PDT 24 |
Peak memory | 205128 kb |
Host | smart-c84165a1-aa2b-4680-a75e-7731d7e8a2db |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796327367 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.3796327367 |
Directory | /workspace/13.rv_dm_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.375824769 |
Short name | T53 |
Test name | |
Test status | |
Simulation time | 2415843638 ps |
CPU time | 7.22 seconds |
Started | Jun 07 08:24:21 PM PDT 24 |
Finished | Jun 07 08:24:32 PM PDT 24 |
Peak memory | 205148 kb |
Host | smart-219b43df-56f1-4059-80d3-2b7711c9420e |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375824769 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same_ csr_outstanding.375824769 |
Directory | /workspace/17.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/default/1.rv_dm_sba_tl_access.2929809958 |
Short name | T212 |
Test name | |
Test status | |
Simulation time | 2169894432 ps |
CPU time | 3.13 seconds |
Started | Jun 07 08:24:34 PM PDT 24 |
Finished | Jun 07 08:24:39 PM PDT 24 |
Peak memory | 205240 kb |
Host | smart-2e1e3bf9-13fe-404d-aa9a-a455c1dae552 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2929809958 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.2929809958 |
Directory | /workspace/1.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.1117478950 |
Short name | T42 |
Test name | |
Test status | |
Simulation time | 684214375 ps |
CPU time | 2.68 seconds |
Started | Jun 07 08:24:29 PM PDT 24 |
Finished | Jun 07 08:24:35 PM PDT 24 |
Peak memory | 204756 kb |
Host | smart-85f24984-e84f-4a0f-a7d2-ca27a8672d6c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1117478950 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.1117478950 |
Directory | /workspace/0.rv_dm_progbuf_read_write_execute/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2011202171 |
Short name | T134 |
Test name | |
Test status | |
Simulation time | 3229013557 ps |
CPU time | 19.31 seconds |
Started | Jun 07 08:24:06 PM PDT 24 |
Finished | Jun 07 08:24:27 PM PDT 24 |
Peak memory | 213404 kb |
Host | smart-e24c2197-5bb0-4bd0-aed3-1aba48672ff4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011202171 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.2011202171 |
Directory | /workspace/7.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2469956763 |
Short name | T81 |
Test name | |
Test status | |
Simulation time | 1694259140 ps |
CPU time | 9.84 seconds |
Started | Jun 07 08:24:09 PM PDT 24 |
Finished | Jun 07 08:24:21 PM PDT 24 |
Peak memory | 213324 kb |
Host | smart-56688d39-6684-4330-a5a7-ec8fc408c17e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469956763 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.2469956763 |
Directory | /workspace/6.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/19.rv_dm_alert_test.3238739513 |
Short name | T77 |
Test name | |
Test status | |
Simulation time | 30043962 ps |
CPU time | 0.72 seconds |
Started | Jun 07 08:24:49 PM PDT 24 |
Finished | Jun 07 08:24:56 PM PDT 24 |
Peak memory | 204804 kb |
Host | smart-00ea5edc-f5c3-4484-b646-039212197809 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238739513 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.3238739513 |
Directory | /workspace/19.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/15.rv_dm_sba_tl_access.2689554398 |
Short name | T48 |
Test name | |
Test status | |
Simulation time | 6140338467 ps |
CPU time | 17.92 seconds |
Started | Jun 07 08:24:48 PM PDT 24 |
Finished | Jun 07 08:25:12 PM PDT 24 |
Peak memory | 205240 kb |
Host | smart-da3c96a1-9825-4245-aeaa-6e1a530e3734 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2689554398 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.2689554398 |
Directory | /workspace/15.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.1732854552 |
Short name | T290 |
Test name | |
Test status | |
Simulation time | 387468961 ps |
CPU time | 1.34 seconds |
Started | Jun 07 08:23:48 PM PDT 24 |
Finished | Jun 07 08:23:51 PM PDT 24 |
Peak memory | 204616 kb |
Host | smart-bb17bcca-b21f-46cb-b603-e1f8f4345669 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732854552 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_aliasing.1732854552 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2982452700 |
Short name | T93 |
Test name | |
Test status | |
Simulation time | 10508800839 ps |
CPU time | 18.04 seconds |
Started | Jun 07 08:23:49 PM PDT 24 |
Finished | Jun 07 08:24:09 PM PDT 24 |
Peak memory | 205148 kb |
Host | smart-19321b14-9eba-468e-b20c-d0ad59bad5eb |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982452700 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs r_hw_reset.2982452700 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.3601927257 |
Short name | T35 |
Test name | |
Test status | |
Simulation time | 594973711 ps |
CPU time | 0.83 seconds |
Started | Jun 07 08:24:25 PM PDT 24 |
Finished | Jun 07 08:24:28 PM PDT 24 |
Peak memory | 204588 kb |
Host | smart-9500f3d4-4d5d-44ec-aa55-294cda8feda2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3601927257 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.3601927257 |
Directory | /workspace/0.rv_dm_cmderr_halt_resume/latest |
Test location | /workspace/coverage/default/0.rv_dm_progbuf_busy.1228620489 |
Short name | T14 |
Test name | |
Test status | |
Simulation time | 504830495 ps |
CPU time | 1.02 seconds |
Started | Jun 07 08:24:34 PM PDT 24 |
Finished | Jun 07 08:24:38 PM PDT 24 |
Peak memory | 204712 kb |
Host | smart-fff3baf6-7292-4a2f-bec6-691ba7a26494 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1228620489 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.1228620489 |
Directory | /workspace/0.rv_dm_progbuf_busy/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.139108801 |
Short name | T388 |
Test name | |
Test status | |
Simulation time | 3559157457 ps |
CPU time | 14.06 seconds |
Started | Jun 07 08:23:50 PM PDT 24 |
Finished | Jun 07 08:24:06 PM PDT 24 |
Peak memory | 213388 kb |
Host | smart-a40be65f-a91a-4e28-a41b-1e187d58a94e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139108801 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.139108801 |
Directory | /workspace/1.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3955533868 |
Short name | T127 |
Test name | |
Test status | |
Simulation time | 3456872416 ps |
CPU time | 5.33 seconds |
Started | Jun 07 08:23:50 PM PDT 24 |
Finished | Jun 07 08:23:58 PM PDT 24 |
Peak memory | 221548 kb |
Host | smart-2c92a5d5-0b6c-4292-96e4-6bc445a143e1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955533868 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.3955533868 |
Directory | /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.763832992 |
Short name | T129 |
Test name | |
Test status | |
Simulation time | 571181265 ps |
CPU time | 8.58 seconds |
Started | Jun 07 08:24:00 PM PDT 24 |
Finished | Jun 07 08:24:10 PM PDT 24 |
Peak memory | 213372 kb |
Host | smart-3798cc00-8edd-4489-a165-43561de90d48 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763832992 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.763832992 |
Directory | /workspace/0.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.2384985861 |
Short name | T249 |
Test name | |
Test status | |
Simulation time | 16215878701 ps |
CPU time | 24.19 seconds |
Started | Jun 07 08:24:48 PM PDT 24 |
Finished | Jun 07 08:25:18 PM PDT 24 |
Peak memory | 205484 kb |
Host | smart-d922488f-debe-46a8-b7dd-8ddfc7d8c7e3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2384985861 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.2384985861 |
Directory | /workspace/13.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3829790317 |
Short name | T99 |
Test name | |
Test status | |
Simulation time | 3522118319 ps |
CPU time | 75.62 seconds |
Started | Jun 07 08:23:51 PM PDT 24 |
Finished | Jun 07 08:25:09 PM PDT 24 |
Peak memory | 213400 kb |
Host | smart-8620737a-dd77-4504-bfce-a9a634c3eae0 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829790317 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 0.rv_dm_csr_aliasing.3829790317 |
Directory | /workspace/0.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.768717823 |
Short name | T276 |
Test name | |
Test status | |
Simulation time | 2456742357 ps |
CPU time | 27.92 seconds |
Started | Jun 07 08:23:48 PM PDT 24 |
Finished | Jun 07 08:24:17 PM PDT 24 |
Peak memory | 213356 kb |
Host | smart-8b24f4ae-2485-47e7-8d46-243bfbc188e6 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768717823 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.768717823 |
Directory | /workspace/0.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.1401316391 |
Short name | T109 |
Test name | |
Test status | |
Simulation time | 279793646 ps |
CPU time | 1.69 seconds |
Started | Jun 07 08:23:59 PM PDT 24 |
Finished | Jun 07 08:24:02 PM PDT 24 |
Peak memory | 213372 kb |
Host | smart-1597fe48-11df-40c6-bca2-d28ee9b4f305 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401316391 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.1401316391 |
Directory | /workspace/0.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2667273614 |
Short name | T84 |
Test name | |
Test status | |
Simulation time | 180823347 ps |
CPU time | 1.9 seconds |
Started | Jun 07 08:23:47 PM PDT 24 |
Finished | Jun 07 08:23:50 PM PDT 24 |
Peak memory | 213272 kb |
Host | smart-deaf84ca-9fc7-421f-bf0c-90ead6bc5fae |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667273614 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.2667273614 |
Directory | /workspace/0.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1758498034 |
Short name | T362 |
Test name | |
Test status | |
Simulation time | 29369498509 ps |
CPU time | 13.39 seconds |
Started | Jun 07 08:23:52 PM PDT 24 |
Finished | Jun 07 08:24:07 PM PDT 24 |
Peak memory | 205060 kb |
Host | smart-e396b546-dacf-4cbd-bdf7-893c64f1d8d1 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758498034 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs r_aliasing.1758498034 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.3111646869 |
Short name | T314 |
Test name | |
Test status | |
Simulation time | 13956355002 ps |
CPU time | 22.21 seconds |
Started | Jun 07 08:23:47 PM PDT 24 |
Finished | Jun 07 08:24:10 PM PDT 24 |
Peak memory | 205092 kb |
Host | smart-524bd23a-740c-4464-9232-feef25fde849 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111646869 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0. rv_dm_jtag_dmi_csr_bit_bash.3111646869 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.3612522507 |
Short name | T368 |
Test name | |
Test status | |
Simulation time | 5522622020 ps |
CPU time | 9.35 seconds |
Started | Jun 07 08:23:49 PM PDT 24 |
Finished | Jun 07 08:24:00 PM PDT 24 |
Peak memory | 205064 kb |
Host | smart-c85533dc-320d-46f4-bd12-99bb27eb5c50 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612522507 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs r_hw_reset.3612522507 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3049201205 |
Short name | T349 |
Test name | |
Test status | |
Simulation time | 2470719675 ps |
CPU time | 1.87 seconds |
Started | Jun 07 08:23:46 PM PDT 24 |
Finished | Jun 07 08:23:49 PM PDT 24 |
Peak memory | 205080 kb |
Host | smart-45d60203-cb81-4b2a-a0c8-69bb179d633c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049201205 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.3 049201205 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1223336402 |
Short name | T281 |
Test name | |
Test status | |
Simulation time | 3933881504 ps |
CPU time | 7.74 seconds |
Started | Jun 07 08:23:50 PM PDT 24 |
Finished | Jun 07 08:23:59 PM PDT 24 |
Peak memory | 204980 kb |
Host | smart-3909ca0e-2457-489d-bc12-7b3b1e98995e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223336402 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_bit_bash.1223336402 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2899142382 |
Short name | T288 |
Test name | |
Test status | |
Simulation time | 167149561 ps |
CPU time | 0.96 seconds |
Started | Jun 07 08:23:50 PM PDT 24 |
Finished | Jun 07 08:23:53 PM PDT 24 |
Peak memory | 204712 kb |
Host | smart-94ef27c3-94a0-4733-a14b-5c587d67501d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899142382 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_hw_reset.2899142382 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3832855657 |
Short name | T355 |
Test name | |
Test status | |
Simulation time | 225437148 ps |
CPU time | 1.28 seconds |
Started | Jun 07 08:23:48 PM PDT 24 |
Finished | Jun 07 08:23:50 PM PDT 24 |
Peak memory | 204744 kb |
Host | smart-cd990cf5-8e67-4ecf-ae6e-775a2c754d39 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832855657 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.3 832855657 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1292981997 |
Short name | T376 |
Test name | |
Test status | |
Simulation time | 46534871 ps |
CPU time | 0.79 seconds |
Started | Jun 07 08:23:58 PM PDT 24 |
Finished | Jun 07 08:24:00 PM PDT 24 |
Peak memory | 204676 kb |
Host | smart-181073ac-99f4-4157-9696-9ffbf530924d |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292981997 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par tial_access.1292981997 |
Directory | /workspace/0.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.3288972488 |
Short name | T307 |
Test name | |
Test status | |
Simulation time | 72535940 ps |
CPU time | 0.67 seconds |
Started | Jun 07 08:23:46 PM PDT 24 |
Finished | Jun 07 08:23:47 PM PDT 24 |
Peak memory | 204728 kb |
Host | smart-18e1f796-17ec-4237-a750-6ced2f5a36d5 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288972488 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.3288972488 |
Directory | /workspace/0.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2213540071 |
Short name | T87 |
Test name | |
Test status | |
Simulation time | 164619559 ps |
CPU time | 6.6 seconds |
Started | Jun 07 08:23:50 PM PDT 24 |
Finished | Jun 07 08:23:58 PM PDT 24 |
Peak memory | 205044 kb |
Host | smart-17f7d53f-28fe-47c2-b89a-ab622798939a |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213540071 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_ csr_outstanding.2213540071 |
Directory | /workspace/0.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.2525014079 |
Short name | T126 |
Test name | |
Test status | |
Simulation time | 86450638 ps |
CPU time | 2.85 seconds |
Started | Jun 07 08:23:47 PM PDT 24 |
Finished | Jun 07 08:23:51 PM PDT 24 |
Peak memory | 213324 kb |
Host | smart-8e65cccd-74c9-4dcd-879a-f35594c9ce19 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525014079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.2525014079 |
Directory | /workspace/0.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3124289116 |
Short name | T402 |
Test name | |
Test status | |
Simulation time | 2437282592 ps |
CPU time | 66.66 seconds |
Started | Jun 07 08:23:49 PM PDT 24 |
Finished | Jun 07 08:24:57 PM PDT 24 |
Peak memory | 212860 kb |
Host | smart-808eb9b1-9fe7-4163-9435-d440be9e6b2c |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124289116 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 1.rv_dm_csr_aliasing.3124289116 |
Directory | /workspace/1.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.4288047996 |
Short name | T410 |
Test name | |
Test status | |
Simulation time | 3772011501 ps |
CPU time | 36.19 seconds |
Started | Jun 07 08:23:50 PM PDT 24 |
Finished | Jun 07 08:24:28 PM PDT 24 |
Peak memory | 213384 kb |
Host | smart-5564d995-354f-4056-964e-138a7e7f303b |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288047996 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.4288047996 |
Directory | /workspace/1.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.588096131 |
Short name | T382 |
Test name | |
Test status | |
Simulation time | 393079541 ps |
CPU time | 1.66 seconds |
Started | Jun 07 08:23:51 PM PDT 24 |
Finished | Jun 07 08:23:55 PM PDT 24 |
Peak memory | 213316 kb |
Host | smart-2ec8d8be-0c23-4b9a-a46c-93024fc97971 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588096131 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.588096131 |
Directory | /workspace/1.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.498464221 |
Short name | T317 |
Test name | |
Test status | |
Simulation time | 2058859337 ps |
CPU time | 6.14 seconds |
Started | Jun 07 08:23:51 PM PDT 24 |
Finished | Jun 07 08:23:59 PM PDT 24 |
Peak memory | 221592 kb |
Host | smart-ca73ebb4-7a5e-4e3b-a8bd-3e51cdae5356 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498464221 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.498464221 |
Directory | /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.3574966905 |
Short name | T97 |
Test name | |
Test status | |
Simulation time | 65826017 ps |
CPU time | 1.61 seconds |
Started | Jun 07 08:23:49 PM PDT 24 |
Finished | Jun 07 08:23:52 PM PDT 24 |
Peak memory | 212820 kb |
Host | smart-9cfc1301-6725-4b2f-bd4e-cd01d6112161 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574966905 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.3574966905 |
Directory | /workspace/1.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1011305893 |
Short name | T305 |
Test name | |
Test status | |
Simulation time | 126834680318 ps |
CPU time | 62.12 seconds |
Started | Jun 07 08:23:50 PM PDT 24 |
Finished | Jun 07 08:24:55 PM PDT 24 |
Peak memory | 205012 kb |
Host | smart-b8678902-1fb2-4f82-9791-895e2d80cfb4 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011305893 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs r_aliasing.1011305893 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1363738306 |
Short name | T378 |
Test name | |
Test status | |
Simulation time | 30239304524 ps |
CPU time | 44.21 seconds |
Started | Jun 07 08:23:47 PM PDT 24 |
Finished | Jun 07 08:24:33 PM PDT 24 |
Peak memory | 205004 kb |
Host | smart-4b452bec-67eb-48cf-a2c9-43ab544c7e69 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363738306 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1. rv_dm_jtag_dmi_csr_bit_bash.1363738306 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1742502667 |
Short name | T395 |
Test name | |
Test status | |
Simulation time | 2251970493 ps |
CPU time | 5.71 seconds |
Started | Jun 07 08:23:49 PM PDT 24 |
Finished | Jun 07 08:23:56 PM PDT 24 |
Peak memory | 205044 kb |
Host | smart-f9f8707e-6edd-40cc-8fd6-0022b5357544 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742502667 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.1 742502667 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3998116800 |
Short name | T353 |
Test name | |
Test status | |
Simulation time | 597490894 ps |
CPU time | 1.29 seconds |
Started | Jun 07 08:23:48 PM PDT 24 |
Finished | Jun 07 08:23:51 PM PDT 24 |
Peak memory | 204724 kb |
Host | smart-871e7fd2-45ca-4afb-943e-4d7e0aba4f08 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998116800 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_aliasing.3998116800 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.945447064 |
Short name | T334 |
Test name | |
Test status | |
Simulation time | 5283728211 ps |
CPU time | 8.5 seconds |
Started | Jun 07 08:23:48 PM PDT 24 |
Finished | Jun 07 08:23:58 PM PDT 24 |
Peak memory | 205036 kb |
Host | smart-cc99a61d-18af-4910-acf7-723939968a61 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945447064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr _bit_bash.945447064 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1503173491 |
Short name | T374 |
Test name | |
Test status | |
Simulation time | 607190766 ps |
CPU time | 1.53 seconds |
Started | Jun 07 08:23:48 PM PDT 24 |
Finished | Jun 07 08:23:51 PM PDT 24 |
Peak memory | 204788 kb |
Host | smart-beb63734-27c1-42a1-8f2e-abe44ee237e3 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503173491 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_hw_reset.1503173491 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.2324220812 |
Short name | T339 |
Test name | |
Test status | |
Simulation time | 543313182 ps |
CPU time | 2.04 seconds |
Started | Jun 07 08:23:51 PM PDT 24 |
Finished | Jun 07 08:23:55 PM PDT 24 |
Peak memory | 204832 kb |
Host | smart-4dce1895-962a-4024-b024-d51d5bed2696 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324220812 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.2 324220812 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2451174081 |
Short name | T323 |
Test name | |
Test status | |
Simulation time | 130994108 ps |
CPU time | 0.74 seconds |
Started | Jun 07 08:23:50 PM PDT 24 |
Finished | Jun 07 08:23:52 PM PDT 24 |
Peak memory | 204508 kb |
Host | smart-c1643f24-733b-469d-8c6a-093b4dd8264d |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451174081 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par tial_access.2451174081 |
Directory | /workspace/1.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.3455569231 |
Short name | T344 |
Test name | |
Test status | |
Simulation time | 145980855 ps |
CPU time | 0.89 seconds |
Started | Jun 07 08:23:49 PM PDT 24 |
Finished | Jun 07 08:23:52 PM PDT 24 |
Peak memory | 204724 kb |
Host | smart-7c539194-606a-408b-9129-f6d48d63ea3c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455569231 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.3455569231 |
Directory | /workspace/1.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2934191292 |
Short name | T403 |
Test name | |
Test status | |
Simulation time | 947917289 ps |
CPU time | 8.01 seconds |
Started | Jun 07 08:23:49 PM PDT 24 |
Finished | Jun 07 08:23:59 PM PDT 24 |
Peak memory | 205172 kb |
Host | smart-cbc5d995-22de-41d9-90f2-9be59b5485cd |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934191292 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_ csr_outstanding.2934191292 |
Directory | /workspace/1.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.1521331936 |
Short name | T141 |
Test name | |
Test status | |
Simulation time | 75661029372 ps |
CPU time | 102.84 seconds |
Started | Jun 07 08:23:59 PM PDT 24 |
Finished | Jun 07 08:25:43 PM PDT 24 |
Peak memory | 224656 kb |
Host | smart-c474a739-b1ab-4531-b939-9dbbd91ee42e |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521331936 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.1521331936 |
Directory | /workspace/1.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.973281764 |
Short name | T383 |
Test name | |
Test status | |
Simulation time | 160395962 ps |
CPU time | 2.41 seconds |
Started | Jun 07 08:23:49 PM PDT 24 |
Finished | Jun 07 08:23:53 PM PDT 24 |
Peak memory | 213304 kb |
Host | smart-a6a4816c-16a5-403a-be32-3ede8713e137 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973281764 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.973281764 |
Directory | /workspace/1.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.694286217 |
Short name | T351 |
Test name | |
Test status | |
Simulation time | 412929295 ps |
CPU time | 2.93 seconds |
Started | Jun 07 08:24:16 PM PDT 24 |
Finished | Jun 07 08:24:20 PM PDT 24 |
Peak memory | 217680 kb |
Host | smart-7d4952ad-312a-452c-8575-c8d195243706 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694286217 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.694286217 |
Directory | /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.1678287099 |
Short name | T360 |
Test name | |
Test status | |
Simulation time | 174560984 ps |
CPU time | 1.63 seconds |
Started | Jun 07 08:24:20 PM PDT 24 |
Finished | Jun 07 08:24:26 PM PDT 24 |
Peak memory | 213296 kb |
Host | smart-c588a938-8804-4b0c-a490-2e32ed784b37 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678287099 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.1678287099 |
Directory | /workspace/10.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.2008284790 |
Short name | T274 |
Test name | |
Test status | |
Simulation time | 27202966255 ps |
CPU time | 22.02 seconds |
Started | Jun 07 08:24:18 PM PDT 24 |
Finished | Jun 07 08:24:42 PM PDT 24 |
Peak memory | 205048 kb |
Host | smart-1d255150-b559-42ae-83d0-432f31856b0e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008284790 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10 .rv_dm_jtag_dmi_csr_bit_bash.2008284790 |
Directory | /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.648089281 |
Short name | T333 |
Test name | |
Test status | |
Simulation time | 1764775052 ps |
CPU time | 3.92 seconds |
Started | Jun 07 08:24:19 PM PDT 24 |
Finished | Jun 07 08:24:28 PM PDT 24 |
Peak memory | 204932 kb |
Host | smart-709c23a6-e02d-463a-979c-251cb972dafa |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648089281 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.648089281 |
Directory | /workspace/10.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.6120616 |
Short name | T302 |
Test name | |
Test status | |
Simulation time | 185264339 ps |
CPU time | 1.18 seconds |
Started | Jun 07 08:24:16 PM PDT 24 |
Finished | Jun 07 08:24:19 PM PDT 24 |
Peak memory | 204744 kb |
Host | smart-26bcd667-faec-43aa-93b8-4162cbe7cf04 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6120616 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.6120616 |
Directory | /workspace/10.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.57845883 |
Short name | T373 |
Test name | |
Test status | |
Simulation time | 91467020 ps |
CPU time | 3.5 seconds |
Started | Jun 07 08:24:18 PM PDT 24 |
Finished | Jun 07 08:24:24 PM PDT 24 |
Peak memory | 205096 kb |
Host | smart-de1dbac3-cd8c-445d-95c0-f094089a4061 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57845883 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same_c sr_outstanding.57845883 |
Directory | /workspace/10.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.2275211875 |
Short name | T369 |
Test name | |
Test status | |
Simulation time | 839417380 ps |
CPU time | 3.57 seconds |
Started | Jun 07 08:24:15 PM PDT 24 |
Finished | Jun 07 08:24:20 PM PDT 24 |
Peak memory | 213296 kb |
Host | smart-df72f130-6fa1-4b0b-86e0-dc805a52bbd9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275211875 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.2275211875 |
Directory | /workspace/10.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.575272458 |
Short name | T130 |
Test name | |
Test status | |
Simulation time | 3039352108 ps |
CPU time | 16.42 seconds |
Started | Jun 07 08:24:20 PM PDT 24 |
Finished | Jun 07 08:24:41 PM PDT 24 |
Peak memory | 213348 kb |
Host | smart-7b3c0150-d175-4bd2-bec4-bac0c448408a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575272458 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.575272458 |
Directory | /workspace/10.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1354410744 |
Short name | T320 |
Test name | |
Test status | |
Simulation time | 4105665910 ps |
CPU time | 9.57 seconds |
Started | Jun 07 08:24:21 PM PDT 24 |
Finished | Jun 07 08:24:34 PM PDT 24 |
Peak memory | 221092 kb |
Host | smart-6b802e31-e5ac-476f-9563-d0dc69d2aaa2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354410744 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.1354410744 |
Directory | /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.3437995115 |
Short name | T90 |
Test name | |
Test status | |
Simulation time | 422871655 ps |
CPU time | 1.7 seconds |
Started | Jun 07 08:24:19 PM PDT 24 |
Finished | Jun 07 08:24:25 PM PDT 24 |
Peak memory | 213296 kb |
Host | smart-c647c54c-d655-4f2b-9e0e-829d9cd22548 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437995115 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.3437995115 |
Directory | /workspace/11.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.328102966 |
Short name | T412 |
Test name | |
Test status | |
Simulation time | 2744812606 ps |
CPU time | 8.7 seconds |
Started | Jun 07 08:24:18 PM PDT 24 |
Finished | Jun 07 08:24:29 PM PDT 24 |
Peak memory | 204964 kb |
Host | smart-92082064-7729-4379-b43c-73a129431dc5 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328102966 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11. rv_dm_jtag_dmi_csr_bit_bash.328102966 |
Directory | /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3408495102 |
Short name | T352 |
Test name | |
Test status | |
Simulation time | 10369543696 ps |
CPU time | 29.75 seconds |
Started | Jun 07 08:24:18 PM PDT 24 |
Finished | Jun 07 08:24:50 PM PDT 24 |
Peak memory | 205056 kb |
Host | smart-8be56528-db45-4421-9dbd-c66d3a31ae94 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408495102 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw. 3408495102 |
Directory | /workspace/11.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.131289115 |
Short name | T336 |
Test name | |
Test status | |
Simulation time | 342999126 ps |
CPU time | 1.58 seconds |
Started | Jun 07 08:24:18 PM PDT 24 |
Finished | Jun 07 08:24:21 PM PDT 24 |
Peak memory | 204724 kb |
Host | smart-4c75bb9c-1a8c-4858-9b60-82187e027aa5 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131289115 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.131289115 |
Directory | /workspace/11.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.1937335026 |
Short name | T89 |
Test name | |
Test status | |
Simulation time | 270117549 ps |
CPU time | 4.12 seconds |
Started | Jun 07 08:24:16 PM PDT 24 |
Finished | Jun 07 08:24:21 PM PDT 24 |
Peak memory | 205108 kb |
Host | smart-e572272e-bc59-4b28-b5df-22809227f4f8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937335026 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same _csr_outstanding.1937335026 |
Directory | /workspace/11.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3094273358 |
Short name | T407 |
Test name | |
Test status | |
Simulation time | 4063789088 ps |
CPU time | 31.85 seconds |
Started | Jun 07 08:24:16 PM PDT 24 |
Finished | Jun 07 08:24:49 PM PDT 24 |
Peak memory | 213468 kb |
Host | smart-caa833e6-b861-4b94-9c39-5d9c393882b1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094273358 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.3 094273358 |
Directory | /workspace/11.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.4073494971 |
Short name | T338 |
Test name | |
Test status | |
Simulation time | 595101563 ps |
CPU time | 4.66 seconds |
Started | Jun 07 08:24:17 PM PDT 24 |
Finished | Jun 07 08:24:24 PM PDT 24 |
Peak memory | 219636 kb |
Host | smart-4ccde985-2383-4b0c-b2ad-2ff6ba3422f5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073494971 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.4073494971 |
Directory | /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.318222380 |
Short name | T110 |
Test name | |
Test status | |
Simulation time | 213257887 ps |
CPU time | 2.37 seconds |
Started | Jun 07 08:24:19 PM PDT 24 |
Finished | Jun 07 08:24:24 PM PDT 24 |
Peak memory | 213224 kb |
Host | smart-dade0cd3-0c67-4f14-b3f2-c6ba08a28efe |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318222380 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.318222380 |
Directory | /workspace/12.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.1865667583 |
Short name | T294 |
Test name | |
Test status | |
Simulation time | 10022985248 ps |
CPU time | 18.06 seconds |
Started | Jun 07 08:24:16 PM PDT 24 |
Finished | Jun 07 08:24:36 PM PDT 24 |
Peak memory | 205032 kb |
Host | smart-e2bf34af-79ce-4c28-9d5e-425e6909a6be |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865667583 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12 .rv_dm_jtag_dmi_csr_bit_bash.1865667583 |
Directory | /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.938952707 |
Short name | T386 |
Test name | |
Test status | |
Simulation time | 4537810746 ps |
CPU time | 4.62 seconds |
Started | Jun 07 08:24:21 PM PDT 24 |
Finished | Jun 07 08:24:30 PM PDT 24 |
Peak memory | 205044 kb |
Host | smart-d1f76108-862b-4e9f-9b1b-1fa1b4a8b3bb |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938952707 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.938952707 |
Directory | /workspace/12.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3992154863 |
Short name | T370 |
Test name | |
Test status | |
Simulation time | 342120708 ps |
CPU time | 1.3 seconds |
Started | Jun 07 08:24:19 PM PDT 24 |
Finished | Jun 07 08:24:25 PM PDT 24 |
Peak memory | 204720 kb |
Host | smart-431d3e75-3e1b-47d5-9bb5-0f2403f13cbf |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992154863 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw. 3992154863 |
Directory | /workspace/12.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.2529460499 |
Short name | T397 |
Test name | |
Test status | |
Simulation time | 902109908 ps |
CPU time | 7.81 seconds |
Started | Jun 07 08:24:20 PM PDT 24 |
Finished | Jun 07 08:24:32 PM PDT 24 |
Peak memory | 205084 kb |
Host | smart-5f900602-8fae-4283-bd6a-bda1dde7f112 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529460499 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same _csr_outstanding.2529460499 |
Directory | /workspace/12.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.793927989 |
Short name | T411 |
Test name | |
Test status | |
Simulation time | 49399728 ps |
CPU time | 2.04 seconds |
Started | Jun 07 08:24:17 PM PDT 24 |
Finished | Jun 07 08:24:21 PM PDT 24 |
Peak memory | 213400 kb |
Host | smart-08907f4b-1ad0-4716-af28-04222ae8892b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793927989 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.793927989 |
Directory | /workspace/12.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.894814008 |
Short name | T138 |
Test name | |
Test status | |
Simulation time | 4346145533 ps |
CPU time | 26.84 seconds |
Started | Jun 07 08:24:18 PM PDT 24 |
Finished | Jun 07 08:24:48 PM PDT 24 |
Peak memory | 213320 kb |
Host | smart-262e5351-f014-4447-b061-2ed437b10dc9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894814008 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.894814008 |
Directory | /workspace/12.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.818729266 |
Short name | T359 |
Test name | |
Test status | |
Simulation time | 333942512 ps |
CPU time | 2.83 seconds |
Started | Jun 07 08:24:17 PM PDT 24 |
Finished | Jun 07 08:24:21 PM PDT 24 |
Peak memory | 215068 kb |
Host | smart-d9faefcb-2e36-450a-a97d-e1c329799991 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818729266 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.818729266 |
Directory | /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.2675360909 |
Short name | T392 |
Test name | |
Test status | |
Simulation time | 204030868 ps |
CPU time | 2.12 seconds |
Started | Jun 07 08:24:19 PM PDT 24 |
Finished | Jun 07 08:24:24 PM PDT 24 |
Peak memory | 213292 kb |
Host | smart-3ba442f6-6d84-417c-9d86-87ccf65e2036 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675360909 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.2675360909 |
Directory | /workspace/13.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.2451451544 |
Short name | T348 |
Test name | |
Test status | |
Simulation time | 15612796083 ps |
CPU time | 20.41 seconds |
Started | Jun 07 08:24:19 PM PDT 24 |
Finished | Jun 07 08:24:43 PM PDT 24 |
Peak memory | 204920 kb |
Host | smart-c6dc5336-7a03-4265-a13d-5387f5089de1 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451451544 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13 .rv_dm_jtag_dmi_csr_bit_bash.2451451544 |
Directory | /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.3189053630 |
Short name | T310 |
Test name | |
Test status | |
Simulation time | 9133229465 ps |
CPU time | 3.56 seconds |
Started | Jun 07 08:24:18 PM PDT 24 |
Finished | Jun 07 08:24:24 PM PDT 24 |
Peak memory | 205020 kb |
Host | smart-9ae289b9-5d17-4ee3-8a4f-e8e4c8a210ef |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189053630 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw. 3189053630 |
Directory | /workspace/13.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2271672567 |
Short name | T358 |
Test name | |
Test status | |
Simulation time | 703728755 ps |
CPU time | 0.97 seconds |
Started | Jun 07 08:24:18 PM PDT 24 |
Finished | Jun 07 08:24:22 PM PDT 24 |
Peak memory | 204748 kb |
Host | smart-426728fc-6b5c-49fa-afed-c71cef1c55ba |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271672567 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw. 2271672567 |
Directory | /workspace/13.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.1504203288 |
Short name | T105 |
Test name | |
Test status | |
Simulation time | 325851186 ps |
CPU time | 3.71 seconds |
Started | Jun 07 08:24:17 PM PDT 24 |
Finished | Jun 07 08:24:22 PM PDT 24 |
Peak memory | 205184 kb |
Host | smart-1095b4e4-0855-4fb9-868f-c05802dcc37a |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504203288 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same _csr_outstanding.1504203288 |
Directory | /workspace/13.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.811668766 |
Short name | T389 |
Test name | |
Test status | |
Simulation time | 278463738 ps |
CPU time | 4.01 seconds |
Started | Jun 07 08:24:17 PM PDT 24 |
Finished | Jun 07 08:24:23 PM PDT 24 |
Peak memory | 213256 kb |
Host | smart-45de8768-884d-4a3f-94ec-fb37d44740c3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811668766 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.811668766 |
Directory | /workspace/13.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3905579371 |
Short name | T405 |
Test name | |
Test status | |
Simulation time | 3559187716 ps |
CPU time | 23.39 seconds |
Started | Jun 07 08:24:16 PM PDT 24 |
Finished | Jun 07 08:24:40 PM PDT 24 |
Peak memory | 213392 kb |
Host | smart-b2ef01ae-ac20-4b18-9404-05e19c3160b5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905579371 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.3 905579371 |
Directory | /workspace/13.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.2165058584 |
Short name | T341 |
Test name | |
Test status | |
Simulation time | 102695191 ps |
CPU time | 2.38 seconds |
Started | Jun 07 08:24:18 PM PDT 24 |
Finished | Jun 07 08:24:24 PM PDT 24 |
Peak memory | 213344 kb |
Host | smart-c9002d8b-702c-4473-9de9-82af20f9f33d |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165058584 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.2165058584 |
Directory | /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.4075972713 |
Short name | T96 |
Test name | |
Test status | |
Simulation time | 58187922 ps |
CPU time | 2.11 seconds |
Started | Jun 07 08:24:19 PM PDT 24 |
Finished | Jun 07 08:24:25 PM PDT 24 |
Peak memory | 213252 kb |
Host | smart-35a2d033-67a7-487c-a25f-25c1b5a36960 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075972713 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.4075972713 |
Directory | /workspace/14.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.145042091 |
Short name | T321 |
Test name | |
Test status | |
Simulation time | 101017115 ps |
CPU time | 0.76 seconds |
Started | Jun 07 08:24:17 PM PDT 24 |
Finished | Jun 07 08:24:19 PM PDT 24 |
Peak memory | 204740 kb |
Host | smart-8f0db546-f0e6-4f21-8631-c1272ad1ef3d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145042091 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14. rv_dm_jtag_dmi_csr_bit_bash.145042091 |
Directory | /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1691139783 |
Short name | T329 |
Test name | |
Test status | |
Simulation time | 3017341368 ps |
CPU time | 6.07 seconds |
Started | Jun 07 08:24:17 PM PDT 24 |
Finished | Jun 07 08:24:25 PM PDT 24 |
Peak memory | 204972 kb |
Host | smart-810abb1d-e025-49ed-93ef-4d9e18920ed9 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691139783 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw. 1691139783 |
Directory | /workspace/14.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.792837579 |
Short name | T326 |
Test name | |
Test status | |
Simulation time | 355547233 ps |
CPU time | 0.86 seconds |
Started | Jun 07 08:24:19 PM PDT 24 |
Finished | Jun 07 08:24:25 PM PDT 24 |
Peak memory | 204764 kb |
Host | smart-c84412cf-cdbf-4602-9738-43c08146a069 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792837579 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.792837579 |
Directory | /workspace/14.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.809542712 |
Short name | T357 |
Test name | |
Test status | |
Simulation time | 563788195 ps |
CPU time | 8.04 seconds |
Started | Jun 07 08:24:19 PM PDT 24 |
Finished | Jun 07 08:24:31 PM PDT 24 |
Peak memory | 205104 kb |
Host | smart-07896fae-b1e0-484b-a947-d182f24f177e |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809542712 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same_ csr_outstanding.809542712 |
Directory | /workspace/14.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.817069684 |
Short name | T312 |
Test name | |
Test status | |
Simulation time | 242859319 ps |
CPU time | 5.86 seconds |
Started | Jun 07 08:24:16 PM PDT 24 |
Finished | Jun 07 08:24:23 PM PDT 24 |
Peak memory | 213228 kb |
Host | smart-8bde55d6-5fed-485e-90e3-687faa7d137f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817069684 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.817069684 |
Directory | /workspace/14.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1885799579 |
Short name | T135 |
Test name | |
Test status | |
Simulation time | 2847861496 ps |
CPU time | 11.46 seconds |
Started | Jun 07 08:24:19 PM PDT 24 |
Finished | Jun 07 08:24:35 PM PDT 24 |
Peak memory | 213392 kb |
Host | smart-2a000b3e-bfc2-4013-9ba1-9c049fd12992 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885799579 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.1 885799579 |
Directory | /workspace/14.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.3399709393 |
Short name | T330 |
Test name | |
Test status | |
Simulation time | 294749882 ps |
CPU time | 2.24 seconds |
Started | Jun 07 08:24:19 PM PDT 24 |
Finished | Jun 07 08:24:24 PM PDT 24 |
Peak memory | 215080 kb |
Host | smart-aa8aaafc-54b5-49fb-834d-964a015e96a0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399709393 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.3399709393 |
Directory | /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.1503170793 |
Short name | T346 |
Test name | |
Test status | |
Simulation time | 258278757 ps |
CPU time | 1.65 seconds |
Started | Jun 07 08:24:18 PM PDT 24 |
Finished | Jun 07 08:24:23 PM PDT 24 |
Peak memory | 213216 kb |
Host | smart-e8d95817-f1ac-4fa6-8bdf-699618c18e97 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503170793 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.1503170793 |
Directory | /workspace/15.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.484044282 |
Short name | T311 |
Test name | |
Test status | |
Simulation time | 18737747339 ps |
CPU time | 46.47 seconds |
Started | Jun 07 08:24:19 PM PDT 24 |
Finished | Jun 07 08:25:09 PM PDT 24 |
Peak memory | 205040 kb |
Host | smart-a26263a0-ecce-4e6a-815e-74173e7f0f26 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484044282 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15. rv_dm_jtag_dmi_csr_bit_bash.484044282 |
Directory | /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.2847122705 |
Short name | T296 |
Test name | |
Test status | |
Simulation time | 4549434367 ps |
CPU time | 1.92 seconds |
Started | Jun 07 08:24:19 PM PDT 24 |
Finished | Jun 07 08:24:25 PM PDT 24 |
Peak memory | 205076 kb |
Host | smart-8d8de726-7e1e-44ba-a311-4b1a9e118182 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847122705 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw. 2847122705 |
Directory | /workspace/15.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3580768558 |
Short name | T313 |
Test name | |
Test status | |
Simulation time | 1319946411 ps |
CPU time | 1 seconds |
Started | Jun 07 08:24:19 PM PDT 24 |
Finished | Jun 07 08:24:24 PM PDT 24 |
Peak memory | 204764 kb |
Host | smart-2a747883-c25c-4f39-bb5d-8ad028d62538 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580768558 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw. 3580768558 |
Directory | /workspace/15.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.2412159336 |
Short name | T119 |
Test name | |
Test status | |
Simulation time | 3753326623 ps |
CPU time | 4.05 seconds |
Started | Jun 07 08:24:19 PM PDT 24 |
Finished | Jun 07 08:24:27 PM PDT 24 |
Peak memory | 205124 kb |
Host | smart-69023b06-7ddd-4d74-af7b-e39ee40a0c23 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412159336 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same _csr_outstanding.2412159336 |
Directory | /workspace/15.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.1033556964 |
Short name | T367 |
Test name | |
Test status | |
Simulation time | 556393399 ps |
CPU time | 5.87 seconds |
Started | Jun 07 08:24:18 PM PDT 24 |
Finished | Jun 07 08:24:26 PM PDT 24 |
Peak memory | 213336 kb |
Host | smart-62751a1e-7494-4928-945d-d210b338b960 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033556964 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.1033556964 |
Directory | /workspace/15.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.115065762 |
Short name | T133 |
Test name | |
Test status | |
Simulation time | 4168967371 ps |
CPU time | 25.7 seconds |
Started | Jun 07 08:24:19 PM PDT 24 |
Finished | Jun 07 08:24:49 PM PDT 24 |
Peak memory | 213376 kb |
Host | smart-eab2b5e2-affa-4c8f-ab7f-040c6f595975 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115065762 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.115065762 |
Directory | /workspace/15.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2034974574 |
Short name | T82 |
Test name | |
Test status | |
Simulation time | 2793982041 ps |
CPU time | 8.65 seconds |
Started | Jun 07 08:24:18 PM PDT 24 |
Finished | Jun 07 08:24:28 PM PDT 24 |
Peak memory | 221652 kb |
Host | smart-08904706-47e2-4bbf-ba04-0ef224e1e4d3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034974574 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.2034974574 |
Directory | /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2823950924 |
Short name | T112 |
Test name | |
Test status | |
Simulation time | 190749257 ps |
CPU time | 1.69 seconds |
Started | Jun 07 08:24:17 PM PDT 24 |
Finished | Jun 07 08:24:20 PM PDT 24 |
Peak memory | 213244 kb |
Host | smart-d46a9653-a074-45ec-9879-f50ad1844b2d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823950924 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.2823950924 |
Directory | /workspace/16.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.2864224181 |
Short name | T335 |
Test name | |
Test status | |
Simulation time | 18654133142 ps |
CPU time | 13.25 seconds |
Started | Jun 07 08:24:19 PM PDT 24 |
Finished | Jun 07 08:24:37 PM PDT 24 |
Peak memory | 205012 kb |
Host | smart-b4851681-c36c-475f-9793-4dbd048572f5 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864224181 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16 .rv_dm_jtag_dmi_csr_bit_bash.2864224181 |
Directory | /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2664789641 |
Short name | T284 |
Test name | |
Test status | |
Simulation time | 3600510219 ps |
CPU time | 7.08 seconds |
Started | Jun 07 08:24:17 PM PDT 24 |
Finished | Jun 07 08:24:25 PM PDT 24 |
Peak memory | 205000 kb |
Host | smart-5282cd4b-1226-4d59-9c2f-d0c53e34d3b9 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664789641 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw. 2664789641 |
Directory | /workspace/16.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2698895786 |
Short name | T399 |
Test name | |
Test status | |
Simulation time | 101235624 ps |
CPU time | 1.01 seconds |
Started | Jun 07 08:24:20 PM PDT 24 |
Finished | Jun 07 08:24:25 PM PDT 24 |
Peak memory | 204684 kb |
Host | smart-b4e6867d-a337-45b2-b5ca-fb11466163fb |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698895786 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw. 2698895786 |
Directory | /workspace/16.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3407068116 |
Short name | T101 |
Test name | |
Test status | |
Simulation time | 920402212 ps |
CPU time | 7.78 seconds |
Started | Jun 07 08:24:18 PM PDT 24 |
Finished | Jun 07 08:24:30 PM PDT 24 |
Peak memory | 205112 kb |
Host | smart-60dc4b48-500d-423f-acb4-3c9489af0f87 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407068116 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same _csr_outstanding.3407068116 |
Directory | /workspace/16.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.676647432 |
Short name | T366 |
Test name | |
Test status | |
Simulation time | 56230624 ps |
CPU time | 2.31 seconds |
Started | Jun 07 08:24:19 PM PDT 24 |
Finished | Jun 07 08:24:25 PM PDT 24 |
Peak memory | 213300 kb |
Host | smart-0fbf0879-cb52-4346-8e06-1f22b4d7d4be |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676647432 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.676647432 |
Directory | /workspace/16.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.2120912212 |
Short name | T137 |
Test name | |
Test status | |
Simulation time | 3408994293 ps |
CPU time | 17.88 seconds |
Started | Jun 07 08:24:17 PM PDT 24 |
Finished | Jun 07 08:24:36 PM PDT 24 |
Peak memory | 213448 kb |
Host | smart-c6eb9043-bef9-400a-9bc2-ff6c3bcf2181 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120912212 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.2 120912212 |
Directory | /workspace/16.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.3376950702 |
Short name | T280 |
Test name | |
Test status | |
Simulation time | 1715400841 ps |
CPU time | 5.25 seconds |
Started | Jun 07 08:24:24 PM PDT 24 |
Finished | Jun 07 08:24:32 PM PDT 24 |
Peak memory | 219596 kb |
Host | smart-60f054ec-08ee-4433-912c-cafa0ae9d7fe |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376950702 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.3376950702 |
Directory | /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.60706732 |
Short name | T103 |
Test name | |
Test status | |
Simulation time | 89017173 ps |
CPU time | 2.31 seconds |
Started | Jun 07 08:24:19 PM PDT 24 |
Finished | Jun 07 08:24:26 PM PDT 24 |
Peak memory | 213296 kb |
Host | smart-8955e6d4-c64a-462b-8ba1-752f4f747fb4 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60706732 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.60706732 |
Directory | /workspace/17.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.3291953459 |
Short name | T279 |
Test name | |
Test status | |
Simulation time | 5331910281 ps |
CPU time | 3.14 seconds |
Started | Jun 07 08:24:21 PM PDT 24 |
Finished | Jun 07 08:24:28 PM PDT 24 |
Peak memory | 204948 kb |
Host | smart-a5565828-6733-4a82-b9b5-084d1f5ba468 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291953459 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17 .rv_dm_jtag_dmi_csr_bit_bash.3291953459 |
Directory | /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.3396956174 |
Short name | T365 |
Test name | |
Test status | |
Simulation time | 2835424567 ps |
CPU time | 2.24 seconds |
Started | Jun 07 08:24:24 PM PDT 24 |
Finished | Jun 07 08:24:29 PM PDT 24 |
Peak memory | 205036 kb |
Host | smart-5a3e95a5-eea5-4fb7-9ccb-e3e2692e470d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396956174 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw. 3396956174 |
Directory | /workspace/17.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.1675236135 |
Short name | T295 |
Test name | |
Test status | |
Simulation time | 319981063 ps |
CPU time | 0.93 seconds |
Started | Jun 07 08:24:20 PM PDT 24 |
Finished | Jun 07 08:24:25 PM PDT 24 |
Peak memory | 204668 kb |
Host | smart-e9cd4277-770d-4637-87e6-0bb879edb475 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675236135 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw. 1675236135 |
Directory | /workspace/17.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.622569798 |
Short name | T79 |
Test name | |
Test status | |
Simulation time | 526138641 ps |
CPU time | 3.33 seconds |
Started | Jun 07 08:24:21 PM PDT 24 |
Finished | Jun 07 08:24:28 PM PDT 24 |
Peak memory | 213380 kb |
Host | smart-cf7b9d9c-73ad-4e7b-9754-0c24b6d34729 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622569798 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.622569798 |
Directory | /workspace/17.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1196221160 |
Short name | T304 |
Test name | |
Test status | |
Simulation time | 4279197571 ps |
CPU time | 3.92 seconds |
Started | Jun 07 08:24:22 PM PDT 24 |
Finished | Jun 07 08:24:30 PM PDT 24 |
Peak memory | 218740 kb |
Host | smart-db2e6edd-329d-4159-a33e-c44cf437e270 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196221160 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.1196221160 |
Directory | /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2033963182 |
Short name | T85 |
Test name | |
Test status | |
Simulation time | 836891342 ps |
CPU time | 2.59 seconds |
Started | Jun 07 08:24:22 PM PDT 24 |
Finished | Jun 07 08:24:28 PM PDT 24 |
Peak memory | 213428 kb |
Host | smart-3fa9a9e0-e1bf-4aac-a21f-6363107dece6 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033963182 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.2033963182 |
Directory | /workspace/18.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.2400269995 |
Short name | T364 |
Test name | |
Test status | |
Simulation time | 44803012317 ps |
CPU time | 13 seconds |
Started | Jun 07 08:24:21 PM PDT 24 |
Finished | Jun 07 08:24:39 PM PDT 24 |
Peak memory | 205068 kb |
Host | smart-4816fb97-f79b-4867-9876-ee504cc02b76 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400269995 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18 .rv_dm_jtag_dmi_csr_bit_bash.2400269995 |
Directory | /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.3878706526 |
Short name | T272 |
Test name | |
Test status | |
Simulation time | 7577392385 ps |
CPU time | 20.08 seconds |
Started | Jun 07 08:24:19 PM PDT 24 |
Finished | Jun 07 08:24:44 PM PDT 24 |
Peak memory | 205084 kb |
Host | smart-cf75ab10-d7dd-45ef-979e-8a629f3e27f3 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878706526 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw. 3878706526 |
Directory | /workspace/18.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.3103198577 |
Short name | T301 |
Test name | |
Test status | |
Simulation time | 125091867 ps |
CPU time | 0.9 seconds |
Started | Jun 07 08:24:21 PM PDT 24 |
Finished | Jun 07 08:24:27 PM PDT 24 |
Peak memory | 204736 kb |
Host | smart-2b09437b-2a42-47c9-9562-f57d204b3d50 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103198577 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw. 3103198577 |
Directory | /workspace/18.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1056105158 |
Short name | T95 |
Test name | |
Test status | |
Simulation time | 433697537 ps |
CPU time | 7.41 seconds |
Started | Jun 07 08:24:18 PM PDT 24 |
Finished | Jun 07 08:24:29 PM PDT 24 |
Peak memory | 205168 kb |
Host | smart-585e261e-af93-4c98-a2e5-5634a2cf871e |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056105158 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same _csr_outstanding.1056105158 |
Directory | /workspace/18.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.3246084727 |
Short name | T300 |
Test name | |
Test status | |
Simulation time | 418130066 ps |
CPU time | 2.21 seconds |
Started | Jun 07 08:24:20 PM PDT 24 |
Finished | Jun 07 08:24:26 PM PDT 24 |
Peak memory | 213332 kb |
Host | smart-194e3bfa-9f89-4244-8f92-9ee26af1b4fa |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246084727 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.3246084727 |
Directory | /workspace/18.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.43163994 |
Short name | T136 |
Test name | |
Test status | |
Simulation time | 1724694973 ps |
CPU time | 17.21 seconds |
Started | Jun 07 08:24:19 PM PDT 24 |
Finished | Jun 07 08:24:41 PM PDT 24 |
Peak memory | 213304 kb |
Host | smart-4d7d0e6c-7ccc-4e74-84ff-2b29a88eec68 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43163994 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.43163994 |
Directory | /workspace/18.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1157278392 |
Short name | T325 |
Test name | |
Test status | |
Simulation time | 272732444 ps |
CPU time | 3.23 seconds |
Started | Jun 07 08:24:21 PM PDT 24 |
Finished | Jun 07 08:24:29 PM PDT 24 |
Peak memory | 213220 kb |
Host | smart-d959abb7-ac1e-4c78-bb7e-2edecd4f64cd |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157278392 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.1157278392 |
Directory | /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3945809016 |
Short name | T413 |
Test name | |
Test status | |
Simulation time | 397871413 ps |
CPU time | 2.31 seconds |
Started | Jun 07 08:24:21 PM PDT 24 |
Finished | Jun 07 08:24:27 PM PDT 24 |
Peak memory | 213320 kb |
Host | smart-13883145-f857-4092-933e-86a4b29b5da6 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945809016 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.3945809016 |
Directory | /workspace/19.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.678358901 |
Short name | T273 |
Test name | |
Test status | |
Simulation time | 27483228310 ps |
CPU time | 71.34 seconds |
Started | Jun 07 08:24:18 PM PDT 24 |
Finished | Jun 07 08:25:33 PM PDT 24 |
Peak memory | 205048 kb |
Host | smart-a5070d70-9900-4e27-9449-d57b551ca421 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678358901 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19. rv_dm_jtag_dmi_csr_bit_bash.678358901 |
Directory | /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2465009780 |
Short name | T408 |
Test name | |
Test status | |
Simulation time | 10233013092 ps |
CPU time | 27.89 seconds |
Started | Jun 07 08:24:22 PM PDT 24 |
Finished | Jun 07 08:24:54 PM PDT 24 |
Peak memory | 205040 kb |
Host | smart-2165495d-669f-4719-83c9-0f294f08e67d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465009780 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw. 2465009780 |
Directory | /workspace/19.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.4112550351 |
Short name | T371 |
Test name | |
Test status | |
Simulation time | 451631247 ps |
CPU time | 1.33 seconds |
Started | Jun 07 08:24:20 PM PDT 24 |
Finished | Jun 07 08:24:26 PM PDT 24 |
Peak memory | 204716 kb |
Host | smart-dc7afce0-c4cf-4872-9cea-80a55b9623bc |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112550351 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw. 4112550351 |
Directory | /workspace/19.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.4103482684 |
Short name | T118 |
Test name | |
Test status | |
Simulation time | 1920692769 ps |
CPU time | 7.78 seconds |
Started | Jun 07 08:24:24 PM PDT 24 |
Finished | Jun 07 08:24:34 PM PDT 24 |
Peak memory | 205176 kb |
Host | smart-6775ecd5-d390-426e-ad87-747a04522bcb |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103482684 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same _csr_outstanding.4103482684 |
Directory | /workspace/19.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3669637308 |
Short name | T350 |
Test name | |
Test status | |
Simulation time | 378496216 ps |
CPU time | 2.92 seconds |
Started | Jun 07 08:24:23 PM PDT 24 |
Finished | Jun 07 08:24:29 PM PDT 24 |
Peak memory | 213320 kb |
Host | smart-2ae408ec-00ab-4331-a755-11cfa10b1a0f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669637308 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.3669637308 |
Directory | /workspace/19.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.727621557 |
Short name | T140 |
Test name | |
Test status | |
Simulation time | 3216936809 ps |
CPU time | 10.68 seconds |
Started | Jun 07 08:24:27 PM PDT 24 |
Finished | Jun 07 08:24:40 PM PDT 24 |
Peak memory | 213084 kb |
Host | smart-0d54c68a-5194-4f0e-ac05-6c8b7116d314 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727621557 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.727621557 |
Directory | /workspace/19.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.182681316 |
Short name | T102 |
Test name | |
Test status | |
Simulation time | 1688960414 ps |
CPU time | 32.06 seconds |
Started | Jun 07 08:23:51 PM PDT 24 |
Finished | Jun 07 08:24:25 PM PDT 24 |
Peak memory | 205104 kb |
Host | smart-af6ee730-4f39-4c13-a2fe-ec9225e5783d |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182681316 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 2.rv_dm_csr_aliasing.182681316 |
Directory | /workspace/2.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.1103529833 |
Short name | T111 |
Test name | |
Test status | |
Simulation time | 1448906743 ps |
CPU time | 27.5 seconds |
Started | Jun 07 08:24:04 PM PDT 24 |
Finished | Jun 07 08:24:33 PM PDT 24 |
Peak memory | 204924 kb |
Host | smart-6a7ac102-aae4-4ef4-85c0-3ae70444cf6a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103529833 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.1103529833 |
Directory | /workspace/2.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.1808072995 |
Short name | T115 |
Test name | |
Test status | |
Simulation time | 383763750 ps |
CPU time | 1.52 seconds |
Started | Jun 07 08:23:56 PM PDT 24 |
Finished | Jun 07 08:23:58 PM PDT 24 |
Peak memory | 213320 kb |
Host | smart-82f7453f-3977-4453-b950-a1aa5efc8336 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808072995 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.1808072995 |
Directory | /workspace/2.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.993646080 |
Short name | T401 |
Test name | |
Test status | |
Simulation time | 959786211 ps |
CPU time | 2.73 seconds |
Started | Jun 07 08:23:55 PM PDT 24 |
Finished | Jun 07 08:23:58 PM PDT 24 |
Peak memory | 215068 kb |
Host | smart-bed45fda-997a-4624-954f-74804428a312 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993646080 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.993646080 |
Directory | /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2131935031 |
Short name | T356 |
Test name | |
Test status | |
Simulation time | 41219909167 ps |
CPU time | 55.98 seconds |
Started | Jun 07 08:23:51 PM PDT 24 |
Finished | Jun 07 08:24:49 PM PDT 24 |
Peak memory | 205132 kb |
Host | smart-7151b6e5-a856-494b-a9a3-06d8c4a38999 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131935031 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs r_aliasing.2131935031 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.4270981313 |
Short name | T289 |
Test name | |
Test status | |
Simulation time | 27409306949 ps |
CPU time | 14.98 seconds |
Started | Jun 07 08:23:52 PM PDT 24 |
Finished | Jun 07 08:24:09 PM PDT 24 |
Peak memory | 205116 kb |
Host | smart-5e3fbc54-b3d5-4bf2-a742-f1a55a582065 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270981313 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2. rv_dm_jtag_dmi_csr_bit_bash.4270981313 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.3108270417 |
Short name | T332 |
Test name | |
Test status | |
Simulation time | 9444546364 ps |
CPU time | 25.92 seconds |
Started | Jun 07 08:23:50 PM PDT 24 |
Finished | Jun 07 08:24:18 PM PDT 24 |
Peak memory | 205172 kb |
Host | smart-0ab15a38-372e-42a3-a4d1-eb8513e3bde4 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108270417 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs r_hw_reset.3108270417 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.3362771517 |
Short name | T309 |
Test name | |
Test status | |
Simulation time | 5711163342 ps |
CPU time | 4.89 seconds |
Started | Jun 07 08:23:51 PM PDT 24 |
Finished | Jun 07 08:23:58 PM PDT 24 |
Peak memory | 205144 kb |
Host | smart-951d7f9d-fcf7-4937-b709-0a4878f194fa |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362771517 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.3 362771517 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.2104973374 |
Short name | T337 |
Test name | |
Test status | |
Simulation time | 570222356 ps |
CPU time | 2.17 seconds |
Started | Jun 07 08:23:51 PM PDT 24 |
Finished | Jun 07 08:23:55 PM PDT 24 |
Peak memory | 204728 kb |
Host | smart-3df5de51-77a3-4c62-8d0d-4373b6ebb996 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104973374 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_aliasing.2104973374 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1150149137 |
Short name | T73 |
Test name | |
Test status | |
Simulation time | 5610061108 ps |
CPU time | 6.26 seconds |
Started | Jun 07 08:23:53 PM PDT 24 |
Finished | Jun 07 08:24:00 PM PDT 24 |
Peak memory | 205028 kb |
Host | smart-40fcec01-fbbb-44c9-89ee-36d9a57e9e87 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150149137 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_bit_bash.1150149137 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3907573443 |
Short name | T74 |
Test name | |
Test status | |
Simulation time | 735448757 ps |
CPU time | 1.11 seconds |
Started | Jun 07 08:23:59 PM PDT 24 |
Finished | Jun 07 08:24:01 PM PDT 24 |
Peak memory | 204776 kb |
Host | smart-0c52cb3d-148a-40f7-9c81-81fe7824d7b1 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907573443 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_hw_reset.3907573443 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.1745090301 |
Short name | T278 |
Test name | |
Test status | |
Simulation time | 205941483 ps |
CPU time | 0.95 seconds |
Started | Jun 07 08:23:59 PM PDT 24 |
Finished | Jun 07 08:24:01 PM PDT 24 |
Peak memory | 204760 kb |
Host | smart-d0896cb1-7d80-4a33-ac22-6dac7420bfff |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745090301 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.1 745090301 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1544619862 |
Short name | T306 |
Test name | |
Test status | |
Simulation time | 63941369 ps |
CPU time | 0.73 seconds |
Started | Jun 07 08:23:58 PM PDT 24 |
Finished | Jun 07 08:24:00 PM PDT 24 |
Peak memory | 204652 kb |
Host | smart-e2fbf2ad-3244-4809-b3ec-bb6af7dc3ce3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544619862 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par tial_access.1544619862 |
Directory | /workspace/2.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.2332492764 |
Short name | T396 |
Test name | |
Test status | |
Simulation time | 58859043 ps |
CPU time | 0.73 seconds |
Started | Jun 07 08:23:56 PM PDT 24 |
Finished | Jun 07 08:23:57 PM PDT 24 |
Peak memory | 204708 kb |
Host | smart-bd16896b-0e11-4d02-a07a-aebd8c4fbebc |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332492764 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.2332492764 |
Directory | /workspace/2.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.1957082889 |
Short name | T391 |
Test name | |
Test status | |
Simulation time | 306741261 ps |
CPU time | 3.78 seconds |
Started | Jun 07 08:23:56 PM PDT 24 |
Finished | Jun 07 08:24:00 PM PDT 24 |
Peak memory | 205156 kb |
Host | smart-9ce4bcc3-426e-4a6d-a69b-e074244e3b5e |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957082889 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_ csr_outstanding.1957082889 |
Directory | /workspace/2.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.70799442 |
Short name | T390 |
Test name | |
Test status | |
Simulation time | 69802076410 ps |
CPU time | 27.11 seconds |
Started | Jun 07 08:23:49 PM PDT 24 |
Finished | Jun 07 08:24:18 PM PDT 24 |
Peak memory | 229812 kb |
Host | smart-5df7878e-61f1-42c0-ba5c-511071c57e39 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70799442 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.70799442 |
Directory | /workspace/2.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.3769323429 |
Short name | T363 |
Test name | |
Test status | |
Simulation time | 383917664 ps |
CPU time | 3.81 seconds |
Started | Jun 07 08:23:47 PM PDT 24 |
Finished | Jun 07 08:23:52 PM PDT 24 |
Peak memory | 213300 kb |
Host | smart-c1a9a24d-f453-4dd6-afa3-11201cf62dba |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769323429 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.3769323429 |
Directory | /workspace/2.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2454097218 |
Short name | T381 |
Test name | |
Test status | |
Simulation time | 2918575832 ps |
CPU time | 14.86 seconds |
Started | Jun 07 08:23:58 PM PDT 24 |
Finished | Jun 07 08:24:14 PM PDT 24 |
Peak memory | 213392 kb |
Host | smart-ca93d5a5-f9ea-408b-a8f9-0d05445f6f67 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454097218 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.2454097218 |
Directory | /workspace/2.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.3681596289 |
Short name | T108 |
Test name | |
Test status | |
Simulation time | 4258902438 ps |
CPU time | 78.97 seconds |
Started | Jun 07 08:23:58 PM PDT 24 |
Finished | Jun 07 08:25:19 PM PDT 24 |
Peak memory | 217924 kb |
Host | smart-a9df43ad-e9df-47f4-8891-4a35ea9fff11 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681596289 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 3.rv_dm_csr_aliasing.3681596289 |
Directory | /workspace/3.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1332554986 |
Short name | T91 |
Test name | |
Test status | |
Simulation time | 5918640190 ps |
CPU time | 29.72 seconds |
Started | Jun 07 08:23:57 PM PDT 24 |
Finished | Jun 07 08:24:28 PM PDT 24 |
Peak memory | 205224 kb |
Host | smart-01904618-e886-455c-ac16-c8dad8a860f3 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332554986 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.1332554986 |
Directory | /workspace/3.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1472815312 |
Short name | T113 |
Test name | |
Test status | |
Simulation time | 89921424 ps |
CPU time | 2.35 seconds |
Started | Jun 07 08:24:04 PM PDT 24 |
Finished | Jun 07 08:24:07 PM PDT 24 |
Peak memory | 214240 kb |
Host | smart-18a12d77-82fa-4993-9b5c-de89528d83cf |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472815312 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.1472815312 |
Directory | /workspace/3.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.487732505 |
Short name | T385 |
Test name | |
Test status | |
Simulation time | 4288026092 ps |
CPU time | 4.34 seconds |
Started | Jun 07 08:24:07 PM PDT 24 |
Finished | Jun 07 08:24:13 PM PDT 24 |
Peak memory | 213368 kb |
Host | smart-58f0e811-c1d2-4a56-98b0-2207bc23daac |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487732505 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.487732505 |
Directory | /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.855643454 |
Short name | T88 |
Test name | |
Test status | |
Simulation time | 256890792 ps |
CPU time | 2.11 seconds |
Started | Jun 07 08:23:57 PM PDT 24 |
Finished | Jun 07 08:24:01 PM PDT 24 |
Peak memory | 213296 kb |
Host | smart-27373e93-1ed7-4c3a-b710-f8d25b2173fa |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855643454 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.855643454 |
Directory | /workspace/3.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.276365057 |
Short name | T303 |
Test name | |
Test status | |
Simulation time | 13511893958 ps |
CPU time | 36.66 seconds |
Started | Jun 07 08:23:57 PM PDT 24 |
Finished | Jun 07 08:24:35 PM PDT 24 |
Peak memory | 205024 kb |
Host | smart-0f75b717-b4df-407d-b9e6-5ab53ebcb484 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276365057 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.r v_dm_jtag_dmi_csr_bit_bash.276365057 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.3062662893 |
Short name | T287 |
Test name | |
Test status | |
Simulation time | 4539196147 ps |
CPU time | 12.82 seconds |
Started | Jun 07 08:24:04 PM PDT 24 |
Finished | Jun 07 08:24:18 PM PDT 24 |
Peak memory | 205156 kb |
Host | smart-59cd17e2-60e8-4f37-8baa-7cd452c8de75 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062662893 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs r_hw_reset.3062662893 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.2664118112 |
Short name | T285 |
Test name | |
Test status | |
Simulation time | 6902232117 ps |
CPU time | 4.68 seconds |
Started | Jun 07 08:23:57 PM PDT 24 |
Finished | Jun 07 08:24:03 PM PDT 24 |
Peak memory | 205040 kb |
Host | smart-84551742-0a61-4016-8ef6-3ff9412fc377 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664118112 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.2 664118112 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3664676749 |
Short name | T316 |
Test name | |
Test status | |
Simulation time | 415056107 ps |
CPU time | 1.03 seconds |
Started | Jun 07 08:23:56 PM PDT 24 |
Finished | Jun 07 08:23:58 PM PDT 24 |
Peak memory | 204668 kb |
Host | smart-bcb69955-b095-4c70-88fd-ac2019e24de9 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664676749 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_aliasing.3664676749 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2678325947 |
Short name | T377 |
Test name | |
Test status | |
Simulation time | 3301245188 ps |
CPU time | 3.3 seconds |
Started | Jun 07 08:23:56 PM PDT 24 |
Finished | Jun 07 08:24:01 PM PDT 24 |
Peak memory | 204912 kb |
Host | smart-705ee71d-1f74-4e14-aed4-b7eebbedd0fb |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678325947 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_bit_bash.2678325947 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.2522176437 |
Short name | T384 |
Test name | |
Test status | |
Simulation time | 318945516 ps |
CPU time | 1.4 seconds |
Started | Jun 07 08:23:56 PM PDT 24 |
Finished | Jun 07 08:23:59 PM PDT 24 |
Peak memory | 204756 kb |
Host | smart-41442698-6b78-44bc-854a-02d65039d053 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522176437 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_hw_reset.2522176437 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2917162549 |
Short name | T292 |
Test name | |
Test status | |
Simulation time | 911639825 ps |
CPU time | 1.27 seconds |
Started | Jun 07 08:23:57 PM PDT 24 |
Finished | Jun 07 08:24:00 PM PDT 24 |
Peak memory | 204720 kb |
Host | smart-7c5b0701-e98e-4e5a-9d11-be24c8e68765 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917162549 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.2 917162549 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.1944657403 |
Short name | T372 |
Test name | |
Test status | |
Simulation time | 163244433 ps |
CPU time | 0.71 seconds |
Started | Jun 07 08:23:59 PM PDT 24 |
Finished | Jun 07 08:24:01 PM PDT 24 |
Peak memory | 204644 kb |
Host | smart-b2e1d673-05ed-41b2-96aa-ccfeefe14f5d |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944657403 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par tial_access.1944657403 |
Directory | /workspace/3.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.2595000266 |
Short name | T277 |
Test name | |
Test status | |
Simulation time | 88835441 ps |
CPU time | 0.74 seconds |
Started | Jun 07 08:23:58 PM PDT 24 |
Finished | Jun 07 08:24:01 PM PDT 24 |
Peak memory | 204724 kb |
Host | smart-1c51a2d5-66f6-489c-a8d4-f865e1c3c72a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595000266 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.2595000266 |
Directory | /workspace/3.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.4268338258 |
Short name | T345 |
Test name | |
Test status | |
Simulation time | 595561986 ps |
CPU time | 8.13 seconds |
Started | Jun 07 08:24:09 PM PDT 24 |
Finished | Jun 07 08:24:19 PM PDT 24 |
Peak memory | 205076 kb |
Host | smart-de8ffe08-bbd5-4aa3-9653-9d8f24045e42 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268338258 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_ csr_outstanding.4268338258 |
Directory | /workspace/3.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2672727983 |
Short name | T78 |
Test name | |
Test status | |
Simulation time | 607754805 ps |
CPU time | 3.61 seconds |
Started | Jun 07 08:23:58 PM PDT 24 |
Finished | Jun 07 08:24:04 PM PDT 24 |
Peak memory | 213256 kb |
Host | smart-0a6a4e13-57a5-4aaa-8920-3b5628eacc89 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672727983 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.2672727983 |
Directory | /workspace/3.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.1401968570 |
Short name | T139 |
Test name | |
Test status | |
Simulation time | 3208288712 ps |
CPU time | 20.49 seconds |
Started | Jun 07 08:23:58 PM PDT 24 |
Finished | Jun 07 08:24:20 PM PDT 24 |
Peak memory | 213396 kb |
Host | smart-cb8b13b0-8468-4777-b93b-5123154766c5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401968570 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.1401968570 |
Directory | /workspace/3.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1056552267 |
Short name | T282 |
Test name | |
Test status | |
Simulation time | 2042080429 ps |
CPU time | 32.51 seconds |
Started | Jun 07 08:24:08 PM PDT 24 |
Finished | Jun 07 08:24:43 PM PDT 24 |
Peak memory | 205068 kb |
Host | smart-135e297f-8933-40e7-b563-e2a84076db3f |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056552267 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 4.rv_dm_csr_aliasing.1056552267 |
Directory | /workspace/4.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.578495854 |
Short name | T297 |
Test name | |
Test status | |
Simulation time | 9837883806 ps |
CPU time | 34.97 seconds |
Started | Jun 07 08:24:08 PM PDT 24 |
Finished | Jun 07 08:24:45 PM PDT 24 |
Peak memory | 205216 kb |
Host | smart-1f62e4a3-fe79-4627-960c-6524f33b2336 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578495854 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.578495854 |
Directory | /workspace/4.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.3423535833 |
Short name | T409 |
Test name | |
Test status | |
Simulation time | 390472557 ps |
CPU time | 2.8 seconds |
Started | Jun 07 08:24:07 PM PDT 24 |
Finished | Jun 07 08:24:12 PM PDT 24 |
Peak memory | 213416 kb |
Host | smart-c6befcb2-6aba-4c20-8cf5-2d296fd3a64d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423535833 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.3423535833 |
Directory | /workspace/4.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2537837120 |
Short name | T379 |
Test name | |
Test status | |
Simulation time | 1604954062 ps |
CPU time | 4.15 seconds |
Started | Jun 07 08:24:07 PM PDT 24 |
Finished | Jun 07 08:24:13 PM PDT 24 |
Peak memory | 221444 kb |
Host | smart-e3076bbd-c57f-49cc-b072-446bf935ce1b |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537837120 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.2537837120 |
Directory | /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.3946762256 |
Short name | T107 |
Test name | |
Test status | |
Simulation time | 65190353 ps |
CPU time | 1.49 seconds |
Started | Jun 07 08:24:08 PM PDT 24 |
Finished | Jun 07 08:24:11 PM PDT 24 |
Peak memory | 213248 kb |
Host | smart-5ef446ed-96d5-4a2b-80c4-470bdba73491 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946762256 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.3946762256 |
Directory | /workspace/4.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.541647142 |
Short name | T271 |
Test name | |
Test status | |
Simulation time | 78980363833 ps |
CPU time | 141.7 seconds |
Started | Jun 07 08:24:07 PM PDT 24 |
Finished | Jun 07 08:26:31 PM PDT 24 |
Peak memory | 205072 kb |
Host | smart-c8c071b9-c032-4120-8336-91c553165410 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541647142 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.r v_dm_jtag_dmi_csr_bit_bash.541647142 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.3512380555 |
Short name | T94 |
Test name | |
Test status | |
Simulation time | 13960798340 ps |
CPU time | 7.96 seconds |
Started | Jun 07 08:24:06 PM PDT 24 |
Finished | Jun 07 08:24:15 PM PDT 24 |
Peak memory | 205032 kb |
Host | smart-f1a499d0-e6c2-4d25-9a6d-c4cd8a79cfe3 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512380555 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs r_hw_reset.3512380555 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.2583490827 |
Short name | T275 |
Test name | |
Test status | |
Simulation time | 1049005437 ps |
CPU time | 1.75 seconds |
Started | Jun 07 08:24:08 PM PDT 24 |
Finished | Jun 07 08:24:11 PM PDT 24 |
Peak memory | 204940 kb |
Host | smart-7ef3ae88-a315-4d9d-aaac-c989da8fab80 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583490827 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.2 583490827 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.756118383 |
Short name | T406 |
Test name | |
Test status | |
Simulation time | 1601388424 ps |
CPU time | 2.94 seconds |
Started | Jun 07 08:24:12 PM PDT 24 |
Finished | Jun 07 08:24:16 PM PDT 24 |
Peak memory | 204696 kb |
Host | smart-d958cb96-c403-4f41-a85c-97d346b669c3 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756118383 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr _aliasing.756118383 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.1599749951 |
Short name | T342 |
Test name | |
Test status | |
Simulation time | 13345492935 ps |
CPU time | 10.12 seconds |
Started | Jun 07 08:24:08 PM PDT 24 |
Finished | Jun 07 08:24:20 PM PDT 24 |
Peak memory | 204972 kb |
Host | smart-a64ea80e-eb89-4f96-a165-68edff2ff797 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599749951 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs r_bit_bash.1599749951 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.1839634184 |
Short name | T398 |
Test name | |
Test status | |
Simulation time | 204512105 ps |
CPU time | 1.12 seconds |
Started | Jun 07 08:24:08 PM PDT 24 |
Finished | Jun 07 08:24:11 PM PDT 24 |
Peak memory | 204764 kb |
Host | smart-d0387b1d-4319-483c-9d03-a8e98f48871e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839634184 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs r_hw_reset.1839634184 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2000568787 |
Short name | T375 |
Test name | |
Test status | |
Simulation time | 642546686 ps |
CPU time | 1.52 seconds |
Started | Jun 07 08:24:11 PM PDT 24 |
Finished | Jun 07 08:24:14 PM PDT 24 |
Peak memory | 204644 kb |
Host | smart-d00ddfc5-3a2e-4eef-8a8f-13a466d950ea |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000568787 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.2 000568787 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1608147099 |
Short name | T286 |
Test name | |
Test status | |
Simulation time | 107020174 ps |
CPU time | 0.82 seconds |
Started | Jun 07 08:24:09 PM PDT 24 |
Finished | Jun 07 08:24:12 PM PDT 24 |
Peak memory | 204644 kb |
Host | smart-9a55b1cf-8531-4628-b122-eb104980a993 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608147099 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par tial_access.1608147099 |
Directory | /workspace/4.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.2608005645 |
Short name | T404 |
Test name | |
Test status | |
Simulation time | 85032685 ps |
CPU time | 0.73 seconds |
Started | Jun 07 08:24:10 PM PDT 24 |
Finished | Jun 07 08:24:13 PM PDT 24 |
Peak memory | 204644 kb |
Host | smart-d10ac952-f3c8-4c86-837a-26870ec92d9c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608005645 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.2608005645 |
Directory | /workspace/4.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.2018018867 |
Short name | T100 |
Test name | |
Test status | |
Simulation time | 141924008 ps |
CPU time | 3.9 seconds |
Started | Jun 07 08:24:09 PM PDT 24 |
Finished | Jun 07 08:24:14 PM PDT 24 |
Peak memory | 205044 kb |
Host | smart-884c3a46-b9e5-43cc-8d05-8dd5d5c9df6a |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018018867 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_ csr_outstanding.2018018867 |
Directory | /workspace/4.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.436167691 |
Short name | T29 |
Test name | |
Test status | |
Simulation time | 25743931438 ps |
CPU time | 40.46 seconds |
Started | Jun 07 08:24:09 PM PDT 24 |
Finished | Jun 07 08:24:52 PM PDT 24 |
Peak memory | 221632 kb |
Host | smart-e2b29ae3-1e64-4f4a-9d91-ec9a1360908d |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436167691 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.436167691 |
Directory | /workspace/4.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.3833472401 |
Short name | T83 |
Test name | |
Test status | |
Simulation time | 97853207 ps |
CPU time | 5.82 seconds |
Started | Jun 07 08:24:09 PM PDT 24 |
Finished | Jun 07 08:24:17 PM PDT 24 |
Peak memory | 213348 kb |
Host | smart-9e3f42b4-0407-4352-b600-4d318a87362b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833472401 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.3833472401 |
Directory | /workspace/4.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3288036513 |
Short name | T400 |
Test name | |
Test status | |
Simulation time | 2710704905 ps |
CPU time | 6.91 seconds |
Started | Jun 07 08:24:08 PM PDT 24 |
Finished | Jun 07 08:24:17 PM PDT 24 |
Peak memory | 213428 kb |
Host | smart-e6fba37b-0bad-44df-b48a-df447251b240 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288036513 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.3288036513 |
Directory | /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.745639274 |
Short name | T328 |
Test name | |
Test status | |
Simulation time | 945017553 ps |
CPU time | 1.68 seconds |
Started | Jun 07 08:24:07 PM PDT 24 |
Finished | Jun 07 08:24:11 PM PDT 24 |
Peak memory | 213392 kb |
Host | smart-a2c223d0-9a61-4254-b92a-2d32f140f0eb |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745639274 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.745639274 |
Directory | /workspace/5.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.587452714 |
Short name | T331 |
Test name | |
Test status | |
Simulation time | 23853961398 ps |
CPU time | 33.91 seconds |
Started | Jun 07 08:24:07 PM PDT 24 |
Finished | Jun 07 08:24:43 PM PDT 24 |
Peak memory | 205012 kb |
Host | smart-998f3e18-fc14-41be-9249-b90cf3dde4e9 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587452714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.r v_dm_jtag_dmi_csr_bit_bash.587452714 |
Directory | /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.1116199627 |
Short name | T324 |
Test name | |
Test status | |
Simulation time | 2532204511 ps |
CPU time | 1.97 seconds |
Started | Jun 07 08:24:08 PM PDT 24 |
Finished | Jun 07 08:24:12 PM PDT 24 |
Peak memory | 204992 kb |
Host | smart-e1c78e82-7519-4528-b0d1-61e0989a3124 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116199627 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.1 116199627 |
Directory | /workspace/5.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.2498718093 |
Short name | T72 |
Test name | |
Test status | |
Simulation time | 567801910 ps |
CPU time | 0.93 seconds |
Started | Jun 07 08:24:10 PM PDT 24 |
Finished | Jun 07 08:24:13 PM PDT 24 |
Peak memory | 204676 kb |
Host | smart-b3dfcee2-7fc3-41f3-a939-fe62221dfc4f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498718093 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.2 498718093 |
Directory | /workspace/5.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1172827432 |
Short name | T117 |
Test name | |
Test status | |
Simulation time | 1538680002 ps |
CPU time | 7.28 seconds |
Started | Jun 07 08:24:09 PM PDT 24 |
Finished | Jun 07 08:24:18 PM PDT 24 |
Peak memory | 205084 kb |
Host | smart-5d3208f0-2320-4542-8b19-cc4412e0bb76 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172827432 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_ csr_outstanding.1172827432 |
Directory | /workspace/5.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.2547324690 |
Short name | T322 |
Test name | |
Test status | |
Simulation time | 77734918996 ps |
CPU time | 63.95 seconds |
Started | Jun 07 08:24:05 PM PDT 24 |
Finished | Jun 07 08:25:10 PM PDT 24 |
Peak memory | 224336 kb |
Host | smart-1fa535de-037d-4264-af93-3064a806da1b |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547324690 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.2547324690 |
Directory | /workspace/5.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.125714907 |
Short name | T122 |
Test name | |
Test status | |
Simulation time | 1106005958 ps |
CPU time | 6.1 seconds |
Started | Jun 07 08:24:08 PM PDT 24 |
Finished | Jun 07 08:24:16 PM PDT 24 |
Peak memory | 213344 kb |
Host | smart-57ab0c55-f88a-4135-8efc-2d0eda01a545 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125714907 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.125714907 |
Directory | /workspace/5.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.82861361 |
Short name | T132 |
Test name | |
Test status | |
Simulation time | 2247817035 ps |
CPU time | 10.8 seconds |
Started | Jun 07 08:24:09 PM PDT 24 |
Finished | Jun 07 08:24:21 PM PDT 24 |
Peak memory | 213320 kb |
Host | smart-069c5820-f455-4da5-83c7-3afb2b4cb403 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82861361 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.82861361 |
Directory | /workspace/5.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.1137848257 |
Short name | T80 |
Test name | |
Test status | |
Simulation time | 1755551214 ps |
CPU time | 6.62 seconds |
Started | Jun 07 08:24:10 PM PDT 24 |
Finished | Jun 07 08:24:19 PM PDT 24 |
Peak memory | 221448 kb |
Host | smart-186dc36f-e110-4eb6-ae1c-648b360373e4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137848257 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.1137848257 |
Directory | /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1094314500 |
Short name | T114 |
Test name | |
Test status | |
Simulation time | 217713053 ps |
CPU time | 2.2 seconds |
Started | Jun 07 08:24:10 PM PDT 24 |
Finished | Jun 07 08:24:14 PM PDT 24 |
Peak memory | 213280 kb |
Host | smart-f2cd2374-70f5-4845-903e-83439eb83837 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094314500 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.1094314500 |
Directory | /workspace/6.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.1215068263 |
Short name | T394 |
Test name | |
Test status | |
Simulation time | 45372973708 ps |
CPU time | 59.82 seconds |
Started | Jun 07 08:24:07 PM PDT 24 |
Finished | Jun 07 08:25:08 PM PDT 24 |
Peak memory | 205012 kb |
Host | smart-ff3b9595-49a2-466a-88bf-e0edbc8350a3 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215068263 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6. rv_dm_jtag_dmi_csr_bit_bash.1215068263 |
Directory | /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2013247464 |
Short name | T387 |
Test name | |
Test status | |
Simulation time | 3288470528 ps |
CPU time | 10.91 seconds |
Started | Jun 07 08:24:10 PM PDT 24 |
Finished | Jun 07 08:24:23 PM PDT 24 |
Peak memory | 204976 kb |
Host | smart-276b32d3-8d14-4b73-84d3-b59ad0c56f7d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013247464 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.2 013247464 |
Directory | /workspace/6.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.1055149012 |
Short name | T299 |
Test name | |
Test status | |
Simulation time | 896061818 ps |
CPU time | 0.8 seconds |
Started | Jun 07 08:24:12 PM PDT 24 |
Finished | Jun 07 08:24:14 PM PDT 24 |
Peak memory | 204760 kb |
Host | smart-f8d5c702-4a72-4be7-9569-8cc3a9ac17f7 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055149012 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.1 055149012 |
Directory | /workspace/6.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.3683158180 |
Short name | T104 |
Test name | |
Test status | |
Simulation time | 9111991832 ps |
CPU time | 9.03 seconds |
Started | Jun 07 08:24:07 PM PDT 24 |
Finished | Jun 07 08:24:17 PM PDT 24 |
Peak memory | 205220 kb |
Host | smart-949ef807-de03-4ddb-a980-8ecaf928bb63 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683158180 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_ csr_outstanding.3683158180 |
Directory | /workspace/6.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.1097671144 |
Short name | T380 |
Test name | |
Test status | |
Simulation time | 27238580232 ps |
CPU time | 76.07 seconds |
Started | Jun 07 08:24:10 PM PDT 24 |
Finished | Jun 07 08:25:28 PM PDT 24 |
Peak memory | 221680 kb |
Host | smart-6e5d891e-f831-4ce0-b6c3-b7976cab62ff |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097671144 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.1097671144 |
Directory | /workspace/6.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.1539345084 |
Short name | T361 |
Test name | |
Test status | |
Simulation time | 132103297 ps |
CPU time | 2.91 seconds |
Started | Jun 07 08:24:07 PM PDT 24 |
Finished | Jun 07 08:24:11 PM PDT 24 |
Peak memory | 213284 kb |
Host | smart-dc1aa9c0-96ef-4922-b957-5e4c320fd170 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539345084 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.1539345084 |
Directory | /workspace/6.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.118767564 |
Short name | T51 |
Test name | |
Test status | |
Simulation time | 3678345614 ps |
CPU time | 5.12 seconds |
Started | Jun 07 08:24:07 PM PDT 24 |
Finished | Jun 07 08:24:14 PM PDT 24 |
Peak memory | 218496 kb |
Host | smart-ad57d2e7-9614-4b7a-aa09-3ad1ff52f5d1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118767564 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.118767564 |
Directory | /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.1113590389 |
Short name | T98 |
Test name | |
Test status | |
Simulation time | 343482826 ps |
CPU time | 2.17 seconds |
Started | Jun 07 08:24:09 PM PDT 24 |
Finished | Jun 07 08:24:13 PM PDT 24 |
Peak memory | 213308 kb |
Host | smart-19ef84d2-52ec-4913-b3cc-62650c724a70 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113590389 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.1113590389 |
Directory | /workspace/7.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.978652773 |
Short name | T298 |
Test name | |
Test status | |
Simulation time | 11687060693 ps |
CPU time | 19.22 seconds |
Started | Jun 07 08:24:07 PM PDT 24 |
Finished | Jun 07 08:24:28 PM PDT 24 |
Peak memory | 205128 kb |
Host | smart-f793df57-8e39-42a3-ad65-24e1e2f630a7 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978652773 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.r v_dm_jtag_dmi_csr_bit_bash.978652773 |
Directory | /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.1440432149 |
Short name | T270 |
Test name | |
Test status | |
Simulation time | 5870944371 ps |
CPU time | 4.83 seconds |
Started | Jun 07 08:24:09 PM PDT 24 |
Finished | Jun 07 08:24:16 PM PDT 24 |
Peak memory | 205048 kb |
Host | smart-7a831ba3-4430-4fc7-8ceb-35d43c4ff43e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440432149 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.1 440432149 |
Directory | /workspace/7.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1888535395 |
Short name | T354 |
Test name | |
Test status | |
Simulation time | 862132944 ps |
CPU time | 2.94 seconds |
Started | Jun 07 08:24:08 PM PDT 24 |
Finished | Jun 07 08:24:13 PM PDT 24 |
Peak memory | 204764 kb |
Host | smart-35d63941-922a-4230-a444-6f23736726eb |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888535395 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.1 888535395 |
Directory | /workspace/7.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3592077057 |
Short name | T116 |
Test name | |
Test status | |
Simulation time | 342973679 ps |
CPU time | 4.03 seconds |
Started | Jun 07 08:24:05 PM PDT 24 |
Finished | Jun 07 08:24:11 PM PDT 24 |
Peak memory | 205076 kb |
Host | smart-ad53a2fd-243a-4a34-8cef-f454099cc1b4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592077057 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_ csr_outstanding.3592077057 |
Directory | /workspace/7.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.2587805837 |
Short name | T319 |
Test name | |
Test status | |
Simulation time | 87302975 ps |
CPU time | 3.03 seconds |
Started | Jun 07 08:24:10 PM PDT 24 |
Finished | Jun 07 08:24:15 PM PDT 24 |
Peak memory | 213292 kb |
Host | smart-ad7b48df-62a6-47f8-bdd2-17f2603028fe |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587805837 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.2587805837 |
Directory | /workspace/7.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.3866950992 |
Short name | T293 |
Test name | |
Test status | |
Simulation time | 3836608595 ps |
CPU time | 5.7 seconds |
Started | Jun 07 08:24:09 PM PDT 24 |
Finished | Jun 07 08:24:17 PM PDT 24 |
Peak memory | 220992 kb |
Host | smart-01d9f8a9-23ef-4d54-a2fa-0f00da1a07d8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866950992 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.3866950992 |
Directory | /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1959584622 |
Short name | T291 |
Test name | |
Test status | |
Simulation time | 134349070 ps |
CPU time | 1.87 seconds |
Started | Jun 07 08:24:09 PM PDT 24 |
Finished | Jun 07 08:24:13 PM PDT 24 |
Peak memory | 213304 kb |
Host | smart-4c62a882-aece-4179-b241-9bcc27195725 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959584622 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.1959584622 |
Directory | /workspace/8.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.3668104969 |
Short name | T340 |
Test name | |
Test status | |
Simulation time | 10508399134 ps |
CPU time | 20.74 seconds |
Started | Jun 07 08:24:06 PM PDT 24 |
Finished | Jun 07 08:24:28 PM PDT 24 |
Peak memory | 205016 kb |
Host | smart-c72a78f0-5ada-4b2f-a278-c79c7817cea8 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668104969 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8. rv_dm_jtag_dmi_csr_bit_bash.3668104969 |
Directory | /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3456067664 |
Short name | T308 |
Test name | |
Test status | |
Simulation time | 2593470790 ps |
CPU time | 7.22 seconds |
Started | Jun 07 08:24:10 PM PDT 24 |
Finished | Jun 07 08:24:19 PM PDT 24 |
Peak memory | 204920 kb |
Host | smart-a8359c6e-dfd1-40cd-8dd3-4cf44fbeeb0c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456067664 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.3 456067664 |
Directory | /workspace/8.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.751212988 |
Short name | T283 |
Test name | |
Test status | |
Simulation time | 1229464233 ps |
CPU time | 1.84 seconds |
Started | Jun 07 08:24:05 PM PDT 24 |
Finished | Jun 07 08:24:08 PM PDT 24 |
Peak memory | 204712 kb |
Host | smart-76da756f-a1a5-4059-b68c-aed621e08ba9 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751212988 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.751212988 |
Directory | /workspace/8.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.3323603692 |
Short name | T347 |
Test name | |
Test status | |
Simulation time | 2376139272 ps |
CPU time | 4.43 seconds |
Started | Jun 07 08:24:07 PM PDT 24 |
Finished | Jun 07 08:24:14 PM PDT 24 |
Peak memory | 205152 kb |
Host | smart-9ec25c5d-fe87-483e-a840-4af235334fa1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323603692 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_ csr_outstanding.3323603692 |
Directory | /workspace/8.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.3945123285 |
Short name | T31 |
Test name | |
Test status | |
Simulation time | 42405009421 ps |
CPU time | 63.34 seconds |
Started | Jun 07 08:24:08 PM PDT 24 |
Finished | Jun 07 08:25:14 PM PDT 24 |
Peak memory | 220776 kb |
Host | smart-5158a85c-13c4-44a9-aacd-a0b5c5eb981a |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945123285 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.3945123285 |
Directory | /workspace/8.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.1742568643 |
Short name | T92 |
Test name | |
Test status | |
Simulation time | 392449073 ps |
CPU time | 3.51 seconds |
Started | Jun 07 08:24:08 PM PDT 24 |
Finished | Jun 07 08:24:13 PM PDT 24 |
Peak memory | 213264 kb |
Host | smart-8a28882a-7ea1-40e7-9fcd-06d5af6a2fb1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742568643 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.1742568643 |
Directory | /workspace/8.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3237833505 |
Short name | T128 |
Test name | |
Test status | |
Simulation time | 5783028341 ps |
CPU time | 22.82 seconds |
Started | Jun 07 08:24:08 PM PDT 24 |
Finished | Jun 07 08:24:33 PM PDT 24 |
Peak memory | 213472 kb |
Host | smart-a0af468a-c4e1-4c66-8d67-d4e9d5b9c52d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237833505 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.3237833505 |
Directory | /workspace/8.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.2602704247 |
Short name | T318 |
Test name | |
Test status | |
Simulation time | 3281316227 ps |
CPU time | 9.03 seconds |
Started | Jun 07 08:24:19 PM PDT 24 |
Finished | Jun 07 08:24:33 PM PDT 24 |
Peak memory | 219316 kb |
Host | smart-c384299e-e0dc-4b0e-b2f2-24d538617102 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602704247 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.2602704247 |
Directory | /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.625776530 |
Short name | T86 |
Test name | |
Test status | |
Simulation time | 233205942 ps |
CPU time | 1.63 seconds |
Started | Jun 07 08:24:16 PM PDT 24 |
Finished | Jun 07 08:24:19 PM PDT 24 |
Peak memory | 213252 kb |
Host | smart-1ba53336-f5f2-4344-9313-24fc9322dba8 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625776530 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.625776530 |
Directory | /workspace/9.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.2700583084 |
Short name | T393 |
Test name | |
Test status | |
Simulation time | 26865674611 ps |
CPU time | 25.84 seconds |
Started | Jun 07 08:24:10 PM PDT 24 |
Finished | Jun 07 08:24:38 PM PDT 24 |
Peak memory | 204992 kb |
Host | smart-6e708c6f-a4ec-4c7b-9f82-e5b1fef73d33 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700583084 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9. rv_dm_jtag_dmi_csr_bit_bash.2700583084 |
Directory | /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.1177089889 |
Short name | T343 |
Test name | |
Test status | |
Simulation time | 8091547113 ps |
CPU time | 6.84 seconds |
Started | Jun 07 08:24:07 PM PDT 24 |
Finished | Jun 07 08:24:16 PM PDT 24 |
Peak memory | 204996 kb |
Host | smart-1a48bc8b-6df0-4b55-963c-0fbdaafe21d5 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177089889 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.1 177089889 |
Directory | /workspace/9.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.3103063440 |
Short name | T315 |
Test name | |
Test status | |
Simulation time | 690405114 ps |
CPU time | 2.37 seconds |
Started | Jun 07 08:24:07 PM PDT 24 |
Finished | Jun 07 08:24:12 PM PDT 24 |
Peak memory | 204632 kb |
Host | smart-f0807537-9be9-45c4-8166-ea3a536ad02a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103063440 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.3 103063440 |
Directory | /workspace/9.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.2995768393 |
Short name | T106 |
Test name | |
Test status | |
Simulation time | 166446460 ps |
CPU time | 3.75 seconds |
Started | Jun 07 08:24:18 PM PDT 24 |
Finished | Jun 07 08:24:24 PM PDT 24 |
Peak memory | 205128 kb |
Host | smart-3bb61741-e027-4188-b269-a3c2f439147d |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995768393 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_ csr_outstanding.2995768393 |
Directory | /workspace/9.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.2031152770 |
Short name | T327 |
Test name | |
Test status | |
Simulation time | 26003017935 ps |
CPU time | 22.15 seconds |
Started | Jun 07 08:24:09 PM PDT 24 |
Finished | Jun 07 08:24:33 PM PDT 24 |
Peak memory | 221376 kb |
Host | smart-13f24557-d44d-4fb6-8420-09cfb7aae0dc |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031152770 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.2031152770 |
Directory | /workspace/9.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.2852082324 |
Short name | T52 |
Test name | |
Test status | |
Simulation time | 319994854 ps |
CPU time | 4.32 seconds |
Started | Jun 07 08:24:20 PM PDT 24 |
Finished | Jun 07 08:24:29 PM PDT 24 |
Peak memory | 213300 kb |
Host | smart-6c3e6998-f08b-4e74-aab9-cd0a8ccd9539 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852082324 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.2852082324 |
Directory | /workspace/9.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2087894594 |
Short name | T131 |
Test name | |
Test status | |
Simulation time | 2172066898 ps |
CPU time | 19.98 seconds |
Started | Jun 07 08:24:19 PM PDT 24 |
Finished | Jun 07 08:24:43 PM PDT 24 |
Peak memory | 213096 kb |
Host | smart-e1ddc914-2ca7-40dc-b273-ce04f1f88902 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087894594 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.2087894594 |
Directory | /workspace/9.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.rv_dm_alert_test.1195256212 |
Short name | T174 |
Test name | |
Test status | |
Simulation time | 143081415 ps |
CPU time | 1.04 seconds |
Started | Jun 07 08:24:27 PM PDT 24 |
Finished | Jun 07 08:24:31 PM PDT 24 |
Peak memory | 204820 kb |
Host | smart-8cf8185e-321d-441b-bc64-b5f2da67e290 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195256212 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.1195256212 |
Directory | /workspace/0.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.3576133147 |
Short name | T230 |
Test name | |
Test status | |
Simulation time | 25741854256 ps |
CPU time | 18.39 seconds |
Started | Jun 07 08:24:27 PM PDT 24 |
Finished | Jun 07 08:24:47 PM PDT 24 |
Peak memory | 218080 kb |
Host | smart-dbf74f35-713c-4a8e-a29d-a5cfa9d26c57 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3576133147 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.3576133147 |
Directory | /workspace/0.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.2374633280 |
Short name | T220 |
Test name | |
Test status | |
Simulation time | 7279722448 ps |
CPU time | 10.91 seconds |
Started | Jun 07 08:24:27 PM PDT 24 |
Finished | Jun 07 08:24:40 PM PDT 24 |
Peak memory | 205184 kb |
Host | smart-02592981-e336-4efd-9600-502768cdef53 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2374633280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.2374633280 |
Directory | /workspace/0.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_busy.3757695203 |
Short name | T240 |
Test name | |
Test status | |
Simulation time | 14455570367 ps |
CPU time | 12.71 seconds |
Started | Jun 07 08:24:21 PM PDT 24 |
Finished | Jun 07 08:24:38 PM PDT 24 |
Peak memory | 205064 kb |
Host | smart-0bbee0ea-2352-4bdc-989f-03c202b647e1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3757695203 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.3757695203 |
Directory | /workspace/0.rv_dm_cmderr_busy/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_not_supported.2836656417 |
Short name | T150 |
Test name | |
Test status | |
Simulation time | 5226826817 ps |
CPU time | 4.93 seconds |
Started | Jun 07 08:24:22 PM PDT 24 |
Finished | Jun 07 08:24:31 PM PDT 24 |
Peak memory | 205004 kb |
Host | smart-0a45c184-bb32-406c-a7fe-c9aec9f7e296 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2836656417 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.2836656417 |
Directory | /workspace/0.rv_dm_cmderr_not_supported/latest |
Test location | /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.1784587789 |
Short name | T245 |
Test name | |
Test status | |
Simulation time | 377993489 ps |
CPU time | 0.77 seconds |
Started | Jun 07 08:24:23 PM PDT 24 |
Finished | Jun 07 08:24:27 PM PDT 24 |
Peak memory | 204712 kb |
Host | smart-03509f9a-ec3f-4dfe-82f5-eb5ee14e7d67 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1784587789 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.1784587789 |
Directory | /workspace/0.rv_dm_dataaddr_rw_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.2847821956 |
Short name | T262 |
Test name | |
Test status | |
Simulation time | 4158247943 ps |
CPU time | 4.03 seconds |
Started | Jun 07 08:24:20 PM PDT 24 |
Finished | Jun 07 08:24:29 PM PDT 24 |
Peak memory | 205268 kb |
Host | smart-496c6cc5-0a70-4e8c-b47b-60ff5c381aa3 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2847821956 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t l_access.2847821956 |
Directory | /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_halt_resume_whereto.926451018 |
Short name | T38 |
Test name | |
Test status | |
Simulation time | 583263679 ps |
CPU time | 1.93 seconds |
Started | Jun 07 08:24:19 PM PDT 24 |
Finished | Jun 07 08:24:25 PM PDT 24 |
Peak memory | 204728 kb |
Host | smart-b1c496b2-b6ad-4a02-94db-6a557619d20c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=926451018 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.926451018 |
Directory | /workspace/0.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/0.rv_dm_hart_unavail.481501587 |
Short name | T234 |
Test name | |
Test status | |
Simulation time | 323054631 ps |
CPU time | 1.55 seconds |
Started | Jun 07 08:24:24 PM PDT 24 |
Finished | Jun 07 08:24:28 PM PDT 24 |
Peak memory | 204592 kb |
Host | smart-7052f8c7-b5ba-43e3-a2f3-2899d5ebcc03 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=481501587 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.481501587 |
Directory | /workspace/0.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.4269866552 |
Short name | T198 |
Test name | |
Test status | |
Simulation time | 1709553559 ps |
CPU time | 1.83 seconds |
Started | Jun 07 08:24:25 PM PDT 24 |
Finished | Jun 07 08:24:30 PM PDT 24 |
Peak memory | 204600 kb |
Host | smart-5e53fdb4-63df-46ee-be5b-0b047e0faf3c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4269866552 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.4269866552 |
Directory | /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.857799266 |
Short name | T256 |
Test name | |
Test status | |
Simulation time | 1404582065 ps |
CPU time | 1.2 seconds |
Started | Jun 07 08:24:29 PM PDT 24 |
Finished | Jun 07 08:24:32 PM PDT 24 |
Peak memory | 204608 kb |
Host | smart-f6b11543-2614-417c-ad95-89cc5d8ca1d3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=857799266 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.857799266 |
Directory | /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.801053541 |
Short name | T257 |
Test name | |
Test status | |
Simulation time | 693115759 ps |
CPU time | 1.27 seconds |
Started | Jun 07 08:24:33 PM PDT 24 |
Finished | Jun 07 08:24:36 PM PDT 24 |
Peak memory | 204616 kb |
Host | smart-2fafb00c-954f-4f59-9db2-136df1a0d031 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=801053541 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.801053541 |
Directory | /workspace/0.rv_dm_jtag_dtm_hard_reset/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.766377542 |
Short name | T199 |
Test name | |
Test status | |
Simulation time | 101788122 ps |
CPU time | 0.97 seconds |
Started | Jun 07 08:24:33 PM PDT 24 |
Finished | Jun 07 08:24:36 PM PDT 24 |
Peak memory | 204596 kb |
Host | smart-89770629-fff2-4adf-b030-d67050c4a3f8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=766377542 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.766377542 |
Directory | /workspace/0.rv_dm_jtag_dtm_idle_hint/latest |
Test location | /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.818669979 |
Short name | T143 |
Test name | |
Test status | |
Simulation time | 1766750684 ps |
CPU time | 1.97 seconds |
Started | Jun 07 08:24:24 PM PDT 24 |
Finished | Jun 07 08:24:29 PM PDT 24 |
Peak memory | 204704 kb |
Host | smart-043f3c9c-5f47-42fd-a5d4-cb68f73671d2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=818669979 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.818669979 |
Directory | /workspace/0.rv_dm_mem_tl_access_halted/latest |
Test location | /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.1511943298 |
Short name | T154 |
Test name | |
Test status | |
Simulation time | 3111414904 ps |
CPU time | 9.66 seconds |
Started | Jun 07 08:24:20 PM PDT 24 |
Finished | Jun 07 08:24:34 PM PDT 24 |
Peak memory | 204792 kb |
Host | smart-28503501-0aae-47eb-9f91-6cd69eee1790 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1511943298 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.1511943298 |
Directory | /workspace/0.rv_dm_mem_tl_access_resuming/latest |
Test location | /workspace/coverage/default/0.rv_dm_ndmreset_req.4160332886 |
Short name | T8 |
Test name | |
Test status | |
Simulation time | 7050505924 ps |
CPU time | 5.33 seconds |
Started | Jun 07 08:24:47 PM PDT 24 |
Finished | Jun 07 08:24:58 PM PDT 24 |
Peak memory | 205048 kb |
Host | smart-256993f3-e346-4e7f-a853-ed4dbb5a3252 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4160332886 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.4160332886 |
Directory | /workspace/0.rv_dm_ndmreset_req/latest |
Test location | /workspace/coverage/default/0.rv_dm_sba_tl_access.1753641381 |
Short name | T232 |
Test name | |
Test status | |
Simulation time | 2467232625 ps |
CPU time | 2.85 seconds |
Started | Jun 07 08:24:21 PM PDT 24 |
Finished | Jun 07 08:24:28 PM PDT 24 |
Peak memory | 205184 kb |
Host | smart-4a820320-1564-45f7-a6f3-8fef4e2badd1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1753641381 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.1753641381 |
Directory | /workspace/0.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_smoke.1980505923 |
Short name | T233 |
Test name | |
Test status | |
Simulation time | 5373543133 ps |
CPU time | 7.11 seconds |
Started | Jun 07 08:24:27 PM PDT 24 |
Finished | Jun 07 08:24:36 PM PDT 24 |
Peak memory | 204596 kb |
Host | smart-7b0fa8ba-58d2-453c-a194-a255772379d6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1980505923 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.1980505923 |
Directory | /workspace/0.rv_dm_smoke/latest |
Test location | /workspace/coverage/default/1.rv_dm_abstractcmd_status.1712663280 |
Short name | T44 |
Test name | |
Test status | |
Simulation time | 355417410 ps |
CPU time | 1.2 seconds |
Started | Jun 07 08:24:30 PM PDT 24 |
Finished | Jun 07 08:24:33 PM PDT 24 |
Peak memory | 204696 kb |
Host | smart-2df24be9-c86b-4a7d-832f-995c5aad3870 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1712663280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.1712663280 |
Directory | /workspace/1.rv_dm_abstractcmd_status/latest |
Test location | /workspace/coverage/default/1.rv_dm_alert_test.2653888679 |
Short name | T166 |
Test name | |
Test status | |
Simulation time | 59866485 ps |
CPU time | 0.79 seconds |
Started | Jun 07 08:24:29 PM PDT 24 |
Finished | Jun 07 08:24:32 PM PDT 24 |
Peak memory | 204804 kb |
Host | smart-980f88b4-863c-4b68-9ad0-367902126b37 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653888679 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.2653888679 |
Directory | /workspace/1.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.3694875973 |
Short name | T205 |
Test name | |
Test status | |
Simulation time | 2472410726 ps |
CPU time | 3.16 seconds |
Started | Jun 07 08:24:31 PM PDT 24 |
Finished | Jun 07 08:24:37 PM PDT 24 |
Peak memory | 205244 kb |
Host | smart-a7397c46-f285-4618-91b5-b553571ab9a7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3694875973 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.3694875973 |
Directory | /workspace/1.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.1237019190 |
Short name | T263 |
Test name | |
Test status | |
Simulation time | 1549828556 ps |
CPU time | 2.3 seconds |
Started | Jun 07 08:24:32 PM PDT 24 |
Finished | Jun 07 08:24:37 PM PDT 24 |
Peak memory | 205092 kb |
Host | smart-ad20aca9-f9f9-4803-bf2e-3f93f3bf251e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1237019190 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.1237019190 |
Directory | /workspace/1.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_busy.2847017070 |
Short name | T259 |
Test name | |
Test status | |
Simulation time | 21180804613 ps |
CPU time | 57.29 seconds |
Started | Jun 07 08:24:26 PM PDT 24 |
Finished | Jun 07 08:25:26 PM PDT 24 |
Peak memory | 205140 kb |
Host | smart-716972c8-b59b-4caa-9d9e-a41d0c28abec |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2847017070 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.2847017070 |
Directory | /workspace/1.rv_dm_cmderr_busy/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_exception.218941345 |
Short name | T41 |
Test name | |
Test status | |
Simulation time | 1054597095 ps |
CPU time | 2.2 seconds |
Started | Jun 07 08:24:29 PM PDT 24 |
Finished | Jun 07 08:24:34 PM PDT 24 |
Peak memory | 204720 kb |
Host | smart-3aac8ac9-53b0-4de1-919d-cf2e31855923 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=218941345 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.218941345 |
Directory | /workspace/1.rv_dm_cmderr_exception/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.516093888 |
Short name | T21 |
Test name | |
Test status | |
Simulation time | 287992453 ps |
CPU time | 1.03 seconds |
Started | Jun 07 08:24:27 PM PDT 24 |
Finished | Jun 07 08:24:31 PM PDT 24 |
Peak memory | 204560 kb |
Host | smart-9b656286-f99d-4b68-8184-513c849ddb96 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=516093888 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.516093888 |
Directory | /workspace/1.rv_dm_cmderr_halt_resume/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_not_supported.1597647364 |
Short name | T148 |
Test name | |
Test status | |
Simulation time | 8253008094 ps |
CPU time | 14.94 seconds |
Started | Jun 07 08:24:34 PM PDT 24 |
Finished | Jun 07 08:24:51 PM PDT 24 |
Peak memory | 205064 kb |
Host | smart-51439ed6-e421-4e55-aefd-8ea0d32398e0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1597647364 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.1597647364 |
Directory | /workspace/1.rv_dm_cmderr_not_supported/latest |
Test location | /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.1285532707 |
Short name | T22 |
Test name | |
Test status | |
Simulation time | 113366407 ps |
CPU time | 1.01 seconds |
Started | Jun 07 08:24:27 PM PDT 24 |
Finished | Jun 07 08:24:31 PM PDT 24 |
Peak memory | 204728 kb |
Host | smart-1ba5fcec-3145-446a-a2c8-d4b5b169ecb2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1285532707 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.1285532707 |
Directory | /workspace/1.rv_dm_dataaddr_rw_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.1558055921 |
Short name | T185 |
Test name | |
Test status | |
Simulation time | 6733131631 ps |
CPU time | 21.3 seconds |
Started | Jun 07 08:24:28 PM PDT 24 |
Finished | Jun 07 08:24:52 PM PDT 24 |
Peak memory | 205200 kb |
Host | smart-6ace0c71-064f-4967-ae68-87a6c3cb6916 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1558055921 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t l_access.1558055921 |
Directory | /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_halt_resume_whereto.1943354548 |
Short name | T6 |
Test name | |
Test status | |
Simulation time | 330835069 ps |
CPU time | 0.96 seconds |
Started | Jun 07 08:24:28 PM PDT 24 |
Finished | Jun 07 08:24:32 PM PDT 24 |
Peak memory | 204716 kb |
Host | smart-67bdb5aa-3e95-4720-9d13-fe1aabb11d8d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1943354548 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.1943354548 |
Directory | /workspace/1.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/1.rv_dm_hart_unavail.1119538851 |
Short name | T208 |
Test name | |
Test status | |
Simulation time | 342009733 ps |
CPU time | 0.89 seconds |
Started | Jun 07 08:24:37 PM PDT 24 |
Finished | Jun 07 08:24:41 PM PDT 24 |
Peak memory | 204624 kb |
Host | smart-764b8466-de44-46b5-b386-8920429fa4c1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1119538851 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.1119538851 |
Directory | /workspace/1.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.1798697703 |
Short name | T7 |
Test name | |
Test status | |
Simulation time | 393374106 ps |
CPU time | 1.23 seconds |
Started | Jun 07 08:24:28 PM PDT 24 |
Finished | Jun 07 08:24:32 PM PDT 24 |
Peak memory | 204608 kb |
Host | smart-1b42e9db-595a-420d-adb6-b9add729a686 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1798697703 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.1798697703 |
Directory | /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.2664015086 |
Short name | T268 |
Test name | |
Test status | |
Simulation time | 1265663417 ps |
CPU time | 3.96 seconds |
Started | Jun 07 08:24:36 PM PDT 24 |
Finished | Jun 07 08:24:42 PM PDT 24 |
Peak memory | 204612 kb |
Host | smart-a284c1d9-3122-4f0c-9441-db6fa6f51275 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2664015086 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.2664015086 |
Directory | /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.1278710124 |
Short name | T227 |
Test name | |
Test status | |
Simulation time | 1490628314 ps |
CPU time | 2.13 seconds |
Started | Jun 07 08:24:25 PM PDT 24 |
Finished | Jun 07 08:24:30 PM PDT 24 |
Peak memory | 204748 kb |
Host | smart-88895a36-3b7f-4e3f-a5fd-ea234f1d1185 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1278710124 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.1278710124 |
Directory | /workspace/1.rv_dm_jtag_dtm_hard_reset/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.1832237761 |
Short name | T265 |
Test name | |
Test status | |
Simulation time | 472772368 ps |
CPU time | 0.94 seconds |
Started | Jun 07 08:24:28 PM PDT 24 |
Finished | Jun 07 08:24:32 PM PDT 24 |
Peak memory | 204604 kb |
Host | smart-af1acd83-cd63-469a-9b7f-ad3ef625ae4f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1832237761 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.1832237761 |
Directory | /workspace/1.rv_dm_jtag_dtm_idle_hint/latest |
Test location | /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.1729411931 |
Short name | T156 |
Test name | |
Test status | |
Simulation time | 1807579849 ps |
CPU time | 1.58 seconds |
Started | Jun 07 08:24:29 PM PDT 24 |
Finished | Jun 07 08:24:33 PM PDT 24 |
Peak memory | 204680 kb |
Host | smart-28b1f3f1-5b70-4e05-8207-ba0290b5c15d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1729411931 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.1729411931 |
Directory | /workspace/1.rv_dm_mem_tl_access_halted/latest |
Test location | /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.2098922116 |
Short name | T157 |
Test name | |
Test status | |
Simulation time | 1637377086 ps |
CPU time | 3.13 seconds |
Started | Jun 07 08:24:36 PM PDT 24 |
Finished | Jun 07 08:24:42 PM PDT 24 |
Peak memory | 204720 kb |
Host | smart-af16b002-9443-44bd-a251-dcd00a60d583 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2098922116 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.2098922116 |
Directory | /workspace/1.rv_dm_mem_tl_access_resuming/latest |
Test location | /workspace/coverage/default/1.rv_dm_ndmreset_req.1512873863 |
Short name | T17 |
Test name | |
Test status | |
Simulation time | 10742077792 ps |
CPU time | 30.3 seconds |
Started | Jun 07 08:24:34 PM PDT 24 |
Finished | Jun 07 08:25:06 PM PDT 24 |
Peak memory | 205072 kb |
Host | smart-dcdc27b3-b259-4e5f-ae17-3dbfba30ed8e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1512873863 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.1512873863 |
Directory | /workspace/1.rv_dm_ndmreset_req/latest |
Test location | /workspace/coverage/default/1.rv_dm_progbuf_busy.1661026907 |
Short name | T5 |
Test name | |
Test status | |
Simulation time | 317329594 ps |
CPU time | 0.89 seconds |
Started | Jun 07 08:24:28 PM PDT 24 |
Finished | Jun 07 08:24:31 PM PDT 24 |
Peak memory | 204728 kb |
Host | smart-b60990c9-ebce-49dd-8ac9-c1899fe74ef5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1661026907 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.1661026907 |
Directory | /workspace/1.rv_dm_progbuf_busy/latest |
Test location | /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.2466499191 |
Short name | T43 |
Test name | |
Test status | |
Simulation time | 925118896 ps |
CPU time | 1.18 seconds |
Started | Jun 07 08:24:47 PM PDT 24 |
Finished | Jun 07 08:24:54 PM PDT 24 |
Peak memory | 204740 kb |
Host | smart-4e251109-3d26-43c5-a9c7-91f1414e569d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2466499191 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.2466499191 |
Directory | /workspace/1.rv_dm_progbuf_read_write_execute/latest |
Test location | /workspace/coverage/default/1.rv_dm_rom_read_access.664670544 |
Short name | T37 |
Test name | |
Test status | |
Simulation time | 119228254 ps |
CPU time | 0.89 seconds |
Started | Jun 07 08:24:28 PM PDT 24 |
Finished | Jun 07 08:24:31 PM PDT 24 |
Peak memory | 212968 kb |
Host | smart-4659121d-0118-4cee-9e0e-f894469717af |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=664670544 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.664670544 |
Directory | /workspace/1.rv_dm_rom_read_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_sec_cm.324221886 |
Short name | T26 |
Test name | |
Test status | |
Simulation time | 1341882591 ps |
CPU time | 1.68 seconds |
Started | Jun 07 08:24:27 PM PDT 24 |
Finished | Jun 07 08:24:32 PM PDT 24 |
Peak memory | 229240 kb |
Host | smart-d09a76e5-360c-49f6-a4d2-71e5ef5e7bc1 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324221886 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.324221886 |
Directory | /workspace/1.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/1.rv_dm_smoke.2167257430 |
Short name | T32 |
Test name | |
Test status | |
Simulation time | 2342933978 ps |
CPU time | 7.26 seconds |
Started | Jun 07 08:24:24 PM PDT 24 |
Finished | Jun 07 08:24:34 PM PDT 24 |
Peak memory | 204896 kb |
Host | smart-8514be22-b261-468a-b088-bdbb98a10f36 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2167257430 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.2167257430 |
Directory | /workspace/1.rv_dm_smoke/latest |
Test location | /workspace/coverage/default/1.rv_dm_stress_all.363800342 |
Short name | T12 |
Test name | |
Test status | |
Simulation time | 17500335549 ps |
CPU time | 14.2 seconds |
Started | Jun 07 08:24:31 PM PDT 24 |
Finished | Jun 07 08:24:47 PM PDT 24 |
Peak memory | 205080 kb |
Host | smart-390298dd-7687-4dba-a202-3a3e3bd3b7c3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363800342 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.363800342 |
Directory | /workspace/1.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.4253854936 |
Short name | T266 |
Test name | |
Test status | |
Simulation time | 55519298294 ps |
CPU time | 52.99 seconds |
Started | Jun 07 08:24:36 PM PDT 24 |
Finished | Jun 07 08:25:31 PM PDT 24 |
Peak memory | 213364 kb |
Host | smart-31f143d4-6df9-44dd-9855-b75509cc9bbb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4253854936 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.4253854936 |
Directory | /workspace/10.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.72355446 |
Short name | T187 |
Test name | |
Test status | |
Simulation time | 3043702328 ps |
CPU time | 4.23 seconds |
Started | Jun 07 08:24:42 PM PDT 24 |
Finished | Jun 07 08:24:49 PM PDT 24 |
Peak memory | 205244 kb |
Host | smart-e517c19c-1e93-4beb-9cbf-51e1167d5747 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=72355446 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.72355446 |
Directory | /workspace/10.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.1628818115 |
Short name | T247 |
Test name | |
Test status | |
Simulation time | 3374511832 ps |
CPU time | 3.93 seconds |
Started | Jun 07 08:24:45 PM PDT 24 |
Finished | Jun 07 08:24:53 PM PDT 24 |
Peak memory | 205168 kb |
Host | smart-5e152fc3-1435-401f-a79f-87b7be31253e |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1628818115 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_ tl_access.1628818115 |
Directory | /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_sba_tl_access.3120216755 |
Short name | T64 |
Test name | |
Test status | |
Simulation time | 2497909215 ps |
CPU time | 2.44 seconds |
Started | Jun 07 08:24:36 PM PDT 24 |
Finished | Jun 07 08:24:41 PM PDT 24 |
Peak memory | 205248 kb |
Host | smart-d02be57f-6b96-48a6-9282-c330e9448cb8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3120216755 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.3120216755 |
Directory | /workspace/10.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_stress_all.3412090994 |
Short name | T151 |
Test name | |
Test status | |
Simulation time | 14138618307 ps |
CPU time | 19.4 seconds |
Started | Jun 07 08:24:42 PM PDT 24 |
Finished | Jun 07 08:25:05 PM PDT 24 |
Peak memory | 215256 kb |
Host | smart-45509d85-4b26-4bb2-804c-6538f2bfb7f2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412090994 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.3412090994 |
Directory | /workspace/10.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/11.rv_dm_alert_test.500167023 |
Short name | T218 |
Test name | |
Test status | |
Simulation time | 57487207 ps |
CPU time | 0.72 seconds |
Started | Jun 07 08:24:37 PM PDT 24 |
Finished | Jun 07 08:24:41 PM PDT 24 |
Peak memory | 204800 kb |
Host | smart-4b02eb59-cdae-458f-870d-716c96cf0355 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500167023 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.500167023 |
Directory | /workspace/11.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.1457549766 |
Short name | T49 |
Test name | |
Test status | |
Simulation time | 29618914104 ps |
CPU time | 48.17 seconds |
Started | Jun 07 08:24:45 PM PDT 24 |
Finished | Jun 07 08:25:37 PM PDT 24 |
Peak memory | 213440 kb |
Host | smart-af4759c7-4d77-43c6-b2e1-6c3345e885ca |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1457549766 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.1457549766 |
Directory | /workspace/11.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.2507294414 |
Short name | T70 |
Test name | |
Test status | |
Simulation time | 2546942904 ps |
CPU time | 7.67 seconds |
Started | Jun 07 08:24:37 PM PDT 24 |
Finished | Jun 07 08:24:48 PM PDT 24 |
Peak memory | 205208 kb |
Host | smart-c503122a-12cd-4f1f-b2d8-575be8da8882 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2507294414 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.2507294414 |
Directory | /workspace/11.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.27896006 |
Short name | T235 |
Test name | |
Test status | |
Simulation time | 8255273440 ps |
CPU time | 4.93 seconds |
Started | Jun 07 08:24:40 PM PDT 24 |
Finished | Jun 07 08:24:46 PM PDT 24 |
Peak memory | 205388 kb |
Host | smart-fca1658e-3517-4529-b720-2398980e3cde |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=27896006 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_tl _access.27896006 |
Directory | /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_sba_tl_access.2044773639 |
Short name | T188 |
Test name | |
Test status | |
Simulation time | 7137845939 ps |
CPU time | 21.1 seconds |
Started | Jun 07 08:24:41 PM PDT 24 |
Finished | Jun 07 08:25:04 PM PDT 24 |
Peak memory | 205324 kb |
Host | smart-97dd4bd4-044f-4525-a853-b202d53d5207 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2044773639 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.2044773639 |
Directory | /workspace/11.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_stress_all.3618830887 |
Short name | T142 |
Test name | |
Test status | |
Simulation time | 10603438668 ps |
CPU time | 32.85 seconds |
Started | Jun 07 08:24:41 PM PDT 24 |
Finished | Jun 07 08:25:17 PM PDT 24 |
Peak memory | 205104 kb |
Host | smart-5fe3e707-f618-457e-ae25-d9917f7eae49 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618830887 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.3618830887 |
Directory | /workspace/11.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/12.rv_dm_alert_test.4063610413 |
Short name | T3 |
Test name | |
Test status | |
Simulation time | 97517484 ps |
CPU time | 0.76 seconds |
Started | Jun 07 08:24:49 PM PDT 24 |
Finished | Jun 07 08:24:56 PM PDT 24 |
Peak memory | 204832 kb |
Host | smart-d5c42ece-a4a2-421d-bd37-4fa6bf94e82c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063610413 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.4063610413 |
Directory | /workspace/12.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.3938536379 |
Short name | T264 |
Test name | |
Test status | |
Simulation time | 13178679790 ps |
CPU time | 11.71 seconds |
Started | Jun 07 08:24:49 PM PDT 24 |
Finished | Jun 07 08:25:07 PM PDT 24 |
Peak memory | 213204 kb |
Host | smart-7ea05760-f72b-48eb-9d37-ab1dba5d6cec |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3938536379 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.3938536379 |
Directory | /workspace/12.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.711911498 |
Short name | T237 |
Test name | |
Test status | |
Simulation time | 13102991728 ps |
CPU time | 33.81 seconds |
Started | Jun 07 08:24:46 PM PDT 24 |
Finished | Jun 07 08:25:25 PM PDT 24 |
Peak memory | 213488 kb |
Host | smart-380206c6-8dbd-428d-aa93-f92a114fb474 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=711911498 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.711911498 |
Directory | /workspace/12.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.3886013759 |
Short name | T231 |
Test name | |
Test status | |
Simulation time | 3860290591 ps |
CPU time | 8.62 seconds |
Started | Jun 07 08:24:47 PM PDT 24 |
Finished | Jun 07 08:25:02 PM PDT 24 |
Peak memory | 205208 kb |
Host | smart-833a978a-416b-4cbb-a503-3875e05e0102 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3886013759 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_ tl_access.3886013759 |
Directory | /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_sba_tl_access.3979698385 |
Short name | T253 |
Test name | |
Test status | |
Simulation time | 3063257013 ps |
CPU time | 1.58 seconds |
Started | Jun 07 08:24:48 PM PDT 24 |
Finished | Jun 07 08:24:55 PM PDT 24 |
Peak memory | 205212 kb |
Host | smart-e5beec97-89e8-4359-90db-1341b3d2ca8a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3979698385 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.3979698385 |
Directory | /workspace/12.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_stress_all.464460549 |
Short name | T144 |
Test name | |
Test status | |
Simulation time | 32985784277 ps |
CPU time | 55.36 seconds |
Started | Jun 07 08:24:46 PM PDT 24 |
Finished | Jun 07 08:25:46 PM PDT 24 |
Peak memory | 213220 kb |
Host | smart-7ab0804a-5cb1-4bb2-977c-61b14801bb0a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464460549 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.464460549 |
Directory | /workspace/12.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/13.rv_dm_alert_test.2770410350 |
Short name | T178 |
Test name | |
Test status | |
Simulation time | 66866098 ps |
CPU time | 0.88 seconds |
Started | Jun 07 08:24:50 PM PDT 24 |
Finished | Jun 07 08:24:57 PM PDT 24 |
Peak memory | 204916 kb |
Host | smart-8f5ea20f-a4a3-41c9-9b26-fc70ff7b38a1 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770410350 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.2770410350 |
Directory | /workspace/13.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.851139557 |
Short name | T225 |
Test name | |
Test status | |
Simulation time | 2501136306 ps |
CPU time | 4.08 seconds |
Started | Jun 07 08:24:46 PM PDT 24 |
Finished | Jun 07 08:24:55 PM PDT 24 |
Peak memory | 205220 kb |
Host | smart-c23d7314-a2c0-45ad-8247-9e379618a4c9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=851139557 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.851139557 |
Directory | /workspace/13.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.1460890719 |
Short name | T241 |
Test name | |
Test status | |
Simulation time | 2117321792 ps |
CPU time | 6.89 seconds |
Started | Jun 07 08:24:44 PM PDT 24 |
Finished | Jun 07 08:24:54 PM PDT 24 |
Peak memory | 205064 kb |
Host | smart-fa9c496f-10e2-49b2-94e1-56a036d3959c |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1460890719 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_ tl_access.1460890719 |
Directory | /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_sba_tl_access.2415400467 |
Short name | T192 |
Test name | |
Test status | |
Simulation time | 3437546686 ps |
CPU time | 3.66 seconds |
Started | Jun 07 08:24:47 PM PDT 24 |
Finished | Jun 07 08:24:57 PM PDT 24 |
Peak memory | 205272 kb |
Host | smart-f341e92a-bc1e-4b24-8954-2ca1ea715c40 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2415400467 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.2415400467 |
Directory | /workspace/13.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/14.rv_dm_alert_test.2649393815 |
Short name | T204 |
Test name | |
Test status | |
Simulation time | 46668447 ps |
CPU time | 0.78 seconds |
Started | Jun 07 08:24:46 PM PDT 24 |
Finished | Jun 07 08:24:51 PM PDT 24 |
Peak memory | 204820 kb |
Host | smart-9c076282-767b-4183-a339-fbaf26cfee9b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649393815 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.2649393815 |
Directory | /workspace/14.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.4224857647 |
Short name | T1 |
Test name | |
Test status | |
Simulation time | 18061201785 ps |
CPU time | 26.53 seconds |
Started | Jun 07 08:24:46 PM PDT 24 |
Finished | Jun 07 08:25:17 PM PDT 24 |
Peak memory | 213420 kb |
Host | smart-cdbd1459-3740-4a07-910a-ad6a0efda6b4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4224857647 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.4224857647 |
Directory | /workspace/14.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.1141317474 |
Short name | T269 |
Test name | |
Test status | |
Simulation time | 3859676769 ps |
CPU time | 4.02 seconds |
Started | Jun 07 08:24:47 PM PDT 24 |
Finished | Jun 07 08:24:57 PM PDT 24 |
Peak memory | 205236 kb |
Host | smart-1141b5ab-33f9-4c1b-ad5c-092908c9d0fe |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1141317474 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_ tl_access.1141317474 |
Directory | /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/14.rv_dm_sba_tl_access.2464302983 |
Short name | T214 |
Test name | |
Test status | |
Simulation time | 1895098819 ps |
CPU time | 4.26 seconds |
Started | Jun 07 08:24:46 PM PDT 24 |
Finished | Jun 07 08:24:55 PM PDT 24 |
Peak memory | 205080 kb |
Host | smart-5e6999ea-efe7-4907-9498-6a70e0ba7b15 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2464302983 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.2464302983 |
Directory | /workspace/14.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/14.rv_dm_stress_all.2458067166 |
Short name | T34 |
Test name | |
Test status | |
Simulation time | 11179317411 ps |
CPU time | 34.62 seconds |
Started | Jun 07 08:24:49 PM PDT 24 |
Finished | Jun 07 08:25:30 PM PDT 24 |
Peak memory | 205040 kb |
Host | smart-1f850e60-1f36-4961-9ff8-eac264681def |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458067166 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.2458067166 |
Directory | /workspace/14.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/15.rv_dm_alert_test.1236206043 |
Short name | T177 |
Test name | |
Test status | |
Simulation time | 90289422 ps |
CPU time | 0.75 seconds |
Started | Jun 07 08:24:46 PM PDT 24 |
Finished | Jun 07 08:24:52 PM PDT 24 |
Peak memory | 204808 kb |
Host | smart-318130c8-65f9-4759-bf54-9c0a9db455c9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236206043 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.1236206043 |
Directory | /workspace/15.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.2418521781 |
Short name | T19 |
Test name | |
Test status | |
Simulation time | 23283823717 ps |
CPU time | 29.91 seconds |
Started | Jun 07 08:24:48 PM PDT 24 |
Finished | Jun 07 08:25:24 PM PDT 24 |
Peak memory | 213420 kb |
Host | smart-cb3c24d9-4061-4f6b-826d-fe4d46d32d43 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2418521781 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.2418521781 |
Directory | /workspace/15.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.731356541 |
Short name | T203 |
Test name | |
Test status | |
Simulation time | 1436831700 ps |
CPU time | 3.45 seconds |
Started | Jun 07 08:24:50 PM PDT 24 |
Finished | Jun 07 08:24:59 PM PDT 24 |
Peak memory | 205076 kb |
Host | smart-cbed3b57-11b0-44a2-9cbd-ef56fab50341 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=731356541 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.731356541 |
Directory | /workspace/15.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.185458705 |
Short name | T9 |
Test name | |
Test status | |
Simulation time | 1120502602 ps |
CPU time | 4.18 seconds |
Started | Jun 07 08:24:47 PM PDT 24 |
Finished | Jun 07 08:24:57 PM PDT 24 |
Peak memory | 205140 kb |
Host | smart-81904c1d-e651-44c8-8c47-3d7bb4c7b4f4 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=185458705 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_t l_access.185458705 |
Directory | /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_stress_all.862788397 |
Short name | T145 |
Test name | |
Test status | |
Simulation time | 7608750322 ps |
CPU time | 12.52 seconds |
Started | Jun 07 08:24:46 PM PDT 24 |
Finished | Jun 07 08:25:04 PM PDT 24 |
Peak memory | 205096 kb |
Host | smart-ffa3ecf0-0cd6-4265-81f8-8fff5a72d50d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862788397 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.862788397 |
Directory | /workspace/15.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/16.rv_dm_alert_test.2990112628 |
Short name | T58 |
Test name | |
Test status | |
Simulation time | 71769841 ps |
CPU time | 0.76 seconds |
Started | Jun 07 08:24:55 PM PDT 24 |
Finished | Jun 07 08:25:00 PM PDT 24 |
Peak memory | 204752 kb |
Host | smart-d5c9c365-17c4-49e6-972c-de0e283297ac |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990112628 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.2990112628 |
Directory | /workspace/16.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.408262523 |
Short name | T254 |
Test name | |
Test status | |
Simulation time | 20449608564 ps |
CPU time | 19.1 seconds |
Started | Jun 07 08:24:52 PM PDT 24 |
Finished | Jun 07 08:25:17 PM PDT 24 |
Peak memory | 205212 kb |
Host | smart-cd333a8c-2837-4cf8-9e58-1fe049ed0d2a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=408262523 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.408262523 |
Directory | /workspace/16.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.3444339162 |
Short name | T184 |
Test name | |
Test status | |
Simulation time | 1426418146 ps |
CPU time | 2.9 seconds |
Started | Jun 07 08:24:49 PM PDT 24 |
Finished | Jun 07 08:24:58 PM PDT 24 |
Peak memory | 204904 kb |
Host | smart-3a479e30-042f-40ad-8b68-ec10fb124fa8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3444339162 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.3444339162 |
Directory | /workspace/16.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.571638417 |
Short name | T67 |
Test name | |
Test status | |
Simulation time | 8537140047 ps |
CPU time | 14.54 seconds |
Started | Jun 07 08:24:46 PM PDT 24 |
Finished | Jun 07 08:25:05 PM PDT 24 |
Peak memory | 205196 kb |
Host | smart-9be1d276-969a-460d-82a7-9eb4af7e22dd |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=571638417 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_t l_access.571638417 |
Directory | /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_sba_tl_access.4196328740 |
Short name | T201 |
Test name | |
Test status | |
Simulation time | 4867446233 ps |
CPU time | 2.98 seconds |
Started | Jun 07 08:24:48 PM PDT 24 |
Finished | Jun 07 08:24:57 PM PDT 24 |
Peak memory | 205288 kb |
Host | smart-01821320-8c63-421f-b88f-ed74df845f6d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4196328740 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.4196328740 |
Directory | /workspace/16.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_alert_test.2062419029 |
Short name | T23 |
Test name | |
Test status | |
Simulation time | 31950151 ps |
CPU time | 0.73 seconds |
Started | Jun 07 08:24:56 PM PDT 24 |
Finished | Jun 07 08:25:01 PM PDT 24 |
Peak memory | 204824 kb |
Host | smart-a17593a0-fc28-41c5-b2e6-42af435404c0 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062419029 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.2062419029 |
Directory | /workspace/17.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.310562908 |
Short name | T236 |
Test name | |
Test status | |
Simulation time | 31024093762 ps |
CPU time | 26.03 seconds |
Started | Jun 07 08:24:49 PM PDT 24 |
Finished | Jun 07 08:25:21 PM PDT 24 |
Peak memory | 213472 kb |
Host | smart-e99dd335-5780-4709-a783-ed36351c69bb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=310562908 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.310562908 |
Directory | /workspace/17.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.3101352410 |
Short name | T183 |
Test name | |
Test status | |
Simulation time | 1418506624 ps |
CPU time | 5.09 seconds |
Started | Jun 07 08:24:51 PM PDT 24 |
Finished | Jun 07 08:25:02 PM PDT 24 |
Peak memory | 213324 kb |
Host | smart-d522f64a-daa5-4d90-8920-e5e25708ce1f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3101352410 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.3101352410 |
Directory | /workspace/17.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.3071693999 |
Short name | T57 |
Test name | |
Test status | |
Simulation time | 5781197255 ps |
CPU time | 9.67 seconds |
Started | Jun 07 08:24:48 PM PDT 24 |
Finished | Jun 07 08:25:04 PM PDT 24 |
Peak memory | 205260 kb |
Host | smart-f496ba82-3a74-461c-ab0f-7c7c66ee843a |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3071693999 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_ tl_access.3071693999 |
Directory | /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_sba_tl_access.3060235944 |
Short name | T65 |
Test name | |
Test status | |
Simulation time | 4162314039 ps |
CPU time | 7 seconds |
Started | Jun 07 08:24:47 PM PDT 24 |
Finished | Jun 07 08:25:00 PM PDT 24 |
Peak memory | 205248 kb |
Host | smart-8ce3a28e-2b79-4f5e-9ac4-d016e6a802ed |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3060235944 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.3060235944 |
Directory | /workspace/17.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_alert_test.3558941485 |
Short name | T170 |
Test name | |
Test status | |
Simulation time | 125317738 ps |
CPU time | 0.78 seconds |
Started | Jun 07 08:25:00 PM PDT 24 |
Finished | Jun 07 08:25:06 PM PDT 24 |
Peak memory | 204832 kb |
Host | smart-8a5185c5-b5cd-46c4-89f0-3f55c240462a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558941485 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.3558941485 |
Directory | /workspace/18.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.2863974018 |
Short name | T216 |
Test name | |
Test status | |
Simulation time | 6883736148 ps |
CPU time | 5.53 seconds |
Started | Jun 07 08:24:50 PM PDT 24 |
Finished | Jun 07 08:25:02 PM PDT 24 |
Peak memory | 213468 kb |
Host | smart-2b160178-b483-44d8-9f7c-5d116d49397d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2863974018 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.2863974018 |
Directory | /workspace/18.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.2774094307 |
Short name | T66 |
Test name | |
Test status | |
Simulation time | 5730061747 ps |
CPU time | 10.24 seconds |
Started | Jun 07 08:24:50 PM PDT 24 |
Finished | Jun 07 08:25:06 PM PDT 24 |
Peak memory | 205256 kb |
Host | smart-95e766e3-6e6e-457f-a3b8-f695e281f1fa |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2774094307 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.2774094307 |
Directory | /workspace/18.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.188005514 |
Short name | T221 |
Test name | |
Test status | |
Simulation time | 8766878705 ps |
CPU time | 7.35 seconds |
Started | Jun 07 08:24:50 PM PDT 24 |
Finished | Jun 07 08:25:04 PM PDT 24 |
Peak memory | 205184 kb |
Host | smart-5ddacc9c-867e-46e8-9d85-8dbefa31572e |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=188005514 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_t l_access.188005514 |
Directory | /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_sba_tl_access.2806526627 |
Short name | T13 |
Test name | |
Test status | |
Simulation time | 1410906954 ps |
CPU time | 3.64 seconds |
Started | Jun 07 08:25:00 PM PDT 24 |
Finished | Jun 07 08:25:09 PM PDT 24 |
Peak memory | 205100 kb |
Host | smart-6af27597-8685-4bb1-8003-add76e4629aa |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2806526627 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.2806526627 |
Directory | /workspace/18.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.278462907 |
Short name | T62 |
Test name | |
Test status | |
Simulation time | 29631397416 ps |
CPU time | 74.93 seconds |
Started | Jun 07 08:24:55 PM PDT 24 |
Finished | Jun 07 08:26:14 PM PDT 24 |
Peak memory | 205300 kb |
Host | smart-167b608e-5864-419f-8096-214d4d7aafaf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=278462907 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.278462907 |
Directory | /workspace/19.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.384593050 |
Short name | T69 |
Test name | |
Test status | |
Simulation time | 4963220867 ps |
CPU time | 7.62 seconds |
Started | Jun 07 08:24:50 PM PDT 24 |
Finished | Jun 07 08:25:04 PM PDT 24 |
Peak memory | 205216 kb |
Host | smart-df373486-19b2-4854-9971-4191a45d5a36 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=384593050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.384593050 |
Directory | /workspace/19.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.2601884955 |
Short name | T260 |
Test name | |
Test status | |
Simulation time | 5496219213 ps |
CPU time | 4.49 seconds |
Started | Jun 07 08:24:50 PM PDT 24 |
Finished | Jun 07 08:25:01 PM PDT 24 |
Peak memory | 205240 kb |
Host | smart-c00a480a-3043-4d94-9e79-b41348a0eaeb |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2601884955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_ tl_access.2601884955 |
Directory | /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_sba_tl_access.249492323 |
Short name | T242 |
Test name | |
Test status | |
Simulation time | 10712536932 ps |
CPU time | 27.51 seconds |
Started | Jun 07 08:24:51 PM PDT 24 |
Finished | Jun 07 08:25:25 PM PDT 24 |
Peak memory | 205264 kb |
Host | smart-354876c5-4f1f-4604-b722-860c685a2dbb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=249492323 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.249492323 |
Directory | /workspace/19.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_alert_test.2989511641 |
Short name | T182 |
Test name | |
Test status | |
Simulation time | 74594197 ps |
CPU time | 0.84 seconds |
Started | Jun 07 08:24:43 PM PDT 24 |
Finished | Jun 07 08:24:47 PM PDT 24 |
Peak memory | 204852 kb |
Host | smart-eb2d55ce-dd60-4652-973f-290b5cf81983 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989511641 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.2989511641 |
Directory | /workspace/2.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.1405893888 |
Short name | T206 |
Test name | |
Test status | |
Simulation time | 1960905033 ps |
CPU time | 2.22 seconds |
Started | Jun 07 08:24:27 PM PDT 24 |
Finished | Jun 07 08:24:32 PM PDT 24 |
Peak memory | 205084 kb |
Host | smart-99d41e5f-01cf-4ce4-a886-b71647d8cb56 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1405893888 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.1405893888 |
Directory | /workspace/2.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.1172016058 |
Short name | T229 |
Test name | |
Test status | |
Simulation time | 2615747174 ps |
CPU time | 3.08 seconds |
Started | Jun 07 08:24:28 PM PDT 24 |
Finished | Jun 07 08:24:34 PM PDT 24 |
Peak memory | 205216 kb |
Host | smart-69666386-f95b-4831-966f-ffc872e428e1 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1172016058 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t l_access.1172016058 |
Directory | /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_hart_unavail.877113821 |
Short name | T243 |
Test name | |
Test status | |
Simulation time | 503157382 ps |
CPU time | 1.99 seconds |
Started | Jun 07 08:24:30 PM PDT 24 |
Finished | Jun 07 08:24:35 PM PDT 24 |
Peak memory | 204636 kb |
Host | smart-4756321e-03bc-47fe-80de-f3875dfa9079 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=877113821 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.877113821 |
Directory | /workspace/2.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/2.rv_dm_sec_cm.743014530 |
Short name | T27 |
Test name | |
Test status | |
Simulation time | 324584024 ps |
CPU time | 1.21 seconds |
Started | Jun 07 08:24:40 PM PDT 24 |
Finished | Jun 07 08:24:43 PM PDT 24 |
Peak memory | 229664 kb |
Host | smart-1f616372-e550-47c6-be77-bf041a3baefb |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743014530 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.743014530 |
Directory | /workspace/2.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/20.rv_dm_alert_test.1185439927 |
Short name | T248 |
Test name | |
Test status | |
Simulation time | 96592232 ps |
CPU time | 0.72 seconds |
Started | Jun 07 08:24:47 PM PDT 24 |
Finished | Jun 07 08:24:54 PM PDT 24 |
Peak memory | 204808 kb |
Host | smart-0f45bbb8-9d59-4d66-be08-265d627103b3 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185439927 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.1185439927 |
Directory | /workspace/20.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/21.rv_dm_alert_test.1374831432 |
Short name | T211 |
Test name | |
Test status | |
Simulation time | 75735519 ps |
CPU time | 0.73 seconds |
Started | Jun 07 08:24:51 PM PDT 24 |
Finished | Jun 07 08:24:58 PM PDT 24 |
Peak memory | 204816 kb |
Host | smart-a429bb33-673c-4d5a-a28b-926fd4472659 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374831432 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.1374831432 |
Directory | /workspace/21.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/21.rv_dm_stress_all.398758932 |
Short name | T33 |
Test name | |
Test status | |
Simulation time | 9293062392 ps |
CPU time | 2.68 seconds |
Started | Jun 07 08:24:59 PM PDT 24 |
Finished | Jun 07 08:25:05 PM PDT 24 |
Peak memory | 205100 kb |
Host | smart-f9d87087-0eb4-436c-a70c-0a588bb49cda |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398758932 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.398758932 |
Directory | /workspace/21.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/22.rv_dm_alert_test.805779974 |
Short name | T164 |
Test name | |
Test status | |
Simulation time | 39124412 ps |
CPU time | 0.78 seconds |
Started | Jun 07 08:25:00 PM PDT 24 |
Finished | Jun 07 08:25:06 PM PDT 24 |
Peak memory | 204808 kb |
Host | smart-ed2bf2b1-9e97-4f3c-aed0-8c4771888b60 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805779974 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.805779974 |
Directory | /workspace/22.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/22.rv_dm_stress_all.1490074362 |
Short name | T147 |
Test name | |
Test status | |
Simulation time | 12350920760 ps |
CPU time | 39.6 seconds |
Started | Jun 07 08:24:51 PM PDT 24 |
Finished | Jun 07 08:25:37 PM PDT 24 |
Peak memory | 213236 kb |
Host | smart-cddc6e74-797f-4948-8cf6-6046de795029 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490074362 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.1490074362 |
Directory | /workspace/22.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/23.rv_dm_alert_test.3077050269 |
Short name | T125 |
Test name | |
Test status | |
Simulation time | 65791979 ps |
CPU time | 0.73 seconds |
Started | Jun 07 08:24:55 PM PDT 24 |
Finished | Jun 07 08:25:00 PM PDT 24 |
Peak memory | 204788 kb |
Host | smart-ca22f8b6-5662-40c3-92d9-ee3a39c9b038 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077050269 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.3077050269 |
Directory | /workspace/23.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/24.rv_dm_alert_test.2422967357 |
Short name | T210 |
Test name | |
Test status | |
Simulation time | 101805532 ps |
CPU time | 0.71 seconds |
Started | Jun 07 08:24:51 PM PDT 24 |
Finished | Jun 07 08:24:58 PM PDT 24 |
Peak memory | 204832 kb |
Host | smart-18e07d6f-5d21-4f6b-96b9-ba8b0c6c0cc8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422967357 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.2422967357 |
Directory | /workspace/24.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/25.rv_dm_alert_test.3230093720 |
Short name | T179 |
Test name | |
Test status | |
Simulation time | 72682704 ps |
CPU time | 0.89 seconds |
Started | Jun 07 08:24:49 PM PDT 24 |
Finished | Jun 07 08:24:56 PM PDT 24 |
Peak memory | 204820 kb |
Host | smart-dc1b2359-5e13-4e93-a1fe-b646cb02347b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230093720 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.3230093720 |
Directory | /workspace/25.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/25.rv_dm_stress_all.874388626 |
Short name | T155 |
Test name | |
Test status | |
Simulation time | 28459668511 ps |
CPU time | 10.98 seconds |
Started | Jun 07 08:24:51 PM PDT 24 |
Finished | Jun 07 08:25:08 PM PDT 24 |
Peak memory | 213256 kb |
Host | smart-58d0776c-d8e1-4857-b490-95870c7eb18b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874388626 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.874388626 |
Directory | /workspace/25.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/26.rv_dm_alert_test.2140790516 |
Short name | T172 |
Test name | |
Test status | |
Simulation time | 46773899 ps |
CPU time | 0.83 seconds |
Started | Jun 07 08:24:58 PM PDT 24 |
Finished | Jun 07 08:25:03 PM PDT 24 |
Peak memory | 204852 kb |
Host | smart-76a374e5-02d1-4d71-8e70-1b52c908e2f8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140790516 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.2140790516 |
Directory | /workspace/26.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/27.rv_dm_alert_test.2714489728 |
Short name | T171 |
Test name | |
Test status | |
Simulation time | 72510345 ps |
CPU time | 0.75 seconds |
Started | Jun 07 08:24:50 PM PDT 24 |
Finished | Jun 07 08:24:57 PM PDT 24 |
Peak memory | 204816 kb |
Host | smart-d25b815e-6bad-4d04-aaa8-dbd8be72b1f0 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714489728 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.2714489728 |
Directory | /workspace/27.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/27.rv_dm_stress_all.414321927 |
Short name | T149 |
Test name | |
Test status | |
Simulation time | 37855600227 ps |
CPU time | 17.28 seconds |
Started | Jun 07 08:25:00 PM PDT 24 |
Finished | Jun 07 08:25:23 PM PDT 24 |
Peak memory | 213268 kb |
Host | smart-83fa7b4d-e6b9-46e6-9825-0e3e180f2c91 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414321927 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.414321927 |
Directory | /workspace/27.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/28.rv_dm_alert_test.2252113226 |
Short name | T163 |
Test name | |
Test status | |
Simulation time | 72555247 ps |
CPU time | 0.79 seconds |
Started | Jun 07 08:25:01 PM PDT 24 |
Finished | Jun 07 08:25:06 PM PDT 24 |
Peak memory | 204808 kb |
Host | smart-10b21b35-4987-486d-aa0e-6a65f41aa0fa |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252113226 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.2252113226 |
Directory | /workspace/28.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/29.rv_dm_alert_test.2085319440 |
Short name | T219 |
Test name | |
Test status | |
Simulation time | 45301784 ps |
CPU time | 0.73 seconds |
Started | Jun 07 08:24:59 PM PDT 24 |
Finished | Jun 07 08:25:03 PM PDT 24 |
Peak memory | 204780 kb |
Host | smart-f02e5a17-bef0-4b45-b7c7-a3eaa204c31f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085319440 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.2085319440 |
Directory | /workspace/29.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/3.rv_dm_alert_test.2356376541 |
Short name | T239 |
Test name | |
Test status | |
Simulation time | 45500389 ps |
CPU time | 0.73 seconds |
Started | Jun 07 08:24:39 PM PDT 24 |
Finished | Jun 07 08:24:42 PM PDT 24 |
Peak memory | 204852 kb |
Host | smart-c6d39897-577e-47db-90f8-9baa73ccd2c1 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356376541 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.2356376541 |
Directory | /workspace/3.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.2437419083 |
Short name | T267 |
Test name | |
Test status | |
Simulation time | 11511289810 ps |
CPU time | 14.79 seconds |
Started | Jun 07 08:24:31 PM PDT 24 |
Finished | Jun 07 08:24:48 PM PDT 24 |
Peak memory | 213424 kb |
Host | smart-27b3289b-1905-4fc1-a2fd-d6426b49534a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2437419083 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.2437419083 |
Directory | /workspace/3.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.1653488106 |
Short name | T59 |
Test name | |
Test status | |
Simulation time | 3205055779 ps |
CPU time | 9.93 seconds |
Started | Jun 07 08:24:38 PM PDT 24 |
Finished | Jun 07 08:24:50 PM PDT 24 |
Peak memory | 205212 kb |
Host | smart-13fc6040-ed39-4624-b98e-ba80df3a7e7b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1653488106 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.1653488106 |
Directory | /workspace/3.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.3387546223 |
Short name | T202 |
Test name | |
Test status | |
Simulation time | 1569822962 ps |
CPU time | 2.14 seconds |
Started | Jun 07 08:24:28 PM PDT 24 |
Finished | Jun 07 08:24:32 PM PDT 24 |
Peak memory | 205136 kb |
Host | smart-6dc11e0c-2b37-4c86-b483-09eb0c82b71d |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3387546223 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t l_access.3387546223 |
Directory | /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_hart_unavail.736177364 |
Short name | T195 |
Test name | |
Test status | |
Simulation time | 270718704 ps |
CPU time | 1.47 seconds |
Started | Jun 07 08:24:39 PM PDT 24 |
Finished | Jun 07 08:24:42 PM PDT 24 |
Peak memory | 204672 kb |
Host | smart-e454a4af-739b-4b5a-846e-50b996e664c9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=736177364 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.736177364 |
Directory | /workspace/3.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/3.rv_dm_sba_tl_access.3995050011 |
Short name | T191 |
Test name | |
Test status | |
Simulation time | 7608308145 ps |
CPU time | 6.73 seconds |
Started | Jun 07 08:24:35 PM PDT 24 |
Finished | Jun 07 08:24:44 PM PDT 24 |
Peak memory | 205232 kb |
Host | smart-62d2d7e0-2c7e-483a-bd73-39b5e3f3fc0e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3995050011 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.3995050011 |
Directory | /workspace/3.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_sec_cm.41025620 |
Short name | T60 |
Test name | |
Test status | |
Simulation time | 1385284423 ps |
CPU time | 1.96 seconds |
Started | Jun 07 08:24:39 PM PDT 24 |
Finished | Jun 07 08:24:43 PM PDT 24 |
Peak memory | 228312 kb |
Host | smart-5ee6e695-2b7e-4ebb-9d0e-77eafc7935eb |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41025620 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.41025620 |
Directory | /workspace/3.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/3.rv_dm_stress_all.3054311487 |
Short name | T152 |
Test name | |
Test status | |
Simulation time | 13796823614 ps |
CPU time | 11.67 seconds |
Started | Jun 07 08:24:38 PM PDT 24 |
Finished | Jun 07 08:24:52 PM PDT 24 |
Peak memory | 205120 kb |
Host | smart-154215c4-2f02-49a2-aec6-72c2a9a1ae2a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054311487 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.3054311487 |
Directory | /workspace/3.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/30.rv_dm_alert_test.105835160 |
Short name | T169 |
Test name | |
Test status | |
Simulation time | 123848285 ps |
CPU time | 0.73 seconds |
Started | Jun 07 08:25:02 PM PDT 24 |
Finished | Jun 07 08:25:08 PM PDT 24 |
Peak memory | 204848 kb |
Host | smart-070304f5-94d5-43bb-b833-6ae895bae6c8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105835160 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.105835160 |
Directory | /workspace/30.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/31.rv_dm_alert_test.479857388 |
Short name | T176 |
Test name | |
Test status | |
Simulation time | 59534202 ps |
CPU time | 0.83 seconds |
Started | Jun 07 08:25:01 PM PDT 24 |
Finished | Jun 07 08:25:06 PM PDT 24 |
Peak memory | 204804 kb |
Host | smart-6b3faee9-6b5d-4d6f-8dd6-0dd2ac620bd7 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479857388 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.479857388 |
Directory | /workspace/31.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/32.rv_dm_alert_test.1423783357 |
Short name | T165 |
Test name | |
Test status | |
Simulation time | 107542968 ps |
CPU time | 0.76 seconds |
Started | Jun 07 08:25:01 PM PDT 24 |
Finished | Jun 07 08:25:06 PM PDT 24 |
Peak memory | 204840 kb |
Host | smart-cbdb497c-d387-43d3-aa4d-dc8dde04ed13 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423783357 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.1423783357 |
Directory | /workspace/32.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/33.rv_dm_alert_test.1854805074 |
Short name | T190 |
Test name | |
Test status | |
Simulation time | 108450252 ps |
CPU time | 0.75 seconds |
Started | Jun 07 08:24:58 PM PDT 24 |
Finished | Jun 07 08:25:02 PM PDT 24 |
Peak memory | 204796 kb |
Host | smart-4448a971-f23f-4fb5-8e64-49c51ca6fc98 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854805074 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.1854805074 |
Directory | /workspace/33.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/34.rv_dm_alert_test.884221928 |
Short name | T173 |
Test name | |
Test status | |
Simulation time | 211767697 ps |
CPU time | 0.79 seconds |
Started | Jun 07 08:25:01 PM PDT 24 |
Finished | Jun 07 08:25:06 PM PDT 24 |
Peak memory | 204748 kb |
Host | smart-a9a18b2d-531d-425c-ae29-ccfffd3c6924 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884221928 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.884221928 |
Directory | /workspace/34.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/35.rv_dm_alert_test.1040089375 |
Short name | T121 |
Test name | |
Test status | |
Simulation time | 28652011 ps |
CPU time | 0.74 seconds |
Started | Jun 07 08:25:00 PM PDT 24 |
Finished | Jun 07 08:25:05 PM PDT 24 |
Peak memory | 204736 kb |
Host | smart-1fcbd8a2-f73c-4356-9ba7-0470c55a45ac |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040089375 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.1040089375 |
Directory | /workspace/35.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/36.rv_dm_alert_test.756351485 |
Short name | T55 |
Test name | |
Test status | |
Simulation time | 74795611 ps |
CPU time | 0.75 seconds |
Started | Jun 07 08:25:02 PM PDT 24 |
Finished | Jun 07 08:25:08 PM PDT 24 |
Peak memory | 204800 kb |
Host | smart-9d77a45b-a9e5-4c24-b5a4-8d2de136ed5e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756351485 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.756351485 |
Directory | /workspace/36.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/37.rv_dm_alert_test.2129379806 |
Short name | T250 |
Test name | |
Test status | |
Simulation time | 76413587 ps |
CPU time | 0.73 seconds |
Started | Jun 07 08:25:02 PM PDT 24 |
Finished | Jun 07 08:25:07 PM PDT 24 |
Peak memory | 204784 kb |
Host | smart-14c81727-790b-4be3-9641-4e688ebae495 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129379806 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.2129379806 |
Directory | /workspace/37.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/38.rv_dm_alert_test.3759312350 |
Short name | T47 |
Test name | |
Test status | |
Simulation time | 230620286 ps |
CPU time | 0.71 seconds |
Started | Jun 07 08:25:00 PM PDT 24 |
Finished | Jun 07 08:25:06 PM PDT 24 |
Peak memory | 204796 kb |
Host | smart-a87b1407-7c8e-4b27-8418-2ee089aa7661 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759312350 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.3759312350 |
Directory | /workspace/38.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/39.rv_dm_alert_test.2691906054 |
Short name | T46 |
Test name | |
Test status | |
Simulation time | 198527142 ps |
CPU time | 0.79 seconds |
Started | Jun 07 08:25:03 PM PDT 24 |
Finished | Jun 07 08:25:09 PM PDT 24 |
Peak memory | 204776 kb |
Host | smart-44c22d2b-5841-45cc-8561-c7c6ca4d53df |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691906054 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.2691906054 |
Directory | /workspace/39.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/4.rv_dm_alert_test.109477195 |
Short name | T213 |
Test name | |
Test status | |
Simulation time | 87523593 ps |
CPU time | 0.71 seconds |
Started | Jun 07 08:24:41 PM PDT 24 |
Finished | Jun 07 08:24:45 PM PDT 24 |
Peak memory | 204784 kb |
Host | smart-504f8f9c-b1c5-4522-bbaf-621ea6a0cab1 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109477195 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.109477195 |
Directory | /workspace/4.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.3872148340 |
Short name | T124 |
Test name | |
Test status | |
Simulation time | 4118336434 ps |
CPU time | 13.16 seconds |
Started | Jun 07 08:24:47 PM PDT 24 |
Finished | Jun 07 08:25:06 PM PDT 24 |
Peak memory | 205180 kb |
Host | smart-329a38dc-dfaa-46fc-8d99-27d0084d159d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3872148340 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.3872148340 |
Directory | /workspace/4.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.2255054904 |
Short name | T228 |
Test name | |
Test status | |
Simulation time | 7309921203 ps |
CPU time | 8.98 seconds |
Started | Jun 07 08:24:39 PM PDT 24 |
Finished | Jun 07 08:24:50 PM PDT 24 |
Peak memory | 205212 kb |
Host | smart-5b32dd55-0216-4a58-8931-5a7ad5c2d7e3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2255054904 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.2255054904 |
Directory | /workspace/4.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.2619658986 |
Short name | T63 |
Test name | |
Test status | |
Simulation time | 9783122934 ps |
CPU time | 14.79 seconds |
Started | Jun 07 08:24:29 PM PDT 24 |
Finished | Jun 07 08:24:46 PM PDT 24 |
Peak memory | 205228 kb |
Host | smart-a6497eaa-3d34-4543-90d0-cb09b6f2b6ad |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2619658986 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t l_access.2619658986 |
Directory | /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_hart_unavail.2838905196 |
Short name | T246 |
Test name | |
Test status | |
Simulation time | 173140811 ps |
CPU time | 0.78 seconds |
Started | Jun 07 08:24:47 PM PDT 24 |
Finished | Jun 07 08:24:53 PM PDT 24 |
Peak memory | 204624 kb |
Host | smart-bf3afe19-8c8b-4a03-b394-9f6e0c46eddf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2838905196 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.2838905196 |
Directory | /workspace/4.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/4.rv_dm_sba_tl_access.1419809595 |
Short name | T200 |
Test name | |
Test status | |
Simulation time | 3225693149 ps |
CPU time | 6.6 seconds |
Started | Jun 07 08:24:29 PM PDT 24 |
Finished | Jun 07 08:24:38 PM PDT 24 |
Peak memory | 205220 kb |
Host | smart-58b57b54-384a-4bf9-88d9-dfa694ac91ac |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1419809595 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.1419809595 |
Directory | /workspace/4.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_sec_cm.394203917 |
Short name | T61 |
Test name | |
Test status | |
Simulation time | 1086816709 ps |
CPU time | 1.77 seconds |
Started | Jun 07 08:24:35 PM PDT 24 |
Finished | Jun 07 08:24:39 PM PDT 24 |
Peak memory | 228588 kb |
Host | smart-371ae308-2525-4c6d-bfc5-b0aa7eebb8f7 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394203917 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.394203917 |
Directory | /workspace/4.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/4.rv_dm_stress_all.3623575383 |
Short name | T146 |
Test name | |
Test status | |
Simulation time | 35146624175 ps |
CPU time | 58.08 seconds |
Started | Jun 07 08:24:38 PM PDT 24 |
Finished | Jun 07 08:25:38 PM PDT 24 |
Peak memory | 205100 kb |
Host | smart-2d731cbc-7d2d-47c6-a878-3bfe0ee47da1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623575383 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.3623575383 |
Directory | /workspace/4.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/40.rv_dm_alert_test.1018145115 |
Short name | T175 |
Test name | |
Test status | |
Simulation time | 32209639 ps |
CPU time | 0.73 seconds |
Started | Jun 07 08:25:00 PM PDT 24 |
Finished | Jun 07 08:25:06 PM PDT 24 |
Peak memory | 204796 kb |
Host | smart-0821fde0-f168-467e-b803-225f43c1715d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018145115 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.1018145115 |
Directory | /workspace/40.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/41.rv_dm_alert_test.2440664208 |
Short name | T24 |
Test name | |
Test status | |
Simulation time | 41222958 ps |
CPU time | 0.78 seconds |
Started | Jun 07 08:25:03 PM PDT 24 |
Finished | Jun 07 08:25:09 PM PDT 24 |
Peak memory | 204776 kb |
Host | smart-6ce92d5f-1ef3-42f9-9c08-8ea811fc6b30 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440664208 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.2440664208 |
Directory | /workspace/41.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/42.rv_dm_alert_test.1566061583 |
Short name | T181 |
Test name | |
Test status | |
Simulation time | 55308258 ps |
CPU time | 0.74 seconds |
Started | Jun 07 08:25:05 PM PDT 24 |
Finished | Jun 07 08:25:11 PM PDT 24 |
Peak memory | 204808 kb |
Host | smart-eae79321-7fd4-4f63-ad81-ce355dcada12 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566061583 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.1566061583 |
Directory | /workspace/42.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/42.rv_dm_stress_all.716635049 |
Short name | T28 |
Test name | |
Test status | |
Simulation time | 18096607271 ps |
CPU time | 56.93 seconds |
Started | Jun 07 08:25:05 PM PDT 24 |
Finished | Jun 07 08:26:07 PM PDT 24 |
Peak memory | 213236 kb |
Host | smart-6ce411df-ea28-426e-afa4-b8a439581619 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716635049 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.716635049 |
Directory | /workspace/42.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/43.rv_dm_alert_test.612570319 |
Short name | T159 |
Test name | |
Test status | |
Simulation time | 48889297 ps |
CPU time | 0.8 seconds |
Started | Jun 07 08:25:02 PM PDT 24 |
Finished | Jun 07 08:25:08 PM PDT 24 |
Peak memory | 204848 kb |
Host | smart-d0a3eb20-4fa5-4949-bc8c-63b604c2e857 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612570319 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.612570319 |
Directory | /workspace/43.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/43.rv_dm_stress_all.3159989795 |
Short name | T158 |
Test name | |
Test status | |
Simulation time | 12506027256 ps |
CPU time | 12 seconds |
Started | Jun 07 08:24:59 PM PDT 24 |
Finished | Jun 07 08:25:16 PM PDT 24 |
Peak memory | 205052 kb |
Host | smart-e47c3991-396f-441e-8360-843abec695c1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159989795 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.3159989795 |
Directory | /workspace/43.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/44.rv_dm_alert_test.602168545 |
Short name | T68 |
Test name | |
Test status | |
Simulation time | 97829066 ps |
CPU time | 0.74 seconds |
Started | Jun 07 08:25:15 PM PDT 24 |
Finished | Jun 07 08:25:18 PM PDT 24 |
Peak memory | 204784 kb |
Host | smart-58712ed6-a74c-495c-8f19-c400c8b72560 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602168545 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.602168545 |
Directory | /workspace/44.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/45.rv_dm_alert_test.388467676 |
Short name | T160 |
Test name | |
Test status | |
Simulation time | 163488277 ps |
CPU time | 1.08 seconds |
Started | Jun 07 08:25:18 PM PDT 24 |
Finished | Jun 07 08:25:23 PM PDT 24 |
Peak memory | 204808 kb |
Host | smart-1a026d03-8121-451f-b975-403ed31fb93d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388467676 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.388467676 |
Directory | /workspace/45.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/46.rv_dm_alert_test.3259627363 |
Short name | T162 |
Test name | |
Test status | |
Simulation time | 78088937 ps |
CPU time | 0.76 seconds |
Started | Jun 07 08:25:16 PM PDT 24 |
Finished | Jun 07 08:25:19 PM PDT 24 |
Peak memory | 204840 kb |
Host | smart-294b2ce4-758e-46f0-b04d-a9c5cdf116cd |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259627363 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.3259627363 |
Directory | /workspace/46.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/47.rv_dm_alert_test.2531463398 |
Short name | T161 |
Test name | |
Test status | |
Simulation time | 114949646 ps |
CPU time | 0.71 seconds |
Started | Jun 07 08:25:15 PM PDT 24 |
Finished | Jun 07 08:25:18 PM PDT 24 |
Peak memory | 204820 kb |
Host | smart-4162dd51-b498-4c9f-b141-a9b3d38528d1 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531463398 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.2531463398 |
Directory | /workspace/47.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/48.rv_dm_alert_test.266331962 |
Short name | T180 |
Test name | |
Test status | |
Simulation time | 66925989 ps |
CPU time | 0.73 seconds |
Started | Jun 07 08:25:17 PM PDT 24 |
Finished | Jun 07 08:25:21 PM PDT 24 |
Peak memory | 204800 kb |
Host | smart-172b307f-e6c5-4f77-b82e-88339cbdaa33 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266331962 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.266331962 |
Directory | /workspace/48.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/49.rv_dm_alert_test.1263017728 |
Short name | T168 |
Test name | |
Test status | |
Simulation time | 60996360 ps |
CPU time | 0.83 seconds |
Started | Jun 07 08:25:19 PM PDT 24 |
Finished | Jun 07 08:25:24 PM PDT 24 |
Peak memory | 204780 kb |
Host | smart-bb974e99-3905-4c7e-b424-c28a54e6a158 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263017728 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.1263017728 |
Directory | /workspace/49.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/5.rv_dm_alert_test.2282032611 |
Short name | T167 |
Test name | |
Test status | |
Simulation time | 121119304 ps |
CPU time | 0.74 seconds |
Started | Jun 07 08:24:37 PM PDT 24 |
Finished | Jun 07 08:24:40 PM PDT 24 |
Peak memory | 204824 kb |
Host | smart-1bac65c9-fd9d-49db-8964-d352233d4d8b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282032611 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.2282032611 |
Directory | /workspace/5.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.3772580061 |
Short name | T222 |
Test name | |
Test status | |
Simulation time | 9566816404 ps |
CPU time | 27.52 seconds |
Started | Jun 07 08:24:39 PM PDT 24 |
Finished | Jun 07 08:25:09 PM PDT 24 |
Peak memory | 213408 kb |
Host | smart-3a6bb8b2-be7d-4ba2-aec1-b26c954b32d1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3772580061 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.3772580061 |
Directory | /workspace/5.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.2314625335 |
Short name | T209 |
Test name | |
Test status | |
Simulation time | 8446211571 ps |
CPU time | 6.88 seconds |
Started | Jun 07 08:24:35 PM PDT 24 |
Finished | Jun 07 08:24:45 PM PDT 24 |
Peak memory | 213424 kb |
Host | smart-d3bb1b03-8d18-4f03-91a0-55a2c205ab4f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2314625335 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.2314625335 |
Directory | /workspace/5.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.3482595174 |
Short name | T207 |
Test name | |
Test status | |
Simulation time | 12028078695 ps |
CPU time | 36.81 seconds |
Started | Jun 07 08:24:36 PM PDT 24 |
Finished | Jun 07 08:25:16 PM PDT 24 |
Peak memory | 205228 kb |
Host | smart-92eba5ae-47ab-49cb-8659-894ae4e6b611 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3482595174 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t l_access.3482595174 |
Directory | /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_sba_tl_access.4080986373 |
Short name | T223 |
Test name | |
Test status | |
Simulation time | 7983494895 ps |
CPU time | 15.03 seconds |
Started | Jun 07 08:24:44 PM PDT 24 |
Finished | Jun 07 08:25:03 PM PDT 24 |
Peak memory | 205160 kb |
Host | smart-b6270c4e-a023-4c96-b510-f911a6ee337b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4080986373 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.4080986373 |
Directory | /workspace/5.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_alert_test.3310718245 |
Short name | T252 |
Test name | |
Test status | |
Simulation time | 117997020 ps |
CPU time | 0.81 seconds |
Started | Jun 07 08:24:34 PM PDT 24 |
Finished | Jun 07 08:24:38 PM PDT 24 |
Peak memory | 204804 kb |
Host | smart-c68bf516-738b-45ef-a71b-80e8908d4d0b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310718245 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.3310718245 |
Directory | /workspace/6.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.568920959 |
Short name | T255 |
Test name | |
Test status | |
Simulation time | 9070023413 ps |
CPU time | 6.32 seconds |
Started | Jun 07 08:24:42 PM PDT 24 |
Finished | Jun 07 08:24:51 PM PDT 24 |
Peak memory | 215248 kb |
Host | smart-0bcb3e6a-80b7-4662-9434-17ce85c8e731 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=568920959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.568920959 |
Directory | /workspace/6.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.4154305160 |
Short name | T71 |
Test name | |
Test status | |
Simulation time | 8323117391 ps |
CPU time | 8.51 seconds |
Started | Jun 07 08:24:35 PM PDT 24 |
Finished | Jun 07 08:24:46 PM PDT 24 |
Peak memory | 213480 kb |
Host | smart-28c98728-987e-4d1c-b90a-276aa6e3e5f7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4154305160 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.4154305160 |
Directory | /workspace/6.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.86727074 |
Short name | T189 |
Test name | |
Test status | |
Simulation time | 1456198186 ps |
CPU time | 4.97 seconds |
Started | Jun 07 08:24:40 PM PDT 24 |
Finished | Jun 07 08:24:46 PM PDT 24 |
Peak memory | 205076 kb |
Host | smart-151f6382-16cf-4773-bb4c-d8b55cb5eaec |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=86727074 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_tl_ access.86727074 |
Directory | /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_sba_tl_access.3746514250 |
Short name | T261 |
Test name | |
Test status | |
Simulation time | 3380297371 ps |
CPU time | 6.87 seconds |
Started | Jun 07 08:24:35 PM PDT 24 |
Finished | Jun 07 08:24:44 PM PDT 24 |
Peak memory | 205216 kb |
Host | smart-d039a044-23c1-4cc8-a878-017362b710dc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3746514250 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.3746514250 |
Directory | /workspace/6.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_alert_test.2566671013 |
Short name | T197 |
Test name | |
Test status | |
Simulation time | 84608869 ps |
CPU time | 0.73 seconds |
Started | Jun 07 08:24:42 PM PDT 24 |
Finished | Jun 07 08:24:46 PM PDT 24 |
Peak memory | 204804 kb |
Host | smart-586ca2b9-fa8a-4b4c-b7ee-9b12f6d165e3 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566671013 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.2566671013 |
Directory | /workspace/7.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.1816285932 |
Short name | T15 |
Test name | |
Test status | |
Simulation time | 2303691523 ps |
CPU time | 2.4 seconds |
Started | Jun 07 08:24:34 PM PDT 24 |
Finished | Jun 07 08:24:38 PM PDT 24 |
Peak memory | 205220 kb |
Host | smart-e80397a9-f619-4d6d-85e1-d27098f974f3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1816285932 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.1816285932 |
Directory | /workspace/7.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.2950685630 |
Short name | T244 |
Test name | |
Test status | |
Simulation time | 20950328028 ps |
CPU time | 59.64 seconds |
Started | Jun 07 08:24:40 PM PDT 24 |
Finished | Jun 07 08:25:42 PM PDT 24 |
Peak memory | 213392 kb |
Host | smart-e672215c-f289-449e-bb71-63d1645fcfa2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2950685630 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.2950685630 |
Directory | /workspace/7.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.2276767402 |
Short name | T186 |
Test name | |
Test status | |
Simulation time | 1032744976 ps |
CPU time | 2.73 seconds |
Started | Jun 07 08:24:40 PM PDT 24 |
Finished | Jun 07 08:24:45 PM PDT 24 |
Peak memory | 205088 kb |
Host | smart-a92abda3-abcc-4804-8f33-4f76f783aab4 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2276767402 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t l_access.2276767402 |
Directory | /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_sba_tl_access.3251819420 |
Short name | T238 |
Test name | |
Test status | |
Simulation time | 981481292 ps |
CPU time | 3.44 seconds |
Started | Jun 07 08:24:41 PM PDT 24 |
Finished | Jun 07 08:24:46 PM PDT 24 |
Peak memory | 205256 kb |
Host | smart-cd444f03-e87b-4c9e-ac2c-6aa4d1439a2a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3251819420 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.3251819420 |
Directory | /workspace/7.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_stress_all.3989264565 |
Short name | T153 |
Test name | |
Test status | |
Simulation time | 6523124871 ps |
CPU time | 19.52 seconds |
Started | Jun 07 08:24:36 PM PDT 24 |
Finished | Jun 07 08:24:58 PM PDT 24 |
Peak memory | 205112 kb |
Host | smart-e366359f-a093-45e9-bef6-d873ab00f577 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989264565 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.3989264565 |
Directory | /workspace/7.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/8.rv_dm_alert_test.1719456758 |
Short name | T76 |
Test name | |
Test status | |
Simulation time | 47193617 ps |
CPU time | 0.76 seconds |
Started | Jun 07 08:24:43 PM PDT 24 |
Finished | Jun 07 08:24:47 PM PDT 24 |
Peak memory | 204756 kb |
Host | smart-a362ac3b-3d05-424a-a9d6-ff329aa43015 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719456758 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.1719456758 |
Directory | /workspace/8.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.2817454147 |
Short name | T193 |
Test name | |
Test status | |
Simulation time | 24797393311 ps |
CPU time | 22.54 seconds |
Started | Jun 07 08:24:36 PM PDT 24 |
Finished | Jun 07 08:25:01 PM PDT 24 |
Peak memory | 213352 kb |
Host | smart-b7a91424-2798-4a25-a190-cdc3d7499079 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2817454147 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.2817454147 |
Directory | /workspace/8.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.2006974960 |
Short name | T258 |
Test name | |
Test status | |
Simulation time | 6937909020 ps |
CPU time | 21.26 seconds |
Started | Jun 07 08:24:37 PM PDT 24 |
Finished | Jun 07 08:25:01 PM PDT 24 |
Peak memory | 213384 kb |
Host | smart-4745c658-907b-446f-b9a2-092a16117d51 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2006974960 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.2006974960 |
Directory | /workspace/8.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.740647206 |
Short name | T196 |
Test name | |
Test status | |
Simulation time | 3030007625 ps |
CPU time | 5.5 seconds |
Started | Jun 07 08:24:34 PM PDT 24 |
Finished | Jun 07 08:24:42 PM PDT 24 |
Peak memory | 205284 kb |
Host | smart-9a68ff0a-814a-45a5-91d6-8add8d98b8e5 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=740647206 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_tl _access.740647206 |
Directory | /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_sba_tl_access.2794453816 |
Short name | T217 |
Test name | |
Test status | |
Simulation time | 2890703970 ps |
CPU time | 2.8 seconds |
Started | Jun 07 08:24:36 PM PDT 24 |
Finished | Jun 07 08:24:42 PM PDT 24 |
Peak memory | 205180 kb |
Host | smart-68d07cab-ff0b-45d6-9ea5-6389cf0af9e6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2794453816 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.2794453816 |
Directory | /workspace/8.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_alert_test.4120387752 |
Short name | T120 |
Test name | |
Test status | |
Simulation time | 203919358 ps |
CPU time | 0.84 seconds |
Started | Jun 07 08:24:45 PM PDT 24 |
Finished | Jun 07 08:24:50 PM PDT 24 |
Peak memory | 204804 kb |
Host | smart-ed4774f0-19bf-4a84-b84b-97745457eced |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120387752 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.4120387752 |
Directory | /workspace/9.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.1045487384 |
Short name | T215 |
Test name | |
Test status | |
Simulation time | 9161440280 ps |
CPU time | 8.11 seconds |
Started | Jun 07 08:24:44 PM PDT 24 |
Finished | Jun 07 08:24:55 PM PDT 24 |
Peak memory | 213396 kb |
Host | smart-81f38b4f-a74b-474c-a37b-97707acb74cd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1045487384 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.1045487384 |
Directory | /workspace/9.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.692485865 |
Short name | T224 |
Test name | |
Test status | |
Simulation time | 19465679661 ps |
CPU time | 27.77 seconds |
Started | Jun 07 08:24:38 PM PDT 24 |
Finished | Jun 07 08:25:08 PM PDT 24 |
Peak memory | 213364 kb |
Host | smart-8a682324-c4b8-44e7-a50f-c3fcc2a3693c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=692485865 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.692485865 |
Directory | /workspace/9.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.1321109002 |
Short name | T194 |
Test name | |
Test status | |
Simulation time | 2839622803 ps |
CPU time | 5.96 seconds |
Started | Jun 07 08:24:36 PM PDT 24 |
Finished | Jun 07 08:24:45 PM PDT 24 |
Peak memory | 205284 kb |
Host | smart-ac3ea430-c21b-42ac-92a9-6977aaf6b8d4 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1321109002 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t l_access.1321109002 |
Directory | /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_sba_tl_access.1649672698 |
Short name | T251 |
Test name | |
Test status | |
Simulation time | 6372631971 ps |
CPU time | 13.6 seconds |
Started | Jun 07 08:24:43 PM PDT 24 |
Finished | Jun 07 08:25:00 PM PDT 24 |
Peak memory | 205212 kb |
Host | smart-d60cc658-b03e-49f9-a89e-525b61571768 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1649672698 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.1649672698 |
Directory | /workspace/9.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_stress_all.874158655 |
Short name | T45 |
Test name | |
Test status | |
Simulation time | 15689715083 ps |
CPU time | 44.64 seconds |
Started | Jun 07 08:24:44 PM PDT 24 |
Finished | Jun 07 08:25:32 PM PDT 24 |
Peak memory | 205056 kb |
Host | smart-757d9a4e-c969-4fc9-aba1-5a180094a0bf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874158655 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.874158655 |
Directory | /workspace/9.rv_dm_stress_all/latest |
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