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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
79.30 94.66 79.40 86.17 73.08 84.67 98.31 38.80


Total test records in report: 408
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T284 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.2931353751 Jun 09 12:29:36 PM PDT 24 Jun 09 12:29:39 PM PDT 24 79014604 ps
T285 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2511396747 Jun 09 12:30:13 PM PDT 24 Jun 09 12:30:15 PM PDT 24 589225611 ps
T114 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1976813322 Jun 09 12:30:09 PM PDT 24 Jun 09 12:30:17 PM PDT 24 454169045 ps
T286 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.902950064 Jun 09 12:29:46 PM PDT 24 Jun 09 12:29:48 PM PDT 24 343982562 ps
T100 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.1896059931 Jun 09 12:29:49 PM PDT 24 Jun 09 12:29:51 PM PDT 24 81531737 ps
T287 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3490076575 Jun 09 12:30:25 PM PDT 24 Jun 09 12:30:27 PM PDT 24 290455730 ps
T162 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2500002077 Jun 09 12:29:50 PM PDT 24 Jun 09 12:29:56 PM PDT 24 100517229 ps
T101 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2919763829 Jun 09 12:29:44 PM PDT 24 Jun 09 12:31:01 PM PDT 24 15662111387 ps
T108 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.486012847 Jun 09 12:29:50 PM PDT 24 Jun 09 12:30:44 PM PDT 24 2658317307 ps
T52 /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.2235158265 Jun 09 12:29:57 PM PDT 24 Jun 09 12:30:33 PM PDT 24 39749495864 ps
T123 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3300213079 Jun 09 12:30:00 PM PDT 24 Jun 09 12:30:04 PM PDT 24 335516959 ps
T109 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.3679260485 Jun 09 12:29:46 PM PDT 24 Jun 09 12:29:48 PM PDT 24 44689617 ps
T124 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2750656388 Jun 09 12:30:28 PM PDT 24 Jun 09 12:30:49 PM PDT 24 2993032775 ps
T115 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.253350950 Jun 09 12:29:46 PM PDT 24 Jun 09 12:29:51 PM PDT 24 148859389 ps
T102 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.2029186269 Jun 09 12:29:46 PM PDT 24 Jun 09 12:29:54 PM PDT 24 550573206 ps
T288 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.2719133783 Jun 09 12:30:24 PM PDT 24 Jun 09 12:30:45 PM PDT 24 14006687724 ps
T289 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.3321791531 Jun 09 12:30:13 PM PDT 24 Jun 09 12:30:27 PM PDT 24 5140223330 ps
T290 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3629798577 Jun 09 12:30:17 PM PDT 24 Jun 09 12:30:22 PM PDT 24 146643258 ps
T291 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2332544895 Jun 09 12:30:26 PM PDT 24 Jun 09 12:30:33 PM PDT 24 270317337 ps
T103 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.1877241471 Jun 09 12:29:50 PM PDT 24 Jun 09 12:29:54 PM PDT 24 547956903 ps
T292 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.3231900022 Jun 09 12:29:44 PM PDT 24 Jun 09 12:29:46 PM PDT 24 353180776 ps
T110 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.118350122 Jun 09 12:29:47 PM PDT 24 Jun 09 12:29:50 PM PDT 24 87544875 ps
T293 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3243126242 Jun 09 12:30:08 PM PDT 24 Jun 09 12:30:10 PM PDT 24 235503886 ps
T294 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.114680894 Jun 09 12:29:46 PM PDT 24 Jun 09 12:29:48 PM PDT 24 111865902 ps
T66 /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.743186967 Jun 09 12:29:42 PM PDT 24 Jun 09 12:30:18 PM PDT 24 11797927195 ps
T116 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.1973747506 Jun 09 12:29:57 PM PDT 24 Jun 09 12:30:01 PM PDT 24 189778208 ps
T295 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.2689755905 Jun 09 12:29:35 PM PDT 24 Jun 09 12:29:37 PM PDT 24 116949993 ps
T111 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.67389895 Jun 09 12:29:46 PM PDT 24 Jun 09 12:29:49 PM PDT 24 341950637 ps
T296 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.1555824331 Jun 09 12:29:51 PM PDT 24 Jun 09 12:34:58 PM PDT 24 110392437365 ps
T104 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.2078060461 Jun 09 12:30:01 PM PDT 24 Jun 09 12:30:09 PM PDT 24 855052661 ps
T297 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.3225500435 Jun 09 12:29:31 PM PDT 24 Jun 09 12:30:37 PM PDT 24 20498069830 ps
T129 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.955585492 Jun 09 12:30:01 PM PDT 24 Jun 09 12:30:26 PM PDT 24 4006464797 ps
T298 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.2522132706 Jun 09 12:29:46 PM PDT 24 Jun 09 12:30:02 PM PDT 24 5462892237 ps
T105 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.2784355301 Jun 09 12:30:14 PM PDT 24 Jun 09 12:30:18 PM PDT 24 162626635 ps
T299 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.98983481 Jun 09 12:29:45 PM PDT 24 Jun 09 12:29:46 PM PDT 24 115736946 ps
T134 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.4223418126 Jun 09 12:30:39 PM PDT 24 Jun 09 12:30:51 PM PDT 24 4652910317 ps
T300 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.1362241538 Jun 09 12:30:26 PM PDT 24 Jun 09 12:30:46 PM PDT 24 9119810390 ps
T301 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.170988728 Jun 09 12:29:36 PM PDT 24 Jun 09 12:30:41 PM PDT 24 85129301024 ps
T112 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2304072083 Jun 09 12:29:48 PM PDT 24 Jun 09 12:30:57 PM PDT 24 2271601038 ps
T302 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1563416415 Jun 09 12:29:57 PM PDT 24 Jun 09 12:29:59 PM PDT 24 358203135 ps
T303 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.2939370666 Jun 09 12:29:46 PM PDT 24 Jun 09 12:29:48 PM PDT 24 770693267 ps
T304 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.103114605 Jun 09 12:29:46 PM PDT 24 Jun 09 12:30:10 PM PDT 24 24106134019 ps
T305 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.4001387460 Jun 09 12:29:41 PM PDT 24 Jun 09 12:29:42 PM PDT 24 75397565 ps
T306 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.111093472 Jun 09 12:29:39 PM PDT 24 Jun 09 12:29:41 PM PDT 24 602229821 ps
T135 /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.3080155599 Jun 09 12:29:39 PM PDT 24 Jun 09 12:30:08 PM PDT 24 33935094297 ps
T106 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3274765995 Jun 09 12:30:32 PM PDT 24 Jun 09 12:30:37 PM PDT 24 102432210 ps
T307 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3132588563 Jun 09 12:30:09 PM PDT 24 Jun 09 12:30:10 PM PDT 24 683996079 ps
T308 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.1227834551 Jun 09 12:29:49 PM PDT 24 Jun 09 12:29:52 PM PDT 24 1413254560 ps
T309 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.2206361185 Jun 09 12:29:50 PM PDT 24 Jun 09 12:29:51 PM PDT 24 80173762 ps
T310 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.739925131 Jun 09 12:29:47 PM PDT 24 Jun 09 12:29:52 PM PDT 24 1889196963 ps
T311 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.1458013533 Jun 09 12:29:56 PM PDT 24 Jun 09 12:29:58 PM PDT 24 54159064 ps
T312 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.2208665387 Jun 09 12:30:01 PM PDT 24 Jun 09 12:30:11 PM PDT 24 5039742963 ps
T130 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2183679180 Jun 09 12:29:46 PM PDT 24 Jun 09 12:29:56 PM PDT 24 2254571443 ps
T313 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3858803343 Jun 09 12:29:37 PM PDT 24 Jun 09 12:29:46 PM PDT 24 2802974398 ps
T314 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.1347608673 Jun 09 12:29:47 PM PDT 24 Jun 09 12:29:49 PM PDT 24 332156383 ps
T117 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.2174196966 Jun 09 12:29:49 PM PDT 24 Jun 09 12:29:56 PM PDT 24 664070239 ps
T315 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.2839355708 Jun 09 12:30:38 PM PDT 24 Jun 09 12:30:41 PM PDT 24 667968501 ps
T316 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.1227727070 Jun 09 12:29:45 PM PDT 24 Jun 09 12:29:50 PM PDT 24 1173008859 ps
T96 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2391951205 Jun 09 12:29:40 PM PDT 24 Jun 09 12:29:46 PM PDT 24 3672885337 ps
T317 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3978336855 Jun 09 12:30:00 PM PDT 24 Jun 09 12:30:12 PM PDT 24 2252231281 ps
T318 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2698897763 Jun 09 12:29:53 PM PDT 24 Jun 09 12:29:55 PM PDT 24 502382936 ps
T319 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.640983684 Jun 09 12:30:00 PM PDT 24 Jun 09 12:30:02 PM PDT 24 135479813 ps
T320 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1628755953 Jun 09 12:29:46 PM PDT 24 Jun 09 12:29:54 PM PDT 24 1847337795 ps
T321 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3211974883 Jun 09 12:29:43 PM PDT 24 Jun 09 12:29:50 PM PDT 24 184176637 ps
T132 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3868258333 Jun 09 12:29:59 PM PDT 24 Jun 09 12:30:08 PM PDT 24 1571982175 ps
T322 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.4246028352 Jun 09 12:29:46 PM PDT 24 Jun 09 12:29:50 PM PDT 24 2965631519 ps
T323 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.724077088 Jun 09 12:29:46 PM PDT 24 Jun 09 12:29:47 PM PDT 24 77562083 ps
T324 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3541731288 Jun 09 12:30:28 PM PDT 24 Jun 09 12:30:34 PM PDT 24 875801634 ps
T325 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.234391888 Jun 09 12:29:42 PM PDT 24 Jun 09 12:29:47 PM PDT 24 281786808 ps
T326 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.1279850420 Jun 09 12:29:54 PM PDT 24 Jun 09 12:29:56 PM PDT 24 1360338477 ps
T327 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.3475648491 Jun 09 12:30:00 PM PDT 24 Jun 09 12:30:13 PM PDT 24 15361717533 ps
T328 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3416946082 Jun 09 12:29:36 PM PDT 24 Jun 09 12:29:37 PM PDT 24 143773838 ps
T329 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.958981732 Jun 09 12:30:27 PM PDT 24 Jun 09 12:30:29 PM PDT 24 75777251 ps
T133 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.564830797 Jun 09 12:29:52 PM PDT 24 Jun 09 12:30:13 PM PDT 24 3527853318 ps
T330 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3641706490 Jun 09 12:29:41 PM PDT 24 Jun 09 12:29:44 PM PDT 24 3482440403 ps
T331 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2866424168 Jun 09 12:30:19 PM PDT 24 Jun 09 12:30:26 PM PDT 24 1332058598 ps
T332 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.3562197665 Jun 09 12:29:49 PM PDT 24 Jun 09 12:29:51 PM PDT 24 150225032 ps
T333 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.2023157190 Jun 09 12:29:47 PM PDT 24 Jun 09 12:29:58 PM PDT 24 1560967834 ps
T334 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.4280896414 Jun 09 12:29:45 PM PDT 24 Jun 09 12:29:48 PM PDT 24 686696694 ps
T335 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.1826363092 Jun 09 12:29:37 PM PDT 24 Jun 09 12:29:41 PM PDT 24 1324917671 ps
T336 /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.4024383409 Jun 09 12:29:41 PM PDT 24 Jun 09 12:30:39 PM PDT 24 66606283623 ps
T337 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.1385671300 Jun 09 12:29:44 PM PDT 24 Jun 09 12:29:49 PM PDT 24 763883575 ps
T338 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.254756115 Jun 09 12:30:21 PM PDT 24 Jun 09 12:30:24 PM PDT 24 203286307 ps
T107 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.3086428312 Jun 09 12:29:43 PM PDT 24 Jun 09 12:29:46 PM PDT 24 719329411 ps
T339 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.4222982004 Jun 09 12:29:55 PM PDT 24 Jun 09 12:29:57 PM PDT 24 131031692 ps
T340 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.2740245240 Jun 09 12:30:31 PM PDT 24 Jun 09 12:30:40 PM PDT 24 4885683007 ps
T341 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.3687556470 Jun 09 12:29:57 PM PDT 24 Jun 09 12:30:03 PM PDT 24 254769534 ps
T342 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.1095461350 Jun 09 12:29:38 PM PDT 24 Jun 09 12:29:41 PM PDT 24 725380089 ps
T343 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.514323281 Jun 09 12:29:35 PM PDT 24 Jun 09 12:29:36 PM PDT 24 50017298 ps
T344 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1164174802 Jun 09 12:29:42 PM PDT 24 Jun 09 12:30:08 PM PDT 24 2391059170 ps
T345 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.827457931 Jun 09 12:29:48 PM PDT 24 Jun 09 12:30:02 PM PDT 24 7377792126 ps
T346 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.129724738 Jun 09 12:29:47 PM PDT 24 Jun 09 12:31:05 PM PDT 24 7593564663 ps
T347 /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.2173819371 Jun 09 12:29:44 PM PDT 24 Jun 09 12:30:31 PM PDT 24 30217165445 ps
T348 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.4230447467 Jun 09 12:30:33 PM PDT 24 Jun 09 12:30:45 PM PDT 24 17483668161 ps
T349 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.3921488855 Jun 09 12:29:36 PM PDT 24 Jun 09 12:29:37 PM PDT 24 54691594 ps
T350 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1179368296 Jun 09 12:30:24 PM PDT 24 Jun 09 12:30:28 PM PDT 24 412265228 ps
T351 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2258159225 Jun 09 12:29:58 PM PDT 24 Jun 09 12:29:59 PM PDT 24 298687808 ps
T352 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1364556019 Jun 09 12:29:30 PM PDT 24 Jun 09 12:29:32 PM PDT 24 277080670 ps
T353 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.3344307648 Jun 09 12:29:48 PM PDT 24 Jun 09 12:29:49 PM PDT 24 186327237 ps
T354 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.600418253 Jun 09 12:29:53 PM PDT 24 Jun 09 12:30:01 PM PDT 24 3281998514 ps
T355 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.1815224982 Jun 09 12:29:51 PM PDT 24 Jun 09 12:29:59 PM PDT 24 1579608845 ps
T356 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2779429655 Jun 09 12:29:53 PM PDT 24 Jun 09 12:29:59 PM PDT 24 6291478548 ps
T357 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2720126336 Jun 09 12:29:42 PM PDT 24 Jun 09 12:29:44 PM PDT 24 314775148 ps
T358 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.3844301683 Jun 09 12:30:29 PM PDT 24 Jun 09 12:30:36 PM PDT 24 4197369406 ps
T359 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.893288298 Jun 09 12:30:22 PM PDT 24 Jun 09 12:30:24 PM PDT 24 66080827 ps
T360 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.3759929066 Jun 09 12:30:35 PM PDT 24 Jun 09 12:30:43 PM PDT 24 3529586931 ps
T361 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3684732476 Jun 09 12:29:53 PM PDT 24 Jun 09 12:30:00 PM PDT 24 348428119 ps
T362 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.3648187563 Jun 09 12:30:00 PM PDT 24 Jun 09 12:30:08 PM PDT 24 3758775039 ps
T363 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.3400090527 Jun 09 12:29:59 PM PDT 24 Jun 09 12:30:01 PM PDT 24 156194174 ps
T131 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2196707199 Jun 09 12:29:47 PM PDT 24 Jun 09 12:29:56 PM PDT 24 1193748486 ps
T364 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.2660905952 Jun 09 12:29:59 PM PDT 24 Jun 09 12:30:02 PM PDT 24 112221569 ps
T365 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3550195422 Jun 09 12:29:59 PM PDT 24 Jun 09 12:30:27 PM PDT 24 17623743049 ps
T366 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.843674246 Jun 09 12:29:56 PM PDT 24 Jun 09 12:29:59 PM PDT 24 287815129 ps
T367 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.17080603 Jun 09 12:30:13 PM PDT 24 Jun 09 12:30:27 PM PDT 24 4495323247 ps
T126 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.298400582 Jun 09 12:29:47 PM PDT 24 Jun 09 12:29:59 PM PDT 24 3386380898 ps
T368 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2541312023 Jun 09 12:29:53 PM PDT 24 Jun 09 12:29:56 PM PDT 24 175056647 ps
T369 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2964818310 Jun 09 12:30:00 PM PDT 24 Jun 09 12:30:03 PM PDT 24 107108919 ps
T370 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.3798986879 Jun 09 12:29:42 PM PDT 24 Jun 09 12:30:31 PM PDT 24 61477056305 ps
T371 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.2251018150 Jun 09 12:29:59 PM PDT 24 Jun 09 12:30:12 PM PDT 24 4087918544 ps
T372 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.488412502 Jun 09 12:29:54 PM PDT 24 Jun 09 12:29:57 PM PDT 24 441857080 ps
T373 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.2358930668 Jun 09 12:30:00 PM PDT 24 Jun 09 12:30:02 PM PDT 24 152992011 ps
T374 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3596254024 Jun 09 12:30:25 PM PDT 24 Jun 09 12:30:46 PM PDT 24 2651583065 ps
T375 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.4127130562 Jun 09 12:30:25 PM PDT 24 Jun 09 12:30:30 PM PDT 24 346255387 ps
T376 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.438478235 Jun 09 12:29:59 PM PDT 24 Jun 09 12:30:08 PM PDT 24 5510286066 ps
T377 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.1569037484 Jun 09 12:29:45 PM PDT 24 Jun 09 12:29:46 PM PDT 24 79911332 ps
T378 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.76484970 Jun 09 12:29:59 PM PDT 24 Jun 09 12:30:08 PM PDT 24 2943092822 ps
T379 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2641025324 Jun 09 12:30:36 PM PDT 24 Jun 09 12:30:46 PM PDT 24 12138863165 ps
T380 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.688592015 Jun 09 12:29:46 PM PDT 24 Jun 09 12:31:55 PM PDT 24 91492134243 ps
T381 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.880987332 Jun 09 12:30:06 PM PDT 24 Jun 09 12:30:08 PM PDT 24 330205832 ps
T382 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.3067450750 Jun 09 12:29:39 PM PDT 24 Jun 09 12:29:41 PM PDT 24 75481856 ps
T383 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.2904393954 Jun 09 12:29:41 PM PDT 24 Jun 09 12:29:52 PM PDT 24 1087015823 ps
T384 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2051617036 Jun 09 12:30:17 PM PDT 24 Jun 09 12:30:24 PM PDT 24 880324958 ps
T385 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2333045295 Jun 09 12:30:21 PM PDT 24 Jun 09 12:30:23 PM PDT 24 47396757 ps
T386 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.985439829 Jun 09 12:30:27 PM PDT 24 Jun 09 12:30:34 PM PDT 24 1150095645 ps
T387 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.3176427655 Jun 09 12:29:39 PM PDT 24 Jun 09 12:30:04 PM PDT 24 15974161348 ps
T388 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.3568260360 Jun 09 12:29:59 PM PDT 24 Jun 09 12:30:19 PM PDT 24 17294534069 ps
T389 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.2477421234 Jun 09 12:30:03 PM PDT 24 Jun 09 12:30:10 PM PDT 24 672395602 ps
T390 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3598802113 Jun 09 12:30:07 PM PDT 24 Jun 09 12:30:20 PM PDT 24 5687394802 ps
T391 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3449183900 Jun 09 12:29:45 PM PDT 24 Jun 09 12:31:42 PM PDT 24 41062421726 ps
T392 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.3781377280 Jun 09 12:30:33 PM PDT 24 Jun 09 12:30:35 PM PDT 24 288877870 ps
T97 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2354990959 Jun 09 12:29:49 PM PDT 24 Jun 09 12:29:55 PM PDT 24 5373927591 ps
T393 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3954615655 Jun 09 12:29:47 PM PDT 24 Jun 09 12:29:49 PM PDT 24 254758544 ps
T394 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.3243086548 Jun 09 12:30:31 PM PDT 24 Jun 09 12:30:35 PM PDT 24 339324593 ps
T395 /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.2606943714 Jun 09 12:29:44 PM PDT 24 Jun 09 12:31:15 PM PDT 24 45560100138 ps
T396 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1376272369 Jun 09 12:30:01 PM PDT 24 Jun 09 12:30:07 PM PDT 24 1329288356 ps
T397 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.291955792 Jun 09 12:29:42 PM PDT 24 Jun 09 12:29:54 PM PDT 24 3737578975 ps
T398 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1777658597 Jun 09 12:29:34 PM PDT 24 Jun 09 12:30:14 PM PDT 24 27376690654 ps
T399 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.4017612730 Jun 09 12:30:11 PM PDT 24 Jun 09 12:30:15 PM PDT 24 379116480 ps
T400 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.2084127243 Jun 09 12:29:53 PM PDT 24 Jun 09 12:29:55 PM PDT 24 64116931 ps
T401 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.2539668674 Jun 09 12:29:53 PM PDT 24 Jun 09 12:29:55 PM PDT 24 201168467 ps
T402 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.3226665693 Jun 09 12:30:18 PM PDT 24 Jun 09 12:30:22 PM PDT 24 1654434807 ps
T403 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2361984632 Jun 09 12:29:47 PM PDT 24 Jun 09 12:29:49 PM PDT 24 83707819 ps
T404 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.1714649489 Jun 09 12:29:59 PM PDT 24 Jun 09 12:30:57 PM PDT 24 67650085007 ps
T405 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.4200566098 Jun 09 12:29:59 PM PDT 24 Jun 09 12:30:38 PM PDT 24 21627420103 ps
T406 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.253935475 Jun 09 12:30:14 PM PDT 24 Jun 09 12:30:32 PM PDT 24 18844757813 ps
T128 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.1805950906 Jun 09 12:30:10 PM PDT 24 Jun 09 12:30:22 PM PDT 24 4901134417 ps
T407 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.1495548863 Jun 09 12:29:35 PM PDT 24 Jun 09 12:29:37 PM PDT 24 100757208 ps
T408 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.4235989742 Jun 09 12:29:45 PM PDT 24 Jun 09 12:29:52 PM PDT 24 206524234 ps

Test location /workspace/coverage/default/34.rv_dm_stress_all.3269410748
Short name T1
Test name
Test status
Simulation time 21815097094 ps
CPU time 15.86 seconds
Started Jun 09 12:32:32 PM PDT 24
Finished Jun 09 12:32:48 PM PDT 24
Peak memory 213216 kb
Host smart-0172539b-7743-4a4d-a9bc-45b8c2c580fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269410748 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.3269410748
Directory /workspace/34.rv_dm_stress_all/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.721559359
Short name T18
Test name
Test status
Simulation time 2059200893 ps
CPU time 2.41 seconds
Started Jun 09 12:32:13 PM PDT 24
Finished Jun 09 12:32:15 PM PDT 24
Peak memory 205016 kb
Host smart-aab49c60-07b8-4496-85eb-94a21b247a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721559359 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.721559359
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.3673641492
Short name T55
Test name
Test status
Simulation time 10407738617 ps
CPU time 40.39 seconds
Started Jun 09 12:30:22 PM PDT 24
Finished Jun 09 12:31:04 PM PDT 24
Peak memory 213336 kb
Host smart-71a4ead3-953a-4ab9-8b2d-a41e3542b52b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673641492 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.3
673641492
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.2177753723
Short name T54
Test name
Test status
Simulation time 139122352 ps
CPU time 0.82 seconds
Started Jun 09 12:32:26 PM PDT 24
Finished Jun 09 12:32:27 PM PDT 24
Peak memory 204760 kb
Host smart-d00cf8ad-5872-42f7-907e-0d0d27691395
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177753723 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.2177753723
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.657920524
Short name T51
Test name
Test status
Simulation time 20551674158 ps
CPU time 19.44 seconds
Started Jun 09 12:29:53 PM PDT 24
Finished Jun 09 12:30:13 PM PDT 24
Peak memory 221472 kb
Host smart-1da83e86-bb8e-4b6b-a067-501fb41413f1
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657920524 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.657920524
Directory /workspace/5.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/8.rv_dm_stress_all.3597517570
Short name T41
Test name
Test status
Simulation time 19673407242 ps
CPU time 57.46 seconds
Started Jun 09 12:32:19 PM PDT 24
Finished Jun 09 12:33:17 PM PDT 24
Peak memory 205076 kb
Host smart-f2657cfd-06ea-4de9-b18e-466a58563bc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597517570 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.3597517570
Directory /workspace/8.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2919763829
Short name T101
Test name
Test status
Simulation time 15662111387 ps
CPU time 76.65 seconds
Started Jun 09 12:29:44 PM PDT 24
Finished Jun 09 12:31:01 PM PDT 24
Peak memory 213344 kb
Host smart-b0c42796-581f-42f5-abbf-6322470bd423
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919763829 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.2919763829
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.2003436298
Short name T34
Test name
Test status
Simulation time 18703368672 ps
CPU time 51.44 seconds
Started Jun 09 12:32:23 PM PDT 24
Finished Jun 09 12:33:15 PM PDT 24
Peak memory 205316 kb
Host smart-505fabe3-2eb5-49a1-a0ed-bade81b9aa93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003436298 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.2003436298
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.423886429
Short name T26
Test name
Test status
Simulation time 41197104730 ps
CPU time 58.61 seconds
Started Jun 09 12:32:22 PM PDT 24
Finished Jun 09 12:33:21 PM PDT 24
Peak memory 213436 kb
Host smart-94873baa-32ea-4012-a673-840c5556ca2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423886429 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.423886429
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.2419205205
Short name T99
Test name
Test status
Simulation time 1112764993 ps
CPU time 64.4 seconds
Started Jun 09 12:29:38 PM PDT 24
Finished Jun 09 12:30:43 PM PDT 24
Peak memory 213232 kb
Host smart-d1a82466-1d6a-4550-96cc-5502dddfca70
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419205205 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.2419205205
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.2235158265
Short name T52
Test name
Test status
Simulation time 39749495864 ps
CPU time 35.02 seconds
Started Jun 09 12:29:57 PM PDT 24
Finished Jun 09 12:30:33 PM PDT 24
Peak memory 221532 kb
Host smart-afcb7dcb-9392-4b26-b72b-d74e860b5e04
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235158265 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.2235158265
Directory /workspace/8.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.743186967
Short name T66
Test name
Test status
Simulation time 11797927195 ps
CPU time 36.07 seconds
Started Jun 09 12:29:42 PM PDT 24
Finished Jun 09 12:30:18 PM PDT 24
Peak memory 217724 kb
Host smart-db7daf2a-a6f9-45b5-8488-b6d35ab560dd
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743186967 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.743186967
Directory /workspace/0.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.3033473466
Short name T6
Test name
Test status
Simulation time 184667794 ps
CPU time 0.82 seconds
Started Jun 09 12:31:45 PM PDT 24
Finished Jun 09 12:31:46 PM PDT 24
Peak memory 204716 kb
Host smart-50694ba4-e1ba-42e9-b660-2502d860eba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033473466 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.3033473466
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.3898360862
Short name T48
Test name
Test status
Simulation time 1474745398 ps
CPU time 2.99 seconds
Started Jun 09 12:31:57 PM PDT 24
Finished Jun 09 12:32:00 PM PDT 24
Peak memory 229236 kb
Host smart-c793b6fd-5bb6-4db0-a3b7-bb41fbc10a9a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898360862 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.3898360862
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/26.rv_dm_stress_all.227909230
Short name T40
Test name
Test status
Simulation time 15253754061 ps
CPU time 9.88 seconds
Started Jun 09 12:32:27 PM PDT 24
Finished Jun 09 12:32:37 PM PDT 24
Peak memory 205028 kb
Host smart-088d5936-0a83-48ed-9310-97b2f1d798e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227909230 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.227909230
Directory /workspace/26.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.1655793794
Short name T75
Test name
Test status
Simulation time 6281667131 ps
CPU time 24.54 seconds
Started Jun 09 12:29:49 PM PDT 24
Finished Jun 09 12:30:13 PM PDT 24
Peak memory 213376 kb
Host smart-0cc077f0-8eda-4ac8-90ec-27bf4c134b07
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655793794 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.1655793794
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.2664349322
Short name T38
Test name
Test status
Simulation time 85424402 ps
CPU time 0.98 seconds
Started Jun 09 12:31:46 PM PDT 24
Finished Jun 09 12:31:47 PM PDT 24
Peak memory 212952 kb
Host smart-3a406a88-5c98-4ef4-94b1-09b1c1a9fe20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664349322 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.2664349322
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.3241088986
Short name T7
Test name
Test status
Simulation time 1040732143 ps
CPU time 1.33 seconds
Started Jun 09 12:31:30 PM PDT 24
Finished Jun 09 12:31:32 PM PDT 24
Peak memory 204652 kb
Host smart-894ff240-5d7b-4e97-9d6a-ef814a13835f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241088986 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.3241088986
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.339714981
Short name T215
Test name
Test status
Simulation time 28230716493 ps
CPU time 75.96 seconds
Started Jun 09 12:32:18 PM PDT 24
Finished Jun 09 12:33:34 PM PDT 24
Peak memory 213412 kb
Host smart-f99dc112-f016-4cfc-acaa-2e30b090fed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339714981 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.339714981
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1356928290
Short name T87
Test name
Test status
Simulation time 972459232 ps
CPU time 6.24 seconds
Started Jun 09 12:30:11 PM PDT 24
Finished Jun 09 12:30:18 PM PDT 24
Peak memory 205036 kb
Host smart-74932977-0fb2-4b32-8a80-71af749734fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356928290 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.1356928290
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.3702132105
Short name T46
Test name
Test status
Simulation time 258994212 ps
CPU time 1.39 seconds
Started Jun 09 12:31:44 PM PDT 24
Finished Jun 09 12:31:46 PM PDT 24
Peak memory 204668 kb
Host smart-fbd30f17-0ef7-4de2-8e42-87c5202297e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702132105 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.3702132105
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.3435485819
Short name T31
Test name
Test status
Simulation time 65197080 ps
CPU time 0.76 seconds
Started Jun 09 12:32:28 PM PDT 24
Finished Jun 09 12:32:30 PM PDT 24
Peak memory 204760 kb
Host smart-46daa70d-fc92-4c85-97df-3c519123fca0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435485819 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.3435485819
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.2231653091
Short name T88
Test name
Test status
Simulation time 1666724627 ps
CPU time 17.43 seconds
Started Jun 09 12:29:37 PM PDT 24
Finished Jun 09 12:29:55 PM PDT 24
Peak memory 213276 kb
Host smart-8fba1681-a297-4b58-8b32-60af9908dc32
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231653091 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.2231653091
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.2817185694
Short name T281
Test name
Test status
Simulation time 7089118999 ps
CPU time 20.82 seconds
Started Jun 09 12:29:38 PM PDT 24
Finished Jun 09 12:29:59 PM PDT 24
Peak memory 204956 kb
Host smart-fb9a2458-2b6e-43a2-a91d-6a1249c10bfe
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817185694 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.2817185694
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.3392171281
Short name T95
Test name
Test status
Simulation time 2121274447 ps
CPU time 2.36 seconds
Started Jun 09 12:29:46 PM PDT 24
Finished Jun 09 12:29:49 PM PDT 24
Peak memory 205060 kb
Host smart-328f2d89-47ac-4b49-b742-02699f530580
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392171281 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.3392171281
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1602128122
Short name T79
Test name
Test status
Simulation time 3168108170 ps
CPU time 21.26 seconds
Started Jun 09 12:29:52 PM PDT 24
Finished Jun 09 12:30:14 PM PDT 24
Peak memory 213352 kb
Host smart-16aaa23d-7c12-4105-8dce-d38224fcdf13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602128122 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.1
602128122
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.288210724
Short name T127
Test name
Test status
Simulation time 2055380377 ps
CPU time 18.65 seconds
Started Jun 09 12:29:48 PM PDT 24
Finished Jun 09 12:30:07 PM PDT 24
Peak memory 213280 kb
Host smart-61f37638-a35d-4254-befe-8f9de353a785
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288210724 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.288210724
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.1044655601
Short name T151
Test name
Test status
Simulation time 59344025 ps
CPU time 0.85 seconds
Started Jun 09 12:31:50 PM PDT 24
Finished Jun 09 12:31:52 PM PDT 24
Peak memory 204748 kb
Host smart-a605cd10-039d-47bc-b0c6-eb1333902bfc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044655601 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.1044655601
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.3642317240
Short name T35
Test name
Test status
Simulation time 1185367262 ps
CPU time 1.44 seconds
Started Jun 09 12:31:31 PM PDT 24
Finished Jun 09 12:31:33 PM PDT 24
Peak memory 204528 kb
Host smart-5f060695-9d29-47c8-8f78-c19fedd3d84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642317240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.3642317240
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.4131994135
Short name T17
Test name
Test status
Simulation time 734568297 ps
CPU time 1.69 seconds
Started Jun 09 12:31:37 PM PDT 24
Finished Jun 09 12:31:39 PM PDT 24
Peak memory 204692 kb
Host smart-aa245d6a-5834-4d80-8b65-0d9021d1da6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131994135 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.4131994135
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.3225500435
Short name T297
Test name
Test status
Simulation time 20498069830 ps
CPU time 66.02 seconds
Started Jun 09 12:29:31 PM PDT 24
Finished Jun 09 12:30:37 PM PDT 24
Peak memory 213388 kb
Host smart-68faedbc-7569-4dcf-b785-6bdf9d9d8e28
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225500435 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.3225500435
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.2029186269
Short name T102
Test name
Test status
Simulation time 550573206 ps
CPU time 2.74 seconds
Started Jun 09 12:29:46 PM PDT 24
Finished Jun 09 12:29:54 PM PDT 24
Peak memory 213496 kb
Host smart-255c63c4-2388-4111-879d-78d3faa336f2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029186269 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.2029186269
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3858803343
Short name T313
Test name
Test status
Simulation time 2802974398 ps
CPU time 7.88 seconds
Started Jun 09 12:29:37 PM PDT 24
Finished Jun 09 12:29:46 PM PDT 24
Peak memory 220264 kb
Host smart-199b3529-6ed6-43b4-b4d0-955494aabfb5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858803343 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.3858803343
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.3679260485
Short name T109
Test name
Test status
Simulation time 44689617 ps
CPU time 1.45 seconds
Started Jun 09 12:29:46 PM PDT 24
Finished Jun 09 12:29:48 PM PDT 24
Peak memory 213208 kb
Host smart-6bc403f2-d1a1-466f-9479-34fa2da1ee2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679260485 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.3679260485
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.442509481
Short name T263
Test name
Test status
Simulation time 44746947698 ps
CPU time 27.03 seconds
Started Jun 09 12:29:43 PM PDT 24
Finished Jun 09 12:30:11 PM PDT 24
Peak memory 205020 kb
Host smart-8594fb4c-c36b-4b4c-9ea3-c4450d3472b1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442509481 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr
_aliasing.442509481
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.3921488855
Short name T349
Test name
Test status
Simulation time 54691594 ps
CPU time 0.69 seconds
Started Jun 09 12:29:36 PM PDT 24
Finished Jun 09 12:29:37 PM PDT 24
Peak memory 204632 kb
Host smart-a3f64c5d-951e-4baa-a68e-db2edfb093ab
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921488855 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
rv_dm_jtag_dmi_csr_bit_bash.3921488855
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3641706490
Short name T330
Test name
Test status
Simulation time 3482440403 ps
CPU time 3 seconds
Started Jun 09 12:29:41 PM PDT 24
Finished Jun 09 12:29:44 PM PDT 24
Peak memory 204852 kb
Host smart-17b5349b-bbda-476e-a942-f9f2fee29150
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641706490 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.3
641706490
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.1095461350
Short name T342
Test name
Test status
Simulation time 725380089 ps
CPU time 2.91 seconds
Started Jun 09 12:29:38 PM PDT 24
Finished Jun 09 12:29:41 PM PDT 24
Peak memory 204636 kb
Host smart-c62cbda7-cf00-4b03-bbfb-4e17ba958ed0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095461350 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.1095461350
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.1533904090
Short name T280
Test name
Test status
Simulation time 736452678 ps
CPU time 1.22 seconds
Started Jun 09 12:29:45 PM PDT 24
Finished Jun 09 12:29:46 PM PDT 24
Peak memory 204732 kb
Host smart-aa571f7e-f206-49cf-bded-4e3887ac42c1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533904090 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.1533904090
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1364556019
Short name T352
Test name
Test status
Simulation time 277080670 ps
CPU time 1.09 seconds
Started Jun 09 12:29:30 PM PDT 24
Finished Jun 09 12:29:32 PM PDT 24
Peak memory 204720 kb
Host smart-67d4fd3f-9244-43bc-bb48-0d57a782d8b9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364556019 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.1
364556019
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.2689755905
Short name T295
Test name
Test status
Simulation time 116949993 ps
CPU time 0.93 seconds
Started Jun 09 12:29:35 PM PDT 24
Finished Jun 09 12:29:37 PM PDT 24
Peak memory 204612 kb
Host smart-7fd51e21-9a50-49fb-b179-34a8ac961842
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689755905 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.2689755905
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.1569037484
Short name T377
Test name
Test status
Simulation time 79911332 ps
CPU time 0.68 seconds
Started Jun 09 12:29:45 PM PDT 24
Finished Jun 09 12:29:46 PM PDT 24
Peak memory 204668 kb
Host smart-c569e33f-4e37-46f8-990f-3a4a9a6a6434
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569037484 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.1569037484
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1628755953
Short name T320
Test name
Test status
Simulation time 1847337795 ps
CPU time 7.42 seconds
Started Jun 09 12:29:46 PM PDT 24
Finished Jun 09 12:29:54 PM PDT 24
Peak memory 205056 kb
Host smart-56dbe337-05b3-43bf-ae26-97a922d25144
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628755953 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.1628755953
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.234391888
Short name T325
Test name
Test status
Simulation time 281786808 ps
CPU time 4.37 seconds
Started Jun 09 12:29:42 PM PDT 24
Finished Jun 09 12:29:47 PM PDT 24
Peak memory 213320 kb
Host smart-50f37523-b8f8-41d4-bbcc-39d43bc60324
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234391888 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.234391888
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1164174802
Short name T344
Test name
Test status
Simulation time 2391059170 ps
CPU time 25.64 seconds
Started Jun 09 12:29:42 PM PDT 24
Finished Jun 09 12:30:08 PM PDT 24
Peak memory 204980 kb
Host smart-0ded4fd3-6c8a-48ac-a5ce-da27e2a2bf41
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164174802 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.1164174802
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2346735594
Short name T61
Test name
Test status
Simulation time 2499981153 ps
CPU time 33.94 seconds
Started Jun 09 12:29:38 PM PDT 24
Finished Jun 09 12:30:12 PM PDT 24
Peak memory 213328 kb
Host smart-4a9e9c4c-4f6e-4308-bca7-31af7616ea56
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346735594 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.2346735594
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.816959236
Short name T84
Test name
Test status
Simulation time 576829460 ps
CPU time 2.49 seconds
Started Jun 09 12:29:38 PM PDT 24
Finished Jun 09 12:29:41 PM PDT 24
Peak memory 213208 kb
Host smart-e48124ec-c915-4dd2-946d-2e03fad178c3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816959236 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.816959236
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3225261446
Short name T56
Test name
Test status
Simulation time 4370381709 ps
CPU time 3.72 seconds
Started Jun 09 12:29:39 PM PDT 24
Finished Jun 09 12:29:43 PM PDT 24
Peak memory 213340 kb
Host smart-85687c49-11bf-4a63-9ce0-8537f6fd8312
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225261446 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.3225261446
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.67389895
Short name T111
Test name
Test status
Simulation time 341950637 ps
CPU time 2.03 seconds
Started Jun 09 12:29:46 PM PDT 24
Finished Jun 09 12:29:49 PM PDT 24
Peak memory 213336 kb
Host smart-db569de0-6cb9-41e6-b77b-eac4c310b0df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67389895 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.67389895
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3449183900
Short name T391
Test name
Test status
Simulation time 41062421726 ps
CPU time 116.37 seconds
Started Jun 09 12:29:45 PM PDT 24
Finished Jun 09 12:31:42 PM PDT 24
Peak memory 204948 kb
Host smart-b604c7ab-91a2-4a23-9400-f2ad354d00dc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449183900 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
rv_dm_jtag_dmi_csr_bit_bash.3449183900
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2354990959
Short name T97
Test name
Test status
Simulation time 5373927591 ps
CPU time 5.19 seconds
Started Jun 09 12:29:49 PM PDT 24
Finished Jun 09 12:29:55 PM PDT 24
Peak memory 205112 kb
Host smart-7d7a6eba-cc8a-455f-a602-7f36d3738221
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354990959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.2354990959
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.3176427655
Short name T387
Test name
Test status
Simulation time 15974161348 ps
CPU time 25.09 seconds
Started Jun 09 12:29:39 PM PDT 24
Finished Jun 09 12:30:04 PM PDT 24
Peak memory 204916 kb
Host smart-1e8f0d9e-8db6-4211-adb0-fe709c0b4556
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176427655 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.3
176427655
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.902950064
Short name T286
Test name
Test status
Simulation time 343982562 ps
CPU time 0.98 seconds
Started Jun 09 12:29:46 PM PDT 24
Finished Jun 09 12:29:48 PM PDT 24
Peak memory 204644 kb
Host smart-5e830582-a23b-4c5c-8098-9193ee472307
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902950064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_aliasing.902950064
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.103114605
Short name T304
Test name
Test status
Simulation time 24106134019 ps
CPU time 23.68 seconds
Started Jun 09 12:29:46 PM PDT 24
Finished Jun 09 12:30:10 PM PDT 24
Peak memory 204960 kb
Host smart-6bcfabe5-e150-45e2-93af-588456dad96c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103114605 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_bit_bash.103114605
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2720126336
Short name T357
Test name
Test status
Simulation time 314775148 ps
CPU time 1.5 seconds
Started Jun 09 12:29:42 PM PDT 24
Finished Jun 09 12:29:44 PM PDT 24
Peak memory 204676 kb
Host smart-bd84f492-d4d2-48e8-b7ee-44b6d490bb43
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720126336 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.2720126336
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.726696943
Short name T68
Test name
Test status
Simulation time 569586908 ps
CPU time 1.47 seconds
Started Jun 09 12:29:46 PM PDT 24
Finished Jun 09 12:29:48 PM PDT 24
Peak memory 204612 kb
Host smart-3ac9d0d4-fef7-4a89-8578-17de42fd6e61
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726696943 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.726696943
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.514323281
Short name T343
Test name
Test status
Simulation time 50017298 ps
CPU time 0.7 seconds
Started Jun 09 12:29:35 PM PDT 24
Finished Jun 09 12:29:36 PM PDT 24
Peak memory 204552 kb
Host smart-6f319446-7742-41ce-b02b-f85668450576
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514323281 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_part
ial_access.514323281
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.114680894
Short name T294
Test name
Test status
Simulation time 111865902 ps
CPU time 0.96 seconds
Started Jun 09 12:29:46 PM PDT 24
Finished Jun 09 12:29:48 PM PDT 24
Peak memory 204620 kb
Host smart-25b908fd-0af3-4d3e-bff3-904bd65e6733
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114680894 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.114680894
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.164873494
Short name T83
Test name
Test status
Simulation time 453452266 ps
CPU time 4.46 seconds
Started Jun 09 12:29:48 PM PDT 24
Finished Jun 09 12:29:53 PM PDT 24
Peak memory 205068 kb
Host smart-c536f94d-80a8-4f23-a2a1-bd2a9146adef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164873494 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_c
sr_outstanding.164873494
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.2606943714
Short name T395
Test name
Test status
Simulation time 45560100138 ps
CPU time 90.92 seconds
Started Jun 09 12:29:44 PM PDT 24
Finished Jun 09 12:31:15 PM PDT 24
Peak memory 221484 kb
Host smart-834b540e-5ebe-4417-9606-7d2804709ab2
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606943714 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.2606943714
Directory /workspace/1.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.2931353751
Short name T284
Test name
Test status
Simulation time 79014604 ps
CPU time 2.61 seconds
Started Jun 09 12:29:36 PM PDT 24
Finished Jun 09 12:29:39 PM PDT 24
Peak memory 213244 kb
Host smart-5224053f-b45b-403d-850b-e75ba7a3845d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931353751 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.2931353751
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.2904393954
Short name T383
Test name
Test status
Simulation time 1087015823 ps
CPU time 11.25 seconds
Started Jun 09 12:29:41 PM PDT 24
Finished Jun 09 12:29:52 PM PDT 24
Peak memory 213224 kb
Host smart-c609ea31-969a-4f40-8fec-72bdceecb4ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904393954 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.2904393954
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.57361867
Short name T78
Test name
Test status
Simulation time 2199107769 ps
CPU time 7.85 seconds
Started Jun 09 12:30:00 PM PDT 24
Finished Jun 09 12:30:09 PM PDT 24
Peak memory 219084 kb
Host smart-96cd8938-1138-48c3-9dd7-4f5169c6a91e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57361867 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.57361867
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.640983684
Short name T319
Test name
Test status
Simulation time 135479813 ps
CPU time 1.5 seconds
Started Jun 09 12:30:00 PM PDT 24
Finished Jun 09 12:30:02 PM PDT 24
Peak memory 212804 kb
Host smart-41b2be13-4fa8-4252-ae63-407c6513e753
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640983684 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.640983684
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.4200566098
Short name T405
Test name
Test status
Simulation time 21627420103 ps
CPU time 38.77 seconds
Started Jun 09 12:29:59 PM PDT 24
Finished Jun 09 12:30:38 PM PDT 24
Peak memory 204996 kb
Host smart-351d4c11-2caf-4b13-994a-6fb60f53e070
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200566098 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.rv_dm_jtag_dmi_csr_bit_bash.4200566098
Directory /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3550195422
Short name T365
Test name
Test status
Simulation time 17623743049 ps
CPU time 27.71 seconds
Started Jun 09 12:29:59 PM PDT 24
Finished Jun 09 12:30:27 PM PDT 24
Peak memory 204956 kb
Host smart-60b8d8a9-6b7f-4806-aeb9-fc160dde2c82
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550195422 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
3550195422
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.3400090527
Short name T363
Test name
Test status
Simulation time 156194174 ps
CPU time 1.03 seconds
Started Jun 09 12:29:59 PM PDT 24
Finished Jun 09 12:30:01 PM PDT 24
Peak memory 204692 kb
Host smart-5680b51d-1eba-45cb-a080-c17023ff54a8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400090527 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
3400090527
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.600418253
Short name T354
Test name
Test status
Simulation time 3281998514 ps
CPU time 8.13 seconds
Started Jun 09 12:29:53 PM PDT 24
Finished Jun 09 12:30:01 PM PDT 24
Peak memory 205088 kb
Host smart-a87750de-dc4c-49cb-9d55-98dec996dd71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600418253 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same_
csr_outstanding.600418253
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3300213079
Short name T123
Test name
Test status
Simulation time 335516959 ps
CPU time 3.46 seconds
Started Jun 09 12:30:00 PM PDT 24
Finished Jun 09 12:30:04 PM PDT 24
Peak memory 213280 kb
Host smart-278a784f-ae09-4717-8cc1-a0065737923f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300213079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.3300213079
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1512073547
Short name T80
Test name
Test status
Simulation time 1132615782 ps
CPU time 3.85 seconds
Started Jun 09 12:29:59 PM PDT 24
Finished Jun 09 12:30:04 PM PDT 24
Peak memory 218268 kb
Host smart-2659699b-c35a-44eb-8a32-e8ff14222575
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512073547 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.1512073547
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.1458013533
Short name T311
Test name
Test status
Simulation time 54159064 ps
CPU time 1.38 seconds
Started Jun 09 12:29:56 PM PDT 24
Finished Jun 09 12:29:58 PM PDT 24
Peak memory 213152 kb
Host smart-034f8bc4-ea4a-4f95-bd30-a229cbeab9c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458013533 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.1458013533
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.300796822
Short name T271
Test name
Test status
Simulation time 44264386253 ps
CPU time 29.22 seconds
Started Jun 09 12:30:07 PM PDT 24
Finished Jun 09 12:30:37 PM PDT 24
Peak memory 204964 kb
Host smart-8448909f-8722-4f78-b8c9-fced154ed9b3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300796822 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
rv_dm_jtag_dmi_csr_bit_bash.300796822
Directory /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.2208665387
Short name T312
Test name
Test status
Simulation time 5039742963 ps
CPU time 9.85 seconds
Started Jun 09 12:30:01 PM PDT 24
Finished Jun 09 12:30:11 PM PDT 24
Peak memory 205024 kb
Host smart-130292c0-c46c-4012-9ac0-424876bf2c6f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208665387 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
2208665387
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3243126242
Short name T293
Test name
Test status
Simulation time 235503886 ps
CPU time 0.77 seconds
Started Jun 09 12:30:08 PM PDT 24
Finished Jun 09 12:30:10 PM PDT 24
Peak memory 204664 kb
Host smart-af78a4d2-c95d-4132-9f5a-91d124b083b2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243126242 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.
3243126242
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.1973747506
Short name T116
Test name
Test status
Simulation time 189778208 ps
CPU time 3.75 seconds
Started Jun 09 12:29:57 PM PDT 24
Finished Jun 09 12:30:01 PM PDT 24
Peak memory 205096 kb
Host smart-eef4d072-61fd-4f5e-8b54-3f1a5294e407
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973747506 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same
_csr_outstanding.1973747506
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1376272369
Short name T396
Test name
Test status
Simulation time 1329288356 ps
CPU time 5.59 seconds
Started Jun 09 12:30:01 PM PDT 24
Finished Jun 09 12:30:07 PM PDT 24
Peak memory 213528 kb
Host smart-36ca8e43-b28f-403b-a4ef-acdb7295c839
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376272369 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.1376272369
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3868258333
Short name T132
Test name
Test status
Simulation time 1571982175 ps
CPU time 9.2 seconds
Started Jun 09 12:29:59 PM PDT 24
Finished Jun 09 12:30:08 PM PDT 24
Peak memory 213252 kb
Host smart-d336226e-487a-4f84-99a4-1d60e27067bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868258333 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.3
868258333
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.3648187563
Short name T362
Test name
Test status
Simulation time 3758775039 ps
CPU time 7.6 seconds
Started Jun 09 12:30:00 PM PDT 24
Finished Jun 09 12:30:08 PM PDT 24
Peak memory 215576 kb
Host smart-dfef803c-7ea3-412d-b997-42e98934f979
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648187563 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.3648187563
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.2366107572
Short name T81
Test name
Test status
Simulation time 140870645 ps
CPU time 2.14 seconds
Started Jun 09 12:30:02 PM PDT 24
Finished Jun 09 12:30:05 PM PDT 24
Peak memory 213216 kb
Host smart-501fdca6-2489-481e-a697-59f28e8f8cfd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366107572 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.2366107572
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.3475648491
Short name T327
Test name
Test status
Simulation time 15361717533 ps
CPU time 13.2 seconds
Started Jun 09 12:30:00 PM PDT 24
Finished Jun 09 12:30:13 PM PDT 24
Peak memory 204928 kb
Host smart-abb95d70-e307-4a11-8300-c483d058eeea
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475648491 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.rv_dm_jtag_dmi_csr_bit_bash.3475648491
Directory /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.76484970
Short name T378
Test name
Test status
Simulation time 2943092822 ps
CPU time 8.99 seconds
Started Jun 09 12:29:59 PM PDT 24
Finished Jun 09 12:30:08 PM PDT 24
Peak memory 204916 kb
Host smart-a37f0ee6-7973-4cda-83d5-4707e821d8a4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76484970 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.76484970
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3132588563
Short name T307
Test name
Test status
Simulation time 683996079 ps
CPU time 0.81 seconds
Started Jun 09 12:30:09 PM PDT 24
Finished Jun 09 12:30:10 PM PDT 24
Peak memory 204712 kb
Host smart-456d2cbf-2d43-470a-92e5-ca14cd8a629d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132588563 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
3132588563
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.2078060461
Short name T104
Test name
Test status
Simulation time 855052661 ps
CPU time 7.54 seconds
Started Jun 09 12:30:01 PM PDT 24
Finished Jun 09 12:30:09 PM PDT 24
Peak memory 205052 kb
Host smart-35da62c6-a7ae-4a55-a3c9-90ca8ee77eba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078060461 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.2078060461
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.2477421234
Short name T389
Test name
Test status
Simulation time 672395602 ps
CPU time 6.06 seconds
Started Jun 09 12:30:03 PM PDT 24
Finished Jun 09 12:30:10 PM PDT 24
Peak memory 213188 kb
Host smart-675f82ec-d8d4-46a9-974e-f0b0b235cbdc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477421234 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.2477421234
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.955585492
Short name T129
Test name
Test status
Simulation time 4006464797 ps
CPU time 24.71 seconds
Started Jun 09 12:30:01 PM PDT 24
Finished Jun 09 12:30:26 PM PDT 24
Peak memory 213356 kb
Host smart-71a0164e-4f69-4e04-ad27-3384deb7f24f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955585492 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.955585492
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.4127130562
Short name T375
Test name
Test status
Simulation time 346255387 ps
CPU time 3.92 seconds
Started Jun 09 12:30:25 PM PDT 24
Finished Jun 09 12:30:30 PM PDT 24
Peak memory 219888 kb
Host smart-e2a51186-ded4-4a30-bce5-c2d05446f7b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127130562 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.4127130562
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.2660905952
Short name T364
Test name
Test status
Simulation time 112221569 ps
CPU time 2.34 seconds
Started Jun 09 12:29:59 PM PDT 24
Finished Jun 09 12:30:02 PM PDT 24
Peak memory 213188 kb
Host smart-c409092c-b7d2-433e-8a86-9a48cfbef77c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660905952 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.2660905952
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.1714649489
Short name T404
Test name
Test status
Simulation time 67650085007 ps
CPU time 56.62 seconds
Started Jun 09 12:29:59 PM PDT 24
Finished Jun 09 12:30:57 PM PDT 24
Peak memory 205016 kb
Host smart-e3cab49f-dc67-49b6-80d4-454ab337c8c2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714649489 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.rv_dm_jtag_dmi_csr_bit_bash.1714649489
Directory /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.438478235
Short name T376
Test name
Test status
Simulation time 5510286066 ps
CPU time 8.31 seconds
Started Jun 09 12:29:59 PM PDT 24
Finished Jun 09 12:30:08 PM PDT 24
Peak memory 205208 kb
Host smart-94eca1b5-1364-4ed3-9450-7dc7e7c43065
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438478235 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.438478235
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2258159225
Short name T351
Test name
Test status
Simulation time 298687808 ps
CPU time 1.09 seconds
Started Jun 09 12:29:58 PM PDT 24
Finished Jun 09 12:29:59 PM PDT 24
Peak memory 204636 kb
Host smart-109515c6-8bd6-4c8a-9f50-4c3bf1fe9767
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258159225 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
2258159225
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.1085868263
Short name T98
Test name
Test status
Simulation time 172455050 ps
CPU time 3.51 seconds
Started Jun 09 12:30:03 PM PDT 24
Finished Jun 09 12:30:07 PM PDT 24
Peak memory 205072 kb
Host smart-17cd1a5e-ba05-44d5-a3ef-70a51549d215
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085868263 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.1085868263
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.843674246
Short name T366
Test name
Test status
Simulation time 287815129 ps
CPU time 2.54 seconds
Started Jun 09 12:29:56 PM PDT 24
Finished Jun 09 12:29:59 PM PDT 24
Peak memory 213300 kb
Host smart-c100b91b-29bd-44d6-8e89-62fd5c925d33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843674246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.843674246
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3598802113
Short name T390
Test name
Test status
Simulation time 5687394802 ps
CPU time 11.96 seconds
Started Jun 09 12:30:07 PM PDT 24
Finished Jun 09 12:30:20 PM PDT 24
Peak memory 213436 kb
Host smart-ff774631-91d0-4513-a462-77f88e512452
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598802113 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.3
598802113
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.4017612730
Short name T399
Test name
Test status
Simulation time 379116480 ps
CPU time 4.26 seconds
Started Jun 09 12:30:11 PM PDT 24
Finished Jun 09 12:30:15 PM PDT 24
Peak memory 221412 kb
Host smart-c46bd918-9fc9-4918-9b5d-422ea987ec4b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017612730 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.4017612730
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.2784355301
Short name T105
Test name
Test status
Simulation time 162626635 ps
CPU time 2.47 seconds
Started Jun 09 12:30:14 PM PDT 24
Finished Jun 09 12:30:18 PM PDT 24
Peak memory 213340 kb
Host smart-3507201a-000f-4571-a1eb-fb8d6105f012
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784355301 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.2784355301
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.371584634
Short name T264
Test name
Test status
Simulation time 15238007429 ps
CPU time 42.67 seconds
Started Jun 09 12:30:25 PM PDT 24
Finished Jun 09 12:31:08 PM PDT 24
Peak memory 205004 kb
Host smart-88c52d35-fdef-47be-8358-620d8df67cef
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371584634 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
rv_dm_jtag_dmi_csr_bit_bash.371584634
Directory /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2646622257
Short name T268
Test name
Test status
Simulation time 2040183740 ps
CPU time 1.26 seconds
Started Jun 09 12:30:12 PM PDT 24
Finished Jun 09 12:30:14 PM PDT 24
Peak memory 204864 kb
Host smart-938cca05-f028-4cdf-aa97-d45cbc1c3d15
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646622257 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
2646622257
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.880987332
Short name T381
Test name
Test status
Simulation time 330205832 ps
CPU time 1.64 seconds
Started Jun 09 12:30:06 PM PDT 24
Finished Jun 09 12:30:08 PM PDT 24
Peak memory 204624 kb
Host smart-c225ac01-80ac-47c6-a06b-55d9a870157e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880987332 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.880987332
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.985439829
Short name T386
Test name
Test status
Simulation time 1150095645 ps
CPU time 5.55 seconds
Started Jun 09 12:30:27 PM PDT 24
Finished Jun 09 12:30:34 PM PDT 24
Peak memory 213232 kb
Host smart-9d04c848-0b49-44f1-8e06-264b26ca8a59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985439829 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.985439829
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3596254024
Short name T374
Test name
Test status
Simulation time 2651583065 ps
CPU time 19.78 seconds
Started Jun 09 12:30:25 PM PDT 24
Finished Jun 09 12:30:46 PM PDT 24
Peak memory 213296 kb
Host smart-97babb85-f959-48c2-b395-0f725c09b2aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596254024 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.3
596254024
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.4101022885
Short name T165
Test name
Test status
Simulation time 403918930 ps
CPU time 2.54 seconds
Started Jun 09 12:30:14 PM PDT 24
Finished Jun 09 12:30:18 PM PDT 24
Peak memory 221412 kb
Host smart-133a0e71-791f-4bdd-aefd-e0a09485dbb9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101022885 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.4101022885
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.958981732
Short name T329
Test name
Test status
Simulation time 75777251 ps
CPU time 1.59 seconds
Started Jun 09 12:30:27 PM PDT 24
Finished Jun 09 12:30:29 PM PDT 24
Peak memory 213136 kb
Host smart-26abe8d0-7397-4093-b9ca-31d64ba1f2bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958981732 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.958981732
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.17080603
Short name T367
Test name
Test status
Simulation time 4495323247 ps
CPU time 13.05 seconds
Started Jun 09 12:30:13 PM PDT 24
Finished Jun 09 12:30:27 PM PDT 24
Peak memory 205212 kb
Host smart-f2c922dd-bb28-4ec5-bbc5-6a37891b2519
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17080603 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.r
v_dm_jtag_dmi_csr_bit_bash.17080603
Directory /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1203347375
Short name T272
Test name
Test status
Simulation time 5234198151 ps
CPU time 8.66 seconds
Started Jun 09 12:30:21 PM PDT 24
Finished Jun 09 12:30:30 PM PDT 24
Peak memory 205020 kb
Host smart-4af28589-5bfc-4f4b-9a79-eee03ca092ce
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203347375 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
1203347375
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.35051291
Short name T265
Test name
Test status
Simulation time 651614780 ps
CPU time 2.44 seconds
Started Jun 09 12:30:12 PM PDT 24
Finished Jun 09 12:30:15 PM PDT 24
Peak memory 204664 kb
Host smart-65e1bf35-87ec-4aab-ae22-3e068f1f94be
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35051291 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.35051291
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.3243086548
Short name T394
Test name
Test status
Simulation time 339324593 ps
CPU time 3.62 seconds
Started Jun 09 12:30:31 PM PDT 24
Finished Jun 09 12:30:35 PM PDT 24
Peak memory 205256 kb
Host smart-5ccdd6c7-f1ea-4a88-beee-bfe5f3198857
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243086548 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.3243086548
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.930532240
Short name T57
Test name
Test status
Simulation time 91053213 ps
CPU time 2.51 seconds
Started Jun 09 12:30:09 PM PDT 24
Finished Jun 09 12:30:12 PM PDT 24
Peak memory 213372 kb
Host smart-a636378c-0d7a-48bc-9e96-ee7c78b42cf9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930532240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.930532240
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2750656388
Short name T124
Test name
Test status
Simulation time 2993032775 ps
CPU time 20 seconds
Started Jun 09 12:30:28 PM PDT 24
Finished Jun 09 12:30:49 PM PDT 24
Peak memory 213284 kb
Host smart-c1ac7dd0-0867-4a7f-b4f6-4a2e894746e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750656388 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.2
750656388
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.3844301683
Short name T358
Test name
Test status
Simulation time 4197369406 ps
CPU time 5.91 seconds
Started Jun 09 12:30:29 PM PDT 24
Finished Jun 09 12:30:36 PM PDT 24
Peak memory 219784 kb
Host smart-48780cee-483d-431b-8f2f-e806503007f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844301683 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.3844301683
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2847937907
Short name T60
Test name
Test status
Simulation time 101932778 ps
CPU time 2.35 seconds
Started Jun 09 12:30:10 PM PDT 24
Finished Jun 09 12:30:13 PM PDT 24
Peak memory 213268 kb
Host smart-e3152ebe-cc6c-4f62-8838-1fe263a90fb0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847937907 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.2847937907
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.2740245240
Short name T340
Test name
Test status
Simulation time 4885683007 ps
CPU time 8.31 seconds
Started Jun 09 12:30:31 PM PDT 24
Finished Jun 09 12:30:40 PM PDT 24
Peak memory 204964 kb
Host smart-b55b1c96-4327-4511-9615-5477c358a9c3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740245240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.rv_dm_jtag_dmi_csr_bit_bash.2740245240
Directory /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.3321791531
Short name T289
Test name
Test status
Simulation time 5140223330 ps
CPU time 13.97 seconds
Started Jun 09 12:30:13 PM PDT 24
Finished Jun 09 12:30:27 PM PDT 24
Peak memory 204980 kb
Host smart-acb9551a-197f-4d4d-aee6-e036ced55cf0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321791531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
3321791531
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2511396747
Short name T285
Test name
Test status
Simulation time 589225611 ps
CPU time 1.4 seconds
Started Jun 09 12:30:13 PM PDT 24
Finished Jun 09 12:30:15 PM PDT 24
Peak memory 204592 kb
Host smart-0991c924-5b99-465e-b8b0-9200c5098100
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511396747 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
2511396747
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1179368296
Short name T350
Test name
Test status
Simulation time 412265228 ps
CPU time 3.85 seconds
Started Jun 09 12:30:24 PM PDT 24
Finished Jun 09 12:30:28 PM PDT 24
Peak memory 204996 kb
Host smart-672941bc-3f89-4115-8396-647be2e6d52e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179368296 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.1179368296
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3541731288
Short name T324
Test name
Test status
Simulation time 875801634 ps
CPU time 3.99 seconds
Started Jun 09 12:30:28 PM PDT 24
Finished Jun 09 12:30:34 PM PDT 24
Peak memory 213192 kb
Host smart-02beb9ea-6d65-4895-a933-7e6f2f4cbb48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541731288 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.3541731288
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.2719133783
Short name T288
Test name
Test status
Simulation time 14006687724 ps
CPU time 20.24 seconds
Started Jun 09 12:30:24 PM PDT 24
Finished Jun 09 12:30:45 PM PDT 24
Peak memory 213384 kb
Host smart-08f35779-0489-464a-9b92-43a35c70a926
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719133783 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.2
719133783
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.3759929066
Short name T360
Test name
Test status
Simulation time 3529586931 ps
CPU time 7.26 seconds
Started Jun 09 12:30:35 PM PDT 24
Finished Jun 09 12:30:43 PM PDT 24
Peak memory 220360 kb
Host smart-999f6a14-577d-46c6-a8f6-93ced71f492a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759929066 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.3759929066
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.2839355708
Short name T315
Test name
Test status
Simulation time 667968501 ps
CPU time 2.15 seconds
Started Jun 09 12:30:38 PM PDT 24
Finished Jun 09 12:30:41 PM PDT 24
Peak memory 213256 kb
Host smart-dfcabef1-a634-42ed-972a-c097a0f5a393
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839355708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.2839355708
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.1362241538
Short name T300
Test name
Test status
Simulation time 9119810390 ps
CPU time 19.43 seconds
Started Jun 09 12:30:26 PM PDT 24
Finished Jun 09 12:30:46 PM PDT 24
Peak memory 205020 kb
Host smart-9b20eece-f518-4de9-849f-392774d95208
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362241538 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.rv_dm_jtag_dmi_csr_bit_bash.1362241538
Directory /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2050422576
Short name T278
Test name
Test status
Simulation time 3227210911 ps
CPU time 2.19 seconds
Started Jun 09 12:30:20 PM PDT 24
Finished Jun 09 12:30:23 PM PDT 24
Peak memory 204928 kb
Host smart-d43a4473-70ef-48c1-bcb5-0dcbc130a758
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050422576 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
2050422576
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.183854301
Short name T273
Test name
Test status
Simulation time 296028324 ps
CPU time 1.41 seconds
Started Jun 09 12:30:10 PM PDT 24
Finished Jun 09 12:30:12 PM PDT 24
Peak memory 204664 kb
Host smart-f635feec-484b-4c9c-b6e9-60e2617a577f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183854301 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.183854301
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2051617036
Short name T384
Test name
Test status
Simulation time 880324958 ps
CPU time 6.29 seconds
Started Jun 09 12:30:17 PM PDT 24
Finished Jun 09 12:30:24 PM PDT 24
Peak memory 205036 kb
Host smart-592d391c-b76d-4b7c-8d72-a35595dcb700
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051617036 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.2051617036
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.3226665693
Short name T402
Test name
Test status
Simulation time 1654434807 ps
CPU time 3.23 seconds
Started Jun 09 12:30:18 PM PDT 24
Finished Jun 09 12:30:22 PM PDT 24
Peak memory 213192 kb
Host smart-c0fa8228-cdde-4b72-8241-f5e4c3776b24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226665693 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.3226665693
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2866424168
Short name T331
Test name
Test status
Simulation time 1332058598 ps
CPU time 6.86 seconds
Started Jun 09 12:30:19 PM PDT 24
Finished Jun 09 12:30:26 PM PDT 24
Peak memory 219636 kb
Host smart-ea16e14f-8227-4614-b49d-07b08729fc57
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866424168 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.2866424168
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2333045295
Short name T385
Test name
Test status
Simulation time 47396757 ps
CPU time 1.46 seconds
Started Jun 09 12:30:21 PM PDT 24
Finished Jun 09 12:30:23 PM PDT 24
Peak memory 213200 kb
Host smart-aafc49e2-f969-460f-9b2a-b9db29c1b499
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333045295 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.2333045295
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.253935475
Short name T406
Test name
Test status
Simulation time 18844757813 ps
CPU time 17.32 seconds
Started Jun 09 12:30:14 PM PDT 24
Finished Jun 09 12:30:32 PM PDT 24
Peak memory 204948 kb
Host smart-e09b1de1-4fe5-4e2f-bb9e-9795a3305884
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253935475 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
rv_dm_jtag_dmi_csr_bit_bash.253935475
Directory /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2641025324
Short name T379
Test name
Test status
Simulation time 12138863165 ps
CPU time 9.39 seconds
Started Jun 09 12:30:36 PM PDT 24
Finished Jun 09 12:30:46 PM PDT 24
Peak memory 204992 kb
Host smart-4ad67c77-6d1e-4021-b958-a7008a98e850
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641025324 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
2641025324
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.3781377280
Short name T392
Test name
Test status
Simulation time 288877870 ps
CPU time 1.42 seconds
Started Jun 09 12:30:33 PM PDT 24
Finished Jun 09 12:30:35 PM PDT 24
Peak memory 204708 kb
Host smart-eaac234d-4fce-4f29-9b75-79a400013a19
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781377280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
3781377280
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3274765995
Short name T106
Test name
Test status
Simulation time 102432210 ps
CPU time 3.79 seconds
Started Jun 09 12:30:32 PM PDT 24
Finished Jun 09 12:30:37 PM PDT 24
Peak memory 205272 kb
Host smart-f6e66616-e2ad-40d3-9ff1-21359407a559
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274765995 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.3274765995
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2332544895
Short name T291
Test name
Test status
Simulation time 270317337 ps
CPU time 6.13 seconds
Started Jun 09 12:30:26 PM PDT 24
Finished Jun 09 12:30:33 PM PDT 24
Peak memory 213316 kb
Host smart-fb67d83c-9fed-44c8-8c35-e63d33f6b7c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332544895 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.2332544895
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3756712218
Short name T77
Test name
Test status
Simulation time 2909005572 ps
CPU time 9.97 seconds
Started Jun 09 12:30:33 PM PDT 24
Finished Jun 09 12:30:43 PM PDT 24
Peak memory 213316 kb
Host smart-7b515e0f-e61b-4944-9637-abbb95646fbd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756712218 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.3
756712218
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.254756115
Short name T338
Test name
Test status
Simulation time 203286307 ps
CPU time 2.5 seconds
Started Jun 09 12:30:21 PM PDT 24
Finished Jun 09 12:30:24 PM PDT 24
Peak memory 218852 kb
Host smart-3f40bad5-416b-48d4-ac10-d6be143ce016
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254756115 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.254756115
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.893288298
Short name T359
Test name
Test status
Simulation time 66080827 ps
CPU time 1.49 seconds
Started Jun 09 12:30:22 PM PDT 24
Finished Jun 09 12:30:24 PM PDT 24
Peak memory 213244 kb
Host smart-ad248c31-535b-4601-995e-0dd22c9d86f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893288298 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.893288298
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.75065170
Short name T274
Test name
Test status
Simulation time 83305856375 ps
CPU time 84.3 seconds
Started Jun 09 12:30:25 PM PDT 24
Finished Jun 09 12:31:50 PM PDT 24
Peak memory 204936 kb
Host smart-7452d5d2-e203-4b13-8f39-ce4d58419024
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75065170 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.r
v_dm_jtag_dmi_csr_bit_bash.75065170
Directory /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.4230447467
Short name T348
Test name
Test status
Simulation time 17483668161 ps
CPU time 10.8 seconds
Started Jun 09 12:30:33 PM PDT 24
Finished Jun 09 12:30:45 PM PDT 24
Peak memory 204976 kb
Host smart-7d369b0f-7ea8-4e91-a6ca-5e829699d001
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230447467 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
4230447467
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3490076575
Short name T287
Test name
Test status
Simulation time 290455730 ps
CPU time 0.87 seconds
Started Jun 09 12:30:25 PM PDT 24
Finished Jun 09 12:30:27 PM PDT 24
Peak memory 204628 kb
Host smart-a8ccd6c9-9c44-4070-b13c-b79edbae6942
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490076575 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
3490076575
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1976813322
Short name T114
Test name
Test status
Simulation time 454169045 ps
CPU time 7.52 seconds
Started Jun 09 12:30:09 PM PDT 24
Finished Jun 09 12:30:17 PM PDT 24
Peak memory 204992 kb
Host smart-170cc844-49f8-41c1-973b-ee652eb8fedf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976813322 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.1976813322
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3629798577
Short name T290
Test name
Test status
Simulation time 146643258 ps
CPU time 5 seconds
Started Jun 09 12:30:17 PM PDT 24
Finished Jun 09 12:30:22 PM PDT 24
Peak memory 213248 kb
Host smart-ddd0a5d8-e256-4715-9bf3-fa34b364cfe1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629798577 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.3629798577
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.4223418126
Short name T134
Test name
Test status
Simulation time 4652910317 ps
CPU time 11.53 seconds
Started Jun 09 12:30:39 PM PDT 24
Finished Jun 09 12:30:51 PM PDT 24
Peak memory 213376 kb
Host smart-4ef5f222-f575-4f9b-a699-021455e3cc55
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223418126 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.4
223418126
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.3879988429
Short name T85
Test name
Test status
Simulation time 1439964715 ps
CPU time 57.53 seconds
Started Jun 09 12:29:47 PM PDT 24
Finished Jun 09 12:30:45 PM PDT 24
Peak memory 205116 kb
Host smart-c195530a-f0ba-4bc9-9162-64a1e61224bd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879988429 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.3879988429
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.1495548863
Short name T407
Test name
Test status
Simulation time 100757208 ps
CPU time 1.49 seconds
Started Jun 09 12:29:35 PM PDT 24
Finished Jun 09 12:29:37 PM PDT 24
Peak memory 213168 kb
Host smart-2322251f-ad16-4b03-b64f-d0976d1ffc0d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495548863 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.1495548863
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.1826363092
Short name T335
Test name
Test status
Simulation time 1324917671 ps
CPU time 3.1 seconds
Started Jun 09 12:29:37 PM PDT 24
Finished Jun 09 12:29:41 PM PDT 24
Peak memory 219088 kb
Host smart-7f4a32b2-e7a2-4acd-b8e7-605205d8177d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826363092 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.1826363092
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3954615655
Short name T393
Test name
Test status
Simulation time 254758544 ps
CPU time 1.53 seconds
Started Jun 09 12:29:47 PM PDT 24
Finished Jun 09 12:29:49 PM PDT 24
Peak memory 213136 kb
Host smart-6a7015f8-25f7-4a26-98db-11a5871c0137
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954615655 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.3954615655
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.170988728
Short name T301
Test name
Test status
Simulation time 85129301024 ps
CPU time 64.43 seconds
Started Jun 09 12:29:36 PM PDT 24
Finished Jun 09 12:30:41 PM PDT 24
Peak memory 204912 kb
Host smart-4630089a-a6d5-40df-a9cb-5cd635ca6682
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170988728 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr
_aliasing.170988728
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.827457931
Short name T345
Test name
Test status
Simulation time 7377792126 ps
CPU time 13.57 seconds
Started Jun 09 12:29:48 PM PDT 24
Finished Jun 09 12:30:02 PM PDT 24
Peak memory 204944 kb
Host smart-d611c79a-e4ea-4b29-83b7-4ae879328a02
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827457931 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.r
v_dm_jtag_dmi_csr_bit_bash.827457931
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.3368827373
Short name T93
Test name
Test status
Simulation time 4662447621 ps
CPU time 4.38 seconds
Started Jun 09 12:29:44 PM PDT 24
Finished Jun 09 12:29:49 PM PDT 24
Peak memory 205056 kb
Host smart-75b7598d-f8cd-4aee-9ee0-94a5fab4cd36
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368827373 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.3368827373
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.3593343490
Short name T276
Test name
Test status
Simulation time 5834320426 ps
CPU time 8.43 seconds
Started Jun 09 12:29:43 PM PDT 24
Finished Jun 09 12:29:52 PM PDT 24
Peak memory 205052 kb
Host smart-9482c1fe-4179-4f07-b18f-31b6332269f6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593343490 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.3
593343490
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.111093472
Short name T306
Test name
Test status
Simulation time 602229821 ps
CPU time 2.31 seconds
Started Jun 09 12:29:39 PM PDT 24
Finished Jun 09 12:29:41 PM PDT 24
Peak memory 204652 kb
Host smart-69c5f9d7-f391-459e-8897-cee15b3da097
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111093472 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_aliasing.111093472
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1777658597
Short name T398
Test name
Test status
Simulation time 27376690654 ps
CPU time 39.05 seconds
Started Jun 09 12:29:34 PM PDT 24
Finished Jun 09 12:30:14 PM PDT 24
Peak memory 204916 kb
Host smart-51a60389-5329-4f7b-9bf6-1898b68f5bb8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777658597 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.1777658597
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3416946082
Short name T328
Test name
Test status
Simulation time 143773838 ps
CPU time 0.72 seconds
Started Jun 09 12:29:36 PM PDT 24
Finished Jun 09 12:29:37 PM PDT 24
Peak memory 204672 kb
Host smart-cc74431e-c516-4474-b65b-12bbd3e66323
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416946082 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.3416946082
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.3344307648
Short name T353
Test name
Test status
Simulation time 186327237 ps
CPU time 0.84 seconds
Started Jun 09 12:29:48 PM PDT 24
Finished Jun 09 12:29:49 PM PDT 24
Peak memory 204688 kb
Host smart-76c02e8e-788d-4670-8a4f-0eaf0278ac06
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344307648 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.3
344307648
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2361984632
Short name T403
Test name
Test status
Simulation time 83707819 ps
CPU time 0.78 seconds
Started Jun 09 12:29:47 PM PDT 24
Finished Jun 09 12:29:49 PM PDT 24
Peak memory 204548 kb
Host smart-8853ae5f-ea62-4dd3-a098-9f2ff689e077
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361984632 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.2361984632
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.98983481
Short name T299
Test name
Test status
Simulation time 115736946 ps
CPU time 0.67 seconds
Started Jun 09 12:29:45 PM PDT 24
Finished Jun 09 12:29:46 PM PDT 24
Peak memory 204612 kb
Host smart-19687bde-b655-42b4-a4b4-b051266e2896
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98983481 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.98983481
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3211974883
Short name T321
Test name
Test status
Simulation time 184176637 ps
CPU time 6.36 seconds
Started Jun 09 12:29:43 PM PDT 24
Finished Jun 09 12:29:50 PM PDT 24
Peak memory 205028 kb
Host smart-e7a3bf5f-d21d-4076-87bd-31e76cda86da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211974883 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.3211974883
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.4024383409
Short name T336
Test name
Test status
Simulation time 66606283623 ps
CPU time 57.01 seconds
Started Jun 09 12:29:41 PM PDT 24
Finished Jun 09 12:30:39 PM PDT 24
Peak memory 221484 kb
Host smart-9f1bb2a1-f74f-4a7b-a7b0-fa9f72d6e6b3
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024383409 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.4024383409
Directory /workspace/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.1385671300
Short name T337
Test name
Test status
Simulation time 763883575 ps
CPU time 4.82 seconds
Started Jun 09 12:29:44 PM PDT 24
Finished Jun 09 12:29:49 PM PDT 24
Peak memory 213188 kb
Host smart-76686bba-f32e-433a-8323-428c137276f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385671300 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.1385671300
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2196707199
Short name T131
Test name
Test status
Simulation time 1193748486 ps
CPU time 8.15 seconds
Started Jun 09 12:29:47 PM PDT 24
Finished Jun 09 12:29:56 PM PDT 24
Peak memory 213276 kb
Host smart-e72ae981-ce26-4b6d-962d-f5daf0da30a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196707199 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.2196707199
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2304072083
Short name T112
Test name
Test status
Simulation time 2271601038 ps
CPU time 68.48 seconds
Started Jun 09 12:29:48 PM PDT 24
Finished Jun 09 12:30:57 PM PDT 24
Peak memory 213336 kb
Host smart-bbc5fa10-3c10-4882-ab03-9c0e736199a8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304072083 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.2304072083
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.129724738
Short name T346
Test name
Test status
Simulation time 7593564663 ps
CPU time 76.53 seconds
Started Jun 09 12:29:47 PM PDT 24
Finished Jun 09 12:31:05 PM PDT 24
Peak memory 213360 kb
Host smart-144441e8-9590-45ee-a508-2e51a512d1b1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129724738 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.129724738
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.3067450750
Short name T382
Test name
Test status
Simulation time 75481856 ps
CPU time 1.49 seconds
Started Jun 09 12:29:39 PM PDT 24
Finished Jun 09 12:29:41 PM PDT 24
Peak memory 213332 kb
Host smart-3b68c05f-1458-4c38-acd6-b8bc0385d3c9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067450750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.3067450750
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.4246028352
Short name T322
Test name
Test status
Simulation time 2965631519 ps
CPU time 4.46 seconds
Started Jun 09 12:29:46 PM PDT 24
Finished Jun 09 12:29:50 PM PDT 24
Peak memory 218988 kb
Host smart-dc368fe9-0809-4b7f-a5c8-e4d05ee89315
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246028352 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.4246028352
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.118350122
Short name T110
Test name
Test status
Simulation time 87544875 ps
CPU time 2.28 seconds
Started Jun 09 12:29:47 PM PDT 24
Finished Jun 09 12:29:50 PM PDT 24
Peak memory 213216 kb
Host smart-3ed2d05e-bd99-4dbf-9518-1ce9a746862b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118350122 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.118350122
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.318291894
Short name T266
Test name
Test status
Simulation time 67352288178 ps
CPU time 63.43 seconds
Started Jun 09 12:29:37 PM PDT 24
Finished Jun 09 12:30:41 PM PDT 24
Peak memory 204964 kb
Host smart-5380b1bf-64e8-4382-bc82-64eb25a8186a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318291894 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr
_aliasing.318291894
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.2522132706
Short name T298
Test name
Test status
Simulation time 5462892237 ps
CPU time 14.91 seconds
Started Jun 09 12:29:46 PM PDT 24
Finished Jun 09 12:30:02 PM PDT 24
Peak memory 204944 kb
Host smart-81815b48-b0cb-4cc0-af41-5b800a673cdd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522132706 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
rv_dm_jtag_dmi_csr_bit_bash.2522132706
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2391951205
Short name T96
Test name
Test status
Simulation time 3672885337 ps
CPU time 5.81 seconds
Started Jun 09 12:29:40 PM PDT 24
Finished Jun 09 12:29:46 PM PDT 24
Peak memory 205008 kb
Host smart-1ef29d2f-867c-4002-8d54-19278684dcbc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391951205 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.2391951205
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3243141457
Short name T270
Test name
Test status
Simulation time 2891849616 ps
CPU time 2.59 seconds
Started Jun 09 12:29:45 PM PDT 24
Finished Jun 09 12:29:48 PM PDT 24
Peak memory 204924 kb
Host smart-8a08f5b3-37a4-4ba7-94d3-45a00e35990a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243141457 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.3
243141457
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.2939370666
Short name T303
Test name
Test status
Simulation time 770693267 ps
CPU time 1.15 seconds
Started Jun 09 12:29:46 PM PDT 24
Finished Jun 09 12:29:48 PM PDT 24
Peak memory 204616 kb
Host smart-a46d3636-3095-4e47-a9bd-c8a7e339ee77
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939370666 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.2939370666
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2779429655
Short name T356
Test name
Test status
Simulation time 6291478548 ps
CPU time 6.06 seconds
Started Jun 09 12:29:53 PM PDT 24
Finished Jun 09 12:29:59 PM PDT 24
Peak memory 204924 kb
Host smart-fc17a4f0-808e-4022-9900-ef21cc666932
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779429655 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.2779429655
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.4280896414
Short name T334
Test name
Test status
Simulation time 686696694 ps
CPU time 2.49 seconds
Started Jun 09 12:29:45 PM PDT 24
Finished Jun 09 12:29:48 PM PDT 24
Peak memory 204676 kb
Host smart-a6637bd7-a2b1-4eb5-889d-875be89ca2a9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280896414 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.4280896414
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.3418470
Short name T69
Test name
Test status
Simulation time 1121409190 ps
CPU time 3.44 seconds
Started Jun 09 12:29:47 PM PDT 24
Finished Jun 09 12:29:52 PM PDT 24
Peak memory 204672 kb
Host smart-9b71683a-e42d-4271-927c-2a082df0fc74
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418470 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.3418470
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.4001387460
Short name T305
Test name
Test status
Simulation time 75397565 ps
CPU time 0.68 seconds
Started Jun 09 12:29:41 PM PDT 24
Finished Jun 09 12:29:42 PM PDT 24
Peak memory 204556 kb
Host smart-46c19943-727d-410c-be42-0270ea60d23e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001387460 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.4001387460
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.724077088
Short name T323
Test name
Test status
Simulation time 77562083 ps
CPU time 0.67 seconds
Started Jun 09 12:29:46 PM PDT 24
Finished Jun 09 12:29:47 PM PDT 24
Peak memory 204652 kb
Host smart-5c6fe9ec-2e45-4a0b-8403-947246178ffb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724077088 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.724077088
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.4235989742
Short name T408
Test name
Test status
Simulation time 206524234 ps
CPU time 6.73 seconds
Started Jun 09 12:29:45 PM PDT 24
Finished Jun 09 12:29:52 PM PDT 24
Peak memory 205056 kb
Host smart-41da2fe8-2243-44c8-9f26-8d2642743d48
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235989742 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.4235989742
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.2173819371
Short name T347
Test name
Test status
Simulation time 30217165445 ps
CPU time 47.42 seconds
Started Jun 09 12:29:44 PM PDT 24
Finished Jun 09 12:30:31 PM PDT 24
Peak memory 221544 kb
Host smart-721b691e-608f-4987-a308-865730aa0105
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173819371 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.2173819371
Directory /workspace/3.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2368774979
Short name T89
Test name
Test status
Simulation time 137118258 ps
CPU time 2.8 seconds
Started Jun 09 12:29:37 PM PDT 24
Finished Jun 09 12:29:40 PM PDT 24
Peak memory 213268 kb
Host smart-3938d352-e040-44d9-b553-dee4ebcdb9db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368774979 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.2368774979
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.298400582
Short name T126
Test name
Test status
Simulation time 3386380898 ps
CPU time 11.24 seconds
Started Jun 09 12:29:47 PM PDT 24
Finished Jun 09 12:29:59 PM PDT 24
Peak memory 213392 kb
Host smart-8b1d6ce2-7206-47d3-bd41-9e7e67c3e735
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298400582 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.298400582
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.3914979565
Short name T82
Test name
Test status
Simulation time 1148016322 ps
CPU time 67.68 seconds
Started Jun 09 12:29:45 PM PDT 24
Finished Jun 09 12:30:53 PM PDT 24
Peak memory 213572 kb
Host smart-1b75ed51-1901-4f99-a2d7-7ea88ba4832f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914979565 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.3914979565
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.486012847
Short name T108
Test name
Test status
Simulation time 2658317307 ps
CPU time 54.05 seconds
Started Jun 09 12:29:50 PM PDT 24
Finished Jun 09 12:30:44 PM PDT 24
Peak memory 213284 kb
Host smart-11b79b9d-8b76-481e-b730-ab599067bd69
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486012847 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.486012847
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.3086428312
Short name T107
Test name
Test status
Simulation time 719329411 ps
CPU time 2.43 seconds
Started Jun 09 12:29:43 PM PDT 24
Finished Jun 09 12:29:46 PM PDT 24
Peak memory 213272 kb
Host smart-1ef601fe-1bf1-49e3-8308-f4dad657ed0d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086428312 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.3086428312
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.739925131
Short name T310
Test name
Test status
Simulation time 1889196963 ps
CPU time 4.33 seconds
Started Jun 09 12:29:47 PM PDT 24
Finished Jun 09 12:29:52 PM PDT 24
Peak memory 221496 kb
Host smart-95bde2f9-0fc5-434c-85e3-1f5044dcfe2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739925131 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.739925131
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.1896059931
Short name T100
Test name
Test status
Simulation time 81531737 ps
CPU time 1.67 seconds
Started Jun 09 12:29:49 PM PDT 24
Finished Jun 09 12:29:51 PM PDT 24
Peak memory 213224 kb
Host smart-8c992508-d88b-485e-837b-421aa230f0c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896059931 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.1896059931
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3806244632
Short name T275
Test name
Test status
Simulation time 27776217274 ps
CPU time 44.34 seconds
Started Jun 09 12:29:47 PM PDT 24
Finished Jun 09 12:30:32 PM PDT 24
Peak memory 204948 kb
Host smart-cf871ae0-77b6-4e12-b18f-b3a8909170b1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806244632 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
rv_dm_jtag_dmi_csr_bit_bash.3806244632
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.502346451
Short name T94
Test name
Test status
Simulation time 20538045063 ps
CPU time 5.17 seconds
Started Jun 09 12:29:48 PM PDT 24
Finished Jun 09 12:29:54 PM PDT 24
Peak memory 205060 kb
Host smart-2d579231-a92e-492c-b7e3-b9a78d036f2a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502346451 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr
_hw_reset.502346451
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.1227834551
Short name T308
Test name
Test status
Simulation time 1413254560 ps
CPU time 3.21 seconds
Started Jun 09 12:29:49 PM PDT 24
Finished Jun 09 12:29:52 PM PDT 24
Peak memory 204828 kb
Host smart-7cde74d4-f6bd-4ff2-be04-950b6b07a5ed
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227834551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.1
227834551
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.3231900022
Short name T292
Test name
Test status
Simulation time 353180776 ps
CPU time 1.58 seconds
Started Jun 09 12:29:44 PM PDT 24
Finished Jun 09 12:29:46 PM PDT 24
Peak memory 204616 kb
Host smart-e343a0d0-1bd3-452c-ad9f-d87375c97ab8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231900022 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.3231900022
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.3798986879
Short name T370
Test name
Test status
Simulation time 61477056305 ps
CPU time 47.97 seconds
Started Jun 09 12:29:42 PM PDT 24
Finished Jun 09 12:30:31 PM PDT 24
Peak memory 204944 kb
Host smart-8a96baaa-df33-474a-baef-828a3cbaf551
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798986879 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.3798986879
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2828860130
Short name T269
Test name
Test status
Simulation time 396212427 ps
CPU time 1.76 seconds
Started Jun 09 12:29:43 PM PDT 24
Finished Jun 09 12:29:45 PM PDT 24
Peak memory 204684 kb
Host smart-0fe624fb-e0a4-40f9-8848-e5519f8fc16f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828860130 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.2828860130
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2124883956
Short name T267
Test name
Test status
Simulation time 230356368 ps
CPU time 1.22 seconds
Started Jun 09 12:29:39 PM PDT 24
Finished Jun 09 12:29:40 PM PDT 24
Peak memory 204636 kb
Host smart-8015aa6a-7b25-49b7-ada6-54cfa7732a46
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124883956 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.2
124883956
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.2206361185
Short name T309
Test name
Test status
Simulation time 80173762 ps
CPU time 0.72 seconds
Started Jun 09 12:29:50 PM PDT 24
Finished Jun 09 12:29:51 PM PDT 24
Peak memory 204552 kb
Host smart-ed07d02f-da6f-424e-a83f-d14ef84fabb8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206361185 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.2206361185
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.2734985614
Short name T277
Test name
Test status
Simulation time 43826338 ps
CPU time 0.75 seconds
Started Jun 09 12:29:46 PM PDT 24
Finished Jun 09 12:29:48 PM PDT 24
Peak memory 204540 kb
Host smart-8da780af-24ba-430e-b912-5f7a837ab3b4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734985614 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.2734985614
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3684732476
Short name T361
Test name
Test status
Simulation time 348428119 ps
CPU time 6.48 seconds
Started Jun 09 12:29:53 PM PDT 24
Finished Jun 09 12:30:00 PM PDT 24
Peak memory 205032 kb
Host smart-1b688f7f-580a-48ff-a527-d873d63e71a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684732476 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.3684732476
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.3080155599
Short name T135
Test name
Test status
Simulation time 33935094297 ps
CPU time 29.2 seconds
Started Jun 09 12:29:39 PM PDT 24
Finished Jun 09 12:30:08 PM PDT 24
Peak memory 221540 kb
Host smart-13218ec6-c19a-4245-927a-184beef3640f
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080155599 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.3080155599
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2500002077
Short name T162
Test name
Test status
Simulation time 100517229 ps
CPU time 5.32 seconds
Started Jun 09 12:29:50 PM PDT 24
Finished Jun 09 12:29:56 PM PDT 24
Peak memory 213284 kb
Host smart-b62a61f2-53f1-4160-9107-fa18c2611cba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500002077 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.2500002077
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.2023157190
Short name T333
Test name
Test status
Simulation time 1560967834 ps
CPU time 10.12 seconds
Started Jun 09 12:29:47 PM PDT 24
Finished Jun 09 12:29:58 PM PDT 24
Peak memory 213240 kb
Host smart-4d1b52cd-9835-4b04-ab5b-0158ed0e4c77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023157190 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.2023157190
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.2251018150
Short name T371
Test name
Test status
Simulation time 4087918544 ps
CPU time 8.5 seconds
Started Jun 09 12:29:59 PM PDT 24
Finished Jun 09 12:30:12 PM PDT 24
Peak memory 213356 kb
Host smart-46d8efae-d678-43f0-91b2-9cc48ff72867
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251018150 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.2251018150
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.1550116455
Short name T59
Test name
Test status
Simulation time 150681846 ps
CPU time 2.33 seconds
Started Jun 09 12:29:44 PM PDT 24
Finished Jun 09 12:29:47 PM PDT 24
Peak memory 213172 kb
Host smart-7d6416d1-4f1c-44cb-bd8e-63b53afca6e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550116455 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.1550116455
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.688592015
Short name T380
Test name
Test status
Simulation time 91492134243 ps
CPU time 128.63 seconds
Started Jun 09 12:29:46 PM PDT 24
Finished Jun 09 12:31:55 PM PDT 24
Peak memory 204948 kb
Host smart-75499cfc-0203-40f2-9b07-cb6a7d71f6c4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688592015 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.r
v_dm_jtag_dmi_csr_bit_bash.688592015
Directory /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.291955792
Short name T397
Test name
Test status
Simulation time 3737578975 ps
CPU time 11.01 seconds
Started Jun 09 12:29:42 PM PDT 24
Finished Jun 09 12:29:54 PM PDT 24
Peak memory 204944 kb
Host smart-75b5c320-524c-41f8-94ac-c13495e8171c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291955792 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.291955792
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.1279850420
Short name T326
Test name
Test status
Simulation time 1360338477 ps
CPU time 1.47 seconds
Started Jun 09 12:29:54 PM PDT 24
Finished Jun 09 12:29:56 PM PDT 24
Peak memory 204660 kb
Host smart-c0e7b40c-c4c9-4623-8754-aafb785c902e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279850420 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.1
279850420
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.2174196966
Short name T117
Test name
Test status
Simulation time 664070239 ps
CPU time 6.57 seconds
Started Jun 09 12:29:49 PM PDT 24
Finished Jun 09 12:29:56 PM PDT 24
Peak memory 205028 kb
Host smart-0fb140c1-5545-4bde-a7a5-6133617b849a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174196966 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.2174196966
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.1227727070
Short name T316
Test name
Test status
Simulation time 1173008859 ps
CPU time 4.97 seconds
Started Jun 09 12:29:45 PM PDT 24
Finished Jun 09 12:29:50 PM PDT 24
Peak memory 213240 kb
Host smart-6a32a11b-b215-4c73-989e-740f83f20019
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227727070 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.1227727070
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2183679180
Short name T130
Test name
Test status
Simulation time 2254571443 ps
CPU time 8.99 seconds
Started Jun 09 12:29:46 PM PDT 24
Finished Jun 09 12:29:56 PM PDT 24
Peak memory 213380 kb
Host smart-f2d402e8-bd47-4e98-a67f-9b8956d0d330
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183679180 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.2183679180
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2964818310
Short name T369
Test name
Test status
Simulation time 107108919 ps
CPU time 2.55 seconds
Started Jun 09 12:30:00 PM PDT 24
Finished Jun 09 12:30:03 PM PDT 24
Peak memory 218716 kb
Host smart-f47e958b-71f7-4553-8183-4bbd623b5d4b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964818310 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.2964818310
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.4222982004
Short name T339
Test name
Test status
Simulation time 131031692 ps
CPU time 1.65 seconds
Started Jun 09 12:29:55 PM PDT 24
Finished Jun 09 12:29:57 PM PDT 24
Peak memory 213216 kb
Host smart-5655a847-ed87-4566-ab72-8658ca396cbc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222982004 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.4222982004
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.4123029089
Short name T283
Test name
Test status
Simulation time 54915733320 ps
CPU time 99.62 seconds
Started Jun 09 12:29:52 PM PDT 24
Finished Jun 09 12:31:32 PM PDT 24
Peak memory 204948 kb
Host smart-d17518c2-c9d9-4963-97b7-7d835307afc4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123029089 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
rv_dm_jtag_dmi_csr_bit_bash.4123029089
Directory /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.438508132
Short name T282
Test name
Test status
Simulation time 6444823681 ps
CPU time 4.14 seconds
Started Jun 09 12:29:47 PM PDT 24
Finished Jun 09 12:29:52 PM PDT 24
Peak memory 204952 kb
Host smart-d7e9e843-f768-4dc7-b1a6-70da709780ee
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438508132 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.438508132
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.1347608673
Short name T314
Test name
Test status
Simulation time 332156383 ps
CPU time 1.08 seconds
Started Jun 09 12:29:47 PM PDT 24
Finished Jun 09 12:29:49 PM PDT 24
Peak memory 204660 kb
Host smart-48e359f5-7406-47da-92a2-1f1d1c3cbeab
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347608673 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.1
347608673
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.1877241471
Short name T103
Test name
Test status
Simulation time 547956903 ps
CPU time 3.73 seconds
Started Jun 09 12:29:50 PM PDT 24
Finished Jun 09 12:29:54 PM PDT 24
Peak memory 205084 kb
Host smart-fbd0e188-ddc0-47a1-9128-db50ad3275f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877241471 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.1877241471
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.3562197665
Short name T332
Test name
Test status
Simulation time 150225032 ps
CPU time 2.08 seconds
Started Jun 09 12:29:49 PM PDT 24
Finished Jun 09 12:29:51 PM PDT 24
Peak memory 213228 kb
Host smart-f05024ac-56c0-457a-847a-a579766058ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562197665 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.3562197665
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3819166025
Short name T147
Test name
Test status
Simulation time 292529962 ps
CPU time 4.17 seconds
Started Jun 09 12:29:52 PM PDT 24
Finished Jun 09 12:29:57 PM PDT 24
Peak memory 219412 kb
Host smart-ad836989-fd83-411f-935a-15685d07632d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819166025 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.3819166025
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.2084127243
Short name T400
Test name
Test status
Simulation time 64116931 ps
CPU time 1.6 seconds
Started Jun 09 12:29:53 PM PDT 24
Finished Jun 09 12:29:55 PM PDT 24
Peak memory 213240 kb
Host smart-c482c123-5801-47eb-b59a-f0f679c91d19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084127243 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.2084127243
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.3568260360
Short name T388
Test name
Test status
Simulation time 17294534069 ps
CPU time 19.87 seconds
Started Jun 09 12:29:59 PM PDT 24
Finished Jun 09 12:30:19 PM PDT 24
Peak memory 204948 kb
Host smart-b409eac0-06b9-465a-9a92-0a66fb705046
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568260360 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
rv_dm_jtag_dmi_csr_bit_bash.3568260360
Directory /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.1826329750
Short name T279
Test name
Test status
Simulation time 1884505537 ps
CPU time 1.85 seconds
Started Jun 09 12:29:52 PM PDT 24
Finished Jun 09 12:29:54 PM PDT 24
Peak memory 204880 kb
Host smart-4e00af46-f696-44e5-977f-3a2ff9965b42
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826329750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.1
826329750
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1563416415
Short name T302
Test name
Test status
Simulation time 358203135 ps
CPU time 1.19 seconds
Started Jun 09 12:29:57 PM PDT 24
Finished Jun 09 12:29:59 PM PDT 24
Peak memory 204664 kb
Host smart-a1d4a2c6-de75-4259-a6bb-1020b8765949
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563416415 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.1
563416415
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.1815224982
Short name T355
Test name
Test status
Simulation time 1579608845 ps
CPU time 7.68 seconds
Started Jun 09 12:29:51 PM PDT 24
Finished Jun 09 12:29:59 PM PDT 24
Peak memory 204996 kb
Host smart-e7d1e6d2-9ed0-4ba2-b26f-1747c497ed7c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815224982 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.1815224982
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.38244095
Short name T58
Test name
Test status
Simulation time 362482197 ps
CPU time 2.7 seconds
Started Jun 09 12:29:55 PM PDT 24
Finished Jun 09 12:29:59 PM PDT 24
Peak memory 213324 kb
Host smart-f7a74bea-25b9-4cc0-89e1-d9c9ffb422c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38244095 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.38244095
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.1805950906
Short name T128
Test name
Test status
Simulation time 4901134417 ps
CPU time 10.92 seconds
Started Jun 09 12:30:10 PM PDT 24
Finished Jun 09 12:30:22 PM PDT 24
Peak memory 213376 kb
Host smart-dee9e2c0-e8d0-4b7d-85b3-0a3974a50c7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805950906 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.1805950906
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2541312023
Short name T368
Test name
Test status
Simulation time 175056647 ps
CPU time 2.44 seconds
Started Jun 09 12:29:53 PM PDT 24
Finished Jun 09 12:29:56 PM PDT 24
Peak memory 221576 kb
Host smart-169662bf-5f5c-4f67-a4cb-0831129faec9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541312023 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.2541312023
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.488412502
Short name T372
Test name
Test status
Simulation time 441857080 ps
CPU time 2.25 seconds
Started Jun 09 12:29:54 PM PDT 24
Finished Jun 09 12:29:57 PM PDT 24
Peak memory 213252 kb
Host smart-9c9ba07d-3e63-4d96-9425-d1722d8e72d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488412502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.488412502
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.1555824331
Short name T296
Test name
Test status
Simulation time 110392437365 ps
CPU time 306.31 seconds
Started Jun 09 12:29:51 PM PDT 24
Finished Jun 09 12:34:58 PM PDT 24
Peak memory 204924 kb
Host smart-4d438936-fa86-45a8-8228-cb565d71bf2b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555824331 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
rv_dm_jtag_dmi_csr_bit_bash.1555824331
Directory /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3978336855
Short name T317
Test name
Test status
Simulation time 2252231281 ps
CPU time 6.79 seconds
Started Jun 09 12:30:00 PM PDT 24
Finished Jun 09 12:30:12 PM PDT 24
Peak memory 204900 kb
Host smart-c95159c1-b3ff-4738-8f45-3d915b50e79a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978336855 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.3
978336855
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2698897763
Short name T318
Test name
Test status
Simulation time 502382936 ps
CPU time 1.39 seconds
Started Jun 09 12:29:53 PM PDT 24
Finished Jun 09 12:29:55 PM PDT 24
Peak memory 204632 kb
Host smart-dc19edc5-6c36-47c5-9a64-a19dc93b1c86
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698897763 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.2
698897763
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.253350950
Short name T115
Test name
Test status
Simulation time 148859389 ps
CPU time 3.89 seconds
Started Jun 09 12:29:46 PM PDT 24
Finished Jun 09 12:29:51 PM PDT 24
Peak memory 204996 kb
Host smart-a29cd125-4d71-4aab-b5eb-1b70d88ad4df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253350950 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_c
sr_outstanding.253350950
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.387172234
Short name T76
Test name
Test status
Simulation time 337114964 ps
CPU time 4.35 seconds
Started Jun 09 12:29:46 PM PDT 24
Finished Jun 09 12:29:51 PM PDT 24
Peak memory 213200 kb
Host smart-1808bb71-08ba-44c0-85f0-97aa5f769e6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387172234 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.387172234
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.2358930668
Short name T373
Test name
Test status
Simulation time 152992011 ps
CPU time 2.29 seconds
Started Jun 09 12:30:00 PM PDT 24
Finished Jun 09 12:30:02 PM PDT 24
Peak memory 216720 kb
Host smart-e40d8e20-87bd-4f36-bb79-4e79b612cb8b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358930668 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.2358930668
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1356877297
Short name T86
Test name
Test status
Simulation time 94409369 ps
CPU time 1.46 seconds
Started Jun 09 12:29:55 PM PDT 24
Finished Jun 09 12:29:57 PM PDT 24
Peak memory 213220 kb
Host smart-b1914370-e09f-4870-ac38-b310e4e7adb5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356877297 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.1356877297
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.2539668674
Short name T401
Test name
Test status
Simulation time 201168467 ps
CPU time 0.74 seconds
Started Jun 09 12:29:53 PM PDT 24
Finished Jun 09 12:29:55 PM PDT 24
Peak memory 204648 kb
Host smart-b22206b1-9c8e-4b22-841e-75f8eaafc6ee
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539668674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
rv_dm_jtag_dmi_csr_bit_bash.2539668674
Directory /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.1189236973
Short name T262
Test name
Test status
Simulation time 1764592547 ps
CPU time 5.92 seconds
Started Jun 09 12:29:55 PM PDT 24
Finished Jun 09 12:30:02 PM PDT 24
Peak memory 204828 kb
Host smart-84980425-1ab5-47ca-af8d-e67fee55cfc8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189236973 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.1
189236973
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1032123835
Short name T67
Test name
Test status
Simulation time 211760270 ps
CPU time 0.91 seconds
Started Jun 09 12:29:52 PM PDT 24
Finished Jun 09 12:29:54 PM PDT 24
Peak memory 204692 kb
Host smart-f9acff07-32fb-4336-8f3b-6c503ec46bf7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032123835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.1
032123835
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.2317979345
Short name T113
Test name
Test status
Simulation time 522188154 ps
CPU time 3.61 seconds
Started Jun 09 12:29:59 PM PDT 24
Finished Jun 09 12:30:03 PM PDT 24
Peak memory 205016 kb
Host smart-38c802a7-03fe-4c44-8f1d-2ee5375a28b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317979345 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.2317979345
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.3687556470
Short name T341
Test name
Test status
Simulation time 254769534 ps
CPU time 4.99 seconds
Started Jun 09 12:29:57 PM PDT 24
Finished Jun 09 12:30:03 PM PDT 24
Peak memory 213240 kb
Host smart-d749708e-2a19-4337-acb6-028d6d0ed7ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687556470 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.3687556470
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.564830797
Short name T133
Test name
Test status
Simulation time 3527853318 ps
CPU time 20.95 seconds
Started Jun 09 12:29:52 PM PDT 24
Finished Jun 09 12:30:13 PM PDT 24
Peak memory 213284 kb
Host smart-805abb97-67c8-4bfc-885b-eb8ebcb69fbe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564830797 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.564830797
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.953911971
Short name T255
Test name
Test status
Simulation time 52478199722 ps
CPU time 77.3 seconds
Started Jun 09 12:31:33 PM PDT 24
Finished Jun 09 12:32:51 PM PDT 24
Peak memory 213472 kb
Host smart-17ef78f0-3985-4d62-8139-2bedf90aaa89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953911971 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.953911971
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.3180732033
Short name T228
Test name
Test status
Simulation time 5963765676 ps
CPU time 6.41 seconds
Started Jun 09 12:31:32 PM PDT 24
Finished Jun 09 12:31:38 PM PDT 24
Peak memory 213404 kb
Host smart-143e6c99-174a-48a6-8a55-a1f0e3209140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180732033 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.3180732033
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.307107749
Short name T13
Test name
Test status
Simulation time 11168098723 ps
CPU time 8.76 seconds
Started Jun 09 12:31:31 PM PDT 24
Finished Jun 09 12:31:40 PM PDT 24
Peak memory 205028 kb
Host smart-d7bc123c-40de-49af-9202-bc048dba3921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307107749 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.307107749
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.1556053781
Short name T141
Test name
Test status
Simulation time 3203890915 ps
CPU time 10.09 seconds
Started Jun 09 12:31:33 PM PDT 24
Finished Jun 09 12:31:43 PM PDT 24
Peak memory 205012 kb
Host smart-70e49d86-8adb-4793-801f-f4d038d95760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556053781 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.1556053781
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.2250018089
Short name T28
Test name
Test status
Simulation time 283436641 ps
CPU time 0.96 seconds
Started Jun 09 12:31:35 PM PDT 24
Finished Jun 09 12:31:36 PM PDT 24
Peak memory 204680 kb
Host smart-46cf3098-bd84-4ee9-9fdd-a1e4be2c2afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250018089 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.2250018089
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.1791618360
Short name T230
Test name
Test status
Simulation time 2171022721 ps
CPU time 7.07 seconds
Started Jun 09 12:31:36 PM PDT 24
Finished Jun 09 12:31:43 PM PDT 24
Peak memory 205156 kb
Host smart-bdb55f05-e6c4-42ae-9a0f-75cbbb63b254
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1791618360 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t
l_access.1791618360
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.451996326
Short name T242
Test name
Test status
Simulation time 315752753 ps
CPU time 1.68 seconds
Started Jun 09 12:31:37 PM PDT 24
Finished Jun 09 12:31:39 PM PDT 24
Peak memory 204704 kb
Host smart-fc2620b6-b489-4a97-809a-0fe0ef7f4840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451996326 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.451996326
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.2884662557
Short name T225
Test name
Test status
Simulation time 1026119766 ps
CPU time 2.11 seconds
Started Jun 09 12:31:38 PM PDT 24
Finished Jun 09 12:31:41 PM PDT 24
Peak memory 204520 kb
Host smart-dfd08933-0ef1-482f-91f4-5f2464205569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884662557 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.2884662557
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.1638486578
Short name T203
Test name
Test status
Simulation time 5583923458 ps
CPU time 5.55 seconds
Started Jun 09 12:31:37 PM PDT 24
Finished Jun 09 12:31:43 PM PDT 24
Peak memory 204836 kb
Host smart-47aed9f9-f363-4656-8a14-c8f68df21703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638486578 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.1638486578
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.2016921179
Short name T202
Test name
Test status
Simulation time 702968149 ps
CPU time 1.23 seconds
Started Jun 09 12:31:31 PM PDT 24
Finished Jun 09 12:31:33 PM PDT 24
Peak memory 204812 kb
Host smart-b1d64c86-594a-4dd4-b2f0-feb57815c8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016921179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.2016921179
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.3389739919
Short name T50
Test name
Test status
Simulation time 280345585 ps
CPU time 1.47 seconds
Started Jun 09 12:31:40 PM PDT 24
Finished Jun 09 12:31:42 PM PDT 24
Peak memory 204572 kb
Host smart-0dab8e7b-887c-4c8a-a641-ad1a9af7d9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389739919 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.3389739919
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.1022521817
Short name T222
Test name
Test status
Simulation time 160654630 ps
CPU time 0.75 seconds
Started Jun 09 12:31:44 PM PDT 24
Finished Jun 09 12:31:45 PM PDT 24
Peak memory 204528 kb
Host smart-9b7591df-5682-41b0-83fd-83680f6a378f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022521817 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.1022521817
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.3649070272
Short name T140
Test name
Test status
Simulation time 688678458 ps
CPU time 1.54 seconds
Started Jun 09 12:31:32 PM PDT 24
Finished Jun 09 12:31:34 PM PDT 24
Peak memory 204676 kb
Host smart-6ba9d858-d712-4d67-a9bf-f95a511a7f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649070272 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.3649070272
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.4223019381
Short name T143
Test name
Test status
Simulation time 4642309859 ps
CPU time 13.41 seconds
Started Jun 09 12:31:36 PM PDT 24
Finished Jun 09 12:31:50 PM PDT 24
Peak memory 205016 kb
Host smart-bf35cf02-7046-46ee-97bb-30d6a82712e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223019381 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.4223019381
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.842156
Short name T246
Test name
Test status
Simulation time 4956240068 ps
CPU time 7.37 seconds
Started Jun 09 12:31:38 PM PDT 24
Finished Jun 09 12:31:45 PM PDT 24
Peak memory 204988 kb
Host smart-c8aff553-172f-4c4d-9cf9-8fde5123ed88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842156 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.842156
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.2913141357
Short name T219
Test name
Test status
Simulation time 4340840811 ps
CPU time 3.45 seconds
Started Jun 09 12:31:33 PM PDT 24
Finished Jun 09 12:31:37 PM PDT 24
Peak memory 205216 kb
Host smart-34731fc3-786f-4480-8024-056eca983363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913141357 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.2913141357
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.1994759581
Short name T187
Test name
Test status
Simulation time 553833403 ps
CPU time 1.01 seconds
Started Jun 09 12:31:26 PM PDT 24
Finished Jun 09 12:31:27 PM PDT 24
Peak memory 204572 kb
Host smart-b62fb758-9a59-417c-ad0c-c450cdf89e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994759581 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.1994759581
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.2064635876
Short name T30
Test name
Test status
Simulation time 8363244499 ps
CPU time 16.87 seconds
Started Jun 09 12:31:31 PM PDT 24
Finished Jun 09 12:31:48 PM PDT 24
Peak memory 204944 kb
Host smart-34097532-ab26-4701-8025-f85bcaf27d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064635876 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.2064635876
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.657938784
Short name T47
Test name
Test status
Simulation time 523434556 ps
CPU time 0.95 seconds
Started Jun 09 12:32:00 PM PDT 24
Finished Jun 09 12:32:01 PM PDT 24
Peak memory 204704 kb
Host smart-6784b863-83aa-48ad-9fb5-8cb5f2d0f970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657938784 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.657938784
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.737687563
Short name T152
Test name
Test status
Simulation time 153876413 ps
CPU time 0.89 seconds
Started Jun 09 12:32:06 PM PDT 24
Finished Jun 09 12:32:07 PM PDT 24
Peak memory 204772 kb
Host smart-99ad01f5-3055-49be-98fc-9aac7fca6b54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737687563 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.737687563
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.630173258
Short name T213
Test name
Test status
Simulation time 2791232568 ps
CPU time 5 seconds
Started Jun 09 12:32:00 PM PDT 24
Finished Jun 09 12:32:05 PM PDT 24
Peak memory 205144 kb
Host smart-906e80b9-3a25-4d86-88cf-f1981887ad22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630173258 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.630173258
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.448840020
Short name T258
Test name
Test status
Simulation time 3490660587 ps
CPU time 11.27 seconds
Started Jun 09 12:31:53 PM PDT 24
Finished Jun 09 12:32:05 PM PDT 24
Peak memory 205180 kb
Host smart-8c80f728-7e51-4968-aa73-9194ffaafd6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448840020 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.448840020
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.2121633248
Short name T14
Test name
Test status
Simulation time 30343313675 ps
CPU time 86.71 seconds
Started Jun 09 12:31:58 PM PDT 24
Finished Jun 09 12:33:25 PM PDT 24
Peak memory 205084 kb
Host smart-d24d66fc-144a-4e17-b5e3-acb65673be5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121633248 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.2121633248
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.4207857993
Short name T42
Test name
Test status
Simulation time 598590196 ps
CPU time 2.47 seconds
Started Jun 09 12:31:58 PM PDT 24
Finished Jun 09 12:32:01 PM PDT 24
Peak memory 204656 kb
Host smart-86118124-9d96-4044-aa74-1dde44f117e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207857993 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.4207857993
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.60699329
Short name T36
Test name
Test status
Simulation time 1222214755 ps
CPU time 2.43 seconds
Started Jun 09 12:32:05 PM PDT 24
Finished Jun 09 12:32:07 PM PDT 24
Peak memory 204556 kb
Host smart-c4cb0e15-edea-4bd4-9a07-eb44dc79e8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60699329 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.60699329
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.717605300
Short name T10
Test name
Test status
Simulation time 17318871010 ps
CPU time 9.12 seconds
Started Jun 09 12:31:53 PM PDT 24
Finished Jun 09 12:32:03 PM PDT 24
Peak memory 204992 kb
Host smart-c57796e3-07dc-489e-87bb-5ba656cc2aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717605300 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.717605300
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.116883750
Short name T29
Test name
Test status
Simulation time 216651631 ps
CPU time 1.23 seconds
Started Jun 09 12:32:02 PM PDT 24
Finished Jun 09 12:32:03 PM PDT 24
Peak memory 204652 kb
Host smart-2f08e080-9191-40ee-b940-4b13901d5529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116883750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.116883750
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.3663111186
Short name T220
Test name
Test status
Simulation time 4611103278 ps
CPU time 7.81 seconds
Started Jun 09 12:32:00 PM PDT 24
Finished Jun 09 12:32:08 PM PDT 24
Peak memory 205128 kb
Host smart-1ed31ca9-d884-418a-9b10-679c298b0dea
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3663111186 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.3663111186
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.2555743035
Short name T43
Test name
Test status
Simulation time 936059807 ps
CPU time 3.27 seconds
Started Jun 09 12:32:02 PM PDT 24
Finished Jun 09 12:32:05 PM PDT 24
Peak memory 204700 kb
Host smart-4917b96d-dd87-4917-af89-b052b40e50ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555743035 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.2555743035
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.3423629226
Short name T229
Test name
Test status
Simulation time 57287512 ps
CPU time 0.78 seconds
Started Jun 09 12:32:01 PM PDT 24
Finished Jun 09 12:32:02 PM PDT 24
Peak memory 204540 kb
Host smart-49303eb1-8fcb-4251-90e0-4c7e5c1c7b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423629226 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.3423629226
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.2892144936
Short name T245
Test name
Test status
Simulation time 323265933 ps
CPU time 1.03 seconds
Started Jun 09 12:32:00 PM PDT 24
Finished Jun 09 12:32:01 PM PDT 24
Peak memory 204604 kb
Host smart-d5b8cf7c-8689-468d-a9b8-6d1e0ad51dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892144936 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.2892144936
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.292830181
Short name T176
Test name
Test status
Simulation time 603142807 ps
CPU time 1.91 seconds
Started Jun 09 12:32:04 PM PDT 24
Finished Jun 09 12:32:06 PM PDT 24
Peak memory 204480 kb
Host smart-0685d1bb-37e5-4722-b44a-78895fe759d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292830181 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.292830181
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.3328144502
Short name T244
Test name
Test status
Simulation time 4076519627 ps
CPU time 6.61 seconds
Started Jun 09 12:32:00 PM PDT 24
Finished Jun 09 12:32:07 PM PDT 24
Peak memory 205092 kb
Host smart-a6024c9a-1a3e-49e5-9854-7d181ecab668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328144502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.3328144502
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.1492554016
Short name T53
Test name
Test status
Simulation time 581609446 ps
CPU time 1.28 seconds
Started Jun 09 12:32:06 PM PDT 24
Finished Jun 09 12:32:07 PM PDT 24
Peak memory 204572 kb
Host smart-d76995da-9023-4ddb-b566-bcc28c591d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492554016 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.1492554016
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.3107344951
Short name T138
Test name
Test status
Simulation time 468740597 ps
CPU time 2.11 seconds
Started Jun 09 12:31:55 PM PDT 24
Finished Jun 09 12:31:58 PM PDT 24
Peak memory 204696 kb
Host smart-65a53bbd-d031-4a74-9c99-acc1ac6edf69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107344951 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.3107344951
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.1167471459
Short name T9
Test name
Test status
Simulation time 886788984 ps
CPU time 1.26 seconds
Started Jun 09 12:32:04 PM PDT 24
Finished Jun 09 12:32:06 PM PDT 24
Peak memory 204648 kb
Host smart-6f9cd0d2-7b88-4d7f-995e-c91de2d7ffab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167471459 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.1167471459
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.2254995821
Short name T21
Test name
Test status
Simulation time 1922677452 ps
CPU time 3.65 seconds
Started Jun 09 12:31:59 PM PDT 24
Finished Jun 09 12:32:03 PM PDT 24
Peak memory 204844 kb
Host smart-4352fa74-e873-4a35-8b9f-883c67ee6dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254995821 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.2254995821
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.1292950497
Short name T16
Test name
Test status
Simulation time 738750698 ps
CPU time 1.76 seconds
Started Jun 09 12:32:00 PM PDT 24
Finished Jun 09 12:32:02 PM PDT 24
Peak memory 204692 kb
Host smart-691eaced-cef7-4b2c-b8d4-53de032423ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292950497 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.1292950497
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.3102144776
Short name T45
Test name
Test status
Simulation time 578689237 ps
CPU time 1.29 seconds
Started Jun 09 12:32:00 PM PDT 24
Finished Jun 09 12:32:01 PM PDT 24
Peak memory 204656 kb
Host smart-d437ea23-f583-48b9-8c63-32cd908c2ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102144776 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.3102144776
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.889658395
Short name T39
Test name
Test status
Simulation time 104620025 ps
CPU time 1.04 seconds
Started Jun 09 12:32:00 PM PDT 24
Finished Jun 09 12:32:02 PM PDT 24
Peak memory 212904 kb
Host smart-e46837e2-64f4-41df-864c-5fdd1c103809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889658395 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.889658395
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.3039076843
Short name T193
Test name
Test status
Simulation time 8527138668 ps
CPU time 14.17 seconds
Started Jun 09 12:31:52 PM PDT 24
Finished Jun 09 12:32:07 PM PDT 24
Peak memory 205176 kb
Host smart-bd9411e1-8e18-445f-9f10-8d70e37ad23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039076843 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.3039076843
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.1047307644
Short name T5
Test name
Test status
Simulation time 253327611 ps
CPU time 1.32 seconds
Started Jun 09 12:32:04 PM PDT 24
Finished Jun 09 12:32:05 PM PDT 24
Peak memory 229232 kb
Host smart-2bcbaaf2-dc1e-4d9c-86c4-70c7fa45d9f1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047307644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.1047307644
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.3974281974
Short name T218
Test name
Test status
Simulation time 659759959 ps
CPU time 1.32 seconds
Started Jun 09 12:31:53 PM PDT 24
Finished Jun 09 12:31:54 PM PDT 24
Peak memory 204504 kb
Host smart-16160561-6656-41d7-8bfa-968cb72b03ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974281974 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.3974281974
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.2646593662
Short name T73
Test name
Test status
Simulation time 107824265 ps
CPU time 0.96 seconds
Started Jun 09 12:32:19 PM PDT 24
Finished Jun 09 12:32:20 PM PDT 24
Peak memory 204692 kb
Host smart-b3e992b8-2d22-4c21-97c5-b35cd63cbf39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646593662 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.2646593662
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.2170191032
Short name T237
Test name
Test status
Simulation time 8524839712 ps
CPU time 15.6 seconds
Started Jun 09 12:32:20 PM PDT 24
Finished Jun 09 12:32:37 PM PDT 24
Peak memory 215396 kb
Host smart-6d4b27b6-5917-44c2-a541-9d64800b0d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170191032 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.2170191032
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.3576885251
Short name T182
Test name
Test status
Simulation time 3551862110 ps
CPU time 10.44 seconds
Started Jun 09 12:32:18 PM PDT 24
Finished Jun 09 12:32:29 PM PDT 24
Peak memory 205176 kb
Host smart-0e8dba59-2bd8-4305-b089-404ae47bcda9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576885251 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.3576885251
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.16235145
Short name T216
Test name
Test status
Simulation time 6175169711 ps
CPU time 9.77 seconds
Started Jun 09 12:32:20 PM PDT 24
Finished Jun 09 12:32:31 PM PDT 24
Peak memory 205156 kb
Host smart-29acff6a-b7d6-4a02-b609-7b6b30615e23
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=16235145 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_tl
_access.16235145
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.497511748
Short name T211
Test name
Test status
Simulation time 2328590606 ps
CPU time 6.2 seconds
Started Jun 09 12:32:15 PM PDT 24
Finished Jun 09 12:32:22 PM PDT 24
Peak memory 205204 kb
Host smart-add16534-0940-4289-a801-fc2aac1116c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497511748 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.497511748
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.2748465636
Short name T158
Test name
Test status
Simulation time 85058571 ps
CPU time 0.76 seconds
Started Jun 09 12:32:19 PM PDT 24
Finished Jun 09 12:32:21 PM PDT 24
Peak memory 204764 kb
Host smart-dbdd5af5-49b0-4d98-affb-dbbc179a6a3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748465636 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.2748465636
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.270275299
Short name T249
Test name
Test status
Simulation time 10845373963 ps
CPU time 22.04 seconds
Started Jun 09 12:32:15 PM PDT 24
Finished Jun 09 12:32:38 PM PDT 24
Peak memory 213412 kb
Host smart-3db12a21-ff4e-452d-bcda-3d2ff72c7385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270275299 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.270275299
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.2306628864
Short name T257
Test name
Test status
Simulation time 3794930988 ps
CPU time 11.47 seconds
Started Jun 09 12:32:16 PM PDT 24
Finished Jun 09 12:32:28 PM PDT 24
Peak memory 205220 kb
Host smart-846695cd-88f5-4e32-91af-ba1b3aa0e6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306628864 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.2306628864
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.187039318
Short name T223
Test name
Test status
Simulation time 12132525333 ps
CPU time 33.18 seconds
Started Jun 09 12:32:18 PM PDT 24
Finished Jun 09 12:32:52 PM PDT 24
Peak memory 205132 kb
Host smart-e3a3c997-dded-463a-95ff-8c8d70d20a9f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=187039318 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_t
l_access.187039318
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.1987187099
Short name T197
Test name
Test status
Simulation time 6070610828 ps
CPU time 7.77 seconds
Started Jun 09 12:32:18 PM PDT 24
Finished Jun 09 12:32:26 PM PDT 24
Peak memory 205196 kb
Host smart-f8f55b6b-6cac-410b-ad72-cdf72bcf4122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987187099 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.1987187099
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_stress_all.221638999
Short name T136
Test name
Test status
Simulation time 10554241656 ps
CPU time 32.09 seconds
Started Jun 09 12:32:21 PM PDT 24
Finished Jun 09 12:32:54 PM PDT 24
Peak memory 205020 kb
Host smart-ea949fd5-ed26-4fa6-87c1-2f66ef9887e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221638999 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.221638999
Directory /workspace/11.rv_dm_stress_all/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.3947532302
Short name T153
Test name
Test status
Simulation time 55376184 ps
CPU time 0.78 seconds
Started Jun 09 12:32:17 PM PDT 24
Finished Jun 09 12:32:19 PM PDT 24
Peak memory 204736 kb
Host smart-26daaca0-dedb-4ff7-91ed-e9f9857dfabd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947532302 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.3947532302
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.2606893788
Short name T247
Test name
Test status
Simulation time 7103822432 ps
CPU time 6.73 seconds
Started Jun 09 12:32:18 PM PDT 24
Finished Jun 09 12:32:26 PM PDT 24
Peak memory 213344 kb
Host smart-5d0b9e42-c8d7-409d-98e4-b891ea1a5735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606893788 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.2606893788
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.4012675829
Short name T185
Test name
Test status
Simulation time 4174874514 ps
CPU time 3.75 seconds
Started Jun 09 12:32:18 PM PDT 24
Finished Jun 09 12:32:22 PM PDT 24
Peak memory 205128 kb
Host smart-8f743776-f4ab-4602-8d1d-20050496fd4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012675829 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.4012675829
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.1939812935
Short name T205
Test name
Test status
Simulation time 11550545874 ps
CPU time 23.47 seconds
Started Jun 09 12:32:21 PM PDT 24
Finished Jun 09 12:32:46 PM PDT 24
Peak memory 205136 kb
Host smart-b61f5548-3a70-4783-8644-936ebd0d4320
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1939812935 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.1939812935
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.2380585971
Short name T90
Test name
Test status
Simulation time 3968758478 ps
CPU time 5.16 seconds
Started Jun 09 12:32:18 PM PDT 24
Finished Jun 09 12:32:23 PM PDT 24
Peak memory 205128 kb
Host smart-9b6545db-4c18-431e-adec-252365d62959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380585971 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.2380585971
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_stress_all.3603418079
Short name T22
Test name
Test status
Simulation time 14050339896 ps
CPU time 40.83 seconds
Started Jun 09 12:32:19 PM PDT 24
Finished Jun 09 12:33:01 PM PDT 24
Peak memory 204988 kb
Host smart-93fc25b7-84ec-493f-976c-47907926765c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603418079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.3603418079
Directory /workspace/12.rv_dm_stress_all/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.4054947193
Short name T159
Test name
Test status
Simulation time 61138819 ps
CPU time 0.77 seconds
Started Jun 09 12:32:20 PM PDT 24
Finished Jun 09 12:32:22 PM PDT 24
Peak memory 204764 kb
Host smart-730b8146-0a59-47af-8c27-e268fa9cba8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054947193 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.4054947193
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.2166978533
Short name T25
Test name
Test status
Simulation time 2375069797 ps
CPU time 5.26 seconds
Started Jun 09 12:32:14 PM PDT 24
Finished Jun 09 12:32:20 PM PDT 24
Peak memory 205132 kb
Host smart-07d7e62d-db89-4f77-8731-2d52c1dcec08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166978533 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.2166978533
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.3071924078
Short name T252
Test name
Test status
Simulation time 2462512994 ps
CPU time 6.38 seconds
Started Jun 09 12:32:15 PM PDT 24
Finished Jun 09 12:32:22 PM PDT 24
Peak memory 205172 kb
Host smart-cd4849af-a0a0-429d-bd45-65b3cca44551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071924078 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.3071924078
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.3341509881
Short name T92
Test name
Test status
Simulation time 1986122304 ps
CPU time 3.27 seconds
Started Jun 09 12:32:28 PM PDT 24
Finished Jun 09 12:32:31 PM PDT 24
Peak memory 205064 kb
Host smart-4b90d493-b6a6-4587-99eb-649856c02d5f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3341509881 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_
tl_access.3341509881
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.3032133201
Short name T233
Test name
Test status
Simulation time 8258331072 ps
CPU time 6.83 seconds
Started Jun 09 12:32:15 PM PDT 24
Finished Jun 09 12:32:22 PM PDT 24
Peak memory 205208 kb
Host smart-9d90b05b-b0cd-448b-b100-c2b66458f5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032133201 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.3032133201
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_stress_all.2884684772
Short name T261
Test name
Test status
Simulation time 4933986458 ps
CPU time 5.5 seconds
Started Jun 09 12:32:17 PM PDT 24
Finished Jun 09 12:32:22 PM PDT 24
Peak memory 205056 kb
Host smart-f4f755f9-0ac3-4f78-ba2b-1c0e5726342a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884684772 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.2884684772
Directory /workspace/13.rv_dm_stress_all/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.2026880439
Short name T241
Test name
Test status
Simulation time 52739304 ps
CPU time 0.83 seconds
Started Jun 09 12:32:18 PM PDT 24
Finished Jun 09 12:32:20 PM PDT 24
Peak memory 204780 kb
Host smart-7d574aa1-6cb8-473e-8c6d-c6f1ab1b9510
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026880439 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.2026880439
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.3927072300
Short name T184
Test name
Test status
Simulation time 9032971571 ps
CPU time 13.97 seconds
Started Jun 09 12:32:21 PM PDT 24
Finished Jun 09 12:32:37 PM PDT 24
Peak memory 205160 kb
Host smart-7613007d-2317-4fda-a729-460f4589c686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927072300 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.3927072300
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.4058199616
Short name T260
Test name
Test status
Simulation time 1266413931 ps
CPU time 4.37 seconds
Started Jun 09 12:32:17 PM PDT 24
Finished Jun 09 12:32:22 PM PDT 24
Peak memory 205040 kb
Host smart-103f1cd0-2cd6-4482-afb6-648782d847e2
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4058199616 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.4058199616
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.949162610
Short name T232
Test name
Test status
Simulation time 2346990521 ps
CPU time 3.47 seconds
Started Jun 09 12:32:16 PM PDT 24
Finished Jun 09 12:32:19 PM PDT 24
Peak memory 205176 kb
Host smart-aa860b94-0cd5-4b12-8a31-8ef044fe80e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949162610 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.949162610
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.3995210528
Short name T154
Test name
Test status
Simulation time 48756559 ps
CPU time 0.8 seconds
Started Jun 09 12:32:18 PM PDT 24
Finished Jun 09 12:32:19 PM PDT 24
Peak memory 204740 kb
Host smart-8e7cad3d-5558-4c55-96b0-553a915852dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995210528 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.3995210528
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.2526311655
Short name T195
Test name
Test status
Simulation time 39531989686 ps
CPU time 108.99 seconds
Started Jun 09 12:32:23 PM PDT 24
Finished Jun 09 12:34:13 PM PDT 24
Peak memory 213264 kb
Host smart-e7cd0135-b2fd-4ef3-b5ca-158b3873baf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526311655 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.2526311655
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.735192337
Short name T19
Test name
Test status
Simulation time 4057649228 ps
CPU time 3.43 seconds
Started Jun 09 12:32:19 PM PDT 24
Finished Jun 09 12:32:23 PM PDT 24
Peak memory 205176 kb
Host smart-f2637861-8daa-4d5f-a7b6-82cbe30b37f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735192337 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.735192337
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.3042260422
Short name T196
Test name
Test status
Simulation time 1216655330 ps
CPU time 4.3 seconds
Started Jun 09 12:32:21 PM PDT 24
Finished Jun 09 12:32:26 PM PDT 24
Peak memory 205052 kb
Host smart-8c656dea-4fd0-4338-9cfb-9ce90c451b11
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3042260422 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_
tl_access.3042260422
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.1736816070
Short name T199
Test name
Test status
Simulation time 7802983576 ps
CPU time 6.8 seconds
Started Jun 09 12:32:23 PM PDT 24
Finished Jun 09 12:32:31 PM PDT 24
Peak memory 204768 kb
Host smart-3e2f085d-bc81-45e0-9f6c-9b5b65861348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736816070 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.1736816070
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.2577266041
Short name T4
Test name
Test status
Simulation time 36791227 ps
CPU time 0.8 seconds
Started Jun 09 12:32:24 PM PDT 24
Finished Jun 09 12:32:26 PM PDT 24
Peak memory 204780 kb
Host smart-a87536e6-a30b-4511-af76-5cde9d537d62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577266041 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.2577266041
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.2487859096
Short name T207
Test name
Test status
Simulation time 1120267906 ps
CPU time 4.03 seconds
Started Jun 09 12:32:21 PM PDT 24
Finished Jun 09 12:32:26 PM PDT 24
Peak memory 205024 kb
Host smart-d7acfe4e-aaf2-4c4e-9c98-4ef47a2733d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487859096 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.2487859096
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.3473900712
Short name T71
Test name
Test status
Simulation time 12168649708 ps
CPU time 10.43 seconds
Started Jun 09 12:32:23 PM PDT 24
Finished Jun 09 12:32:35 PM PDT 24
Peak memory 205084 kb
Host smart-ced1ac5b-c5fa-437c-994c-912bda54081c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473900712 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.3473900712
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.2399051817
Short name T179
Test name
Test status
Simulation time 2865005701 ps
CPU time 8.94 seconds
Started Jun 09 12:32:18 PM PDT 24
Finished Jun 09 12:32:27 PM PDT 24
Peak memory 205128 kb
Host smart-e149c013-647d-4361-a9b5-224c9684e2d5
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2399051817 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_
tl_access.2399051817
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.1943599947
Short name T226
Test name
Test status
Simulation time 5146877053 ps
CPU time 7.19 seconds
Started Jun 09 12:32:22 PM PDT 24
Finished Jun 09 12:32:30 PM PDT 24
Peak memory 205160 kb
Host smart-096be6b4-1120-4cf2-89c0-3bcf89ad351f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943599947 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.1943599947
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_stress_all.162226769
Short name T11
Test name
Test status
Simulation time 4310828109 ps
CPU time 12.76 seconds
Started Jun 09 12:32:23 PM PDT 24
Finished Jun 09 12:32:37 PM PDT 24
Peak memory 205068 kb
Host smart-bda2fd3a-55d9-4d02-849c-9b4936dd467c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162226769 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.162226769
Directory /workspace/16.rv_dm_stress_all/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.4161620975
Short name T146
Test name
Test status
Simulation time 29455103 ps
CPU time 0.79 seconds
Started Jun 09 12:32:24 PM PDT 24
Finished Jun 09 12:32:26 PM PDT 24
Peak memory 204784 kb
Host smart-7f48c1e9-522b-4555-bfbb-ed329ee6664b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161620975 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.4161620975
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.2737641850
Short name T236
Test name
Test status
Simulation time 89795030116 ps
CPU time 136.63 seconds
Started Jun 09 12:32:18 PM PDT 24
Finished Jun 09 12:34:36 PM PDT 24
Peak memory 214940 kb
Host smart-d5afd578-2525-4f8f-804f-6426ecc2edbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737641850 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.2737641850
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.2421195795
Short name T20
Test name
Test status
Simulation time 1024117446 ps
CPU time 2.27 seconds
Started Jun 09 12:32:17 PM PDT 24
Finished Jun 09 12:32:20 PM PDT 24
Peak memory 205032 kb
Host smart-201c8057-6765-41e4-8c7f-a77264682d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421195795 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.2421195795
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.3090600672
Short name T198
Test name
Test status
Simulation time 19884038612 ps
CPU time 15.45 seconds
Started Jun 09 12:32:20 PM PDT 24
Finished Jun 09 12:32:36 PM PDT 24
Peak memory 205312 kb
Host smart-b5886cc5-3ea3-4bd4-b7dc-d90a09b51679
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3090600672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_
tl_access.3090600672
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.2662014143
Short name T15
Test name
Test status
Simulation time 10648371163 ps
CPU time 8.66 seconds
Started Jun 09 12:32:23 PM PDT 24
Finished Jun 09 12:32:33 PM PDT 24
Peak memory 204768 kb
Host smart-9017ac1c-1ca5-49dd-b778-73c4b63badff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662014143 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.2662014143
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.2436668579
Short name T150
Test name
Test status
Simulation time 63103553 ps
CPU time 0.74 seconds
Started Jun 09 12:32:20 PM PDT 24
Finished Jun 09 12:32:22 PM PDT 24
Peak memory 204784 kb
Host smart-65c8d0ae-77c3-4289-bbe5-9d55bb0c1417
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436668579 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.2436668579
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.1999833072
Short name T227
Test name
Test status
Simulation time 11682227919 ps
CPU time 21.05 seconds
Started Jun 09 12:32:21 PM PDT 24
Finished Jun 09 12:32:43 PM PDT 24
Peak memory 213424 kb
Host smart-8154ed9f-3325-47c8-8c00-cf8ba4c876e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999833072 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.1999833072
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.2721043435
Short name T188
Test name
Test status
Simulation time 6254026406 ps
CPU time 11.92 seconds
Started Jun 09 12:32:23 PM PDT 24
Finished Jun 09 12:32:36 PM PDT 24
Peak memory 205200 kb
Host smart-3f198835-ef5e-4f79-a701-f90329a9f039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721043435 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.2721043435
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.697037535
Short name T212
Test name
Test status
Simulation time 2460874285 ps
CPU time 2.4 seconds
Started Jun 09 12:32:20 PM PDT 24
Finished Jun 09 12:32:24 PM PDT 24
Peak memory 205176 kb
Host smart-f5e68eb7-d946-4ca0-9a9f-af5503ea173c
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=697037535 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_t
l_access.697037535
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.400315730
Short name T217
Test name
Test status
Simulation time 1914678721 ps
CPU time 5.42 seconds
Started Jun 09 12:32:23 PM PDT 24
Finished Jun 09 12:32:29 PM PDT 24
Peak memory 205068 kb
Host smart-ed09bf56-f13c-4dd0-9726-59ac1a6fa87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400315730 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.400315730
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.3625338693
Short name T163
Test name
Test status
Simulation time 47798539 ps
CPU time 0.81 seconds
Started Jun 09 12:32:25 PM PDT 24
Finished Jun 09 12:32:27 PM PDT 24
Peak memory 204736 kb
Host smart-fcba37e1-2c48-4c2d-8491-b25c7616156e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625338693 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.3625338693
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.1705078311
Short name T254
Test name
Test status
Simulation time 3652948418 ps
CPU time 6.47 seconds
Started Jun 09 12:32:23 PM PDT 24
Finished Jun 09 12:32:30 PM PDT 24
Peak memory 205164 kb
Host smart-01ce5d6a-6119-421c-9a5d-f011f4d8f1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705078311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.1705078311
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.1326513264
Short name T186
Test name
Test status
Simulation time 16321032960 ps
CPU time 15.17 seconds
Started Jun 09 12:32:25 PM PDT 24
Finished Jun 09 12:32:41 PM PDT 24
Peak memory 213328 kb
Host smart-7708e3bb-de28-4ca7-9350-0c744a0c8236
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1326513264 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_
tl_access.1326513264
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.2846956460
Short name T121
Test name
Test status
Simulation time 122697291 ps
CPU time 0.8 seconds
Started Jun 09 12:32:03 PM PDT 24
Finished Jun 09 12:32:04 PM PDT 24
Peak memory 204808 kb
Host smart-5c0dc29d-dcd4-4b2c-8e5d-dd1839364f3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846956460 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.2846956460
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.1194628741
Short name T256
Test name
Test status
Simulation time 39565186578 ps
CPU time 33.36 seconds
Started Jun 09 12:32:07 PM PDT 24
Finished Jun 09 12:32:41 PM PDT 24
Peak memory 213408 kb
Host smart-5a9de95e-6a27-4c5e-9301-1475bc1c7fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194628741 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.1194628741
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.1790513852
Short name T125
Test name
Test status
Simulation time 2458507330 ps
CPU time 3.18 seconds
Started Jun 09 12:32:09 PM PDT 24
Finished Jun 09 12:32:13 PM PDT 24
Peak memory 205256 kb
Host smart-43aa3efa-583d-4a3d-b07c-cefd975e9eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790513852 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.1790513852
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.3300265633
Short name T206
Test name
Test status
Simulation time 3747099163 ps
CPU time 11.58 seconds
Started Jun 09 12:32:07 PM PDT 24
Finished Jun 09 12:32:19 PM PDT 24
Peak memory 205228 kb
Host smart-075541c7-5f52-4a10-9b3e-489a80b087c8
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3300265633 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.3300265633
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.2820895988
Short name T208
Test name
Test status
Simulation time 117525514 ps
CPU time 0.82 seconds
Started Jun 09 12:32:14 PM PDT 24
Finished Jun 09 12:32:15 PM PDT 24
Peak memory 204568 kb
Host smart-b5d0d7d7-39ea-4e53-a031-ce0851806572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820895988 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.2820895988
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.1570653216
Short name T190
Test name
Test status
Simulation time 3585710064 ps
CPU time 10.55 seconds
Started Jun 09 12:32:08 PM PDT 24
Finished Jun 09 12:32:19 PM PDT 24
Peak memory 205128 kb
Host smart-e626d0db-aee8-48c5-bbde-de57f9e7f2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570653216 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.1570653216
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.99629753
Short name T63
Test name
Test status
Simulation time 404204174 ps
CPU time 1.17 seconds
Started Jun 09 12:32:07 PM PDT 24
Finished Jun 09 12:32:09 PM PDT 24
Peak memory 237344 kb
Host smart-6f728c90-0b05-405a-bc5a-062c025428a9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99629753 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.99629753
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.3204126298
Short name T168
Test name
Test status
Simulation time 61502591 ps
CPU time 0.72 seconds
Started Jun 09 12:32:25 PM PDT 24
Finished Jun 09 12:32:27 PM PDT 24
Peak memory 204728 kb
Host smart-4a5eb8b4-52a3-4aa7-91be-f128d018065e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204126298 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.3204126298
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/20.rv_dm_stress_all.2967923857
Short name T8
Test name
Test status
Simulation time 17227824150 ps
CPU time 49.28 seconds
Started Jun 09 12:32:21 PM PDT 24
Finished Jun 09 12:33:12 PM PDT 24
Peak memory 204952 kb
Host smart-ab468d6f-bd76-45ff-b3b7-add0813ae03f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967923857 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.2967923857
Directory /workspace/20.rv_dm_stress_all/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.1675298454
Short name T170
Test name
Test status
Simulation time 93998244 ps
CPU time 0.87 seconds
Started Jun 09 12:32:23 PM PDT 24
Finished Jun 09 12:32:25 PM PDT 24
Peak memory 204784 kb
Host smart-ef393c29-cdb6-4b41-a2ba-54b96c8eecb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675298454 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.1675298454
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.1262278755
Short name T62
Test name
Test status
Simulation time 46193779 ps
CPU time 0.76 seconds
Started Jun 09 12:32:27 PM PDT 24
Finished Jun 09 12:32:28 PM PDT 24
Peak memory 204808 kb
Host smart-733e7a81-c16a-4a88-9fab-6b202793f4f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262278755 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.1262278755
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.1399734615
Short name T33
Test name
Test status
Simulation time 45316522 ps
CPU time 0.73 seconds
Started Jun 09 12:32:26 PM PDT 24
Finished Jun 09 12:32:27 PM PDT 24
Peak memory 204744 kb
Host smart-1bd4d244-92bf-430d-baa5-3634b567c0e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399734615 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.1399734615
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.2524134355
Short name T210
Test name
Test status
Simulation time 26641482 ps
CPU time 0.77 seconds
Started Jun 09 12:32:29 PM PDT 24
Finished Jun 09 12:32:30 PM PDT 24
Peak memory 204732 kb
Host smart-02ea4c74-55be-4f6a-afc0-682ecd41b437
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524134355 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.2524134355
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.2739695953
Short name T156
Test name
Test status
Simulation time 36065698 ps
CPU time 0.77 seconds
Started Jun 09 12:32:28 PM PDT 24
Finished Jun 09 12:32:29 PM PDT 24
Peak memory 204736 kb
Host smart-704302e8-ff3b-4305-9300-933dcc816000
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739695953 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.2739695953
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.1811060886
Short name T200
Test name
Test status
Simulation time 121450966 ps
CPU time 1 seconds
Started Jun 09 12:32:28 PM PDT 24
Finished Jun 09 12:32:30 PM PDT 24
Peak memory 204760 kb
Host smart-f46b739b-27e0-43af-99ac-a4d029285612
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811060886 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.1811060886
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.959672159
Short name T157
Test name
Test status
Simulation time 61293626 ps
CPU time 0.88 seconds
Started Jun 09 12:32:29 PM PDT 24
Finished Jun 09 12:32:31 PM PDT 24
Peak memory 204764 kb
Host smart-a05c6b6f-0633-48c1-b0a3-7a97baac6f2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959672159 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.959672159
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.1108325832
Short name T2
Test name
Test status
Simulation time 67612257 ps
CPU time 0.87 seconds
Started Jun 09 12:32:07 PM PDT 24
Finished Jun 09 12:32:08 PM PDT 24
Peak memory 204784 kb
Host smart-42198e5a-1ef0-4861-80c7-d224fe8ed106
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108325832 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.1108325832
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.1191780035
Short name T191
Test name
Test status
Simulation time 11966074909 ps
CPU time 9.87 seconds
Started Jun 09 12:32:09 PM PDT 24
Finished Jun 09 12:32:19 PM PDT 24
Peak memory 213056 kb
Host smart-895c208b-aff9-4abc-b3c5-c93388181b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191780035 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.1191780035
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.4030693404
Short name T173
Test name
Test status
Simulation time 2051073936 ps
CPU time 6.99 seconds
Started Jun 09 12:32:04 PM PDT 24
Finished Jun 09 12:32:12 PM PDT 24
Peak memory 205308 kb
Host smart-fdb3e43c-adf8-411e-ba10-f77191713bd4
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4030693404 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.4030693404
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.1847089661
Short name T239
Test name
Test status
Simulation time 95061146 ps
CPU time 0.95 seconds
Started Jun 09 12:32:08 PM PDT 24
Finished Jun 09 12:32:09 PM PDT 24
Peak memory 204568 kb
Host smart-32b412f8-90a4-4b82-be6b-39f7f53d4454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847089661 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.1847089661
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.1689140809
Short name T250
Test name
Test status
Simulation time 14443103657 ps
CPU time 10.45 seconds
Started Jun 09 12:32:05 PM PDT 24
Finished Jun 09 12:32:16 PM PDT 24
Peak memory 213452 kb
Host smart-76d0e533-de0e-4062-9fa4-76bda231c182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689140809 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.1689140809
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.3875976397
Short name T64
Test name
Test status
Simulation time 1171788803 ps
CPU time 1.24 seconds
Started Jun 09 12:32:17 PM PDT 24
Finished Jun 09 12:32:19 PM PDT 24
Peak memory 228920 kb
Host smart-33e2a5a1-76c7-432c-bf2a-a1dbe25e3f83
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875976397 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.3875976397
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.1724428221
Short name T161
Test name
Test status
Simulation time 39347085 ps
CPU time 0.76 seconds
Started Jun 09 12:32:34 PM PDT 24
Finished Jun 09 12:32:36 PM PDT 24
Peak memory 204760 kb
Host smart-58f1016d-2413-49be-baa6-15c9823414f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724428221 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.1724428221
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.21972644
Short name T145
Test name
Test status
Simulation time 102613273 ps
CPU time 0.74 seconds
Started Jun 09 12:32:30 PM PDT 24
Finished Jun 09 12:32:31 PM PDT 24
Peak memory 204792 kb
Host smart-e8a60b17-5169-4fdd-9074-59e89e4aa847
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21972644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.21972644
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.1694684150
Short name T231
Test name
Test status
Simulation time 69859825 ps
CPU time 0.79 seconds
Started Jun 09 12:32:28 PM PDT 24
Finished Jun 09 12:32:29 PM PDT 24
Peak memory 204724 kb
Host smart-a0466317-aff9-4a6f-9a4a-643d67f1102a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694684150 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.1694684150
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_stress_all.763556227
Short name T44
Test name
Test status
Simulation time 4549222811 ps
CPU time 7.37 seconds
Started Jun 09 12:32:33 PM PDT 24
Finished Jun 09 12:32:40 PM PDT 24
Peak memory 204968 kb
Host smart-f2c8e370-4b66-4013-af93-f60f87bfbab3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763556227 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.763556227
Directory /workspace/32.rv_dm_stress_all/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.1864264651
Short name T166
Test name
Test status
Simulation time 84856823 ps
CPU time 0.87 seconds
Started Jun 09 12:32:29 PM PDT 24
Finished Jun 09 12:32:31 PM PDT 24
Peak memory 204784 kb
Host smart-c8e73aca-5f86-406f-b70c-c913c454ac1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864264651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.1864264651
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_stress_all.888023802
Short name T142
Test name
Test status
Simulation time 9326392758 ps
CPU time 14.58 seconds
Started Jun 09 12:32:28 PM PDT 24
Finished Jun 09 12:32:43 PM PDT 24
Peak memory 205028 kb
Host smart-61f3c588-07d2-40f2-bf4e-b50a6072294e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888023802 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.888023802
Directory /workspace/33.rv_dm_stress_all/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.3306806474
Short name T72
Test name
Test status
Simulation time 40084640 ps
CPU time 0.82 seconds
Started Jun 09 12:32:29 PM PDT 24
Finished Jun 09 12:32:31 PM PDT 24
Peak memory 204788 kb
Host smart-bb3251d8-bdfa-41b3-a815-48e95f7937e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306806474 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.3306806474
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.2670816913
Short name T160
Test name
Test status
Simulation time 79201908 ps
CPU time 0.69 seconds
Started Jun 09 12:32:33 PM PDT 24
Finished Jun 09 12:32:34 PM PDT 24
Peak memory 204736 kb
Host smart-379e817f-e1b0-45eb-b28c-40339eb791bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670816913 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.2670816913
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.3462652240
Short name T144
Test name
Test status
Simulation time 64825072 ps
CPU time 0.75 seconds
Started Jun 09 12:32:33 PM PDT 24
Finished Jun 09 12:32:34 PM PDT 24
Peak memory 204692 kb
Host smart-d11c68f2-2534-4122-a4b4-94cbfaa1f0dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462652240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.3462652240
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.3426228605
Short name T122
Test name
Test status
Simulation time 129293727 ps
CPU time 0.77 seconds
Started Jun 09 12:32:37 PM PDT 24
Finished Jun 09 12:32:38 PM PDT 24
Peak memory 204768 kb
Host smart-ac4d7b9d-b2d7-4ec1-a6c0-4069a88b9b0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426228605 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.3426228605
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_stress_all.985423748
Short name T139
Test name
Test status
Simulation time 7351899252 ps
CPU time 11.04 seconds
Started Jun 09 12:32:31 PM PDT 24
Finished Jun 09 12:32:42 PM PDT 24
Peak memory 205088 kb
Host smart-7408df22-7f0c-4714-b557-4273b2e50e82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985423748 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.985423748
Directory /workspace/37.rv_dm_stress_all/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.1086268466
Short name T181
Test name
Test status
Simulation time 151851959 ps
CPU time 0.8 seconds
Started Jun 09 12:32:34 PM PDT 24
Finished Jun 09 12:32:36 PM PDT 24
Peak memory 204760 kb
Host smart-a354904e-189c-46b3-ba00-6d62968ad368
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086268466 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.1086268466
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_stress_all.1581634227
Short name T24
Test name
Test status
Simulation time 12330448390 ps
CPU time 32.87 seconds
Started Jun 09 12:32:34 PM PDT 24
Finished Jun 09 12:33:07 PM PDT 24
Peak memory 213220 kb
Host smart-60380362-6cbc-445b-8428-b4f5d61c8363
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581634227 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.1581634227
Directory /workspace/38.rv_dm_stress_all/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.2186896389
Short name T164
Test name
Test status
Simulation time 36980119 ps
CPU time 0.76 seconds
Started Jun 09 12:32:41 PM PDT 24
Finished Jun 09 12:32:42 PM PDT 24
Peak memory 204784 kb
Host smart-c283f7ba-5e15-4396-8cca-2815ab99641a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186896389 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.2186896389
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_stress_all.2409963829
Short name T137
Test name
Test status
Simulation time 20486851767 ps
CPU time 30.04 seconds
Started Jun 09 12:32:34 PM PDT 24
Finished Jun 09 12:33:05 PM PDT 24
Peak memory 204984 kb
Host smart-7986258a-e10a-45c6-af40-daf09a58a1ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409963829 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.2409963829
Directory /workspace/39.rv_dm_stress_all/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.950169133
Short name T32
Test name
Test status
Simulation time 52218646 ps
CPU time 0.75 seconds
Started Jun 09 12:32:07 PM PDT 24
Finished Jun 09 12:32:08 PM PDT 24
Peak memory 204784 kb
Host smart-c3a33dfb-a9e6-4105-8bea-bb469bbc771d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950169133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.950169133
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.1183505355
Short name T204
Test name
Test status
Simulation time 12536983213 ps
CPU time 8.13 seconds
Started Jun 09 12:32:09 PM PDT 24
Finished Jun 09 12:32:18 PM PDT 24
Peak memory 205056 kb
Host smart-c2e2ffc8-9b4e-4757-9c57-732f13e0d08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183505355 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.1183505355
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.2089689097
Short name T235
Test name
Test status
Simulation time 5782182880 ps
CPU time 15.98 seconds
Started Jun 09 12:32:17 PM PDT 24
Finished Jun 09 12:32:34 PM PDT 24
Peak memory 213316 kb
Host smart-f0d5d359-9f37-49a6-a6ae-06598e3e0b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089689097 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.2089689097
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.1789021481
Short name T234
Test name
Test status
Simulation time 2718377548 ps
CPU time 5.44 seconds
Started Jun 09 12:32:05 PM PDT 24
Finished Jun 09 12:32:11 PM PDT 24
Peak memory 205132 kb
Host smart-c8fc4538-f56f-4a5b-8952-0fd744796617
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1789021481 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.1789021481
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.2564884868
Short name T178
Test name
Test status
Simulation time 235512175 ps
CPU time 1.11 seconds
Started Jun 09 12:32:08 PM PDT 24
Finished Jun 09 12:32:09 PM PDT 24
Peak memory 204568 kb
Host smart-379ee98f-6777-4076-bcb4-4c2782734b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564884868 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.2564884868
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.3352676625
Short name T172
Test name
Test status
Simulation time 7994128948 ps
CPU time 11.21 seconds
Started Jun 09 12:32:06 PM PDT 24
Finished Jun 09 12:32:17 PM PDT 24
Peak memory 205128 kb
Host smart-1ce90476-1cd5-47d1-94be-01906d911dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352676625 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.3352676625
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.1838878310
Short name T49
Test name
Test status
Simulation time 1616854828 ps
CPU time 3.63 seconds
Started Jun 09 12:32:11 PM PDT 24
Finished Jun 09 12:32:14 PM PDT 24
Peak memory 229600 kb
Host smart-6385220b-31bf-42ca-b574-943009b71530
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838878310 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.1838878310
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.2259772656
Short name T238
Test name
Test status
Simulation time 56064343 ps
CPU time 0.7 seconds
Started Jun 09 12:32:33 PM PDT 24
Finished Jun 09 12:32:34 PM PDT 24
Peak memory 204672 kb
Host smart-6a241c41-fb82-4a25-8fa8-e6b6638ed918
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259772656 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.2259772656
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.3852412664
Short name T167
Test name
Test status
Simulation time 43253901 ps
CPU time 0.73 seconds
Started Jun 09 12:32:38 PM PDT 24
Finished Jun 09 12:32:39 PM PDT 24
Peak memory 204764 kb
Host smart-a5a13216-89a1-4109-b5da-25037c14023a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852412664 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.3852412664
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.3724408715
Short name T148
Test name
Test status
Simulation time 40741150 ps
CPU time 0.75 seconds
Started Jun 09 12:32:33 PM PDT 24
Finished Jun 09 12:32:34 PM PDT 24
Peak memory 204732 kb
Host smart-c6a55440-d287-42e5-abe7-960753375f42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724408715 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.3724408715
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.673831752
Short name T149
Test name
Test status
Simulation time 65071868 ps
CPU time 0.76 seconds
Started Jun 09 12:32:41 PM PDT 24
Finished Jun 09 12:32:42 PM PDT 24
Peak memory 204736 kb
Host smart-4b9ebef3-ba5c-4b56-a522-18aaad0e4dd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673831752 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.673831752
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.1248942816
Short name T74
Test name
Test status
Simulation time 55316715 ps
CPU time 0.72 seconds
Started Jun 09 12:32:37 PM PDT 24
Finished Jun 09 12:32:38 PM PDT 24
Peak memory 204736 kb
Host smart-8c21ef9a-266d-4514-acf1-326403e77919
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248942816 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.1248942816
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.2033165896
Short name T180
Test name
Test status
Simulation time 40846568 ps
CPU time 0.76 seconds
Started Jun 09 12:32:35 PM PDT 24
Finished Jun 09 12:32:36 PM PDT 24
Peak memory 204756 kb
Host smart-01776ed4-0f93-4e5e-b339-aabcda3a52f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033165896 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.2033165896
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.1516608377
Short name T70
Test name
Test status
Simulation time 79636740 ps
CPU time 0.93 seconds
Started Jun 09 12:32:37 PM PDT 24
Finished Jun 09 12:32:39 PM PDT 24
Peak memory 204784 kb
Host smart-4a952aaf-2b50-401d-a983-b662bc73ef7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516608377 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.1516608377
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_stress_all.530156412
Short name T23
Test name
Test status
Simulation time 9787018183 ps
CPU time 5.07 seconds
Started Jun 09 12:32:34 PM PDT 24
Finished Jun 09 12:32:39 PM PDT 24
Peak memory 204956 kb
Host smart-fcc198d5-441a-466a-b11a-131498a32243
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530156412 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.530156412
Directory /workspace/46.rv_dm_stress_all/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.1435350528
Short name T155
Test name
Test status
Simulation time 186677330 ps
CPU time 1.16 seconds
Started Jun 09 12:32:43 PM PDT 24
Finished Jun 09 12:32:45 PM PDT 24
Peak memory 204760 kb
Host smart-bdd1949c-8e3d-4a8b-9c48-0c1b84b3a932
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435350528 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.1435350528
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.971765305
Short name T259
Test name
Test status
Simulation time 76234293 ps
CPU time 0.87 seconds
Started Jun 09 12:32:40 PM PDT 24
Finished Jun 09 12:32:41 PM PDT 24
Peak memory 204716 kb
Host smart-e79378c7-c77e-452b-8fa8-4a12df021966
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971765305 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.971765305
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.3493802610
Short name T120
Test name
Test status
Simulation time 94089415 ps
CPU time 0.71 seconds
Started Jun 09 12:32:59 PM PDT 24
Finished Jun 09 12:33:00 PM PDT 24
Peak memory 204788 kb
Host smart-7ee01067-5847-4cdd-81b2-509da858596a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493802610 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.3493802610
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_stress_all.227913721
Short name T177
Test name
Test status
Simulation time 4401450332 ps
CPU time 5.28 seconds
Started Jun 09 12:32:42 PM PDT 24
Finished Jun 09 12:32:48 PM PDT 24
Peak memory 204948 kb
Host smart-17880b7f-0b9f-4b26-a45a-c752f5eb312a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227913721 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.227913721
Directory /workspace/49.rv_dm_stress_all/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.62367062
Short name T169
Test name
Test status
Simulation time 38596037 ps
CPU time 0.77 seconds
Started Jun 09 12:32:17 PM PDT 24
Finished Jun 09 12:32:18 PM PDT 24
Peak memory 204700 kb
Host smart-272d9f75-9a8d-4e1b-a318-955e0d939121
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62367062 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.62367062
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.1682807290
Short name T248
Test name
Test status
Simulation time 53577166288 ps
CPU time 85.29 seconds
Started Jun 09 12:32:09 PM PDT 24
Finished Jun 09 12:33:35 PM PDT 24
Peak memory 213328 kb
Host smart-b73a7ee2-4769-4f89-9314-d5caed4bc9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682807290 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.1682807290
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.3338779292
Short name T65
Test name
Test status
Simulation time 1329343517 ps
CPU time 4.51 seconds
Started Jun 09 12:32:09 PM PDT 24
Finished Jun 09 12:32:14 PM PDT 24
Peak memory 205020 kb
Host smart-02b78efa-0b47-4b68-ab6b-12415c06f2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338779292 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.3338779292
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.3985341790
Short name T171
Test name
Test status
Simulation time 4788909199 ps
CPU time 4.3 seconds
Started Jun 09 12:32:09 PM PDT 24
Finished Jun 09 12:32:13 PM PDT 24
Peak memory 205232 kb
Host smart-02951a46-e232-4a11-9d8b-7f8618aa0505
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3985341790 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t
l_access.3985341790
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.3801771605
Short name T12
Test name
Test status
Simulation time 6065129839 ps
CPU time 11.7 seconds
Started Jun 09 12:32:17 PM PDT 24
Finished Jun 09 12:32:29 PM PDT 24
Peak memory 205024 kb
Host smart-1e50c1d9-22a5-4b7f-b6fc-c17276c30a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801771605 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.3801771605
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.2525241834
Short name T253
Test name
Test status
Simulation time 97206324 ps
CPU time 0.89 seconds
Started Jun 09 12:32:07 PM PDT 24
Finished Jun 09 12:32:08 PM PDT 24
Peak memory 204804 kb
Host smart-0cc50311-69fe-4ff1-a184-fc031898f254
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525241834 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.2525241834
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.3809491027
Short name T189
Test name
Test status
Simulation time 5364513939 ps
CPU time 9.43 seconds
Started Jun 09 12:32:10 PM PDT 24
Finished Jun 09 12:32:20 PM PDT 24
Peak memory 213296 kb
Host smart-c9bfb432-b7b6-4673-897c-db82c141d7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809491027 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.3809491027
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.394499551
Short name T183
Test name
Test status
Simulation time 7347456358 ps
CPU time 19.45 seconds
Started Jun 09 12:32:17 PM PDT 24
Finished Jun 09 12:32:37 PM PDT 24
Peak memory 213404 kb
Host smart-35578300-4511-49b8-af71-78a7fb9891de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394499551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.394499551
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.2922853352
Short name T3
Test name
Test status
Simulation time 2187784743 ps
CPU time 4.23 seconds
Started Jun 09 12:32:12 PM PDT 24
Finished Jun 09 12:32:17 PM PDT 24
Peak memory 205144 kb
Host smart-143083f0-2e89-4ca1-bfc8-0216711226f1
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2922853352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t
l_access.2922853352
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.2574680230
Short name T243
Test name
Test status
Simulation time 1997371541 ps
CPU time 3.77 seconds
Started Jun 09 12:32:12 PM PDT 24
Finished Jun 09 12:32:16 PM PDT 24
Peak memory 205064 kb
Host smart-3a798114-82c9-4f39-ba88-dbc68e710aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574680230 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.2574680230
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.798416145
Short name T119
Test name
Test status
Simulation time 162580745 ps
CPU time 0.77 seconds
Started Jun 09 12:32:20 PM PDT 24
Finished Jun 09 12:32:22 PM PDT 24
Peak memory 204776 kb
Host smart-e8232490-f313-4b27-9615-595bb4e1619b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798416145 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.798416145
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.1979893376
Short name T201
Test name
Test status
Simulation time 58391985640 ps
CPU time 67.1 seconds
Started Jun 09 12:32:09 PM PDT 24
Finished Jun 09 12:33:17 PM PDT 24
Peak memory 213092 kb
Host smart-ccc30bb4-ddf4-46f9-96fb-45807d519ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979893376 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.1979893376
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.2730922938
Short name T194
Test name
Test status
Simulation time 2985510862 ps
CPU time 5.06 seconds
Started Jun 09 12:32:09 PM PDT 24
Finished Jun 09 12:32:14 PM PDT 24
Peak memory 205184 kb
Host smart-65f81252-3437-4ee1-8f60-848fba037cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730922938 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.2730922938
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.1180784174
Short name T224
Test name
Test status
Simulation time 3064831607 ps
CPU time 3.37 seconds
Started Jun 09 12:32:06 PM PDT 24
Finished Jun 09 12:32:10 PM PDT 24
Peak memory 205224 kb
Host smart-bab45c24-334e-4b29-973d-737e631a424d
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1180784174 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.1180784174
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.1908367853
Short name T91
Test name
Test status
Simulation time 1303255079 ps
CPU time 2.68 seconds
Started Jun 09 12:32:13 PM PDT 24
Finished Jun 09 12:32:16 PM PDT 24
Peak memory 205004 kb
Host smart-4ce45aba-5ab6-42cb-815d-837d7293a444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908367853 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.1908367853
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_stress_all.1875625267
Short name T37
Test name
Test status
Simulation time 6443358277 ps
CPU time 17.62 seconds
Started Jun 09 12:32:14 PM PDT 24
Finished Jun 09 12:32:33 PM PDT 24
Peak memory 213264 kb
Host smart-c528929f-e019-418f-8a80-a2d0d7981843
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875625267 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.1875625267
Directory /workspace/7.rv_dm_stress_all/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.518730118
Short name T118
Test name
Test status
Simulation time 34011139 ps
CPU time 0.75 seconds
Started Jun 09 12:32:13 PM PDT 24
Finished Jun 09 12:32:14 PM PDT 24
Peak memory 204944 kb
Host smart-b1ea009a-1708-4945-b9cc-4930e80709c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518730118 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.518730118
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.2875405939
Short name T27
Test name
Test status
Simulation time 7983555100 ps
CPU time 23.27 seconds
Started Jun 09 12:32:18 PM PDT 24
Finished Jun 09 12:32:41 PM PDT 24
Peak memory 205088 kb
Host smart-2bfa3701-4429-466e-95e5-a205be8e39f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875405939 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.2875405939
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.1375532607
Short name T221
Test name
Test status
Simulation time 3472453617 ps
CPU time 2.73 seconds
Started Jun 09 12:32:17 PM PDT 24
Finished Jun 09 12:32:20 PM PDT 24
Peak memory 205172 kb
Host smart-ef51e52e-9d25-4cab-9267-378190ff6f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375532607 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.1375532607
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.3837806096
Short name T174
Test name
Test status
Simulation time 3479227150 ps
CPU time 3.81 seconds
Started Jun 09 12:32:21 PM PDT 24
Finished Jun 09 12:32:26 PM PDT 24
Peak memory 205208 kb
Host smart-526d33a2-5a8b-4aff-8e17-7a5b9e0b8961
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3837806096 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t
l_access.3837806096
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.2583080071
Short name T251
Test name
Test status
Simulation time 8201158594 ps
CPU time 20.87 seconds
Started Jun 09 12:32:22 PM PDT 24
Finished Jun 09 12:32:44 PM PDT 24
Peak memory 205124 kb
Host smart-2b651457-43b3-4874-ad0d-f5b2e0397674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583080071 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.2583080071
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.3410423558
Short name T240
Test name
Test status
Simulation time 105789484 ps
CPU time 0.87 seconds
Started Jun 09 12:32:20 PM PDT 24
Finished Jun 09 12:32:22 PM PDT 24
Peak memory 204752 kb
Host smart-546e6782-2f80-4578-bcb5-1273ba49d029
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410423558 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.3410423558
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.4011405589
Short name T209
Test name
Test status
Simulation time 25917655367 ps
CPU time 22.76 seconds
Started Jun 09 12:32:27 PM PDT 24
Finished Jun 09 12:32:50 PM PDT 24
Peak memory 213344 kb
Host smart-84b8d5bf-fb39-48a0-900e-e4d91b46cba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011405589 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.4011405589
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.284956855
Short name T214
Test name
Test status
Simulation time 1714896718 ps
CPU time 3.36 seconds
Started Jun 09 12:32:17 PM PDT 24
Finished Jun 09 12:32:21 PM PDT 24
Peak memory 205036 kb
Host smart-e2495ea7-d3c3-40b6-b289-8d1a092f6e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284956855 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.284956855
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.758754535
Short name T192
Test name
Test status
Simulation time 10075012400 ps
CPU time 8.63 seconds
Started Jun 09 12:32:15 PM PDT 24
Finished Jun 09 12:32:24 PM PDT 24
Peak memory 205140 kb
Host smart-85bf07bf-71f4-45c3-86a1-367c5b477b49
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=758754535 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_tl
_access.758754535
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.2846274673
Short name T175
Test name
Test status
Simulation time 2506740029 ps
CPU time 7.62 seconds
Started Jun 09 12:32:19 PM PDT 24
Finished Jun 09 12:32:27 PM PDT 24
Peak memory 205136 kb
Host smart-321b2d88-098a-4478-a977-72c9e4d31643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846274673 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.2846274673
Directory /workspace/9.rv_dm_sba_tl_access/latest
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